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Merge branch 'for-2.6.30' into for-2.6.31
[firewire-audio.git] / sound / soc / pxa / pxa-ssp.c
blob487079550e710a5cd7e69d854e7f749f879d1e46
1 /*
2 * pxa-ssp.c -- ALSA Soc Audio Layer
3 *
4 * Copyright 2005,2008 Wolfson Microelectronics PLC.
5 * Author: Liam Girdwood
6 * Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * TODO:
14 * o Test network mode for > 16bit sample size
15 */
16
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/clk.h>
21 #include <linux/io.h>
22
23 #include <asm/irq.h>
24
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/initval.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/pxa2xx-lib.h>
31
32 #include <mach/hardware.h>
33 #include <mach/dma.h>
34 #include <mach/regs-ssp.h>
35 #include <mach/audio.h>
36 #include <mach/ssp.h>
37
38 #include "pxa2xx-pcm.h"
39 #include "pxa-ssp.h"
40
41 /*
42 * SSP audio private data
43 */
44 struct ssp_priv {
45 struct ssp_dev dev;
46 unsigned int sysclk;
47 int dai_fmt;
48 #ifdef CONFIG_PM
49 struct ssp_state state;
50 #endif
51 };
52
53 #define PXA2xx_SSP1_BASE 0x41000000
54 #define PXA27x_SSP2_BASE 0x41700000
55 #define PXA27x_SSP3_BASE 0x41900000
56 #define PXA3xx_SSP4_BASE 0x41a00000
57
58 static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_mono_out = {
59 .name = "SSP1 PCM Mono out",
60 .dev_addr = PXA2xx_SSP1_BASE + SSDR,
61 .drcmr = &DRCMR(14),
62 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
63 DCMD_BURST16 | DCMD_WIDTH2,
64 };
65
66 static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_mono_in = {
67 .name = "SSP1 PCM Mono in",
68 .dev_addr = PXA2xx_SSP1_BASE + SSDR,
69 .drcmr = &DRCMR(13),
70 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
71 DCMD_BURST16 | DCMD_WIDTH2,
72 };
73
74 static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_stereo_out = {
75 .name = "SSP1 PCM Stereo out",
76 .dev_addr = PXA2xx_SSP1_BASE + SSDR,
77 .drcmr = &DRCMR(14),
78 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
79 DCMD_BURST16 | DCMD_WIDTH4,
80 };
81
82 static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_stereo_in = {
83 .name = "SSP1 PCM Stereo in",
84 .dev_addr = PXA2xx_SSP1_BASE + SSDR,
85 .drcmr = &DRCMR(13),
86 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
87 DCMD_BURST16 | DCMD_WIDTH4,
88 };
89
90 static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_mono_out = {
91 .name = "SSP2 PCM Mono out",
92 .dev_addr = PXA27x_SSP2_BASE + SSDR,
93 .drcmr = &DRCMR(16),
94 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
95 DCMD_BURST16 | DCMD_WIDTH2,
96 };
97
98 static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_mono_in = {
99 .name = "SSP2 PCM Mono in",
100 .dev_addr = PXA27x_SSP2_BASE + SSDR,
101 .drcmr = &DRCMR(15),
102 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
103 DCMD_BURST16 | DCMD_WIDTH2,
104 };
105
106 static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_stereo_out = {
107 .name = "SSP2 PCM Stereo out",
108 .dev_addr = PXA27x_SSP2_BASE + SSDR,
109 .drcmr = &DRCMR(16),
110 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
111 DCMD_BURST16 | DCMD_WIDTH4,
112 };
113
114 static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_stereo_in = {
115 .name = "SSP2 PCM Stereo in",
116 .dev_addr = PXA27x_SSP2_BASE + SSDR,
117 .drcmr = &DRCMR(15),
118 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
119 DCMD_BURST16 | DCMD_WIDTH4,
120 };
121
122 static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_mono_out = {
123 .name = "SSP3 PCM Mono out",
124 .dev_addr = PXA27x_SSP3_BASE + SSDR,
125 .drcmr = &DRCMR(67),
126 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
127 DCMD_BURST16 | DCMD_WIDTH2,
128 };
129
130 static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_mono_in = {
131 .name = "SSP3 PCM Mono in",
132 .dev_addr = PXA27x_SSP3_BASE + SSDR,
133 .drcmr = &DRCMR(66),
134 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
135 DCMD_BURST16 | DCMD_WIDTH2,
136 };
137
138 static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_stereo_out = {
139 .name = "SSP3 PCM Stereo out",
140 .dev_addr = PXA27x_SSP3_BASE + SSDR,
141 .drcmr = &DRCMR(67),
142 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
143 DCMD_BURST16 | DCMD_WIDTH4,
144 };
145
146 static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_stereo_in = {
147 .name = "SSP3 PCM Stereo in",
148 .dev_addr = PXA27x_SSP3_BASE + SSDR,
149 .drcmr = &DRCMR(66),
150 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
151 DCMD_BURST16 | DCMD_WIDTH4,
152 };
153
154 static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_mono_out = {
155 .name = "SSP4 PCM Mono out",
156 .dev_addr = PXA3xx_SSP4_BASE + SSDR,
157 .drcmr = &DRCMR(67),
158 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
159 DCMD_BURST16 | DCMD_WIDTH2,
160 };
161
162 static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_mono_in = {
163 .name = "SSP4 PCM Mono in",
164 .dev_addr = PXA3xx_SSP4_BASE + SSDR,
165 .drcmr = &DRCMR(66),
166 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
167 DCMD_BURST16 | DCMD_WIDTH2,
168 };
169
170 static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_stereo_out = {
171 .name = "SSP4 PCM Stereo out",
172 .dev_addr = PXA3xx_SSP4_BASE + SSDR,
173 .drcmr = &DRCMR(67),
174 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
175 DCMD_BURST16 | DCMD_WIDTH4,
176 };
177
178 static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_stereo_in = {
179 .name = "SSP4 PCM Stereo in",
180 .dev_addr = PXA3xx_SSP4_BASE + SSDR,
181 .drcmr = &DRCMR(66),
182 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
183 DCMD_BURST16 | DCMD_WIDTH4,
184 };
185
186 static void dump_registers(struct ssp_device *ssp)
187 {
188 dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
189 ssp_read_reg(ssp, SSCR0), ssp_read_reg(ssp, SSCR1),
190 ssp_read_reg(ssp, SSTO));
191
192 dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
193 ssp_read_reg(ssp, SSPSP), ssp_read_reg(ssp, SSSR),
194 ssp_read_reg(ssp, SSACD));
195 }
196
197 static struct pxa2xx_pcm_dma_params *ssp_dma_params[4][4] = {
198 {
199 &pxa_ssp1_pcm_mono_out, &pxa_ssp1_pcm_mono_in,
200 &pxa_ssp1_pcm_stereo_out, &pxa_ssp1_pcm_stereo_in,
201 },
202 {
203 &pxa_ssp2_pcm_mono_out, &pxa_ssp2_pcm_mono_in,
204 &pxa_ssp2_pcm_stereo_out, &pxa_ssp2_pcm_stereo_in,
205 },
206 {
207 &pxa_ssp3_pcm_mono_out, &pxa_ssp3_pcm_mono_in,
208 &pxa_ssp3_pcm_stereo_out, &pxa_ssp3_pcm_stereo_in,
209 },
210 {
211 &pxa_ssp4_pcm_mono_out, &pxa_ssp4_pcm_mono_in,
212 &pxa_ssp4_pcm_stereo_out, &pxa_ssp4_pcm_stereo_in,
213 },
214 };
215
216 static int pxa_ssp_startup(struct snd_pcm_substream *substream,
217 struct snd_soc_dai *dai)
218 {
219 struct snd_soc_pcm_runtime *rtd = substream->private_data;
220 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
221 struct ssp_priv *priv = cpu_dai->private_data;
222 int ret = 0;
223
224 if (!cpu_dai->active) {
225 priv->dev.port = cpu_dai->id + 1;
226 priv->dev.irq = NO_IRQ;
227 clk_enable(priv->dev.ssp->clk);
228 ssp_disable(&priv->dev);
229 }
230 return ret;
231 }
232
233 static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
234 struct snd_soc_dai *dai)
235 {
236 struct snd_soc_pcm_runtime *rtd = substream->private_data;
237 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
238 struct ssp_priv *priv = cpu_dai->private_data;
239
240 if (!cpu_dai->active) {
241 ssp_disable(&priv->dev);
242 clk_disable(priv->dev.ssp->clk);
243 }
244 }
245
246 #ifdef CONFIG_PM
247
248 static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai)
249 {
250 struct ssp_priv *priv = cpu_dai->private_data;
251
252 if (!cpu_dai->active)
253 return 0;
254
255 ssp_save_state(&priv->dev, &priv->state);
256 clk_disable(priv->dev.ssp->clk);
257 return 0;
258 }
259
260 static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai)
261 {
262 struct ssp_priv *priv = cpu_dai->private_data;
263
264 if (!cpu_dai->active)
265 return 0;
266
267 clk_enable(priv->dev.ssp->clk);
268 ssp_restore_state(&priv->dev, &priv->state);
269 ssp_enable(&priv->dev);
270
271 return 0;
272 }
273
274 #else
275 #define pxa_ssp_suspend NULL
276 #define pxa_ssp_resume NULL
277 #endif
278
279 /**
280 * ssp_set_clkdiv - set SSP clock divider
281 * @div: serial clock rate divider
282 */
283 static void ssp_set_scr(struct ssp_dev *dev, u32 div)
284 {
285 struct ssp_device *ssp = dev->ssp;
286 u32 sscr0 = ssp_read_reg(dev->ssp, SSCR0) & ~SSCR0_SCR;
287
288 ssp_write_reg(ssp, SSCR0, (sscr0 | SSCR0_SerClkDiv(div)));
289 }
290
291 /*
292 * Set the SSP ports SYSCLK.
293 */
294 static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
295 int clk_id, unsigned int freq, int dir)
296 {
297 struct ssp_priv *priv = cpu_dai->private_data;
298 struct ssp_device *ssp = priv->dev.ssp;
299 int val;
300
301 u32 sscr0 = ssp_read_reg(ssp, SSCR0) &
302 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
303
304 dev_dbg(&ssp->pdev->dev,
305 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %d\n",
306 cpu_dai->id, clk_id, freq);
307
308 switch (clk_id) {
309 case PXA_SSP_CLK_NET_PLL:
310 sscr0 |= SSCR0_MOD;
311 break;
312 case PXA_SSP_CLK_PLL:
313 /* Internal PLL is fixed */
314 if (cpu_is_pxa25x())
315 priv->sysclk = 1843200;
316 else
317 priv->sysclk = 13000000;
318 break;
319 case PXA_SSP_CLK_EXT:
320 priv->sysclk = freq;
321 sscr0 |= SSCR0_ECS;
322 break;
323 case PXA_SSP_CLK_NET:
324 priv->sysclk = freq;
325 sscr0 |= SSCR0_NCS | SSCR0_MOD;
326 break;
327 case PXA_SSP_CLK_AUDIO:
328 priv->sysclk = 0;
329 ssp_set_scr(&priv->dev, 1);
330 sscr0 |= SSCR0_ACS;
331 break;
332 default:
333 return -ENODEV;
334 }
335
336 /* The SSP clock must be disabled when changing SSP clock mode
337 * on PXA2xx. On PXA3xx it must be enabled when doing so. */
338 if (!cpu_is_pxa3xx())
339 clk_disable(priv->dev.ssp->clk);
340 val = ssp_read_reg(ssp, SSCR0) | sscr0;
341 ssp_write_reg(ssp, SSCR0, val);
342 if (!cpu_is_pxa3xx())
343 clk_enable(priv->dev.ssp->clk);
344
345 return 0;
346 }
347
348 /*
349 * Set the SSP clock dividers.
350 */
351 static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
352 int div_id, int div)
353 {
354 struct ssp_priv *priv = cpu_dai->private_data;
355 struct ssp_device *ssp = priv->dev.ssp;
356 int val;
357
358 switch (div_id) {
359 case PXA_SSP_AUDIO_DIV_ACDS:
360 val = (ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div);
361 ssp_write_reg(ssp, SSACD, val);
362 break;
363 case PXA_SSP_AUDIO_DIV_SCDB:
364 val = ssp_read_reg(ssp, SSACD);
365 val &= ~SSACD_SCDB;
366 #if defined(CONFIG_PXA3xx)
367 if (cpu_is_pxa3xx())
368 val &= ~SSACD_SCDX8;
369 #endif
370 switch (div) {
371 case PXA_SSP_CLK_SCDB_1:
372 val |= SSACD_SCDB;
373 break;
374 case PXA_SSP_CLK_SCDB_4:
375 break;
376 #if defined(CONFIG_PXA3xx)
377 case PXA_SSP_CLK_SCDB_8:
378 if (cpu_is_pxa3xx())
379 val |= SSACD_SCDX8;
380 else
381 return -EINVAL;
382 break;
383 #endif
384 default:
385 return -EINVAL;
386 }
387 ssp_write_reg(ssp, SSACD, val);
388 break;
389 case PXA_SSP_DIV_SCR:
390 ssp_set_scr(&priv->dev, div);
391 break;
392 default:
393 return -ENODEV;
394 }
395
396 return 0;
397 }
398
399 /*
400 * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
401 */
402 static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai,
403 int pll_id, unsigned int freq_in, unsigned int freq_out)
404 {
405 struct ssp_priv *priv = cpu_dai->private_data;
406 struct ssp_device *ssp = priv->dev.ssp;
407 u32 ssacd = ssp_read_reg(ssp, SSACD) & ~0x70;
408
409 #if defined(CONFIG_PXA3xx)
410 if (cpu_is_pxa3xx())
411 ssp_write_reg(ssp, SSACDD, 0);
412 #endif
413
414 switch (freq_out) {
415 case 5622000:
416 break;
417 case 11345000:
418 ssacd |= (0x1 << 4);
419 break;
420 case 12235000:
421 ssacd |= (0x2 << 4);
422 break;
423 case 14857000:
424 ssacd |= (0x3 << 4);
425 break;
426 case 32842000:
427 ssacd |= (0x4 << 4);
428 break;
429 case 48000000:
430 ssacd |= (0x5 << 4);
431 break;
432 case 0:
433 /* Disable */
434 break;
435
436 default:
437 #ifdef CONFIG_PXA3xx
438 /* PXA3xx has a clock ditherer which can be used to generate
439 * a wider range of frequencies - calculate a value for it.
440 */
441 if (cpu_is_pxa3xx()) {
442 u32 val;
443 u64 tmp = 19968;
444 tmp *= 1000000;
445 do_div(tmp, freq_out);
446 val = tmp;
447
448 val = (val << 16) | 64;;
449 ssp_write_reg(ssp, SSACDD, val);
450
451 ssacd |= (0x6 << 4);
452
453 dev_dbg(&ssp->pdev->dev,
454 "Using SSACDD %x to supply %dHz\n",
455 val, freq_out);
456 break;
457 }
458 #endif
459
460 return -EINVAL;
461 }
462
463 ssp_write_reg(ssp, SSACD, ssacd);
464
465 return 0;
466 }
467
468 /*
469 * Set the active slots in TDM/Network mode
470 */
471 static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
472 unsigned int mask, int slots)
473 {
474 struct ssp_priv *priv = cpu_dai->private_data;
475 struct ssp_device *ssp = priv->dev.ssp;
476 u32 sscr0;
477
478 sscr0 = ssp_read_reg(ssp, SSCR0) & ~SSCR0_SlotsPerFrm(7);
479
480 /* set number of active slots */
481 sscr0 |= SSCR0_SlotsPerFrm(slots);
482 ssp_write_reg(ssp, SSCR0, sscr0);
483
484 /* set active slot mask */
485 ssp_write_reg(ssp, SSTSA, mask);
486 ssp_write_reg(ssp, SSRSA, mask);
487 return 0;
488 }
489
490 /*
491 * Tristate the SSP DAI lines
492 */
493 static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
494 int tristate)
495 {
496 struct ssp_priv *priv = cpu_dai->private_data;
497 struct ssp_device *ssp = priv->dev.ssp;
498 u32 sscr1;
499
500 sscr1 = ssp_read_reg(ssp, SSCR1);
501 if (tristate)
502 sscr1 &= ~SSCR1_TTE;
503 else
504 sscr1 |= SSCR1_TTE;
505 ssp_write_reg(ssp, SSCR1, sscr1);
506
507 return 0;
508 }
509
510 /*
511 * Set up the SSP DAI format.
512 * The SSP Port must be inactive before calling this function as the
513 * physical interface format is changed.
514 */
515 static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
516 unsigned int fmt)
517 {
518 struct ssp_priv *priv = cpu_dai->private_data;
519 struct ssp_device *ssp = priv->dev.ssp;
520 u32 sscr0;
521 u32 sscr1;
522 u32 sspsp;
523
524 /* check if we need to change anything at all */
525 if (priv->dai_fmt == fmt)
526 return 0;
527
528 /* we can only change the settings if the port is not in use */
529 if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) {
530 dev_err(&ssp->pdev->dev,
531 "can't change hardware dai format: stream is in use");
532 return -EINVAL;
533 }
534
535 /* reset port settings */
536 sscr0 = ssp_read_reg(ssp, SSCR0) &
537 (SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
538 sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
539 sspsp = 0;
540
541 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
542 case SND_SOC_DAIFMT_CBM_CFM:
543 sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR;
544 break;
545 case SND_SOC_DAIFMT_CBM_CFS:
546 sscr1 |= SSCR1_SCLKDIR;
547 break;
548 case SND_SOC_DAIFMT_CBS_CFS:
549 break;
550 default:
551 return -EINVAL;
552 }
553
554 ssp_write_reg(ssp, SSCR0, sscr0);
555 ssp_write_reg(ssp, SSCR1, sscr1);
556 ssp_write_reg(ssp, SSPSP, sspsp);
557
558 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
559 case SND_SOC_DAIFMT_I2S:
560 sscr0 |= SSCR0_PSP;
561 sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
562
563 /* See hw_params() */
564 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
565 case SND_SOC_DAIFMT_NB_NF:
566 sspsp |= SSPSP_SFRMP;
567 break;
568 case SND_SOC_DAIFMT_NB_IF:
569 break;
570 case SND_SOC_DAIFMT_IB_IF:
571 sspsp |= SSPSP_SCMODE(2);
572 break;
573 case SND_SOC_DAIFMT_IB_NF:
574 sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
575 break;
576 default:
577 return -EINVAL;
578 }
579 break;
580
581 case SND_SOC_DAIFMT_DSP_A:
582 sspsp |= SSPSP_FSRT;
583 case SND_SOC_DAIFMT_DSP_B:
584 sscr0 |= SSCR0_MOD | SSCR0_PSP;
585 sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
586
587 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
588 case SND_SOC_DAIFMT_NB_NF:
589 sspsp |= SSPSP_SFRMP;
590 break;
591 case SND_SOC_DAIFMT_NB_IF:
592 break;
593 case SND_SOC_DAIFMT_IB_IF:
594 sspsp |= SSPSP_SCMODE(2);
595 break;
596 case SND_SOC_DAIFMT_IB_NF:
597 sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
598 break;
599 default:
600 return -EINVAL;
601 }
602 break;
603
604 default:
605 return -EINVAL;
606 }
607
608 ssp_write_reg(ssp, SSCR0, sscr0);
609 ssp_write_reg(ssp, SSCR1, sscr1);
610 ssp_write_reg(ssp, SSPSP, sspsp);
611
612 dump_registers(ssp);
613
614 /* Since we are configuring the timings for the format by hand
615 * we have to defer some things until hw_params() where we
616 * know parameters like the sample size.
617 */
618 priv->dai_fmt = fmt;
619
620 return 0;
621 }
622
623 /*
624 * Set the SSP audio DMA parameters and sample size.
625 * Can be called multiple times by oss emulation.
626 */
627 static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
628 struct snd_pcm_hw_params *params,
629 struct snd_soc_dai *dai)
630 {
631 struct snd_soc_pcm_runtime *rtd = substream->private_data;
632 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
633 struct ssp_priv *priv = cpu_dai->private_data;
634 struct ssp_device *ssp = priv->dev.ssp;
635 int dma = 0, chn = params_channels(params);
636 u32 sscr0;
637 u32 sspsp;
638 int width = snd_pcm_format_physical_width(params_format(params));
639 int ttsa = ssp_read_reg(ssp, SSTSA) & 0xf;
640
641 /* select correct DMA params */
642 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
643 dma = 1; /* capture DMA offset is 1,3 */
644 /* Network mode with one active slot (ttsa == 1) can be used
645 * to force 16-bit frame width on the wire (for S16_LE), even
646 * with two channels. Use 16-bit DMA transfers for this case.
647 */
648 if (((chn == 2) && (ttsa != 1)) || (width == 32))
649 dma += 2; /* 32-bit DMA offset is 2, 16-bit is 0 */
650
651 cpu_dai->dma_data = ssp_dma_params[cpu_dai->id][dma];
652
653 dev_dbg(&ssp->pdev->dev, "pxa_ssp_hw_params: dma %d\n", dma);
654
655 /* we can only change the settings if the port is not in use */
656 if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
657 return 0;
658
659 /* clear selected SSP bits */
660 sscr0 = ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
661 ssp_write_reg(ssp, SSCR0, sscr0);
662
663 /* bit size */
664 sscr0 = ssp_read_reg(ssp, SSCR0);
665 switch (params_format(params)) {
666 case SNDRV_PCM_FORMAT_S16_LE:
667 #ifdef CONFIG_PXA3xx
668 if (cpu_is_pxa3xx())
669 sscr0 |= SSCR0_FPCKE;
670 #endif
671 sscr0 |= SSCR0_DataSize(16);
672 break;
673 case SNDRV_PCM_FORMAT_S24_LE:
674 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
675 break;
676 case SNDRV_PCM_FORMAT_S32_LE:
677 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
678 break;
679 }
680 ssp_write_reg(ssp, SSCR0, sscr0);
681
682 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
683 case SND_SOC_DAIFMT_I2S:
684 sspsp = ssp_read_reg(ssp, SSPSP);
685
686 if (((sscr0 & SSCR0_SCR) == SSCR0_SerClkDiv(4)) &&
687 (width == 16)) {
688 /* This is a special case where the bitclk is 64fs
689 * and we're not dealing with 2*32 bits of audio
690 * samples.
691 *
692 * The SSP values used for that are all found out by
693 * trying and failing a lot; some of the registers
694 * needed for that mode are only available on PXA3xx.
695 */
696
697 #ifdef CONFIG_PXA3xx
698 if (!cpu_is_pxa3xx())
699 return -EINVAL;
700
701 sspsp |= SSPSP_SFRMWDTH(width * 2);
702 sspsp |= SSPSP_SFRMDLY(width * 4);
703 sspsp |= SSPSP_EDMYSTOP(3);
704 sspsp |= SSPSP_DMYSTOP(3);
705 sspsp |= SSPSP_DMYSTRT(1);
706 #else
707 return -EINVAL;
708 #endif
709 } else {
710 /* The frame width is the width the LRCLK is
711 * asserted for; the delay is expressed in
712 * half cycle units. We need the extra cycle
713 * because the data starts clocking out one BCLK
714 * after LRCLK changes polarity.
715 */
716 sspsp |= SSPSP_SFRMWDTH(width + 1);
717 sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
718 sspsp |= SSPSP_DMYSTRT(1);
719 }
720
721 ssp_write_reg(ssp, SSPSP, sspsp);
722 break;
723 default:
724 break;
725 }
726
727 /* When we use a network mode, we always require TDM slots
728 * - complain loudly and fail if they've not been set up yet.
729 */
730 if ((sscr0 & SSCR0_MOD) && !ttsa) {
731 dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n");
732 return -EINVAL;
733 }
734
735 dump_registers(ssp);
736
737 return 0;
738 }
739
740 static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
741 struct snd_soc_dai *dai)
742 {
743 struct snd_soc_pcm_runtime *rtd = substream->private_data;
744 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
745 int ret = 0;
746 struct ssp_priv *priv = cpu_dai->private_data;
747 struct ssp_device *ssp = priv->dev.ssp;
748 int val;
749
750 switch (cmd) {
751 case SNDRV_PCM_TRIGGER_RESUME:
752 ssp_enable(&priv->dev);
753 break;
754 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
755 val = ssp_read_reg(ssp, SSCR1);
756 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
757 val |= SSCR1_TSRE;
758 else
759 val |= SSCR1_RSRE;
760 ssp_write_reg(ssp, SSCR1, val);
761 val = ssp_read_reg(ssp, SSSR);
762 ssp_write_reg(ssp, SSSR, val);
763 break;
764 case SNDRV_PCM_TRIGGER_START:
765 val = ssp_read_reg(ssp, SSCR1);
766 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
767 val |= SSCR1_TSRE;
768 else
769 val |= SSCR1_RSRE;
770 ssp_write_reg(ssp, SSCR1, val);
771 ssp_enable(&priv->dev);
772 break;
773 case SNDRV_PCM_TRIGGER_STOP:
774 val = ssp_read_reg(ssp, SSCR1);
775 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
776 val &= ~SSCR1_TSRE;
777 else
778 val &= ~SSCR1_RSRE;
779 ssp_write_reg(ssp, SSCR1, val);
780 break;
781 case SNDRV_PCM_TRIGGER_SUSPEND:
782 ssp_disable(&priv->dev);
783 break;
784 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
785 val = ssp_read_reg(ssp, SSCR1);
786 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
787 val &= ~SSCR1_TSRE;
788 else
789 val &= ~SSCR1_RSRE;
790 ssp_write_reg(ssp, SSCR1, val);
791 break;
792
793 default:
794 ret = -EINVAL;
795 }
796
797 dump_registers(ssp);
798
799 return ret;
800 }
801
802 static int pxa_ssp_probe(struct platform_device *pdev,
803 struct snd_soc_dai *dai)
804 {
805 struct ssp_priv *priv;
806 int ret;
807
808 priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
809 if (!priv)
810 return -ENOMEM;
811
812 priv->dev.ssp = ssp_request(dai->id + 1, "SoC audio");
813 if (priv->dev.ssp == NULL) {
814 ret = -ENODEV;
815 goto err_priv;
816 }
817
818 priv->dai_fmt = (unsigned int) -1;
819 dai->private_data = priv;
820
821 return 0;
822
823 err_priv:
824 kfree(priv);
825 return ret;
826 }
827
828 static void pxa_ssp_remove(struct platform_device *pdev,
829 struct snd_soc_dai *dai)
830 {
831 struct ssp_priv *priv = dai->private_data;
832 ssp_free(priv->dev.ssp);
833 }
834
835 #define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
836 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
837 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
838 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
839
840 #define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
841 SNDRV_PCM_FMTBIT_S24_LE | \
842 SNDRV_PCM_FMTBIT_S32_LE)
843
844 static struct snd_soc_dai_ops pxa_ssp_dai_ops = {
845 .startup = pxa_ssp_startup,
846 .shutdown = pxa_ssp_shutdown,
847 .trigger = pxa_ssp_trigger,
848 .hw_params = pxa_ssp_hw_params,
849 .set_sysclk = pxa_ssp_set_dai_sysclk,
850 .set_clkdiv = pxa_ssp_set_dai_clkdiv,
851 .set_pll = pxa_ssp_set_dai_pll,
852 .set_fmt = pxa_ssp_set_dai_fmt,
853 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
854 .set_tristate = pxa_ssp_set_dai_tristate,
855 };
856
857 struct snd_soc_dai pxa_ssp_dai[] = {
858 {
859 .name = "pxa2xx-ssp1",
860 .id = 0,
861 .probe = pxa_ssp_probe,
862 .remove = pxa_ssp_remove,
863 .suspend = pxa_ssp_suspend,
864 .resume = pxa_ssp_resume,
865 .playback = {
866 .channels_min = 1,
867 .channels_max = 2,
868 .rates = PXA_SSP_RATES,
869 .formats = PXA_SSP_FORMATS,
870 },
871 .capture = {
872 .channels_min = 1,
873 .channels_max = 2,
874 .rates = PXA_SSP_RATES,
875 .formats = PXA_SSP_FORMATS,
876 },
877 .ops = &pxa_ssp_dai_ops,
878 },
879 { .name = "pxa2xx-ssp2",
880 .id = 1,
881 .probe = pxa_ssp_probe,
882 .remove = pxa_ssp_remove,
883 .suspend = pxa_ssp_suspend,
884 .resume = pxa_ssp_resume,
885 .playback = {
886 .channels_min = 1,
887 .channels_max = 2,
888 .rates = PXA_SSP_RATES,
889 .formats = PXA_SSP_FORMATS,
890 },
891 .capture = {
892 .channels_min = 1,
893 .channels_max = 2,
894 .rates = PXA_SSP_RATES,
895 .formats = PXA_SSP_FORMATS,
896 },
897 .ops = &pxa_ssp_dai_ops,
898 },
899 {
900 .name = "pxa2xx-ssp3",
901 .id = 2,
902 .probe = pxa_ssp_probe,
903 .remove = pxa_ssp_remove,
904 .suspend = pxa_ssp_suspend,
905 .resume = pxa_ssp_resume,
906 .playback = {
907 .channels_min = 1,
908 .channels_max = 2,
909 .rates = PXA_SSP_RATES,
910 .formats = PXA_SSP_FORMATS,
911 },
912 .capture = {
913 .channels_min = 1,
914 .channels_max = 2,
915 .rates = PXA_SSP_RATES,
916 .formats = PXA_SSP_FORMATS,
917 },
918 .ops = &pxa_ssp_dai_ops,
919 },
920 {
921 .name = "pxa2xx-ssp4",
922 .id = 3,
923 .probe = pxa_ssp_probe,
924 .remove = pxa_ssp_remove,
925 .suspend = pxa_ssp_suspend,
926 .resume = pxa_ssp_resume,
927 .playback = {
928 .channels_min = 1,
929 .channels_max = 2,
930 .rates = PXA_SSP_RATES,
931 .formats = PXA_SSP_FORMATS,
932 },
933 .capture = {
934 .channels_min = 1,
935 .channels_max = 2,
936 .rates = PXA_SSP_RATES,
937 .formats = PXA_SSP_FORMATS,
938 },
939 .ops = &pxa_ssp_dai_ops,
940 },
941 };
942 EXPORT_SYMBOL_GPL(pxa_ssp_dai);
943
944 static int __init pxa_ssp_init(void)
945 {
946 return snd_soc_register_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai));
947 }
948 module_init(pxa_ssp_init);
949
950 static void __exit pxa_ssp_exit(void)
951 {
952 snd_soc_unregister_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai));
953 }
954 module_exit(pxa_ssp_exit);
955
956 /* Module information */
957 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
958 MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
959 MODULE_LICENSE("GPL");
AMDTP streaming driver for the Linux FireWire stack (Juju)