arch/mips/kernel/i8259.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Code to handle x86 style IRQs plus some generic interrupt stuff.
   7  *
   8  * Copyright (C) 1992 Linus Torvalds
   9  * Copyright (C) 1994 - 2000 Ralf Baechle
  10  */
  11 #include <linux/delay.h>
  12 #include <linux/init.h>
  13 #include <linux/ioport.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/kernel.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/sysdev.h>
  18
  19 #include <asm/i8259.h>
  20 #include <asm/io.h>
  21
  22 void enable_8259A_irq(unsigned int irq);
  23 void disable_8259A_irq(unsigned int irq);
  24
  25 /*
  26  * This is the 'legacy' 8259A Programmable Interrupt Controller,
  27  * present in the majority of PC/AT boxes.
  28  * plus some generic x86 specific things if generic specifics makes
  29  * any sense at all.
  30  * this file should become arch/i386/kernel/irq.c when the old irq.c
  31  * moves to arch independent land
  32  */
  33
  34 DEFINE_SPINLOCK(i8259A_lock);
  35
  36 static void end_8259A_irq (unsigned int irq)
  37 {
  38         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) &&
  39             irq_desc[irq].action)
  40                 enable_8259A_irq(irq);
  41 }
  42
  43 void mask_and_ack_8259A(unsigned int);
  44
  45 static struct irq_chip i8259A_irq_type = {
  46         .typename = "XT-PIC",
  47         .enable = enable_8259A_irq,
  48         .disable = disable_8259A_irq,
  49         .ack = mask_and_ack_8259A,
  50         .end = end_8259A_irq,
  51 };
  52
  53 /*
  54  * 8259A PIC functions to handle ISA devices:
  55  */
  56
  57 /*
  58  * This contains the irq mask for both 8259A irq controllers,
  59  */
  60 static unsigned int cached_irq_mask = 0xffff;
  61
  62 #define cached_21       (cached_irq_mask)
  63 #define cached_A1       (cached_irq_mask >> 8)
  64
  65 void disable_8259A_irq(unsigned int irq)
  66 {
  67         unsigned int mask = 1 << irq;
  68         unsigned long flags;
  69
  70         spin_lock_irqsave(&i8259A_lock, flags);
  71         cached_irq_mask |= mask;
  72         if (irq & 8)
  73                 outb(cached_A1,0xA1);
  74         else
  75                 outb(cached_21,0x21);
  76         spin_unlock_irqrestore(&i8259A_lock, flags);
  77 }
  78
  79 void enable_8259A_irq(unsigned int irq)
  80 {
  81         unsigned int mask = ~(1 << irq);
  82         unsigned long flags;
  83
  84         spin_lock_irqsave(&i8259A_lock, flags);
  85         cached_irq_mask &= mask;
  86         if (irq & 8)
  87                 outb(cached_A1,0xA1);
  88         else
  89                 outb(cached_21,0x21);
  90         spin_unlock_irqrestore(&i8259A_lock, flags);
  91 }
  92
  93 int i8259A_irq_pending(unsigned int irq)
  94 {
  95         unsigned int mask = 1 << irq;
  96         unsigned long flags;
  97         int ret;
  98
  99         spin_lock_irqsave(&i8259A_lock, flags);
 100         if (irq < 8)
 101                 ret = inb(0x20) & mask;
 102         else
 103                 ret = inb(0xA0) & (mask >> 8);
 104         spin_unlock_irqrestore(&i8259A_lock, flags);
 105
 106         return ret;
 107 }
 108
 109 void make_8259A_irq(unsigned int irq)
 110 {
 111         disable_irq_nosync(irq);
 112         set_irq_chip(irq, &i8259A_irq_type);
 113         enable_irq(irq);
 114 }
 115
 116 /*
 117  * This function assumes to be called rarely. Switching between
 118  * 8259A registers is slow.
 119  * This has to be protected by the irq controller spinlock
 120  * before being called.
 121  */
 122 static inline int i8259A_irq_real(unsigned int irq)
 123 {
 124         int value;
 125         int irqmask = 1 << irq;
 126
 127         if (irq < 8) {
 128                 outb(0x0B,0x20);                /* ISR register */
 129                 value = inb(0x20) & irqmask;
 130                 outb(0x0A,0x20);                /* back to the IRR register */
 131                 return value;
 132         }
 133         outb(0x0B,0xA0);                /* ISR register */
 134         value = inb(0xA0) & (irqmask >> 8);
 135         outb(0x0A,0xA0);                /* back to the IRR register */
 136         return value;
 137 }
 138
 139 /*
 140  * Careful! The 8259A is a fragile beast, it pretty
 141  * much _has_ to be done exactly like this (mask it
 142  * first, _then_ send the EOI, and the order of EOI
 143  * to the two 8259s is important!
 144  */
 145 void mask_and_ack_8259A(unsigned int irq)
 146 {
 147         unsigned int irqmask = 1 << irq;
 148         unsigned long flags;
 149
 150         spin_lock_irqsave(&i8259A_lock, flags);
 151         /*
 152          * Lightweight spurious IRQ detection. We do not want to overdo
 153          * spurious IRQ handling - it's usually a sign of hardware problems, so
 154          * we only do the checks we can do without slowing down good hardware
 155          * nnecesserily.
 156          *
 157          * Note that IRQ7 and IRQ15 (the two spurious IRQs usually resulting
 158          * rom the 8259A-1|2 PICs) occur even if the IRQ is masked in the 8259A.
 159          * Thus we can check spurious 8259A IRQs without doing the quite slow
 160          * i8259A_irq_real() call for every IRQ.  This does not cover 100% of
 161          * spurious interrupts, but should be enough to warn the user that
 162          * there is something bad going on ...
 163          */
 164         if (cached_irq_mask & irqmask)
 165                 goto spurious_8259A_irq;
 166         cached_irq_mask |= irqmask;
 167
 168 handle_real_irq:
 169         if (irq & 8) {
 170                 inb(0xA1);              /* DUMMY - (do we need this?) */
 171                 outb(cached_A1,0xA1);
 172                 outb(0x60+(irq&7),0xA0);/* 'Specific EOI' to slave */
 173                 outb(0x62,0x20);        /* 'Specific EOI' to master-IRQ2 */
 174         } else {
 175                 inb(0x21);              /* DUMMY - (do we need this?) */
 176                 outb(cached_21,0x21);
 177                 outb(0x60+irq,0x20);    /* 'Specific EOI' to master */
 178         }
 179 #ifdef CONFIG_MIPS_MT_SMTC
 180         if (irq_hwmask[irq] & ST0_IM)
 181                 set_c0_status(irq_hwmask[irq] & ST0_IM);
 182 #endif /* CONFIG_MIPS_MT_SMTC */
 183         spin_unlock_irqrestore(&i8259A_lock, flags);
 184         return;
 185
 186 spurious_8259A_irq:
 187         /*
 188          * this is the slow path - should happen rarely.
 189          */
 190         if (i8259A_irq_real(irq))
 191                 /*
 192                  * oops, the IRQ _is_ in service according to the
 193                  * 8259A - not spurious, go handle it.
 194                  */
 195                 goto handle_real_irq;
 196
 197         {
 198                 static int spurious_irq_mask = 0;
 199                 /*
 200                  * At this point we can be sure the IRQ is spurious,
 201                  * lets ACK and report it. [once per IRQ]
 202                  */
 203                 if (!(spurious_irq_mask & irqmask)) {
 204                         printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
 205                         spurious_irq_mask |= irqmask;
 206                 }
 207                 atomic_inc(&irq_err_count);
 208                 /*
 209                  * Theoretically we do not have to handle this IRQ,
 210                  * but in Linux this does not cause problems and is
 211                  * simpler for us.
 212                  */
 213                 goto handle_real_irq;
 214         }
 215 }
 216
 217 static int i8259A_resume(struct sys_device *dev)
 218 {
 219         init_8259A(0);
 220         return 0;
 221 }
 222
 223 static struct sysdev_class i8259_sysdev_class = {
 224         set_kset_name("i8259"),
 225         .resume = i8259A_resume,
 226 };
 227
 228 static struct sys_device device_i8259A = {
 229         .id     = 0,
 230         .cls    = &i8259_sysdev_class,
 231 };
 232
 233 static int __init i8259A_init_sysfs(void)
 234 {
 235         int error = sysdev_class_register(&i8259_sysdev_class);
 236         if (!error)
 237                 error = sysdev_register(&device_i8259A);
 238         return error;
 239 }
 240
 241 device_initcall(i8259A_init_sysfs);
 242
 243 void __init init_8259A(int auto_eoi)
 244 {
 245         unsigned long flags;
 246
 247         spin_lock_irqsave(&i8259A_lock, flags);
 248
 249         outb(0xff, 0x21);       /* mask all of 8259A-1 */
 250         outb(0xff, 0xA1);       /* mask all of 8259A-2 */
 251
 252         /*
 253          * outb_p - this has to work on a wide range of PC hardware.
 254          */
 255         outb_p(0x11, 0x20);     /* ICW1: select 8259A-1 init */
 256         outb_p(0x00, 0x21);     /* ICW2: 8259A-1 IR0-7 mapped to 0x00-0x07 */
 257         outb_p(0x04, 0x21);     /* 8259A-1 (the master) has a slave on IR2 */
 258         if (auto_eoi)
 259                 outb_p(0x03, 0x21);     /* master does Auto EOI */
 260         else
 261                 outb_p(0x01, 0x21);     /* master expects normal EOI */
 262
 263         outb_p(0x11, 0xA0);     /* ICW1: select 8259A-2 init */
 264         outb_p(0x08, 0xA1);     /* ICW2: 8259A-2 IR0-7 mapped to 0x08-0x0f */
 265         outb_p(0x02, 0xA1);     /* 8259A-2 is a slave on master's IR2 */
 266         outb_p(0x01, 0xA1);     /* (slave's support for AEOI in flat mode
 267                                     is to be investigated) */
 268
 269         if (auto_eoi)
 270                 /*
 271                  * in AEOI mode we just have to mask the interrupt
 272                  * when acking.
 273                  */
 274                 i8259A_irq_type.ack = disable_8259A_irq;
 275         else
 276                 i8259A_irq_type.ack = mask_and_ack_8259A;
 277
 278         udelay(100);            /* wait for 8259A to initialize */
 279
 280         outb(cached_21, 0x21);  /* restore master IRQ mask */
 281         outb(cached_A1, 0xA1);  /* restore slave IRQ mask */
 282
 283         spin_unlock_irqrestore(&i8259A_lock, flags);
 284 }
 285
 286 /*
 287  * IRQ2 is cascade interrupt to second interrupt controller
 288  */
 289 static struct irqaction irq2 = {
 290         no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL
 291 };
 292
 293 static struct resource pic1_io_resource = {
 294         .name = "pic1", .start = 0x20, .end = 0x21, .flags = IORESOURCE_BUSY
 295 };
 296
 297 static struct resource pic2_io_resource = {
 298         .name = "pic2", .start = 0xa0, .end = 0xa1, .flags = IORESOURCE_BUSY
 299 };
 300
 301 /*
 302  * On systems with i8259-style interrupt controllers we assume for
 303  * driver compatibility reasons interrupts 0 - 15 to be the i8259
 304  * interrupts even if the hardware uses a different interrupt numbering.
 305  */
 306 void __init init_i8259_irqs (void)
 307 {
 308         int i;
 309
 310         request_resource(&ioport_resource, &pic1_io_resource);
 311         request_resource(&ioport_resource, &pic2_io_resource);
 312
 313         init_8259A(0);
 314
 315         for (i = 0; i < 16; i++)
 316                 set_irq_chip(i, &i8259A_irq_type);
 317
 318         setup_irq(2, &irq2);
 319 }