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drm: add 32/64 support for MGA/R128/i915
[firewire-audio.git] / drivers / serial / 8250_pci.c
blobde54bdc5398b96b6c44b01c881c91a5a1010a296
1 /*
2 * linux/drivers/char/8250_pci.c
3 *
4 * Probe module for 8250/16550-type PCI serial ports.
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
15 */
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/pci.h>
19 #include <linux/sched.h>
20 #include <linux/string.h>
21 #include <linux/kernel.h>
22 #include <linux/slab.h>
23 #include <linux/delay.h>
24 #include <linux/tty.h>
25 #include <linux/serial_core.h>
26 #include <linux/8250_pci.h>
27 #include <linux/bitops.h>
28
29 #include <asm/byteorder.h>
30 #include <asm/io.h>
31
32 #include "8250.h"
33
34 #undef SERIAL_DEBUG_PCI
35
36 /*
37 * Definitions for PCI support.
38 */
39 #define FL_BASE_MASK 0x0007
40 #define FL_BASE0 0x0000
41 #define FL_BASE1 0x0001
42 #define FL_BASE2 0x0002
43 #define FL_BASE3 0x0003
44 #define FL_BASE4 0x0004
45 #define FL_GET_BASE(x) (x & FL_BASE_MASK)
46
47 /* Use successive BARs (PCI base address registers),
48 else use offset into some specified BAR */
49 #define FL_BASE_BARS 0x0008
50
51 /* do not assign an irq */
52 #define FL_NOIRQ 0x0080
53
54 /* Use the Base address register size to cap number of ports */
55 #define FL_REGION_SZ_CAP 0x0100
56
57 struct pci_board {
58 unsigned int flags;
59 unsigned int num_ports;
60 unsigned int base_baud;
61 unsigned int uart_offset;
62 unsigned int reg_shift;
63 unsigned int first_offset;
64 };
65
66 /*
67 * init function returns:
68 * > 0 - number of ports
69 * = 0 - use board->num_ports
70 * < 0 - error
71 */
72 struct pci_serial_quirk {
73 u32 vendor;
74 u32 device;
75 u32 subvendor;
76 u32 subdevice;
77 int (*init)(struct pci_dev *dev);
78 int (*setup)(struct pci_dev *dev, struct pci_board *board,
79 struct uart_port *port, int idx);
80 void (*exit)(struct pci_dev *dev);
81 };
82
83 #define PCI_NUM_BAR_RESOURCES 6
84
85 struct serial_private {
86 unsigned int nr;
87 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
88 struct pci_serial_quirk *quirk;
89 int line[0];
90 };
91
92 static void moan_device(const char *str, struct pci_dev *dev)
93 {
94 printk(KERN_WARNING "%s: %s\n"
95 KERN_WARNING "Please send the output of lspci -vv, this\n"
96 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
97 KERN_WARNING "manufacturer and name of serial board or\n"
98 KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
99 pci_name(dev), str, dev->vendor, dev->device,
100 dev->subsystem_vendor, dev->subsystem_device);
101 }
102
103 static int
104 setup_port(struct pci_dev *dev, struct uart_port *port,
105 int bar, int offset, int regshift)
106 {
107 struct serial_private *priv = pci_get_drvdata(dev);
108 unsigned long base, len;
109
110 if (bar >= PCI_NUM_BAR_RESOURCES)
111 return -EINVAL;
112
113 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
114 base = pci_resource_start(dev, bar);
115 len = pci_resource_len(dev, bar);
116
117 if (!priv->remapped_bar[bar])
118 priv->remapped_bar[bar] = ioremap(base, len);
119 if (!priv->remapped_bar[bar])
120 return -ENOMEM;
121
122 port->iotype = UPIO_MEM;
123 port->mapbase = base + offset;
124 port->membase = priv->remapped_bar[bar] + offset;
125 port->regshift = regshift;
126 } else {
127 base = pci_resource_start(dev, bar) + offset;
128 port->iotype = UPIO_PORT;
129 port->iobase = base;
130 }
131 return 0;
132 }
133
134 /*
135 * AFAVLAB uses a different mixture of BARs and offsets
136 * Not that ugly ;) -- HW
137 */
138 static int
139 afavlab_setup(struct pci_dev *dev, struct pci_board *board,
140 struct uart_port *port, int idx)
141 {
142 unsigned int bar, offset = board->first_offset;
143
144 bar = FL_GET_BASE(board->flags);
145 if (idx < 4)
146 bar += idx;
147 else {
148 bar = 4;
149 offset += (idx - 4) * board->uart_offset;
150 }
151
152 return setup_port(dev, port, bar, offset, board->reg_shift);
153 }
154
155 /*
156 * HP's Remote Management Console. The Diva chip came in several
157 * different versions. N-class, L2000 and A500 have two Diva chips, each
158 * with 3 UARTs (the third UART on the second chip is unused). Superdome
159 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
160 * one Diva chip, but it has been expanded to 5 UARTs.
161 */
162 static int __devinit pci_hp_diva_init(struct pci_dev *dev)
163 {
164 int rc = 0;
165
166 switch (dev->subsystem_device) {
167 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
168 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
169 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
170 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
171 rc = 3;
172 break;
173 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
174 rc = 2;
175 break;
176 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
177 rc = 4;
178 break;
179 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
180 rc = 1;
181 break;
182 }
183
184 return rc;
185 }
186
187 /*
188 * HP's Diva chip puts the 4th/5th serial port further out, and
189 * some serial ports are supposed to be hidden on certain models.
190 */
191 static int
192 pci_hp_diva_setup(struct pci_dev *dev, struct pci_board *board,
193 struct uart_port *port, int idx)
194 {
195 unsigned int offset = board->first_offset;
196 unsigned int bar = FL_GET_BASE(board->flags);
197
198 switch (dev->subsystem_device) {
199 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
200 if (idx == 3)
201 idx++;
202 break;
203 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
204 if (idx > 0)
205 idx++;
206 if (idx > 2)
207 idx++;
208 break;
209 }
210 if (idx > 2)
211 offset = 0x18;
212
213 offset += idx * board->uart_offset;
214
215 return setup_port(dev, port, bar, offset, board->reg_shift);
216 }
217
218 /*
219 * Added for EKF Intel i960 serial boards
220 */
221 static int __devinit pci_inteli960ni_init(struct pci_dev *dev)
222 {
223 unsigned long oldval;
224
225 if (!(dev->subsystem_device & 0x1000))
226 return -ENODEV;
227
228 /* is firmware started? */
229 pci_read_config_dword(dev, 0x44, (void*) &oldval);
230 if (oldval == 0x00001000L) { /* RESET value */
231 printk(KERN_DEBUG "Local i960 firmware missing");
232 return -ENODEV;
233 }
234 return 0;
235 }
236
237 /*
238 * Some PCI serial cards using the PLX 9050 PCI interface chip require
239 * that the card interrupt be explicitly enabled or disabled. This
240 * seems to be mainly needed on card using the PLX which also use I/O
241 * mapped memory.
242 */
243 static int __devinit pci_plx9050_init(struct pci_dev *dev)
244 {
245 u8 irq_config;
246 void __iomem *p;
247
248 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
249 moan_device("no memory in bar 0", dev);
250 return 0;
251 }
252
253 irq_config = 0x41;
254 if (dev->vendor == PCI_VENDOR_ID_PANACOM)
255 irq_config = 0x43;
256 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
257 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
258 /*
259 * As the megawolf cards have the int pins active
260 * high, and have 2 UART chips, both ints must be
261 * enabled on the 9050. Also, the UARTS are set in
262 * 16450 mode by default, so we have to enable the
263 * 16C950 'enhanced' mode so that we can use the
264 * deep FIFOs
265 */
266 irq_config = 0x5b;
267 }
268
269 /*
270 * enable/disable interrupts
271 */
272 p = ioremap(pci_resource_start(dev, 0), 0x80);
273 if (p == NULL)
274 return -ENOMEM;
275 writel(irq_config, p + 0x4c);
276
277 /*
278 * Read the register back to ensure that it took effect.
279 */
280 readl(p + 0x4c);
281 iounmap(p);
282
283 return 0;
284 }
285
286 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
287 {
288 u8 __iomem *p;
289
290 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
291 return;
292
293 /*
294 * disable interrupts
295 */
296 p = ioremap(pci_resource_start(dev, 0), 0x80);
297 if (p != NULL) {
298 writel(0, p + 0x4c);
299
300 /*
301 * Read the register back to ensure that it took effect.
302 */
303 readl(p + 0x4c);
304 iounmap(p);
305 }
306 }
307
308 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
309 static int
310 sbs_setup(struct pci_dev *dev, struct pci_board *board,
311 struct uart_port *port, int idx)
312 {
313 unsigned int bar, offset = board->first_offset;
314
315 bar = 0;
316
317 if (idx < 4) {
318 /* first four channels map to 0, 0x100, 0x200, 0x300 */
319 offset += idx * board->uart_offset;
320 } else if (idx < 8) {
321 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
322 offset += idx * board->uart_offset + 0xC00;
323 } else /* we have only 8 ports on PMC-OCTALPRO */
324 return 1;
325
326 return setup_port(dev, port, bar, offset, board->reg_shift);
327 }
328
329 /*
330 * This does initialization for PMC OCTALPRO cards:
331 * maps the device memory, resets the UARTs (needed, bc
332 * if the module is removed and inserted again, the card
333 * is in the sleep mode) and enables global interrupt.
334 */
335
336 /* global control register offset for SBS PMC-OctalPro */
337 #define OCT_REG_CR_OFF 0x500
338
339 static int __devinit sbs_init(struct pci_dev *dev)
340 {
341 u8 __iomem *p;
342
343 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
344
345 if (p == NULL)
346 return -ENOMEM;
347 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
348 writeb(0x10,p + OCT_REG_CR_OFF);
349 udelay(50);
350 writeb(0x0,p + OCT_REG_CR_OFF);
351
352 /* Set bit-2 (INTENABLE) of Control Register */
353 writeb(0x4, p + OCT_REG_CR_OFF);
354 iounmap(p);
355
356 return 0;
357 }
358
359 /*
360 * Disables the global interrupt of PMC-OctalPro
361 */
362
363 static void __devexit sbs_exit(struct pci_dev *dev)
364 {
365 u8 __iomem *p;
366
367 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
368 if (p != NULL) {
369 writeb(0, p + OCT_REG_CR_OFF);
370 }
371 iounmap(p);
372 }
373
374 /*
375 * SIIG serial cards have an PCI interface chip which also controls
376 * the UART clocking frequency. Each UART can be clocked independently
377 * (except cards equiped with 4 UARTs) and initial clocking settings
378 * are stored in the EEPROM chip. It can cause problems because this
379 * version of serial driver doesn't support differently clocked UART's
380 * on single PCI card. To prevent this, initialization functions set
381 * high frequency clocking for all UART's on given card. It is safe (I
382 * hope) because it doesn't touch EEPROM settings to prevent conflicts
383 * with other OSes (like M$ DOS).
384 *
385 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
386 *
387 * There is two family of SIIG serial cards with different PCI
388 * interface chip and different configuration methods:
389 * - 10x cards have control registers in IO and/or memory space;
390 * - 20x cards have control registers in standard PCI configuration space.
391 *
392 * Note: some SIIG cards are probed by the parport_serial object.
393 */
394
395 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
396 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
397
398 static int pci_siig10x_init(struct pci_dev *dev)
399 {
400 u16 data;
401 void __iomem *p;
402
403 switch (dev->device & 0xfff8) {
404 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
405 data = 0xffdf;
406 break;
407 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
408 data = 0xf7ff;
409 break;
410 default: /* 1S1P, 4S */
411 data = 0xfffb;
412 break;
413 }
414
415 p = ioremap(pci_resource_start(dev, 0), 0x80);
416 if (p == NULL)
417 return -ENOMEM;
418
419 writew(readw(p + 0x28) & data, p + 0x28);
420 readw(p + 0x28);
421 iounmap(p);
422 return 0;
423 }
424
425 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
426 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
427
428 static int pci_siig20x_init(struct pci_dev *dev)
429 {
430 u8 data;
431
432 /* Change clock frequency for the first UART. */
433 pci_read_config_byte(dev, 0x6f, &data);
434 pci_write_config_byte(dev, 0x6f, data & 0xef);
435
436 /* If this card has 2 UART, we have to do the same with second UART. */
437 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
438 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
439 pci_read_config_byte(dev, 0x73, &data);
440 pci_write_config_byte(dev, 0x73, data & 0xef);
441 }
442 return 0;
443 }
444
445 int pci_siig10x_fn(struct pci_dev *dev, int enable)
446 {
447 int ret = 0;
448 if (enable)
449 ret = pci_siig10x_init(dev);
450 return ret;
451 }
452
453 int pci_siig20x_fn(struct pci_dev *dev, int enable)
454 {
455 int ret = 0;
456 if (enable)
457 ret = pci_siig20x_init(dev);
458 return ret;
459 }
460
461 EXPORT_SYMBOL(pci_siig10x_fn);
462 EXPORT_SYMBOL(pci_siig20x_fn);
463
464 /*
465 * Timedia has an explosion of boards, and to avoid the PCI table from
466 * growing *huge*, we use this function to collapse some 70 entries
467 * in the PCI table into one, for sanity's and compactness's sake.
468 */
469 static unsigned short timedia_single_port[] = {
470 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
471 };
472
473 static unsigned short timedia_dual_port[] = {
474 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
475 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
476 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
477 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
478 0xD079, 0
479 };
480
481 static unsigned short timedia_quad_port[] = {
482 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
483 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
484 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
485 0xB157, 0
486 };
487
488 static unsigned short timedia_eight_port[] = {
489 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
490 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
491 };
492
493 static struct timedia_struct {
494 int num;
495 unsigned short *ids;
496 } timedia_data[] = {
497 { 1, timedia_single_port },
498 { 2, timedia_dual_port },
499 { 4, timedia_quad_port },
500 { 8, timedia_eight_port },
501 { 0, NULL }
502 };
503
504 static int __devinit pci_timedia_init(struct pci_dev *dev)
505 {
506 unsigned short *ids;
507 int i, j;
508
509 for (i = 0; timedia_data[i].num; i++) {
510 ids = timedia_data[i].ids;
511 for (j = 0; ids[j]; j++)
512 if (dev->subsystem_device == ids[j])
513 return timedia_data[i].num;
514 }
515 return 0;
516 }
517
518 /*
519 * Timedia/SUNIX uses a mixture of BARs and offsets
520 * Ugh, this is ugly as all hell --- TYT
521 */
522 static int
523 pci_timedia_setup(struct pci_dev *dev, struct pci_board *board,
524 struct uart_port *port, int idx)
525 {
526 unsigned int bar = 0, offset = board->first_offset;
527
528 switch (idx) {
529 case 0:
530 bar = 0;
531 break;
532 case 1:
533 offset = board->uart_offset;
534 bar = 0;
535 break;
536 case 2:
537 bar = 1;
538 break;
539 case 3:
540 offset = board->uart_offset;
541 bar = 1;
542 case 4: /* BAR 2 */
543 case 5: /* BAR 3 */
544 case 6: /* BAR 4 */
545 case 7: /* BAR 5 */
546 bar = idx - 2;
547 }
548
549 return setup_port(dev, port, bar, offset, board->reg_shift);
550 }
551
552 /*
553 * Some Titan cards are also a little weird
554 */
555 static int
556 titan_400l_800l_setup(struct pci_dev *dev, struct pci_board *board,
557 struct uart_port *port, int idx)
558 {
559 unsigned int bar, offset = board->first_offset;
560
561 switch (idx) {
562 case 0:
563 bar = 1;
564 break;
565 case 1:
566 bar = 2;
567 break;
568 default:
569 bar = 4;
570 offset = (idx - 2) * board->uart_offset;
571 }
572
573 return setup_port(dev, port, bar, offset, board->reg_shift);
574 }
575
576 static int __devinit pci_xircom_init(struct pci_dev *dev)
577 {
578 msleep(100);
579 return 0;
580 }
581
582 static int __devinit pci_netmos_init(struct pci_dev *dev)
583 {
584 /* subdevice 0x00PS means <P> parallel, <S> serial */
585 unsigned int num_serial = dev->subsystem_device & 0xf;
586
587 if (num_serial == 0)
588 return -ENODEV;
589 return num_serial;
590 }
591
592 static int
593 pci_default_setup(struct pci_dev *dev, struct pci_board *board,
594 struct uart_port *port, int idx)
595 {
596 unsigned int bar, offset = board->first_offset, maxnr;
597
598 bar = FL_GET_BASE(board->flags);
599 if (board->flags & FL_BASE_BARS)
600 bar += idx;
601 else
602 offset += idx * board->uart_offset;
603
604 maxnr = (pci_resource_len(dev, bar) - board->first_offset) /
605 (8 << board->reg_shift);
606
607 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
608 return 1;
609
610 return setup_port(dev, port, bar, offset, board->reg_shift);
611 }
612
613 /* This should be in linux/pci_ids.h */
614 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
615 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
616 #define PCI_DEVICE_ID_OCTPRO 0x0001
617 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
618 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
619 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
620 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
621
622 /*
623 * Master list of serial port init/setup/exit quirks.
624 * This does not describe the general nature of the port.
625 * (ie, baud base, number and location of ports, etc)
626 *
627 * This list is ordered alphabetically by vendor then device.
628 * Specific entries must come before more generic entries.
629 */
630 static struct pci_serial_quirk pci_serial_quirks[] = {
631 /*
632 * AFAVLAB cards.
633 * It is not clear whether this applies to all products.
634 */
635 {
636 .vendor = PCI_VENDOR_ID_AFAVLAB,
637 .device = PCI_ANY_ID,
638 .subvendor = PCI_ANY_ID,
639 .subdevice = PCI_ANY_ID,
640 .setup = afavlab_setup,
641 },
642 /*
643 * HP Diva
644 */
645 {
646 .vendor = PCI_VENDOR_ID_HP,
647 .device = PCI_DEVICE_ID_HP_DIVA,
648 .subvendor = PCI_ANY_ID,
649 .subdevice = PCI_ANY_ID,
650 .init = pci_hp_diva_init,
651 .setup = pci_hp_diva_setup,
652 },
653 /*
654 * Intel
655 */
656 {
657 .vendor = PCI_VENDOR_ID_INTEL,
658 .device = PCI_DEVICE_ID_INTEL_80960_RP,
659 .subvendor = 0xe4bf,
660 .subdevice = PCI_ANY_ID,
661 .init = pci_inteli960ni_init,
662 .setup = pci_default_setup,
663 },
664 /*
665 * Panacom
666 */
667 {
668 .vendor = PCI_VENDOR_ID_PANACOM,
669 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
670 .subvendor = PCI_ANY_ID,
671 .subdevice = PCI_ANY_ID,
672 .init = pci_plx9050_init,
673 .setup = pci_default_setup,
674 .exit = __devexit_p(pci_plx9050_exit),
675 },
676 {
677 .vendor = PCI_VENDOR_ID_PANACOM,
678 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
679 .subvendor = PCI_ANY_ID,
680 .subdevice = PCI_ANY_ID,
681 .init = pci_plx9050_init,
682 .setup = pci_default_setup,
683 .exit = __devexit_p(pci_plx9050_exit),
684 },
685 /*
686 * PLX
687 */
688 {
689 .vendor = PCI_VENDOR_ID_PLX,
690 .device = PCI_DEVICE_ID_PLX_9050,
691 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
692 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
693 .init = pci_plx9050_init,
694 .setup = pci_default_setup,
695 .exit = __devexit_p(pci_plx9050_exit),
696 },
697 {
698 .vendor = PCI_VENDOR_ID_PLX,
699 .device = PCI_DEVICE_ID_PLX_ROMULUS,
700 .subvendor = PCI_VENDOR_ID_PLX,
701 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
702 .init = pci_plx9050_init,
703 .setup = pci_default_setup,
704 .exit = __devexit_p(pci_plx9050_exit),
705 },
706 /*
707 * SBS Technologies, Inc., PMC-OCTALPRO 232
708 */
709 {
710 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
711 .device = PCI_DEVICE_ID_OCTPRO,
712 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
713 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
714 .init = sbs_init,
715 .setup = sbs_setup,
716 .exit = __devexit_p(sbs_exit),
717 },
718 /*
719 * SBS Technologies, Inc., PMC-OCTALPRO 422
720 */
721 {
722 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
723 .device = PCI_DEVICE_ID_OCTPRO,
724 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
725 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
726 .init = sbs_init,
727 .setup = sbs_setup,
728 .exit = __devexit_p(sbs_exit),
729 },
730 /*
731 * SBS Technologies, Inc., P-Octal 232
732 */
733 {
734 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
735 .device = PCI_DEVICE_ID_OCTPRO,
736 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
737 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
738 .init = sbs_init,
739 .setup = sbs_setup,
740 .exit = __devexit_p(sbs_exit),
741 },
742 /*
743 * SBS Technologies, Inc., P-Octal 422
744 */
745 {
746 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
747 .device = PCI_DEVICE_ID_OCTPRO,
748 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
749 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
750 .init = sbs_init,
751 .setup = sbs_setup,
752 .exit = __devexit_p(sbs_exit),
753 },
754
755 /*
756 * SIIG cards.
757 * It is not clear whether these could be collapsed.
758 */
759 {
760 .vendor = PCI_VENDOR_ID_SIIG,
761 .device = PCI_DEVICE_ID_SIIG_1S_10x_550,
762 .subvendor = PCI_ANY_ID,
763 .subdevice = PCI_ANY_ID,
764 .init = pci_siig10x_init,
765 .setup = pci_default_setup,
766 },
767 {
768 .vendor = PCI_VENDOR_ID_SIIG,
769 .device = PCI_DEVICE_ID_SIIG_1S_10x_650,
770 .subvendor = PCI_ANY_ID,
771 .subdevice = PCI_ANY_ID,
772 .init = pci_siig10x_init,
773 .setup = pci_default_setup,
774 },
775 {
776 .vendor = PCI_VENDOR_ID_SIIG,
777 .device = PCI_DEVICE_ID_SIIG_1S_10x_850,
778 .subvendor = PCI_ANY_ID,
779 .subdevice = PCI_ANY_ID,
780 .init = pci_siig10x_init,
781 .setup = pci_default_setup,
782 },
783 {
784 .vendor = PCI_VENDOR_ID_SIIG,
785 .device = PCI_DEVICE_ID_SIIG_2S_10x_550,
786 .subvendor = PCI_ANY_ID,
787 .subdevice = PCI_ANY_ID,
788 .init = pci_siig10x_init,
789 .setup = pci_default_setup,
790 },
791 {
792 .vendor = PCI_VENDOR_ID_SIIG,
793 .device = PCI_DEVICE_ID_SIIG_2S_10x_650,
794 .subvendor = PCI_ANY_ID,
795 .subdevice = PCI_ANY_ID,
796 .init = pci_siig10x_init,
797 .setup = pci_default_setup,
798 },
799 {
800 .vendor = PCI_VENDOR_ID_SIIG,
801 .device = PCI_DEVICE_ID_SIIG_2S_10x_850,
802 .subvendor = PCI_ANY_ID,
803 .subdevice = PCI_ANY_ID,
804 .init = pci_siig10x_init,
805 .setup = pci_default_setup,
806 },
807 {
808 .vendor = PCI_VENDOR_ID_SIIG,
809 .device = PCI_DEVICE_ID_SIIG_4S_10x_550,
810 .subvendor = PCI_ANY_ID,
811 .subdevice = PCI_ANY_ID,
812 .init = pci_siig10x_init,
813 .setup = pci_default_setup,
814 },
815 {
816 .vendor = PCI_VENDOR_ID_SIIG,
817 .device = PCI_DEVICE_ID_SIIG_4S_10x_650,
818 .subvendor = PCI_ANY_ID,
819 .subdevice = PCI_ANY_ID,
820 .init = pci_siig10x_init,
821 .setup = pci_default_setup,
822 },
823 {
824 .vendor = PCI_VENDOR_ID_SIIG,
825 .device = PCI_DEVICE_ID_SIIG_4S_10x_850,
826 .subvendor = PCI_ANY_ID,
827 .subdevice = PCI_ANY_ID,
828 .init = pci_siig10x_init,
829 .setup = pci_default_setup,
830 },
831 {
832 .vendor = PCI_VENDOR_ID_SIIG,
833 .device = PCI_DEVICE_ID_SIIG_1S_20x_550,
834 .subvendor = PCI_ANY_ID,
835 .subdevice = PCI_ANY_ID,
836 .init = pci_siig20x_init,
837 .setup = pci_default_setup,
838 },
839 {
840 .vendor = PCI_VENDOR_ID_SIIG,
841 .device = PCI_DEVICE_ID_SIIG_1S_20x_650,
842 .subvendor = PCI_ANY_ID,
843 .subdevice = PCI_ANY_ID,
844 .init = pci_siig20x_init,
845 .setup = pci_default_setup,
846 },
847 {
848 .vendor = PCI_VENDOR_ID_SIIG,
849 .device = PCI_DEVICE_ID_SIIG_1S_20x_850,
850 .subvendor = PCI_ANY_ID,
851 .subdevice = PCI_ANY_ID,
852 .init = pci_siig20x_init,
853 .setup = pci_default_setup,
854 },
855 {
856 .vendor = PCI_VENDOR_ID_SIIG,
857 .device = PCI_DEVICE_ID_SIIG_2S_20x_550,
858 .subvendor = PCI_ANY_ID,
859 .subdevice = PCI_ANY_ID,
860 .init = pci_siig20x_init,
861 .setup = pci_default_setup,
862 },
863 { .vendor = PCI_VENDOR_ID_SIIG,
864 .device = PCI_DEVICE_ID_SIIG_2S_20x_650,
865 .subvendor = PCI_ANY_ID,
866 .subdevice = PCI_ANY_ID,
867 .init = pci_siig20x_init,
868 .setup = pci_default_setup,
869 },
870 {
871 .vendor = PCI_VENDOR_ID_SIIG,
872 .device = PCI_DEVICE_ID_SIIG_2S_20x_850,
873 .subvendor = PCI_ANY_ID,
874 .subdevice = PCI_ANY_ID,
875 .init = pci_siig20x_init,
876 .setup = pci_default_setup,
877 },
878 {
879 .vendor = PCI_VENDOR_ID_SIIG,
880 .device = PCI_DEVICE_ID_SIIG_4S_20x_550,
881 .subvendor = PCI_ANY_ID,
882 .subdevice = PCI_ANY_ID,
883 .init = pci_siig20x_init,
884 .setup = pci_default_setup,
885 },
886 {
887 .vendor = PCI_VENDOR_ID_SIIG,
888 .device = PCI_DEVICE_ID_SIIG_4S_20x_650,
889 .subvendor = PCI_ANY_ID,
890 .subdevice = PCI_ANY_ID,
891 .init = pci_siig20x_init,
892 .setup = pci_default_setup,
893 },
894 {
895 .vendor = PCI_VENDOR_ID_SIIG,
896 .device = PCI_DEVICE_ID_SIIG_4S_20x_850,
897 .subvendor = PCI_ANY_ID,
898 .subdevice = PCI_ANY_ID,
899 .init = pci_siig20x_init,
900 .setup = pci_default_setup,
901 },
902 /*
903 * Titan cards
904 */
905 {
906 .vendor = PCI_VENDOR_ID_TITAN,
907 .device = PCI_DEVICE_ID_TITAN_400L,
908 .subvendor = PCI_ANY_ID,
909 .subdevice = PCI_ANY_ID,
910 .setup = titan_400l_800l_setup,
911 },
912 {
913 .vendor = PCI_VENDOR_ID_TITAN,
914 .device = PCI_DEVICE_ID_TITAN_800L,
915 .subvendor = PCI_ANY_ID,
916 .subdevice = PCI_ANY_ID,
917 .setup = titan_400l_800l_setup,
918 },
919 /*
920 * Timedia cards
921 */
922 {
923 .vendor = PCI_VENDOR_ID_TIMEDIA,
924 .device = PCI_DEVICE_ID_TIMEDIA_1889,
925 .subvendor = PCI_VENDOR_ID_TIMEDIA,
926 .subdevice = PCI_ANY_ID,
927 .init = pci_timedia_init,
928 .setup = pci_timedia_setup,
929 },
930 {
931 .vendor = PCI_VENDOR_ID_TIMEDIA,
932 .device = PCI_ANY_ID,
933 .subvendor = PCI_ANY_ID,
934 .subdevice = PCI_ANY_ID,
935 .setup = pci_timedia_setup,
936 },
937 /*
938 * Xircom cards
939 */
940 {
941 .vendor = PCI_VENDOR_ID_XIRCOM,
942 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
943 .subvendor = PCI_ANY_ID,
944 .subdevice = PCI_ANY_ID,
945 .init = pci_xircom_init,
946 .setup = pci_default_setup,
947 },
948 /*
949 * Netmos cards
950 */
951 {
952 .vendor = PCI_VENDOR_ID_NETMOS,
953 .device = PCI_ANY_ID,
954 .subvendor = PCI_ANY_ID,
955 .subdevice = PCI_ANY_ID,
956 .init = pci_netmos_init,
957 .setup = pci_default_setup,
958 },
959 /*
960 * Default "match everything" terminator entry
961 */
962 {
963 .vendor = PCI_ANY_ID,
964 .device = PCI_ANY_ID,
965 .subvendor = PCI_ANY_ID,
966 .subdevice = PCI_ANY_ID,
967 .setup = pci_default_setup,
968 }
969 };
970
971 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
972 {
973 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
974 }
975
976 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
977 {
978 struct pci_serial_quirk *quirk;
979
980 for (quirk = pci_serial_quirks; ; quirk++)
981 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
982 quirk_id_matches(quirk->device, dev->device) &&
983 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
984 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
985 break;
986 return quirk;
987 }
988
989 static _INLINE_ int
990 get_pci_irq(struct pci_dev *dev, struct pci_board *board, int idx)
991 {
992 if (board->flags & FL_NOIRQ)
993 return 0;
994 else
995 return dev->irq;
996 }
997
998 /*
999 * This is the configuration table for all of the PCI serial boards
1000 * which we support. It is directly indexed by the pci_board_num_t enum
1001 * value, which is encoded in the pci_device_id PCI probe table's
1002 * driver_data member.
1003 *
1004 * The makeup of these names are:
1005 * pbn_bn{_bt}_n_baud
1006 *
1007 * bn = PCI BAR number
1008 * bt = Index using PCI BARs
1009 * n = number of serial ports
1010 * baud = baud rate
1011 *
1012 * This table is sorted by (in order): baud, bt, bn, n.
1013 *
1014 * Please note: in theory if n = 1, _bt infix should make no difference.
1015 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1016 */
1017 enum pci_board_num_t {
1018 pbn_default = 0,
1019
1020 pbn_b0_1_115200,
1021 pbn_b0_2_115200,
1022 pbn_b0_4_115200,
1023 pbn_b0_5_115200,
1024
1025 pbn_b0_1_921600,
1026 pbn_b0_2_921600,
1027 pbn_b0_4_921600,
1028
1029 pbn_b0_bt_1_115200,
1030 pbn_b0_bt_2_115200,
1031 pbn_b0_bt_8_115200,
1032
1033 pbn_b0_bt_1_460800,
1034 pbn_b0_bt_2_460800,
1035 pbn_b0_bt_4_460800,
1036
1037 pbn_b0_bt_1_921600,
1038 pbn_b0_bt_2_921600,
1039 pbn_b0_bt_4_921600,
1040 pbn_b0_bt_8_921600,
1041
1042 pbn_b1_1_115200,
1043 pbn_b1_2_115200,
1044 pbn_b1_4_115200,
1045 pbn_b1_8_115200,
1046
1047 pbn_b1_1_921600,
1048 pbn_b1_2_921600,
1049 pbn_b1_4_921600,
1050 pbn_b1_8_921600,
1051
1052 pbn_b1_bt_2_921600,
1053
1054 pbn_b1_1_1382400,
1055 pbn_b1_2_1382400,
1056 pbn_b1_4_1382400,
1057 pbn_b1_8_1382400,
1058
1059 pbn_b2_1_115200,
1060 pbn_b2_8_115200,
1061
1062 pbn_b2_1_460800,
1063 pbn_b2_4_460800,
1064 pbn_b2_8_460800,
1065 pbn_b2_16_460800,
1066
1067 pbn_b2_1_921600,
1068 pbn_b2_4_921600,
1069 pbn_b2_8_921600,
1070
1071 pbn_b2_bt_1_115200,
1072 pbn_b2_bt_2_115200,
1073 pbn_b2_bt_4_115200,
1074
1075 pbn_b2_bt_2_921600,
1076 pbn_b2_bt_4_921600,
1077
1078 pbn_b3_4_115200,
1079 pbn_b3_8_115200,
1080
1081 /*
1082 * Board-specific versions.
1083 */
1084 pbn_panacom,
1085 pbn_panacom2,
1086 pbn_panacom4,
1087 pbn_plx_romulus,
1088 pbn_oxsemi,
1089 pbn_intel_i960,
1090 pbn_sgi_ioc3,
1091 pbn_nec_nile4,
1092 pbn_computone_4,
1093 pbn_computone_6,
1094 pbn_computone_8,
1095 pbn_sbsxrsio,
1096 pbn_exar_XR17C152,
1097 pbn_exar_XR17C154,
1098 pbn_exar_XR17C158,
1099 };
1100
1101 /*
1102 * uart_offset - the space between channels
1103 * reg_shift - describes how the UART registers are mapped
1104 * to PCI memory by the card.
1105 * For example IER register on SBS, Inc. PMC-OctPro is located at
1106 * offset 0x10 from the UART base, while UART_IER is defined as 1
1107 * in include/linux/serial_reg.h,
1108 * see first lines of serial_in() and serial_out() in 8250.c
1109 */
1110
1111 static struct pci_board pci_boards[] __devinitdata = {
1112 [pbn_default] = {
1113 .flags = FL_BASE0,
1114 .num_ports = 1,
1115 .base_baud = 115200,
1116 .uart_offset = 8,
1117 },
1118 [pbn_b0_1_115200] = {
1119 .flags = FL_BASE0,
1120 .num_ports = 1,
1121 .base_baud = 115200,
1122 .uart_offset = 8,
1123 },
1124 [pbn_b0_2_115200] = {
1125 .flags = FL_BASE0,
1126 .num_ports = 2,
1127 .base_baud = 115200,
1128 .uart_offset = 8,
1129 },
1130 [pbn_b0_4_115200] = {
1131 .flags = FL_BASE0,
1132 .num_ports = 4,
1133 .base_baud = 115200,
1134 .uart_offset = 8,
1135 },
1136 [pbn_b0_5_115200] = {
1137 .flags = FL_BASE0,
1138 .num_ports = 5,
1139 .base_baud = 115200,
1140 .uart_offset = 8,
1141 },
1142
1143 [pbn_b0_1_921600] = {
1144 .flags = FL_BASE0,
1145 .num_ports = 1,
1146 .base_baud = 921600,
1147 .uart_offset = 8,
1148 },
1149 [pbn_b0_2_921600] = {
1150 .flags = FL_BASE0,
1151 .num_ports = 2,
1152 .base_baud = 921600,
1153 .uart_offset = 8,
1154 },
1155 [pbn_b0_4_921600] = {
1156 .flags = FL_BASE0,
1157 .num_ports = 4,
1158 .base_baud = 921600,
1159 .uart_offset = 8,
1160 },
1161
1162 [pbn_b0_bt_1_115200] = {
1163 .flags = FL_BASE0|FL_BASE_BARS,
1164 .num_ports = 1,
1165 .base_baud = 115200,
1166 .uart_offset = 8,
1167 },
1168 [pbn_b0_bt_2_115200] = {
1169 .flags = FL_BASE0|FL_BASE_BARS,
1170 .num_ports = 2,
1171 .base_baud = 115200,
1172 .uart_offset = 8,
1173 },
1174 [pbn_b0_bt_8_115200] = {
1175 .flags = FL_BASE0|FL_BASE_BARS,
1176 .num_ports = 8,
1177 .base_baud = 115200,
1178 .uart_offset = 8,
1179 },
1180
1181 [pbn_b0_bt_1_460800] = {
1182 .flags = FL_BASE0|FL_BASE_BARS,
1183 .num_ports = 1,
1184 .base_baud = 460800,
1185 .uart_offset = 8,
1186 },
1187 [pbn_b0_bt_2_460800] = {
1188 .flags = FL_BASE0|FL_BASE_BARS,
1189 .num_ports = 2,
1190 .base_baud = 460800,
1191 .uart_offset = 8,
1192 },
1193 [pbn_b0_bt_4_460800] = {
1194 .flags = FL_BASE0|FL_BASE_BARS,
1195 .num_ports = 4,
1196 .base_baud = 460800,
1197 .uart_offset = 8,
1198 },
1199
1200 [pbn_b0_bt_1_921600] = {
1201 .flags = FL_BASE0|FL_BASE_BARS,
1202 .num_ports = 1,
1203 .base_baud = 921600,
1204 .uart_offset = 8,
1205 },
1206 [pbn_b0_bt_2_921600] = {
1207 .flags = FL_BASE0|FL_BASE_BARS,
1208 .num_ports = 2,
1209 .base_baud = 921600,
1210 .uart_offset = 8,
1211 },
1212 [pbn_b0_bt_4_921600] = {
1213 .flags = FL_BASE0|FL_BASE_BARS,
1214 .num_ports = 4,
1215 .base_baud = 921600,
1216 .uart_offset = 8,
1217 },
1218 [pbn_b0_bt_8_921600] = {
1219 .flags = FL_BASE0|FL_BASE_BARS,
1220 .num_ports = 8,
1221 .base_baud = 921600,
1222 .uart_offset = 8,
1223 },
1224
1225 [pbn_b1_1_115200] = {
1226 .flags = FL_BASE1,
1227 .num_ports = 1,
1228 .base_baud = 115200,
1229 .uart_offset = 8,
1230 },
1231 [pbn_b1_2_115200] = {
1232 .flags = FL_BASE1,
1233 .num_ports = 2,
1234 .base_baud = 115200,
1235 .uart_offset = 8,
1236 },
1237 [pbn_b1_4_115200] = {
1238 .flags = FL_BASE1,
1239 .num_ports = 4,
1240 .base_baud = 115200,
1241 .uart_offset = 8,
1242 },
1243 [pbn_b1_8_115200] = {
1244 .flags = FL_BASE1,
1245 .num_ports = 8,
1246 .base_baud = 115200,
1247 .uart_offset = 8,
1248 },
1249
1250 [pbn_b1_1_921600] = {
1251 .flags = FL_BASE1,
1252 .num_ports = 1,
1253 .base_baud = 921600,
1254 .uart_offset = 8,
1255 },
1256 [pbn_b1_2_921600] = {
1257 .flags = FL_BASE1,
1258 .num_ports = 2,
1259 .base_baud = 921600,
1260 .uart_offset = 8,
1261 },
1262 [pbn_b1_4_921600] = {
1263 .flags = FL_BASE1,
1264 .num_ports = 4,
1265 .base_baud = 921600,
1266 .uart_offset = 8,
1267 },
1268 [pbn_b1_8_921600] = {
1269 .flags = FL_BASE1,
1270 .num_ports = 8,
1271 .base_baud = 921600,
1272 .uart_offset = 8,
1273 },
1274
1275 [pbn_b1_bt_2_921600] = {
1276 .flags = FL_BASE1|FL_BASE_BARS,
1277 .num_ports = 2,
1278 .base_baud = 921600,
1279 .uart_offset = 8,
1280 },
1281
1282 [pbn_b1_1_1382400] = {
1283 .flags = FL_BASE1,
1284 .num_ports = 1,
1285 .base_baud = 1382400,
1286 .uart_offset = 8,
1287 },
1288 [pbn_b1_2_1382400] = {
1289 .flags = FL_BASE1,
1290 .num_ports = 2,
1291 .base_baud = 1382400,
1292 .uart_offset = 8,
1293 },
1294 [pbn_b1_4_1382400] = {
1295 .flags = FL_BASE1,
1296 .num_ports = 4,
1297 .base_baud = 1382400,
1298 .uart_offset = 8,
1299 },
1300 [pbn_b1_8_1382400] = {
1301 .flags = FL_BASE1,
1302 .num_ports = 8,
1303 .base_baud = 1382400,
1304 .uart_offset = 8,
1305 },
1306
1307 [pbn_b2_1_115200] = {
1308 .flags = FL_BASE2,
1309 .num_ports = 1,
1310 .base_baud = 115200,
1311 .uart_offset = 8,
1312 },
1313 [pbn_b2_8_115200] = {
1314 .flags = FL_BASE2,
1315 .num_ports = 8,
1316 .base_baud = 115200,
1317 .uart_offset = 8,
1318 },
1319
1320 [pbn_b2_1_460800] = {
1321 .flags = FL_BASE2,
1322 .num_ports = 1,
1323 .base_baud = 460800,
1324 .uart_offset = 8,
1325 },
1326 [pbn_b2_4_460800] = {
1327 .flags = FL_BASE2,
1328 .num_ports = 4,
1329 .base_baud = 460800,
1330 .uart_offset = 8,
1331 },
1332 [pbn_b2_8_460800] = {
1333 .flags = FL_BASE2,
1334 .num_ports = 8,
1335 .base_baud = 460800,
1336 .uart_offset = 8,
1337 },
1338 [pbn_b2_16_460800] = {
1339 .flags = FL_BASE2,
1340 .num_ports = 16,
1341 .base_baud = 460800,
1342 .uart_offset = 8,
1343 },
1344
1345 [pbn_b2_1_921600] = {
1346 .flags = FL_BASE2,
1347 .num_ports = 1,
1348 .base_baud = 921600,
1349 .uart_offset = 8,
1350 },
1351 [pbn_b2_4_921600] = {
1352 .flags = FL_BASE2,
1353 .num_ports = 4,
1354 .base_baud = 921600,
1355 .uart_offset = 8,
1356 },
1357 [pbn_b2_8_921600] = {
1358 .flags = FL_BASE2,
1359 .num_ports = 8,
1360 .base_baud = 921600,
1361 .uart_offset = 8,
1362 },
1363
1364 [pbn_b2_bt_1_115200] = {
1365 .flags = FL_BASE2|FL_BASE_BARS,
1366 .num_ports = 1,
1367 .base_baud = 115200,
1368 .uart_offset = 8,
1369 },
1370 [pbn_b2_bt_2_115200] = {
1371 .flags = FL_BASE2|FL_BASE_BARS,
1372 .num_ports = 2,
1373 .base_baud = 115200,
1374 .uart_offset = 8,
1375 },
1376 [pbn_b2_bt_4_115200] = {
1377 .flags = FL_BASE2|FL_BASE_BARS,
1378 .num_ports = 4,
1379 .base_baud = 115200,
1380 .uart_offset = 8,
1381 },
1382
1383 [pbn_b2_bt_2_921600] = {
1384 .flags = FL_BASE2|FL_BASE_BARS,
1385 .num_ports = 2,
1386 .base_baud = 921600,
1387 .uart_offset = 8,
1388 },
1389 [pbn_b2_bt_4_921600] = {
1390 .flags = FL_BASE2|FL_BASE_BARS,
1391 .num_ports = 4,
1392 .base_baud = 921600,
1393 .uart_offset = 8,
1394 },
1395
1396 [pbn_b3_4_115200] = {
1397 .flags = FL_BASE3,
1398 .num_ports = 4,
1399 .base_baud = 115200,
1400 .uart_offset = 8,
1401 },
1402 [pbn_b3_8_115200] = {
1403 .flags = FL_BASE3,
1404 .num_ports = 8,
1405 .base_baud = 115200,
1406 .uart_offset = 8,
1407 },
1408
1409 /*
1410 * Entries following this are board-specific.
1411 */
1412
1413 /*
1414 * Panacom - IOMEM
1415 */
1416 [pbn_panacom] = {
1417 .flags = FL_BASE2,
1418 .num_ports = 2,
1419 .base_baud = 921600,
1420 .uart_offset = 0x400,
1421 .reg_shift = 7,
1422 },
1423 [pbn_panacom2] = {
1424 .flags = FL_BASE2|FL_BASE_BARS,
1425 .num_ports = 2,
1426 .base_baud = 921600,
1427 .uart_offset = 0x400,
1428 .reg_shift = 7,
1429 },
1430 [pbn_panacom4] = {
1431 .flags = FL_BASE2|FL_BASE_BARS,
1432 .num_ports = 4,
1433 .base_baud = 921600,
1434 .uart_offset = 0x400,
1435 .reg_shift = 7,
1436 },
1437
1438 /* I think this entry is broken - the first_offset looks wrong --rmk */
1439 [pbn_plx_romulus] = {
1440 .flags = FL_BASE2,
1441 .num_ports = 4,
1442 .base_baud = 921600,
1443 .uart_offset = 8 << 2,
1444 .reg_shift = 2,
1445 .first_offset = 0x03,
1446 },
1447
1448 /*
1449 * This board uses the size of PCI Base region 0 to
1450 * signal now many ports are available
1451 */
1452 [pbn_oxsemi] = {
1453 .flags = FL_BASE0|FL_REGION_SZ_CAP,
1454 .num_ports = 32,
1455 .base_baud = 115200,
1456 .uart_offset = 8,
1457 },
1458
1459 /*
1460 * EKF addition for i960 Boards form EKF with serial port.
1461 * Max 256 ports.
1462 */
1463 [pbn_intel_i960] = {
1464 .flags = FL_BASE0,
1465 .num_ports = 32,
1466 .base_baud = 921600,
1467 .uart_offset = 8 << 2,
1468 .reg_shift = 2,
1469 .first_offset = 0x10000,
1470 },
1471 [pbn_sgi_ioc3] = {
1472 .flags = FL_BASE0|FL_NOIRQ,
1473 .num_ports = 1,
1474 .base_baud = 458333,
1475 .uart_offset = 8,
1476 .reg_shift = 0,
1477 .first_offset = 0x20178,
1478 },
1479
1480 /*
1481 * NEC Vrc-5074 (Nile 4) builtin UART.
1482 */
1483 [pbn_nec_nile4] = {
1484 .flags = FL_BASE0,
1485 .num_ports = 1,
1486 .base_baud = 520833,
1487 .uart_offset = 8 << 3,
1488 .reg_shift = 3,
1489 .first_offset = 0x300,
1490 },
1491
1492 /*
1493 * Computone - uses IOMEM.
1494 */
1495 [pbn_computone_4] = {
1496 .flags = FL_BASE0,
1497 .num_ports = 4,
1498 .base_baud = 921600,
1499 .uart_offset = 0x40,
1500 .reg_shift = 2,
1501 .first_offset = 0x200,
1502 },
1503 [pbn_computone_6] = {
1504 .flags = FL_BASE0,
1505 .num_ports = 6,
1506 .base_baud = 921600,
1507 .uart_offset = 0x40,
1508 .reg_shift = 2,
1509 .first_offset = 0x200,
1510 },
1511 [pbn_computone_8] = {
1512 .flags = FL_BASE0,
1513 .num_ports = 8,
1514 .base_baud = 921600,
1515 .uart_offset = 0x40,
1516 .reg_shift = 2,
1517 .first_offset = 0x200,
1518 },
1519 [pbn_sbsxrsio] = {
1520 .flags = FL_BASE0,
1521 .num_ports = 8,
1522 .base_baud = 460800,
1523 .uart_offset = 256,
1524 .reg_shift = 4,
1525 },
1526 /*
1527 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1528 * Only basic 16550A support.
1529 * XR17C15[24] are not tested, but they should work.
1530 */
1531 [pbn_exar_XR17C152] = {
1532 .flags = FL_BASE0,
1533 .num_ports = 2,
1534 .base_baud = 921600,
1535 .uart_offset = 0x200,
1536 },
1537 [pbn_exar_XR17C154] = {
1538 .flags = FL_BASE0,
1539 .num_ports = 4,
1540 .base_baud = 921600,
1541 .uart_offset = 0x200,
1542 },
1543 [pbn_exar_XR17C158] = {
1544 .flags = FL_BASE0,
1545 .num_ports = 8,
1546 .base_baud = 921600,
1547 .uart_offset = 0x200,
1548 },
1549 };
1550
1551 /*
1552 * Given a complete unknown PCI device, try to use some heuristics to
1553 * guess what the configuration might be, based on the pitiful PCI
1554 * serial specs. Returns 0 on success, 1 on failure.
1555 */
1556 static int __devinit
1557 serial_pci_guess_board(struct pci_dev *dev, struct pci_board *board)
1558 {
1559 int num_iomem, num_port, first_port = -1, i;
1560
1561 /*
1562 * If it is not a communications device or the programming
1563 * interface is greater than 6, give up.
1564 *
1565 * (Should we try to make guesses for multiport serial devices
1566 * later?)
1567 */
1568 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1569 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1570 (dev->class & 0xff) > 6)
1571 return -ENODEV;
1572
1573 num_iomem = num_port = 0;
1574 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1575 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1576 num_port++;
1577 if (first_port == -1)
1578 first_port = i;
1579 }
1580 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1581 num_iomem++;
1582 }
1583
1584 /*
1585 * If there is 1 or 0 iomem regions, and exactly one port,
1586 * use it. We guess the number of ports based on the IO
1587 * region size.
1588 */
1589 if (num_iomem <= 1 && num_port == 1) {
1590 board->flags = first_port;
1591 board->num_ports = pci_resource_len(dev, first_port) / 8;
1592 return 0;
1593 }
1594
1595 /*
1596 * Now guess if we've got a board which indexes by BARs.
1597 * Each IO BAR should be 8 bytes, and they should follow
1598 * consecutively.
1599 */
1600 first_port = -1;
1601 num_port = 0;
1602 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1603 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1604 pci_resource_len(dev, i) == 8 &&
1605 (first_port == -1 || (first_port + num_port) == i)) {
1606 num_port++;
1607 if (first_port == -1)
1608 first_port = i;
1609 }
1610 }
1611
1612 if (num_port > 1) {
1613 board->flags = first_port | FL_BASE_BARS;
1614 board->num_ports = num_port;
1615 return 0;
1616 }
1617
1618 return -ENODEV;
1619 }
1620
1621 static inline int
1622 serial_pci_matches(struct pci_board *board, struct pci_board *guessed)
1623 {
1624 return
1625 board->num_ports == guessed->num_ports &&
1626 board->base_baud == guessed->base_baud &&
1627 board->uart_offset == guessed->uart_offset &&
1628 board->reg_shift == guessed->reg_shift &&
1629 board->first_offset == guessed->first_offset;
1630 }
1631
1632 /*
1633 * Probe one serial board. Unfortunately, there is no rhyme nor reason
1634 * to the arrangement of serial ports on a PCI card.
1635 */
1636 static int __devinit
1637 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1638 {
1639 struct serial_private *priv;
1640 struct pci_board *board, tmp;
1641 struct pci_serial_quirk *quirk;
1642 int rc, nr_ports, i;
1643
1644 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1645 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1646 ent->driver_data);
1647 return -EINVAL;
1648 }
1649
1650 board = &pci_boards[ent->driver_data];
1651
1652 rc = pci_enable_device(dev);
1653 if (rc)
1654 return rc;
1655
1656 if (ent->driver_data == pbn_default) {
1657 /*
1658 * Use a copy of the pci_board entry for this;
1659 * avoid changing entries in the table.
1660 */
1661 memcpy(&tmp, board, sizeof(struct pci_board));
1662 board = &tmp;
1663
1664 /*
1665 * We matched one of our class entries. Try to
1666 * determine the parameters of this board.
1667 */
1668 rc = serial_pci_guess_board(dev, board);
1669 if (rc)
1670 goto disable;
1671 } else {
1672 /*
1673 * We matched an explicit entry. If we are able to
1674 * detect this boards settings with our heuristic,
1675 * then we no longer need this entry.
1676 */
1677 memcpy(&tmp, &pci_boards[pbn_default], sizeof(struct pci_board));
1678 rc = serial_pci_guess_board(dev, &tmp);
1679 if (rc == 0 && serial_pci_matches(board, &tmp))
1680 moan_device("Redundant entry in serial pci_table.",
1681 dev);
1682 }
1683
1684 nr_ports = board->num_ports;
1685
1686 /*
1687 * Find an init and setup quirks.
1688 */
1689 quirk = find_quirk(dev);
1690
1691 /*
1692 * Run the new-style initialization function.
1693 * The initialization function returns:
1694 * <0 - error
1695 * 0 - use board->num_ports
1696 * >0 - number of ports
1697 */
1698 if (quirk->init) {
1699 rc = quirk->init(dev);
1700 if (rc < 0)
1701 goto disable;
1702 if (rc)
1703 nr_ports = rc;
1704 }
1705
1706 priv = kmalloc(sizeof(struct serial_private) +
1707 sizeof(unsigned int) * nr_ports,
1708 GFP_KERNEL);
1709 if (!priv) {
1710 rc = -ENOMEM;
1711 goto deinit;
1712 }
1713
1714 memset(priv, 0, sizeof(struct serial_private) +
1715 sizeof(unsigned int) * nr_ports);
1716
1717 priv->quirk = quirk;
1718 pci_set_drvdata(dev, priv);
1719
1720 for (i = 0; i < nr_ports; i++) {
1721 struct uart_port serial_port;
1722 memset(&serial_port, 0, sizeof(struct uart_port));
1723
1724 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF |
1725 UPF_SHARE_IRQ;
1726 serial_port.uartclk = board->base_baud * 16;
1727 serial_port.irq = get_pci_irq(dev, board, i);
1728 serial_port.dev = &dev->dev;
1729 if (quirk->setup(dev, board, &serial_port, i))
1730 break;
1731 #ifdef SERIAL_DEBUG_PCI
1732 printk("Setup PCI port: port %x, irq %d, type %d\n",
1733 serial_port.iobase, serial_port.irq, serial_port.iotype);
1734 #endif
1735
1736 priv->line[i] = serial8250_register_port(&serial_port);
1737 if (priv->line[i] < 0) {
1738 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1739 break;
1740 }
1741 }
1742
1743 priv->nr = i;
1744
1745 return 0;
1746
1747 deinit:
1748 if (quirk->exit)
1749 quirk->exit(dev);
1750 disable:
1751 pci_disable_device(dev);
1752 return rc;
1753 }
1754
1755 static void __devexit pciserial_remove_one(struct pci_dev *dev)
1756 {
1757 struct serial_private *priv = pci_get_drvdata(dev);
1758
1759 pci_set_drvdata(dev, NULL);
1760
1761 if (priv) {
1762 struct pci_serial_quirk *quirk;
1763 int i;
1764
1765 for (i = 0; i < priv->nr; i++)
1766 serial8250_unregister_port(priv->line[i]);
1767
1768 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1769 if (priv->remapped_bar[i])
1770 iounmap(priv->remapped_bar[i]);
1771 priv->remapped_bar[i] = NULL;
1772 }
1773
1774 /*
1775 * Find the exit quirks.
1776 */
1777 quirk = find_quirk(dev);
1778 if (quirk->exit)
1779 quirk->exit(dev);
1780
1781 pci_disable_device(dev);
1782
1783 kfree(priv);
1784 }
1785 }
1786
1787 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
1788 {
1789 struct serial_private *priv = pci_get_drvdata(dev);
1790
1791 if (priv) {
1792 int i;
1793
1794 for (i = 0; i < priv->nr; i++)
1795 serial8250_suspend_port(priv->line[i]);
1796 }
1797 pci_save_state(dev);
1798 pci_set_power_state(dev, pci_choose_state(dev, state));
1799 return 0;
1800 }
1801
1802 static int pciserial_resume_one(struct pci_dev *dev)
1803 {
1804 struct serial_private *priv = pci_get_drvdata(dev);
1805
1806 pci_set_power_state(dev, PCI_D0);
1807 pci_restore_state(dev);
1808
1809 if (priv) {
1810 int i;
1811
1812 /*
1813 * The device may have been disabled. Re-enable it.
1814 */
1815 pci_enable_device(dev);
1816
1817 /*
1818 * Ensure that the board is correctly configured.
1819 */
1820 if (priv->quirk->init)
1821 priv->quirk->init(dev);
1822
1823 for (i = 0; i < priv->nr; i++)
1824 serial8250_resume_port(priv->line[i]);
1825 }
1826 return 0;
1827 }
1828
1829 static struct pci_device_id serial_pci_tbl[] = {
1830 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1831 PCI_SUBVENDOR_ID_CONNECT_TECH,
1832 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1833 pbn_b1_8_1382400 },
1834 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1835 PCI_SUBVENDOR_ID_CONNECT_TECH,
1836 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1837 pbn_b1_4_1382400 },
1838 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1839 PCI_SUBVENDOR_ID_CONNECT_TECH,
1840 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1841 pbn_b1_2_1382400 },
1842 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1843 PCI_SUBVENDOR_ID_CONNECT_TECH,
1844 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1845 pbn_b1_8_1382400 },
1846 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1847 PCI_SUBVENDOR_ID_CONNECT_TECH,
1848 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1849 pbn_b1_4_1382400 },
1850 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1851 PCI_SUBVENDOR_ID_CONNECT_TECH,
1852 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1853 pbn_b1_2_1382400 },
1854 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1855 PCI_SUBVENDOR_ID_CONNECT_TECH,
1856 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1857 pbn_b1_8_921600 },
1858 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1859 PCI_SUBVENDOR_ID_CONNECT_TECH,
1860 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1861 pbn_b1_8_921600 },
1862 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1863 PCI_SUBVENDOR_ID_CONNECT_TECH,
1864 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1865 pbn_b1_4_921600 },
1866 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1867 PCI_SUBVENDOR_ID_CONNECT_TECH,
1868 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1869 pbn_b1_4_921600 },
1870 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1871 PCI_SUBVENDOR_ID_CONNECT_TECH,
1872 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1873 pbn_b1_2_921600 },
1874 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1875 PCI_SUBVENDOR_ID_CONNECT_TECH,
1876 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1877 pbn_b1_8_921600 },
1878 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1879 PCI_SUBVENDOR_ID_CONNECT_TECH,
1880 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1881 pbn_b1_8_921600 },
1882 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1883 PCI_SUBVENDOR_ID_CONNECT_TECH,
1884 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1885 pbn_b1_4_921600 },
1886
1887 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1888 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1889 pbn_b2_bt_1_115200 },
1890 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1891 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1892 pbn_b2_bt_2_115200 },
1893 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1894 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1895 pbn_b2_bt_4_115200 },
1896 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1897 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1898 pbn_b2_bt_2_115200 },
1899 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1900 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1901 pbn_b2_bt_4_115200 },
1902 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1903 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1904 pbn_b2_8_115200 },
1905 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
1906 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1907 pbn_b2_8_115200 },
1908
1909 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1910 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1911 pbn_b2_bt_2_115200 },
1912 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1913 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1914 pbn_b2_bt_2_921600 },
1915 /*
1916 * VScom SPCOM800, from sl@s.pl
1917 */
1918 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1919 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1920 pbn_b2_8_921600 },
1921 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1922 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1923 pbn_b2_4_921600 },
1924 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1925 PCI_SUBVENDOR_ID_KEYSPAN,
1926 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1927 pbn_panacom },
1928 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1929 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1930 pbn_panacom4 },
1931 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
1932 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1933 pbn_panacom2 },
1934 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1935 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1936 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1937 pbn_b2_4_460800 },
1938 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1939 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1940 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1941 pbn_b2_8_460800 },
1942 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1943 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1944 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1945 pbn_b2_16_460800 },
1946 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1947 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1948 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1949 pbn_b2_16_460800 },
1950 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1951 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1952 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1953 pbn_b2_4_460800 },
1954 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1955 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1956 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1957 pbn_b2_8_460800 },
1958 /*
1959 * Megawolf Romulus PCI Serial Card, from Mike Hudson
1960 * (Exoray@isys.ca)
1961 */
1962 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
1963 0x10b5, 0x106a, 0, 0,
1964 pbn_plx_romulus },
1965 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
1966 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1967 pbn_b1_4_115200 },
1968 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
1969 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1970 pbn_b1_2_115200 },
1971 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
1972 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1973 pbn_b1_8_115200 },
1974 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
1975 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1976 pbn_b1_8_115200 },
1977 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
1978 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
1979 pbn_b0_4_921600 },
1980 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1981 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1982 pbn_b0_4_115200 },
1983 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
1984 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1985 pbn_b0_bt_2_921600 },
1986
1987 /*
1988 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
1989 * from skokodyn@yahoo.com
1990 */
1991 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1992 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
1993 pbn_sbsxrsio },
1994 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1995 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
1996 pbn_sbsxrsio },
1997 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1998 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
1999 pbn_sbsxrsio },
2000 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2001 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2002 pbn_sbsxrsio },
2003
2004 /*
2005 * Digitan DS560-558, from jimd@esoft.com
2006 */
2007 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2008 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2009 pbn_b1_1_115200 },
2010
2011 /*
2012 * Titan Electronic cards
2013 * The 400L and 800L have a custom setup quirk.
2014 */
2015 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2016 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2017 pbn_b0_1_921600 },
2018 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2019 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2020 pbn_b0_2_921600 },
2021 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2022 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2023 pbn_b0_4_921600 },
2024 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2025 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2026 pbn_b0_4_921600 },
2027 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2028 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2029 pbn_b1_1_921600 },
2030 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2031 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2032 pbn_b1_bt_2_921600 },
2033 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2034 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2035 pbn_b0_bt_4_921600 },
2036 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2037 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2038 pbn_b0_bt_8_921600 },
2039
2040 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2041 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2042 pbn_b2_1_460800 },
2043 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2044 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2045 pbn_b2_1_460800 },
2046 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2047 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2048 pbn_b2_1_460800 },
2049 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2050 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2051 pbn_b2_bt_2_921600 },
2052 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2053 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2054 pbn_b2_bt_2_921600 },
2055 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2056 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2057 pbn_b2_bt_2_921600 },
2058 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2059 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2060 pbn_b2_bt_4_921600 },
2061 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2062 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2063 pbn_b2_bt_4_921600 },
2064 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2065 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2066 pbn_b2_bt_4_921600 },
2067 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2068 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2069 pbn_b0_1_921600 },
2070 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2071 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2072 pbn_b0_1_921600 },
2073 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2074 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2075 pbn_b0_1_921600 },
2076 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2077 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2078 pbn_b0_bt_2_921600 },
2079 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2080 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2081 pbn_b0_bt_2_921600 },
2082 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2083 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2084 pbn_b0_bt_2_921600 },
2085 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2086 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2087 pbn_b0_bt_4_921600 },
2088 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2089 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2090 pbn_b0_bt_4_921600 },
2091 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2092 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2093 pbn_b0_bt_4_921600 },
2094
2095 /*
2096 * Computone devices submitted by Doug McNash dmcnash@computone.com
2097 */
2098 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2099 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2100 0, 0, pbn_computone_4 },
2101 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2102 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2103 0, 0, pbn_computone_8 },
2104 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2105 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2106 0, 0, pbn_computone_6 },
2107
2108 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2109 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2110 pbn_oxsemi },
2111 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2112 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2113 pbn_b0_bt_1_921600 },
2114
2115 /*
2116 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2117 */
2118 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2119 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2120 pbn_b0_bt_8_115200 },
2121 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2122 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2123 pbn_b0_bt_8_115200 },
2124
2125 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2126 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2127 pbn_b0_bt_2_115200 },
2128 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2129 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2130 pbn_b0_bt_2_115200 },
2131 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2132 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2133 pbn_b0_bt_2_115200 },
2134 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2135 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2136 pbn_b0_bt_4_460800 },
2137 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2138 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2139 pbn_b0_bt_4_460800 },
2140 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2141 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2142 pbn_b0_bt_2_460800 },
2143 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2144 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2145 pbn_b0_bt_2_460800 },
2146 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2147 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2148 pbn_b0_bt_2_460800 },
2149 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2150 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2151 pbn_b0_bt_1_115200 },
2152 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2153 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2154 pbn_b0_bt_1_460800 },
2155
2156 /*
2157 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2158 */
2159 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2160 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2161 pbn_b1_1_1382400 },
2162
2163 /*
2164 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2165 */
2166 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2167 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2168 pbn_b1_1_1382400 },
2169
2170 /*
2171 * RAStel 2 port modem, gerg@moreton.com.au
2172 */
2173 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2174 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2175 pbn_b2_bt_2_115200 },
2176
2177 /*
2178 * EKF addition for i960 Boards form EKF with serial port
2179 */
2180 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2181 0xE4BF, PCI_ANY_ID, 0, 0,
2182 pbn_intel_i960 },
2183
2184 /*
2185 * Xircom Cardbus/Ethernet combos
2186 */
2187 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2188 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2189 pbn_b0_1_115200 },
2190 /*
2191 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2192 */
2193 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2194 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2195 pbn_b0_1_115200 },
2196
2197 /*
2198 * Untested PCI modems, sent in from various folks...
2199 */
2200
2201 /*
2202 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2203 */
2204 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
2205 0x1048, 0x1500, 0, 0,
2206 pbn_b1_1_115200 },
2207
2208 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2209 0xFF00, 0, 0, 0,
2210 pbn_sgi_ioc3 },
2211
2212 /*
2213 * HP Diva card
2214 */
2215 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2216 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2217 pbn_b1_1_115200 },
2218 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2219 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2220 pbn_b0_5_115200 },
2221 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2222 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2223 pbn_b2_1_115200 },
2224
2225 /*
2226 * NEC Vrc-5074 (Nile 4) builtin UART.
2227 */
2228 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
2229 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2230 pbn_nec_nile4 },
2231
2232 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2233 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2234 pbn_b3_4_115200 },
2235 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2236 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2237 pbn_b3_8_115200 },
2238
2239 /*
2240 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2241 */
2242 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2243 PCI_ANY_ID, PCI_ANY_ID,
2244 0,
2245 0, pbn_exar_XR17C152 },
2246 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2247 PCI_ANY_ID, PCI_ANY_ID,
2248 0,
2249 0, pbn_exar_XR17C154 },
2250 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2251 PCI_ANY_ID, PCI_ANY_ID,
2252 0,
2253 0, pbn_exar_XR17C158 },
2254
2255 /*
2256 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2257 */
2258 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2259 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2260 pbn_b0_1_115200 },
2261
2262 /*
2263 * These entries match devices with class COMMUNICATION_SERIAL,
2264 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2265 */
2266 { PCI_ANY_ID, PCI_ANY_ID,
2267 PCI_ANY_ID, PCI_ANY_ID,
2268 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2269 0xffff00, pbn_default },
2270 { PCI_ANY_ID, PCI_ANY_ID,
2271 PCI_ANY_ID, PCI_ANY_ID,
2272 PCI_CLASS_COMMUNICATION_MODEM << 8,
2273 0xffff00, pbn_default },
2274 { PCI_ANY_ID, PCI_ANY_ID,
2275 PCI_ANY_ID, PCI_ANY_ID,
2276 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2277 0xffff00, pbn_default },
2278 { 0, }
2279 };
2280
2281 static struct pci_driver serial_pci_driver = {
2282 .name = "serial",
2283 .probe = pciserial_init_one,
2284 .remove = __devexit_p(pciserial_remove_one),
2285 .suspend = pciserial_suspend_one,
2286 .resume = pciserial_resume_one,
2287 .id_table = serial_pci_tbl,
2288 };
2289
2290 static int __init serial8250_pci_init(void)
2291 {
2292 return pci_register_driver(&serial_pci_driver);
2293 }
2294
2295 static void __exit serial8250_pci_exit(void)
2296 {
2297 pci_unregister_driver(&serial_pci_driver);
2298 }
2299
2300 module_init(serial8250_pci_init);
2301 module_exit(serial8250_pci_exit);
2302
2303 MODULE_LICENSE("GPL");
2304 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2305 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
AMDTP streaming driver for the Linux FireWire stack (Juju)