2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2009 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
45 #include <net/checksum.h>
48 #include <asm/system.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
54 #include <asm/idprom.h>
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
64 #define TG3_VLAN_TAG_USED 0
69 #define DRV_MODULE_NAME "tg3"
70 #define PFX DRV_MODULE_NAME ": "
71 #define DRV_MODULE_VERSION "3.103"
72 #define DRV_MODULE_RELDATE "November 2, 2009"
74 #define TG3_DEF_MAC_MODE 0
75 #define TG3_DEF_RX_MODE 0
76 #define TG3_DEF_TX_MODE 0
77 #define TG3_DEF_MSG_ENABLE \
87 /* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
90 #define TG3_TX_TIMEOUT (5 * HZ)
92 /* hardware minimum and maximum for a single frame's data payload */
93 #define TG3_MIN_MTU 60
94 #define TG3_MAX_MTU(tp) \
95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
97 /* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
101 #define TG3_RX_RING_SIZE 512
102 #define TG3_DEF_RX_RING_PENDING 200
103 #define TG3_RX_JUMBO_RING_SIZE 256
104 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
105 #define TG3_RSS_INDIR_TBL_SIZE 128
107 /* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
113 #define TG3_RX_RCB_RING_SIZE(tp) \
114 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
115 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
117 #define TG3_TX_RING_SIZE 512
118 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
120 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
122 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
123 TG3_RX_JUMBO_RING_SIZE)
124 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
125 TG3_RX_RCB_RING_SIZE(tp))
126 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
128 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
130 #define TG3_DMA_BYTE_ENAB 64
132 #define TG3_RX_STD_DMA_SZ 1536
133 #define TG3_RX_JMB_DMA_SZ 9046
135 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
137 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
138 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
140 /* minimum number of free TX descriptors required to wake up TX process */
141 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
143 #define TG3_RAW_IP_ALIGN 2
145 /* number of ETHTOOL_GSTATS u64's */
146 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
148 #define TG3_NUM_TEST 6
150 #define FIRMWARE_TG3 "tigon/tg3.bin"
151 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
152 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
154 static char version
[] __devinitdata
=
155 DRV_MODULE_NAME
".c:v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")\n";
157 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
158 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
159 MODULE_LICENSE("GPL");
160 MODULE_VERSION(DRV_MODULE_VERSION
);
161 MODULE_FIRMWARE(FIRMWARE_TG3
);
162 MODULE_FIRMWARE(FIRMWARE_TG3TSO
);
163 MODULE_FIRMWARE(FIRMWARE_TG3TSO5
);
165 #define TG3_RSS_MIN_NUM_MSIX_VECS 2
167 static int tg3_debug
= -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
168 module_param(tg3_debug
, int, 0);
169 MODULE_PARM_DESC(tg3_debug
, "Tigon3 bitmapped debugging message enable value");
171 static struct pci_device_id tg3_pci_tbl
[] = {
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5700
)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5701
)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702
)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703
)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704
)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702FE
)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705
)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705_2
)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M
)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M_2
)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702X
)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703X
)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S
)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702A3
)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703A3
)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5782
)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5788
)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5789
)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901
)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901_2
)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S_2
)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705F
)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5720
)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5721
)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5722
)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5750
)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751
)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5750M
)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751M
)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751F
)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752
)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752M
)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753
)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753M
)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753F
)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754
)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754M
)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755
)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755M
)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5756
)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5786
)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787
)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787M
)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787F
)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714
)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714S
)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715
)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715S
)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780
)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780S
)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5781
)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906
)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906M
)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5784
)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5764
)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5723
)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761
)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761E
)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761S
)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761SE
)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5785_G
)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5785_F
)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57780
)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57760
)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57790
)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57788
)},
238 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9DXX
)},
239 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9MXX
)},
240 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1000
)},
241 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1001
)},
242 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1003
)},
243 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC9100
)},
244 {PCI_DEVICE(PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_TIGON3
)},
248 MODULE_DEVICE_TABLE(pci
, tg3_pci_tbl
);
250 static const struct {
251 const char string
[ETH_GSTRING_LEN
];
252 } ethtool_stats_keys
[TG3_NUM_STATS
] = {
255 { "rx_ucast_packets" },
256 { "rx_mcast_packets" },
257 { "rx_bcast_packets" },
259 { "rx_align_errors" },
260 { "rx_xon_pause_rcvd" },
261 { "rx_xoff_pause_rcvd" },
262 { "rx_mac_ctrl_rcvd" },
263 { "rx_xoff_entered" },
264 { "rx_frame_too_long_errors" },
266 { "rx_undersize_packets" },
267 { "rx_in_length_errors" },
268 { "rx_out_length_errors" },
269 { "rx_64_or_less_octet_packets" },
270 { "rx_65_to_127_octet_packets" },
271 { "rx_128_to_255_octet_packets" },
272 { "rx_256_to_511_octet_packets" },
273 { "rx_512_to_1023_octet_packets" },
274 { "rx_1024_to_1522_octet_packets" },
275 { "rx_1523_to_2047_octet_packets" },
276 { "rx_2048_to_4095_octet_packets" },
277 { "rx_4096_to_8191_octet_packets" },
278 { "rx_8192_to_9022_octet_packets" },
285 { "tx_flow_control" },
287 { "tx_single_collisions" },
288 { "tx_mult_collisions" },
290 { "tx_excessive_collisions" },
291 { "tx_late_collisions" },
292 { "tx_collide_2times" },
293 { "tx_collide_3times" },
294 { "tx_collide_4times" },
295 { "tx_collide_5times" },
296 { "tx_collide_6times" },
297 { "tx_collide_7times" },
298 { "tx_collide_8times" },
299 { "tx_collide_9times" },
300 { "tx_collide_10times" },
301 { "tx_collide_11times" },
302 { "tx_collide_12times" },
303 { "tx_collide_13times" },
304 { "tx_collide_14times" },
305 { "tx_collide_15times" },
306 { "tx_ucast_packets" },
307 { "tx_mcast_packets" },
308 { "tx_bcast_packets" },
309 { "tx_carrier_sense_errors" },
313 { "dma_writeq_full" },
314 { "dma_write_prioq_full" },
318 { "rx_threshold_hit" },
320 { "dma_readq_full" },
321 { "dma_read_prioq_full" },
322 { "tx_comp_queue_full" },
324 { "ring_set_send_prod_index" },
325 { "ring_status_update" },
327 { "nic_avoided_irqs" },
328 { "nic_tx_threshold_hit" }
331 static const struct {
332 const char string
[ETH_GSTRING_LEN
];
333 } ethtool_test_keys
[TG3_NUM_TEST
] = {
334 { "nvram test (online) " },
335 { "link test (online) " },
336 { "register test (offline)" },
337 { "memory test (offline)" },
338 { "loopback test (offline)" },
339 { "interrupt test (offline)" },
342 static void tg3_write32(struct tg3
*tp
, u32 off
, u32 val
)
344 writel(val
, tp
->regs
+ off
);
347 static u32
tg3_read32(struct tg3
*tp
, u32 off
)
349 return (readl(tp
->regs
+ off
));
352 static void tg3_ape_write32(struct tg3
*tp
, u32 off
, u32 val
)
354 writel(val
, tp
->aperegs
+ off
);
357 static u32
tg3_ape_read32(struct tg3
*tp
, u32 off
)
359 return (readl(tp
->aperegs
+ off
));
362 static void tg3_write_indirect_reg32(struct tg3
*tp
, u32 off
, u32 val
)
366 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
367 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
368 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
369 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
372 static void tg3_write_flush_reg32(struct tg3
*tp
, u32 off
, u32 val
)
374 writel(val
, tp
->regs
+ off
);
375 readl(tp
->regs
+ off
);
378 static u32
tg3_read_indirect_reg32(struct tg3
*tp
, u32 off
)
383 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
384 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
385 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
386 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
390 static void tg3_write_indirect_mbox(struct tg3
*tp
, u32 off
, u32 val
)
394 if (off
== (MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
)) {
395 pci_write_config_dword(tp
->pdev
, TG3PCI_RCV_RET_RING_CON_IDX
+
396 TG3_64BIT_REG_LOW
, val
);
399 if (off
== (MAILBOX_RCV_STD_PROD_IDX
+ TG3_64BIT_REG_LOW
)) {
400 pci_write_config_dword(tp
->pdev
, TG3PCI_STD_RING_PROD_IDX
+
401 TG3_64BIT_REG_LOW
, val
);
405 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
406 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
407 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
408 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
410 /* In indirect mode when disabling interrupts, we also need
411 * to clear the interrupt bit in the GRC local ctrl register.
413 if ((off
== (MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
)) &&
415 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_LOCAL_CTRL
,
416 tp
->grc_local_ctrl
|GRC_LCLCTRL_CLEARINT
);
420 static u32
tg3_read_indirect_mbox(struct tg3
*tp
, u32 off
)
425 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
426 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
427 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
428 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
432 /* usec_wait specifies the wait time in usec when writing to certain registers
433 * where it is unsafe to read back the register without some delay.
434 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
435 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
437 static void _tw32_flush(struct tg3
*tp
, u32 off
, u32 val
, u32 usec_wait
)
439 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) ||
440 (tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
))
441 /* Non-posted methods */
442 tp
->write32(tp
, off
, val
);
445 tg3_write32(tp
, off
, val
);
450 /* Wait again after the read for the posted method to guarantee that
451 * the wait time is met.
457 static inline void tw32_mailbox_flush(struct tg3
*tp
, u32 off
, u32 val
)
459 tp
->write32_mbox(tp
, off
, val
);
460 if (!(tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
) &&
461 !(tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
))
462 tp
->read32_mbox(tp
, off
);
465 static void tg3_write32_tx_mbox(struct tg3
*tp
, u32 off
, u32 val
)
467 void __iomem
*mbox
= tp
->regs
+ off
;
469 if (tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
)
471 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
475 static u32
tg3_read32_mbox_5906(struct tg3
*tp
, u32 off
)
477 return (readl(tp
->regs
+ off
+ GRCMBOX_BASE
));
480 static void tg3_write32_mbox_5906(struct tg3
*tp
, u32 off
, u32 val
)
482 writel(val
, tp
->regs
+ off
+ GRCMBOX_BASE
);
485 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
486 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
487 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
488 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
489 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
491 #define tw32(reg,val) tp->write32(tp, reg, val)
492 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
493 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
494 #define tr32(reg) tp->read32(tp, reg)
496 static void tg3_write_mem(struct tg3
*tp
, u32 off
, u32 val
)
500 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) &&
501 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
))
504 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
505 if (tp
->tg3_flags
& TG3_FLAG_SRAM_USE_CONFIG
) {
506 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
507 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
509 /* Always leave this as zero. */
510 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
512 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
513 tw32_f(TG3PCI_MEM_WIN_DATA
, val
);
515 /* Always leave this as zero. */
516 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
518 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
521 static void tg3_read_mem(struct tg3
*tp
, u32 off
, u32
*val
)
525 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) &&
526 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
)) {
531 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
532 if (tp
->tg3_flags
& TG3_FLAG_SRAM_USE_CONFIG
) {
533 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
534 pci_read_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
536 /* Always leave this as zero. */
537 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
539 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
540 *val
= tr32(TG3PCI_MEM_WIN_DATA
);
542 /* Always leave this as zero. */
543 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
545 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
548 static void tg3_ape_lock_init(struct tg3
*tp
)
552 /* Make sure the driver hasn't any stale locks. */
553 for (i
= 0; i
< 8; i
++)
554 tg3_ape_write32(tp
, TG3_APE_LOCK_GRANT
+ 4 * i
,
555 APE_LOCK_GRANT_DRIVER
);
558 static int tg3_ape_lock(struct tg3
*tp
, int locknum
)
564 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
568 case TG3_APE_LOCK_GRC
:
569 case TG3_APE_LOCK_MEM
:
577 tg3_ape_write32(tp
, TG3_APE_LOCK_REQ
+ off
, APE_LOCK_REQ_DRIVER
);
579 /* Wait for up to 1 millisecond to acquire lock. */
580 for (i
= 0; i
< 100; i
++) {
581 status
= tg3_ape_read32(tp
, TG3_APE_LOCK_GRANT
+ off
);
582 if (status
== APE_LOCK_GRANT_DRIVER
)
587 if (status
!= APE_LOCK_GRANT_DRIVER
) {
588 /* Revoke the lock request. */
589 tg3_ape_write32(tp
, TG3_APE_LOCK_GRANT
+ off
,
590 APE_LOCK_GRANT_DRIVER
);
598 static void tg3_ape_unlock(struct tg3
*tp
, int locknum
)
602 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
606 case TG3_APE_LOCK_GRC
:
607 case TG3_APE_LOCK_MEM
:
614 tg3_ape_write32(tp
, TG3_APE_LOCK_GRANT
+ off
, APE_LOCK_GRANT_DRIVER
);
617 static void tg3_disable_ints(struct tg3
*tp
)
621 tw32(TG3PCI_MISC_HOST_CTRL
,
622 (tp
->misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
));
623 for (i
= 0; i
< tp
->irq_max
; i
++)
624 tw32_mailbox_f(tp
->napi
[i
].int_mbox
, 0x00000001);
627 static void tg3_enable_ints(struct tg3
*tp
)
635 tw32(TG3PCI_MISC_HOST_CTRL
,
636 (tp
->misc_host_ctrl
& ~MISC_HOST_CTRL_MASK_PCI_INT
));
638 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
639 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
640 tw32_mailbox_f(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
641 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)
642 tw32_mailbox_f(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
644 coal_now
|= tnapi
->coal_now
;
647 /* Force an initial interrupt */
648 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
649 (tp
->napi
[0].hw_status
->status
& SD_STATUS_UPDATED
))
650 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
652 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
653 HOSTCC_MODE_ENABLE
| coal_now
);
656 static inline unsigned int tg3_has_work(struct tg3_napi
*tnapi
)
658 struct tg3
*tp
= tnapi
->tp
;
659 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
660 unsigned int work_exists
= 0;
662 /* check for phy events */
663 if (!(tp
->tg3_flags
&
664 (TG3_FLAG_USE_LINKCHG_REG
|
665 TG3_FLAG_POLL_SERDES
))) {
666 if (sblk
->status
& SD_STATUS_LINK_CHG
)
669 /* check for RX/TX work to do */
670 if (sblk
->idx
[0].tx_consumer
!= tnapi
->tx_cons
||
671 *(tnapi
->rx_rcb_prod_idx
) != tnapi
->rx_rcb_ptr
)
678 * similar to tg3_enable_ints, but it accurately determines whether there
679 * is new work pending and can return without flushing the PIO write
680 * which reenables interrupts
682 static void tg3_int_reenable(struct tg3_napi
*tnapi
)
684 struct tg3
*tp
= tnapi
->tp
;
686 tw32_mailbox(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
689 /* When doing tagged status, this work check is unnecessary.
690 * The last_tag we write above tells the chip which piece of
691 * work we've completed.
693 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
695 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
696 HOSTCC_MODE_ENABLE
| tnapi
->coal_now
);
699 static void tg3_napi_disable(struct tg3
*tp
)
703 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--)
704 napi_disable(&tp
->napi
[i
].napi
);
707 static void tg3_napi_enable(struct tg3
*tp
)
711 for (i
= 0; i
< tp
->irq_cnt
; i
++)
712 napi_enable(&tp
->napi
[i
].napi
);
715 static inline void tg3_netif_stop(struct tg3
*tp
)
717 tp
->dev
->trans_start
= jiffies
; /* prevent tx timeout */
718 tg3_napi_disable(tp
);
719 netif_tx_disable(tp
->dev
);
722 static inline void tg3_netif_start(struct tg3
*tp
)
724 /* NOTE: unconditional netif_tx_wake_all_queues is only
725 * appropriate so long as all callers are assured to
726 * have free tx slots (such as after tg3_init_hw)
728 netif_tx_wake_all_queues(tp
->dev
);
731 tp
->napi
[0].hw_status
->status
|= SD_STATUS_UPDATED
;
735 static void tg3_switch_clocks(struct tg3
*tp
)
740 if ((tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
741 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
744 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
);
746 orig_clock_ctrl
= clock_ctrl
;
747 clock_ctrl
&= (CLOCK_CTRL_FORCE_CLKRUN
|
748 CLOCK_CTRL_CLKRUN_OENABLE
|
750 tp
->pci_clock_ctrl
= clock_ctrl
;
752 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
753 if (orig_clock_ctrl
& CLOCK_CTRL_625_CORE
) {
754 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
755 clock_ctrl
| CLOCK_CTRL_625_CORE
, 40);
757 } else if ((orig_clock_ctrl
& CLOCK_CTRL_44MHZ_CORE
) != 0) {
758 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
760 (CLOCK_CTRL_44MHZ_CORE
| CLOCK_CTRL_ALTCLK
),
762 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
763 clock_ctrl
| (CLOCK_CTRL_ALTCLK
),
766 tw32_wait_f(TG3PCI_CLOCK_CTRL
, clock_ctrl
, 40);
769 #define PHY_BUSY_LOOPS 5000
771 static int tg3_readphy(struct tg3
*tp
, int reg
, u32
*val
)
777 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
779 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
785 frame_val
= ((tp
->phy_addr
<< MI_COM_PHY_ADDR_SHIFT
) &
786 MI_COM_PHY_ADDR_MASK
);
787 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
788 MI_COM_REG_ADDR_MASK
);
789 frame_val
|= (MI_COM_CMD_READ
| MI_COM_START
);
791 tw32_f(MAC_MI_COM
, frame_val
);
793 loops
= PHY_BUSY_LOOPS
;
796 frame_val
= tr32(MAC_MI_COM
);
798 if ((frame_val
& MI_COM_BUSY
) == 0) {
800 frame_val
= tr32(MAC_MI_COM
);
808 *val
= frame_val
& MI_COM_DATA_MASK
;
812 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
813 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
820 static int tg3_writephy(struct tg3
*tp
, int reg
, u32 val
)
826 if ((tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) &&
827 (reg
== MII_TG3_CTRL
|| reg
== MII_TG3_AUX_CTRL
))
830 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
832 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
836 frame_val
= ((tp
->phy_addr
<< MI_COM_PHY_ADDR_SHIFT
) &
837 MI_COM_PHY_ADDR_MASK
);
838 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
839 MI_COM_REG_ADDR_MASK
);
840 frame_val
|= (val
& MI_COM_DATA_MASK
);
841 frame_val
|= (MI_COM_CMD_WRITE
| MI_COM_START
);
843 tw32_f(MAC_MI_COM
, frame_val
);
845 loops
= PHY_BUSY_LOOPS
;
848 frame_val
= tr32(MAC_MI_COM
);
849 if ((frame_val
& MI_COM_BUSY
) == 0) {
851 frame_val
= tr32(MAC_MI_COM
);
861 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
862 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
869 static int tg3_bmcr_reset(struct tg3
*tp
)
874 /* OK, reset it, and poll the BMCR_RESET bit until it
875 * clears or we time out.
877 phy_control
= BMCR_RESET
;
878 err
= tg3_writephy(tp
, MII_BMCR
, phy_control
);
884 err
= tg3_readphy(tp
, MII_BMCR
, &phy_control
);
888 if ((phy_control
& BMCR_RESET
) == 0) {
900 static int tg3_mdio_read(struct mii_bus
*bp
, int mii_id
, int reg
)
902 struct tg3
*tp
= bp
->priv
;
905 spin_lock_bh(&tp
->lock
);
907 if (tg3_readphy(tp
, reg
, &val
))
910 spin_unlock_bh(&tp
->lock
);
915 static int tg3_mdio_write(struct mii_bus
*bp
, int mii_id
, int reg
, u16 val
)
917 struct tg3
*tp
= bp
->priv
;
920 spin_lock_bh(&tp
->lock
);
922 if (tg3_writephy(tp
, reg
, val
))
925 spin_unlock_bh(&tp
->lock
);
930 static int tg3_mdio_reset(struct mii_bus
*bp
)
935 static void tg3_mdio_config_5785(struct tg3
*tp
)
938 struct phy_device
*phydev
;
940 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
941 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
942 case TG3_PHY_ID_BCM50610
:
943 case TG3_PHY_ID_BCM50610M
:
944 val
= MAC_PHYCFG2_50610_LED_MODES
;
946 case TG3_PHY_ID_BCMAC131
:
947 val
= MAC_PHYCFG2_AC131_LED_MODES
;
949 case TG3_PHY_ID_RTL8211C
:
950 val
= MAC_PHYCFG2_RTL8211C_LED_MODES
;
952 case TG3_PHY_ID_RTL8201E
:
953 val
= MAC_PHYCFG2_RTL8201E_LED_MODES
;
959 if (phydev
->interface
!= PHY_INTERFACE_MODE_RGMII
) {
960 tw32(MAC_PHYCFG2
, val
);
962 val
= tr32(MAC_PHYCFG1
);
963 val
&= ~(MAC_PHYCFG1_RGMII_INT
|
964 MAC_PHYCFG1_RXCLK_TO_MASK
| MAC_PHYCFG1_TXCLK_TO_MASK
);
965 val
|= MAC_PHYCFG1_RXCLK_TIMEOUT
| MAC_PHYCFG1_TXCLK_TIMEOUT
;
966 tw32(MAC_PHYCFG1
, val
);
971 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_STD_IBND_DISABLE
))
972 val
|= MAC_PHYCFG2_EMODE_MASK_MASK
|
973 MAC_PHYCFG2_FMODE_MASK_MASK
|
974 MAC_PHYCFG2_GMODE_MASK_MASK
|
975 MAC_PHYCFG2_ACT_MASK_MASK
|
976 MAC_PHYCFG2_QUAL_MASK_MASK
|
977 MAC_PHYCFG2_INBAND_ENABLE
;
979 tw32(MAC_PHYCFG2
, val
);
981 val
= tr32(MAC_PHYCFG1
);
982 val
&= ~(MAC_PHYCFG1_RXCLK_TO_MASK
| MAC_PHYCFG1_TXCLK_TO_MASK
|
983 MAC_PHYCFG1_RGMII_EXT_RX_DEC
| MAC_PHYCFG1_RGMII_SND_STAT_EN
);
984 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_STD_IBND_DISABLE
)) {
985 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
986 val
|= MAC_PHYCFG1_RGMII_EXT_RX_DEC
;
987 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
988 val
|= MAC_PHYCFG1_RGMII_SND_STAT_EN
;
990 val
|= MAC_PHYCFG1_RXCLK_TIMEOUT
| MAC_PHYCFG1_TXCLK_TIMEOUT
|
991 MAC_PHYCFG1_RGMII_INT
| MAC_PHYCFG1_TXC_DRV
;
992 tw32(MAC_PHYCFG1
, val
);
994 val
= tr32(MAC_EXT_RGMII_MODE
);
995 val
&= ~(MAC_RGMII_MODE_RX_INT_B
|
996 MAC_RGMII_MODE_RX_QUALITY
|
997 MAC_RGMII_MODE_RX_ACTIVITY
|
998 MAC_RGMII_MODE_RX_ENG_DET
|
999 MAC_RGMII_MODE_TX_ENABLE
|
1000 MAC_RGMII_MODE_TX_LOWPWR
|
1001 MAC_RGMII_MODE_TX_RESET
);
1002 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_STD_IBND_DISABLE
)) {
1003 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1004 val
|= MAC_RGMII_MODE_RX_INT_B
|
1005 MAC_RGMII_MODE_RX_QUALITY
|
1006 MAC_RGMII_MODE_RX_ACTIVITY
|
1007 MAC_RGMII_MODE_RX_ENG_DET
;
1008 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1009 val
|= MAC_RGMII_MODE_TX_ENABLE
|
1010 MAC_RGMII_MODE_TX_LOWPWR
|
1011 MAC_RGMII_MODE_TX_RESET
;
1013 tw32(MAC_EXT_RGMII_MODE
, val
);
1016 static void tg3_mdio_start(struct tg3
*tp
)
1018 tp
->mi_mode
&= ~MAC_MI_MODE_AUTO_POLL
;
1019 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
1022 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
) {
1023 u32 funcnum
, is_serdes
;
1025 funcnum
= tr32(TG3_CPMU_STATUS
) & TG3_CPMU_STATUS_PCIE_FUNC
;
1031 is_serdes
= tr32(SG_DIG_STATUS
) & SG_DIG_IS_SERDES
;
1035 tp
->phy_addr
= TG3_PHY_MII_ADDR
;
1037 if ((tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) &&
1038 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
1039 tg3_mdio_config_5785(tp
);
1042 static int tg3_mdio_init(struct tg3
*tp
)
1046 struct phy_device
*phydev
;
1050 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) ||
1051 (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
))
1054 tp
->mdio_bus
= mdiobus_alloc();
1055 if (tp
->mdio_bus
== NULL
)
1058 tp
->mdio_bus
->name
= "tg3 mdio bus";
1059 snprintf(tp
->mdio_bus
->id
, MII_BUS_ID_SIZE
, "%x",
1060 (tp
->pdev
->bus
->number
<< 8) | tp
->pdev
->devfn
);
1061 tp
->mdio_bus
->priv
= tp
;
1062 tp
->mdio_bus
->parent
= &tp
->pdev
->dev
;
1063 tp
->mdio_bus
->read
= &tg3_mdio_read
;
1064 tp
->mdio_bus
->write
= &tg3_mdio_write
;
1065 tp
->mdio_bus
->reset
= &tg3_mdio_reset
;
1066 tp
->mdio_bus
->phy_mask
= ~(1 << TG3_PHY_MII_ADDR
);
1067 tp
->mdio_bus
->irq
= &tp
->mdio_irq
[0];
1069 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
1070 tp
->mdio_bus
->irq
[i
] = PHY_POLL
;
1072 /* The bus registration will look for all the PHYs on the mdio bus.
1073 * Unfortunately, it does not ensure the PHY is powered up before
1074 * accessing the PHY ID registers. A chip reset is the
1075 * quickest way to bring the device back to an operational state..
1077 if (tg3_readphy(tp
, MII_BMCR
, ®
) || (reg
& BMCR_PDOWN
))
1080 i
= mdiobus_register(tp
->mdio_bus
);
1082 printk(KERN_WARNING
"%s: mdiobus_reg failed (0x%x)\n",
1084 mdiobus_free(tp
->mdio_bus
);
1088 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1090 if (!phydev
|| !phydev
->drv
) {
1091 printk(KERN_WARNING
"%s: No PHY devices\n", tp
->dev
->name
);
1092 mdiobus_unregister(tp
->mdio_bus
);
1093 mdiobus_free(tp
->mdio_bus
);
1097 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
1098 case TG3_PHY_ID_BCM57780
:
1099 phydev
->interface
= PHY_INTERFACE_MODE_GMII
;
1100 phydev
->dev_flags
|= PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1102 case TG3_PHY_ID_BCM50610
:
1103 case TG3_PHY_ID_BCM50610M
:
1104 phydev
->dev_flags
|= PHY_BRCM_CLEAR_RGMII_MODE
|
1105 PHY_BRCM_RX_REFCLK_UNUSED
|
1106 PHY_BRCM_DIS_TXCRXC_NOENRGY
|
1107 PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1108 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_STD_IBND_DISABLE
)
1109 phydev
->dev_flags
|= PHY_BRCM_STD_IBND_DISABLE
;
1110 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1111 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_RX_ENABLE
;
1112 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1113 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_TX_ENABLE
;
1115 case TG3_PHY_ID_RTL8211C
:
1116 phydev
->interface
= PHY_INTERFACE_MODE_RGMII
;
1118 case TG3_PHY_ID_RTL8201E
:
1119 case TG3_PHY_ID_BCMAC131
:
1120 phydev
->interface
= PHY_INTERFACE_MODE_MII
;
1121 phydev
->dev_flags
|= PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1122 tp
->tg3_flags3
|= TG3_FLG3_PHY_IS_FET
;
1126 tp
->tg3_flags3
|= TG3_FLG3_MDIOBUS_INITED
;
1128 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
1129 tg3_mdio_config_5785(tp
);
1134 static void tg3_mdio_fini(struct tg3
*tp
)
1136 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) {
1137 tp
->tg3_flags3
&= ~TG3_FLG3_MDIOBUS_INITED
;
1138 mdiobus_unregister(tp
->mdio_bus
);
1139 mdiobus_free(tp
->mdio_bus
);
1143 /* tp->lock is held. */
1144 static inline void tg3_generate_fw_event(struct tg3
*tp
)
1148 val
= tr32(GRC_RX_CPU_EVENT
);
1149 val
|= GRC_RX_CPU_DRIVER_EVENT
;
1150 tw32_f(GRC_RX_CPU_EVENT
, val
);
1152 tp
->last_event_jiffies
= jiffies
;
1155 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1157 /* tp->lock is held. */
1158 static void tg3_wait_for_event_ack(struct tg3
*tp
)
1161 unsigned int delay_cnt
;
1164 /* If enough time has passed, no wait is necessary. */
1165 time_remain
= (long)(tp
->last_event_jiffies
+ 1 +
1166 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC
)) -
1168 if (time_remain
< 0)
1171 /* Check if we can shorten the wait time. */
1172 delay_cnt
= jiffies_to_usecs(time_remain
);
1173 if (delay_cnt
> TG3_FW_EVENT_TIMEOUT_USEC
)
1174 delay_cnt
= TG3_FW_EVENT_TIMEOUT_USEC
;
1175 delay_cnt
= (delay_cnt
>> 3) + 1;
1177 for (i
= 0; i
< delay_cnt
; i
++) {
1178 if (!(tr32(GRC_RX_CPU_EVENT
) & GRC_RX_CPU_DRIVER_EVENT
))
1184 /* tp->lock is held. */
1185 static void tg3_ump_link_report(struct tg3
*tp
)
1190 if (!(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
1191 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
1194 tg3_wait_for_event_ack(tp
);
1196 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_LINK_UPDATE
);
1198 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 14);
1201 if (!tg3_readphy(tp
, MII_BMCR
, ®
))
1203 if (!tg3_readphy(tp
, MII_BMSR
, ®
))
1204 val
|= (reg
& 0xffff);
1205 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
, val
);
1208 if (!tg3_readphy(tp
, MII_ADVERTISE
, ®
))
1210 if (!tg3_readphy(tp
, MII_LPA
, ®
))
1211 val
|= (reg
& 0xffff);
1212 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 4, val
);
1215 if (!(tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)) {
1216 if (!tg3_readphy(tp
, MII_CTRL1000
, ®
))
1218 if (!tg3_readphy(tp
, MII_STAT1000
, ®
))
1219 val
|= (reg
& 0xffff);
1221 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 8, val
);
1223 if (!tg3_readphy(tp
, MII_PHYADDR
, ®
))
1227 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 12, val
);
1229 tg3_generate_fw_event(tp
);
1232 static void tg3_link_report(struct tg3
*tp
)
1234 if (!netif_carrier_ok(tp
->dev
)) {
1235 if (netif_msg_link(tp
))
1236 printk(KERN_INFO PFX
"%s: Link is down.\n",
1238 tg3_ump_link_report(tp
);
1239 } else if (netif_msg_link(tp
)) {
1240 printk(KERN_INFO PFX
"%s: Link is up at %d Mbps, %s duplex.\n",
1242 (tp
->link_config
.active_speed
== SPEED_1000
?
1244 (tp
->link_config
.active_speed
== SPEED_100
?
1246 (tp
->link_config
.active_duplex
== DUPLEX_FULL
?
1249 printk(KERN_INFO PFX
1250 "%s: Flow control is %s for TX and %s for RX.\n",
1252 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
) ?
1254 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
) ?
1256 tg3_ump_link_report(tp
);
1260 static u16
tg3_advert_flowctrl_1000T(u8 flow_ctrl
)
1264 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1265 miireg
= ADVERTISE_PAUSE_CAP
;
1266 else if (flow_ctrl
& FLOW_CTRL_TX
)
1267 miireg
= ADVERTISE_PAUSE_ASYM
;
1268 else if (flow_ctrl
& FLOW_CTRL_RX
)
1269 miireg
= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1276 static u16
tg3_advert_flowctrl_1000X(u8 flow_ctrl
)
1280 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1281 miireg
= ADVERTISE_1000XPAUSE
;
1282 else if (flow_ctrl
& FLOW_CTRL_TX
)
1283 miireg
= ADVERTISE_1000XPSE_ASYM
;
1284 else if (flow_ctrl
& FLOW_CTRL_RX
)
1285 miireg
= ADVERTISE_1000XPAUSE
| ADVERTISE_1000XPSE_ASYM
;
1292 static u8
tg3_resolve_flowctrl_1000X(u16 lcladv
, u16 rmtadv
)
1296 if (lcladv
& ADVERTISE_1000XPAUSE
) {
1297 if (lcladv
& ADVERTISE_1000XPSE_ASYM
) {
1298 if (rmtadv
& LPA_1000XPAUSE
)
1299 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1300 else if (rmtadv
& LPA_1000XPAUSE_ASYM
)
1303 if (rmtadv
& LPA_1000XPAUSE
)
1304 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1306 } else if (lcladv
& ADVERTISE_1000XPSE_ASYM
) {
1307 if ((rmtadv
& LPA_1000XPAUSE
) && (rmtadv
& LPA_1000XPAUSE_ASYM
))
1314 static void tg3_setup_flow_control(struct tg3
*tp
, u32 lcladv
, u32 rmtadv
)
1318 u32 old_rx_mode
= tp
->rx_mode
;
1319 u32 old_tx_mode
= tp
->tx_mode
;
1321 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)
1322 autoneg
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]->autoneg
;
1324 autoneg
= tp
->link_config
.autoneg
;
1326 if (autoneg
== AUTONEG_ENABLE
&&
1327 (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
)) {
1328 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)
1329 flowctrl
= tg3_resolve_flowctrl_1000X(lcladv
, rmtadv
);
1331 flowctrl
= mii_resolve_flowctrl_fdx(lcladv
, rmtadv
);
1333 flowctrl
= tp
->link_config
.flowctrl
;
1335 tp
->link_config
.active_flowctrl
= flowctrl
;
1337 if (flowctrl
& FLOW_CTRL_RX
)
1338 tp
->rx_mode
|= RX_MODE_FLOW_CTRL_ENABLE
;
1340 tp
->rx_mode
&= ~RX_MODE_FLOW_CTRL_ENABLE
;
1342 if (old_rx_mode
!= tp
->rx_mode
)
1343 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
1345 if (flowctrl
& FLOW_CTRL_TX
)
1346 tp
->tx_mode
|= TX_MODE_FLOW_CTRL_ENABLE
;
1348 tp
->tx_mode
&= ~TX_MODE_FLOW_CTRL_ENABLE
;
1350 if (old_tx_mode
!= tp
->tx_mode
)
1351 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
1354 static void tg3_adjust_link(struct net_device
*dev
)
1356 u8 oldflowctrl
, linkmesg
= 0;
1357 u32 mac_mode
, lcl_adv
, rmt_adv
;
1358 struct tg3
*tp
= netdev_priv(dev
);
1359 struct phy_device
*phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1361 spin_lock_bh(&tp
->lock
);
1363 mac_mode
= tp
->mac_mode
& ~(MAC_MODE_PORT_MODE_MASK
|
1364 MAC_MODE_HALF_DUPLEX
);
1366 oldflowctrl
= tp
->link_config
.active_flowctrl
;
1372 if (phydev
->speed
== SPEED_100
|| phydev
->speed
== SPEED_10
)
1373 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
1374 else if (phydev
->speed
== SPEED_1000
||
1375 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
)
1376 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1378 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
1380 if (phydev
->duplex
== DUPLEX_HALF
)
1381 mac_mode
|= MAC_MODE_HALF_DUPLEX
;
1383 lcl_adv
= tg3_advert_flowctrl_1000T(
1384 tp
->link_config
.flowctrl
);
1387 rmt_adv
= LPA_PAUSE_CAP
;
1388 if (phydev
->asym_pause
)
1389 rmt_adv
|= LPA_PAUSE_ASYM
;
1392 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
1394 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1396 if (mac_mode
!= tp
->mac_mode
) {
1397 tp
->mac_mode
= mac_mode
;
1398 tw32_f(MAC_MODE
, tp
->mac_mode
);
1402 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
) {
1403 if (phydev
->speed
== SPEED_10
)
1405 MAC_MI_STAT_10MBPS_MODE
|
1406 MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
1408 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
1411 if (phydev
->speed
== SPEED_1000
&& phydev
->duplex
== DUPLEX_HALF
)
1412 tw32(MAC_TX_LENGTHS
,
1413 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
1414 (6 << TX_LENGTHS_IPG_SHIFT
) |
1415 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
1417 tw32(MAC_TX_LENGTHS
,
1418 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
1419 (6 << TX_LENGTHS_IPG_SHIFT
) |
1420 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
1422 if ((phydev
->link
&& tp
->link_config
.active_speed
== SPEED_INVALID
) ||
1423 (!phydev
->link
&& tp
->link_config
.active_speed
!= SPEED_INVALID
) ||
1424 phydev
->speed
!= tp
->link_config
.active_speed
||
1425 phydev
->duplex
!= tp
->link_config
.active_duplex
||
1426 oldflowctrl
!= tp
->link_config
.active_flowctrl
)
1429 tp
->link_config
.active_speed
= phydev
->speed
;
1430 tp
->link_config
.active_duplex
= phydev
->duplex
;
1432 spin_unlock_bh(&tp
->lock
);
1435 tg3_link_report(tp
);
1438 static int tg3_phy_init(struct tg3
*tp
)
1440 struct phy_device
*phydev
;
1442 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
)
1445 /* Bring the PHY back to a known state. */
1448 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1450 /* Attach the MAC to the PHY. */
1451 phydev
= phy_connect(tp
->dev
, dev_name(&phydev
->dev
), tg3_adjust_link
,
1452 phydev
->dev_flags
, phydev
->interface
);
1453 if (IS_ERR(phydev
)) {
1454 printk(KERN_ERR
"%s: Could not attach to PHY\n", tp
->dev
->name
);
1455 return PTR_ERR(phydev
);
1458 /* Mask with MAC supported features. */
1459 switch (phydev
->interface
) {
1460 case PHY_INTERFACE_MODE_GMII
:
1461 case PHY_INTERFACE_MODE_RGMII
:
1462 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
1463 phydev
->supported
&= (PHY_GBIT_FEATURES
|
1465 SUPPORTED_Asym_Pause
);
1469 case PHY_INTERFACE_MODE_MII
:
1470 phydev
->supported
&= (PHY_BASIC_FEATURES
|
1472 SUPPORTED_Asym_Pause
);
1475 phy_disconnect(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
1479 tp
->tg3_flags3
|= TG3_FLG3_PHY_CONNECTED
;
1481 phydev
->advertising
= phydev
->supported
;
1486 static void tg3_phy_start(struct tg3
*tp
)
1488 struct phy_device
*phydev
;
1490 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
1493 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1495 if (tp
->link_config
.phy_is_low_power
) {
1496 tp
->link_config
.phy_is_low_power
= 0;
1497 phydev
->speed
= tp
->link_config
.orig_speed
;
1498 phydev
->duplex
= tp
->link_config
.orig_duplex
;
1499 phydev
->autoneg
= tp
->link_config
.orig_autoneg
;
1500 phydev
->advertising
= tp
->link_config
.orig_advertising
;
1505 phy_start_aneg(phydev
);
1508 static void tg3_phy_stop(struct tg3
*tp
)
1510 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
1513 phy_stop(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
1516 static void tg3_phy_fini(struct tg3
*tp
)
1518 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) {
1519 phy_disconnect(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
1520 tp
->tg3_flags3
&= ~TG3_FLG3_PHY_CONNECTED
;
1524 static void tg3_phydsp_write(struct tg3
*tp
, u32 reg
, u32 val
)
1526 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, reg
);
1527 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, val
);
1530 static void tg3_phy_fet_toggle_apd(struct tg3
*tp
, bool enable
)
1534 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &phytest
)) {
1537 tg3_writephy(tp
, MII_TG3_FET_TEST
,
1538 phytest
| MII_TG3_FET_SHADOW_EN
);
1539 if (!tg3_readphy(tp
, MII_TG3_FET_SHDW_AUXSTAT2
, &phy
)) {
1541 phy
|= MII_TG3_FET_SHDW_AUXSTAT2_APD
;
1543 phy
&= ~MII_TG3_FET_SHDW_AUXSTAT2_APD
;
1544 tg3_writephy(tp
, MII_TG3_FET_SHDW_AUXSTAT2
, phy
);
1546 tg3_writephy(tp
, MII_TG3_FET_TEST
, phytest
);
1550 static void tg3_phy_toggle_apd(struct tg3
*tp
, bool enable
)
1554 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
1557 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
1558 tg3_phy_fet_toggle_apd(tp
, enable
);
1562 reg
= MII_TG3_MISC_SHDW_WREN
|
1563 MII_TG3_MISC_SHDW_SCR5_SEL
|
1564 MII_TG3_MISC_SHDW_SCR5_LPED
|
1565 MII_TG3_MISC_SHDW_SCR5_DLPTLM
|
1566 MII_TG3_MISC_SHDW_SCR5_SDTL
|
1567 MII_TG3_MISC_SHDW_SCR5_C125OE
;
1568 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5784
|| !enable
)
1569 reg
|= MII_TG3_MISC_SHDW_SCR5_DLLAPD
;
1571 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
1574 reg
= MII_TG3_MISC_SHDW_WREN
|
1575 MII_TG3_MISC_SHDW_APD_SEL
|
1576 MII_TG3_MISC_SHDW_APD_WKTM_84MS
;
1578 reg
|= MII_TG3_MISC_SHDW_APD_ENABLE
;
1580 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
1583 static void tg3_phy_toggle_automdix(struct tg3
*tp
, int enable
)
1587 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
1588 (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
))
1591 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
1594 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &ephy
)) {
1595 u32 reg
= MII_TG3_FET_SHDW_MISCCTRL
;
1597 tg3_writephy(tp
, MII_TG3_FET_TEST
,
1598 ephy
| MII_TG3_FET_SHADOW_EN
);
1599 if (!tg3_readphy(tp
, reg
, &phy
)) {
1601 phy
|= MII_TG3_FET_SHDW_MISCCTRL_MDIX
;
1603 phy
&= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX
;
1604 tg3_writephy(tp
, reg
, phy
);
1606 tg3_writephy(tp
, MII_TG3_FET_TEST
, ephy
);
1609 phy
= MII_TG3_AUXCTL_MISC_RDSEL_MISC
|
1610 MII_TG3_AUXCTL_SHDWSEL_MISC
;
1611 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
) &&
1612 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &phy
)) {
1614 phy
|= MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
1616 phy
&= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
1617 phy
|= MII_TG3_AUXCTL_MISC_WREN
;
1618 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1623 static void tg3_phy_set_wirespeed(struct tg3
*tp
)
1627 if (tp
->tg3_flags2
& TG3_FLG2_NO_ETH_WIRE_SPEED
)
1630 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x7007) &&
1631 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
))
1632 tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
1633 (val
| (1 << 15) | (1 << 4)));
1636 static void tg3_phy_apply_otp(struct tg3
*tp
)
1645 /* Enable SM_DSP clock and tx 6dB coding. */
1646 phy
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1647 MII_TG3_AUXCTL_ACTL_SMDSP_ENA
|
1648 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1649 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1651 phy
= ((otp
& TG3_OTP_AGCTGT_MASK
) >> TG3_OTP_AGCTGT_SHIFT
);
1652 phy
|= MII_TG3_DSP_TAP1_AGCTGT_DFLT
;
1653 tg3_phydsp_write(tp
, MII_TG3_DSP_TAP1
, phy
);
1655 phy
= ((otp
& TG3_OTP_HPFFLTR_MASK
) >> TG3_OTP_HPFFLTR_SHIFT
) |
1656 ((otp
& TG3_OTP_HPFOVER_MASK
) >> TG3_OTP_HPFOVER_SHIFT
);
1657 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH0
, phy
);
1659 phy
= ((otp
& TG3_OTP_LPFDIS_MASK
) >> TG3_OTP_LPFDIS_SHIFT
);
1660 phy
|= MII_TG3_DSP_AADJ1CH3_ADCCKADJ
;
1661 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH3
, phy
);
1663 phy
= ((otp
& TG3_OTP_VDAC_MASK
) >> TG3_OTP_VDAC_SHIFT
);
1664 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP75
, phy
);
1666 phy
= ((otp
& TG3_OTP_10BTAMP_MASK
) >> TG3_OTP_10BTAMP_SHIFT
);
1667 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP96
, phy
);
1669 phy
= ((otp
& TG3_OTP_ROFF_MASK
) >> TG3_OTP_ROFF_SHIFT
) |
1670 ((otp
& TG3_OTP_RCOFF_MASK
) >> TG3_OTP_RCOFF_SHIFT
);
1671 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP97
, phy
);
1673 /* Turn off SM_DSP clock. */
1674 phy
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1675 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1676 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1679 static int tg3_wait_macro_done(struct tg3
*tp
)
1686 if (!tg3_readphy(tp
, 0x16, &tmp32
)) {
1687 if ((tmp32
& 0x1000) == 0)
1697 static int tg3_phy_write_and_check_testpat(struct tg3
*tp
, int *resetp
)
1699 static const u32 test_pat
[4][6] = {
1700 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1701 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1702 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1703 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1707 for (chan
= 0; chan
< 4; chan
++) {
1710 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1711 (chan
* 0x2000) | 0x0200);
1712 tg3_writephy(tp
, 0x16, 0x0002);
1714 for (i
= 0; i
< 6; i
++)
1715 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
,
1718 tg3_writephy(tp
, 0x16, 0x0202);
1719 if (tg3_wait_macro_done(tp
)) {
1724 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1725 (chan
* 0x2000) | 0x0200);
1726 tg3_writephy(tp
, 0x16, 0x0082);
1727 if (tg3_wait_macro_done(tp
)) {
1732 tg3_writephy(tp
, 0x16, 0x0802);
1733 if (tg3_wait_macro_done(tp
)) {
1738 for (i
= 0; i
< 6; i
+= 2) {
1741 if (tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &low
) ||
1742 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &high
) ||
1743 tg3_wait_macro_done(tp
)) {
1749 if (low
!= test_pat
[chan
][i
] ||
1750 high
!= test_pat
[chan
][i
+1]) {
1751 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000b);
1752 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4001);
1753 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4005);
1763 static int tg3_phy_reset_chanpat(struct tg3
*tp
)
1767 for (chan
= 0; chan
< 4; chan
++) {
1770 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1771 (chan
* 0x2000) | 0x0200);
1772 tg3_writephy(tp
, 0x16, 0x0002);
1773 for (i
= 0; i
< 6; i
++)
1774 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x000);
1775 tg3_writephy(tp
, 0x16, 0x0202);
1776 if (tg3_wait_macro_done(tp
))
1783 static int tg3_phy_reset_5703_4_5(struct tg3
*tp
)
1785 u32 reg32
, phy9_orig
;
1786 int retries
, do_phy_reset
, err
;
1792 err
= tg3_bmcr_reset(tp
);
1798 /* Disable transmitter and interrupt. */
1799 if (tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
))
1803 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
1805 /* Set full-duplex, 1000 mbps. */
1806 tg3_writephy(tp
, MII_BMCR
,
1807 BMCR_FULLDPLX
| TG3_BMCR_SPEED1000
);
1809 /* Set to master mode. */
1810 if (tg3_readphy(tp
, MII_TG3_CTRL
, &phy9_orig
))
1813 tg3_writephy(tp
, MII_TG3_CTRL
,
1814 (MII_TG3_CTRL_AS_MASTER
|
1815 MII_TG3_CTRL_ENABLE_AS_MASTER
));
1817 /* Enable SM_DSP_CLOCK and 6dB. */
1818 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1820 /* Block the PHY control access. */
1821 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8005);
1822 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0800);
1824 err
= tg3_phy_write_and_check_testpat(tp
, &do_phy_reset
);
1827 } while (--retries
);
1829 err
= tg3_phy_reset_chanpat(tp
);
1833 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8005);
1834 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0000);
1836 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8200);
1837 tg3_writephy(tp
, 0x16, 0x0000);
1839 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
1840 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
1841 /* Set Extended packet length bit for jumbo frames */
1842 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4400);
1845 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1848 tg3_writephy(tp
, MII_TG3_CTRL
, phy9_orig
);
1850 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
)) {
1852 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
1859 /* This will reset the tigon3 PHY if there is no valid
1860 * link unless the FORCE argument is non-zero.
1862 static int tg3_phy_reset(struct tg3
*tp
)
1868 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
1871 val
= tr32(GRC_MISC_CFG
);
1872 tw32_f(GRC_MISC_CFG
, val
& ~GRC_MISC_CFG_EPHY_IDDQ
);
1875 err
= tg3_readphy(tp
, MII_BMSR
, &phy_status
);
1876 err
|= tg3_readphy(tp
, MII_BMSR
, &phy_status
);
1880 if (netif_running(tp
->dev
) && netif_carrier_ok(tp
->dev
)) {
1881 netif_carrier_off(tp
->dev
);
1882 tg3_link_report(tp
);
1885 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
1886 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
1887 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
1888 err
= tg3_phy_reset_5703_4_5(tp
);
1895 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
1896 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) {
1897 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
1898 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
)
1900 cpmuctrl
& ~CPMU_CTRL_GPHY_10MB_RXONLY
);
1903 err
= tg3_bmcr_reset(tp
);
1907 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
) {
1910 phy
= MII_TG3_DSP_EXP8_AEDW
| MII_TG3_DSP_EXP8_REJ2MHz
;
1911 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP8
, phy
);
1913 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
1916 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
||
1917 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5761_AX
) {
1920 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
1921 if ((val
& CPMU_LSPD_1000MB_MACCLK_MASK
) ==
1922 CPMU_LSPD_1000MB_MACCLK_12_5
) {
1923 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
1925 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
1929 tg3_phy_apply_otp(tp
);
1931 if (tp
->tg3_flags3
& TG3_FLG3_PHY_ENABLE_APD
)
1932 tg3_phy_toggle_apd(tp
, true);
1934 tg3_phy_toggle_apd(tp
, false);
1937 if (tp
->tg3_flags2
& TG3_FLG2_PHY_ADC_BUG
) {
1938 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1939 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
1940 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x2aaa);
1941 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
1942 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0323);
1943 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1945 if (tp
->tg3_flags2
& TG3_FLG2_PHY_5704_A0_BUG
) {
1946 tg3_writephy(tp
, 0x1c, 0x8d68);
1947 tg3_writephy(tp
, 0x1c, 0x8d68);
1949 if (tp
->tg3_flags2
& TG3_FLG2_PHY_BER_BUG
) {
1950 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1951 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
1952 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x310b);
1953 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
1954 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x9506);
1955 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x401f);
1956 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x14e2);
1957 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1959 else if (tp
->tg3_flags2
& TG3_FLG2_PHY_JITTER_BUG
) {
1960 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1961 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
1962 if (tp
->tg3_flags2
& TG3_FLG2_PHY_ADJUST_TRIM
) {
1963 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x110b);
1964 tg3_writephy(tp
, MII_TG3_TEST1
,
1965 MII_TG3_TEST1_TRIM_EN
| 0x4);
1967 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x010b);
1968 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1970 /* Set Extended packet length bit (bit 14) on all chips that */
1971 /* support jumbo frames */
1972 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
) {
1973 /* Cannot do read-modify-write on 5401 */
1974 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
1975 } else if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
1978 /* Set bit 14 with read-modify-write to preserve other bits */
1979 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0007) &&
1980 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &phy_reg
))
1981 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy_reg
| 0x4000);
1984 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1985 * jumbo frames transmission.
1987 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
1990 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, &phy_reg
))
1991 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
1992 phy_reg
| MII_TG3_EXT_CTRL_FIFO_ELASTIC
);
1995 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
1996 /* adjust output voltage */
1997 tg3_writephy(tp
, MII_TG3_FET_PTEST
, 0x12);
2000 tg3_phy_toggle_automdix(tp
, 1);
2001 tg3_phy_set_wirespeed(tp
);
2005 static void tg3_frob_aux_power(struct tg3
*tp
)
2007 struct tg3
*tp_peer
= tp
;
2009 if ((tp
->tg3_flags2
& TG3_FLG2_IS_NIC
) == 0)
2012 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2013 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
||
2014 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
) {
2015 struct net_device
*dev_peer
;
2017 dev_peer
= pci_get_drvdata(tp
->pdev_peer
);
2018 /* remove_one() may have been run on the peer. */
2022 tp_peer
= netdev_priv(dev_peer
);
2025 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) != 0 ||
2026 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0 ||
2027 (tp_peer
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) != 0 ||
2028 (tp_peer
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0) {
2029 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2030 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2031 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2032 (GRC_LCLCTRL_GPIO_OE0
|
2033 GRC_LCLCTRL_GPIO_OE1
|
2034 GRC_LCLCTRL_GPIO_OE2
|
2035 GRC_LCLCTRL_GPIO_OUTPUT0
|
2036 GRC_LCLCTRL_GPIO_OUTPUT1
),
2038 } else if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
2039 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
) {
2040 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2041 u32 grc_local_ctrl
= GRC_LCLCTRL_GPIO_OE0
|
2042 GRC_LCLCTRL_GPIO_OE1
|
2043 GRC_LCLCTRL_GPIO_OE2
|
2044 GRC_LCLCTRL_GPIO_OUTPUT0
|
2045 GRC_LCLCTRL_GPIO_OUTPUT1
|
2047 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2049 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT2
;
2050 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2052 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT0
;
2053 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2056 u32 grc_local_ctrl
= 0;
2058 if (tp_peer
!= tp
&&
2059 (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) != 0)
2062 /* Workaround to prevent overdrawing Amps. */
2063 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
2065 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
2066 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2067 grc_local_ctrl
, 100);
2070 /* On 5753 and variants, GPIO2 cannot be used. */
2071 no_gpio2
= tp
->nic_sram_data_cfg
&
2072 NIC_SRAM_DATA_CFG_NO_GPIO2
;
2074 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
2075 GRC_LCLCTRL_GPIO_OE1
|
2076 GRC_LCLCTRL_GPIO_OE2
|
2077 GRC_LCLCTRL_GPIO_OUTPUT1
|
2078 GRC_LCLCTRL_GPIO_OUTPUT2
;
2080 grc_local_ctrl
&= ~(GRC_LCLCTRL_GPIO_OE2
|
2081 GRC_LCLCTRL_GPIO_OUTPUT2
);
2083 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2084 grc_local_ctrl
, 100);
2086 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT0
;
2088 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2089 grc_local_ctrl
, 100);
2092 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT2
;
2093 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2094 grc_local_ctrl
, 100);
2098 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
2099 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
2100 if (tp_peer
!= tp
&&
2101 (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) != 0)
2104 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2105 (GRC_LCLCTRL_GPIO_OE1
|
2106 GRC_LCLCTRL_GPIO_OUTPUT1
), 100);
2108 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2109 GRC_LCLCTRL_GPIO_OE1
, 100);
2111 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2112 (GRC_LCLCTRL_GPIO_OE1
|
2113 GRC_LCLCTRL_GPIO_OUTPUT1
), 100);
2118 static int tg3_5700_link_polarity(struct tg3
*tp
, u32 speed
)
2120 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_2
)
2122 else if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5411
) {
2123 if (speed
!= SPEED_10
)
2125 } else if (speed
== SPEED_10
)
2131 static int tg3_setup_phy(struct tg3
*, int);
2133 #define RESET_KIND_SHUTDOWN 0
2134 #define RESET_KIND_INIT 1
2135 #define RESET_KIND_SUSPEND 2
2137 static void tg3_write_sig_post_reset(struct tg3
*, int);
2138 static int tg3_halt_cpu(struct tg3
*, u32
);
2140 static void tg3_power_down_phy(struct tg3
*tp
, bool do_low_power
)
2144 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
2145 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
2146 u32 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
2147 u32 serdes_cfg
= tr32(MAC_SERDES_CFG
);
2150 SG_DIG_USING_HW_AUTONEG
| SG_DIG_SOFT_RESET
;
2151 tw32(SG_DIG_CTRL
, sg_dig_ctrl
);
2152 tw32(MAC_SERDES_CFG
, serdes_cfg
| (1 << 15));
2157 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2159 val
= tr32(GRC_MISC_CFG
);
2160 tw32_f(GRC_MISC_CFG
, val
| GRC_MISC_CFG_EPHY_IDDQ
);
2163 } else if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
2165 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &phytest
)) {
2168 tg3_writephy(tp
, MII_ADVERTISE
, 0);
2169 tg3_writephy(tp
, MII_BMCR
,
2170 BMCR_ANENABLE
| BMCR_ANRESTART
);
2172 tg3_writephy(tp
, MII_TG3_FET_TEST
,
2173 phytest
| MII_TG3_FET_SHADOW_EN
);
2174 if (!tg3_readphy(tp
, MII_TG3_FET_SHDW_AUXMODE4
, &phy
)) {
2175 phy
|= MII_TG3_FET_SHDW_AUXMODE4_SBPD
;
2177 MII_TG3_FET_SHDW_AUXMODE4
,
2180 tg3_writephy(tp
, MII_TG3_FET_TEST
, phytest
);
2183 } else if (do_low_power
) {
2184 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
2185 MII_TG3_EXT_CTRL_FORCE_LED_OFF
);
2187 tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
2188 MII_TG3_AUXCTL_SHDWSEL_PWRCTL
|
2189 MII_TG3_AUXCTL_PCTL_100TX_LPWR
|
2190 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE
|
2191 MII_TG3_AUXCTL_PCTL_VREG_11V
);
2194 /* The PHY should not be powered down on some chips because
2197 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2198 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2199 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
&&
2200 (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)))
2203 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
||
2204 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5761_AX
) {
2205 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
2206 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
2207 val
|= CPMU_LSPD_1000MB_MACCLK_12_5
;
2208 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
2211 tg3_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
2214 /* tp->lock is held. */
2215 static int tg3_nvram_lock(struct tg3
*tp
)
2217 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
2220 if (tp
->nvram_lock_cnt
== 0) {
2221 tw32(NVRAM_SWARB
, SWARB_REQ_SET1
);
2222 for (i
= 0; i
< 8000; i
++) {
2223 if (tr32(NVRAM_SWARB
) & SWARB_GNT1
)
2228 tw32(NVRAM_SWARB
, SWARB_REQ_CLR1
);
2232 tp
->nvram_lock_cnt
++;
2237 /* tp->lock is held. */
2238 static void tg3_nvram_unlock(struct tg3
*tp
)
2240 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
2241 if (tp
->nvram_lock_cnt
> 0)
2242 tp
->nvram_lock_cnt
--;
2243 if (tp
->nvram_lock_cnt
== 0)
2244 tw32_f(NVRAM_SWARB
, SWARB_REQ_CLR1
);
2248 /* tp->lock is held. */
2249 static void tg3_enable_nvram_access(struct tg3
*tp
)
2251 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2252 !(tp
->tg3_flags2
& TG3_FLG2_PROTECTED_NVRAM
)) {
2253 u32 nvaccess
= tr32(NVRAM_ACCESS
);
2255 tw32(NVRAM_ACCESS
, nvaccess
| ACCESS_ENABLE
);
2259 /* tp->lock is held. */
2260 static void tg3_disable_nvram_access(struct tg3
*tp
)
2262 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2263 !(tp
->tg3_flags2
& TG3_FLG2_PROTECTED_NVRAM
)) {
2264 u32 nvaccess
= tr32(NVRAM_ACCESS
);
2266 tw32(NVRAM_ACCESS
, nvaccess
& ~ACCESS_ENABLE
);
2270 static int tg3_nvram_read_using_eeprom(struct tg3
*tp
,
2271 u32 offset
, u32
*val
)
2276 if (offset
> EEPROM_ADDR_ADDR_MASK
|| (offset
% 4) != 0)
2279 tmp
= tr32(GRC_EEPROM_ADDR
) & ~(EEPROM_ADDR_ADDR_MASK
|
2280 EEPROM_ADDR_DEVID_MASK
|
2282 tw32(GRC_EEPROM_ADDR
,
2284 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
2285 ((offset
<< EEPROM_ADDR_ADDR_SHIFT
) &
2286 EEPROM_ADDR_ADDR_MASK
) |
2287 EEPROM_ADDR_READ
| EEPROM_ADDR_START
);
2289 for (i
= 0; i
< 1000; i
++) {
2290 tmp
= tr32(GRC_EEPROM_ADDR
);
2292 if (tmp
& EEPROM_ADDR_COMPLETE
)
2296 if (!(tmp
& EEPROM_ADDR_COMPLETE
))
2299 tmp
= tr32(GRC_EEPROM_DATA
);
2302 * The data will always be opposite the native endian
2303 * format. Perform a blind byteswap to compensate.
2310 #define NVRAM_CMD_TIMEOUT 10000
2312 static int tg3_nvram_exec_cmd(struct tg3
*tp
, u32 nvram_cmd
)
2316 tw32(NVRAM_CMD
, nvram_cmd
);
2317 for (i
= 0; i
< NVRAM_CMD_TIMEOUT
; i
++) {
2319 if (tr32(NVRAM_CMD
) & NVRAM_CMD_DONE
) {
2325 if (i
== NVRAM_CMD_TIMEOUT
)
2331 static u32
tg3_nvram_phys_addr(struct tg3
*tp
, u32 addr
)
2333 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM
) &&
2334 (tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
2335 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
2336 !(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM_ADDR_TRANS
) &&
2337 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
2339 addr
= ((addr
/ tp
->nvram_pagesize
) <<
2340 ATMEL_AT45DB0X1B_PAGE_POS
) +
2341 (addr
% tp
->nvram_pagesize
);
2346 static u32
tg3_nvram_logical_addr(struct tg3
*tp
, u32 addr
)
2348 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM
) &&
2349 (tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
2350 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
2351 !(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM_ADDR_TRANS
) &&
2352 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
2354 addr
= ((addr
>> ATMEL_AT45DB0X1B_PAGE_POS
) *
2355 tp
->nvram_pagesize
) +
2356 (addr
& ((1 << ATMEL_AT45DB0X1B_PAGE_POS
) - 1));
2361 /* NOTE: Data read in from NVRAM is byteswapped according to
2362 * the byteswapping settings for all other register accesses.
2363 * tg3 devices are BE devices, so on a BE machine, the data
2364 * returned will be exactly as it is seen in NVRAM. On a LE
2365 * machine, the 32-bit value will be byteswapped.
2367 static int tg3_nvram_read(struct tg3
*tp
, u32 offset
, u32
*val
)
2371 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
))
2372 return tg3_nvram_read_using_eeprom(tp
, offset
, val
);
2374 offset
= tg3_nvram_phys_addr(tp
, offset
);
2376 if (offset
> NVRAM_ADDR_MSK
)
2379 ret
= tg3_nvram_lock(tp
);
2383 tg3_enable_nvram_access(tp
);
2385 tw32(NVRAM_ADDR
, offset
);
2386 ret
= tg3_nvram_exec_cmd(tp
, NVRAM_CMD_RD
| NVRAM_CMD_GO
|
2387 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_DONE
);
2390 *val
= tr32(NVRAM_RDDATA
);
2392 tg3_disable_nvram_access(tp
);
2394 tg3_nvram_unlock(tp
);
2399 /* Ensures NVRAM data is in bytestream format. */
2400 static int tg3_nvram_read_be32(struct tg3
*tp
, u32 offset
, __be32
*val
)
2403 int res
= tg3_nvram_read(tp
, offset
, &v
);
2405 *val
= cpu_to_be32(v
);
2409 /* tp->lock is held. */
2410 static void __tg3_set_mac_addr(struct tg3
*tp
, int skip_mac_1
)
2412 u32 addr_high
, addr_low
;
2415 addr_high
= ((tp
->dev
->dev_addr
[0] << 8) |
2416 tp
->dev
->dev_addr
[1]);
2417 addr_low
= ((tp
->dev
->dev_addr
[2] << 24) |
2418 (tp
->dev
->dev_addr
[3] << 16) |
2419 (tp
->dev
->dev_addr
[4] << 8) |
2420 (tp
->dev
->dev_addr
[5] << 0));
2421 for (i
= 0; i
< 4; i
++) {
2422 if (i
== 1 && skip_mac_1
)
2424 tw32(MAC_ADDR_0_HIGH
+ (i
* 8), addr_high
);
2425 tw32(MAC_ADDR_0_LOW
+ (i
* 8), addr_low
);
2428 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
2429 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
2430 for (i
= 0; i
< 12; i
++) {
2431 tw32(MAC_EXTADDR_0_HIGH
+ (i
* 8), addr_high
);
2432 tw32(MAC_EXTADDR_0_LOW
+ (i
* 8), addr_low
);
2436 addr_high
= (tp
->dev
->dev_addr
[0] +
2437 tp
->dev
->dev_addr
[1] +
2438 tp
->dev
->dev_addr
[2] +
2439 tp
->dev
->dev_addr
[3] +
2440 tp
->dev
->dev_addr
[4] +
2441 tp
->dev
->dev_addr
[5]) &
2442 TX_BACKOFF_SEED_MASK
;
2443 tw32(MAC_TX_BACKOFF_SEED
, addr_high
);
2446 static int tg3_set_power_state(struct tg3
*tp
, pci_power_t state
)
2449 bool device_should_wake
, do_low_power
;
2451 /* Make sure register accesses (indirect or otherwise)
2452 * will function correctly.
2454 pci_write_config_dword(tp
->pdev
,
2455 TG3PCI_MISC_HOST_CTRL
,
2456 tp
->misc_host_ctrl
);
2460 pci_enable_wake(tp
->pdev
, state
, false);
2461 pci_set_power_state(tp
->pdev
, PCI_D0
);
2463 /* Switch out of Vaux if it is a NIC */
2464 if (tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)
2465 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
, 100);
2475 printk(KERN_ERR PFX
"%s: Invalid power state (D%d) requested\n",
2476 tp
->dev
->name
, state
);
2480 /* Restore the CLKREQ setting. */
2481 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
) {
2484 pci_read_config_word(tp
->pdev
,
2485 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2487 lnkctl
|= PCI_EXP_LNKCTL_CLKREQ_EN
;
2488 pci_write_config_word(tp
->pdev
,
2489 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2493 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
2494 tw32(TG3PCI_MISC_HOST_CTRL
,
2495 misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
);
2497 device_should_wake
= pci_pme_capable(tp
->pdev
, state
) &&
2498 device_may_wakeup(&tp
->pdev
->dev
) &&
2499 (tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
2501 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
2502 do_low_power
= false;
2503 if ((tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) &&
2504 !tp
->link_config
.phy_is_low_power
) {
2505 struct phy_device
*phydev
;
2506 u32 phyid
, advertising
;
2508 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
2510 tp
->link_config
.phy_is_low_power
= 1;
2512 tp
->link_config
.orig_speed
= phydev
->speed
;
2513 tp
->link_config
.orig_duplex
= phydev
->duplex
;
2514 tp
->link_config
.orig_autoneg
= phydev
->autoneg
;
2515 tp
->link_config
.orig_advertising
= phydev
->advertising
;
2517 advertising
= ADVERTISED_TP
|
2519 ADVERTISED_Autoneg
|
2520 ADVERTISED_10baseT_Half
;
2522 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
2523 device_should_wake
) {
2524 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
2526 ADVERTISED_100baseT_Half
|
2527 ADVERTISED_100baseT_Full
|
2528 ADVERTISED_10baseT_Full
;
2530 advertising
|= ADVERTISED_10baseT_Full
;
2533 phydev
->advertising
= advertising
;
2535 phy_start_aneg(phydev
);
2537 phyid
= phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
;
2538 if (phyid
!= TG3_PHY_ID_BCMAC131
) {
2539 phyid
&= TG3_PHY_OUI_MASK
;
2540 if (phyid
== TG3_PHY_OUI_1
||
2541 phyid
== TG3_PHY_OUI_2
||
2542 phyid
== TG3_PHY_OUI_3
)
2543 do_low_power
= true;
2547 do_low_power
= true;
2549 if (tp
->link_config
.phy_is_low_power
== 0) {
2550 tp
->link_config
.phy_is_low_power
= 1;
2551 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
2552 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
2553 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
2556 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)) {
2557 tp
->link_config
.speed
= SPEED_10
;
2558 tp
->link_config
.duplex
= DUPLEX_HALF
;
2559 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
2560 tg3_setup_phy(tp
, 0);
2564 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2567 val
= tr32(GRC_VCPU_EXT_CTRL
);
2568 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_DISABLE_WOL
);
2569 } else if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
2573 for (i
= 0; i
< 200; i
++) {
2574 tg3_read_mem(tp
, NIC_SRAM_FW_ASF_STATUS_MBOX
, &val
);
2575 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
2580 if (tp
->tg3_flags
& TG3_FLAG_WOL_CAP
)
2581 tg3_write_mem(tp
, NIC_SRAM_WOL_MBOX
, WOL_SIGNATURE
|
2582 WOL_DRV_STATE_SHUTDOWN
|
2586 if (device_should_wake
) {
2589 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
2591 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x5a);
2595 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)
2596 mac_mode
= MAC_MODE_PORT_MODE_GMII
;
2598 mac_mode
= MAC_MODE_PORT_MODE_MII
;
2600 mac_mode
|= tp
->mac_mode
& MAC_MODE_LINK_POLARITY
;
2601 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
2603 u32 speed
= (tp
->tg3_flags
&
2604 TG3_FLAG_WOL_SPEED_100MB
) ?
2605 SPEED_100
: SPEED_10
;
2606 if (tg3_5700_link_polarity(tp
, speed
))
2607 mac_mode
|= MAC_MODE_LINK_POLARITY
;
2609 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
2612 mac_mode
= MAC_MODE_PORT_MODE_TBI
;
2615 if (!(tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
2616 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
2618 mac_mode
|= MAC_MODE_MAGIC_PKT_ENABLE
;
2619 if (((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
2620 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) &&
2621 ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
2622 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)))
2623 mac_mode
|= MAC_MODE_KEEP_FRAME_IN_WOL
;
2625 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
2626 mac_mode
|= tp
->mac_mode
&
2627 (MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
);
2628 if (mac_mode
& MAC_MODE_APE_TX_EN
)
2629 mac_mode
|= MAC_MODE_TDE_ENABLE
;
2632 tw32_f(MAC_MODE
, mac_mode
);
2635 tw32_f(MAC_RX_MODE
, RX_MODE_ENABLE
);
2639 if (!(tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
) &&
2640 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2641 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
2644 base_val
= tp
->pci_clock_ctrl
;
2645 base_val
|= (CLOCK_CTRL_RXCLK_DISABLE
|
2646 CLOCK_CTRL_TXCLK_DISABLE
);
2648 tw32_wait_f(TG3PCI_CLOCK_CTRL
, base_val
| CLOCK_CTRL_ALTCLK
|
2649 CLOCK_CTRL_PWRDOWN_PLL133
, 40);
2650 } else if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
2651 (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
2652 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)) {
2654 } else if (!((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2655 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))) {
2656 u32 newbits1
, newbits2
;
2658 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2659 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2660 newbits1
= (CLOCK_CTRL_RXCLK_DISABLE
|
2661 CLOCK_CTRL_TXCLK_DISABLE
|
2663 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
2664 } else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
2665 newbits1
= CLOCK_CTRL_625_CORE
;
2666 newbits2
= newbits1
| CLOCK_CTRL_ALTCLK
;
2668 newbits1
= CLOCK_CTRL_ALTCLK
;
2669 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
2672 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits1
,
2675 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits2
,
2678 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
2681 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2682 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2683 newbits3
= (CLOCK_CTRL_RXCLK_DISABLE
|
2684 CLOCK_CTRL_TXCLK_DISABLE
|
2685 CLOCK_CTRL_44MHZ_CORE
);
2687 newbits3
= CLOCK_CTRL_44MHZ_CORE
;
2690 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
2691 tp
->pci_clock_ctrl
| newbits3
, 40);
2695 if (!(device_should_wake
) &&
2696 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
2697 tg3_power_down_phy(tp
, do_low_power
);
2699 tg3_frob_aux_power(tp
);
2701 /* Workaround for unstable PLL clock */
2702 if ((GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
) ||
2703 (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
)) {
2704 u32 val
= tr32(0x7d00);
2706 val
&= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2708 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
2711 err
= tg3_nvram_lock(tp
);
2712 tg3_halt_cpu(tp
, RX_CPU_BASE
);
2714 tg3_nvram_unlock(tp
);
2718 tg3_write_sig_post_reset(tp
, RESET_KIND_SHUTDOWN
);
2720 if (device_should_wake
)
2721 pci_enable_wake(tp
->pdev
, state
, true);
2723 /* Finally, set the new power state. */
2724 pci_set_power_state(tp
->pdev
, state
);
2729 static void tg3_aux_stat_to_speed_duplex(struct tg3
*tp
, u32 val
, u16
*speed
, u8
*duplex
)
2731 switch (val
& MII_TG3_AUX_STAT_SPDMASK
) {
2732 case MII_TG3_AUX_STAT_10HALF
:
2734 *duplex
= DUPLEX_HALF
;
2737 case MII_TG3_AUX_STAT_10FULL
:
2739 *duplex
= DUPLEX_FULL
;
2742 case MII_TG3_AUX_STAT_100HALF
:
2744 *duplex
= DUPLEX_HALF
;
2747 case MII_TG3_AUX_STAT_100FULL
:
2749 *duplex
= DUPLEX_FULL
;
2752 case MII_TG3_AUX_STAT_1000HALF
:
2753 *speed
= SPEED_1000
;
2754 *duplex
= DUPLEX_HALF
;
2757 case MII_TG3_AUX_STAT_1000FULL
:
2758 *speed
= SPEED_1000
;
2759 *duplex
= DUPLEX_FULL
;
2763 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
2764 *speed
= (val
& MII_TG3_AUX_STAT_100
) ? SPEED_100
:
2766 *duplex
= (val
& MII_TG3_AUX_STAT_FULL
) ? DUPLEX_FULL
:
2770 *speed
= SPEED_INVALID
;
2771 *duplex
= DUPLEX_INVALID
;
2776 static void tg3_phy_copper_begin(struct tg3
*tp
)
2781 if (tp
->link_config
.phy_is_low_power
) {
2782 /* Entering low power mode. Disable gigabit and
2783 * 100baseT advertisements.
2785 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
2787 new_adv
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
2788 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
2789 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
2790 new_adv
|= (ADVERTISE_100HALF
| ADVERTISE_100FULL
);
2792 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2793 } else if (tp
->link_config
.speed
== SPEED_INVALID
) {
2794 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
2795 tp
->link_config
.advertising
&=
2796 ~(ADVERTISED_1000baseT_Half
|
2797 ADVERTISED_1000baseT_Full
);
2799 new_adv
= ADVERTISE_CSMA
;
2800 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Half
)
2801 new_adv
|= ADVERTISE_10HALF
;
2802 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Full
)
2803 new_adv
|= ADVERTISE_10FULL
;
2804 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Half
)
2805 new_adv
|= ADVERTISE_100HALF
;
2806 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Full
)
2807 new_adv
|= ADVERTISE_100FULL
;
2809 new_adv
|= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2811 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2813 if (tp
->link_config
.advertising
&
2814 (ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
)) {
2816 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
2817 new_adv
|= MII_TG3_CTRL_ADV_1000_HALF
;
2818 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
2819 new_adv
|= MII_TG3_CTRL_ADV_1000_FULL
;
2820 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
) &&
2821 (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2822 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
))
2823 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
2824 MII_TG3_CTRL_ENABLE_AS_MASTER
);
2825 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
2827 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
2830 new_adv
= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2831 new_adv
|= ADVERTISE_CSMA
;
2833 /* Asking for a specific link mode. */
2834 if (tp
->link_config
.speed
== SPEED_1000
) {
2835 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2837 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2838 new_adv
= MII_TG3_CTRL_ADV_1000_FULL
;
2840 new_adv
= MII_TG3_CTRL_ADV_1000_HALF
;
2841 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2842 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
2843 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
2844 MII_TG3_CTRL_ENABLE_AS_MASTER
);
2846 if (tp
->link_config
.speed
== SPEED_100
) {
2847 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2848 new_adv
|= ADVERTISE_100FULL
;
2850 new_adv
|= ADVERTISE_100HALF
;
2852 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2853 new_adv
|= ADVERTISE_10FULL
;
2855 new_adv
|= ADVERTISE_10HALF
;
2857 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2862 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
2865 if (tp
->link_config
.autoneg
== AUTONEG_DISABLE
&&
2866 tp
->link_config
.speed
!= SPEED_INVALID
) {
2867 u32 bmcr
, orig_bmcr
;
2869 tp
->link_config
.active_speed
= tp
->link_config
.speed
;
2870 tp
->link_config
.active_duplex
= tp
->link_config
.duplex
;
2873 switch (tp
->link_config
.speed
) {
2879 bmcr
|= BMCR_SPEED100
;
2883 bmcr
|= TG3_BMCR_SPEED1000
;
2887 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2888 bmcr
|= BMCR_FULLDPLX
;
2890 if (!tg3_readphy(tp
, MII_BMCR
, &orig_bmcr
) &&
2891 (bmcr
!= orig_bmcr
)) {
2892 tg3_writephy(tp
, MII_BMCR
, BMCR_LOOPBACK
);
2893 for (i
= 0; i
< 1500; i
++) {
2897 if (tg3_readphy(tp
, MII_BMSR
, &tmp
) ||
2898 tg3_readphy(tp
, MII_BMSR
, &tmp
))
2900 if (!(tmp
& BMSR_LSTATUS
)) {
2905 tg3_writephy(tp
, MII_BMCR
, bmcr
);
2909 tg3_writephy(tp
, MII_BMCR
,
2910 BMCR_ANENABLE
| BMCR_ANRESTART
);
2914 static int tg3_init_5401phy_dsp(struct tg3
*tp
)
2918 /* Turn off tap power management. */
2919 /* Set Extended packet length bit */
2920 err
= tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
2922 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x0012);
2923 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x1804);
2925 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x0013);
2926 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x1204);
2928 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8006);
2929 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0132);
2931 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8006);
2932 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0232);
2934 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
2935 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0a20);
2942 static int tg3_copper_is_advertising_all(struct tg3
*tp
, u32 mask
)
2944 u32 adv_reg
, all_mask
= 0;
2946 if (mask
& ADVERTISED_10baseT_Half
)
2947 all_mask
|= ADVERTISE_10HALF
;
2948 if (mask
& ADVERTISED_10baseT_Full
)
2949 all_mask
|= ADVERTISE_10FULL
;
2950 if (mask
& ADVERTISED_100baseT_Half
)
2951 all_mask
|= ADVERTISE_100HALF
;
2952 if (mask
& ADVERTISED_100baseT_Full
)
2953 all_mask
|= ADVERTISE_100FULL
;
2955 if (tg3_readphy(tp
, MII_ADVERTISE
, &adv_reg
))
2958 if ((adv_reg
& all_mask
) != all_mask
)
2960 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
2964 if (mask
& ADVERTISED_1000baseT_Half
)
2965 all_mask
|= ADVERTISE_1000HALF
;
2966 if (mask
& ADVERTISED_1000baseT_Full
)
2967 all_mask
|= ADVERTISE_1000FULL
;
2969 if (tg3_readphy(tp
, MII_TG3_CTRL
, &tg3_ctrl
))
2972 if ((tg3_ctrl
& all_mask
) != all_mask
)
2978 static int tg3_adv_1000T_flowctrl_ok(struct tg3
*tp
, u32
*lcladv
, u32
*rmtadv
)
2982 if (tg3_readphy(tp
, MII_ADVERTISE
, lcladv
))
2985 curadv
= *lcladv
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
2986 reqadv
= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2988 if (tp
->link_config
.active_duplex
== DUPLEX_FULL
) {
2989 if (curadv
!= reqadv
)
2992 if (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
)
2993 tg3_readphy(tp
, MII_LPA
, rmtadv
);
2995 /* Reprogram the advertisement register, even if it
2996 * does not affect the current link. If the link
2997 * gets renegotiated in the future, we can save an
2998 * additional renegotiation cycle by advertising
2999 * it correctly in the first place.
3001 if (curadv
!= reqadv
) {
3002 *lcladv
&= ~(ADVERTISE_PAUSE_CAP
|
3003 ADVERTISE_PAUSE_ASYM
);
3004 tg3_writephy(tp
, MII_ADVERTISE
, *lcladv
| reqadv
);
3011 static int tg3_setup_copper_phy(struct tg3
*tp
, int force_reset
)
3013 int current_link_up
;
3015 u32 lcl_adv
, rmt_adv
;
3023 (MAC_STATUS_SYNC_CHANGED
|
3024 MAC_STATUS_CFG_CHANGED
|
3025 MAC_STATUS_MI_COMPLETION
|
3026 MAC_STATUS_LNKSTATE_CHANGED
));
3029 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
3031 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
3035 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x02);
3037 /* Some third-party PHYs need to be reset on link going
3040 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
3041 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
3042 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
3043 netif_carrier_ok(tp
->dev
)) {
3044 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3045 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3046 !(bmsr
& BMSR_LSTATUS
))
3052 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
) {
3053 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3054 if (tg3_readphy(tp
, MII_BMSR
, &bmsr
) ||
3055 !(tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
))
3058 if (!(bmsr
& BMSR_LSTATUS
)) {
3059 err
= tg3_init_5401phy_dsp(tp
);
3063 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3064 for (i
= 0; i
< 1000; i
++) {
3066 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3067 (bmsr
& BMSR_LSTATUS
)) {
3073 if ((tp
->phy_id
& PHY_ID_REV_MASK
) == PHY_REV_BCM5401_B0
&&
3074 !(bmsr
& BMSR_LSTATUS
) &&
3075 tp
->link_config
.active_speed
== SPEED_1000
) {
3076 err
= tg3_phy_reset(tp
);
3078 err
= tg3_init_5401phy_dsp(tp
);
3083 } else if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
3084 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
) {
3085 /* 5701 {A0,B0} CRC bug workaround */
3086 tg3_writephy(tp
, 0x15, 0x0a75);
3087 tg3_writephy(tp
, 0x1c, 0x8c68);
3088 tg3_writephy(tp
, 0x1c, 0x8d68);
3089 tg3_writephy(tp
, 0x1c, 0x8c68);
3092 /* Clear pending interrupts... */
3093 tg3_readphy(tp
, MII_TG3_ISTAT
, &dummy
);
3094 tg3_readphy(tp
, MII_TG3_ISTAT
, &dummy
);
3096 if (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
)
3097 tg3_writephy(tp
, MII_TG3_IMASK
, ~MII_TG3_INT_LINKCHG
);
3098 else if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
))
3099 tg3_writephy(tp
, MII_TG3_IMASK
, ~0);
3101 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
3102 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
3103 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_1
)
3104 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
3105 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
3107 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, 0);
3110 current_link_up
= 0;
3111 current_speed
= SPEED_INVALID
;
3112 current_duplex
= DUPLEX_INVALID
;
3114 if (tp
->tg3_flags2
& TG3_FLG2_CAPACITIVE_COUPLING
) {
3117 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4007);
3118 tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
);
3119 if (!(val
& (1 << 10))) {
3121 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, val
);
3127 for (i
= 0; i
< 100; i
++) {
3128 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3129 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3130 (bmsr
& BMSR_LSTATUS
))
3135 if (bmsr
& BMSR_LSTATUS
) {
3138 tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
);
3139 for (i
= 0; i
< 2000; i
++) {
3141 if (!tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
) &&
3146 tg3_aux_stat_to_speed_duplex(tp
, aux_stat
,
3151 for (i
= 0; i
< 200; i
++) {
3152 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
3153 if (tg3_readphy(tp
, MII_BMCR
, &bmcr
))
3155 if (bmcr
&& bmcr
!= 0x7fff)
3163 tp
->link_config
.active_speed
= current_speed
;
3164 tp
->link_config
.active_duplex
= current_duplex
;
3166 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3167 if ((bmcr
& BMCR_ANENABLE
) &&
3168 tg3_copper_is_advertising_all(tp
,
3169 tp
->link_config
.advertising
)) {
3170 if (tg3_adv_1000T_flowctrl_ok(tp
, &lcl_adv
,
3172 current_link_up
= 1;
3175 if (!(bmcr
& BMCR_ANENABLE
) &&
3176 tp
->link_config
.speed
== current_speed
&&
3177 tp
->link_config
.duplex
== current_duplex
&&
3178 tp
->link_config
.flowctrl
==
3179 tp
->link_config
.active_flowctrl
) {
3180 current_link_up
= 1;
3184 if (current_link_up
== 1 &&
3185 tp
->link_config
.active_duplex
== DUPLEX_FULL
)
3186 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
3190 if (current_link_up
== 0 || tp
->link_config
.phy_is_low_power
) {
3193 tg3_phy_copper_begin(tp
);
3195 tg3_readphy(tp
, MII_BMSR
, &tmp
);
3196 if (!tg3_readphy(tp
, MII_BMSR
, &tmp
) &&
3197 (tmp
& BMSR_LSTATUS
))
3198 current_link_up
= 1;
3201 tp
->mac_mode
&= ~MAC_MODE_PORT_MODE_MASK
;
3202 if (current_link_up
== 1) {
3203 if (tp
->link_config
.active_speed
== SPEED_100
||
3204 tp
->link_config
.active_speed
== SPEED_10
)
3205 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
3207 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3208 } else if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
)
3209 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
3211 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3213 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
3214 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
3215 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
3217 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
3218 if (current_link_up
== 1 &&
3219 tg3_5700_link_polarity(tp
, tp
->link_config
.active_speed
))
3220 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
3222 tp
->mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
3225 /* ??? Without this setting Netgear GA302T PHY does not
3226 * ??? send/receive packets...
3228 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5411
&&
3229 tp
->pci_chip_rev_id
== CHIPREV_ID_5700_ALTIMA
) {
3230 tp
->mi_mode
|= MAC_MI_MODE_AUTO_POLL
;
3231 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
3235 tw32_f(MAC_MODE
, tp
->mac_mode
);
3238 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
3239 /* Polled via timer. */
3240 tw32_f(MAC_EVENT
, 0);
3242 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
3246 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
&&
3247 current_link_up
== 1 &&
3248 tp
->link_config
.active_speed
== SPEED_1000
&&
3249 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) ||
3250 (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
))) {
3253 (MAC_STATUS_SYNC_CHANGED
|
3254 MAC_STATUS_CFG_CHANGED
));
3257 NIC_SRAM_FIRMWARE_MBOX
,
3258 NIC_SRAM_FIRMWARE_MBOX_MAGIC2
);
3261 /* Prevent send BD corruption. */
3262 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
) {
3263 u16 oldlnkctl
, newlnkctl
;
3265 pci_read_config_word(tp
->pdev
,
3266 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
3268 if (tp
->link_config
.active_speed
== SPEED_100
||
3269 tp
->link_config
.active_speed
== SPEED_10
)
3270 newlnkctl
= oldlnkctl
& ~PCI_EXP_LNKCTL_CLKREQ_EN
;
3272 newlnkctl
= oldlnkctl
| PCI_EXP_LNKCTL_CLKREQ_EN
;
3273 if (newlnkctl
!= oldlnkctl
)
3274 pci_write_config_word(tp
->pdev
,
3275 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
3279 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
3280 if (current_link_up
)
3281 netif_carrier_on(tp
->dev
);
3283 netif_carrier_off(tp
->dev
);
3284 tg3_link_report(tp
);
3290 struct tg3_fiber_aneginfo
{
3292 #define ANEG_STATE_UNKNOWN 0
3293 #define ANEG_STATE_AN_ENABLE 1
3294 #define ANEG_STATE_RESTART_INIT 2
3295 #define ANEG_STATE_RESTART 3
3296 #define ANEG_STATE_DISABLE_LINK_OK 4
3297 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3298 #define ANEG_STATE_ABILITY_DETECT 6
3299 #define ANEG_STATE_ACK_DETECT_INIT 7
3300 #define ANEG_STATE_ACK_DETECT 8
3301 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3302 #define ANEG_STATE_COMPLETE_ACK 10
3303 #define ANEG_STATE_IDLE_DETECT_INIT 11
3304 #define ANEG_STATE_IDLE_DETECT 12
3305 #define ANEG_STATE_LINK_OK 13
3306 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3307 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3310 #define MR_AN_ENABLE 0x00000001
3311 #define MR_RESTART_AN 0x00000002
3312 #define MR_AN_COMPLETE 0x00000004
3313 #define MR_PAGE_RX 0x00000008
3314 #define MR_NP_LOADED 0x00000010
3315 #define MR_TOGGLE_TX 0x00000020
3316 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3317 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3318 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3319 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3320 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3321 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3322 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3323 #define MR_TOGGLE_RX 0x00002000
3324 #define MR_NP_RX 0x00004000
3326 #define MR_LINK_OK 0x80000000
3328 unsigned long link_time
, cur_time
;
3330 u32 ability_match_cfg
;
3331 int ability_match_count
;
3333 char ability_match
, idle_match
, ack_match
;
3335 u32 txconfig
, rxconfig
;
3336 #define ANEG_CFG_NP 0x00000080
3337 #define ANEG_CFG_ACK 0x00000040
3338 #define ANEG_CFG_RF2 0x00000020
3339 #define ANEG_CFG_RF1 0x00000010
3340 #define ANEG_CFG_PS2 0x00000001
3341 #define ANEG_CFG_PS1 0x00008000
3342 #define ANEG_CFG_HD 0x00004000
3343 #define ANEG_CFG_FD 0x00002000
3344 #define ANEG_CFG_INVAL 0x00001f06
3349 #define ANEG_TIMER_ENAB 2
3350 #define ANEG_FAILED -1
3352 #define ANEG_STATE_SETTLE_TIME 10000
3354 static int tg3_fiber_aneg_smachine(struct tg3
*tp
,
3355 struct tg3_fiber_aneginfo
*ap
)
3358 unsigned long delta
;
3362 if (ap
->state
== ANEG_STATE_UNKNOWN
) {
3366 ap
->ability_match_cfg
= 0;
3367 ap
->ability_match_count
= 0;
3368 ap
->ability_match
= 0;
3374 if (tr32(MAC_STATUS
) & MAC_STATUS_RCVD_CFG
) {
3375 rx_cfg_reg
= tr32(MAC_RX_AUTO_NEG
);
3377 if (rx_cfg_reg
!= ap
->ability_match_cfg
) {
3378 ap
->ability_match_cfg
= rx_cfg_reg
;
3379 ap
->ability_match
= 0;
3380 ap
->ability_match_count
= 0;
3382 if (++ap
->ability_match_count
> 1) {
3383 ap
->ability_match
= 1;
3384 ap
->ability_match_cfg
= rx_cfg_reg
;
3387 if (rx_cfg_reg
& ANEG_CFG_ACK
)
3395 ap
->ability_match_cfg
= 0;
3396 ap
->ability_match_count
= 0;
3397 ap
->ability_match
= 0;
3403 ap
->rxconfig
= rx_cfg_reg
;
3407 case ANEG_STATE_UNKNOWN
:
3408 if (ap
->flags
& (MR_AN_ENABLE
| MR_RESTART_AN
))
3409 ap
->state
= ANEG_STATE_AN_ENABLE
;
3412 case ANEG_STATE_AN_ENABLE
:
3413 ap
->flags
&= ~(MR_AN_COMPLETE
| MR_PAGE_RX
);
3414 if (ap
->flags
& MR_AN_ENABLE
) {
3417 ap
->ability_match_cfg
= 0;
3418 ap
->ability_match_count
= 0;
3419 ap
->ability_match
= 0;
3423 ap
->state
= ANEG_STATE_RESTART_INIT
;
3425 ap
->state
= ANEG_STATE_DISABLE_LINK_OK
;
3429 case ANEG_STATE_RESTART_INIT
:
3430 ap
->link_time
= ap
->cur_time
;
3431 ap
->flags
&= ~(MR_NP_LOADED
);
3433 tw32(MAC_TX_AUTO_NEG
, 0);
3434 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3435 tw32_f(MAC_MODE
, tp
->mac_mode
);
3438 ret
= ANEG_TIMER_ENAB
;
3439 ap
->state
= ANEG_STATE_RESTART
;
3442 case ANEG_STATE_RESTART
:
3443 delta
= ap
->cur_time
- ap
->link_time
;
3444 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3445 ap
->state
= ANEG_STATE_ABILITY_DETECT_INIT
;
3447 ret
= ANEG_TIMER_ENAB
;
3451 case ANEG_STATE_DISABLE_LINK_OK
:
3455 case ANEG_STATE_ABILITY_DETECT_INIT
:
3456 ap
->flags
&= ~(MR_TOGGLE_TX
);
3457 ap
->txconfig
= ANEG_CFG_FD
;
3458 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3459 if (flowctrl
& ADVERTISE_1000XPAUSE
)
3460 ap
->txconfig
|= ANEG_CFG_PS1
;
3461 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
3462 ap
->txconfig
|= ANEG_CFG_PS2
;
3463 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
3464 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3465 tw32_f(MAC_MODE
, tp
->mac_mode
);
3468 ap
->state
= ANEG_STATE_ABILITY_DETECT
;
3471 case ANEG_STATE_ABILITY_DETECT
:
3472 if (ap
->ability_match
!= 0 && ap
->rxconfig
!= 0) {
3473 ap
->state
= ANEG_STATE_ACK_DETECT_INIT
;
3477 case ANEG_STATE_ACK_DETECT_INIT
:
3478 ap
->txconfig
|= ANEG_CFG_ACK
;
3479 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
3480 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3481 tw32_f(MAC_MODE
, tp
->mac_mode
);
3484 ap
->state
= ANEG_STATE_ACK_DETECT
;
3487 case ANEG_STATE_ACK_DETECT
:
3488 if (ap
->ack_match
!= 0) {
3489 if ((ap
->rxconfig
& ~ANEG_CFG_ACK
) ==
3490 (ap
->ability_match_cfg
& ~ANEG_CFG_ACK
)) {
3491 ap
->state
= ANEG_STATE_COMPLETE_ACK_INIT
;
3493 ap
->state
= ANEG_STATE_AN_ENABLE
;
3495 } else if (ap
->ability_match
!= 0 &&
3496 ap
->rxconfig
== 0) {
3497 ap
->state
= ANEG_STATE_AN_ENABLE
;
3501 case ANEG_STATE_COMPLETE_ACK_INIT
:
3502 if (ap
->rxconfig
& ANEG_CFG_INVAL
) {
3506 ap
->flags
&= ~(MR_LP_ADV_FULL_DUPLEX
|
3507 MR_LP_ADV_HALF_DUPLEX
|
3508 MR_LP_ADV_SYM_PAUSE
|
3509 MR_LP_ADV_ASYM_PAUSE
|
3510 MR_LP_ADV_REMOTE_FAULT1
|
3511 MR_LP_ADV_REMOTE_FAULT2
|
3512 MR_LP_ADV_NEXT_PAGE
|
3515 if (ap
->rxconfig
& ANEG_CFG_FD
)
3516 ap
->flags
|= MR_LP_ADV_FULL_DUPLEX
;
3517 if (ap
->rxconfig
& ANEG_CFG_HD
)
3518 ap
->flags
|= MR_LP_ADV_HALF_DUPLEX
;
3519 if (ap
->rxconfig
& ANEG_CFG_PS1
)
3520 ap
->flags
|= MR_LP_ADV_SYM_PAUSE
;
3521 if (ap
->rxconfig
& ANEG_CFG_PS2
)
3522 ap
->flags
|= MR_LP_ADV_ASYM_PAUSE
;
3523 if (ap
->rxconfig
& ANEG_CFG_RF1
)
3524 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT1
;
3525 if (ap
->rxconfig
& ANEG_CFG_RF2
)
3526 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT2
;
3527 if (ap
->rxconfig
& ANEG_CFG_NP
)
3528 ap
->flags
|= MR_LP_ADV_NEXT_PAGE
;
3530 ap
->link_time
= ap
->cur_time
;
3532 ap
->flags
^= (MR_TOGGLE_TX
);
3533 if (ap
->rxconfig
& 0x0008)
3534 ap
->flags
|= MR_TOGGLE_RX
;
3535 if (ap
->rxconfig
& ANEG_CFG_NP
)
3536 ap
->flags
|= MR_NP_RX
;
3537 ap
->flags
|= MR_PAGE_RX
;
3539 ap
->state
= ANEG_STATE_COMPLETE_ACK
;
3540 ret
= ANEG_TIMER_ENAB
;
3543 case ANEG_STATE_COMPLETE_ACK
:
3544 if (ap
->ability_match
!= 0 &&
3545 ap
->rxconfig
== 0) {
3546 ap
->state
= ANEG_STATE_AN_ENABLE
;
3549 delta
= ap
->cur_time
- ap
->link_time
;
3550 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3551 if (!(ap
->flags
& (MR_LP_ADV_NEXT_PAGE
))) {
3552 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
3554 if ((ap
->txconfig
& ANEG_CFG_NP
) == 0 &&
3555 !(ap
->flags
& MR_NP_RX
)) {
3556 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
3564 case ANEG_STATE_IDLE_DETECT_INIT
:
3565 ap
->link_time
= ap
->cur_time
;
3566 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
3567 tw32_f(MAC_MODE
, tp
->mac_mode
);
3570 ap
->state
= ANEG_STATE_IDLE_DETECT
;
3571 ret
= ANEG_TIMER_ENAB
;
3574 case ANEG_STATE_IDLE_DETECT
:
3575 if (ap
->ability_match
!= 0 &&
3576 ap
->rxconfig
== 0) {
3577 ap
->state
= ANEG_STATE_AN_ENABLE
;
3580 delta
= ap
->cur_time
- ap
->link_time
;
3581 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3582 /* XXX another gem from the Broadcom driver :( */
3583 ap
->state
= ANEG_STATE_LINK_OK
;
3587 case ANEG_STATE_LINK_OK
:
3588 ap
->flags
|= (MR_AN_COMPLETE
| MR_LINK_OK
);
3592 case ANEG_STATE_NEXT_PAGE_WAIT_INIT
:
3593 /* ??? unimplemented */
3596 case ANEG_STATE_NEXT_PAGE_WAIT
:
3597 /* ??? unimplemented */
3608 static int fiber_autoneg(struct tg3
*tp
, u32
*txflags
, u32
*rxflags
)
3611 struct tg3_fiber_aneginfo aninfo
;
3612 int status
= ANEG_FAILED
;
3616 tw32_f(MAC_TX_AUTO_NEG
, 0);
3618 tmp
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
3619 tw32_f(MAC_MODE
, tmp
| MAC_MODE_PORT_MODE_GMII
);
3622 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
);
3625 memset(&aninfo
, 0, sizeof(aninfo
));
3626 aninfo
.flags
|= MR_AN_ENABLE
;
3627 aninfo
.state
= ANEG_STATE_UNKNOWN
;
3628 aninfo
.cur_time
= 0;
3630 while (++tick
< 195000) {
3631 status
= tg3_fiber_aneg_smachine(tp
, &aninfo
);
3632 if (status
== ANEG_DONE
|| status
== ANEG_FAILED
)
3638 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
3639 tw32_f(MAC_MODE
, tp
->mac_mode
);
3642 *txflags
= aninfo
.txconfig
;
3643 *rxflags
= aninfo
.flags
;
3645 if (status
== ANEG_DONE
&&
3646 (aninfo
.flags
& (MR_AN_COMPLETE
| MR_LINK_OK
|
3647 MR_LP_ADV_FULL_DUPLEX
)))
3653 static void tg3_init_bcm8002(struct tg3
*tp
)
3655 u32 mac_status
= tr32(MAC_STATUS
);
3658 /* Reset when initting first time or we have a link. */
3659 if ((tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) &&
3660 !(mac_status
& MAC_STATUS_PCS_SYNCED
))
3663 /* Set PLL lock range. */
3664 tg3_writephy(tp
, 0x16, 0x8007);
3667 tg3_writephy(tp
, MII_BMCR
, BMCR_RESET
);
3669 /* Wait for reset to complete. */
3670 /* XXX schedule_timeout() ... */
3671 for (i
= 0; i
< 500; i
++)
3674 /* Config mode; select PMA/Ch 1 regs. */
3675 tg3_writephy(tp
, 0x10, 0x8411);
3677 /* Enable auto-lock and comdet, select txclk for tx. */
3678 tg3_writephy(tp
, 0x11, 0x0a10);
3680 tg3_writephy(tp
, 0x18, 0x00a0);
3681 tg3_writephy(tp
, 0x16, 0x41ff);
3683 /* Assert and deassert POR. */
3684 tg3_writephy(tp
, 0x13, 0x0400);
3686 tg3_writephy(tp
, 0x13, 0x0000);
3688 tg3_writephy(tp
, 0x11, 0x0a50);
3690 tg3_writephy(tp
, 0x11, 0x0a10);
3692 /* Wait for signal to stabilize */
3693 /* XXX schedule_timeout() ... */
3694 for (i
= 0; i
< 15000; i
++)
3697 /* Deselect the channel register so we can read the PHYID
3700 tg3_writephy(tp
, 0x10, 0x8011);
3703 static int tg3_setup_fiber_hw_autoneg(struct tg3
*tp
, u32 mac_status
)
3706 u32 sg_dig_ctrl
, sg_dig_status
;
3707 u32 serdes_cfg
, expected_sg_dig_ctrl
;
3708 int workaround
, port_a
;
3709 int current_link_up
;
3712 expected_sg_dig_ctrl
= 0;
3715 current_link_up
= 0;
3717 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A0
&&
3718 tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A1
) {
3720 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
3723 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3724 /* preserve bits 20-23 for voltage regulator */
3725 serdes_cfg
= tr32(MAC_SERDES_CFG
) & 0x00f06fff;
3728 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
3730 if (tp
->link_config
.autoneg
!= AUTONEG_ENABLE
) {
3731 if (sg_dig_ctrl
& SG_DIG_USING_HW_AUTONEG
) {
3733 u32 val
= serdes_cfg
;
3739 tw32_f(MAC_SERDES_CFG
, val
);
3742 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
3744 if (mac_status
& MAC_STATUS_PCS_SYNCED
) {
3745 tg3_setup_flow_control(tp
, 0, 0);
3746 current_link_up
= 1;
3751 /* Want auto-negotiation. */
3752 expected_sg_dig_ctrl
= SG_DIG_USING_HW_AUTONEG
| SG_DIG_COMMON_SETUP
;
3754 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3755 if (flowctrl
& ADVERTISE_1000XPAUSE
)
3756 expected_sg_dig_ctrl
|= SG_DIG_PAUSE_CAP
;
3757 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
3758 expected_sg_dig_ctrl
|= SG_DIG_ASYM_PAUSE
;
3760 if (sg_dig_ctrl
!= expected_sg_dig_ctrl
) {
3761 if ((tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
) &&
3762 tp
->serdes_counter
&&
3763 ((mac_status
& (MAC_STATUS_PCS_SYNCED
|
3764 MAC_STATUS_RCVD_CFG
)) ==
3765 MAC_STATUS_PCS_SYNCED
)) {
3766 tp
->serdes_counter
--;
3767 current_link_up
= 1;
3772 tw32_f(MAC_SERDES_CFG
, serdes_cfg
| 0xc011000);
3773 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
| SG_DIG_SOFT_RESET
);
3775 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
);
3777 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
3778 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3779 } else if (mac_status
& (MAC_STATUS_PCS_SYNCED
|
3780 MAC_STATUS_SIGNAL_DET
)) {
3781 sg_dig_status
= tr32(SG_DIG_STATUS
);
3782 mac_status
= tr32(MAC_STATUS
);
3784 if ((sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
) &&
3785 (mac_status
& MAC_STATUS_PCS_SYNCED
)) {
3786 u32 local_adv
= 0, remote_adv
= 0;
3788 if (sg_dig_ctrl
& SG_DIG_PAUSE_CAP
)
3789 local_adv
|= ADVERTISE_1000XPAUSE
;
3790 if (sg_dig_ctrl
& SG_DIG_ASYM_PAUSE
)
3791 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
3793 if (sg_dig_status
& SG_DIG_PARTNER_PAUSE_CAPABLE
)
3794 remote_adv
|= LPA_1000XPAUSE
;
3795 if (sg_dig_status
& SG_DIG_PARTNER_ASYM_PAUSE
)
3796 remote_adv
|= LPA_1000XPAUSE_ASYM
;
3798 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
3799 current_link_up
= 1;
3800 tp
->serdes_counter
= 0;
3801 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3802 } else if (!(sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
)) {
3803 if (tp
->serdes_counter
)
3804 tp
->serdes_counter
--;
3807 u32 val
= serdes_cfg
;
3814 tw32_f(MAC_SERDES_CFG
, val
);
3817 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
3820 /* Link parallel detection - link is up */
3821 /* only if we have PCS_SYNC and not */
3822 /* receiving config code words */
3823 mac_status
= tr32(MAC_STATUS
);
3824 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) &&
3825 !(mac_status
& MAC_STATUS_RCVD_CFG
)) {
3826 tg3_setup_flow_control(tp
, 0, 0);
3827 current_link_up
= 1;
3829 TG3_FLG2_PARALLEL_DETECT
;
3830 tp
->serdes_counter
=
3831 SERDES_PARALLEL_DET_TIMEOUT
;
3833 goto restart_autoneg
;
3837 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
3838 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3842 return current_link_up
;
3845 static int tg3_setup_fiber_by_hand(struct tg3
*tp
, u32 mac_status
)
3847 int current_link_up
= 0;
3849 if (!(mac_status
& MAC_STATUS_PCS_SYNCED
))
3852 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3853 u32 txflags
, rxflags
;
3856 if (fiber_autoneg(tp
, &txflags
, &rxflags
)) {
3857 u32 local_adv
= 0, remote_adv
= 0;
3859 if (txflags
& ANEG_CFG_PS1
)
3860 local_adv
|= ADVERTISE_1000XPAUSE
;
3861 if (txflags
& ANEG_CFG_PS2
)
3862 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
3864 if (rxflags
& MR_LP_ADV_SYM_PAUSE
)
3865 remote_adv
|= LPA_1000XPAUSE
;
3866 if (rxflags
& MR_LP_ADV_ASYM_PAUSE
)
3867 remote_adv
|= LPA_1000XPAUSE_ASYM
;
3869 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
3871 current_link_up
= 1;
3873 for (i
= 0; i
< 30; i
++) {
3876 (MAC_STATUS_SYNC_CHANGED
|
3877 MAC_STATUS_CFG_CHANGED
));
3879 if ((tr32(MAC_STATUS
) &
3880 (MAC_STATUS_SYNC_CHANGED
|
3881 MAC_STATUS_CFG_CHANGED
)) == 0)
3885 mac_status
= tr32(MAC_STATUS
);
3886 if (current_link_up
== 0 &&
3887 (mac_status
& MAC_STATUS_PCS_SYNCED
) &&
3888 !(mac_status
& MAC_STATUS_RCVD_CFG
))
3889 current_link_up
= 1;
3891 tg3_setup_flow_control(tp
, 0, 0);
3893 /* Forcing 1000FD link up. */
3894 current_link_up
= 1;
3896 tw32_f(MAC_MODE
, (tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
));
3899 tw32_f(MAC_MODE
, tp
->mac_mode
);
3904 return current_link_up
;
3907 static int tg3_setup_fiber_phy(struct tg3
*tp
, int force_reset
)
3910 u16 orig_active_speed
;
3911 u8 orig_active_duplex
;
3913 int current_link_up
;
3916 orig_pause_cfg
= tp
->link_config
.active_flowctrl
;
3917 orig_active_speed
= tp
->link_config
.active_speed
;
3918 orig_active_duplex
= tp
->link_config
.active_duplex
;
3920 if (!(tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
) &&
3921 netif_carrier_ok(tp
->dev
) &&
3922 (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
)) {
3923 mac_status
= tr32(MAC_STATUS
);
3924 mac_status
&= (MAC_STATUS_PCS_SYNCED
|
3925 MAC_STATUS_SIGNAL_DET
|
3926 MAC_STATUS_CFG_CHANGED
|
3927 MAC_STATUS_RCVD_CFG
);
3928 if (mac_status
== (MAC_STATUS_PCS_SYNCED
|
3929 MAC_STATUS_SIGNAL_DET
)) {
3930 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
3931 MAC_STATUS_CFG_CHANGED
));
3936 tw32_f(MAC_TX_AUTO_NEG
, 0);
3938 tp
->mac_mode
&= ~(MAC_MODE_PORT_MODE_MASK
| MAC_MODE_HALF_DUPLEX
);
3939 tp
->mac_mode
|= MAC_MODE_PORT_MODE_TBI
;
3940 tw32_f(MAC_MODE
, tp
->mac_mode
);
3943 if (tp
->phy_id
== PHY_ID_BCM8002
)
3944 tg3_init_bcm8002(tp
);
3946 /* Enable link change event even when serdes polling. */
3947 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
3950 current_link_up
= 0;
3951 mac_status
= tr32(MAC_STATUS
);
3953 if (tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
)
3954 current_link_up
= tg3_setup_fiber_hw_autoneg(tp
, mac_status
);
3956 current_link_up
= tg3_setup_fiber_by_hand(tp
, mac_status
);
3958 tp
->napi
[0].hw_status
->status
=
3959 (SD_STATUS_UPDATED
|
3960 (tp
->napi
[0].hw_status
->status
& ~SD_STATUS_LINK_CHG
));
3962 for (i
= 0; i
< 100; i
++) {
3963 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
3964 MAC_STATUS_CFG_CHANGED
));
3966 if ((tr32(MAC_STATUS
) & (MAC_STATUS_SYNC_CHANGED
|
3967 MAC_STATUS_CFG_CHANGED
|
3968 MAC_STATUS_LNKSTATE_CHANGED
)) == 0)
3972 mac_status
= tr32(MAC_STATUS
);
3973 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) == 0) {
3974 current_link_up
= 0;
3975 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
&&
3976 tp
->serdes_counter
== 0) {
3977 tw32_f(MAC_MODE
, (tp
->mac_mode
|
3978 MAC_MODE_SEND_CONFIGS
));
3980 tw32_f(MAC_MODE
, tp
->mac_mode
);
3984 if (current_link_up
== 1) {
3985 tp
->link_config
.active_speed
= SPEED_1000
;
3986 tp
->link_config
.active_duplex
= DUPLEX_FULL
;
3987 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
3988 LED_CTRL_LNKLED_OVERRIDE
|
3989 LED_CTRL_1000MBPS_ON
));
3991 tp
->link_config
.active_speed
= SPEED_INVALID
;
3992 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
3993 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
3994 LED_CTRL_LNKLED_OVERRIDE
|
3995 LED_CTRL_TRAFFIC_OVERRIDE
));
3998 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
3999 if (current_link_up
)
4000 netif_carrier_on(tp
->dev
);
4002 netif_carrier_off(tp
->dev
);
4003 tg3_link_report(tp
);
4005 u32 now_pause_cfg
= tp
->link_config
.active_flowctrl
;
4006 if (orig_pause_cfg
!= now_pause_cfg
||
4007 orig_active_speed
!= tp
->link_config
.active_speed
||
4008 orig_active_duplex
!= tp
->link_config
.active_duplex
)
4009 tg3_link_report(tp
);
4015 static int tg3_setup_fiber_mii_phy(struct tg3
*tp
, int force_reset
)
4017 int current_link_up
, err
= 0;
4021 u32 local_adv
, remote_adv
;
4023 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
4024 tw32_f(MAC_MODE
, tp
->mac_mode
);
4030 (MAC_STATUS_SYNC_CHANGED
|
4031 MAC_STATUS_CFG_CHANGED
|
4032 MAC_STATUS_MI_COMPLETION
|
4033 MAC_STATUS_LNKSTATE_CHANGED
));
4039 current_link_up
= 0;
4040 current_speed
= SPEED_INVALID
;
4041 current_duplex
= DUPLEX_INVALID
;
4043 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4044 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4045 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
4046 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
4047 bmsr
|= BMSR_LSTATUS
;
4049 bmsr
&= ~BMSR_LSTATUS
;
4052 err
|= tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4054 if ((tp
->link_config
.autoneg
== AUTONEG_ENABLE
) && !force_reset
&&
4055 (tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
)) {
4056 /* do nothing, just check for link up at the end */
4057 } else if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
4060 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
4061 new_adv
= adv
& ~(ADVERTISE_1000XFULL
| ADVERTISE_1000XHALF
|
4062 ADVERTISE_1000XPAUSE
|
4063 ADVERTISE_1000XPSE_ASYM
|
4066 new_adv
|= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
4068 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
4069 new_adv
|= ADVERTISE_1000XHALF
;
4070 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
4071 new_adv
|= ADVERTISE_1000XFULL
;
4073 if ((new_adv
!= adv
) || !(bmcr
& BMCR_ANENABLE
)) {
4074 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
4075 bmcr
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
4076 tg3_writephy(tp
, MII_BMCR
, bmcr
);
4078 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
4079 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5714S
;
4080 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4087 bmcr
&= ~BMCR_SPEED1000
;
4088 new_bmcr
= bmcr
& ~(BMCR_ANENABLE
| BMCR_FULLDPLX
);
4090 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
4091 new_bmcr
|= BMCR_FULLDPLX
;
4093 if (new_bmcr
!= bmcr
) {
4094 /* BMCR_SPEED1000 is a reserved bit that needs
4095 * to be set on write.
4097 new_bmcr
|= BMCR_SPEED1000
;
4099 /* Force a linkdown */
4100 if (netif_carrier_ok(tp
->dev
)) {
4103 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
4104 adv
&= ~(ADVERTISE_1000XFULL
|
4105 ADVERTISE_1000XHALF
|
4107 tg3_writephy(tp
, MII_ADVERTISE
, adv
);
4108 tg3_writephy(tp
, MII_BMCR
, bmcr
|
4112 netif_carrier_off(tp
->dev
);
4114 tg3_writephy(tp
, MII_BMCR
, new_bmcr
);
4116 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4117 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4118 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
4120 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
4121 bmsr
|= BMSR_LSTATUS
;
4123 bmsr
&= ~BMSR_LSTATUS
;
4125 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4129 if (bmsr
& BMSR_LSTATUS
) {
4130 current_speed
= SPEED_1000
;
4131 current_link_up
= 1;
4132 if (bmcr
& BMCR_FULLDPLX
)
4133 current_duplex
= DUPLEX_FULL
;
4135 current_duplex
= DUPLEX_HALF
;
4140 if (bmcr
& BMCR_ANENABLE
) {
4143 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &local_adv
);
4144 err
|= tg3_readphy(tp
, MII_LPA
, &remote_adv
);
4145 common
= local_adv
& remote_adv
;
4146 if (common
& (ADVERTISE_1000XHALF
|
4147 ADVERTISE_1000XFULL
)) {
4148 if (common
& ADVERTISE_1000XFULL
)
4149 current_duplex
= DUPLEX_FULL
;
4151 current_duplex
= DUPLEX_HALF
;
4154 current_link_up
= 0;
4158 if (current_link_up
== 1 && current_duplex
== DUPLEX_FULL
)
4159 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
4161 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
4162 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
4163 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
4165 tw32_f(MAC_MODE
, tp
->mac_mode
);
4168 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
4170 tp
->link_config
.active_speed
= current_speed
;
4171 tp
->link_config
.active_duplex
= current_duplex
;
4173 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
4174 if (current_link_up
)
4175 netif_carrier_on(tp
->dev
);
4177 netif_carrier_off(tp
->dev
);
4178 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4180 tg3_link_report(tp
);
4185 static void tg3_serdes_parallel_detect(struct tg3
*tp
)
4187 if (tp
->serdes_counter
) {
4188 /* Give autoneg time to complete. */
4189 tp
->serdes_counter
--;
4192 if (!netif_carrier_ok(tp
->dev
) &&
4193 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
)) {
4196 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4197 if (bmcr
& BMCR_ANENABLE
) {
4200 /* Select shadow register 0x1f */
4201 tg3_writephy(tp
, 0x1c, 0x7c00);
4202 tg3_readphy(tp
, 0x1c, &phy1
);
4204 /* Select expansion interrupt status register */
4205 tg3_writephy(tp
, 0x17, 0x0f01);
4206 tg3_readphy(tp
, 0x15, &phy2
);
4207 tg3_readphy(tp
, 0x15, &phy2
);
4209 if ((phy1
& 0x10) && !(phy2
& 0x20)) {
4210 /* We have signal detect and not receiving
4211 * config code words, link is up by parallel
4215 bmcr
&= ~BMCR_ANENABLE
;
4216 bmcr
|= BMCR_SPEED1000
| BMCR_FULLDPLX
;
4217 tg3_writephy(tp
, MII_BMCR
, bmcr
);
4218 tp
->tg3_flags2
|= TG3_FLG2_PARALLEL_DETECT
;
4222 else if (netif_carrier_ok(tp
->dev
) &&
4223 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) &&
4224 (tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
)) {
4227 /* Select expansion interrupt status register */
4228 tg3_writephy(tp
, 0x17, 0x0f01);
4229 tg3_readphy(tp
, 0x15, &phy2
);
4233 /* Config code words received, turn on autoneg. */
4234 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4235 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANENABLE
);
4237 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4243 static int tg3_setup_phy(struct tg3
*tp
, int force_reset
)
4247 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
4248 err
= tg3_setup_fiber_phy(tp
, force_reset
);
4249 } else if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
4250 err
= tg3_setup_fiber_mii_phy(tp
, force_reset
);
4252 err
= tg3_setup_copper_phy(tp
, force_reset
);
4255 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
) {
4258 val
= tr32(TG3_CPMU_CLCK_STAT
) & CPMU_CLCK_STAT_MAC_CLCK_MASK
;
4259 if (val
== CPMU_CLCK_STAT_MAC_CLCK_62_5
)
4261 else if (val
== CPMU_CLCK_STAT_MAC_CLCK_6_25
)
4266 val
= tr32(GRC_MISC_CFG
) & ~GRC_MISC_CFG_PRESCALAR_MASK
;
4267 val
|= (scale
<< GRC_MISC_CFG_PRESCALAR_SHIFT
);
4268 tw32(GRC_MISC_CFG
, val
);
4271 if (tp
->link_config
.active_speed
== SPEED_1000
&&
4272 tp
->link_config
.active_duplex
== DUPLEX_HALF
)
4273 tw32(MAC_TX_LENGTHS
,
4274 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
4275 (6 << TX_LENGTHS_IPG_SHIFT
) |
4276 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
4278 tw32(MAC_TX_LENGTHS
,
4279 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
4280 (6 << TX_LENGTHS_IPG_SHIFT
) |
4281 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
4283 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
4284 if (netif_carrier_ok(tp
->dev
)) {
4285 tw32(HOSTCC_STAT_COAL_TICKS
,
4286 tp
->coal
.stats_block_coalesce_usecs
);
4288 tw32(HOSTCC_STAT_COAL_TICKS
, 0);
4292 if (tp
->tg3_flags
& TG3_FLAG_ASPM_WORKAROUND
) {
4293 u32 val
= tr32(PCIE_PWR_MGMT_THRESH
);
4294 if (!netif_carrier_ok(tp
->dev
))
4295 val
= (val
& ~PCIE_PWR_MGMT_L1_THRESH_MSK
) |
4298 val
|= PCIE_PWR_MGMT_L1_THRESH_MSK
;
4299 tw32(PCIE_PWR_MGMT_THRESH
, val
);
4305 /* This is called whenever we suspect that the system chipset is re-
4306 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4307 * is bogus tx completions. We try to recover by setting the
4308 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4311 static void tg3_tx_recover(struct tg3
*tp
)
4313 BUG_ON((tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
) ||
4314 tp
->write32_tx_mbox
== tg3_write_indirect_mbox
);
4316 printk(KERN_WARNING PFX
"%s: The system may be re-ordering memory-"
4317 "mapped I/O cycles to the network device, attempting to "
4318 "recover. Please report the problem to the driver maintainer "
4319 "and include system chipset information.\n", tp
->dev
->name
);
4321 spin_lock(&tp
->lock
);
4322 tp
->tg3_flags
|= TG3_FLAG_TX_RECOVERY_PENDING
;
4323 spin_unlock(&tp
->lock
);
4326 static inline u32
tg3_tx_avail(struct tg3_napi
*tnapi
)
4329 return tnapi
->tx_pending
-
4330 ((tnapi
->tx_prod
- tnapi
->tx_cons
) & (TG3_TX_RING_SIZE
- 1));
4333 /* Tigon3 never reports partial packet sends. So we do not
4334 * need special logic to handle SKBs that have not had all
4335 * of their frags sent yet, like SunGEM does.
4337 static void tg3_tx(struct tg3_napi
*tnapi
)
4339 struct tg3
*tp
= tnapi
->tp
;
4340 u32 hw_idx
= tnapi
->hw_status
->idx
[0].tx_consumer
;
4341 u32 sw_idx
= tnapi
->tx_cons
;
4342 struct netdev_queue
*txq
;
4343 int index
= tnapi
- tp
->napi
;
4345 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)
4348 txq
= netdev_get_tx_queue(tp
->dev
, index
);
4350 while (sw_idx
!= hw_idx
) {
4351 struct tx_ring_info
*ri
= &tnapi
->tx_buffers
[sw_idx
];
4352 struct sk_buff
*skb
= ri
->skb
;
4355 if (unlikely(skb
== NULL
)) {
4360 skb_dma_unmap(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
);
4364 sw_idx
= NEXT_TX(sw_idx
);
4366 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
4367 ri
= &tnapi
->tx_buffers
[sw_idx
];
4368 if (unlikely(ri
->skb
!= NULL
|| sw_idx
== hw_idx
))
4370 sw_idx
= NEXT_TX(sw_idx
);
4375 if (unlikely(tx_bug
)) {
4381 tnapi
->tx_cons
= sw_idx
;
4383 /* Need to make the tx_cons update visible to tg3_start_xmit()
4384 * before checking for netif_queue_stopped(). Without the
4385 * memory barrier, there is a small possibility that tg3_start_xmit()
4386 * will miss it and cause the queue to be stopped forever.
4390 if (unlikely(netif_tx_queue_stopped(txq
) &&
4391 (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
)))) {
4392 __netif_tx_lock(txq
, smp_processor_id());
4393 if (netif_tx_queue_stopped(txq
) &&
4394 (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
)))
4395 netif_tx_wake_queue(txq
);
4396 __netif_tx_unlock(txq
);
4400 /* Returns size of skb allocated or < 0 on error.
4402 * We only need to fill in the address because the other members
4403 * of the RX descriptor are invariant, see tg3_init_rings.
4405 * Note the purposeful assymetry of cpu vs. chip accesses. For
4406 * posting buffers we only dirty the first cache line of the RX
4407 * descriptor (containing the address). Whereas for the RX status
4408 * buffers the cpu only reads the last cacheline of the RX descriptor
4409 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4411 static int tg3_alloc_rx_skb(struct tg3_napi
*tnapi
, u32 opaque_key
,
4412 int src_idx
, u32 dest_idx_unmasked
)
4414 struct tg3
*tp
= tnapi
->tp
;
4415 struct tg3_rx_buffer_desc
*desc
;
4416 struct ring_info
*map
, *src_map
;
4417 struct sk_buff
*skb
;
4419 int skb_size
, dest_idx
;
4420 struct tg3_rx_prodring_set
*tpr
= &tp
->prodring
[0];
4423 switch (opaque_key
) {
4424 case RXD_OPAQUE_RING_STD
:
4425 dest_idx
= dest_idx_unmasked
% TG3_RX_RING_SIZE
;
4426 desc
= &tpr
->rx_std
[dest_idx
];
4427 map
= &tpr
->rx_std_buffers
[dest_idx
];
4429 src_map
= &tpr
->rx_std_buffers
[src_idx
];
4430 skb_size
= tp
->rx_pkt_map_sz
;
4433 case RXD_OPAQUE_RING_JUMBO
:
4434 dest_idx
= dest_idx_unmasked
% TG3_RX_JUMBO_RING_SIZE
;
4435 desc
= &tpr
->rx_jmb
[dest_idx
].std
;
4436 map
= &tpr
->rx_jmb_buffers
[dest_idx
];
4438 src_map
= &tpr
->rx_jmb_buffers
[src_idx
];
4439 skb_size
= TG3_RX_JMB_MAP_SZ
;
4446 /* Do not overwrite any of the map or rp information
4447 * until we are sure we can commit to a new buffer.
4449 * Callers depend upon this behavior and assume that
4450 * we leave everything unchanged if we fail.
4452 skb
= netdev_alloc_skb(tp
->dev
, skb_size
+ tp
->rx_offset
);
4456 skb_reserve(skb
, tp
->rx_offset
);
4458 mapping
= pci_map_single(tp
->pdev
, skb
->data
, skb_size
,
4459 PCI_DMA_FROMDEVICE
);
4460 if (pci_dma_mapping_error(tp
->pdev
, mapping
)) {
4466 pci_unmap_addr_set(map
, mapping
, mapping
);
4468 if (src_map
!= NULL
)
4469 src_map
->skb
= NULL
;
4471 desc
->addr_hi
= ((u64
)mapping
>> 32);
4472 desc
->addr_lo
= ((u64
)mapping
& 0xffffffff);
4477 /* We only need to move over in the address because the other
4478 * members of the RX descriptor are invariant. See notes above
4479 * tg3_alloc_rx_skb for full details.
4481 static void tg3_recycle_rx(struct tg3_napi
*tnapi
, u32 opaque_key
,
4482 int src_idx
, u32 dest_idx_unmasked
)
4484 struct tg3
*tp
= tnapi
->tp
;
4485 struct tg3_rx_buffer_desc
*src_desc
, *dest_desc
;
4486 struct ring_info
*src_map
, *dest_map
;
4488 struct tg3_rx_prodring_set
*tpr
= &tp
->prodring
[0];
4490 switch (opaque_key
) {
4491 case RXD_OPAQUE_RING_STD
:
4492 dest_idx
= dest_idx_unmasked
% TG3_RX_RING_SIZE
;
4493 dest_desc
= &tpr
->rx_std
[dest_idx
];
4494 dest_map
= &tpr
->rx_std_buffers
[dest_idx
];
4495 src_desc
= &tpr
->rx_std
[src_idx
];
4496 src_map
= &tpr
->rx_std_buffers
[src_idx
];
4499 case RXD_OPAQUE_RING_JUMBO
:
4500 dest_idx
= dest_idx_unmasked
% TG3_RX_JUMBO_RING_SIZE
;
4501 dest_desc
= &tpr
->rx_jmb
[dest_idx
].std
;
4502 dest_map
= &tpr
->rx_jmb_buffers
[dest_idx
];
4503 src_desc
= &tpr
->rx_jmb
[src_idx
].std
;
4504 src_map
= &tpr
->rx_jmb_buffers
[src_idx
];
4511 dest_map
->skb
= src_map
->skb
;
4512 pci_unmap_addr_set(dest_map
, mapping
,
4513 pci_unmap_addr(src_map
, mapping
));
4514 dest_desc
->addr_hi
= src_desc
->addr_hi
;
4515 dest_desc
->addr_lo
= src_desc
->addr_lo
;
4517 src_map
->skb
= NULL
;
4520 /* The RX ring scheme is composed of multiple rings which post fresh
4521 * buffers to the chip, and one special ring the chip uses to report
4522 * status back to the host.
4524 * The special ring reports the status of received packets to the
4525 * host. The chip does not write into the original descriptor the
4526 * RX buffer was obtained from. The chip simply takes the original
4527 * descriptor as provided by the host, updates the status and length
4528 * field, then writes this into the next status ring entry.
4530 * Each ring the host uses to post buffers to the chip is described
4531 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4532 * it is first placed into the on-chip ram. When the packet's length
4533 * is known, it walks down the TG3_BDINFO entries to select the ring.
4534 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4535 * which is within the range of the new packet's length is chosen.
4537 * The "separate ring for rx status" scheme may sound queer, but it makes
4538 * sense from a cache coherency perspective. If only the host writes
4539 * to the buffer post rings, and only the chip writes to the rx status
4540 * rings, then cache lines never move beyond shared-modified state.
4541 * If both the host and chip were to write into the same ring, cache line
4542 * eviction could occur since both entities want it in an exclusive state.
4544 static int tg3_rx(struct tg3_napi
*tnapi
, int budget
)
4546 struct tg3
*tp
= tnapi
->tp
;
4547 u32 work_mask
, rx_std_posted
= 0;
4548 u32 sw_idx
= tnapi
->rx_rcb_ptr
;
4551 struct tg3_rx_prodring_set
*tpr
= &tp
->prodring
[0];
4553 hw_idx
= *(tnapi
->rx_rcb_prod_idx
);
4555 * We need to order the read of hw_idx and the read of
4556 * the opaque cookie.
4561 while (sw_idx
!= hw_idx
&& budget
> 0) {
4562 struct tg3_rx_buffer_desc
*desc
= &tnapi
->rx_rcb
[sw_idx
];
4564 struct sk_buff
*skb
;
4565 dma_addr_t dma_addr
;
4566 u32 opaque_key
, desc_idx
, *post_ptr
;
4568 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
4569 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
4570 if (opaque_key
== RXD_OPAQUE_RING_STD
) {
4571 struct ring_info
*ri
= &tpr
->rx_std_buffers
[desc_idx
];
4572 dma_addr
= pci_unmap_addr(ri
, mapping
);
4574 post_ptr
= &tpr
->rx_std_ptr
;
4576 } else if (opaque_key
== RXD_OPAQUE_RING_JUMBO
) {
4577 struct ring_info
*ri
= &tpr
->rx_jmb_buffers
[desc_idx
];
4578 dma_addr
= pci_unmap_addr(ri
, mapping
);
4580 post_ptr
= &tpr
->rx_jmb_ptr
;
4582 goto next_pkt_nopost
;
4584 work_mask
|= opaque_key
;
4586 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
4587 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
)) {
4589 tg3_recycle_rx(tnapi
, opaque_key
,
4590 desc_idx
, *post_ptr
);
4592 /* Other statistics kept track of by card. */
4593 tp
->net_stats
.rx_dropped
++;
4597 len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) -
4600 if (len
> RX_COPY_THRESHOLD
4601 && tp
->rx_offset
== NET_IP_ALIGN
4602 /* rx_offset will likely not equal NET_IP_ALIGN
4603 * if this is a 5701 card running in PCI-X mode
4604 * [see tg3_get_invariants()]
4609 skb_size
= tg3_alloc_rx_skb(tnapi
, opaque_key
,
4610 desc_idx
, *post_ptr
);
4614 pci_unmap_single(tp
->pdev
, dma_addr
, skb_size
,
4615 PCI_DMA_FROMDEVICE
);
4619 struct sk_buff
*copy_skb
;
4621 tg3_recycle_rx(tnapi
, opaque_key
,
4622 desc_idx
, *post_ptr
);
4624 copy_skb
= netdev_alloc_skb(tp
->dev
,
4625 len
+ TG3_RAW_IP_ALIGN
);
4626 if (copy_skb
== NULL
)
4627 goto drop_it_no_recycle
;
4629 skb_reserve(copy_skb
, TG3_RAW_IP_ALIGN
);
4630 skb_put(copy_skb
, len
);
4631 pci_dma_sync_single_for_cpu(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
4632 skb_copy_from_linear_data(skb
, copy_skb
->data
, len
);
4633 pci_dma_sync_single_for_device(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
4635 /* We'll reuse the original ring buffer. */
4639 if ((tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) &&
4640 (desc
->type_flags
& RXD_FLAG_TCPUDP_CSUM
) &&
4641 (((desc
->ip_tcp_csum
& RXD_TCPCSUM_MASK
)
4642 >> RXD_TCPCSUM_SHIFT
) == 0xffff))
4643 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
4645 skb
->ip_summed
= CHECKSUM_NONE
;
4647 skb
->protocol
= eth_type_trans(skb
, tp
->dev
);
4649 if (len
> (tp
->dev
->mtu
+ ETH_HLEN
) &&
4650 skb
->protocol
!= htons(ETH_P_8021Q
)) {
4655 #if TG3_VLAN_TAG_USED
4656 if (tp
->vlgrp
!= NULL
&&
4657 desc
->type_flags
& RXD_FLAG_VLAN
) {
4658 vlan_gro_receive(&tnapi
->napi
, tp
->vlgrp
,
4659 desc
->err_vlan
& RXD_VLAN_MASK
, skb
);
4662 napi_gro_receive(&tnapi
->napi
, skb
);
4670 if (unlikely(rx_std_posted
>= tp
->rx_std_max_post
)) {
4671 u32 idx
= *post_ptr
% TG3_RX_RING_SIZE
;
4673 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX
+
4674 TG3_64BIT_REG_LOW
, idx
);
4675 work_mask
&= ~RXD_OPAQUE_RING_STD
;
4680 sw_idx
&= (TG3_RX_RCB_RING_SIZE(tp
) - 1);
4682 /* Refresh hw_idx to see if there is new work */
4683 if (sw_idx
== hw_idx
) {
4684 hw_idx
= *(tnapi
->rx_rcb_prod_idx
);
4689 /* ACK the status ring. */
4690 tnapi
->rx_rcb_ptr
= sw_idx
;
4691 tw32_rx_mbox(tnapi
->consmbox
, sw_idx
);
4693 /* Refill RX ring(s). */
4694 if (work_mask
& RXD_OPAQUE_RING_STD
) {
4695 sw_idx
= tpr
->rx_std_ptr
% TG3_RX_RING_SIZE
;
4696 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX
+ TG3_64BIT_REG_LOW
,
4699 if (work_mask
& RXD_OPAQUE_RING_JUMBO
) {
4700 sw_idx
= tpr
->rx_jmb_ptr
% TG3_RX_JUMBO_RING_SIZE
;
4701 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX
+ TG3_64BIT_REG_LOW
,
4709 static int tg3_poll_work(struct tg3_napi
*tnapi
, int work_done
, int budget
)
4711 struct tg3
*tp
= tnapi
->tp
;
4712 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
4714 /* handle link change and other phy events */
4715 if (!(tp
->tg3_flags
&
4716 (TG3_FLAG_USE_LINKCHG_REG
|
4717 TG3_FLAG_POLL_SERDES
))) {
4718 if (sblk
->status
& SD_STATUS_LINK_CHG
) {
4719 sblk
->status
= SD_STATUS_UPDATED
|
4720 (sblk
->status
& ~SD_STATUS_LINK_CHG
);
4721 spin_lock(&tp
->lock
);
4722 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
4724 (MAC_STATUS_SYNC_CHANGED
|
4725 MAC_STATUS_CFG_CHANGED
|
4726 MAC_STATUS_MI_COMPLETION
|
4727 MAC_STATUS_LNKSTATE_CHANGED
));
4730 tg3_setup_phy(tp
, 0);
4731 spin_unlock(&tp
->lock
);
4735 /* run TX completion thread */
4736 if (tnapi
->hw_status
->idx
[0].tx_consumer
!= tnapi
->tx_cons
) {
4738 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
4742 /* run RX thread, within the bounds set by NAPI.
4743 * All RX "locking" is done by ensuring outside
4744 * code synchronizes with tg3->napi.poll()
4746 if (*(tnapi
->rx_rcb_prod_idx
) != tnapi
->rx_rcb_ptr
)
4747 work_done
+= tg3_rx(tnapi
, budget
- work_done
);
4752 static int tg3_poll(struct napi_struct
*napi
, int budget
)
4754 struct tg3_napi
*tnapi
= container_of(napi
, struct tg3_napi
, napi
);
4755 struct tg3
*tp
= tnapi
->tp
;
4757 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
4760 work_done
= tg3_poll_work(tnapi
, work_done
, budget
);
4762 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
4765 if (unlikely(work_done
>= budget
))
4768 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
4769 /* tp->last_tag is used in tg3_int_reenable() below
4770 * to tell the hw how much work has been processed,
4771 * so we must read it before checking for more work.
4773 tnapi
->last_tag
= sblk
->status_tag
;
4774 tnapi
->last_irq_tag
= tnapi
->last_tag
;
4777 sblk
->status
&= ~SD_STATUS_UPDATED
;
4779 if (likely(!tg3_has_work(tnapi
))) {
4780 napi_complete(napi
);
4781 tg3_int_reenable(tnapi
);
4789 /* work_done is guaranteed to be less than budget. */
4790 napi_complete(napi
);
4791 schedule_work(&tp
->reset_task
);
4795 static void tg3_irq_quiesce(struct tg3
*tp
)
4799 BUG_ON(tp
->irq_sync
);
4804 for (i
= 0; i
< tp
->irq_cnt
; i
++)
4805 synchronize_irq(tp
->napi
[i
].irq_vec
);
4808 static inline int tg3_irq_sync(struct tg3
*tp
)
4810 return tp
->irq_sync
;
4813 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4814 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4815 * with as well. Most of the time, this is not necessary except when
4816 * shutting down the device.
4818 static inline void tg3_full_lock(struct tg3
*tp
, int irq_sync
)
4820 spin_lock_bh(&tp
->lock
);
4822 tg3_irq_quiesce(tp
);
4825 static inline void tg3_full_unlock(struct tg3
*tp
)
4827 spin_unlock_bh(&tp
->lock
);
4830 /* One-shot MSI handler - Chip automatically disables interrupt
4831 * after sending MSI so driver doesn't have to do it.
4833 static irqreturn_t
tg3_msi_1shot(int irq
, void *dev_id
)
4835 struct tg3_napi
*tnapi
= dev_id
;
4836 struct tg3
*tp
= tnapi
->tp
;
4838 prefetch(tnapi
->hw_status
);
4840 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
4842 if (likely(!tg3_irq_sync(tp
)))
4843 napi_schedule(&tnapi
->napi
);
4848 /* MSI ISR - No need to check for interrupt sharing and no need to
4849 * flush status block and interrupt mailbox. PCI ordering rules
4850 * guarantee that MSI will arrive after the status block.
4852 static irqreturn_t
tg3_msi(int irq
, void *dev_id
)
4854 struct tg3_napi
*tnapi
= dev_id
;
4855 struct tg3
*tp
= tnapi
->tp
;
4857 prefetch(tnapi
->hw_status
);
4859 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
4861 * Writing any value to intr-mbox-0 clears PCI INTA# and
4862 * chip-internal interrupt pending events.
4863 * Writing non-zero to intr-mbox-0 additional tells the
4864 * NIC to stop sending us irqs, engaging "in-intr-handler"
4867 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
4868 if (likely(!tg3_irq_sync(tp
)))
4869 napi_schedule(&tnapi
->napi
);
4871 return IRQ_RETVAL(1);
4874 static irqreturn_t
tg3_interrupt(int irq
, void *dev_id
)
4876 struct tg3_napi
*tnapi
= dev_id
;
4877 struct tg3
*tp
= tnapi
->tp
;
4878 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
4879 unsigned int handled
= 1;
4881 /* In INTx mode, it is possible for the interrupt to arrive at
4882 * the CPU before the status block posted prior to the interrupt.
4883 * Reading the PCI State register will confirm whether the
4884 * interrupt is ours and will flush the status block.
4886 if (unlikely(!(sblk
->status
& SD_STATUS_UPDATED
))) {
4887 if ((tp
->tg3_flags
& TG3_FLAG_CHIP_RESETTING
) ||
4888 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
4895 * Writing any value to intr-mbox-0 clears PCI INTA# and
4896 * chip-internal interrupt pending events.
4897 * Writing non-zero to intr-mbox-0 additional tells the
4898 * NIC to stop sending us irqs, engaging "in-intr-handler"
4901 * Flush the mailbox to de-assert the IRQ immediately to prevent
4902 * spurious interrupts. The flush impacts performance but
4903 * excessive spurious interrupts can be worse in some cases.
4905 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
4906 if (tg3_irq_sync(tp
))
4908 sblk
->status
&= ~SD_STATUS_UPDATED
;
4909 if (likely(tg3_has_work(tnapi
))) {
4910 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
4911 napi_schedule(&tnapi
->napi
);
4913 /* No work, shared interrupt perhaps? re-enable
4914 * interrupts, and flush that PCI write
4916 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
4920 return IRQ_RETVAL(handled
);
4923 static irqreturn_t
tg3_interrupt_tagged(int irq
, void *dev_id
)
4925 struct tg3_napi
*tnapi
= dev_id
;
4926 struct tg3
*tp
= tnapi
->tp
;
4927 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
4928 unsigned int handled
= 1;
4930 /* In INTx mode, it is possible for the interrupt to arrive at
4931 * the CPU before the status block posted prior to the interrupt.
4932 * Reading the PCI State register will confirm whether the
4933 * interrupt is ours and will flush the status block.
4935 if (unlikely(sblk
->status_tag
== tnapi
->last_irq_tag
)) {
4936 if ((tp
->tg3_flags
& TG3_FLAG_CHIP_RESETTING
) ||
4937 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
4944 * writing any value to intr-mbox-0 clears PCI INTA# and
4945 * chip-internal interrupt pending events.
4946 * writing non-zero to intr-mbox-0 additional tells the
4947 * NIC to stop sending us irqs, engaging "in-intr-handler"
4950 * Flush the mailbox to de-assert the IRQ immediately to prevent
4951 * spurious interrupts. The flush impacts performance but
4952 * excessive spurious interrupts can be worse in some cases.
4954 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
4957 * In a shared interrupt configuration, sometimes other devices'
4958 * interrupts will scream. We record the current status tag here
4959 * so that the above check can report that the screaming interrupts
4960 * are unhandled. Eventually they will be silenced.
4962 tnapi
->last_irq_tag
= sblk
->status_tag
;
4964 if (tg3_irq_sync(tp
))
4967 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
4969 napi_schedule(&tnapi
->napi
);
4972 return IRQ_RETVAL(handled
);
4975 /* ISR for interrupt test */
4976 static irqreturn_t
tg3_test_isr(int irq
, void *dev_id
)
4978 struct tg3_napi
*tnapi
= dev_id
;
4979 struct tg3
*tp
= tnapi
->tp
;
4980 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
4982 if ((sblk
->status
& SD_STATUS_UPDATED
) ||
4983 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
4984 tg3_disable_ints(tp
);
4985 return IRQ_RETVAL(1);
4987 return IRQ_RETVAL(0);
4990 static int tg3_init_hw(struct tg3
*, int);
4991 static int tg3_halt(struct tg3
*, int, int);
4993 /* Restart hardware after configuration changes, self-test, etc.
4994 * Invoked with tp->lock held.
4996 static int tg3_restart_hw(struct tg3
*tp
, int reset_phy
)
4997 __releases(tp
->lock
)
4998 __acquires(tp
->lock
)
5002 err
= tg3_init_hw(tp
, reset_phy
);
5004 printk(KERN_ERR PFX
"%s: Failed to re-initialize device, "
5005 "aborting.\n", tp
->dev
->name
);
5006 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
5007 tg3_full_unlock(tp
);
5008 del_timer_sync(&tp
->timer
);
5010 tg3_napi_enable(tp
);
5012 tg3_full_lock(tp
, 0);
5017 #ifdef CONFIG_NET_POLL_CONTROLLER
5018 static void tg3_poll_controller(struct net_device
*dev
)
5021 struct tg3
*tp
= netdev_priv(dev
);
5023 for (i
= 0; i
< tp
->irq_cnt
; i
++)
5024 tg3_interrupt(tp
->napi
[i
].irq_vec
, dev
);
5028 static void tg3_reset_task(struct work_struct
*work
)
5030 struct tg3
*tp
= container_of(work
, struct tg3
, reset_task
);
5032 unsigned int restart_timer
;
5034 tg3_full_lock(tp
, 0);
5036 if (!netif_running(tp
->dev
)) {
5037 tg3_full_unlock(tp
);
5041 tg3_full_unlock(tp
);
5047 tg3_full_lock(tp
, 1);
5049 restart_timer
= tp
->tg3_flags2
& TG3_FLG2_RESTART_TIMER
;
5050 tp
->tg3_flags2
&= ~TG3_FLG2_RESTART_TIMER
;
5052 if (tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
) {
5053 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
5054 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
5055 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
5056 tp
->tg3_flags
&= ~TG3_FLAG_TX_RECOVERY_PENDING
;
5059 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 0);
5060 err
= tg3_init_hw(tp
, 1);
5064 tg3_netif_start(tp
);
5067 mod_timer(&tp
->timer
, jiffies
+ 1);
5070 tg3_full_unlock(tp
);
5076 static void tg3_dump_short_state(struct tg3
*tp
)
5078 printk(KERN_ERR PFX
"DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5079 tr32(MAC_TX_STATUS
), tr32(MAC_RX_STATUS
));
5080 printk(KERN_ERR PFX
"DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5081 tr32(RDMAC_STATUS
), tr32(WDMAC_STATUS
));
5084 static void tg3_tx_timeout(struct net_device
*dev
)
5086 struct tg3
*tp
= netdev_priv(dev
);
5088 if (netif_msg_tx_err(tp
)) {
5089 printk(KERN_ERR PFX
"%s: transmit timed out, resetting\n",
5091 tg3_dump_short_state(tp
);
5094 schedule_work(&tp
->reset_task
);
5097 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5098 static inline int tg3_4g_overflow_test(dma_addr_t mapping
, int len
)
5100 u32 base
= (u32
) mapping
& 0xffffffff;
5102 return ((base
> 0xffffdcc0) &&
5103 (base
+ len
+ 8 < base
));
5106 /* Test for DMA addresses > 40-bit */
5107 static inline int tg3_40bit_overflow_test(struct tg3
*tp
, dma_addr_t mapping
,
5110 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5111 if (tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
)
5112 return (((u64
) mapping
+ len
) > DMA_BIT_MASK(40));
5119 static void tg3_set_txd(struct tg3_napi
*, int, dma_addr_t
, int, u32
, u32
);
5121 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5122 static int tigon3_dma_hwbug_workaround(struct tg3
*tp
, struct sk_buff
*skb
,
5123 u32 last_plus_one
, u32
*start
,
5124 u32 base_flags
, u32 mss
)
5126 struct tg3_napi
*tnapi
= &tp
->napi
[0];
5127 struct sk_buff
*new_skb
;
5128 dma_addr_t new_addr
= 0;
5132 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
5133 new_skb
= skb_copy(skb
, GFP_ATOMIC
);
5135 int more_headroom
= 4 - ((unsigned long)skb
->data
& 3);
5137 new_skb
= skb_copy_expand(skb
,
5138 skb_headroom(skb
) + more_headroom
,
5139 skb_tailroom(skb
), GFP_ATOMIC
);
5145 /* New SKB is guaranteed to be linear. */
5147 ret
= skb_dma_map(&tp
->pdev
->dev
, new_skb
, DMA_TO_DEVICE
);
5148 new_addr
= skb_shinfo(new_skb
)->dma_head
;
5150 /* Make sure new skb does not cross any 4G boundaries.
5151 * Drop the packet if it does.
5153 if (ret
|| ((tp
->tg3_flags3
& TG3_FLG3_4G_DMA_BNDRY_BUG
) &&
5154 tg3_4g_overflow_test(new_addr
, new_skb
->len
))) {
5156 skb_dma_unmap(&tp
->pdev
->dev
, new_skb
,
5159 dev_kfree_skb(new_skb
);
5162 tg3_set_txd(tnapi
, entry
, new_addr
, new_skb
->len
,
5163 base_flags
, 1 | (mss
<< 1));
5164 *start
= NEXT_TX(entry
);
5168 /* Now clean up the sw ring entries. */
5170 while (entry
!= last_plus_one
) {
5172 tnapi
->tx_buffers
[entry
].skb
= new_skb
;
5174 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5175 entry
= NEXT_TX(entry
);
5179 skb_dma_unmap(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
);
5185 static void tg3_set_txd(struct tg3_napi
*tnapi
, int entry
,
5186 dma_addr_t mapping
, int len
, u32 flags
,
5189 struct tg3_tx_buffer_desc
*txd
= &tnapi
->tx_ring
[entry
];
5190 int is_end
= (mss_and_is_end
& 0x1);
5191 u32 mss
= (mss_and_is_end
>> 1);
5195 flags
|= TXD_FLAG_END
;
5196 if (flags
& TXD_FLAG_VLAN
) {
5197 vlan_tag
= flags
>> 16;
5200 vlan_tag
|= (mss
<< TXD_MSS_SHIFT
);
5202 txd
->addr_hi
= ((u64
) mapping
>> 32);
5203 txd
->addr_lo
= ((u64
) mapping
& 0xffffffff);
5204 txd
->len_flags
= (len
<< TXD_LEN_SHIFT
) | flags
;
5205 txd
->vlan_tag
= vlan_tag
<< TXD_VLAN_TAG_SHIFT
;
5208 /* hard_start_xmit for devices that don't have any bugs and
5209 * support TG3_FLG2_HW_TSO_2 only.
5211 static netdev_tx_t
tg3_start_xmit(struct sk_buff
*skb
,
5212 struct net_device
*dev
)
5214 struct tg3
*tp
= netdev_priv(dev
);
5215 u32 len
, entry
, base_flags
, mss
;
5216 struct skb_shared_info
*sp
;
5218 struct tg3_napi
*tnapi
;
5219 struct netdev_queue
*txq
;
5221 txq
= netdev_get_tx_queue(dev
, skb_get_queue_mapping(skb
));
5222 tnapi
= &tp
->napi
[skb_get_queue_mapping(skb
)];
5223 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)
5226 /* We are running in BH disabled context with netif_tx_lock
5227 * and TX reclaim runs via tp->napi.poll inside of a software
5228 * interrupt. Furthermore, IRQ processing runs lockless so we have
5229 * no IRQ context deadlocks to worry about either. Rejoice!
5231 if (unlikely(tg3_tx_avail(tnapi
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
5232 if (!netif_tx_queue_stopped(txq
)) {
5233 netif_tx_stop_queue(txq
);
5235 /* This is a hard error, log it. */
5236 printk(KERN_ERR PFX
"%s: BUG! Tx Ring full when "
5237 "queue awake!\n", dev
->name
);
5239 return NETDEV_TX_BUSY
;
5242 entry
= tnapi
->tx_prod
;
5245 if ((mss
= skb_shinfo(skb
)->gso_size
) != 0) {
5246 int tcp_opt_len
, ip_tcp_len
;
5249 if (skb_header_cloned(skb
) &&
5250 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
5255 if (skb_shinfo(skb
)->gso_type
& SKB_GSO_TCPV6
)
5256 hdrlen
= skb_headlen(skb
) - ETH_HLEN
;
5258 struct iphdr
*iph
= ip_hdr(skb
);
5260 tcp_opt_len
= tcp_optlen(skb
);
5261 ip_tcp_len
= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
5264 iph
->tot_len
= htons(mss
+ ip_tcp_len
+ tcp_opt_len
);
5265 hdrlen
= ip_tcp_len
+ tcp_opt_len
;
5268 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
) {
5269 mss
|= (hdrlen
& 0xc) << 12;
5271 base_flags
|= 0x00000010;
5272 base_flags
|= (hdrlen
& 0x3e0) << 5;
5276 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
5277 TXD_FLAG_CPU_POST_DMA
);
5279 tcp_hdr(skb
)->check
= 0;
5282 else if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
5283 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
5284 #if TG3_VLAN_TAG_USED
5285 if (tp
->vlgrp
!= NULL
&& vlan_tx_tag_present(skb
))
5286 base_flags
|= (TXD_FLAG_VLAN
|
5287 (vlan_tx_tag_get(skb
) << 16));
5290 if (skb_dma_map(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
)) {
5295 sp
= skb_shinfo(skb
);
5297 mapping
= sp
->dma_head
;
5299 tnapi
->tx_buffers
[entry
].skb
= skb
;
5301 len
= skb_headlen(skb
);
5303 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
&&
5304 !mss
&& skb
->len
> ETH_DATA_LEN
)
5305 base_flags
|= TXD_FLAG_JMB_PKT
;
5307 tg3_set_txd(tnapi
, entry
, mapping
, len
, base_flags
,
5308 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
5310 entry
= NEXT_TX(entry
);
5312 /* Now loop through additional data fragments, and queue them. */
5313 if (skb_shinfo(skb
)->nr_frags
> 0) {
5314 unsigned int i
, last
;
5316 last
= skb_shinfo(skb
)->nr_frags
- 1;
5317 for (i
= 0; i
<= last
; i
++) {
5318 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5321 mapping
= sp
->dma_maps
[i
];
5322 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5324 tg3_set_txd(tnapi
, entry
, mapping
, len
,
5325 base_flags
, (i
== last
) | (mss
<< 1));
5327 entry
= NEXT_TX(entry
);
5331 /* Packets are ready, update Tx producer idx local and on card. */
5332 tw32_tx_mbox(tnapi
->prodmbox
, entry
);
5334 tnapi
->tx_prod
= entry
;
5335 if (unlikely(tg3_tx_avail(tnapi
) <= (MAX_SKB_FRAGS
+ 1))) {
5336 netif_tx_stop_queue(txq
);
5337 if (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
))
5338 netif_tx_wake_queue(txq
);
5344 return NETDEV_TX_OK
;
5347 static netdev_tx_t
tg3_start_xmit_dma_bug(struct sk_buff
*,
5348 struct net_device
*);
5350 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5351 * TSO header is greater than 80 bytes.
5353 static int tg3_tso_bug(struct tg3
*tp
, struct sk_buff
*skb
)
5355 struct sk_buff
*segs
, *nskb
;
5356 u32 frag_cnt_est
= skb_shinfo(skb
)->gso_segs
* 3;
5358 /* Estimate the number of fragments in the worst case */
5359 if (unlikely(tg3_tx_avail(&tp
->napi
[0]) <= frag_cnt_est
)) {
5360 netif_stop_queue(tp
->dev
);
5361 if (tg3_tx_avail(&tp
->napi
[0]) <= frag_cnt_est
)
5362 return NETDEV_TX_BUSY
;
5364 netif_wake_queue(tp
->dev
);
5367 segs
= skb_gso_segment(skb
, tp
->dev
->features
& ~NETIF_F_TSO
);
5369 goto tg3_tso_bug_end
;
5375 tg3_start_xmit_dma_bug(nskb
, tp
->dev
);
5381 return NETDEV_TX_OK
;
5384 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5385 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5387 static netdev_tx_t
tg3_start_xmit_dma_bug(struct sk_buff
*skb
,
5388 struct net_device
*dev
)
5390 struct tg3
*tp
= netdev_priv(dev
);
5391 u32 len
, entry
, base_flags
, mss
;
5392 struct skb_shared_info
*sp
;
5393 int would_hit_hwbug
;
5395 struct tg3_napi
*tnapi
= &tp
->napi
[0];
5397 len
= skb_headlen(skb
);
5399 /* We are running in BH disabled context with netif_tx_lock
5400 * and TX reclaim runs via tp->napi.poll inside of a software
5401 * interrupt. Furthermore, IRQ processing runs lockless so we have
5402 * no IRQ context deadlocks to worry about either. Rejoice!
5404 if (unlikely(tg3_tx_avail(tnapi
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
5405 if (!netif_queue_stopped(dev
)) {
5406 netif_stop_queue(dev
);
5408 /* This is a hard error, log it. */
5409 printk(KERN_ERR PFX
"%s: BUG! Tx Ring full when "
5410 "queue awake!\n", dev
->name
);
5412 return NETDEV_TX_BUSY
;
5415 entry
= tnapi
->tx_prod
;
5417 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
5418 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
5420 if ((mss
= skb_shinfo(skb
)->gso_size
) != 0) {
5422 u32 tcp_opt_len
, ip_tcp_len
, hdr_len
;
5424 if (skb_header_cloned(skb
) &&
5425 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
5430 tcp_opt_len
= tcp_optlen(skb
);
5431 ip_tcp_len
= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
5433 hdr_len
= ip_tcp_len
+ tcp_opt_len
;
5434 if (unlikely((ETH_HLEN
+ hdr_len
) > 80) &&
5435 (tp
->tg3_flags2
& TG3_FLG2_TSO_BUG
))
5436 return (tg3_tso_bug(tp
, skb
));
5438 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
5439 TXD_FLAG_CPU_POST_DMA
);
5443 iph
->tot_len
= htons(mss
+ hdr_len
);
5444 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
5445 tcp_hdr(skb
)->check
= 0;
5446 base_flags
&= ~TXD_FLAG_TCPUDP_CSUM
;
5448 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
5453 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
)
5454 mss
|= hdr_len
<< 9;
5455 else if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_1
) ||
5456 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
5457 if (tcp_opt_len
|| iph
->ihl
> 5) {
5460 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
5461 mss
|= (tsflags
<< 11);
5464 if (tcp_opt_len
|| iph
->ihl
> 5) {
5467 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
5468 base_flags
|= tsflags
<< 12;
5472 #if TG3_VLAN_TAG_USED
5473 if (tp
->vlgrp
!= NULL
&& vlan_tx_tag_present(skb
))
5474 base_flags
|= (TXD_FLAG_VLAN
|
5475 (vlan_tx_tag_get(skb
) << 16));
5478 if (skb_dma_map(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
)) {
5483 sp
= skb_shinfo(skb
);
5485 mapping
= sp
->dma_head
;
5487 tnapi
->tx_buffers
[entry
].skb
= skb
;
5489 would_hit_hwbug
= 0;
5491 if ((tp
->tg3_flags3
& TG3_FLG3_SHORT_DMA_BUG
) && len
<= 8)
5492 would_hit_hwbug
= 1;
5494 if ((tp
->tg3_flags3
& TG3_FLG3_4G_DMA_BNDRY_BUG
) &&
5495 tg3_4g_overflow_test(mapping
, len
))
5496 would_hit_hwbug
= 1;
5498 if ((tp
->tg3_flags3
& TG3_FLG3_40BIT_DMA_LIMIT_BUG
) &&
5499 tg3_40bit_overflow_test(tp
, mapping
, len
))
5500 would_hit_hwbug
= 1;
5502 if (tp
->tg3_flags3
& TG3_FLG3_5701_DMA_BUG
)
5503 would_hit_hwbug
= 1;
5505 tg3_set_txd(tnapi
, entry
, mapping
, len
, base_flags
,
5506 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
5508 entry
= NEXT_TX(entry
);
5510 /* Now loop through additional data fragments, and queue them. */
5511 if (skb_shinfo(skb
)->nr_frags
> 0) {
5512 unsigned int i
, last
;
5514 last
= skb_shinfo(skb
)->nr_frags
- 1;
5515 for (i
= 0; i
<= last
; i
++) {
5516 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5519 mapping
= sp
->dma_maps
[i
];
5521 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5523 if ((tp
->tg3_flags3
& TG3_FLG3_SHORT_DMA_BUG
) &&
5525 would_hit_hwbug
= 1;
5527 if ((tp
->tg3_flags3
& TG3_FLG3_4G_DMA_BNDRY_BUG
) &&
5528 tg3_4g_overflow_test(mapping
, len
))
5529 would_hit_hwbug
= 1;
5531 if ((tp
->tg3_flags3
& TG3_FLG3_40BIT_DMA_LIMIT_BUG
) &&
5532 tg3_40bit_overflow_test(tp
, mapping
, len
))
5533 would_hit_hwbug
= 1;
5535 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
5536 tg3_set_txd(tnapi
, entry
, mapping
, len
,
5537 base_flags
, (i
== last
)|(mss
<< 1));
5539 tg3_set_txd(tnapi
, entry
, mapping
, len
,
5540 base_flags
, (i
== last
));
5542 entry
= NEXT_TX(entry
);
5546 if (would_hit_hwbug
) {
5547 u32 last_plus_one
= entry
;
5550 start
= entry
- 1 - skb_shinfo(skb
)->nr_frags
;
5551 start
&= (TG3_TX_RING_SIZE
- 1);
5553 /* If the workaround fails due to memory/mapping
5554 * failure, silently drop this packet.
5556 if (tigon3_dma_hwbug_workaround(tp
, skb
, last_plus_one
,
5557 &start
, base_flags
, mss
))
5563 /* Packets are ready, update Tx producer idx local and on card. */
5564 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
, entry
);
5566 tnapi
->tx_prod
= entry
;
5567 if (unlikely(tg3_tx_avail(tnapi
) <= (MAX_SKB_FRAGS
+ 1))) {
5568 netif_stop_queue(dev
);
5569 if (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
))
5570 netif_wake_queue(tp
->dev
);
5576 return NETDEV_TX_OK
;
5579 static inline void tg3_set_mtu(struct net_device
*dev
, struct tg3
*tp
,
5584 if (new_mtu
> ETH_DATA_LEN
) {
5585 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
5586 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
5587 ethtool_op_set_tso(dev
, 0);
5590 tp
->tg3_flags
|= TG3_FLAG_JUMBO_RING_ENABLE
;
5592 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
5593 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
5594 tp
->tg3_flags
&= ~TG3_FLAG_JUMBO_RING_ENABLE
;
5598 static int tg3_change_mtu(struct net_device
*dev
, int new_mtu
)
5600 struct tg3
*tp
= netdev_priv(dev
);
5603 if (new_mtu
< TG3_MIN_MTU
|| new_mtu
> TG3_MAX_MTU(tp
))
5606 if (!netif_running(dev
)) {
5607 /* We'll just catch it later when the
5610 tg3_set_mtu(dev
, tp
, new_mtu
);
5618 tg3_full_lock(tp
, 1);
5620 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
5622 tg3_set_mtu(dev
, tp
, new_mtu
);
5624 err
= tg3_restart_hw(tp
, 0);
5627 tg3_netif_start(tp
);
5629 tg3_full_unlock(tp
);
5637 static void tg3_rx_prodring_free(struct tg3
*tp
,
5638 struct tg3_rx_prodring_set
*tpr
)
5641 struct ring_info
*rxp
;
5643 for (i
= 0; i
< TG3_RX_RING_SIZE
; i
++) {
5644 rxp
= &tpr
->rx_std_buffers
[i
];
5646 if (rxp
->skb
== NULL
)
5649 pci_unmap_single(tp
->pdev
,
5650 pci_unmap_addr(rxp
, mapping
),
5652 PCI_DMA_FROMDEVICE
);
5653 dev_kfree_skb_any(rxp
->skb
);
5657 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
5658 for (i
= 0; i
< TG3_RX_JUMBO_RING_SIZE
; i
++) {
5659 rxp
= &tpr
->rx_jmb_buffers
[i
];
5661 if (rxp
->skb
== NULL
)
5664 pci_unmap_single(tp
->pdev
,
5665 pci_unmap_addr(rxp
, mapping
),
5667 PCI_DMA_FROMDEVICE
);
5668 dev_kfree_skb_any(rxp
->skb
);
5674 /* Initialize tx/rx rings for packet processing.
5676 * The chip has been shut down and the driver detached from
5677 * the networking, so no interrupts or new tx packets will
5678 * end up in the driver. tp->{tx,}lock are held and thus
5681 static int tg3_rx_prodring_alloc(struct tg3
*tp
,
5682 struct tg3_rx_prodring_set
*tpr
)
5684 u32 i
, rx_pkt_dma_sz
;
5685 struct tg3_napi
*tnapi
= &tp
->napi
[0];
5687 /* Zero out all descriptors. */
5688 memset(tpr
->rx_std
, 0, TG3_RX_RING_BYTES
);
5690 rx_pkt_dma_sz
= TG3_RX_STD_DMA_SZ
;
5691 if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) &&
5692 tp
->dev
->mtu
> ETH_DATA_LEN
)
5693 rx_pkt_dma_sz
= TG3_RX_JMB_DMA_SZ
;
5694 tp
->rx_pkt_map_sz
= TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz
);
5696 /* Initialize invariants of the rings, we only set this
5697 * stuff once. This works because the card does not
5698 * write into the rx buffer posting rings.
5700 for (i
= 0; i
< TG3_RX_RING_SIZE
; i
++) {
5701 struct tg3_rx_buffer_desc
*rxd
;
5703 rxd
= &tpr
->rx_std
[i
];
5704 rxd
->idx_len
= rx_pkt_dma_sz
<< RXD_LEN_SHIFT
;
5705 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
);
5706 rxd
->opaque
= (RXD_OPAQUE_RING_STD
|
5707 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
5710 /* Now allocate fresh SKBs for each rx ring. */
5711 for (i
= 0; i
< tp
->rx_pending
; i
++) {
5712 if (tg3_alloc_rx_skb(tnapi
, RXD_OPAQUE_RING_STD
, -1, i
) < 0) {
5713 printk(KERN_WARNING PFX
5714 "%s: Using a smaller RX standard ring, "
5715 "only %d out of %d buffers were allocated "
5717 tp
->dev
->name
, i
, tp
->rx_pending
);
5725 if (!(tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
))
5728 memset(tpr
->rx_jmb
, 0, TG3_RX_JUMBO_RING_BYTES
);
5730 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) {
5731 for (i
= 0; i
< TG3_RX_JUMBO_RING_SIZE
; i
++) {
5732 struct tg3_rx_buffer_desc
*rxd
;
5734 rxd
= &tpr
->rx_jmb
[i
].std
;
5735 rxd
->idx_len
= TG3_RX_JMB_DMA_SZ
<< RXD_LEN_SHIFT
;
5736 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
) |
5738 rxd
->opaque
= (RXD_OPAQUE_RING_JUMBO
|
5739 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
5742 for (i
= 0; i
< tp
->rx_jumbo_pending
; i
++) {
5743 if (tg3_alloc_rx_skb(tnapi
, RXD_OPAQUE_RING_JUMBO
,
5745 printk(KERN_WARNING PFX
5746 "%s: Using a smaller RX jumbo ring, "
5747 "only %d out of %d buffers were "
5748 "allocated successfully.\n",
5749 tp
->dev
->name
, i
, tp
->rx_jumbo_pending
);
5752 tp
->rx_jumbo_pending
= i
;
5762 tg3_rx_prodring_free(tp
, tpr
);
5766 static void tg3_rx_prodring_fini(struct tg3
*tp
,
5767 struct tg3_rx_prodring_set
*tpr
)
5769 kfree(tpr
->rx_std_buffers
);
5770 tpr
->rx_std_buffers
= NULL
;
5771 kfree(tpr
->rx_jmb_buffers
);
5772 tpr
->rx_jmb_buffers
= NULL
;
5774 pci_free_consistent(tp
->pdev
, TG3_RX_RING_BYTES
,
5775 tpr
->rx_std
, tpr
->rx_std_mapping
);
5779 pci_free_consistent(tp
->pdev
, TG3_RX_JUMBO_RING_BYTES
,
5780 tpr
->rx_jmb
, tpr
->rx_jmb_mapping
);
5785 static int tg3_rx_prodring_init(struct tg3
*tp
,
5786 struct tg3_rx_prodring_set
*tpr
)
5788 tpr
->rx_std_buffers
= kzalloc(sizeof(struct ring_info
) *
5789 TG3_RX_RING_SIZE
, GFP_KERNEL
);
5790 if (!tpr
->rx_std_buffers
)
5793 tpr
->rx_std
= pci_alloc_consistent(tp
->pdev
, TG3_RX_RING_BYTES
,
5794 &tpr
->rx_std_mapping
);
5798 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
5799 tpr
->rx_jmb_buffers
= kzalloc(sizeof(struct ring_info
) *
5800 TG3_RX_JUMBO_RING_SIZE
,
5802 if (!tpr
->rx_jmb_buffers
)
5805 tpr
->rx_jmb
= pci_alloc_consistent(tp
->pdev
,
5806 TG3_RX_JUMBO_RING_BYTES
,
5807 &tpr
->rx_jmb_mapping
);
5815 tg3_rx_prodring_fini(tp
, tpr
);
5819 /* Free up pending packets in all rx/tx rings.
5821 * The chip has been shut down and the driver detached from
5822 * the networking, so no interrupts or new tx packets will
5823 * end up in the driver. tp->{tx,}lock is not held and we are not
5824 * in an interrupt context and thus may sleep.
5826 static void tg3_free_rings(struct tg3
*tp
)
5830 for (j
= 0; j
< tp
->irq_cnt
; j
++) {
5831 struct tg3_napi
*tnapi
= &tp
->napi
[j
];
5833 if (!tnapi
->tx_buffers
)
5836 for (i
= 0; i
< TG3_TX_RING_SIZE
; ) {
5837 struct tx_ring_info
*txp
;
5838 struct sk_buff
*skb
;
5840 txp
= &tnapi
->tx_buffers
[i
];
5848 skb_dma_unmap(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
);
5852 i
+= skb_shinfo(skb
)->nr_frags
+ 1;
5854 dev_kfree_skb_any(skb
);
5858 tg3_rx_prodring_free(tp
, &tp
->prodring
[0]);
5861 /* Initialize tx/rx rings for packet processing.
5863 * The chip has been shut down and the driver detached from
5864 * the networking, so no interrupts or new tx packets will
5865 * end up in the driver. tp->{tx,}lock are held and thus
5868 static int tg3_init_rings(struct tg3
*tp
)
5872 /* Free up all the SKBs. */
5875 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
5876 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
5878 tnapi
->last_tag
= 0;
5879 tnapi
->last_irq_tag
= 0;
5880 tnapi
->hw_status
->status
= 0;
5881 tnapi
->hw_status
->status_tag
= 0;
5882 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
5887 memset(tnapi
->tx_ring
, 0, TG3_TX_RING_BYTES
);
5889 tnapi
->rx_rcb_ptr
= 0;
5891 memset(tnapi
->rx_rcb
, 0, TG3_RX_RCB_RING_BYTES(tp
));
5894 return tg3_rx_prodring_alloc(tp
, &tp
->prodring
[0]);
5898 * Must not be invoked with interrupt sources disabled and
5899 * the hardware shutdown down.
5901 static void tg3_free_consistent(struct tg3
*tp
)
5905 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
5906 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
5908 if (tnapi
->tx_ring
) {
5909 pci_free_consistent(tp
->pdev
, TG3_TX_RING_BYTES
,
5910 tnapi
->tx_ring
, tnapi
->tx_desc_mapping
);
5911 tnapi
->tx_ring
= NULL
;
5914 kfree(tnapi
->tx_buffers
);
5915 tnapi
->tx_buffers
= NULL
;
5917 if (tnapi
->rx_rcb
) {
5918 pci_free_consistent(tp
->pdev
, TG3_RX_RCB_RING_BYTES(tp
),
5920 tnapi
->rx_rcb_mapping
);
5921 tnapi
->rx_rcb
= NULL
;
5924 if (tnapi
->hw_status
) {
5925 pci_free_consistent(tp
->pdev
, TG3_HW_STATUS_SIZE
,
5927 tnapi
->status_mapping
);
5928 tnapi
->hw_status
= NULL
;
5933 pci_free_consistent(tp
->pdev
, sizeof(struct tg3_hw_stats
),
5934 tp
->hw_stats
, tp
->stats_mapping
);
5935 tp
->hw_stats
= NULL
;
5938 tg3_rx_prodring_fini(tp
, &tp
->prodring
[0]);
5942 * Must not be invoked with interrupt sources disabled and
5943 * the hardware shutdown down. Can sleep.
5945 static int tg3_alloc_consistent(struct tg3
*tp
)
5949 if (tg3_rx_prodring_init(tp
, &tp
->prodring
[0]))
5952 tp
->hw_stats
= pci_alloc_consistent(tp
->pdev
,
5953 sizeof(struct tg3_hw_stats
),
5954 &tp
->stats_mapping
);
5958 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
5960 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
5961 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
5962 struct tg3_hw_status
*sblk
;
5964 tnapi
->hw_status
= pci_alloc_consistent(tp
->pdev
,
5966 &tnapi
->status_mapping
);
5967 if (!tnapi
->hw_status
)
5970 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
5971 sblk
= tnapi
->hw_status
;
5974 * When RSS is enabled, the status block format changes
5975 * slightly. The "rx_jumbo_consumer", "reserved",
5976 * and "rx_mini_consumer" members get mapped to the
5977 * other three rx return ring producer indexes.
5981 tnapi
->rx_rcb_prod_idx
= &sblk
->idx
[0].rx_producer
;
5984 tnapi
->rx_rcb_prod_idx
= &sblk
->rx_jumbo_consumer
;
5987 tnapi
->rx_rcb_prod_idx
= &sblk
->reserved
;
5990 tnapi
->rx_rcb_prod_idx
= &sblk
->rx_mini_consumer
;
5995 * If multivector RSS is enabled, vector 0 does not handle
5996 * rx or tx interrupts. Don't allocate any resources for it.
5998 if (!i
&& (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
))
6001 tnapi
->rx_rcb
= pci_alloc_consistent(tp
->pdev
,
6002 TG3_RX_RCB_RING_BYTES(tp
),
6003 &tnapi
->rx_rcb_mapping
);
6007 memset(tnapi
->rx_rcb
, 0, TG3_RX_RCB_RING_BYTES(tp
));
6009 tnapi
->tx_buffers
= kzalloc(sizeof(struct tx_ring_info
) *
6010 TG3_TX_RING_SIZE
, GFP_KERNEL
);
6011 if (!tnapi
->tx_buffers
)
6014 tnapi
->tx_ring
= pci_alloc_consistent(tp
->pdev
,
6016 &tnapi
->tx_desc_mapping
);
6017 if (!tnapi
->tx_ring
)
6024 tg3_free_consistent(tp
);
6028 #define MAX_WAIT_CNT 1000
6030 /* To stop a block, clear the enable bit and poll till it
6031 * clears. tp->lock is held.
6033 static int tg3_stop_block(struct tg3
*tp
, unsigned long ofs
, u32 enable_bit
, int silent
)
6038 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
6045 /* We can't enable/disable these bits of the
6046 * 5705/5750, just say success.
6059 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
6062 if ((val
& enable_bit
) == 0)
6066 if (i
== MAX_WAIT_CNT
&& !silent
) {
6067 printk(KERN_ERR PFX
"tg3_stop_block timed out, "
6068 "ofs=%lx enable_bit=%x\n",
6076 /* tp->lock is held. */
6077 static int tg3_abort_hw(struct tg3
*tp
, int silent
)
6081 tg3_disable_ints(tp
);
6083 tp
->rx_mode
&= ~RX_MODE_ENABLE
;
6084 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
6087 err
= tg3_stop_block(tp
, RCVBDI_MODE
, RCVBDI_MODE_ENABLE
, silent
);
6088 err
|= tg3_stop_block(tp
, RCVLPC_MODE
, RCVLPC_MODE_ENABLE
, silent
);
6089 err
|= tg3_stop_block(tp
, RCVLSC_MODE
, RCVLSC_MODE_ENABLE
, silent
);
6090 err
|= tg3_stop_block(tp
, RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
, silent
);
6091 err
|= tg3_stop_block(tp
, RCVDCC_MODE
, RCVDCC_MODE_ENABLE
, silent
);
6092 err
|= tg3_stop_block(tp
, RCVCC_MODE
, RCVCC_MODE_ENABLE
, silent
);
6094 err
|= tg3_stop_block(tp
, SNDBDS_MODE
, SNDBDS_MODE_ENABLE
, silent
);
6095 err
|= tg3_stop_block(tp
, SNDBDI_MODE
, SNDBDI_MODE_ENABLE
, silent
);
6096 err
|= tg3_stop_block(tp
, SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
, silent
);
6097 err
|= tg3_stop_block(tp
, RDMAC_MODE
, RDMAC_MODE_ENABLE
, silent
);
6098 err
|= tg3_stop_block(tp
, SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
, silent
);
6099 err
|= tg3_stop_block(tp
, DMAC_MODE
, DMAC_MODE_ENABLE
, silent
);
6100 err
|= tg3_stop_block(tp
, SNDBDC_MODE
, SNDBDC_MODE_ENABLE
, silent
);
6102 tp
->mac_mode
&= ~MAC_MODE_TDE_ENABLE
;
6103 tw32_f(MAC_MODE
, tp
->mac_mode
);
6106 tp
->tx_mode
&= ~TX_MODE_ENABLE
;
6107 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
6109 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
6111 if (!(tr32(MAC_TX_MODE
) & TX_MODE_ENABLE
))
6114 if (i
>= MAX_WAIT_CNT
) {
6115 printk(KERN_ERR PFX
"tg3_abort_hw timed out for %s, "
6116 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6117 tp
->dev
->name
, tr32(MAC_TX_MODE
));
6121 err
|= tg3_stop_block(tp
, HOSTCC_MODE
, HOSTCC_MODE_ENABLE
, silent
);
6122 err
|= tg3_stop_block(tp
, WDMAC_MODE
, WDMAC_MODE_ENABLE
, silent
);
6123 err
|= tg3_stop_block(tp
, MBFREE_MODE
, MBFREE_MODE_ENABLE
, silent
);
6125 tw32(FTQ_RESET
, 0xffffffff);
6126 tw32(FTQ_RESET
, 0x00000000);
6128 err
|= tg3_stop_block(tp
, BUFMGR_MODE
, BUFMGR_MODE_ENABLE
, silent
);
6129 err
|= tg3_stop_block(tp
, MEMARB_MODE
, MEMARB_MODE_ENABLE
, silent
);
6131 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6132 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6133 if (tnapi
->hw_status
)
6134 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6137 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
6142 static void tg3_ape_send_event(struct tg3
*tp
, u32 event
)
6147 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
6148 if (apedata
!= APE_SEG_SIG_MAGIC
)
6151 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
6152 if (!(apedata
& APE_FW_STATUS_READY
))
6155 /* Wait for up to 1 millisecond for APE to service previous event. */
6156 for (i
= 0; i
< 10; i
++) {
6157 if (tg3_ape_lock(tp
, TG3_APE_LOCK_MEM
))
6160 apedata
= tg3_ape_read32(tp
, TG3_APE_EVENT_STATUS
);
6162 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6163 tg3_ape_write32(tp
, TG3_APE_EVENT_STATUS
,
6164 event
| APE_EVENT_STATUS_EVENT_PENDING
);
6166 tg3_ape_unlock(tp
, TG3_APE_LOCK_MEM
);
6168 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6174 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6175 tg3_ape_write32(tp
, TG3_APE_EVENT
, APE_EVENT_1
);
6178 static void tg3_ape_driver_state_change(struct tg3
*tp
, int kind
)
6183 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
6187 case RESET_KIND_INIT
:
6188 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
,
6189 APE_HOST_SEG_SIG_MAGIC
);
6190 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_LEN
,
6191 APE_HOST_SEG_LEN_MAGIC
);
6192 apedata
= tg3_ape_read32(tp
, TG3_APE_HOST_INIT_COUNT
);
6193 tg3_ape_write32(tp
, TG3_APE_HOST_INIT_COUNT
, ++apedata
);
6194 tg3_ape_write32(tp
, TG3_APE_HOST_DRIVER_ID
,
6195 APE_HOST_DRIVER_ID_MAGIC
);
6196 tg3_ape_write32(tp
, TG3_APE_HOST_BEHAVIOR
,
6197 APE_HOST_BEHAV_NO_PHYLOCK
);
6199 event
= APE_EVENT_STATUS_STATE_START
;
6201 case RESET_KIND_SHUTDOWN
:
6202 /* With the interface we are currently using,
6203 * APE does not track driver state. Wiping
6204 * out the HOST SEGMENT SIGNATURE forces
6205 * the APE to assume OS absent status.
6207 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
, 0x0);
6209 event
= APE_EVENT_STATUS_STATE_UNLOAD
;
6211 case RESET_KIND_SUSPEND
:
6212 event
= APE_EVENT_STATUS_STATE_SUSPEND
;
6218 event
|= APE_EVENT_STATUS_DRIVER_EVNT
| APE_EVENT_STATUS_STATE_CHNGE
;
6220 tg3_ape_send_event(tp
, event
);
6223 /* tp->lock is held. */
6224 static void tg3_write_sig_pre_reset(struct tg3
*tp
, int kind
)
6226 tg3_write_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
,
6227 NIC_SRAM_FIRMWARE_MBOX_MAGIC1
);
6229 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
6231 case RESET_KIND_INIT
:
6232 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6236 case RESET_KIND_SHUTDOWN
:
6237 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6241 case RESET_KIND_SUSPEND
:
6242 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6251 if (kind
== RESET_KIND_INIT
||
6252 kind
== RESET_KIND_SUSPEND
)
6253 tg3_ape_driver_state_change(tp
, kind
);
6256 /* tp->lock is held. */
6257 static void tg3_write_sig_post_reset(struct tg3
*tp
, int kind
)
6259 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
6261 case RESET_KIND_INIT
:
6262 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6263 DRV_STATE_START_DONE
);
6266 case RESET_KIND_SHUTDOWN
:
6267 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6268 DRV_STATE_UNLOAD_DONE
);
6276 if (kind
== RESET_KIND_SHUTDOWN
)
6277 tg3_ape_driver_state_change(tp
, kind
);
6280 /* tp->lock is held. */
6281 static void tg3_write_sig_legacy(struct tg3
*tp
, int kind
)
6283 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
6285 case RESET_KIND_INIT
:
6286 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6290 case RESET_KIND_SHUTDOWN
:
6291 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6295 case RESET_KIND_SUSPEND
:
6296 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6306 static int tg3_poll_fw(struct tg3
*tp
)
6311 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6312 /* Wait up to 20ms for init done. */
6313 for (i
= 0; i
< 200; i
++) {
6314 if (tr32(VCPU_STATUS
) & VCPU_STATUS_INIT_DONE
)
6321 /* Wait for firmware initialization to complete. */
6322 for (i
= 0; i
< 100000; i
++) {
6323 tg3_read_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
, &val
);
6324 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
6329 /* Chip might not be fitted with firmware. Some Sun onboard
6330 * parts are configured like that. So don't signal the timeout
6331 * of the above loop as an error, but do report the lack of
6332 * running firmware once.
6335 !(tp
->tg3_flags2
& TG3_FLG2_NO_FWARE_REPORTED
)) {
6336 tp
->tg3_flags2
|= TG3_FLG2_NO_FWARE_REPORTED
;
6338 printk(KERN_INFO PFX
"%s: No firmware running.\n",
6345 /* Save PCI command register before chip reset */
6346 static void tg3_save_pci_state(struct tg3
*tp
)
6348 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &tp
->pci_cmd
);
6351 /* Restore PCI state after chip reset */
6352 static void tg3_restore_pci_state(struct tg3
*tp
)
6356 /* Re-enable indirect register accesses. */
6357 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
6358 tp
->misc_host_ctrl
);
6360 /* Set MAX PCI retry to zero. */
6361 val
= (PCISTATE_ROM_ENABLE
| PCISTATE_ROM_RETRY_ENABLE
);
6362 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
6363 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
))
6364 val
|= PCISTATE_RETRY_SAME_DMA
;
6365 /* Allow reads and writes to the APE register and memory space. */
6366 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
6367 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
6368 PCISTATE_ALLOW_APE_SHMEM_WR
;
6369 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, val
);
6371 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, tp
->pci_cmd
);
6373 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
) {
6374 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
6375 pcie_set_readrq(tp
->pdev
, 4096);
6377 pci_write_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
6378 tp
->pci_cacheline_sz
);
6379 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
6384 /* Make sure PCI-X relaxed ordering bit is clear. */
6385 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
6388 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
6390 pcix_cmd
&= ~PCI_X_CMD_ERO
;
6391 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
6395 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
6397 /* Chip reset on 5780 will reset MSI enable bit,
6398 * so need to restore it.
6400 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
6403 pci_read_config_word(tp
->pdev
,
6404 tp
->msi_cap
+ PCI_MSI_FLAGS
,
6406 pci_write_config_word(tp
->pdev
,
6407 tp
->msi_cap
+ PCI_MSI_FLAGS
,
6408 ctrl
| PCI_MSI_FLAGS_ENABLE
);
6409 val
= tr32(MSGINT_MODE
);
6410 tw32(MSGINT_MODE
, val
| MSGINT_MODE_ENABLE
);
6415 static void tg3_stop_fw(struct tg3
*);
6417 /* tp->lock is held. */
6418 static int tg3_chip_reset(struct tg3
*tp
)
6421 void (*write_op
)(struct tg3
*, u32
, u32
);
6426 tg3_ape_lock(tp
, TG3_APE_LOCK_GRC
);
6428 /* No matching tg3_nvram_unlock() after this because
6429 * chip reset below will undo the nvram lock.
6431 tp
->nvram_lock_cnt
= 0;
6433 /* GRC_MISC_CFG core clock reset will clear the memory
6434 * enable bit in PCI register 4 and the MSI enable bit
6435 * on some chips, so we save relevant registers here.
6437 tg3_save_pci_state(tp
);
6439 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
6440 (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
))
6441 tw32(GRC_FASTBOOT_PC
, 0);
6444 * We must avoid the readl() that normally takes place.
6445 * It locks machines, causes machine checks, and other
6446 * fun things. So, temporarily disable the 5701
6447 * hardware workaround, while we do the reset.
6449 write_op
= tp
->write32
;
6450 if (write_op
== tg3_write_flush_reg32
)
6451 tp
->write32
= tg3_write32
;
6453 /* Prevent the irq handler from reading or writing PCI registers
6454 * during chip reset when the memory enable bit in the PCI command
6455 * register may be cleared. The chip does not generate interrupt
6456 * at this time, but the irq handler may still be called due to irq
6457 * sharing or irqpoll.
6459 tp
->tg3_flags
|= TG3_FLAG_CHIP_RESETTING
;
6460 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6461 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6462 if (tnapi
->hw_status
) {
6463 tnapi
->hw_status
->status
= 0;
6464 tnapi
->hw_status
->status_tag
= 0;
6466 tnapi
->last_tag
= 0;
6467 tnapi
->last_irq_tag
= 0;
6471 for (i
= 0; i
< tp
->irq_cnt
; i
++)
6472 synchronize_irq(tp
->napi
[i
].irq_vec
);
6474 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
6475 val
= tr32(TG3_PCIE_LNKCTL
) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN
;
6476 tw32(TG3_PCIE_LNKCTL
, val
| TG3_PCIE_LNKCTL_L1_PLL_PD_DIS
);
6480 val
= GRC_MISC_CFG_CORECLK_RESET
;
6482 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
6483 if (tr32(0x7e2c) == 0x60) {
6486 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
) {
6487 tw32(GRC_MISC_CFG
, (1 << 29));
6492 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6493 tw32(VCPU_STATUS
, tr32(VCPU_STATUS
) | VCPU_STATUS_DRV_RESET
);
6494 tw32(GRC_VCPU_EXT_CTRL
,
6495 tr32(GRC_VCPU_EXT_CTRL
) & ~GRC_VCPU_EXT_CTRL_HALT_CPU
);
6498 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
6499 val
|= GRC_MISC_CFG_KEEP_GPHY_POWER
;
6500 tw32(GRC_MISC_CFG
, val
);
6502 /* restore 5701 hardware bug workaround write method */
6503 tp
->write32
= write_op
;
6505 /* Unfortunately, we have to delay before the PCI read back.
6506 * Some 575X chips even will not respond to a PCI cfg access
6507 * when the reset command is given to the chip.
6509 * How do these hardware designers expect things to work
6510 * properly if the PCI write is posted for a long period
6511 * of time? It is always necessary to have some method by
6512 * which a register read back can occur to push the write
6513 * out which does the reset.
6515 * For most tg3 variants the trick below was working.
6520 /* Flush PCI posted writes. The normal MMIO registers
6521 * are inaccessible at this time so this is the only
6522 * way to make this reliably (actually, this is no longer
6523 * the case, see above). I tried to use indirect
6524 * register read/write but this upset some 5701 variants.
6526 pci_read_config_dword(tp
->pdev
, PCI_COMMAND
, &val
);
6530 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) && tp
->pcie_cap
) {
6533 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
) {
6537 /* Wait for link training to complete. */
6538 for (i
= 0; i
< 5000; i
++)
6541 pci_read_config_dword(tp
->pdev
, 0xc4, &cfg_val
);
6542 pci_write_config_dword(tp
->pdev
, 0xc4,
6543 cfg_val
| (1 << 15));
6546 /* Clear the "no snoop" and "relaxed ordering" bits. */
6547 pci_read_config_word(tp
->pdev
,
6548 tp
->pcie_cap
+ PCI_EXP_DEVCTL
,
6550 val16
&= ~(PCI_EXP_DEVCTL_RELAX_EN
|
6551 PCI_EXP_DEVCTL_NOSNOOP_EN
);
6553 * Older PCIe devices only support the 128 byte
6554 * MPS setting. Enforce the restriction.
6556 if (!(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
6557 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
))
6558 val16
&= ~PCI_EXP_DEVCTL_PAYLOAD
;
6559 pci_write_config_word(tp
->pdev
,
6560 tp
->pcie_cap
+ PCI_EXP_DEVCTL
,
6563 pcie_set_readrq(tp
->pdev
, 4096);
6565 /* Clear error status */
6566 pci_write_config_word(tp
->pdev
,
6567 tp
->pcie_cap
+ PCI_EXP_DEVSTA
,
6568 PCI_EXP_DEVSTA_CED
|
6569 PCI_EXP_DEVSTA_NFED
|
6570 PCI_EXP_DEVSTA_FED
|
6571 PCI_EXP_DEVSTA_URD
);
6574 tg3_restore_pci_state(tp
);
6576 tp
->tg3_flags
&= ~TG3_FLAG_CHIP_RESETTING
;
6579 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
6580 val
= tr32(MEMARB_MODE
);
6581 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
6583 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A3
) {
6585 tw32(0x5000, 0x400);
6588 tw32(GRC_MODE
, tp
->grc_mode
);
6590 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
) {
6593 tw32(0xc4, val
| (1 << 15));
6596 if ((tp
->nic_sram_data_cfg
& NIC_SRAM_DATA_CFG_MINI_PCI
) != 0 &&
6597 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
6598 tp
->pci_clock_ctrl
|= CLOCK_CTRL_CLKRUN_OENABLE
;
6599 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
)
6600 tp
->pci_clock_ctrl
|= CLOCK_CTRL_FORCE_CLKRUN
;
6601 tw32(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
6604 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
6605 tp
->mac_mode
= MAC_MODE_PORT_MODE_TBI
;
6606 tw32_f(MAC_MODE
, tp
->mac_mode
);
6607 } else if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
6608 tp
->mac_mode
= MAC_MODE_PORT_MODE_GMII
;
6609 tw32_f(MAC_MODE
, tp
->mac_mode
);
6610 } else if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
6611 tp
->mac_mode
&= (MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
);
6612 if (tp
->mac_mode
& MAC_MODE_APE_TX_EN
)
6613 tp
->mac_mode
|= MAC_MODE_TDE_ENABLE
;
6614 tw32_f(MAC_MODE
, tp
->mac_mode
);
6616 tw32_f(MAC_MODE
, 0);
6619 tg3_ape_unlock(tp
, TG3_APE_LOCK_GRC
);
6621 err
= tg3_poll_fw(tp
);
6627 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
6630 phy_addr
= tp
->phy_addr
;
6631 tp
->phy_addr
= TG3_PHY_PCIE_ADDR
;
6633 tg3_writephy(tp
, TG3_PCIEPHY_BLOCK_ADDR
,
6634 TG3_PCIEPHY_TXB_BLK
<< TG3_PCIEPHY_BLOCK_SHIFT
);
6635 val
= TG3_PCIEPHY_TX0CTRL1_TXOCM
| TG3_PCIEPHY_TX0CTRL1_RDCTL
|
6636 TG3_PCIEPHY_TX0CTRL1_TXCMV
| TG3_PCIEPHY_TX0CTRL1_TKSEL
|
6637 TG3_PCIEPHY_TX0CTRL1_NB_EN
;
6638 tg3_writephy(tp
, TG3_PCIEPHY_TX0CTRL1
, val
);
6641 tg3_writephy(tp
, TG3_PCIEPHY_BLOCK_ADDR
,
6642 TG3_PCIEPHY_XGXS_BLK1
<< TG3_PCIEPHY_BLOCK_SHIFT
);
6643 val
= TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN
|
6644 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN
;
6645 tg3_writephy(tp
, TG3_PCIEPHY_PWRMGMT4
, val
);
6648 tp
->phy_addr
= phy_addr
;
6651 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
6652 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
&&
6653 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
6654 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5717
) {
6657 tw32(0x7c00, val
| (1 << 25));
6660 /* Reprobe ASF enable state. */
6661 tp
->tg3_flags
&= ~TG3_FLAG_ENABLE_ASF
;
6662 tp
->tg3_flags2
&= ~TG3_FLG2_ASF_NEW_HANDSHAKE
;
6663 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
6664 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
6667 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
6668 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
6669 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
6670 tp
->last_event_jiffies
= jiffies
;
6671 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
6672 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
6679 /* tp->lock is held. */
6680 static void tg3_stop_fw(struct tg3
*tp
)
6682 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
6683 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
6684 /* Wait for RX cpu to ACK the previous event. */
6685 tg3_wait_for_event_ack(tp
);
6687 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_PAUSE_FW
);
6689 tg3_generate_fw_event(tp
);
6691 /* Wait for RX cpu to ACK this event. */
6692 tg3_wait_for_event_ack(tp
);
6696 /* tp->lock is held. */
6697 static int tg3_halt(struct tg3
*tp
, int kind
, int silent
)
6703 tg3_write_sig_pre_reset(tp
, kind
);
6705 tg3_abort_hw(tp
, silent
);
6706 err
= tg3_chip_reset(tp
);
6708 __tg3_set_mac_addr(tp
, 0);
6710 tg3_write_sig_legacy(tp
, kind
);
6711 tg3_write_sig_post_reset(tp
, kind
);
6719 #define RX_CPU_SCRATCH_BASE 0x30000
6720 #define RX_CPU_SCRATCH_SIZE 0x04000
6721 #define TX_CPU_SCRATCH_BASE 0x34000
6722 #define TX_CPU_SCRATCH_SIZE 0x04000
6724 /* tp->lock is held. */
6725 static int tg3_halt_cpu(struct tg3
*tp
, u32 offset
)
6729 BUG_ON(offset
== TX_CPU_BASE
&&
6730 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
));
6732 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6733 u32 val
= tr32(GRC_VCPU_EXT_CTRL
);
6735 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_HALT_CPU
);
6738 if (offset
== RX_CPU_BASE
) {
6739 for (i
= 0; i
< 10000; i
++) {
6740 tw32(offset
+ CPU_STATE
, 0xffffffff);
6741 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
6742 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
6746 tw32(offset
+ CPU_STATE
, 0xffffffff);
6747 tw32_f(offset
+ CPU_MODE
, CPU_MODE_HALT
);
6750 for (i
= 0; i
< 10000; i
++) {
6751 tw32(offset
+ CPU_STATE
, 0xffffffff);
6752 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
6753 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
6759 printk(KERN_ERR PFX
"tg3_reset_cpu timed out for %s, "
6762 (offset
== RX_CPU_BASE
? "RX" : "TX"));
6766 /* Clear firmware's nvram arbitration. */
6767 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
6768 tw32(NVRAM_SWARB
, SWARB_REQ_CLR0
);
6773 unsigned int fw_base
;
6774 unsigned int fw_len
;
6775 const __be32
*fw_data
;
6778 /* tp->lock is held. */
6779 static int tg3_load_firmware_cpu(struct tg3
*tp
, u32 cpu_base
, u32 cpu_scratch_base
,
6780 int cpu_scratch_size
, struct fw_info
*info
)
6782 int err
, lock_err
, i
;
6783 void (*write_op
)(struct tg3
*, u32
, u32
);
6785 if (cpu_base
== TX_CPU_BASE
&&
6786 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
6787 printk(KERN_ERR PFX
"tg3_load_firmware_cpu: Trying to load "
6788 "TX cpu firmware on %s which is 5705.\n",
6793 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
6794 write_op
= tg3_write_mem
;
6796 write_op
= tg3_write_indirect_reg32
;
6798 /* It is possible that bootcode is still loading at this point.
6799 * Get the nvram lock first before halting the cpu.
6801 lock_err
= tg3_nvram_lock(tp
);
6802 err
= tg3_halt_cpu(tp
, cpu_base
);
6804 tg3_nvram_unlock(tp
);
6808 for (i
= 0; i
< cpu_scratch_size
; i
+= sizeof(u32
))
6809 write_op(tp
, cpu_scratch_base
+ i
, 0);
6810 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
6811 tw32(cpu_base
+ CPU_MODE
, tr32(cpu_base
+CPU_MODE
)|CPU_MODE_HALT
);
6812 for (i
= 0; i
< (info
->fw_len
/ sizeof(u32
)); i
++)
6813 write_op(tp
, (cpu_scratch_base
+
6814 (info
->fw_base
& 0xffff) +
6816 be32_to_cpu(info
->fw_data
[i
]));
6824 /* tp->lock is held. */
6825 static int tg3_load_5701_a0_firmware_fix(struct tg3
*tp
)
6827 struct fw_info info
;
6828 const __be32
*fw_data
;
6831 fw_data
= (void *)tp
->fw
->data
;
6833 /* Firmware blob starts with version numbers, followed by
6834 start address and length. We are setting complete length.
6835 length = end_address_of_bss - start_address_of_text.
6836 Remainder is the blob to be loaded contiguously
6837 from start address. */
6839 info
.fw_base
= be32_to_cpu(fw_data
[1]);
6840 info
.fw_len
= tp
->fw
->size
- 12;
6841 info
.fw_data
= &fw_data
[3];
6843 err
= tg3_load_firmware_cpu(tp
, RX_CPU_BASE
,
6844 RX_CPU_SCRATCH_BASE
, RX_CPU_SCRATCH_SIZE
,
6849 err
= tg3_load_firmware_cpu(tp
, TX_CPU_BASE
,
6850 TX_CPU_SCRATCH_BASE
, TX_CPU_SCRATCH_SIZE
,
6855 /* Now startup only the RX cpu. */
6856 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
6857 tw32_f(RX_CPU_BASE
+ CPU_PC
, info
.fw_base
);
6859 for (i
= 0; i
< 5; i
++) {
6860 if (tr32(RX_CPU_BASE
+ CPU_PC
) == info
.fw_base
)
6862 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
6863 tw32(RX_CPU_BASE
+ CPU_MODE
, CPU_MODE_HALT
);
6864 tw32_f(RX_CPU_BASE
+ CPU_PC
, info
.fw_base
);
6868 printk(KERN_ERR PFX
"tg3_load_firmware fails for %s "
6869 "to set RX CPU PC, is %08x should be %08x\n",
6870 tp
->dev
->name
, tr32(RX_CPU_BASE
+ CPU_PC
),
6874 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
6875 tw32_f(RX_CPU_BASE
+ CPU_MODE
, 0x00000000);
6880 /* 5705 needs a special version of the TSO firmware. */
6882 /* tp->lock is held. */
6883 static int tg3_load_tso_firmware(struct tg3
*tp
)
6885 struct fw_info info
;
6886 const __be32
*fw_data
;
6887 unsigned long cpu_base
, cpu_scratch_base
, cpu_scratch_size
;
6890 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
6893 fw_data
= (void *)tp
->fw
->data
;
6895 /* Firmware blob starts with version numbers, followed by
6896 start address and length. We are setting complete length.
6897 length = end_address_of_bss - start_address_of_text.
6898 Remainder is the blob to be loaded contiguously
6899 from start address. */
6901 info
.fw_base
= be32_to_cpu(fw_data
[1]);
6902 cpu_scratch_size
= tp
->fw_len
;
6903 info
.fw_len
= tp
->fw
->size
- 12;
6904 info
.fw_data
= &fw_data
[3];
6906 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
6907 cpu_base
= RX_CPU_BASE
;
6908 cpu_scratch_base
= NIC_SRAM_MBUF_POOL_BASE5705
;
6910 cpu_base
= TX_CPU_BASE
;
6911 cpu_scratch_base
= TX_CPU_SCRATCH_BASE
;
6912 cpu_scratch_size
= TX_CPU_SCRATCH_SIZE
;
6915 err
= tg3_load_firmware_cpu(tp
, cpu_base
,
6916 cpu_scratch_base
, cpu_scratch_size
,
6921 /* Now startup the cpu. */
6922 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
6923 tw32_f(cpu_base
+ CPU_PC
, info
.fw_base
);
6925 for (i
= 0; i
< 5; i
++) {
6926 if (tr32(cpu_base
+ CPU_PC
) == info
.fw_base
)
6928 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
6929 tw32(cpu_base
+ CPU_MODE
, CPU_MODE_HALT
);
6930 tw32_f(cpu_base
+ CPU_PC
, info
.fw_base
);
6934 printk(KERN_ERR PFX
"tg3_load_tso_firmware fails for %s "
6935 "to set CPU PC, is %08x should be %08x\n",
6936 tp
->dev
->name
, tr32(cpu_base
+ CPU_PC
),
6940 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
6941 tw32_f(cpu_base
+ CPU_MODE
, 0x00000000);
6946 static int tg3_set_mac_addr(struct net_device
*dev
, void *p
)
6948 struct tg3
*tp
= netdev_priv(dev
);
6949 struct sockaddr
*addr
= p
;
6950 int err
= 0, skip_mac_1
= 0;
6952 if (!is_valid_ether_addr(addr
->sa_data
))
6955 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
6957 if (!netif_running(dev
))
6960 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
6961 u32 addr0_high
, addr0_low
, addr1_high
, addr1_low
;
6963 addr0_high
= tr32(MAC_ADDR_0_HIGH
);
6964 addr0_low
= tr32(MAC_ADDR_0_LOW
);
6965 addr1_high
= tr32(MAC_ADDR_1_HIGH
);
6966 addr1_low
= tr32(MAC_ADDR_1_LOW
);
6968 /* Skip MAC addr 1 if ASF is using it. */
6969 if ((addr0_high
!= addr1_high
|| addr0_low
!= addr1_low
) &&
6970 !(addr1_high
== 0 && addr1_low
== 0))
6973 spin_lock_bh(&tp
->lock
);
6974 __tg3_set_mac_addr(tp
, skip_mac_1
);
6975 spin_unlock_bh(&tp
->lock
);
6980 /* tp->lock is held. */
6981 static void tg3_set_bdinfo(struct tg3
*tp
, u32 bdinfo_addr
,
6982 dma_addr_t mapping
, u32 maxlen_flags
,
6986 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
6987 ((u64
) mapping
>> 32));
6989 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
),
6990 ((u64
) mapping
& 0xffffffff));
6992 (bdinfo_addr
+ TG3_BDINFO_MAXLEN_FLAGS
),
6995 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
6997 (bdinfo_addr
+ TG3_BDINFO_NIC_ADDR
),
7001 static void __tg3_set_rx_mode(struct net_device
*);
7002 static void __tg3_set_coalesce(struct tg3
*tp
, struct ethtool_coalesce
*ec
)
7006 if (!(tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)) {
7007 tw32(HOSTCC_TXCOL_TICKS
, ec
->tx_coalesce_usecs
);
7008 tw32(HOSTCC_TXMAX_FRAMES
, ec
->tx_max_coalesced_frames
);
7009 tw32(HOSTCC_TXCOAL_MAXF_INT
, ec
->tx_max_coalesced_frames_irq
);
7011 tw32(HOSTCC_RXCOL_TICKS
, ec
->rx_coalesce_usecs
);
7012 tw32(HOSTCC_RXMAX_FRAMES
, ec
->rx_max_coalesced_frames
);
7013 tw32(HOSTCC_RXCOAL_MAXF_INT
, ec
->rx_max_coalesced_frames_irq
);
7015 tw32(HOSTCC_TXCOL_TICKS
, 0);
7016 tw32(HOSTCC_TXMAX_FRAMES
, 0);
7017 tw32(HOSTCC_TXCOAL_MAXF_INT
, 0);
7019 tw32(HOSTCC_RXCOL_TICKS
, 0);
7020 tw32(HOSTCC_RXMAX_FRAMES
, 0);
7021 tw32(HOSTCC_RXCOAL_MAXF_INT
, 0);
7024 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7025 u32 val
= ec
->stats_block_coalesce_usecs
;
7027 tw32(HOSTCC_RXCOAL_TICK_INT
, ec
->rx_coalesce_usecs_irq
);
7028 tw32(HOSTCC_TXCOAL_TICK_INT
, ec
->tx_coalesce_usecs_irq
);
7030 if (!netif_carrier_ok(tp
->dev
))
7033 tw32(HOSTCC_STAT_COAL_TICKS
, val
);
7036 for (i
= 0; i
< tp
->irq_cnt
- 1; i
++) {
7039 reg
= HOSTCC_RXCOL_TICKS_VEC1
+ i
* 0x18;
7040 tw32(reg
, ec
->rx_coalesce_usecs
);
7041 reg
= HOSTCC_TXCOL_TICKS_VEC1
+ i
* 0x18;
7042 tw32(reg
, ec
->tx_coalesce_usecs
);
7043 reg
= HOSTCC_RXMAX_FRAMES_VEC1
+ i
* 0x18;
7044 tw32(reg
, ec
->rx_max_coalesced_frames
);
7045 reg
= HOSTCC_TXMAX_FRAMES_VEC1
+ i
* 0x18;
7046 tw32(reg
, ec
->tx_max_coalesced_frames
);
7047 reg
= HOSTCC_RXCOAL_MAXF_INT_VEC1
+ i
* 0x18;
7048 tw32(reg
, ec
->rx_max_coalesced_frames_irq
);
7049 reg
= HOSTCC_TXCOAL_MAXF_INT_VEC1
+ i
* 0x18;
7050 tw32(reg
, ec
->tx_max_coalesced_frames_irq
);
7053 for (; i
< tp
->irq_max
- 1; i
++) {
7054 tw32(HOSTCC_RXCOL_TICKS_VEC1
+ i
* 0x18, 0);
7055 tw32(HOSTCC_TXCOL_TICKS_VEC1
+ i
* 0x18, 0);
7056 tw32(HOSTCC_RXMAX_FRAMES_VEC1
+ i
* 0x18, 0);
7057 tw32(HOSTCC_TXMAX_FRAMES_VEC1
+ i
* 0x18, 0);
7058 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1
+ i
* 0x18, 0);
7059 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1
+ i
* 0x18, 0);
7063 /* tp->lock is held. */
7064 static void tg3_rings_reset(struct tg3
*tp
)
7067 u32 stblk
, txrcb
, rxrcb
, limit
;
7068 struct tg3_napi
*tnapi
= &tp
->napi
[0];
7070 /* Disable all transmit rings but the first. */
7071 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7072 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
* 16;
7074 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
;
7076 for (txrcb
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
;
7077 txrcb
< limit
; txrcb
+= TG3_BDINFO_SIZE
)
7078 tg3_write_mem(tp
, txrcb
+ TG3_BDINFO_MAXLEN_FLAGS
,
7079 BDINFO_FLAGS_DISABLED
);
7082 /* Disable all receive return rings but the first. */
7083 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
)
7084 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 17;
7085 else if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7086 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 16;
7087 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
7088 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 4;
7090 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
;
7092 for (rxrcb
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
;
7093 rxrcb
< limit
; rxrcb
+= TG3_BDINFO_SIZE
)
7094 tg3_write_mem(tp
, rxrcb
+ TG3_BDINFO_MAXLEN_FLAGS
,
7095 BDINFO_FLAGS_DISABLED
);
7097 /* Disable interrupts */
7098 tw32_mailbox_f(tp
->napi
[0].int_mbox
, 1);
7100 /* Zero mailbox registers. */
7101 if (tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
) {
7102 for (i
= 1; i
< TG3_IRQ_MAX_VECS
; i
++) {
7103 tp
->napi
[i
].tx_prod
= 0;
7104 tp
->napi
[i
].tx_cons
= 0;
7105 tw32_mailbox(tp
->napi
[i
].prodmbox
, 0);
7106 tw32_rx_mbox(tp
->napi
[i
].consmbox
, 0);
7107 tw32_mailbox_f(tp
->napi
[i
].int_mbox
, 1);
7110 tp
->napi
[0].tx_prod
= 0;
7111 tp
->napi
[0].tx_cons
= 0;
7112 tw32_mailbox(tp
->napi
[0].prodmbox
, 0);
7113 tw32_rx_mbox(tp
->napi
[0].consmbox
, 0);
7116 /* Make sure the NIC-based send BD rings are disabled. */
7117 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7118 u32 mbox
= MAILBOX_SNDNIC_PROD_IDX_0
+ TG3_64BIT_REG_LOW
;
7119 for (i
= 0; i
< 16; i
++)
7120 tw32_tx_mbox(mbox
+ i
* 8, 0);
7123 txrcb
= NIC_SRAM_SEND_RCB
;
7124 rxrcb
= NIC_SRAM_RCV_RET_RCB
;
7126 /* Clear status block in ram. */
7127 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
7129 /* Set status block DMA address */
7130 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7131 ((u64
) tnapi
->status_mapping
>> 32));
7132 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7133 ((u64
) tnapi
->status_mapping
& 0xffffffff));
7135 if (tnapi
->tx_ring
) {
7136 tg3_set_bdinfo(tp
, txrcb
, tnapi
->tx_desc_mapping
,
7137 (TG3_TX_RING_SIZE
<<
7138 BDINFO_FLAGS_MAXLEN_SHIFT
),
7139 NIC_SRAM_TX_BUFFER_DESC
);
7140 txrcb
+= TG3_BDINFO_SIZE
;
7143 if (tnapi
->rx_rcb
) {
7144 tg3_set_bdinfo(tp
, rxrcb
, tnapi
->rx_rcb_mapping
,
7145 (TG3_RX_RCB_RING_SIZE(tp
) <<
7146 BDINFO_FLAGS_MAXLEN_SHIFT
), 0);
7147 rxrcb
+= TG3_BDINFO_SIZE
;
7150 stblk
= HOSTCC_STATBLCK_RING1
;
7152 for (i
= 1, tnapi
++; i
< tp
->irq_cnt
; i
++, tnapi
++) {
7153 u64 mapping
= (u64
)tnapi
->status_mapping
;
7154 tw32(stblk
+ TG3_64BIT_REG_HIGH
, mapping
>> 32);
7155 tw32(stblk
+ TG3_64BIT_REG_LOW
, mapping
& 0xffffffff);
7157 /* Clear status block in ram. */
7158 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
7160 tg3_set_bdinfo(tp
, txrcb
, tnapi
->tx_desc_mapping
,
7161 (TG3_TX_RING_SIZE
<<
7162 BDINFO_FLAGS_MAXLEN_SHIFT
),
7163 NIC_SRAM_TX_BUFFER_DESC
);
7165 tg3_set_bdinfo(tp
, rxrcb
, tnapi
->rx_rcb_mapping
,
7166 (TG3_RX_RCB_RING_SIZE(tp
) <<
7167 BDINFO_FLAGS_MAXLEN_SHIFT
), 0);
7170 txrcb
+= TG3_BDINFO_SIZE
;
7171 rxrcb
+= TG3_BDINFO_SIZE
;
7175 /* tp->lock is held. */
7176 static int tg3_reset_hw(struct tg3
*tp
, int reset_phy
)
7178 u32 val
, rdmac_mode
;
7180 struct tg3_rx_prodring_set
*tpr
= &tp
->prodring
[0];
7182 tg3_disable_ints(tp
);
7186 tg3_write_sig_pre_reset(tp
, RESET_KIND_INIT
);
7188 if (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) {
7189 tg3_abort_hw(tp
, 1);
7193 !(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
))
7196 err
= tg3_chip_reset(tp
);
7200 tg3_write_sig_legacy(tp
, RESET_KIND_INIT
);
7202 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
) {
7203 val
= tr32(TG3_CPMU_CTRL
);
7204 val
&= ~(CPMU_CTRL_LINK_AWARE_MODE
| CPMU_CTRL_LINK_IDLE_MODE
);
7205 tw32(TG3_CPMU_CTRL
, val
);
7207 val
= tr32(TG3_CPMU_LSPD_10MB_CLK
);
7208 val
&= ~CPMU_LSPD_10MB_MACCLK_MASK
;
7209 val
|= CPMU_LSPD_10MB_MACCLK_6_25
;
7210 tw32(TG3_CPMU_LSPD_10MB_CLK
, val
);
7212 val
= tr32(TG3_CPMU_LNK_AWARE_PWRMD
);
7213 val
&= ~CPMU_LNK_AWARE_MACCLK_MASK
;
7214 val
|= CPMU_LNK_AWARE_MACCLK_6_25
;
7215 tw32(TG3_CPMU_LNK_AWARE_PWRMD
, val
);
7217 val
= tr32(TG3_CPMU_HST_ACC
);
7218 val
&= ~CPMU_HST_ACC_MACCLK_MASK
;
7219 val
|= CPMU_HST_ACC_MACCLK_6_25
;
7220 tw32(TG3_CPMU_HST_ACC
, val
);
7223 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
7224 val
= tr32(PCIE_PWR_MGMT_THRESH
) & ~PCIE_PWR_MGMT_L1_THRESH_MSK
;
7225 val
|= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN
|
7226 PCIE_PWR_MGMT_L1_THRESH_4MS
;
7227 tw32(PCIE_PWR_MGMT_THRESH
, val
);
7229 val
= tr32(TG3_PCIE_EIDLE_DELAY
) & ~TG3_PCIE_EIDLE_DELAY_MASK
;
7230 tw32(TG3_PCIE_EIDLE_DELAY
, val
| TG3_PCIE_EIDLE_DELAY_13_CLKS
);
7232 tw32(TG3_CORR_ERR_STAT
, TG3_CORR_ERR_STAT_CLEAR
);
7234 val
= tr32(TG3_PCIE_LNKCTL
) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN
;
7235 tw32(TG3_PCIE_LNKCTL
, val
| TG3_PCIE_LNKCTL_L1_PLL_PD_DIS
);
7238 /* This works around an issue with Athlon chipsets on
7239 * B3 tigon3 silicon. This bit has no effect on any
7240 * other revision. But do not set this on PCI Express
7241 * chips and don't even touch the clocks if the CPMU is present.
7243 if (!(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
)) {
7244 if (!(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
7245 tp
->pci_clock_ctrl
|= CLOCK_CTRL_DELAY_PCI_GRANT
;
7246 tw32_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
7249 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
7250 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
7251 val
= tr32(TG3PCI_PCISTATE
);
7252 val
|= PCISTATE_RETRY_SAME_DMA
;
7253 tw32(TG3PCI_PCISTATE
, val
);
7256 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
7257 /* Allow reads and writes to the
7258 * APE register and memory space.
7260 val
= tr32(TG3PCI_PCISTATE
);
7261 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
7262 PCISTATE_ALLOW_APE_SHMEM_WR
;
7263 tw32(TG3PCI_PCISTATE
, val
);
7266 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_BX
) {
7267 /* Enable some hw fixes. */
7268 val
= tr32(TG3PCI_MSI_DATA
);
7269 val
|= (1 << 26) | (1 << 28) | (1 << 29);
7270 tw32(TG3PCI_MSI_DATA
, val
);
7273 /* Descriptor ring init may make accesses to the
7274 * NIC SRAM area to setup the TX descriptors, so we
7275 * can only do this after the hardware has been
7276 * successfully reset.
7278 err
= tg3_init_rings(tp
);
7282 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5784
&&
7283 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5761
&&
7284 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5717
) {
7285 /* This value is determined during the probe time DMA
7286 * engine test, tg3_test_dma.
7288 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
7291 tp
->grc_mode
&= ~(GRC_MODE_HOST_SENDBDS
|
7292 GRC_MODE_4X_NIC_SEND_RINGS
|
7293 GRC_MODE_NO_TX_PHDR_CSUM
|
7294 GRC_MODE_NO_RX_PHDR_CSUM
);
7295 tp
->grc_mode
|= GRC_MODE_HOST_SENDBDS
;
7297 /* Pseudo-header checksum is done by hardware logic and not
7298 * the offload processers, so make the chip do the pseudo-
7299 * header checksums on receive. For transmit it is more
7300 * convenient to do the pseudo-header checksum in software
7301 * as Linux does that on transmit for us in all cases.
7303 tp
->grc_mode
|= GRC_MODE_NO_TX_PHDR_CSUM
;
7307 (GRC_MODE_IRQ_ON_MAC_ATTN
| GRC_MODE_HOST_STACKUP
));
7309 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7310 val
= tr32(GRC_MISC_CFG
);
7312 val
|= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT
);
7313 tw32(GRC_MISC_CFG
, val
);
7315 /* Initialize MBUF/DESC pool. */
7316 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
7318 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5705
) {
7319 tw32(BUFMGR_MB_POOL_ADDR
, NIC_SRAM_MBUF_POOL_BASE
);
7320 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
7321 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE64
);
7323 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE96
);
7324 tw32(BUFMGR_DMA_DESC_POOL_ADDR
, NIC_SRAM_DMA_DESC_POOL_BASE
);
7325 tw32(BUFMGR_DMA_DESC_POOL_SIZE
, NIC_SRAM_DMA_DESC_POOL_SIZE
);
7327 else if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
7330 fw_len
= tp
->fw_len
;
7331 fw_len
= (fw_len
+ (0x80 - 1)) & ~(0x80 - 1);
7332 tw32(BUFMGR_MB_POOL_ADDR
,
7333 NIC_SRAM_MBUF_POOL_BASE5705
+ fw_len
);
7334 tw32(BUFMGR_MB_POOL_SIZE
,
7335 NIC_SRAM_MBUF_POOL_SIZE5705
- fw_len
- 0xa00);
7338 if (tp
->dev
->mtu
<= ETH_DATA_LEN
) {
7339 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
7340 tp
->bufmgr_config
.mbuf_read_dma_low_water
);
7341 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
7342 tp
->bufmgr_config
.mbuf_mac_rx_low_water
);
7343 tw32(BUFMGR_MB_HIGH_WATER
,
7344 tp
->bufmgr_config
.mbuf_high_water
);
7346 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
7347 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
);
7348 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
7349 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
);
7350 tw32(BUFMGR_MB_HIGH_WATER
,
7351 tp
->bufmgr_config
.mbuf_high_water_jumbo
);
7353 tw32(BUFMGR_DMA_LOW_WATER
,
7354 tp
->bufmgr_config
.dma_low_water
);
7355 tw32(BUFMGR_DMA_HIGH_WATER
,
7356 tp
->bufmgr_config
.dma_high_water
);
7358 tw32(BUFMGR_MODE
, BUFMGR_MODE_ENABLE
| BUFMGR_MODE_ATTN_ENABLE
);
7359 for (i
= 0; i
< 2000; i
++) {
7360 if (tr32(BUFMGR_MODE
) & BUFMGR_MODE_ENABLE
)
7365 printk(KERN_ERR PFX
"tg3_reset_hw cannot enable BUFMGR for %s.\n",
7370 /* Setup replenish threshold. */
7371 val
= tp
->rx_pending
/ 8;
7374 else if (val
> tp
->rx_std_max_post
)
7375 val
= tp
->rx_std_max_post
;
7376 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
7377 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5906_A1
)
7378 tw32(ISO_PKT_TX
, (tr32(ISO_PKT_TX
) & ~0x3) | 0x2);
7380 if (val
> (TG3_RX_INTERNAL_RING_SZ_5906
/ 2))
7381 val
= TG3_RX_INTERNAL_RING_SZ_5906
/ 2;
7384 tw32(RCVBDI_STD_THRESH
, val
);
7386 /* Initialize TG3_BDINFO's at:
7387 * RCVDBDI_STD_BD: standard eth size rx ring
7388 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7389 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7392 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7393 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7394 * ring attribute flags
7395 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7397 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7398 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7400 * The size of each ring is fixed in the firmware, but the location is
7403 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7404 ((u64
) tpr
->rx_std_mapping
>> 32));
7405 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7406 ((u64
) tpr
->rx_std_mapping
& 0xffffffff));
7407 if (!(tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
))
7408 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_NIC_ADDR
,
7409 NIC_SRAM_RX_BUFFER_DESC
);
7411 /* Disable the mini ring */
7412 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7413 tw32(RCVDBDI_MINI_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
7414 BDINFO_FLAGS_DISABLED
);
7416 /* Program the jumbo buffer descriptor ring control
7417 * blocks on those devices that have them.
7419 if ((tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) &&
7420 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
7421 /* Setup replenish threshold. */
7422 tw32(RCVBDI_JUMBO_THRESH
, tp
->rx_jumbo_pending
/ 8);
7424 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) {
7425 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7426 ((u64
) tpr
->rx_jmb_mapping
>> 32));
7427 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7428 ((u64
) tpr
->rx_jmb_mapping
& 0xffffffff));
7429 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
7430 (RX_JUMBO_MAX_SIZE
<< BDINFO_FLAGS_MAXLEN_SHIFT
) |
7431 BDINFO_FLAGS_USE_EXT_RECV
);
7432 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7433 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_NIC_ADDR
,
7434 NIC_SRAM_RX_JUMBO_BUFFER_DESC
);
7436 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
7437 BDINFO_FLAGS_DISABLED
);
7440 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
)
7441 val
= (RX_STD_MAX_SIZE_5705
<< BDINFO_FLAGS_MAXLEN_SHIFT
) |
7442 (RX_STD_MAX_SIZE
<< 2);
7444 val
= RX_STD_MAX_SIZE
<< BDINFO_FLAGS_MAXLEN_SHIFT
;
7446 val
= RX_STD_MAX_SIZE_5705
<< BDINFO_FLAGS_MAXLEN_SHIFT
;
7448 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_MAXLEN_FLAGS
, val
);
7450 tpr
->rx_std_ptr
= tp
->rx_pending
;
7451 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX
+ TG3_64BIT_REG_LOW
,
7454 tpr
->rx_jmb_ptr
= (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) ?
7455 tp
->rx_jumbo_pending
: 0;
7456 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX
+ TG3_64BIT_REG_LOW
,
7459 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
) {
7460 tw32(STD_REPLENISH_LWM
, 32);
7461 tw32(JMB_REPLENISH_LWM
, 16);
7464 tg3_rings_reset(tp
);
7466 /* Initialize MAC address and backoff seed. */
7467 __tg3_set_mac_addr(tp
, 0);
7469 /* MTU + ethernet header + FCS + optional VLAN tag */
7470 tw32(MAC_RX_MTU_SIZE
,
7471 tp
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ VLAN_HLEN
);
7473 /* The slot time is changed by tg3_setup_phy if we
7474 * run at gigabit with half duplex.
7476 tw32(MAC_TX_LENGTHS
,
7477 (2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
7478 (6 << TX_LENGTHS_IPG_SHIFT
) |
7479 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
));
7481 /* Receive rules. */
7482 tw32(MAC_RCV_RULE_CFG
, RCV_RULE_CFG_DEFAULT_CLASS
);
7483 tw32(RCVLPC_CONFIG
, 0x0181);
7485 /* Calculate RDMAC_MODE setting early, we need it to determine
7486 * the RCVLPC_STATE_ENABLE mask.
7488 rdmac_mode
= (RDMAC_MODE_ENABLE
| RDMAC_MODE_TGTABORT_ENAB
|
7489 RDMAC_MODE_MSTABORT_ENAB
| RDMAC_MODE_PARITYERR_ENAB
|
7490 RDMAC_MODE_ADDROFLOW_ENAB
| RDMAC_MODE_FIFOOFLOW_ENAB
|
7491 RDMAC_MODE_FIFOURUN_ENAB
| RDMAC_MODE_FIFOOREAD_ENAB
|
7492 RDMAC_MODE_LNGREAD_ENAB
);
7494 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
7495 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
7496 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
7497 rdmac_mode
|= RDMAC_MODE_BD_SBD_CRPT_ENAB
|
7498 RDMAC_MODE_MBUF_RBD_CRPT_ENAB
|
7499 RDMAC_MODE_MBUF_SBD_CRPT_ENAB
;
7501 /* If statement applies to 5705 and 5750 PCI devices only */
7502 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
7503 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) ||
7504 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)) {
7505 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
&&
7506 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
7507 rdmac_mode
|= RDMAC_MODE_FIFO_SIZE_128
;
7508 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
7509 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
)) {
7510 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
7514 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
7515 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
7517 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
7518 rdmac_mode
|= RDMAC_MODE_IPV4_LSO_EN
;
7520 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
7521 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
7522 rdmac_mode
|= RDMAC_MODE_IPV6_LSO_EN
;
7524 /* Receive/send statistics. */
7525 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
7526 val
= tr32(RCVLPC_STATS_ENABLE
);
7527 val
&= ~RCVLPC_STATSENAB_DACK_FIX
;
7528 tw32(RCVLPC_STATS_ENABLE
, val
);
7529 } else if ((rdmac_mode
& RDMAC_MODE_FIFO_SIZE_128
) &&
7530 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
7531 val
= tr32(RCVLPC_STATS_ENABLE
);
7532 val
&= ~RCVLPC_STATSENAB_LNGBRST_RFIX
;
7533 tw32(RCVLPC_STATS_ENABLE
, val
);
7535 tw32(RCVLPC_STATS_ENABLE
, 0xffffff);
7537 tw32(RCVLPC_STATSCTRL
, RCVLPC_STATSCTRL_ENABLE
);
7538 tw32(SNDDATAI_STATSENAB
, 0xffffff);
7539 tw32(SNDDATAI_STATSCTRL
,
7540 (SNDDATAI_SCTRL_ENABLE
|
7541 SNDDATAI_SCTRL_FASTUPD
));
7543 /* Setup host coalescing engine. */
7544 tw32(HOSTCC_MODE
, 0);
7545 for (i
= 0; i
< 2000; i
++) {
7546 if (!(tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
))
7551 __tg3_set_coalesce(tp
, &tp
->coal
);
7553 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7554 /* Status/statistics block address. See tg3_timer,
7555 * the tg3_periodic_fetch_stats call there, and
7556 * tg3_get_stats to see how this works for 5705/5750 chips.
7558 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7559 ((u64
) tp
->stats_mapping
>> 32));
7560 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7561 ((u64
) tp
->stats_mapping
& 0xffffffff));
7562 tw32(HOSTCC_STATS_BLK_NIC_ADDR
, NIC_SRAM_STATS_BLK
);
7564 tw32(HOSTCC_STATUS_BLK_NIC_ADDR
, NIC_SRAM_STATUS_BLK
);
7566 /* Clear statistics and status block memory areas */
7567 for (i
= NIC_SRAM_STATS_BLK
;
7568 i
< NIC_SRAM_STATUS_BLK
+ TG3_HW_STATUS_SIZE
;
7570 tg3_write_mem(tp
, i
, 0);
7575 tw32(HOSTCC_MODE
, HOSTCC_MODE_ENABLE
| tp
->coalesce_mode
);
7577 tw32(RCVCC_MODE
, RCVCC_MODE_ENABLE
| RCVCC_MODE_ATTN_ENABLE
);
7578 tw32(RCVLPC_MODE
, RCVLPC_MODE_ENABLE
);
7579 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7580 tw32(RCVLSC_MODE
, RCVLSC_MODE_ENABLE
| RCVLSC_MODE_ATTN_ENABLE
);
7582 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
7583 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
7584 /* reset to prevent losing 1st rx packet intermittently */
7585 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
7589 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
7590 tp
->mac_mode
&= MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
7593 tp
->mac_mode
|= MAC_MODE_TXSTAT_ENABLE
| MAC_MODE_RXSTAT_ENABLE
|
7594 MAC_MODE_TDE_ENABLE
| MAC_MODE_RDE_ENABLE
| MAC_MODE_FHDE_ENABLE
;
7595 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
7596 !(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
7597 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
)
7598 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
7599 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_RXSTAT_CLEAR
| MAC_MODE_TXSTAT_CLEAR
);
7602 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7603 * If TG3_FLG2_IS_NIC is zero, we should read the
7604 * register to preserve the GPIO settings for LOMs. The GPIOs,
7605 * whether used as inputs or outputs, are set by boot code after
7608 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)) {
7611 gpio_mask
= GRC_LCLCTRL_GPIO_OE0
| GRC_LCLCTRL_GPIO_OE1
|
7612 GRC_LCLCTRL_GPIO_OE2
| GRC_LCLCTRL_GPIO_OUTPUT0
|
7613 GRC_LCLCTRL_GPIO_OUTPUT1
| GRC_LCLCTRL_GPIO_OUTPUT2
;
7615 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
7616 gpio_mask
|= GRC_LCLCTRL_GPIO_OE3
|
7617 GRC_LCLCTRL_GPIO_OUTPUT3
;
7619 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
7620 gpio_mask
|= GRC_LCLCTRL_GPIO_UART_SEL
;
7622 tp
->grc_local_ctrl
&= ~gpio_mask
;
7623 tp
->grc_local_ctrl
|= tr32(GRC_LOCAL_CTRL
) & gpio_mask
;
7625 /* GPIO1 must be driven high for eeprom write protect */
7626 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
)
7627 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
7628 GRC_LCLCTRL_GPIO_OUTPUT1
);
7630 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
7633 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
) {
7634 val
= tr32(MSGINT_MODE
);
7635 val
|= MSGINT_MODE_MULTIVEC_EN
| MSGINT_MODE_ENABLE
;
7636 tw32(MSGINT_MODE
, val
);
7639 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7640 tw32_f(DMAC_MODE
, DMAC_MODE_ENABLE
);
7644 val
= (WDMAC_MODE_ENABLE
| WDMAC_MODE_TGTABORT_ENAB
|
7645 WDMAC_MODE_MSTABORT_ENAB
| WDMAC_MODE_PARITYERR_ENAB
|
7646 WDMAC_MODE_ADDROFLOW_ENAB
| WDMAC_MODE_FIFOOFLOW_ENAB
|
7647 WDMAC_MODE_FIFOURUN_ENAB
| WDMAC_MODE_FIFOOREAD_ENAB
|
7648 WDMAC_MODE_LNGREAD_ENAB
);
7650 /* If statement applies to 5705 and 5750 PCI devices only */
7651 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
7652 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) ||
7653 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) {
7654 if ((tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) &&
7655 (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
||
7656 tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A2
)) {
7658 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
7659 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
7660 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
7661 val
|= WDMAC_MODE_RX_ACCEL
;
7665 /* Enable host coalescing bug fix */
7666 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
7667 val
|= WDMAC_MODE_STATUS_TAG_FIX
;
7669 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
7670 val
|= WDMAC_MODE_BURST_ALL_DATA
;
7672 tw32_f(WDMAC_MODE
, val
);
7675 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
7678 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
7680 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
) {
7681 pcix_cmd
&= ~PCI_X_CMD_MAX_READ
;
7682 pcix_cmd
|= PCI_X_CMD_READ_2K
;
7683 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
7684 pcix_cmd
&= ~(PCI_X_CMD_MAX_SPLIT
| PCI_X_CMD_MAX_READ
);
7685 pcix_cmd
|= PCI_X_CMD_READ_2K
;
7687 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
7691 tw32_f(RDMAC_MODE
, rdmac_mode
);
7694 tw32(RCVDCC_MODE
, RCVDCC_MODE_ENABLE
| RCVDCC_MODE_ATTN_ENABLE
);
7695 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7696 tw32(MBFREE_MODE
, MBFREE_MODE_ENABLE
);
7698 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
7700 SNDDATAC_MODE_ENABLE
| SNDDATAC_MODE_CDELAY
);
7702 tw32(SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
);
7704 tw32(SNDBDC_MODE
, SNDBDC_MODE_ENABLE
| SNDBDC_MODE_ATTN_ENABLE
);
7705 tw32(RCVBDI_MODE
, RCVBDI_MODE_ENABLE
| RCVBDI_MODE_RCB_ATTN_ENAB
);
7706 tw32(RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
| RCVDBDI_MODE_INV_RING_SZ
);
7707 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
);
7708 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
7709 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
| 0x8);
7710 val
= SNDBDI_MODE_ENABLE
| SNDBDI_MODE_ATTN_ENABLE
;
7711 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)
7712 val
|= SNDBDI_MODE_MULTI_TXQ_EN
;
7713 tw32(SNDBDI_MODE
, val
);
7714 tw32(SNDBDS_MODE
, SNDBDS_MODE_ENABLE
| SNDBDS_MODE_ATTN_ENABLE
);
7716 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
7717 err
= tg3_load_5701_a0_firmware_fix(tp
);
7722 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
7723 err
= tg3_load_tso_firmware(tp
);
7728 tp
->tx_mode
= TX_MODE_ENABLE
;
7729 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
7732 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
) {
7733 u32 reg
= MAC_RSS_INDIR_TBL_0
;
7734 u8
*ent
= (u8
*)&val
;
7736 /* Setup the indirection table */
7737 for (i
= 0; i
< TG3_RSS_INDIR_TBL_SIZE
; i
++) {
7738 int idx
= i
% sizeof(val
);
7740 ent
[idx
] = i
% (tp
->irq_cnt
- 1);
7741 if (idx
== sizeof(val
) - 1) {
7747 /* Setup the "secret" hash key. */
7748 tw32(MAC_RSS_HASH_KEY_0
, 0x5f865437);
7749 tw32(MAC_RSS_HASH_KEY_1
, 0xe4ac62cc);
7750 tw32(MAC_RSS_HASH_KEY_2
, 0x50103a45);
7751 tw32(MAC_RSS_HASH_KEY_3
, 0x36621985);
7752 tw32(MAC_RSS_HASH_KEY_4
, 0xbf14c0e8);
7753 tw32(MAC_RSS_HASH_KEY_5
, 0x1bc27a1e);
7754 tw32(MAC_RSS_HASH_KEY_6
, 0x84f4b556);
7755 tw32(MAC_RSS_HASH_KEY_7
, 0x094ea6fe);
7756 tw32(MAC_RSS_HASH_KEY_8
, 0x7dda01e7);
7757 tw32(MAC_RSS_HASH_KEY_9
, 0xc04d7481);
7760 tp
->rx_mode
= RX_MODE_ENABLE
;
7761 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
7762 tp
->rx_mode
|= RX_MODE_IPV6_CSUM_ENABLE
;
7764 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
)
7765 tp
->rx_mode
|= RX_MODE_RSS_ENABLE
|
7766 RX_MODE_RSS_ITBL_HASH_BITS_7
|
7767 RX_MODE_RSS_IPV6_HASH_EN
|
7768 RX_MODE_RSS_TCP_IPV6_HASH_EN
|
7769 RX_MODE_RSS_IPV4_HASH_EN
|
7770 RX_MODE_RSS_TCP_IPV4_HASH_EN
;
7772 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
7775 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
7777 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
7778 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
7779 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
7782 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
7785 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
7786 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) &&
7787 !(tp
->tg3_flags2
& TG3_FLG2_SERDES_PREEMPHASIS
)) {
7788 /* Set drive transmission level to 1.2V */
7789 /* only if the signal pre-emphasis bit is not set */
7790 val
= tr32(MAC_SERDES_CFG
);
7793 tw32(MAC_SERDES_CFG
, val
);
7795 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
)
7796 tw32(MAC_SERDES_CFG
, 0x616000);
7799 /* Prevent chip from dropping frames when flow control
7802 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME
, 2);
7804 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
&&
7805 (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
7806 /* Use hardware link auto-negotiation */
7807 tp
->tg3_flags2
|= TG3_FLG2_HW_AUTONEG
;
7810 if ((tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) &&
7811 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
)) {
7814 tmp
= tr32(SERDES_RX_CTRL
);
7815 tw32(SERDES_RX_CTRL
, tmp
| SERDES_RX_SIG_DETECT
);
7816 tp
->grc_local_ctrl
&= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT
;
7817 tp
->grc_local_ctrl
|= GRC_LCLCTRL_USE_SIG_DETECT
;
7818 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
7821 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)) {
7822 if (tp
->link_config
.phy_is_low_power
) {
7823 tp
->link_config
.phy_is_low_power
= 0;
7824 tp
->link_config
.speed
= tp
->link_config
.orig_speed
;
7825 tp
->link_config
.duplex
= tp
->link_config
.orig_duplex
;
7826 tp
->link_config
.autoneg
= tp
->link_config
.orig_autoneg
;
7829 err
= tg3_setup_phy(tp
, 0);
7833 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
7834 !(tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
)) {
7837 /* Clear CRC stats. */
7838 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &tmp
)) {
7839 tg3_writephy(tp
, MII_TG3_TEST1
,
7840 tmp
| MII_TG3_TEST1_CRC_EN
);
7841 tg3_readphy(tp
, 0x14, &tmp
);
7846 __tg3_set_rx_mode(tp
->dev
);
7848 /* Initialize receive rules. */
7849 tw32(MAC_RCV_RULE_0
, 0xc2000000 & RCV_RULE_DISABLE_MASK
);
7850 tw32(MAC_RCV_VALUE_0
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
7851 tw32(MAC_RCV_RULE_1
, 0x86000004 & RCV_RULE_DISABLE_MASK
);
7852 tw32(MAC_RCV_VALUE_1
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
7854 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
7855 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
7859 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)
7863 tw32(MAC_RCV_RULE_15
, 0); tw32(MAC_RCV_VALUE_15
, 0);
7865 tw32(MAC_RCV_RULE_14
, 0); tw32(MAC_RCV_VALUE_14
, 0);
7867 tw32(MAC_RCV_RULE_13
, 0); tw32(MAC_RCV_VALUE_13
, 0);
7869 tw32(MAC_RCV_RULE_12
, 0); tw32(MAC_RCV_VALUE_12
, 0);
7871 tw32(MAC_RCV_RULE_11
, 0); tw32(MAC_RCV_VALUE_11
, 0);
7873 tw32(MAC_RCV_RULE_10
, 0); tw32(MAC_RCV_VALUE_10
, 0);
7875 tw32(MAC_RCV_RULE_9
, 0); tw32(MAC_RCV_VALUE_9
, 0);
7877 tw32(MAC_RCV_RULE_8
, 0); tw32(MAC_RCV_VALUE_8
, 0);
7879 tw32(MAC_RCV_RULE_7
, 0); tw32(MAC_RCV_VALUE_7
, 0);
7881 tw32(MAC_RCV_RULE_6
, 0); tw32(MAC_RCV_VALUE_6
, 0);
7883 tw32(MAC_RCV_RULE_5
, 0); tw32(MAC_RCV_VALUE_5
, 0);
7885 tw32(MAC_RCV_RULE_4
, 0); tw32(MAC_RCV_VALUE_4
, 0);
7887 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7889 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7897 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
7898 /* Write our heartbeat update interval to APE. */
7899 tg3_ape_write32(tp
, TG3_APE_HOST_HEARTBEAT_INT_MS
,
7900 APE_HOST_HEARTBEAT_INT_DISABLE
);
7902 tg3_write_sig_post_reset(tp
, RESET_KIND_INIT
);
7907 /* Called at device open time to get the chip ready for
7908 * packet processing. Invoked with tp->lock held.
7910 static int tg3_init_hw(struct tg3
*tp
, int reset_phy
)
7912 tg3_switch_clocks(tp
);
7914 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
7916 return tg3_reset_hw(tp
, reset_phy
);
7919 #define TG3_STAT_ADD32(PSTAT, REG) \
7920 do { u32 __val = tr32(REG); \
7921 (PSTAT)->low += __val; \
7922 if ((PSTAT)->low < __val) \
7923 (PSTAT)->high += 1; \
7926 static void tg3_periodic_fetch_stats(struct tg3
*tp
)
7928 struct tg3_hw_stats
*sp
= tp
->hw_stats
;
7930 if (!netif_carrier_ok(tp
->dev
))
7933 TG3_STAT_ADD32(&sp
->tx_octets
, MAC_TX_STATS_OCTETS
);
7934 TG3_STAT_ADD32(&sp
->tx_collisions
, MAC_TX_STATS_COLLISIONS
);
7935 TG3_STAT_ADD32(&sp
->tx_xon_sent
, MAC_TX_STATS_XON_SENT
);
7936 TG3_STAT_ADD32(&sp
->tx_xoff_sent
, MAC_TX_STATS_XOFF_SENT
);
7937 TG3_STAT_ADD32(&sp
->tx_mac_errors
, MAC_TX_STATS_MAC_ERRORS
);
7938 TG3_STAT_ADD32(&sp
->tx_single_collisions
, MAC_TX_STATS_SINGLE_COLLISIONS
);
7939 TG3_STAT_ADD32(&sp
->tx_mult_collisions
, MAC_TX_STATS_MULT_COLLISIONS
);
7940 TG3_STAT_ADD32(&sp
->tx_deferred
, MAC_TX_STATS_DEFERRED
);
7941 TG3_STAT_ADD32(&sp
->tx_excessive_collisions
, MAC_TX_STATS_EXCESSIVE_COL
);
7942 TG3_STAT_ADD32(&sp
->tx_late_collisions
, MAC_TX_STATS_LATE_COL
);
7943 TG3_STAT_ADD32(&sp
->tx_ucast_packets
, MAC_TX_STATS_UCAST
);
7944 TG3_STAT_ADD32(&sp
->tx_mcast_packets
, MAC_TX_STATS_MCAST
);
7945 TG3_STAT_ADD32(&sp
->tx_bcast_packets
, MAC_TX_STATS_BCAST
);
7947 TG3_STAT_ADD32(&sp
->rx_octets
, MAC_RX_STATS_OCTETS
);
7948 TG3_STAT_ADD32(&sp
->rx_fragments
, MAC_RX_STATS_FRAGMENTS
);
7949 TG3_STAT_ADD32(&sp
->rx_ucast_packets
, MAC_RX_STATS_UCAST
);
7950 TG3_STAT_ADD32(&sp
->rx_mcast_packets
, MAC_RX_STATS_MCAST
);
7951 TG3_STAT_ADD32(&sp
->rx_bcast_packets
, MAC_RX_STATS_BCAST
);
7952 TG3_STAT_ADD32(&sp
->rx_fcs_errors
, MAC_RX_STATS_FCS_ERRORS
);
7953 TG3_STAT_ADD32(&sp
->rx_align_errors
, MAC_RX_STATS_ALIGN_ERRORS
);
7954 TG3_STAT_ADD32(&sp
->rx_xon_pause_rcvd
, MAC_RX_STATS_XON_PAUSE_RECVD
);
7955 TG3_STAT_ADD32(&sp
->rx_xoff_pause_rcvd
, MAC_RX_STATS_XOFF_PAUSE_RECVD
);
7956 TG3_STAT_ADD32(&sp
->rx_mac_ctrl_rcvd
, MAC_RX_STATS_MAC_CTRL_RECVD
);
7957 TG3_STAT_ADD32(&sp
->rx_xoff_entered
, MAC_RX_STATS_XOFF_ENTERED
);
7958 TG3_STAT_ADD32(&sp
->rx_frame_too_long_errors
, MAC_RX_STATS_FRAME_TOO_LONG
);
7959 TG3_STAT_ADD32(&sp
->rx_jabbers
, MAC_RX_STATS_JABBERS
);
7960 TG3_STAT_ADD32(&sp
->rx_undersize_packets
, MAC_RX_STATS_UNDERSIZE
);
7962 TG3_STAT_ADD32(&sp
->rxbds_empty
, RCVLPC_NO_RCV_BD_CNT
);
7963 TG3_STAT_ADD32(&sp
->rx_discards
, RCVLPC_IN_DISCARDS_CNT
);
7964 TG3_STAT_ADD32(&sp
->rx_errors
, RCVLPC_IN_ERRORS_CNT
);
7967 static void tg3_timer(unsigned long __opaque
)
7969 struct tg3
*tp
= (struct tg3
*) __opaque
;
7974 spin_lock(&tp
->lock
);
7976 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
7977 /* All of this garbage is because when using non-tagged
7978 * IRQ status the mailbox/status_block protocol the chip
7979 * uses with the cpu is race prone.
7981 if (tp
->napi
[0].hw_status
->status
& SD_STATUS_UPDATED
) {
7982 tw32(GRC_LOCAL_CTRL
,
7983 tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
7985 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
7986 HOSTCC_MODE_ENABLE
| HOSTCC_MODE_NOW
);
7989 if (!(tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
7990 tp
->tg3_flags2
|= TG3_FLG2_RESTART_TIMER
;
7991 spin_unlock(&tp
->lock
);
7992 schedule_work(&tp
->reset_task
);
7997 /* This part only runs once per second. */
7998 if (!--tp
->timer_counter
) {
7999 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
8000 tg3_periodic_fetch_stats(tp
);
8002 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
8006 mac_stat
= tr32(MAC_STATUS
);
8009 if (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
) {
8010 if (mac_stat
& MAC_STATUS_MI_INTERRUPT
)
8012 } else if (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)
8016 tg3_setup_phy(tp
, 0);
8017 } else if (tp
->tg3_flags
& TG3_FLAG_POLL_SERDES
) {
8018 u32 mac_stat
= tr32(MAC_STATUS
);
8021 if (netif_carrier_ok(tp
->dev
) &&
8022 (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)) {
8025 if (! netif_carrier_ok(tp
->dev
) &&
8026 (mac_stat
& (MAC_STATUS_PCS_SYNCED
|
8027 MAC_STATUS_SIGNAL_DET
))) {
8031 if (!tp
->serdes_counter
) {
8034 ~MAC_MODE_PORT_MODE_MASK
));
8036 tw32_f(MAC_MODE
, tp
->mac_mode
);
8039 tg3_setup_phy(tp
, 0);
8041 } else if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)
8042 tg3_serdes_parallel_detect(tp
);
8044 tp
->timer_counter
= tp
->timer_multiplier
;
8047 /* Heartbeat is only sent once every 2 seconds.
8049 * The heartbeat is to tell the ASF firmware that the host
8050 * driver is still alive. In the event that the OS crashes,
8051 * ASF needs to reset the hardware to free up the FIFO space
8052 * that may be filled with rx packets destined for the host.
8053 * If the FIFO is full, ASF will no longer function properly.
8055 * Unintended resets have been reported on real time kernels
8056 * where the timer doesn't run on time. Netpoll will also have
8059 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8060 * to check the ring condition when the heartbeat is expiring
8061 * before doing the reset. This will prevent most unintended
8064 if (!--tp
->asf_counter
) {
8065 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
8066 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
8067 tg3_wait_for_event_ack(tp
);
8069 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
,
8070 FWCMD_NICDRV_ALIVE3
);
8071 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 4);
8072 /* 5 seconds timeout */
8073 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
, 5);
8075 tg3_generate_fw_event(tp
);
8077 tp
->asf_counter
= tp
->asf_multiplier
;
8080 spin_unlock(&tp
->lock
);
8083 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
8084 add_timer(&tp
->timer
);
8087 static int tg3_request_irq(struct tg3
*tp
, int irq_num
)
8090 unsigned long flags
;
8092 struct tg3_napi
*tnapi
= &tp
->napi
[irq_num
];
8094 if (tp
->irq_cnt
== 1)
8095 name
= tp
->dev
->name
;
8097 name
= &tnapi
->irq_lbl
[0];
8098 snprintf(name
, IFNAMSIZ
, "%s-%d", tp
->dev
->name
, irq_num
);
8099 name
[IFNAMSIZ
-1] = 0;
8102 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI_OR_MSIX
) {
8104 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)
8106 flags
= IRQF_SAMPLE_RANDOM
;
8109 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
8110 fn
= tg3_interrupt_tagged
;
8111 flags
= IRQF_SHARED
| IRQF_SAMPLE_RANDOM
;
8114 return request_irq(tnapi
->irq_vec
, fn
, flags
, name
, tnapi
);
8117 static int tg3_test_interrupt(struct tg3
*tp
)
8119 struct tg3_napi
*tnapi
= &tp
->napi
[0];
8120 struct net_device
*dev
= tp
->dev
;
8121 int err
, i
, intr_ok
= 0;
8124 if (!netif_running(dev
))
8127 tg3_disable_ints(tp
);
8129 free_irq(tnapi
->irq_vec
, tnapi
);
8132 * Turn off MSI one shot mode. Otherwise this test has no
8133 * observable way to know whether the interrupt was delivered.
8135 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
&&
8136 (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)) {
8137 val
= tr32(MSGINT_MODE
) | MSGINT_MODE_ONE_SHOT_DISABLE
;
8138 tw32(MSGINT_MODE
, val
);
8141 err
= request_irq(tnapi
->irq_vec
, tg3_test_isr
,
8142 IRQF_SHARED
| IRQF_SAMPLE_RANDOM
, dev
->name
, tnapi
);
8146 tnapi
->hw_status
->status
&= ~SD_STATUS_UPDATED
;
8147 tg3_enable_ints(tp
);
8149 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
8152 for (i
= 0; i
< 5; i
++) {
8153 u32 int_mbox
, misc_host_ctrl
;
8155 int_mbox
= tr32_mailbox(tnapi
->int_mbox
);
8156 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
8158 if ((int_mbox
!= 0) ||
8159 (misc_host_ctrl
& MISC_HOST_CTRL_MASK_PCI_INT
)) {
8167 tg3_disable_ints(tp
);
8169 free_irq(tnapi
->irq_vec
, tnapi
);
8171 err
= tg3_request_irq(tp
, 0);
8177 /* Reenable MSI one shot mode. */
8178 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
&&
8179 (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)) {
8180 val
= tr32(MSGINT_MODE
) & ~MSGINT_MODE_ONE_SHOT_DISABLE
;
8181 tw32(MSGINT_MODE
, val
);
8189 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8190 * successfully restored
8192 static int tg3_test_msi(struct tg3
*tp
)
8197 if (!(tp
->tg3_flags2
& TG3_FLG2_USING_MSI
))
8200 /* Turn off SERR reporting in case MSI terminates with Master
8203 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
8204 pci_write_config_word(tp
->pdev
, PCI_COMMAND
,
8205 pci_cmd
& ~PCI_COMMAND_SERR
);
8207 err
= tg3_test_interrupt(tp
);
8209 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
8214 /* other failures */
8218 /* MSI test failed, go back to INTx mode */
8219 printk(KERN_WARNING PFX
"%s: No interrupt was generated using MSI, "
8220 "switching to INTx mode. Please report this failure to "
8221 "the PCI maintainer and include system chipset information.\n",
8224 free_irq(tp
->napi
[0].irq_vec
, &tp
->napi
[0]);
8226 pci_disable_msi(tp
->pdev
);
8228 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
8230 err
= tg3_request_irq(tp
, 0);
8234 /* Need to reset the chip because the MSI cycle may have terminated
8235 * with Master Abort.
8237 tg3_full_lock(tp
, 1);
8239 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8240 err
= tg3_init_hw(tp
, 1);
8242 tg3_full_unlock(tp
);
8245 free_irq(tp
->napi
[0].irq_vec
, &tp
->napi
[0]);
8250 static int tg3_request_firmware(struct tg3
*tp
)
8252 const __be32
*fw_data
;
8254 if (request_firmware(&tp
->fw
, tp
->fw_needed
, &tp
->pdev
->dev
)) {
8255 printk(KERN_ERR
"%s: Failed to load firmware \"%s\"\n",
8256 tp
->dev
->name
, tp
->fw_needed
);
8260 fw_data
= (void *)tp
->fw
->data
;
8262 /* Firmware blob starts with version numbers, followed by
8263 * start address and _full_ length including BSS sections
8264 * (which must be longer than the actual data, of course
8267 tp
->fw_len
= be32_to_cpu(fw_data
[2]); /* includes bss */
8268 if (tp
->fw_len
< (tp
->fw
->size
- 12)) {
8269 printk(KERN_ERR
"%s: bogus length %d in \"%s\"\n",
8270 tp
->dev
->name
, tp
->fw_len
, tp
->fw_needed
);
8271 release_firmware(tp
->fw
);
8276 /* We no longer need firmware; we have it. */
8277 tp
->fw_needed
= NULL
;
8281 static bool tg3_enable_msix(struct tg3
*tp
)
8283 int i
, rc
, cpus
= num_online_cpus();
8284 struct msix_entry msix_ent
[tp
->irq_max
];
8287 /* Just fallback to the simpler MSI mode. */
8291 * We want as many rx rings enabled as there are cpus.
8292 * The first MSIX vector only deals with link interrupts, etc,
8293 * so we add one to the number of vectors we are requesting.
8295 tp
->irq_cnt
= min_t(unsigned, cpus
+ 1, tp
->irq_max
);
8297 for (i
= 0; i
< tp
->irq_max
; i
++) {
8298 msix_ent
[i
].entry
= i
;
8299 msix_ent
[i
].vector
= 0;
8302 rc
= pci_enable_msix(tp
->pdev
, msix_ent
, tp
->irq_cnt
);
8304 if (rc
< TG3_RSS_MIN_NUM_MSIX_VECS
)
8306 if (pci_enable_msix(tp
->pdev
, msix_ent
, rc
))
8309 "%s: Requested %d MSI-X vectors, received %d\n",
8310 tp
->dev
->name
, tp
->irq_cnt
, rc
);
8314 tp
->tg3_flags3
|= TG3_FLG3_ENABLE_RSS
;
8316 for (i
= 0; i
< tp
->irq_max
; i
++)
8317 tp
->napi
[i
].irq_vec
= msix_ent
[i
].vector
;
8319 tp
->dev
->real_num_tx_queues
= tp
->irq_cnt
- 1;
8324 static void tg3_ints_init(struct tg3
*tp
)
8326 if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSI_OR_MSIX
) &&
8327 !(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
8328 /* All MSI supporting chips should support tagged
8329 * status. Assert that this is the case.
8331 printk(KERN_WARNING PFX
"%s: MSI without TAGGED? "
8332 "Not using MSI.\n", tp
->dev
->name
);
8336 if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
) && tg3_enable_msix(tp
))
8337 tp
->tg3_flags2
|= TG3_FLG2_USING_MSIX
;
8338 else if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSI
) &&
8339 pci_enable_msi(tp
->pdev
) == 0)
8340 tp
->tg3_flags2
|= TG3_FLG2_USING_MSI
;
8342 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI_OR_MSIX
) {
8343 u32 msi_mode
= tr32(MSGINT_MODE
);
8344 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)
8345 msi_mode
|= MSGINT_MODE_MULTIVEC_EN
;
8346 tw32(MSGINT_MODE
, msi_mode
| MSGINT_MODE_ENABLE
);
8349 if (!(tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)) {
8351 tp
->napi
[0].irq_vec
= tp
->pdev
->irq
;
8352 tp
->dev
->real_num_tx_queues
= 1;
8356 static void tg3_ints_fini(struct tg3
*tp
)
8358 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)
8359 pci_disable_msix(tp
->pdev
);
8360 else if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)
8361 pci_disable_msi(tp
->pdev
);
8362 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI_OR_MSIX
;
8363 tp
->tg3_flags3
&= ~TG3_FLG3_ENABLE_RSS
;
8366 static int tg3_open(struct net_device
*dev
)
8368 struct tg3
*tp
= netdev_priv(dev
);
8371 if (tp
->fw_needed
) {
8372 err
= tg3_request_firmware(tp
);
8373 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
8377 printk(KERN_WARNING
"%s: TSO capability disabled.\n",
8379 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
8380 } else if (!(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
8381 printk(KERN_NOTICE
"%s: TSO capability restored.\n",
8383 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
8387 netif_carrier_off(tp
->dev
);
8389 err
= tg3_set_power_state(tp
, PCI_D0
);
8393 tg3_full_lock(tp
, 0);
8395 tg3_disable_ints(tp
);
8396 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
8398 tg3_full_unlock(tp
);
8401 * Setup interrupts first so we know how
8402 * many NAPI resources to allocate
8406 /* The placement of this call is tied
8407 * to the setup and use of Host TX descriptors.
8409 err
= tg3_alloc_consistent(tp
);
8413 tg3_napi_enable(tp
);
8415 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
8416 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8417 err
= tg3_request_irq(tp
, i
);
8419 for (i
--; i
>= 0; i
--)
8420 free_irq(tnapi
->irq_vec
, tnapi
);
8428 tg3_full_lock(tp
, 0);
8430 err
= tg3_init_hw(tp
, 1);
8432 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8435 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
8436 tp
->timer_offset
= HZ
;
8438 tp
->timer_offset
= HZ
/ 10;
8440 BUG_ON(tp
->timer_offset
> HZ
);
8441 tp
->timer_counter
= tp
->timer_multiplier
=
8442 (HZ
/ tp
->timer_offset
);
8443 tp
->asf_counter
= tp
->asf_multiplier
=
8444 ((HZ
/ tp
->timer_offset
) * 2);
8446 init_timer(&tp
->timer
);
8447 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
8448 tp
->timer
.data
= (unsigned long) tp
;
8449 tp
->timer
.function
= tg3_timer
;
8452 tg3_full_unlock(tp
);
8457 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
8458 err
= tg3_test_msi(tp
);
8461 tg3_full_lock(tp
, 0);
8462 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8464 tg3_full_unlock(tp
);
8469 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5717
&&
8470 (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) &&
8471 (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)) {
8472 u32 val
= tr32(PCIE_TRANSACTION_CFG
);
8474 tw32(PCIE_TRANSACTION_CFG
,
8475 val
| PCIE_TRANS_CFG_1SHOT_MSI
);
8481 tg3_full_lock(tp
, 0);
8483 add_timer(&tp
->timer
);
8484 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
8485 tg3_enable_ints(tp
);
8487 tg3_full_unlock(tp
);
8489 netif_tx_start_all_queues(dev
);
8494 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--) {
8495 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8496 free_irq(tnapi
->irq_vec
, tnapi
);
8500 tg3_napi_disable(tp
);
8501 tg3_free_consistent(tp
);
8509 /*static*/ void tg3_dump_state(struct tg3
*tp
)
8511 u32 val32
, val32_2
, val32_3
, val32_4
, val32_5
;
8514 struct tg3_hw_status
*sblk
= tp
->napi
[0]->hw_status
;
8516 pci_read_config_word(tp
->pdev
, PCI_STATUS
, &val16
);
8517 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, &val32
);
8518 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8522 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8523 tr32(MAC_MODE
), tr32(MAC_STATUS
));
8524 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8525 tr32(MAC_EVENT
), tr32(MAC_LED_CTRL
));
8526 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8527 tr32(MAC_TX_MODE
), tr32(MAC_TX_STATUS
));
8528 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8529 tr32(MAC_RX_MODE
), tr32(MAC_RX_STATUS
));
8531 /* Send data initiator control block */
8532 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8533 tr32(SNDDATAI_MODE
), tr32(SNDDATAI_STATUS
));
8534 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8535 tr32(SNDDATAI_STATSCTRL
));
8537 /* Send data completion control block */
8538 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE
));
8540 /* Send BD ring selector block */
8541 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8542 tr32(SNDBDS_MODE
), tr32(SNDBDS_STATUS
));
8544 /* Send BD initiator control block */
8545 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8546 tr32(SNDBDI_MODE
), tr32(SNDBDI_STATUS
));
8548 /* Send BD completion control block */
8549 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE
));
8551 /* Receive list placement control block */
8552 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8553 tr32(RCVLPC_MODE
), tr32(RCVLPC_STATUS
));
8554 printk(" RCVLPC_STATSCTRL[%08x]\n",
8555 tr32(RCVLPC_STATSCTRL
));
8557 /* Receive data and receive BD initiator control block */
8558 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8559 tr32(RCVDBDI_MODE
), tr32(RCVDBDI_STATUS
));
8561 /* Receive data completion control block */
8562 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8565 /* Receive BD initiator control block */
8566 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8567 tr32(RCVBDI_MODE
), tr32(RCVBDI_STATUS
));
8569 /* Receive BD completion control block */
8570 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8571 tr32(RCVCC_MODE
), tr32(RCVCC_STATUS
));
8573 /* Receive list selector control block */
8574 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8575 tr32(RCVLSC_MODE
), tr32(RCVLSC_STATUS
));
8577 /* Mbuf cluster free block */
8578 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8579 tr32(MBFREE_MODE
), tr32(MBFREE_STATUS
));
8581 /* Host coalescing control block */
8582 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8583 tr32(HOSTCC_MODE
), tr32(HOSTCC_STATUS
));
8584 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8585 tr32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
8586 tr32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
));
8587 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8588 tr32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
8589 tr32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
));
8590 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8591 tr32(HOSTCC_STATS_BLK_NIC_ADDR
));
8592 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8593 tr32(HOSTCC_STATUS_BLK_NIC_ADDR
));
8595 /* Memory arbiter control block */
8596 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8597 tr32(MEMARB_MODE
), tr32(MEMARB_STATUS
));
8599 /* Buffer manager control block */
8600 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8601 tr32(BUFMGR_MODE
), tr32(BUFMGR_STATUS
));
8602 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8603 tr32(BUFMGR_MB_POOL_ADDR
), tr32(BUFMGR_MB_POOL_SIZE
));
8604 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8605 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8606 tr32(BUFMGR_DMA_DESC_POOL_ADDR
),
8607 tr32(BUFMGR_DMA_DESC_POOL_SIZE
));
8609 /* Read DMA control block */
8610 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8611 tr32(RDMAC_MODE
), tr32(RDMAC_STATUS
));
8613 /* Write DMA control block */
8614 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8615 tr32(WDMAC_MODE
), tr32(WDMAC_STATUS
));
8617 /* DMA completion block */
8618 printk("DEBUG: DMAC_MODE[%08x]\n",
8622 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8623 tr32(GRC_MODE
), tr32(GRC_MISC_CFG
));
8624 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8625 tr32(GRC_LOCAL_CTRL
));
8628 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8629 tr32(RCVDBDI_JUMBO_BD
+ 0x0),
8630 tr32(RCVDBDI_JUMBO_BD
+ 0x4),
8631 tr32(RCVDBDI_JUMBO_BD
+ 0x8),
8632 tr32(RCVDBDI_JUMBO_BD
+ 0xc));
8633 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8634 tr32(RCVDBDI_STD_BD
+ 0x0),
8635 tr32(RCVDBDI_STD_BD
+ 0x4),
8636 tr32(RCVDBDI_STD_BD
+ 0x8),
8637 tr32(RCVDBDI_STD_BD
+ 0xc));
8638 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8639 tr32(RCVDBDI_MINI_BD
+ 0x0),
8640 tr32(RCVDBDI_MINI_BD
+ 0x4),
8641 tr32(RCVDBDI_MINI_BD
+ 0x8),
8642 tr32(RCVDBDI_MINI_BD
+ 0xc));
8644 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0x0, &val32
);
8645 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0x4, &val32_2
);
8646 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0x8, &val32_3
);
8647 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0xc, &val32_4
);
8648 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8649 val32
, val32_2
, val32_3
, val32_4
);
8651 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0x0, &val32
);
8652 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0x4, &val32_2
);
8653 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0x8, &val32_3
);
8654 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0xc, &val32_4
);
8655 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8656 val32
, val32_2
, val32_3
, val32_4
);
8658 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x0, &val32
);
8659 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x4, &val32_2
);
8660 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x8, &val32_3
);
8661 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0xc, &val32_4
);
8662 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x10, &val32_5
);
8663 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8664 val32
, val32_2
, val32_3
, val32_4
, val32_5
);
8666 /* SW status block */
8668 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8671 sblk
->rx_jumbo_consumer
,
8673 sblk
->rx_mini_consumer
,
8674 sblk
->idx
[0].rx_producer
,
8675 sblk
->idx
[0].tx_consumer
);
8677 /* SW statistics block */
8678 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8679 ((u32
*)tp
->hw_stats
)[0],
8680 ((u32
*)tp
->hw_stats
)[1],
8681 ((u32
*)tp
->hw_stats
)[2],
8682 ((u32
*)tp
->hw_stats
)[3]);
8685 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8686 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0
+ 0x0),
8687 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0
+ 0x4),
8688 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0
+ 0x0),
8689 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0
+ 0x4));
8691 /* NIC side send descriptors. */
8692 for (i
= 0; i
< 6; i
++) {
8695 txd
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_TX_BUFFER_DESC
8696 + (i
* sizeof(struct tg3_tx_buffer_desc
));
8697 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8699 readl(txd
+ 0x0), readl(txd
+ 0x4),
8700 readl(txd
+ 0x8), readl(txd
+ 0xc));
8703 /* NIC side RX descriptors. */
8704 for (i
= 0; i
< 6; i
++) {
8707 rxd
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_RX_BUFFER_DESC
8708 + (i
* sizeof(struct tg3_rx_buffer_desc
));
8709 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8711 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
8712 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
8713 rxd
+= (4 * sizeof(u32
));
8714 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8716 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
8717 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
8720 for (i
= 0; i
< 6; i
++) {
8723 rxd
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_RX_JUMBO_BUFFER_DESC
8724 + (i
* sizeof(struct tg3_rx_buffer_desc
));
8725 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8727 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
8728 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
8729 rxd
+= (4 * sizeof(u32
));
8730 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8732 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
8733 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
8738 static struct net_device_stats
*tg3_get_stats(struct net_device
*);
8739 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*);
8741 static int tg3_close(struct net_device
*dev
)
8744 struct tg3
*tp
= netdev_priv(dev
);
8746 tg3_napi_disable(tp
);
8747 cancel_work_sync(&tp
->reset_task
);
8749 netif_tx_stop_all_queues(dev
);
8751 del_timer_sync(&tp
->timer
);
8755 tg3_full_lock(tp
, 1);
8760 tg3_disable_ints(tp
);
8762 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8764 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
8766 tg3_full_unlock(tp
);
8768 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--) {
8769 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8770 free_irq(tnapi
->irq_vec
, tnapi
);
8775 memcpy(&tp
->net_stats_prev
, tg3_get_stats(tp
->dev
),
8776 sizeof(tp
->net_stats_prev
));
8777 memcpy(&tp
->estats_prev
, tg3_get_estats(tp
),
8778 sizeof(tp
->estats_prev
));
8780 tg3_free_consistent(tp
);
8782 tg3_set_power_state(tp
, PCI_D3hot
);
8784 netif_carrier_off(tp
->dev
);
8789 static inline unsigned long get_stat64(tg3_stat64_t
*val
)
8793 #if (BITS_PER_LONG == 32)
8796 ret
= ((u64
)val
->high
<< 32) | ((u64
)val
->low
);
8801 static inline u64
get_estat64(tg3_stat64_t
*val
)
8803 return ((u64
)val
->high
<< 32) | ((u64
)val
->low
);
8806 static unsigned long calc_crc_errors(struct tg3
*tp
)
8808 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
8810 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
8811 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
8812 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
8815 spin_lock_bh(&tp
->lock
);
8816 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &val
)) {
8817 tg3_writephy(tp
, MII_TG3_TEST1
,
8818 val
| MII_TG3_TEST1_CRC_EN
);
8819 tg3_readphy(tp
, 0x14, &val
);
8822 spin_unlock_bh(&tp
->lock
);
8824 tp
->phy_crc_errors
+= val
;
8826 return tp
->phy_crc_errors
;
8829 return get_stat64(&hw_stats
->rx_fcs_errors
);
8832 #define ESTAT_ADD(member) \
8833 estats->member = old_estats->member + \
8834 get_estat64(&hw_stats->member)
8836 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*tp
)
8838 struct tg3_ethtool_stats
*estats
= &tp
->estats
;
8839 struct tg3_ethtool_stats
*old_estats
= &tp
->estats_prev
;
8840 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
8845 ESTAT_ADD(rx_octets
);
8846 ESTAT_ADD(rx_fragments
);
8847 ESTAT_ADD(rx_ucast_packets
);
8848 ESTAT_ADD(rx_mcast_packets
);
8849 ESTAT_ADD(rx_bcast_packets
);
8850 ESTAT_ADD(rx_fcs_errors
);
8851 ESTAT_ADD(rx_align_errors
);
8852 ESTAT_ADD(rx_xon_pause_rcvd
);
8853 ESTAT_ADD(rx_xoff_pause_rcvd
);
8854 ESTAT_ADD(rx_mac_ctrl_rcvd
);
8855 ESTAT_ADD(rx_xoff_entered
);
8856 ESTAT_ADD(rx_frame_too_long_errors
);
8857 ESTAT_ADD(rx_jabbers
);
8858 ESTAT_ADD(rx_undersize_packets
);
8859 ESTAT_ADD(rx_in_length_errors
);
8860 ESTAT_ADD(rx_out_length_errors
);
8861 ESTAT_ADD(rx_64_or_less_octet_packets
);
8862 ESTAT_ADD(rx_65_to_127_octet_packets
);
8863 ESTAT_ADD(rx_128_to_255_octet_packets
);
8864 ESTAT_ADD(rx_256_to_511_octet_packets
);
8865 ESTAT_ADD(rx_512_to_1023_octet_packets
);
8866 ESTAT_ADD(rx_1024_to_1522_octet_packets
);
8867 ESTAT_ADD(rx_1523_to_2047_octet_packets
);
8868 ESTAT_ADD(rx_2048_to_4095_octet_packets
);
8869 ESTAT_ADD(rx_4096_to_8191_octet_packets
);
8870 ESTAT_ADD(rx_8192_to_9022_octet_packets
);
8872 ESTAT_ADD(tx_octets
);
8873 ESTAT_ADD(tx_collisions
);
8874 ESTAT_ADD(tx_xon_sent
);
8875 ESTAT_ADD(tx_xoff_sent
);
8876 ESTAT_ADD(tx_flow_control
);
8877 ESTAT_ADD(tx_mac_errors
);
8878 ESTAT_ADD(tx_single_collisions
);
8879 ESTAT_ADD(tx_mult_collisions
);
8880 ESTAT_ADD(tx_deferred
);
8881 ESTAT_ADD(tx_excessive_collisions
);
8882 ESTAT_ADD(tx_late_collisions
);
8883 ESTAT_ADD(tx_collide_2times
);
8884 ESTAT_ADD(tx_collide_3times
);
8885 ESTAT_ADD(tx_collide_4times
);
8886 ESTAT_ADD(tx_collide_5times
);
8887 ESTAT_ADD(tx_collide_6times
);
8888 ESTAT_ADD(tx_collide_7times
);
8889 ESTAT_ADD(tx_collide_8times
);
8890 ESTAT_ADD(tx_collide_9times
);
8891 ESTAT_ADD(tx_collide_10times
);
8892 ESTAT_ADD(tx_collide_11times
);
8893 ESTAT_ADD(tx_collide_12times
);
8894 ESTAT_ADD(tx_collide_13times
);
8895 ESTAT_ADD(tx_collide_14times
);
8896 ESTAT_ADD(tx_collide_15times
);
8897 ESTAT_ADD(tx_ucast_packets
);
8898 ESTAT_ADD(tx_mcast_packets
);
8899 ESTAT_ADD(tx_bcast_packets
);
8900 ESTAT_ADD(tx_carrier_sense_errors
);
8901 ESTAT_ADD(tx_discards
);
8902 ESTAT_ADD(tx_errors
);
8904 ESTAT_ADD(dma_writeq_full
);
8905 ESTAT_ADD(dma_write_prioq_full
);
8906 ESTAT_ADD(rxbds_empty
);
8907 ESTAT_ADD(rx_discards
);
8908 ESTAT_ADD(rx_errors
);
8909 ESTAT_ADD(rx_threshold_hit
);
8911 ESTAT_ADD(dma_readq_full
);
8912 ESTAT_ADD(dma_read_prioq_full
);
8913 ESTAT_ADD(tx_comp_queue_full
);
8915 ESTAT_ADD(ring_set_send_prod_index
);
8916 ESTAT_ADD(ring_status_update
);
8917 ESTAT_ADD(nic_irqs
);
8918 ESTAT_ADD(nic_avoided_irqs
);
8919 ESTAT_ADD(nic_tx_threshold_hit
);
8924 static struct net_device_stats
*tg3_get_stats(struct net_device
*dev
)
8926 struct tg3
*tp
= netdev_priv(dev
);
8927 struct net_device_stats
*stats
= &tp
->net_stats
;
8928 struct net_device_stats
*old_stats
= &tp
->net_stats_prev
;
8929 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
8934 stats
->rx_packets
= old_stats
->rx_packets
+
8935 get_stat64(&hw_stats
->rx_ucast_packets
) +
8936 get_stat64(&hw_stats
->rx_mcast_packets
) +
8937 get_stat64(&hw_stats
->rx_bcast_packets
);
8939 stats
->tx_packets
= old_stats
->tx_packets
+
8940 get_stat64(&hw_stats
->tx_ucast_packets
) +
8941 get_stat64(&hw_stats
->tx_mcast_packets
) +
8942 get_stat64(&hw_stats
->tx_bcast_packets
);
8944 stats
->rx_bytes
= old_stats
->rx_bytes
+
8945 get_stat64(&hw_stats
->rx_octets
);
8946 stats
->tx_bytes
= old_stats
->tx_bytes
+
8947 get_stat64(&hw_stats
->tx_octets
);
8949 stats
->rx_errors
= old_stats
->rx_errors
+
8950 get_stat64(&hw_stats
->rx_errors
);
8951 stats
->tx_errors
= old_stats
->tx_errors
+
8952 get_stat64(&hw_stats
->tx_errors
) +
8953 get_stat64(&hw_stats
->tx_mac_errors
) +
8954 get_stat64(&hw_stats
->tx_carrier_sense_errors
) +
8955 get_stat64(&hw_stats
->tx_discards
);
8957 stats
->multicast
= old_stats
->multicast
+
8958 get_stat64(&hw_stats
->rx_mcast_packets
);
8959 stats
->collisions
= old_stats
->collisions
+
8960 get_stat64(&hw_stats
->tx_collisions
);
8962 stats
->rx_length_errors
= old_stats
->rx_length_errors
+
8963 get_stat64(&hw_stats
->rx_frame_too_long_errors
) +
8964 get_stat64(&hw_stats
->rx_undersize_packets
);
8966 stats
->rx_over_errors
= old_stats
->rx_over_errors
+
8967 get_stat64(&hw_stats
->rxbds_empty
);
8968 stats
->rx_frame_errors
= old_stats
->rx_frame_errors
+
8969 get_stat64(&hw_stats
->rx_align_errors
);
8970 stats
->tx_aborted_errors
= old_stats
->tx_aborted_errors
+
8971 get_stat64(&hw_stats
->tx_discards
);
8972 stats
->tx_carrier_errors
= old_stats
->tx_carrier_errors
+
8973 get_stat64(&hw_stats
->tx_carrier_sense_errors
);
8975 stats
->rx_crc_errors
= old_stats
->rx_crc_errors
+
8976 calc_crc_errors(tp
);
8978 stats
->rx_missed_errors
= old_stats
->rx_missed_errors
+
8979 get_stat64(&hw_stats
->rx_discards
);
8984 static inline u32
calc_crc(unsigned char *buf
, int len
)
8992 for (j
= 0; j
< len
; j
++) {
8995 for (k
= 0; k
< 8; k
++) {
9009 static void tg3_set_multi(struct tg3
*tp
, unsigned int accept_all
)
9011 /* accept or reject all multicast frames */
9012 tw32(MAC_HASH_REG_0
, accept_all
? 0xffffffff : 0);
9013 tw32(MAC_HASH_REG_1
, accept_all
? 0xffffffff : 0);
9014 tw32(MAC_HASH_REG_2
, accept_all
? 0xffffffff : 0);
9015 tw32(MAC_HASH_REG_3
, accept_all
? 0xffffffff : 0);
9018 static void __tg3_set_rx_mode(struct net_device
*dev
)
9020 struct tg3
*tp
= netdev_priv(dev
);
9023 rx_mode
= tp
->rx_mode
& ~(RX_MODE_PROMISC
|
9024 RX_MODE_KEEP_VLAN_TAG
);
9026 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9029 #if TG3_VLAN_TAG_USED
9031 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
9032 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
9034 /* By definition, VLAN is disabled always in this
9037 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
9038 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
9041 if (dev
->flags
& IFF_PROMISC
) {
9042 /* Promiscuous mode. */
9043 rx_mode
|= RX_MODE_PROMISC
;
9044 } else if (dev
->flags
& IFF_ALLMULTI
) {
9045 /* Accept all multicast. */
9046 tg3_set_multi (tp
, 1);
9047 } else if (dev
->mc_count
< 1) {
9048 /* Reject all multicast. */
9049 tg3_set_multi (tp
, 0);
9051 /* Accept one or more multicast(s). */
9052 struct dev_mc_list
*mclist
;
9054 u32 mc_filter
[4] = { 0, };
9059 for (i
= 0, mclist
= dev
->mc_list
; mclist
&& i
< dev
->mc_count
;
9060 i
++, mclist
= mclist
->next
) {
9062 crc
= calc_crc (mclist
->dmi_addr
, ETH_ALEN
);
9064 regidx
= (bit
& 0x60) >> 5;
9066 mc_filter
[regidx
] |= (1 << bit
);
9069 tw32(MAC_HASH_REG_0
, mc_filter
[0]);
9070 tw32(MAC_HASH_REG_1
, mc_filter
[1]);
9071 tw32(MAC_HASH_REG_2
, mc_filter
[2]);
9072 tw32(MAC_HASH_REG_3
, mc_filter
[3]);
9075 if (rx_mode
!= tp
->rx_mode
) {
9076 tp
->rx_mode
= rx_mode
;
9077 tw32_f(MAC_RX_MODE
, rx_mode
);
9082 static void tg3_set_rx_mode(struct net_device
*dev
)
9084 struct tg3
*tp
= netdev_priv(dev
);
9086 if (!netif_running(dev
))
9089 tg3_full_lock(tp
, 0);
9090 __tg3_set_rx_mode(dev
);
9091 tg3_full_unlock(tp
);
9094 #define TG3_REGDUMP_LEN (32 * 1024)
9096 static int tg3_get_regs_len(struct net_device
*dev
)
9098 return TG3_REGDUMP_LEN
;
9101 static void tg3_get_regs(struct net_device
*dev
,
9102 struct ethtool_regs
*regs
, void *_p
)
9105 struct tg3
*tp
= netdev_priv(dev
);
9111 memset(p
, 0, TG3_REGDUMP_LEN
);
9113 if (tp
->link_config
.phy_is_low_power
)
9116 tg3_full_lock(tp
, 0);
9118 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
9119 #define GET_REG32_LOOP(base,len) \
9120 do { p = (u32 *)(orig_p + (base)); \
9121 for (i = 0; i < len; i += 4) \
9122 __GET_REG32((base) + i); \
9124 #define GET_REG32_1(reg) \
9125 do { p = (u32 *)(orig_p + (reg)); \
9126 __GET_REG32((reg)); \
9129 GET_REG32_LOOP(TG3PCI_VENDOR
, 0xb0);
9130 GET_REG32_LOOP(MAILBOX_INTERRUPT_0
, 0x200);
9131 GET_REG32_LOOP(MAC_MODE
, 0x4f0);
9132 GET_REG32_LOOP(SNDDATAI_MODE
, 0xe0);
9133 GET_REG32_1(SNDDATAC_MODE
);
9134 GET_REG32_LOOP(SNDBDS_MODE
, 0x80);
9135 GET_REG32_LOOP(SNDBDI_MODE
, 0x48);
9136 GET_REG32_1(SNDBDC_MODE
);
9137 GET_REG32_LOOP(RCVLPC_MODE
, 0x20);
9138 GET_REG32_LOOP(RCVLPC_SELLST_BASE
, 0x15c);
9139 GET_REG32_LOOP(RCVDBDI_MODE
, 0x0c);
9140 GET_REG32_LOOP(RCVDBDI_JUMBO_BD
, 0x3c);
9141 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0
, 0x44);
9142 GET_REG32_1(RCVDCC_MODE
);
9143 GET_REG32_LOOP(RCVBDI_MODE
, 0x20);
9144 GET_REG32_LOOP(RCVCC_MODE
, 0x14);
9145 GET_REG32_LOOP(RCVLSC_MODE
, 0x08);
9146 GET_REG32_1(MBFREE_MODE
);
9147 GET_REG32_LOOP(HOSTCC_MODE
, 0x100);
9148 GET_REG32_LOOP(MEMARB_MODE
, 0x10);
9149 GET_REG32_LOOP(BUFMGR_MODE
, 0x58);
9150 GET_REG32_LOOP(RDMAC_MODE
, 0x08);
9151 GET_REG32_LOOP(WDMAC_MODE
, 0x08);
9152 GET_REG32_1(RX_CPU_MODE
);
9153 GET_REG32_1(RX_CPU_STATE
);
9154 GET_REG32_1(RX_CPU_PGMCTR
);
9155 GET_REG32_1(RX_CPU_HWBKPT
);
9156 GET_REG32_1(TX_CPU_MODE
);
9157 GET_REG32_1(TX_CPU_STATE
);
9158 GET_REG32_1(TX_CPU_PGMCTR
);
9159 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0
, 0x110);
9160 GET_REG32_LOOP(FTQ_RESET
, 0x120);
9161 GET_REG32_LOOP(MSGINT_MODE
, 0x0c);
9162 GET_REG32_1(DMAC_MODE
);
9163 GET_REG32_LOOP(GRC_MODE
, 0x4c);
9164 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
9165 GET_REG32_LOOP(NVRAM_CMD
, 0x24);
9168 #undef GET_REG32_LOOP
9171 tg3_full_unlock(tp
);
9174 static int tg3_get_eeprom_len(struct net_device
*dev
)
9176 struct tg3
*tp
= netdev_priv(dev
);
9178 return tp
->nvram_size
;
9181 static int tg3_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
9183 struct tg3
*tp
= netdev_priv(dev
);
9186 u32 i
, offset
, len
, b_offset
, b_count
;
9189 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
)
9192 if (tp
->link_config
.phy_is_low_power
)
9195 offset
= eeprom
->offset
;
9199 eeprom
->magic
= TG3_EEPROM_MAGIC
;
9202 /* adjustments to start on required 4 byte boundary */
9203 b_offset
= offset
& 3;
9204 b_count
= 4 - b_offset
;
9205 if (b_count
> len
) {
9206 /* i.e. offset=1 len=2 */
9209 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &val
);
9212 memcpy(data
, ((char*)&val
) + b_offset
, b_count
);
9215 eeprom
->len
+= b_count
;
9218 /* read bytes upto the last 4 byte boundary */
9219 pd
= &data
[eeprom
->len
];
9220 for (i
= 0; i
< (len
- (len
& 3)); i
+= 4) {
9221 ret
= tg3_nvram_read_be32(tp
, offset
+ i
, &val
);
9226 memcpy(pd
+ i
, &val
, 4);
9231 /* read last bytes not ending on 4 byte boundary */
9232 pd
= &data
[eeprom
->len
];
9234 b_offset
= offset
+ len
- b_count
;
9235 ret
= tg3_nvram_read_be32(tp
, b_offset
, &val
);
9238 memcpy(pd
, &val
, b_count
);
9239 eeprom
->len
+= b_count
;
9244 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
);
9246 static int tg3_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
9248 struct tg3
*tp
= netdev_priv(dev
);
9250 u32 offset
, len
, b_offset
, odd_len
;
9254 if (tp
->link_config
.phy_is_low_power
)
9257 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
9258 eeprom
->magic
!= TG3_EEPROM_MAGIC
)
9261 offset
= eeprom
->offset
;
9264 if ((b_offset
= (offset
& 3))) {
9265 /* adjustments to start on required 4 byte boundary */
9266 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &start
);
9277 /* adjustments to end on required 4 byte boundary */
9279 len
= (len
+ 3) & ~3;
9280 ret
= tg3_nvram_read_be32(tp
, offset
+len
-4, &end
);
9286 if (b_offset
|| odd_len
) {
9287 buf
= kmalloc(len
, GFP_KERNEL
);
9291 memcpy(buf
, &start
, 4);
9293 memcpy(buf
+len
-4, &end
, 4);
9294 memcpy(buf
+ b_offset
, data
, eeprom
->len
);
9297 ret
= tg3_nvram_write_block(tp
, offset
, len
, buf
);
9305 static int tg3_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
9307 struct tg3
*tp
= netdev_priv(dev
);
9309 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9310 struct phy_device
*phydev
;
9311 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
9313 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
9314 return phy_ethtool_gset(phydev
, cmd
);
9317 cmd
->supported
= (SUPPORTED_Autoneg
);
9319 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
9320 cmd
->supported
|= (SUPPORTED_1000baseT_Half
|
9321 SUPPORTED_1000baseT_Full
);
9323 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)) {
9324 cmd
->supported
|= (SUPPORTED_100baseT_Half
|
9325 SUPPORTED_100baseT_Full
|
9326 SUPPORTED_10baseT_Half
|
9327 SUPPORTED_10baseT_Full
|
9329 cmd
->port
= PORT_TP
;
9331 cmd
->supported
|= SUPPORTED_FIBRE
;
9332 cmd
->port
= PORT_FIBRE
;
9335 cmd
->advertising
= tp
->link_config
.advertising
;
9336 if (netif_running(dev
)) {
9337 cmd
->speed
= tp
->link_config
.active_speed
;
9338 cmd
->duplex
= tp
->link_config
.active_duplex
;
9340 cmd
->phy_address
= tp
->phy_addr
;
9341 cmd
->transceiver
= XCVR_INTERNAL
;
9342 cmd
->autoneg
= tp
->link_config
.autoneg
;
9348 static int tg3_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
9350 struct tg3
*tp
= netdev_priv(dev
);
9352 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9353 struct phy_device
*phydev
;
9354 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
9356 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
9357 return phy_ethtool_sset(phydev
, cmd
);
9360 if (cmd
->autoneg
!= AUTONEG_ENABLE
&&
9361 cmd
->autoneg
!= AUTONEG_DISABLE
)
9364 if (cmd
->autoneg
== AUTONEG_DISABLE
&&
9365 cmd
->duplex
!= DUPLEX_FULL
&&
9366 cmd
->duplex
!= DUPLEX_HALF
)
9369 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
9370 u32 mask
= ADVERTISED_Autoneg
|
9372 ADVERTISED_Asym_Pause
;
9374 if (!(tp
->tg3_flags2
& TG3_FLAG_10_100_ONLY
))
9375 mask
|= ADVERTISED_1000baseT_Half
|
9376 ADVERTISED_1000baseT_Full
;
9378 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
))
9379 mask
|= ADVERTISED_100baseT_Half
|
9380 ADVERTISED_100baseT_Full
|
9381 ADVERTISED_10baseT_Half
|
9382 ADVERTISED_10baseT_Full
|
9385 mask
|= ADVERTISED_FIBRE
;
9387 if (cmd
->advertising
& ~mask
)
9390 mask
&= (ADVERTISED_1000baseT_Half
|
9391 ADVERTISED_1000baseT_Full
|
9392 ADVERTISED_100baseT_Half
|
9393 ADVERTISED_100baseT_Full
|
9394 ADVERTISED_10baseT_Half
|
9395 ADVERTISED_10baseT_Full
);
9397 cmd
->advertising
&= mask
;
9399 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
) {
9400 if (cmd
->speed
!= SPEED_1000
)
9403 if (cmd
->duplex
!= DUPLEX_FULL
)
9406 if (cmd
->speed
!= SPEED_100
&&
9407 cmd
->speed
!= SPEED_10
)
9412 tg3_full_lock(tp
, 0);
9414 tp
->link_config
.autoneg
= cmd
->autoneg
;
9415 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
9416 tp
->link_config
.advertising
= (cmd
->advertising
|
9417 ADVERTISED_Autoneg
);
9418 tp
->link_config
.speed
= SPEED_INVALID
;
9419 tp
->link_config
.duplex
= DUPLEX_INVALID
;
9421 tp
->link_config
.advertising
= 0;
9422 tp
->link_config
.speed
= cmd
->speed
;
9423 tp
->link_config
.duplex
= cmd
->duplex
;
9426 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
9427 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
9428 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
9430 if (netif_running(dev
))
9431 tg3_setup_phy(tp
, 1);
9433 tg3_full_unlock(tp
);
9438 static void tg3_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
9440 struct tg3
*tp
= netdev_priv(dev
);
9442 strcpy(info
->driver
, DRV_MODULE_NAME
);
9443 strcpy(info
->version
, DRV_MODULE_VERSION
);
9444 strcpy(info
->fw_version
, tp
->fw_ver
);
9445 strcpy(info
->bus_info
, pci_name(tp
->pdev
));
9448 static void tg3_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
9450 struct tg3
*tp
= netdev_priv(dev
);
9452 if ((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) &&
9453 device_can_wakeup(&tp
->pdev
->dev
))
9454 wol
->supported
= WAKE_MAGIC
;
9458 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) &&
9459 device_can_wakeup(&tp
->pdev
->dev
))
9460 wol
->wolopts
= WAKE_MAGIC
;
9461 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
9464 static int tg3_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
9466 struct tg3
*tp
= netdev_priv(dev
);
9467 struct device
*dp
= &tp
->pdev
->dev
;
9469 if (wol
->wolopts
& ~WAKE_MAGIC
)
9471 if ((wol
->wolopts
& WAKE_MAGIC
) &&
9472 !((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) && device_can_wakeup(dp
)))
9475 spin_lock_bh(&tp
->lock
);
9476 if (wol
->wolopts
& WAKE_MAGIC
) {
9477 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
9478 device_set_wakeup_enable(dp
, true);
9480 tp
->tg3_flags
&= ~TG3_FLAG_WOL_ENABLE
;
9481 device_set_wakeup_enable(dp
, false);
9483 spin_unlock_bh(&tp
->lock
);
9488 static u32
tg3_get_msglevel(struct net_device
*dev
)
9490 struct tg3
*tp
= netdev_priv(dev
);
9491 return tp
->msg_enable
;
9494 static void tg3_set_msglevel(struct net_device
*dev
, u32 value
)
9496 struct tg3
*tp
= netdev_priv(dev
);
9497 tp
->msg_enable
= value
;
9500 static int tg3_set_tso(struct net_device
*dev
, u32 value
)
9502 struct tg3
*tp
= netdev_priv(dev
);
9504 if (!(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
9509 if ((dev
->features
& NETIF_F_IPV6_CSUM
) &&
9510 (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
)) {
9512 dev
->features
|= NETIF_F_TSO6
;
9513 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
9514 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
9515 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) ||
9516 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
9517 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
9518 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
)
9519 dev
->features
|= NETIF_F_TSO_ECN
;
9521 dev
->features
&= ~(NETIF_F_TSO6
| NETIF_F_TSO_ECN
);
9523 return ethtool_op_set_tso(dev
, value
);
9526 static int tg3_nway_reset(struct net_device
*dev
)
9528 struct tg3
*tp
= netdev_priv(dev
);
9531 if (!netif_running(dev
))
9534 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
9537 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9538 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
9540 r
= phy_start_aneg(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
9544 spin_lock_bh(&tp
->lock
);
9546 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
9547 if (!tg3_readphy(tp
, MII_BMCR
, &bmcr
) &&
9548 ((bmcr
& BMCR_ANENABLE
) ||
9549 (tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
))) {
9550 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANRESTART
|
9554 spin_unlock_bh(&tp
->lock
);
9560 static void tg3_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
9562 struct tg3
*tp
= netdev_priv(dev
);
9564 ering
->rx_max_pending
= TG3_RX_RING_SIZE
- 1;
9565 ering
->rx_mini_max_pending
= 0;
9566 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
)
9567 ering
->rx_jumbo_max_pending
= TG3_RX_JUMBO_RING_SIZE
- 1;
9569 ering
->rx_jumbo_max_pending
= 0;
9571 ering
->tx_max_pending
= TG3_TX_RING_SIZE
- 1;
9573 ering
->rx_pending
= tp
->rx_pending
;
9574 ering
->rx_mini_pending
= 0;
9575 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
)
9576 ering
->rx_jumbo_pending
= tp
->rx_jumbo_pending
;
9578 ering
->rx_jumbo_pending
= 0;
9580 ering
->tx_pending
= tp
->napi
[0].tx_pending
;
9583 static int tg3_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
9585 struct tg3
*tp
= netdev_priv(dev
);
9586 int i
, irq_sync
= 0, err
= 0;
9588 if ((ering
->rx_pending
> TG3_RX_RING_SIZE
- 1) ||
9589 (ering
->rx_jumbo_pending
> TG3_RX_JUMBO_RING_SIZE
- 1) ||
9590 (ering
->tx_pending
> TG3_TX_RING_SIZE
- 1) ||
9591 (ering
->tx_pending
<= MAX_SKB_FRAGS
) ||
9592 ((tp
->tg3_flags2
& TG3_FLG2_TSO_BUG
) &&
9593 (ering
->tx_pending
<= (MAX_SKB_FRAGS
* 3))))
9596 if (netif_running(dev
)) {
9602 tg3_full_lock(tp
, irq_sync
);
9604 tp
->rx_pending
= ering
->rx_pending
;
9606 if ((tp
->tg3_flags2
& TG3_FLG2_MAX_RXPEND_64
) &&
9607 tp
->rx_pending
> 63)
9608 tp
->rx_pending
= 63;
9609 tp
->rx_jumbo_pending
= ering
->rx_jumbo_pending
;
9611 for (i
= 0; i
< TG3_IRQ_MAX_VECS
; i
++)
9612 tp
->napi
[i
].tx_pending
= ering
->tx_pending
;
9614 if (netif_running(dev
)) {
9615 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9616 err
= tg3_restart_hw(tp
, 1);
9618 tg3_netif_start(tp
);
9621 tg3_full_unlock(tp
);
9623 if (irq_sync
&& !err
)
9629 static void tg3_get_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
9631 struct tg3
*tp
= netdev_priv(dev
);
9633 epause
->autoneg
= (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
) != 0;
9635 if (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
)
9636 epause
->rx_pause
= 1;
9638 epause
->rx_pause
= 0;
9640 if (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
)
9641 epause
->tx_pause
= 1;
9643 epause
->tx_pause
= 0;
9646 static int tg3_set_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
9648 struct tg3
*tp
= netdev_priv(dev
);
9651 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9652 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
9655 if (epause
->autoneg
) {
9657 struct phy_device
*phydev
;
9659 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
9661 if (epause
->rx_pause
) {
9662 if (epause
->tx_pause
)
9663 newadv
= ADVERTISED_Pause
;
9665 newadv
= ADVERTISED_Pause
|
9666 ADVERTISED_Asym_Pause
;
9667 } else if (epause
->tx_pause
) {
9668 newadv
= ADVERTISED_Asym_Pause
;
9672 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) {
9673 u32 oldadv
= phydev
->advertising
&
9675 ADVERTISED_Asym_Pause
);
9676 if (oldadv
!= newadv
) {
9677 phydev
->advertising
&=
9678 ~(ADVERTISED_Pause
|
9679 ADVERTISED_Asym_Pause
);
9680 phydev
->advertising
|= newadv
;
9681 err
= phy_start_aneg(phydev
);
9684 tp
->link_config
.advertising
&=
9685 ~(ADVERTISED_Pause
|
9686 ADVERTISED_Asym_Pause
);
9687 tp
->link_config
.advertising
|= newadv
;
9690 if (epause
->rx_pause
)
9691 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
9693 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_RX
;
9695 if (epause
->tx_pause
)
9696 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
9698 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_TX
;
9700 if (netif_running(dev
))
9701 tg3_setup_flow_control(tp
, 0, 0);
9706 if (netif_running(dev
)) {
9711 tg3_full_lock(tp
, irq_sync
);
9713 if (epause
->autoneg
)
9714 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
9716 tp
->tg3_flags
&= ~TG3_FLAG_PAUSE_AUTONEG
;
9717 if (epause
->rx_pause
)
9718 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
9720 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_RX
;
9721 if (epause
->tx_pause
)
9722 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
9724 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_TX
;
9726 if (netif_running(dev
)) {
9727 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9728 err
= tg3_restart_hw(tp
, 1);
9730 tg3_netif_start(tp
);
9733 tg3_full_unlock(tp
);
9739 static u32
tg3_get_rx_csum(struct net_device
*dev
)
9741 struct tg3
*tp
= netdev_priv(dev
);
9742 return (tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) != 0;
9745 static int tg3_set_rx_csum(struct net_device
*dev
, u32 data
)
9747 struct tg3
*tp
= netdev_priv(dev
);
9749 if (tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) {
9755 spin_lock_bh(&tp
->lock
);
9757 tp
->tg3_flags
|= TG3_FLAG_RX_CHECKSUMS
;
9759 tp
->tg3_flags
&= ~TG3_FLAG_RX_CHECKSUMS
;
9760 spin_unlock_bh(&tp
->lock
);
9765 static int tg3_set_tx_csum(struct net_device
*dev
, u32 data
)
9767 struct tg3
*tp
= netdev_priv(dev
);
9769 if (tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) {
9775 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
9776 ethtool_op_set_tx_ipv6_csum(dev
, data
);
9778 ethtool_op_set_tx_csum(dev
, data
);
9783 static int tg3_get_sset_count (struct net_device
*dev
, int sset
)
9787 return TG3_NUM_TEST
;
9789 return TG3_NUM_STATS
;
9795 static void tg3_get_strings (struct net_device
*dev
, u32 stringset
, u8
*buf
)
9797 switch (stringset
) {
9799 memcpy(buf
, ðtool_stats_keys
, sizeof(ethtool_stats_keys
));
9802 memcpy(buf
, ðtool_test_keys
, sizeof(ethtool_test_keys
));
9805 WARN_ON(1); /* we need a WARN() */
9810 static int tg3_phys_id(struct net_device
*dev
, u32 data
)
9812 struct tg3
*tp
= netdev_priv(dev
);
9815 if (!netif_running(tp
->dev
))
9819 data
= UINT_MAX
/ 2;
9821 for (i
= 0; i
< (data
* 2); i
++) {
9823 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
9824 LED_CTRL_1000MBPS_ON
|
9825 LED_CTRL_100MBPS_ON
|
9826 LED_CTRL_10MBPS_ON
|
9827 LED_CTRL_TRAFFIC_OVERRIDE
|
9828 LED_CTRL_TRAFFIC_BLINK
|
9829 LED_CTRL_TRAFFIC_LED
);
9832 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
9833 LED_CTRL_TRAFFIC_OVERRIDE
);
9835 if (msleep_interruptible(500))
9838 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
9842 static void tg3_get_ethtool_stats (struct net_device
*dev
,
9843 struct ethtool_stats
*estats
, u64
*tmp_stats
)
9845 struct tg3
*tp
= netdev_priv(dev
);
9846 memcpy(tmp_stats
, tg3_get_estats(tp
), sizeof(tp
->estats
));
9849 #define NVRAM_TEST_SIZE 0x100
9850 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9851 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9852 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
9853 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9854 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9856 static int tg3_test_nvram(struct tg3
*tp
)
9860 int i
, j
, k
, err
= 0, size
;
9862 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
)
9865 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
9868 if (magic
== TG3_EEPROM_MAGIC
)
9869 size
= NVRAM_TEST_SIZE
;
9870 else if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
) {
9871 if ((magic
& TG3_EEPROM_SB_FORMAT_MASK
) ==
9872 TG3_EEPROM_SB_FORMAT_1
) {
9873 switch (magic
& TG3_EEPROM_SB_REVISION_MASK
) {
9874 case TG3_EEPROM_SB_REVISION_0
:
9875 size
= NVRAM_SELFBOOT_FORMAT1_0_SIZE
;
9877 case TG3_EEPROM_SB_REVISION_2
:
9878 size
= NVRAM_SELFBOOT_FORMAT1_2_SIZE
;
9880 case TG3_EEPROM_SB_REVISION_3
:
9881 size
= NVRAM_SELFBOOT_FORMAT1_3_SIZE
;
9888 } else if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
9889 size
= NVRAM_SELFBOOT_HW_SIZE
;
9893 buf
= kmalloc(size
, GFP_KERNEL
);
9898 for (i
= 0, j
= 0; i
< size
; i
+= 4, j
++) {
9899 err
= tg3_nvram_read_be32(tp
, i
, &buf
[j
]);
9906 /* Selfboot format */
9907 magic
= be32_to_cpu(buf
[0]);
9908 if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) ==
9909 TG3_EEPROM_MAGIC_FW
) {
9910 u8
*buf8
= (u8
*) buf
, csum8
= 0;
9912 if ((magic
& TG3_EEPROM_SB_REVISION_MASK
) ==
9913 TG3_EEPROM_SB_REVISION_2
) {
9914 /* For rev 2, the csum doesn't include the MBA. */
9915 for (i
= 0; i
< TG3_EEPROM_SB_F1R2_MBA_OFF
; i
++)
9917 for (i
= TG3_EEPROM_SB_F1R2_MBA_OFF
+ 4; i
< size
; i
++)
9920 for (i
= 0; i
< size
; i
++)
9933 if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) ==
9934 TG3_EEPROM_MAGIC_HW
) {
9935 u8 data
[NVRAM_SELFBOOT_DATA_SIZE
];
9936 u8 parity
[NVRAM_SELFBOOT_DATA_SIZE
];
9937 u8
*buf8
= (u8
*) buf
;
9939 /* Separate the parity bits and the data bytes. */
9940 for (i
= 0, j
= 0, k
= 0; i
< NVRAM_SELFBOOT_HW_SIZE
; i
++) {
9941 if ((i
== 0) || (i
== 8)) {
9945 for (l
= 0, msk
= 0x80; l
< 7; l
++, msk
>>= 1)
9946 parity
[k
++] = buf8
[i
] & msk
;
9953 for (l
= 0, msk
= 0x20; l
< 6; l
++, msk
>>= 1)
9954 parity
[k
++] = buf8
[i
] & msk
;
9957 for (l
= 0, msk
= 0x80; l
< 8; l
++, msk
>>= 1)
9958 parity
[k
++] = buf8
[i
] & msk
;
9961 data
[j
++] = buf8
[i
];
9965 for (i
= 0; i
< NVRAM_SELFBOOT_DATA_SIZE
; i
++) {
9966 u8 hw8
= hweight8(data
[i
]);
9968 if ((hw8
& 0x1) && parity
[i
])
9970 else if (!(hw8
& 0x1) && !parity
[i
])
9977 /* Bootstrap checksum at offset 0x10 */
9978 csum
= calc_crc((unsigned char *) buf
, 0x10);
9979 if (csum
!= be32_to_cpu(buf
[0x10/4]))
9982 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9983 csum
= calc_crc((unsigned char *) &buf
[0x74/4], 0x88);
9984 if (csum
!= be32_to_cpu(buf
[0xfc/4]))
9994 #define TG3_SERDES_TIMEOUT_SEC 2
9995 #define TG3_COPPER_TIMEOUT_SEC 6
9997 static int tg3_test_link(struct tg3
*tp
)
10001 if (!netif_running(tp
->dev
))
10004 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)
10005 max
= TG3_SERDES_TIMEOUT_SEC
;
10007 max
= TG3_COPPER_TIMEOUT_SEC
;
10009 for (i
= 0; i
< max
; i
++) {
10010 if (netif_carrier_ok(tp
->dev
))
10013 if (msleep_interruptible(1000))
10020 /* Only test the commonly used registers */
10021 static int tg3_test_registers(struct tg3
*tp
)
10023 int i
, is_5705
, is_5750
;
10024 u32 offset
, read_mask
, write_mask
, val
, save_val
, read_val
;
10028 #define TG3_FL_5705 0x1
10029 #define TG3_FL_NOT_5705 0x2
10030 #define TG3_FL_NOT_5788 0x4
10031 #define TG3_FL_NOT_5750 0x8
10035 /* MAC Control Registers */
10036 { MAC_MODE
, TG3_FL_NOT_5705
,
10037 0x00000000, 0x00ef6f8c },
10038 { MAC_MODE
, TG3_FL_5705
,
10039 0x00000000, 0x01ef6b8c },
10040 { MAC_STATUS
, TG3_FL_NOT_5705
,
10041 0x03800107, 0x00000000 },
10042 { MAC_STATUS
, TG3_FL_5705
,
10043 0x03800100, 0x00000000 },
10044 { MAC_ADDR_0_HIGH
, 0x0000,
10045 0x00000000, 0x0000ffff },
10046 { MAC_ADDR_0_LOW
, 0x0000,
10047 0x00000000, 0xffffffff },
10048 { MAC_RX_MTU_SIZE
, 0x0000,
10049 0x00000000, 0x0000ffff },
10050 { MAC_TX_MODE
, 0x0000,
10051 0x00000000, 0x00000070 },
10052 { MAC_TX_LENGTHS
, 0x0000,
10053 0x00000000, 0x00003fff },
10054 { MAC_RX_MODE
, TG3_FL_NOT_5705
,
10055 0x00000000, 0x000007fc },
10056 { MAC_RX_MODE
, TG3_FL_5705
,
10057 0x00000000, 0x000007dc },
10058 { MAC_HASH_REG_0
, 0x0000,
10059 0x00000000, 0xffffffff },
10060 { MAC_HASH_REG_1
, 0x0000,
10061 0x00000000, 0xffffffff },
10062 { MAC_HASH_REG_2
, 0x0000,
10063 0x00000000, 0xffffffff },
10064 { MAC_HASH_REG_3
, 0x0000,
10065 0x00000000, 0xffffffff },
10067 /* Receive Data and Receive BD Initiator Control Registers. */
10068 { RCVDBDI_JUMBO_BD
+0, TG3_FL_NOT_5705
,
10069 0x00000000, 0xffffffff },
10070 { RCVDBDI_JUMBO_BD
+4, TG3_FL_NOT_5705
,
10071 0x00000000, 0xffffffff },
10072 { RCVDBDI_JUMBO_BD
+8, TG3_FL_NOT_5705
,
10073 0x00000000, 0x00000003 },
10074 { RCVDBDI_JUMBO_BD
+0xc, TG3_FL_NOT_5705
,
10075 0x00000000, 0xffffffff },
10076 { RCVDBDI_STD_BD
+0, 0x0000,
10077 0x00000000, 0xffffffff },
10078 { RCVDBDI_STD_BD
+4, 0x0000,
10079 0x00000000, 0xffffffff },
10080 { RCVDBDI_STD_BD
+8, 0x0000,
10081 0x00000000, 0xffff0002 },
10082 { RCVDBDI_STD_BD
+0xc, 0x0000,
10083 0x00000000, 0xffffffff },
10085 /* Receive BD Initiator Control Registers. */
10086 { RCVBDI_STD_THRESH
, TG3_FL_NOT_5705
,
10087 0x00000000, 0xffffffff },
10088 { RCVBDI_STD_THRESH
, TG3_FL_5705
,
10089 0x00000000, 0x000003ff },
10090 { RCVBDI_JUMBO_THRESH
, TG3_FL_NOT_5705
,
10091 0x00000000, 0xffffffff },
10093 /* Host Coalescing Control Registers. */
10094 { HOSTCC_MODE
, TG3_FL_NOT_5705
,
10095 0x00000000, 0x00000004 },
10096 { HOSTCC_MODE
, TG3_FL_5705
,
10097 0x00000000, 0x000000f6 },
10098 { HOSTCC_RXCOL_TICKS
, TG3_FL_NOT_5705
,
10099 0x00000000, 0xffffffff },
10100 { HOSTCC_RXCOL_TICKS
, TG3_FL_5705
,
10101 0x00000000, 0x000003ff },
10102 { HOSTCC_TXCOL_TICKS
, TG3_FL_NOT_5705
,
10103 0x00000000, 0xffffffff },
10104 { HOSTCC_TXCOL_TICKS
, TG3_FL_5705
,
10105 0x00000000, 0x000003ff },
10106 { HOSTCC_RXMAX_FRAMES
, TG3_FL_NOT_5705
,
10107 0x00000000, 0xffffffff },
10108 { HOSTCC_RXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10109 0x00000000, 0x000000ff },
10110 { HOSTCC_TXMAX_FRAMES
, TG3_FL_NOT_5705
,
10111 0x00000000, 0xffffffff },
10112 { HOSTCC_TXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10113 0x00000000, 0x000000ff },
10114 { HOSTCC_RXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
10115 0x00000000, 0xffffffff },
10116 { HOSTCC_TXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
10117 0x00000000, 0xffffffff },
10118 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
10119 0x00000000, 0xffffffff },
10120 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10121 0x00000000, 0x000000ff },
10122 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
10123 0x00000000, 0xffffffff },
10124 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10125 0x00000000, 0x000000ff },
10126 { HOSTCC_STAT_COAL_TICKS
, TG3_FL_NOT_5705
,
10127 0x00000000, 0xffffffff },
10128 { HOSTCC_STATS_BLK_HOST_ADDR
, TG3_FL_NOT_5705
,
10129 0x00000000, 0xffffffff },
10130 { HOSTCC_STATS_BLK_HOST_ADDR
+4, TG3_FL_NOT_5705
,
10131 0x00000000, 0xffffffff },
10132 { HOSTCC_STATUS_BLK_HOST_ADDR
, 0x0000,
10133 0x00000000, 0xffffffff },
10134 { HOSTCC_STATUS_BLK_HOST_ADDR
+4, 0x0000,
10135 0x00000000, 0xffffffff },
10136 { HOSTCC_STATS_BLK_NIC_ADDR
, 0x0000,
10137 0xffffffff, 0x00000000 },
10138 { HOSTCC_STATUS_BLK_NIC_ADDR
, 0x0000,
10139 0xffffffff, 0x00000000 },
10141 /* Buffer Manager Control Registers. */
10142 { BUFMGR_MB_POOL_ADDR
, TG3_FL_NOT_5750
,
10143 0x00000000, 0x007fff80 },
10144 { BUFMGR_MB_POOL_SIZE
, TG3_FL_NOT_5750
,
10145 0x00000000, 0x007fffff },
10146 { BUFMGR_MB_RDMA_LOW_WATER
, 0x0000,
10147 0x00000000, 0x0000003f },
10148 { BUFMGR_MB_MACRX_LOW_WATER
, 0x0000,
10149 0x00000000, 0x000001ff },
10150 { BUFMGR_MB_HIGH_WATER
, 0x0000,
10151 0x00000000, 0x000001ff },
10152 { BUFMGR_DMA_DESC_POOL_ADDR
, TG3_FL_NOT_5705
,
10153 0xffffffff, 0x00000000 },
10154 { BUFMGR_DMA_DESC_POOL_SIZE
, TG3_FL_NOT_5705
,
10155 0xffffffff, 0x00000000 },
10157 /* Mailbox Registers */
10158 { GRCMBOX_RCVSTD_PROD_IDX
+4, 0x0000,
10159 0x00000000, 0x000001ff },
10160 { GRCMBOX_RCVJUMBO_PROD_IDX
+4, TG3_FL_NOT_5705
,
10161 0x00000000, 0x000001ff },
10162 { GRCMBOX_RCVRET_CON_IDX_0
+4, 0x0000,
10163 0x00000000, 0x000007ff },
10164 { GRCMBOX_SNDHOST_PROD_IDX_0
+4, 0x0000,
10165 0x00000000, 0x000001ff },
10167 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10170 is_5705
= is_5750
= 0;
10171 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
10173 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
10177 for (i
= 0; reg_tbl
[i
].offset
!= 0xffff; i
++) {
10178 if (is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5705
))
10181 if (!is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_5705
))
10184 if ((tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
10185 (reg_tbl
[i
].flags
& TG3_FL_NOT_5788
))
10188 if (is_5750
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5750
))
10191 offset
= (u32
) reg_tbl
[i
].offset
;
10192 read_mask
= reg_tbl
[i
].read_mask
;
10193 write_mask
= reg_tbl
[i
].write_mask
;
10195 /* Save the original register content */
10196 save_val
= tr32(offset
);
10198 /* Determine the read-only value. */
10199 read_val
= save_val
& read_mask
;
10201 /* Write zero to the register, then make sure the read-only bits
10202 * are not changed and the read/write bits are all zeros.
10206 val
= tr32(offset
);
10208 /* Test the read-only and read/write bits. */
10209 if (((val
& read_mask
) != read_val
) || (val
& write_mask
))
10212 /* Write ones to all the bits defined by RdMask and WrMask, then
10213 * make sure the read-only bits are not changed and the
10214 * read/write bits are all ones.
10216 tw32(offset
, read_mask
| write_mask
);
10218 val
= tr32(offset
);
10220 /* Test the read-only bits. */
10221 if ((val
& read_mask
) != read_val
)
10224 /* Test the read/write bits. */
10225 if ((val
& write_mask
) != write_mask
)
10228 tw32(offset
, save_val
);
10234 if (netif_msg_hw(tp
))
10235 printk(KERN_ERR PFX
"Register test failed at offset %x\n",
10237 tw32(offset
, save_val
);
10241 static int tg3_do_mem_test(struct tg3
*tp
, u32 offset
, u32 len
)
10243 static const u32 test_pattern
[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10247 for (i
= 0; i
< ARRAY_SIZE(test_pattern
); i
++) {
10248 for (j
= 0; j
< len
; j
+= 4) {
10251 tg3_write_mem(tp
, offset
+ j
, test_pattern
[i
]);
10252 tg3_read_mem(tp
, offset
+ j
, &val
);
10253 if (val
!= test_pattern
[i
])
10260 static int tg3_test_memory(struct tg3
*tp
)
10262 static struct mem_entry
{
10265 } mem_tbl_570x
[] = {
10266 { 0x00000000, 0x00b50},
10267 { 0x00002000, 0x1c000},
10268 { 0xffffffff, 0x00000}
10269 }, mem_tbl_5705
[] = {
10270 { 0x00000100, 0x0000c},
10271 { 0x00000200, 0x00008},
10272 { 0x00004000, 0x00800},
10273 { 0x00006000, 0x01000},
10274 { 0x00008000, 0x02000},
10275 { 0x00010000, 0x0e000},
10276 { 0xffffffff, 0x00000}
10277 }, mem_tbl_5755
[] = {
10278 { 0x00000200, 0x00008},
10279 { 0x00004000, 0x00800},
10280 { 0x00006000, 0x00800},
10281 { 0x00008000, 0x02000},
10282 { 0x00010000, 0x0c000},
10283 { 0xffffffff, 0x00000}
10284 }, mem_tbl_5906
[] = {
10285 { 0x00000200, 0x00008},
10286 { 0x00004000, 0x00400},
10287 { 0x00006000, 0x00400},
10288 { 0x00008000, 0x01000},
10289 { 0x00010000, 0x01000},
10290 { 0xffffffff, 0x00000}
10292 struct mem_entry
*mem_tbl
;
10296 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
10297 mem_tbl
= mem_tbl_5755
;
10298 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
10299 mem_tbl
= mem_tbl_5906
;
10300 else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
10301 mem_tbl
= mem_tbl_5705
;
10303 mem_tbl
= mem_tbl_570x
;
10305 for (i
= 0; mem_tbl
[i
].offset
!= 0xffffffff; i
++) {
10306 if ((err
= tg3_do_mem_test(tp
, mem_tbl
[i
].offset
,
10307 mem_tbl
[i
].len
)) != 0)
10314 #define TG3_MAC_LOOPBACK 0
10315 #define TG3_PHY_LOOPBACK 1
10317 static int tg3_run_loopback(struct tg3
*tp
, int loopback_mode
)
10319 u32 mac_mode
, rx_start_idx
, rx_idx
, tx_idx
, opaque_key
;
10320 u32 desc_idx
, coal_now
;
10321 struct sk_buff
*skb
, *rx_skb
;
10324 int num_pkts
, tx_len
, rx_len
, i
, err
;
10325 struct tg3_rx_buffer_desc
*desc
;
10326 struct tg3_napi
*tnapi
, *rnapi
;
10327 struct tg3_rx_prodring_set
*tpr
= &tp
->prodring
[0];
10329 if (tp
->irq_cnt
> 1) {
10330 tnapi
= &tp
->napi
[1];
10331 rnapi
= &tp
->napi
[1];
10333 tnapi
= &tp
->napi
[0];
10334 rnapi
= &tp
->napi
[0];
10336 coal_now
= tnapi
->coal_now
| rnapi
->coal_now
;
10338 if (loopback_mode
== TG3_MAC_LOOPBACK
) {
10339 /* HW errata - mac loopback fails in some cases on 5780.
10340 * Normal traffic and PHY loopback are not affected by
10343 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
)
10346 mac_mode
= (tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
) |
10347 MAC_MODE_PORT_INT_LPBACK
;
10348 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
10349 mac_mode
|= MAC_MODE_LINK_POLARITY
;
10350 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
10351 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
10353 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
10354 tw32(MAC_MODE
, mac_mode
);
10355 } else if (loopback_mode
== TG3_PHY_LOOPBACK
) {
10358 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
10359 tg3_phy_fet_toggle_apd(tp
, false);
10360 val
= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED100
;
10362 val
= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED1000
;
10364 tg3_phy_toggle_automdix(tp
, 0);
10366 tg3_writephy(tp
, MII_BMCR
, val
);
10369 mac_mode
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
10370 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
10371 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
10372 tg3_writephy(tp
, MII_TG3_FET_PTEST
, 0x1800);
10373 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
10375 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
10377 /* reset to prevent losing 1st rx packet intermittently */
10378 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
10379 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
10381 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
10383 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
10384 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
)
10385 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
10386 else if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5411
)
10387 mac_mode
|= MAC_MODE_LINK_POLARITY
;
10388 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
10389 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
10391 tw32(MAC_MODE
, mac_mode
);
10399 skb
= netdev_alloc_skb(tp
->dev
, tx_len
);
10403 tx_data
= skb_put(skb
, tx_len
);
10404 memcpy(tx_data
, tp
->dev
->dev_addr
, 6);
10405 memset(tx_data
+ 6, 0x0, 8);
10407 tw32(MAC_RX_MTU_SIZE
, tx_len
+ 4);
10409 for (i
= 14; i
< tx_len
; i
++)
10410 tx_data
[i
] = (u8
) (i
& 0xff);
10412 if (skb_dma_map(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
)) {
10413 dev_kfree_skb(skb
);
10417 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
10422 rx_start_idx
= rnapi
->hw_status
->idx
[0].rx_producer
;
10426 tg3_set_txd(tnapi
, tnapi
->tx_prod
,
10427 skb_shinfo(skb
)->dma_head
, tx_len
, 0, 1);
10432 tw32_tx_mbox(tnapi
->prodmbox
, tnapi
->tx_prod
);
10433 tr32_mailbox(tnapi
->prodmbox
);
10437 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10438 for (i
= 0; i
< 35; i
++) {
10439 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
10444 tx_idx
= tnapi
->hw_status
->idx
[0].tx_consumer
;
10445 rx_idx
= rnapi
->hw_status
->idx
[0].rx_producer
;
10446 if ((tx_idx
== tnapi
->tx_prod
) &&
10447 (rx_idx
== (rx_start_idx
+ num_pkts
)))
10451 skb_dma_unmap(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
);
10452 dev_kfree_skb(skb
);
10454 if (tx_idx
!= tnapi
->tx_prod
)
10457 if (rx_idx
!= rx_start_idx
+ num_pkts
)
10460 desc
= &rnapi
->rx_rcb
[rx_start_idx
];
10461 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
10462 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
10463 if (opaque_key
!= RXD_OPAQUE_RING_STD
)
10466 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
10467 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
))
10470 rx_len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) - 4;
10471 if (rx_len
!= tx_len
)
10474 rx_skb
= tpr
->rx_std_buffers
[desc_idx
].skb
;
10476 map
= pci_unmap_addr(&tpr
->rx_std_buffers
[desc_idx
], mapping
);
10477 pci_dma_sync_single_for_cpu(tp
->pdev
, map
, rx_len
, PCI_DMA_FROMDEVICE
);
10479 for (i
= 14; i
< tx_len
; i
++) {
10480 if (*(rx_skb
->data
+ i
) != (u8
) (i
& 0xff))
10485 /* tg3_free_rings will unmap and free the rx_skb */
10490 #define TG3_MAC_LOOPBACK_FAILED 1
10491 #define TG3_PHY_LOOPBACK_FAILED 2
10492 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10493 TG3_PHY_LOOPBACK_FAILED)
10495 static int tg3_test_loopback(struct tg3
*tp
)
10500 if (!netif_running(tp
->dev
))
10501 return TG3_LOOPBACK_FAILED
;
10503 err
= tg3_reset_hw(tp
, 1);
10505 return TG3_LOOPBACK_FAILED
;
10507 /* Turn off gphy autopowerdown. */
10508 if (tp
->tg3_flags3
& TG3_FLG3_PHY_ENABLE_APD
)
10509 tg3_phy_toggle_apd(tp
, false);
10511 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) {
10515 tw32(TG3_CPMU_MUTEX_REQ
, CPMU_MUTEX_REQ_DRIVER
);
10517 /* Wait for up to 40 microseconds to acquire lock. */
10518 for (i
= 0; i
< 4; i
++) {
10519 status
= tr32(TG3_CPMU_MUTEX_GNT
);
10520 if (status
== CPMU_MUTEX_GNT_DRIVER
)
10525 if (status
!= CPMU_MUTEX_GNT_DRIVER
)
10526 return TG3_LOOPBACK_FAILED
;
10528 /* Turn off link-based power management. */
10529 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
10530 tw32(TG3_CPMU_CTRL
,
10531 cpmuctrl
& ~(CPMU_CTRL_LINK_SPEED_MODE
|
10532 CPMU_CTRL_LINK_AWARE_MODE
));
10535 if (tg3_run_loopback(tp
, TG3_MAC_LOOPBACK
))
10536 err
|= TG3_MAC_LOOPBACK_FAILED
;
10538 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) {
10539 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
10541 /* Release the mutex */
10542 tw32(TG3_CPMU_MUTEX_GNT
, CPMU_MUTEX_GNT_DRIVER
);
10545 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
10546 !(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)) {
10547 if (tg3_run_loopback(tp
, TG3_PHY_LOOPBACK
))
10548 err
|= TG3_PHY_LOOPBACK_FAILED
;
10551 /* Re-enable gphy autopowerdown. */
10552 if (tp
->tg3_flags3
& TG3_FLG3_PHY_ENABLE_APD
)
10553 tg3_phy_toggle_apd(tp
, true);
10558 static void tg3_self_test(struct net_device
*dev
, struct ethtool_test
*etest
,
10561 struct tg3
*tp
= netdev_priv(dev
);
10563 if (tp
->link_config
.phy_is_low_power
)
10564 tg3_set_power_state(tp
, PCI_D0
);
10566 memset(data
, 0, sizeof(u64
) * TG3_NUM_TEST
);
10568 if (tg3_test_nvram(tp
) != 0) {
10569 etest
->flags
|= ETH_TEST_FL_FAILED
;
10572 if (tg3_test_link(tp
) != 0) {
10573 etest
->flags
|= ETH_TEST_FL_FAILED
;
10576 if (etest
->flags
& ETH_TEST_FL_OFFLINE
) {
10577 int err
, err2
= 0, irq_sync
= 0;
10579 if (netif_running(dev
)) {
10581 tg3_netif_stop(tp
);
10585 tg3_full_lock(tp
, irq_sync
);
10587 tg3_halt(tp
, RESET_KIND_SUSPEND
, 1);
10588 err
= tg3_nvram_lock(tp
);
10589 tg3_halt_cpu(tp
, RX_CPU_BASE
);
10590 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
10591 tg3_halt_cpu(tp
, TX_CPU_BASE
);
10593 tg3_nvram_unlock(tp
);
10595 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)
10598 if (tg3_test_registers(tp
) != 0) {
10599 etest
->flags
|= ETH_TEST_FL_FAILED
;
10602 if (tg3_test_memory(tp
) != 0) {
10603 etest
->flags
|= ETH_TEST_FL_FAILED
;
10606 if ((data
[4] = tg3_test_loopback(tp
)) != 0)
10607 etest
->flags
|= ETH_TEST_FL_FAILED
;
10609 tg3_full_unlock(tp
);
10611 if (tg3_test_interrupt(tp
) != 0) {
10612 etest
->flags
|= ETH_TEST_FL_FAILED
;
10616 tg3_full_lock(tp
, 0);
10618 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
10619 if (netif_running(dev
)) {
10620 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
10621 err2
= tg3_restart_hw(tp
, 1);
10623 tg3_netif_start(tp
);
10626 tg3_full_unlock(tp
);
10628 if (irq_sync
&& !err2
)
10631 if (tp
->link_config
.phy_is_low_power
)
10632 tg3_set_power_state(tp
, PCI_D3hot
);
10636 static int tg3_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
10638 struct mii_ioctl_data
*data
= if_mii(ifr
);
10639 struct tg3
*tp
= netdev_priv(dev
);
10642 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
10643 struct phy_device
*phydev
;
10644 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
10646 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
10647 return phy_mii_ioctl(phydev
, data
, cmd
);
10652 data
->phy_id
= tp
->phy_addr
;
10655 case SIOCGMIIREG
: {
10658 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
10659 break; /* We have no PHY */
10661 if (tp
->link_config
.phy_is_low_power
)
10664 spin_lock_bh(&tp
->lock
);
10665 err
= tg3_readphy(tp
, data
->reg_num
& 0x1f, &mii_regval
);
10666 spin_unlock_bh(&tp
->lock
);
10668 data
->val_out
= mii_regval
;
10674 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
10675 break; /* We have no PHY */
10677 if (tp
->link_config
.phy_is_low_power
)
10680 spin_lock_bh(&tp
->lock
);
10681 err
= tg3_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
10682 spin_unlock_bh(&tp
->lock
);
10690 return -EOPNOTSUPP
;
10693 #if TG3_VLAN_TAG_USED
10694 static void tg3_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
10696 struct tg3
*tp
= netdev_priv(dev
);
10698 if (!netif_running(dev
)) {
10703 tg3_netif_stop(tp
);
10705 tg3_full_lock(tp
, 0);
10709 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10710 __tg3_set_rx_mode(dev
);
10712 tg3_netif_start(tp
);
10714 tg3_full_unlock(tp
);
10718 static int tg3_get_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
10720 struct tg3
*tp
= netdev_priv(dev
);
10722 memcpy(ec
, &tp
->coal
, sizeof(*ec
));
10726 static int tg3_set_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
10728 struct tg3
*tp
= netdev_priv(dev
);
10729 u32 max_rxcoal_tick_int
= 0, max_txcoal_tick_int
= 0;
10730 u32 max_stat_coal_ticks
= 0, min_stat_coal_ticks
= 0;
10732 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
10733 max_rxcoal_tick_int
= MAX_RXCOAL_TICK_INT
;
10734 max_txcoal_tick_int
= MAX_TXCOAL_TICK_INT
;
10735 max_stat_coal_ticks
= MAX_STAT_COAL_TICKS
;
10736 min_stat_coal_ticks
= MIN_STAT_COAL_TICKS
;
10739 if ((ec
->rx_coalesce_usecs
> MAX_RXCOL_TICKS
) ||
10740 (ec
->tx_coalesce_usecs
> MAX_TXCOL_TICKS
) ||
10741 (ec
->rx_max_coalesced_frames
> MAX_RXMAX_FRAMES
) ||
10742 (ec
->tx_max_coalesced_frames
> MAX_TXMAX_FRAMES
) ||
10743 (ec
->rx_coalesce_usecs_irq
> max_rxcoal_tick_int
) ||
10744 (ec
->tx_coalesce_usecs_irq
> max_txcoal_tick_int
) ||
10745 (ec
->rx_max_coalesced_frames_irq
> MAX_RXCOAL_MAXF_INT
) ||
10746 (ec
->tx_max_coalesced_frames_irq
> MAX_TXCOAL_MAXF_INT
) ||
10747 (ec
->stats_block_coalesce_usecs
> max_stat_coal_ticks
) ||
10748 (ec
->stats_block_coalesce_usecs
< min_stat_coal_ticks
))
10751 /* No rx interrupts will be generated if both are zero */
10752 if ((ec
->rx_coalesce_usecs
== 0) &&
10753 (ec
->rx_max_coalesced_frames
== 0))
10756 /* No tx interrupts will be generated if both are zero */
10757 if ((ec
->tx_coalesce_usecs
== 0) &&
10758 (ec
->tx_max_coalesced_frames
== 0))
10761 /* Only copy relevant parameters, ignore all others. */
10762 tp
->coal
.rx_coalesce_usecs
= ec
->rx_coalesce_usecs
;
10763 tp
->coal
.tx_coalesce_usecs
= ec
->tx_coalesce_usecs
;
10764 tp
->coal
.rx_max_coalesced_frames
= ec
->rx_max_coalesced_frames
;
10765 tp
->coal
.tx_max_coalesced_frames
= ec
->tx_max_coalesced_frames
;
10766 tp
->coal
.rx_coalesce_usecs_irq
= ec
->rx_coalesce_usecs_irq
;
10767 tp
->coal
.tx_coalesce_usecs_irq
= ec
->tx_coalesce_usecs_irq
;
10768 tp
->coal
.rx_max_coalesced_frames_irq
= ec
->rx_max_coalesced_frames_irq
;
10769 tp
->coal
.tx_max_coalesced_frames_irq
= ec
->tx_max_coalesced_frames_irq
;
10770 tp
->coal
.stats_block_coalesce_usecs
= ec
->stats_block_coalesce_usecs
;
10772 if (netif_running(dev
)) {
10773 tg3_full_lock(tp
, 0);
10774 __tg3_set_coalesce(tp
, &tp
->coal
);
10775 tg3_full_unlock(tp
);
10780 static const struct ethtool_ops tg3_ethtool_ops
= {
10781 .get_settings
= tg3_get_settings
,
10782 .set_settings
= tg3_set_settings
,
10783 .get_drvinfo
= tg3_get_drvinfo
,
10784 .get_regs_len
= tg3_get_regs_len
,
10785 .get_regs
= tg3_get_regs
,
10786 .get_wol
= tg3_get_wol
,
10787 .set_wol
= tg3_set_wol
,
10788 .get_msglevel
= tg3_get_msglevel
,
10789 .set_msglevel
= tg3_set_msglevel
,
10790 .nway_reset
= tg3_nway_reset
,
10791 .get_link
= ethtool_op_get_link
,
10792 .get_eeprom_len
= tg3_get_eeprom_len
,
10793 .get_eeprom
= tg3_get_eeprom
,
10794 .set_eeprom
= tg3_set_eeprom
,
10795 .get_ringparam
= tg3_get_ringparam
,
10796 .set_ringparam
= tg3_set_ringparam
,
10797 .get_pauseparam
= tg3_get_pauseparam
,
10798 .set_pauseparam
= tg3_set_pauseparam
,
10799 .get_rx_csum
= tg3_get_rx_csum
,
10800 .set_rx_csum
= tg3_set_rx_csum
,
10801 .set_tx_csum
= tg3_set_tx_csum
,
10802 .set_sg
= ethtool_op_set_sg
,
10803 .set_tso
= tg3_set_tso
,
10804 .self_test
= tg3_self_test
,
10805 .get_strings
= tg3_get_strings
,
10806 .phys_id
= tg3_phys_id
,
10807 .get_ethtool_stats
= tg3_get_ethtool_stats
,
10808 .get_coalesce
= tg3_get_coalesce
,
10809 .set_coalesce
= tg3_set_coalesce
,
10810 .get_sset_count
= tg3_get_sset_count
,
10813 static void __devinit
tg3_get_eeprom_size(struct tg3
*tp
)
10815 u32 cursize
, val
, magic
;
10817 tp
->nvram_size
= EEPROM_CHIP_SIZE
;
10819 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
10822 if ((magic
!= TG3_EEPROM_MAGIC
) &&
10823 ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) != TG3_EEPROM_MAGIC_FW
) &&
10824 ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) != TG3_EEPROM_MAGIC_HW
))
10828 * Size the chip by reading offsets at increasing powers of two.
10829 * When we encounter our validation signature, we know the addressing
10830 * has wrapped around, and thus have our chip size.
10834 while (cursize
< tp
->nvram_size
) {
10835 if (tg3_nvram_read(tp
, cursize
, &val
) != 0)
10844 tp
->nvram_size
= cursize
;
10847 static void __devinit
tg3_get_nvram_size(struct tg3
*tp
)
10851 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
10852 tg3_nvram_read(tp
, 0, &val
) != 0)
10855 /* Selfboot format */
10856 if (val
!= TG3_EEPROM_MAGIC
) {
10857 tg3_get_eeprom_size(tp
);
10861 if (tg3_nvram_read(tp
, 0xf0, &val
) == 0) {
10863 /* This is confusing. We want to operate on the
10864 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10865 * call will read from NVRAM and byteswap the data
10866 * according to the byteswapping settings for all
10867 * other register accesses. This ensures the data we
10868 * want will always reside in the lower 16-bits.
10869 * However, the data in NVRAM is in LE format, which
10870 * means the data from the NVRAM read will always be
10871 * opposite the endianness of the CPU. The 16-bit
10872 * byteswap then brings the data to CPU endianness.
10874 tp
->nvram_size
= swab16((u16
)(val
& 0x0000ffff)) * 1024;
10878 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
10881 static void __devinit
tg3_get_nvram_info(struct tg3
*tp
)
10885 nvcfg1
= tr32(NVRAM_CFG1
);
10886 if (nvcfg1
& NVRAM_CFG1_FLASHIF_ENAB
) {
10887 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10889 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
10890 tw32(NVRAM_CFG1
, nvcfg1
);
10893 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) ||
10894 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
10895 switch (nvcfg1
& NVRAM_CFG1_VENDOR_MASK
) {
10896 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED
:
10897 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10898 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
10899 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10901 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED
:
10902 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10903 tp
->nvram_pagesize
= ATMEL_AT25F512_PAGE_SIZE
;
10905 case FLASH_VENDOR_ATMEL_EEPROM
:
10906 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10907 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
10908 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10910 case FLASH_VENDOR_ST
:
10911 tp
->nvram_jedecnum
= JEDEC_ST
;
10912 tp
->nvram_pagesize
= ST_M45PEX0_PAGE_SIZE
;
10913 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10915 case FLASH_VENDOR_SAIFUN
:
10916 tp
->nvram_jedecnum
= JEDEC_SAIFUN
;
10917 tp
->nvram_pagesize
= SAIFUN_SA25F0XX_PAGE_SIZE
;
10919 case FLASH_VENDOR_SST_SMALL
:
10920 case FLASH_VENDOR_SST_LARGE
:
10921 tp
->nvram_jedecnum
= JEDEC_SST
;
10922 tp
->nvram_pagesize
= SST_25VF0X0_PAGE_SIZE
;
10926 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10927 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
10928 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10932 static void __devinit
tg3_nvram_get_pagesize(struct tg3
*tp
, u32 nvmcfg1
)
10934 switch (nvmcfg1
& NVRAM_CFG1_5752PAGE_SIZE_MASK
) {
10935 case FLASH_5752PAGE_SIZE_256
:
10936 tp
->nvram_pagesize
= 256;
10938 case FLASH_5752PAGE_SIZE_512
:
10939 tp
->nvram_pagesize
= 512;
10941 case FLASH_5752PAGE_SIZE_1K
:
10942 tp
->nvram_pagesize
= 1024;
10944 case FLASH_5752PAGE_SIZE_2K
:
10945 tp
->nvram_pagesize
= 2048;
10947 case FLASH_5752PAGE_SIZE_4K
:
10948 tp
->nvram_pagesize
= 4096;
10950 case FLASH_5752PAGE_SIZE_264
:
10951 tp
->nvram_pagesize
= 264;
10953 case FLASH_5752PAGE_SIZE_528
:
10954 tp
->nvram_pagesize
= 528;
10959 static void __devinit
tg3_get_5752_nvram_info(struct tg3
*tp
)
10963 nvcfg1
= tr32(NVRAM_CFG1
);
10965 /* NVRAM protection for TPM */
10966 if (nvcfg1
& (1 << 27))
10967 tp
->tg3_flags2
|= TG3_FLG2_PROTECTED_NVRAM
;
10969 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
10970 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ
:
10971 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ
:
10972 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10973 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10975 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
10976 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10977 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10978 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10980 case FLASH_5752VENDOR_ST_M45PE10
:
10981 case FLASH_5752VENDOR_ST_M45PE20
:
10982 case FLASH_5752VENDOR_ST_M45PE40
:
10983 tp
->nvram_jedecnum
= JEDEC_ST
;
10984 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10985 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10989 if (tp
->tg3_flags2
& TG3_FLG2_FLASH
) {
10990 tg3_nvram_get_pagesize(tp
, nvcfg1
);
10992 /* For eeprom, set pagesize to maximum eeprom size */
10993 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
10995 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
10996 tw32(NVRAM_CFG1
, nvcfg1
);
11000 static void __devinit
tg3_get_5755_nvram_info(struct tg3
*tp
)
11002 u32 nvcfg1
, protect
= 0;
11004 nvcfg1
= tr32(NVRAM_CFG1
);
11006 /* NVRAM protection for TPM */
11007 if (nvcfg1
& (1 << 27)) {
11008 tp
->tg3_flags2
|= TG3_FLG2_PROTECTED_NVRAM
;
11012 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
11014 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
11015 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
11016 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
11017 case FLASH_5755VENDOR_ATMEL_FLASH_5
:
11018 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11019 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11020 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11021 tp
->nvram_pagesize
= 264;
11022 if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_1
||
11023 nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_5
)
11024 tp
->nvram_size
= (protect
? 0x3e200 :
11025 TG3_NVRAM_SIZE_512KB
);
11026 else if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_2
)
11027 tp
->nvram_size
= (protect
? 0x1f200 :
11028 TG3_NVRAM_SIZE_256KB
);
11030 tp
->nvram_size
= (protect
? 0x1f200 :
11031 TG3_NVRAM_SIZE_128KB
);
11033 case FLASH_5752VENDOR_ST_M45PE10
:
11034 case FLASH_5752VENDOR_ST_M45PE20
:
11035 case FLASH_5752VENDOR_ST_M45PE40
:
11036 tp
->nvram_jedecnum
= JEDEC_ST
;
11037 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11038 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11039 tp
->nvram_pagesize
= 256;
11040 if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE10
)
11041 tp
->nvram_size
= (protect
?
11042 TG3_NVRAM_SIZE_64KB
:
11043 TG3_NVRAM_SIZE_128KB
);
11044 else if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE20
)
11045 tp
->nvram_size
= (protect
?
11046 TG3_NVRAM_SIZE_64KB
:
11047 TG3_NVRAM_SIZE_256KB
);
11049 tp
->nvram_size
= (protect
?
11050 TG3_NVRAM_SIZE_128KB
:
11051 TG3_NVRAM_SIZE_512KB
);
11056 static void __devinit
tg3_get_5787_nvram_info(struct tg3
*tp
)
11060 nvcfg1
= tr32(NVRAM_CFG1
);
11062 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11063 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ
:
11064 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
11065 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ
:
11066 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
11067 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11068 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11069 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11071 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11072 tw32(NVRAM_CFG1
, nvcfg1
);
11074 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11075 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
11076 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
11077 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
11078 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11079 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11080 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11081 tp
->nvram_pagesize
= 264;
11083 case FLASH_5752VENDOR_ST_M45PE10
:
11084 case FLASH_5752VENDOR_ST_M45PE20
:
11085 case FLASH_5752VENDOR_ST_M45PE40
:
11086 tp
->nvram_jedecnum
= JEDEC_ST
;
11087 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11088 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11089 tp
->nvram_pagesize
= 256;
11094 static void __devinit
tg3_get_5761_nvram_info(struct tg3
*tp
)
11096 u32 nvcfg1
, protect
= 0;
11098 nvcfg1
= tr32(NVRAM_CFG1
);
11100 /* NVRAM protection for TPM */
11101 if (nvcfg1
& (1 << 27)) {
11102 tp
->tg3_flags2
|= TG3_FLG2_PROTECTED_NVRAM
;
11106 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
11108 case FLASH_5761VENDOR_ATMEL_ADB021D
:
11109 case FLASH_5761VENDOR_ATMEL_ADB041D
:
11110 case FLASH_5761VENDOR_ATMEL_ADB081D
:
11111 case FLASH_5761VENDOR_ATMEL_ADB161D
:
11112 case FLASH_5761VENDOR_ATMEL_MDB021D
:
11113 case FLASH_5761VENDOR_ATMEL_MDB041D
:
11114 case FLASH_5761VENDOR_ATMEL_MDB081D
:
11115 case FLASH_5761VENDOR_ATMEL_MDB161D
:
11116 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11117 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11118 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11119 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
11120 tp
->nvram_pagesize
= 256;
11122 case FLASH_5761VENDOR_ST_A_M45PE20
:
11123 case FLASH_5761VENDOR_ST_A_M45PE40
:
11124 case FLASH_5761VENDOR_ST_A_M45PE80
:
11125 case FLASH_5761VENDOR_ST_A_M45PE16
:
11126 case FLASH_5761VENDOR_ST_M_M45PE20
:
11127 case FLASH_5761VENDOR_ST_M_M45PE40
:
11128 case FLASH_5761VENDOR_ST_M_M45PE80
:
11129 case FLASH_5761VENDOR_ST_M_M45PE16
:
11130 tp
->nvram_jedecnum
= JEDEC_ST
;
11131 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11132 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11133 tp
->nvram_pagesize
= 256;
11138 tp
->nvram_size
= tr32(NVRAM_ADDR_LOCKOUT
);
11141 case FLASH_5761VENDOR_ATMEL_ADB161D
:
11142 case FLASH_5761VENDOR_ATMEL_MDB161D
:
11143 case FLASH_5761VENDOR_ST_A_M45PE16
:
11144 case FLASH_5761VENDOR_ST_M_M45PE16
:
11145 tp
->nvram_size
= TG3_NVRAM_SIZE_2MB
;
11147 case FLASH_5761VENDOR_ATMEL_ADB081D
:
11148 case FLASH_5761VENDOR_ATMEL_MDB081D
:
11149 case FLASH_5761VENDOR_ST_A_M45PE80
:
11150 case FLASH_5761VENDOR_ST_M_M45PE80
:
11151 tp
->nvram_size
= TG3_NVRAM_SIZE_1MB
;
11153 case FLASH_5761VENDOR_ATMEL_ADB041D
:
11154 case FLASH_5761VENDOR_ATMEL_MDB041D
:
11155 case FLASH_5761VENDOR_ST_A_M45PE40
:
11156 case FLASH_5761VENDOR_ST_M_M45PE40
:
11157 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11159 case FLASH_5761VENDOR_ATMEL_ADB021D
:
11160 case FLASH_5761VENDOR_ATMEL_MDB021D
:
11161 case FLASH_5761VENDOR_ST_A_M45PE20
:
11162 case FLASH_5761VENDOR_ST_M_M45PE20
:
11163 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11169 static void __devinit
tg3_get_5906_nvram_info(struct tg3
*tp
)
11171 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11172 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11173 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11176 static void __devinit
tg3_get_57780_nvram_info(struct tg3
*tp
)
11180 nvcfg1
= tr32(NVRAM_CFG1
);
11182 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11183 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
11184 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
11185 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11186 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11187 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11189 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11190 tw32(NVRAM_CFG1
, nvcfg1
);
11192 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11193 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
11194 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
11195 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
11196 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
11197 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
11198 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
11199 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11200 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11201 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11203 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11204 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11205 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
11206 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
11207 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11209 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
11210 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
11211 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11213 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
11214 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
11215 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11219 case FLASH_5752VENDOR_ST_M45PE10
:
11220 case FLASH_5752VENDOR_ST_M45PE20
:
11221 case FLASH_5752VENDOR_ST_M45PE40
:
11222 tp
->nvram_jedecnum
= JEDEC_ST
;
11223 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11224 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11226 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11227 case FLASH_5752VENDOR_ST_M45PE10
:
11228 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11230 case FLASH_5752VENDOR_ST_M45PE20
:
11231 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11233 case FLASH_5752VENDOR_ST_M45PE40
:
11234 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11239 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM
;
11243 tg3_nvram_get_pagesize(tp
, nvcfg1
);
11244 if (tp
->nvram_pagesize
!= 264 && tp
->nvram_pagesize
!= 528)
11245 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
11249 static void __devinit
tg3_get_5717_nvram_info(struct tg3
*tp
)
11253 nvcfg1
= tr32(NVRAM_CFG1
);
11255 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11256 case FLASH_5717VENDOR_ATMEL_EEPROM
:
11257 case FLASH_5717VENDOR_MICRO_EEPROM
:
11258 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11259 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11260 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11262 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11263 tw32(NVRAM_CFG1
, nvcfg1
);
11265 case FLASH_5717VENDOR_ATMEL_MDB011D
:
11266 case FLASH_5717VENDOR_ATMEL_ADB011B
:
11267 case FLASH_5717VENDOR_ATMEL_ADB011D
:
11268 case FLASH_5717VENDOR_ATMEL_MDB021D
:
11269 case FLASH_5717VENDOR_ATMEL_ADB021B
:
11270 case FLASH_5717VENDOR_ATMEL_ADB021D
:
11271 case FLASH_5717VENDOR_ATMEL_45USPT
:
11272 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11273 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11274 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11276 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11277 case FLASH_5717VENDOR_ATMEL_MDB021D
:
11278 case FLASH_5717VENDOR_ATMEL_ADB021B
:
11279 case FLASH_5717VENDOR_ATMEL_ADB021D
:
11280 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11283 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11287 case FLASH_5717VENDOR_ST_M_M25PE10
:
11288 case FLASH_5717VENDOR_ST_A_M25PE10
:
11289 case FLASH_5717VENDOR_ST_M_M45PE10
:
11290 case FLASH_5717VENDOR_ST_A_M45PE10
:
11291 case FLASH_5717VENDOR_ST_M_M25PE20
:
11292 case FLASH_5717VENDOR_ST_A_M25PE20
:
11293 case FLASH_5717VENDOR_ST_M_M45PE20
:
11294 case FLASH_5717VENDOR_ST_A_M45PE20
:
11295 case FLASH_5717VENDOR_ST_25USPT
:
11296 case FLASH_5717VENDOR_ST_45USPT
:
11297 tp
->nvram_jedecnum
= JEDEC_ST
;
11298 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11299 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11301 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11302 case FLASH_5717VENDOR_ST_M_M25PE20
:
11303 case FLASH_5717VENDOR_ST_A_M25PE20
:
11304 case FLASH_5717VENDOR_ST_M_M45PE20
:
11305 case FLASH_5717VENDOR_ST_A_M45PE20
:
11306 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11309 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11314 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM
;
11318 tg3_nvram_get_pagesize(tp
, nvcfg1
);
11319 if (tp
->nvram_pagesize
!= 264 && tp
->nvram_pagesize
!= 528)
11320 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
11323 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11324 static void __devinit
tg3_nvram_init(struct tg3
*tp
)
11326 tw32_f(GRC_EEPROM_ADDR
,
11327 (EEPROM_ADDR_FSM_RESET
|
11328 (EEPROM_DEFAULT_CLOCK_PERIOD
<<
11329 EEPROM_ADDR_CLKPERD_SHIFT
)));
11333 /* Enable seeprom accesses. */
11334 tw32_f(GRC_LOCAL_CTRL
,
11335 tr32(GRC_LOCAL_CTRL
) | GRC_LCLCTRL_AUTO_SEEPROM
);
11338 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
11339 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
11340 tp
->tg3_flags
|= TG3_FLAG_NVRAM
;
11342 if (tg3_nvram_lock(tp
)) {
11343 printk(KERN_WARNING PFX
"%s: Cannot get nvarm lock, "
11344 "tg3_nvram_init failed.\n", tp
->dev
->name
);
11347 tg3_enable_nvram_access(tp
);
11349 tp
->nvram_size
= 0;
11351 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
11352 tg3_get_5752_nvram_info(tp
);
11353 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
11354 tg3_get_5755_nvram_info(tp
);
11355 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
11356 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
11357 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
11358 tg3_get_5787_nvram_info(tp
);
11359 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
11360 tg3_get_5761_nvram_info(tp
);
11361 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
11362 tg3_get_5906_nvram_info(tp
);
11363 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
11364 tg3_get_57780_nvram_info(tp
);
11365 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
)
11366 tg3_get_5717_nvram_info(tp
);
11368 tg3_get_nvram_info(tp
);
11370 if (tp
->nvram_size
== 0)
11371 tg3_get_nvram_size(tp
);
11373 tg3_disable_nvram_access(tp
);
11374 tg3_nvram_unlock(tp
);
11377 tp
->tg3_flags
&= ~(TG3_FLAG_NVRAM
| TG3_FLAG_NVRAM_BUFFERED
);
11379 tg3_get_eeprom_size(tp
);
11383 static int tg3_nvram_write_block_using_eeprom(struct tg3
*tp
,
11384 u32 offset
, u32 len
, u8
*buf
)
11389 for (i
= 0; i
< len
; i
+= 4) {
11395 memcpy(&data
, buf
+ i
, 4);
11398 * The SEEPROM interface expects the data to always be opposite
11399 * the native endian format. We accomplish this by reversing
11400 * all the operations that would have been performed on the
11401 * data from a call to tg3_nvram_read_be32().
11403 tw32(GRC_EEPROM_DATA
, swab32(be32_to_cpu(data
)));
11405 val
= tr32(GRC_EEPROM_ADDR
);
11406 tw32(GRC_EEPROM_ADDR
, val
| EEPROM_ADDR_COMPLETE
);
11408 val
&= ~(EEPROM_ADDR_ADDR_MASK
| EEPROM_ADDR_DEVID_MASK
|
11410 tw32(GRC_EEPROM_ADDR
, val
|
11411 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
11412 (addr
& EEPROM_ADDR_ADDR_MASK
) |
11413 EEPROM_ADDR_START
|
11414 EEPROM_ADDR_WRITE
);
11416 for (j
= 0; j
< 1000; j
++) {
11417 val
= tr32(GRC_EEPROM_ADDR
);
11419 if (val
& EEPROM_ADDR_COMPLETE
)
11423 if (!(val
& EEPROM_ADDR_COMPLETE
)) {
11432 /* offset and length are dword aligned */
11433 static int tg3_nvram_write_block_unbuffered(struct tg3
*tp
, u32 offset
, u32 len
,
11437 u32 pagesize
= tp
->nvram_pagesize
;
11438 u32 pagemask
= pagesize
- 1;
11442 tmp
= kmalloc(pagesize
, GFP_KERNEL
);
11448 u32 phy_addr
, page_off
, size
;
11450 phy_addr
= offset
& ~pagemask
;
11452 for (j
= 0; j
< pagesize
; j
+= 4) {
11453 ret
= tg3_nvram_read_be32(tp
, phy_addr
+ j
,
11454 (__be32
*) (tmp
+ j
));
11461 page_off
= offset
& pagemask
;
11468 memcpy(tmp
+ page_off
, buf
, size
);
11470 offset
= offset
+ (pagesize
- page_off
);
11472 tg3_enable_nvram_access(tp
);
11475 * Before we can erase the flash page, we need
11476 * to issue a special "write enable" command.
11478 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
11480 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
11483 /* Erase the target page */
11484 tw32(NVRAM_ADDR
, phy_addr
);
11486 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
|
11487 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_ERASE
;
11489 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
11492 /* Issue another write enable to start the write. */
11493 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
11495 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
11498 for (j
= 0; j
< pagesize
; j
+= 4) {
11501 data
= *((__be32
*) (tmp
+ j
));
11503 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
11505 tw32(NVRAM_ADDR
, phy_addr
+ j
);
11507 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
|
11511 nvram_cmd
|= NVRAM_CMD_FIRST
;
11512 else if (j
== (pagesize
- 4))
11513 nvram_cmd
|= NVRAM_CMD_LAST
;
11515 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
11522 nvram_cmd
= NVRAM_CMD_WRDI
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
11523 tg3_nvram_exec_cmd(tp
, nvram_cmd
);
11530 /* offset and length are dword aligned */
11531 static int tg3_nvram_write_block_buffered(struct tg3
*tp
, u32 offset
, u32 len
,
11536 for (i
= 0; i
< len
; i
+= 4, offset
+= 4) {
11537 u32 page_off
, phy_addr
, nvram_cmd
;
11540 memcpy(&data
, buf
+ i
, 4);
11541 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
11543 page_off
= offset
% tp
->nvram_pagesize
;
11545 phy_addr
= tg3_nvram_phys_addr(tp
, offset
);
11547 tw32(NVRAM_ADDR
, phy_addr
);
11549 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
;
11551 if ((page_off
== 0) || (i
== 0))
11552 nvram_cmd
|= NVRAM_CMD_FIRST
;
11553 if (page_off
== (tp
->nvram_pagesize
- 4))
11554 nvram_cmd
|= NVRAM_CMD_LAST
;
11556 if (i
== (len
- 4))
11557 nvram_cmd
|= NVRAM_CMD_LAST
;
11559 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5752
&&
11560 !(tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) &&
11561 (tp
->nvram_jedecnum
== JEDEC_ST
) &&
11562 (nvram_cmd
& NVRAM_CMD_FIRST
)) {
11564 if ((ret
= tg3_nvram_exec_cmd(tp
,
11565 NVRAM_CMD_WREN
| NVRAM_CMD_GO
|
11570 if (!(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
11571 /* We always do complete word writes to eeprom. */
11572 nvram_cmd
|= (NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
);
11575 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
11581 /* offset and length are dword aligned */
11582 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
)
11586 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
11587 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
&
11588 ~GRC_LCLCTRL_GPIO_OUTPUT1
);
11592 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
)) {
11593 ret
= tg3_nvram_write_block_using_eeprom(tp
, offset
, len
, buf
);
11598 ret
= tg3_nvram_lock(tp
);
11602 tg3_enable_nvram_access(tp
);
11603 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
11604 !(tp
->tg3_flags2
& TG3_FLG2_PROTECTED_NVRAM
))
11605 tw32(NVRAM_WRITE1
, 0x406);
11607 grc_mode
= tr32(GRC_MODE
);
11608 tw32(GRC_MODE
, grc_mode
| GRC_MODE_NVRAM_WR_ENABLE
);
11610 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) ||
11611 !(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
11613 ret
= tg3_nvram_write_block_buffered(tp
, offset
, len
,
11617 ret
= tg3_nvram_write_block_unbuffered(tp
, offset
, len
,
11621 grc_mode
= tr32(GRC_MODE
);
11622 tw32(GRC_MODE
, grc_mode
& ~GRC_MODE_NVRAM_WR_ENABLE
);
11624 tg3_disable_nvram_access(tp
);
11625 tg3_nvram_unlock(tp
);
11628 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
11629 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
11636 struct subsys_tbl_ent
{
11637 u16 subsys_vendor
, subsys_devid
;
11641 static struct subsys_tbl_ent subsys_id_to_phy_id
[] = {
11642 /* Broadcom boards. */
11643 { PCI_VENDOR_ID_BROADCOM
, 0x1644, PHY_ID_BCM5401
}, /* BCM95700A6 */
11644 { PCI_VENDOR_ID_BROADCOM
, 0x0001, PHY_ID_BCM5701
}, /* BCM95701A5 */
11645 { PCI_VENDOR_ID_BROADCOM
, 0x0002, PHY_ID_BCM8002
}, /* BCM95700T6 */
11646 { PCI_VENDOR_ID_BROADCOM
, 0x0003, 0 }, /* BCM95700A9 */
11647 { PCI_VENDOR_ID_BROADCOM
, 0x0005, PHY_ID_BCM5701
}, /* BCM95701T1 */
11648 { PCI_VENDOR_ID_BROADCOM
, 0x0006, PHY_ID_BCM5701
}, /* BCM95701T8 */
11649 { PCI_VENDOR_ID_BROADCOM
, 0x0007, 0 }, /* BCM95701A7 */
11650 { PCI_VENDOR_ID_BROADCOM
, 0x0008, PHY_ID_BCM5701
}, /* BCM95701A10 */
11651 { PCI_VENDOR_ID_BROADCOM
, 0x8008, PHY_ID_BCM5701
}, /* BCM95701A12 */
11652 { PCI_VENDOR_ID_BROADCOM
, 0x0009, PHY_ID_BCM5703
}, /* BCM95703Ax1 */
11653 { PCI_VENDOR_ID_BROADCOM
, 0x8009, PHY_ID_BCM5703
}, /* BCM95703Ax2 */
11656 { PCI_VENDOR_ID_3COM
, 0x1000, PHY_ID_BCM5401
}, /* 3C996T */
11657 { PCI_VENDOR_ID_3COM
, 0x1006, PHY_ID_BCM5701
}, /* 3C996BT */
11658 { PCI_VENDOR_ID_3COM
, 0x1004, 0 }, /* 3C996SX */
11659 { PCI_VENDOR_ID_3COM
, 0x1007, PHY_ID_BCM5701
}, /* 3C1000T */
11660 { PCI_VENDOR_ID_3COM
, 0x1008, PHY_ID_BCM5701
}, /* 3C940BR01 */
11663 { PCI_VENDOR_ID_DELL
, 0x00d1, PHY_ID_BCM5401
}, /* VIPER */
11664 { PCI_VENDOR_ID_DELL
, 0x0106, PHY_ID_BCM5401
}, /* JAGUAR */
11665 { PCI_VENDOR_ID_DELL
, 0x0109, PHY_ID_BCM5411
}, /* MERLOT */
11666 { PCI_VENDOR_ID_DELL
, 0x010a, PHY_ID_BCM5411
}, /* SLIM_MERLOT */
11668 /* Compaq boards. */
11669 { PCI_VENDOR_ID_COMPAQ
, 0x007c, PHY_ID_BCM5701
}, /* BANSHEE */
11670 { PCI_VENDOR_ID_COMPAQ
, 0x009a, PHY_ID_BCM5701
}, /* BANSHEE_2 */
11671 { PCI_VENDOR_ID_COMPAQ
, 0x007d, 0 }, /* CHANGELING */
11672 { PCI_VENDOR_ID_COMPAQ
, 0x0085, PHY_ID_BCM5701
}, /* NC7780 */
11673 { PCI_VENDOR_ID_COMPAQ
, 0x0099, PHY_ID_BCM5701
}, /* NC7780_2 */
11676 { PCI_VENDOR_ID_IBM
, 0x0281, 0 } /* IBM??? */
11679 static inline struct subsys_tbl_ent
*lookup_by_subsys(struct tg3
*tp
)
11683 for (i
= 0; i
< ARRAY_SIZE(subsys_id_to_phy_id
); i
++) {
11684 if ((subsys_id_to_phy_id
[i
].subsys_vendor
==
11685 tp
->pdev
->subsystem_vendor
) &&
11686 (subsys_id_to_phy_id
[i
].subsys_devid
==
11687 tp
->pdev
->subsystem_device
))
11688 return &subsys_id_to_phy_id
[i
];
11693 static void __devinit
tg3_get_eeprom_hw_cfg(struct tg3
*tp
)
11698 /* On some early chips the SRAM cannot be accessed in D3hot state,
11699 * so need make sure we're in D0.
11701 pci_read_config_word(tp
->pdev
, tp
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
11702 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
11703 pci_write_config_word(tp
->pdev
, tp
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
11706 /* Make sure register accesses (indirect or otherwise)
11707 * will function correctly.
11709 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
11710 tp
->misc_host_ctrl
);
11712 /* The memory arbiter has to be enabled in order for SRAM accesses
11713 * to succeed. Normally on powerup the tg3 chip firmware will make
11714 * sure it is enabled, but other entities such as system netboot
11715 * code might disable it.
11717 val
= tr32(MEMARB_MODE
);
11718 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
11720 tp
->phy_id
= PHY_ID_INVALID
;
11721 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
11723 /* Assume an onboard device and WOL capable by default. */
11724 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
| TG3_FLAG_WOL_CAP
;
11726 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
11727 if (!(tr32(PCIE_TRANSACTION_CFG
) & PCIE_TRANS_CFG_LOM
)) {
11728 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
11729 tp
->tg3_flags2
|= TG3_FLG2_IS_NIC
;
11731 val
= tr32(VCPU_CFGSHDW
);
11732 if (val
& VCPU_CFGSHDW_ASPM_DBNC
)
11733 tp
->tg3_flags
|= TG3_FLAG_ASPM_WORKAROUND
;
11734 if ((val
& VCPU_CFGSHDW_WOL_ENABLE
) &&
11735 (val
& VCPU_CFGSHDW_WOL_MAGPKT
))
11736 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
11740 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
11741 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
11742 u32 nic_cfg
, led_cfg
;
11743 u32 nic_phy_id
, ver
, cfg2
= 0, cfg4
= 0, eeprom_phy_id
;
11744 int eeprom_phy_serdes
= 0;
11746 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
11747 tp
->nic_sram_data_cfg
= nic_cfg
;
11749 tg3_read_mem(tp
, NIC_SRAM_DATA_VER
, &ver
);
11750 ver
>>= NIC_SRAM_DATA_VER_SHIFT
;
11751 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
) &&
11752 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) &&
11753 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5703
) &&
11754 (ver
> 0) && (ver
< 0x100))
11755 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_2
, &cfg2
);
11757 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
11758 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_4
, &cfg4
);
11760 if ((nic_cfg
& NIC_SRAM_DATA_CFG_PHY_TYPE_MASK
) ==
11761 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER
)
11762 eeprom_phy_serdes
= 1;
11764 tg3_read_mem(tp
, NIC_SRAM_DATA_PHY_ID
, &nic_phy_id
);
11765 if (nic_phy_id
!= 0) {
11766 u32 id1
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID1_MASK
;
11767 u32 id2
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID2_MASK
;
11769 eeprom_phy_id
= (id1
>> 16) << 10;
11770 eeprom_phy_id
|= (id2
& 0xfc00) << 16;
11771 eeprom_phy_id
|= (id2
& 0x03ff) << 0;
11775 tp
->phy_id
= eeprom_phy_id
;
11776 if (eeprom_phy_serdes
) {
11777 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
11778 tp
->tg3_flags2
|= TG3_FLG2_MII_SERDES
;
11780 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
11783 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
11784 led_cfg
= cfg2
& (NIC_SRAM_DATA_CFG_LED_MODE_MASK
|
11785 SHASTA_EXT_LED_MODE_MASK
);
11787 led_cfg
= nic_cfg
& NIC_SRAM_DATA_CFG_LED_MODE_MASK
;
11791 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1
:
11792 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
11795 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2
:
11796 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
11799 case NIC_SRAM_DATA_CFG_LED_MODE_MAC
:
11800 tp
->led_ctrl
= LED_CTRL_MODE_MAC
;
11802 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11803 * read on some older 5700/5701 bootcode.
11805 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
11807 GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
11809 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
11813 case SHASTA_EXT_LED_SHARED
:
11814 tp
->led_ctrl
= LED_CTRL_MODE_SHARED
;
11815 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
&&
11816 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A1
)
11817 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
11818 LED_CTRL_MODE_PHY_2
);
11821 case SHASTA_EXT_LED_MAC
:
11822 tp
->led_ctrl
= LED_CTRL_MODE_SHASTA_MAC
;
11825 case SHASTA_EXT_LED_COMBO
:
11826 tp
->led_ctrl
= LED_CTRL_MODE_COMBO
;
11827 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
)
11828 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
11829 LED_CTRL_MODE_PHY_2
);
11834 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
11835 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) &&
11836 tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
)
11837 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
11839 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
)
11840 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
11842 if (nic_cfg
& NIC_SRAM_DATA_CFG_EEPROM_WP
) {
11843 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
;
11844 if ((tp
->pdev
->subsystem_vendor
==
11845 PCI_VENDOR_ID_ARIMA
) &&
11846 (tp
->pdev
->subsystem_device
== 0x205a ||
11847 tp
->pdev
->subsystem_device
== 0x2063))
11848 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
11850 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
11851 tp
->tg3_flags2
|= TG3_FLG2_IS_NIC
;
11854 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
11855 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
11856 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
11857 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
11860 if ((nic_cfg
& NIC_SRAM_DATA_CFG_APE_ENABLE
) &&
11861 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
11862 tp
->tg3_flags3
|= TG3_FLG3_ENABLE_APE
;
11864 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
&&
11865 !(nic_cfg
& NIC_SRAM_DATA_CFG_FIBER_WOL
))
11866 tp
->tg3_flags
&= ~TG3_FLAG_WOL_CAP
;
11868 if ((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) &&
11869 (nic_cfg
& NIC_SRAM_DATA_CFG_WOL_ENABLE
))
11870 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
11872 if (cfg2
& (1 << 17))
11873 tp
->tg3_flags2
|= TG3_FLG2_CAPACITIVE_COUPLING
;
11875 /* serdes signal pre-emphasis in register 0x590 set by */
11876 /* bootcode if bit 18 is set */
11877 if (cfg2
& (1 << 18))
11878 tp
->tg3_flags2
|= TG3_FLG2_SERDES_PREEMPHASIS
;
11880 if (((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
11881 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
)) &&
11882 (cfg2
& NIC_SRAM_DATA_CFG_2_APD_EN
))
11883 tp
->tg3_flags3
|= TG3_FLG3_PHY_ENABLE_APD
;
11885 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
11888 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_3
, &cfg3
);
11889 if (cfg3
& NIC_SRAM_ASPM_DEBOUNCE
)
11890 tp
->tg3_flags
|= TG3_FLAG_ASPM_WORKAROUND
;
11893 if (cfg4
& NIC_SRAM_RGMII_STD_IBND_DISABLE
)
11894 tp
->tg3_flags3
|= TG3_FLG3_RGMII_STD_IBND_DISABLE
;
11895 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_RX_EN
)
11896 tp
->tg3_flags3
|= TG3_FLG3_RGMII_EXT_IBND_RX_EN
;
11897 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_TX_EN
)
11898 tp
->tg3_flags3
|= TG3_FLG3_RGMII_EXT_IBND_TX_EN
;
11901 device_init_wakeup(&tp
->pdev
->dev
, tp
->tg3_flags
& TG3_FLAG_WOL_CAP
);
11902 device_set_wakeup_enable(&tp
->pdev
->dev
,
11903 tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
11906 static int __devinit
tg3_issue_otp_command(struct tg3
*tp
, u32 cmd
)
11911 tw32(OTP_CTRL
, cmd
| OTP_CTRL_OTP_CMD_START
);
11912 tw32(OTP_CTRL
, cmd
);
11914 /* Wait for up to 1 ms for command to execute. */
11915 for (i
= 0; i
< 100; i
++) {
11916 val
= tr32(OTP_STATUS
);
11917 if (val
& OTP_STATUS_CMD_DONE
)
11922 return (val
& OTP_STATUS_CMD_DONE
) ? 0 : -EBUSY
;
11925 /* Read the gphy configuration from the OTP region of the chip. The gphy
11926 * configuration is a 32-bit value that straddles the alignment boundary.
11927 * We do two 32-bit reads and then shift and merge the results.
11929 static u32 __devinit
tg3_read_otp_phycfg(struct tg3
*tp
)
11931 u32 bhalf_otp
, thalf_otp
;
11933 tw32(OTP_MODE
, OTP_MODE_OTP_THRU_GRC
);
11935 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_INIT
))
11938 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC1
);
11940 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
11943 thalf_otp
= tr32(OTP_READ_DATA
);
11945 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC2
);
11947 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
11950 bhalf_otp
= tr32(OTP_READ_DATA
);
11952 return ((thalf_otp
& 0x0000ffff) << 16) | (bhalf_otp
>> 16);
11955 static int __devinit
tg3_phy_probe(struct tg3
*tp
)
11957 u32 hw_phy_id_1
, hw_phy_id_2
;
11958 u32 hw_phy_id
, hw_phy_id_masked
;
11961 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)
11962 return tg3_phy_init(tp
);
11964 /* Reading the PHY ID register can conflict with ASF
11965 * firmware access to the PHY hardware.
11968 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
11969 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
11970 hw_phy_id
= hw_phy_id_masked
= PHY_ID_INVALID
;
11972 /* Now read the physical PHY_ID from the chip and verify
11973 * that it is sane. If it doesn't look good, we fall back
11974 * to either the hard-coded table based PHY_ID and failing
11975 * that the value found in the eeprom area.
11977 err
|= tg3_readphy(tp
, MII_PHYSID1
, &hw_phy_id_1
);
11978 err
|= tg3_readphy(tp
, MII_PHYSID2
, &hw_phy_id_2
);
11980 hw_phy_id
= (hw_phy_id_1
& 0xffff) << 10;
11981 hw_phy_id
|= (hw_phy_id_2
& 0xfc00) << 16;
11982 hw_phy_id
|= (hw_phy_id_2
& 0x03ff) << 0;
11984 hw_phy_id_masked
= hw_phy_id
& PHY_ID_MASK
;
11987 if (!err
&& KNOWN_PHY_ID(hw_phy_id_masked
)) {
11988 tp
->phy_id
= hw_phy_id
;
11989 if (hw_phy_id_masked
== PHY_ID_BCM8002
)
11990 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
11992 tp
->tg3_flags2
&= ~TG3_FLG2_PHY_SERDES
;
11994 if (tp
->phy_id
!= PHY_ID_INVALID
) {
11995 /* Do nothing, phy ID already set up in
11996 * tg3_get_eeprom_hw_cfg().
11999 struct subsys_tbl_ent
*p
;
12001 /* No eeprom signature? Try the hardcoded
12002 * subsys device table.
12004 p
= lookup_by_subsys(tp
);
12008 tp
->phy_id
= p
->phy_id
;
12010 tp
->phy_id
== PHY_ID_BCM8002
)
12011 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
12015 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
) &&
12016 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) &&
12017 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
12018 u32 bmsr
, adv_reg
, tg3_ctrl
, mask
;
12020 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
12021 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
12022 (bmsr
& BMSR_LSTATUS
))
12023 goto skip_phy_reset
;
12025 err
= tg3_phy_reset(tp
);
12029 adv_reg
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
12030 ADVERTISE_100HALF
| ADVERTISE_100FULL
|
12031 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
12033 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
12034 tg3_ctrl
= (MII_TG3_CTRL_ADV_1000_HALF
|
12035 MII_TG3_CTRL_ADV_1000_FULL
);
12036 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
12037 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
12038 tg3_ctrl
|= (MII_TG3_CTRL_AS_MASTER
|
12039 MII_TG3_CTRL_ENABLE_AS_MASTER
);
12042 mask
= (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
12043 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
12044 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
);
12045 if (!tg3_copper_is_advertising_all(tp
, mask
)) {
12046 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
12048 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
12049 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
12051 tg3_writephy(tp
, MII_BMCR
,
12052 BMCR_ANENABLE
| BMCR_ANRESTART
);
12054 tg3_phy_set_wirespeed(tp
);
12056 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
12057 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
12058 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
12062 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
) {
12063 err
= tg3_init_5401phy_dsp(tp
);
12068 if (!err
&& ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
)) {
12069 err
= tg3_init_5401phy_dsp(tp
);
12072 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)
12073 tp
->link_config
.advertising
=
12074 (ADVERTISED_1000baseT_Half
|
12075 ADVERTISED_1000baseT_Full
|
12076 ADVERTISED_Autoneg
|
12078 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
12079 tp
->link_config
.advertising
&=
12080 ~(ADVERTISED_1000baseT_Half
|
12081 ADVERTISED_1000baseT_Full
);
12086 static void __devinit
tg3_read_partno(struct tg3
*tp
)
12088 unsigned char vpd_data
[256]; /* in little-endian format */
12092 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
12093 tg3_nvram_read(tp
, 0x0, &magic
))
12094 goto out_not_found
;
12096 if (magic
== TG3_EEPROM_MAGIC
) {
12097 for (i
= 0; i
< 256; i
+= 4) {
12100 /* The data is in little-endian format in NVRAM.
12101 * Use the big-endian read routines to preserve
12102 * the byte order as it exists in NVRAM.
12104 if (tg3_nvram_read_be32(tp
, 0x100 + i
, &tmp
))
12105 goto out_not_found
;
12107 memcpy(&vpd_data
[i
], &tmp
, sizeof(tmp
));
12112 vpd_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_VPD
);
12113 for (i
= 0; i
< 256; i
+= 4) {
12118 pci_write_config_word(tp
->pdev
, vpd_cap
+ PCI_VPD_ADDR
,
12120 while (j
++ < 100) {
12121 pci_read_config_word(tp
->pdev
, vpd_cap
+
12122 PCI_VPD_ADDR
, &tmp16
);
12123 if (tmp16
& 0x8000)
12127 if (!(tmp16
& 0x8000))
12128 goto out_not_found
;
12130 pci_read_config_dword(tp
->pdev
, vpd_cap
+ PCI_VPD_DATA
,
12132 v
= cpu_to_le32(tmp
);
12133 memcpy(&vpd_data
[i
], &v
, sizeof(v
));
12137 /* Now parse and find the part number. */
12138 for (i
= 0; i
< 254; ) {
12139 unsigned char val
= vpd_data
[i
];
12140 unsigned int block_end
;
12142 if (val
== 0x82 || val
== 0x91) {
12145 (vpd_data
[i
+ 2] << 8)));
12150 goto out_not_found
;
12152 block_end
= (i
+ 3 +
12154 (vpd_data
[i
+ 2] << 8)));
12157 if (block_end
> 256)
12158 goto out_not_found
;
12160 while (i
< (block_end
- 2)) {
12161 if (vpd_data
[i
+ 0] == 'P' &&
12162 vpd_data
[i
+ 1] == 'N') {
12163 int partno_len
= vpd_data
[i
+ 2];
12166 if (partno_len
> 24 || (partno_len
+ i
) > 256)
12167 goto out_not_found
;
12169 memcpy(tp
->board_part_number
,
12170 &vpd_data
[i
], partno_len
);
12175 i
+= 3 + vpd_data
[i
+ 2];
12178 /* Part number not found. */
12179 goto out_not_found
;
12183 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
12184 strcpy(tp
->board_part_number
, "BCM95906");
12185 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
12186 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57780
)
12187 strcpy(tp
->board_part_number
, "BCM57780");
12188 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
12189 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57760
)
12190 strcpy(tp
->board_part_number
, "BCM57760");
12191 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
12192 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57790
)
12193 strcpy(tp
->board_part_number
, "BCM57790");
12194 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
12195 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57788
)
12196 strcpy(tp
->board_part_number
, "BCM57788");
12198 strcpy(tp
->board_part_number
, "none");
12201 static int __devinit
tg3_fw_img_is_valid(struct tg3
*tp
, u32 offset
)
12205 if (tg3_nvram_read(tp
, offset
, &val
) ||
12206 (val
& 0xfc000000) != 0x0c000000 ||
12207 tg3_nvram_read(tp
, offset
+ 4, &val
) ||
12214 static void __devinit
tg3_read_bc_ver(struct tg3
*tp
)
12216 u32 val
, offset
, start
, ver_offset
;
12218 bool newver
= false;
12220 if (tg3_nvram_read(tp
, 0xc, &offset
) ||
12221 tg3_nvram_read(tp
, 0x4, &start
))
12224 offset
= tg3_nvram_logical_addr(tp
, offset
);
12226 if (tg3_nvram_read(tp
, offset
, &val
))
12229 if ((val
& 0xfc000000) == 0x0c000000) {
12230 if (tg3_nvram_read(tp
, offset
+ 4, &val
))
12238 if (tg3_nvram_read(tp
, offset
+ 8, &ver_offset
))
12241 offset
= offset
+ ver_offset
- start
;
12242 for (i
= 0; i
< 16; i
+= 4) {
12244 if (tg3_nvram_read_be32(tp
, offset
+ i
, &v
))
12247 memcpy(tp
->fw_ver
+ i
, &v
, sizeof(v
));
12252 if (tg3_nvram_read(tp
, TG3_NVM_PTREV_BCVER
, &ver_offset
))
12255 major
= (ver_offset
& TG3_NVM_BCVER_MAJMSK
) >>
12256 TG3_NVM_BCVER_MAJSFT
;
12257 minor
= ver_offset
& TG3_NVM_BCVER_MINMSK
;
12258 snprintf(&tp
->fw_ver
[0], 32, "v%d.%02d", major
, minor
);
12262 static void __devinit
tg3_read_hwsb_ver(struct tg3
*tp
)
12264 u32 val
, major
, minor
;
12266 /* Use native endian representation */
12267 if (tg3_nvram_read(tp
, TG3_NVM_HWSB_CFG1
, &val
))
12270 major
= (val
& TG3_NVM_HWSB_CFG1_MAJMSK
) >>
12271 TG3_NVM_HWSB_CFG1_MAJSFT
;
12272 minor
= (val
& TG3_NVM_HWSB_CFG1_MINMSK
) >>
12273 TG3_NVM_HWSB_CFG1_MINSFT
;
12275 snprintf(&tp
->fw_ver
[0], 32, "sb v%d.%02d", major
, minor
);
12278 static void __devinit
tg3_read_sb_ver(struct tg3
*tp
, u32 val
)
12280 u32 offset
, major
, minor
, build
;
12282 tp
->fw_ver
[0] = 's';
12283 tp
->fw_ver
[1] = 'b';
12284 tp
->fw_ver
[2] = '\0';
12286 if ((val
& TG3_EEPROM_SB_FORMAT_MASK
) != TG3_EEPROM_SB_FORMAT_1
)
12289 switch (val
& TG3_EEPROM_SB_REVISION_MASK
) {
12290 case TG3_EEPROM_SB_REVISION_0
:
12291 offset
= TG3_EEPROM_SB_F1R0_EDH_OFF
;
12293 case TG3_EEPROM_SB_REVISION_2
:
12294 offset
= TG3_EEPROM_SB_F1R2_EDH_OFF
;
12296 case TG3_EEPROM_SB_REVISION_3
:
12297 offset
= TG3_EEPROM_SB_F1R3_EDH_OFF
;
12303 if (tg3_nvram_read(tp
, offset
, &val
))
12306 build
= (val
& TG3_EEPROM_SB_EDH_BLD_MASK
) >>
12307 TG3_EEPROM_SB_EDH_BLD_SHFT
;
12308 major
= (val
& TG3_EEPROM_SB_EDH_MAJ_MASK
) >>
12309 TG3_EEPROM_SB_EDH_MAJ_SHFT
;
12310 minor
= val
& TG3_EEPROM_SB_EDH_MIN_MASK
;
12312 if (minor
> 99 || build
> 26)
12315 snprintf(&tp
->fw_ver
[2], 30, " v%d.%02d", major
, minor
);
12318 tp
->fw_ver
[8] = 'a' + build
- 1;
12319 tp
->fw_ver
[9] = '\0';
12323 static void __devinit
tg3_read_mgmtfw_ver(struct tg3
*tp
)
12325 u32 val
, offset
, start
;
12328 for (offset
= TG3_NVM_DIR_START
;
12329 offset
< TG3_NVM_DIR_END
;
12330 offset
+= TG3_NVM_DIRENT_SIZE
) {
12331 if (tg3_nvram_read(tp
, offset
, &val
))
12334 if ((val
>> TG3_NVM_DIRTYPE_SHIFT
) == TG3_NVM_DIRTYPE_ASFINI
)
12338 if (offset
== TG3_NVM_DIR_END
)
12341 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
12342 start
= 0x08000000;
12343 else if (tg3_nvram_read(tp
, offset
- 4, &start
))
12346 if (tg3_nvram_read(tp
, offset
+ 4, &offset
) ||
12347 !tg3_fw_img_is_valid(tp
, offset
) ||
12348 tg3_nvram_read(tp
, offset
+ 8, &val
))
12351 offset
+= val
- start
;
12353 vlen
= strlen(tp
->fw_ver
);
12355 tp
->fw_ver
[vlen
++] = ',';
12356 tp
->fw_ver
[vlen
++] = ' ';
12358 for (i
= 0; i
< 4; i
++) {
12360 if (tg3_nvram_read_be32(tp
, offset
, &v
))
12363 offset
+= sizeof(v
);
12365 if (vlen
> TG3_VER_SIZE
- sizeof(v
)) {
12366 memcpy(&tp
->fw_ver
[vlen
], &v
, TG3_VER_SIZE
- vlen
);
12370 memcpy(&tp
->fw_ver
[vlen
], &v
, sizeof(v
));
12375 static void __devinit
tg3_read_dash_ver(struct tg3
*tp
)
12380 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) ||
12381 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
12384 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
12385 if (apedata
!= APE_SEG_SIG_MAGIC
)
12388 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
12389 if (!(apedata
& APE_FW_STATUS_READY
))
12392 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_VERSION
);
12394 vlen
= strlen(tp
->fw_ver
);
12396 snprintf(&tp
->fw_ver
[vlen
], TG3_VER_SIZE
- vlen
, " DASH v%d.%d.%d.%d",
12397 (apedata
& APE_FW_VERSION_MAJMSK
) >> APE_FW_VERSION_MAJSFT
,
12398 (apedata
& APE_FW_VERSION_MINMSK
) >> APE_FW_VERSION_MINSFT
,
12399 (apedata
& APE_FW_VERSION_REVMSK
) >> APE_FW_VERSION_REVSFT
,
12400 (apedata
& APE_FW_VERSION_BLDMSK
));
12403 static void __devinit
tg3_read_fw_ver(struct tg3
*tp
)
12407 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) {
12408 tp
->fw_ver
[0] = 's';
12409 tp
->fw_ver
[1] = 'b';
12410 tp
->fw_ver
[2] = '\0';
12415 if (tg3_nvram_read(tp
, 0, &val
))
12418 if (val
== TG3_EEPROM_MAGIC
)
12419 tg3_read_bc_ver(tp
);
12420 else if ((val
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
)
12421 tg3_read_sb_ver(tp
, val
);
12422 else if ((val
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
12423 tg3_read_hwsb_ver(tp
);
12427 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
12428 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
12431 tg3_read_mgmtfw_ver(tp
);
12433 tp
->fw_ver
[TG3_VER_SIZE
- 1] = 0;
12436 static struct pci_dev
* __devinit
tg3_find_peer(struct tg3
*);
12438 static int __devinit
tg3_get_invariants(struct tg3
*tp
)
12440 static struct pci_device_id write_reorder_chipsets
[] = {
12441 { PCI_DEVICE(PCI_VENDOR_ID_AMD
,
12442 PCI_DEVICE_ID_AMD_FE_GATE_700C
) },
12443 { PCI_DEVICE(PCI_VENDOR_ID_AMD
,
12444 PCI_DEVICE_ID_AMD_8131_BRIDGE
) },
12445 { PCI_DEVICE(PCI_VENDOR_ID_VIA
,
12446 PCI_DEVICE_ID_VIA_8385_0
) },
12450 u32 pci_state_reg
, grc_misc_cfg
;
12455 /* Force memory write invalidate off. If we leave it on,
12456 * then on 5700_BX chips we have to enable a workaround.
12457 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12458 * to match the cacheline size. The Broadcom driver have this
12459 * workaround but turns MWI off all the times so never uses
12460 * it. This seems to suggest that the workaround is insufficient.
12462 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
12463 pci_cmd
&= ~PCI_COMMAND_INVALIDATE
;
12464 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
12466 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12467 * has the register indirect write enable bit set before
12468 * we try to access any of the MMIO registers. It is also
12469 * critical that the PCI-X hw workaround situation is decided
12470 * before that as well.
12472 pci_read_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
12475 tp
->pci_chip_rev_id
= (misc_ctrl_reg
>>
12476 MISC_HOST_CTRL_CHIPREV_SHIFT
);
12477 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_USE_PROD_ID_REG
) {
12478 u32 prod_id_asic_rev
;
12480 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5717C
||
12481 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5717S
||
12482 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5718C
||
12483 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5718S
)
12484 pci_read_config_dword(tp
->pdev
,
12485 TG3PCI_GEN2_PRODID_ASICREV
,
12486 &prod_id_asic_rev
);
12488 pci_read_config_dword(tp
->pdev
, TG3PCI_PRODID_ASICREV
,
12489 &prod_id_asic_rev
);
12491 tp
->pci_chip_rev_id
= prod_id_asic_rev
;
12494 /* Wrong chip ID in 5752 A0. This code can be removed later
12495 * as A0 is not in production.
12497 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5752_A0_HW
)
12498 tp
->pci_chip_rev_id
= CHIPREV_ID_5752_A0
;
12500 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12501 * we need to disable memory and use config. cycles
12502 * only to access all registers. The 5702/03 chips
12503 * can mistakenly decode the special cycles from the
12504 * ICH chipsets as memory write cycles, causing corruption
12505 * of register and memory space. Only certain ICH bridges
12506 * will drive special cycles with non-zero data during the
12507 * address phase which can fall within the 5703's address
12508 * range. This is not an ICH bug as the PCI spec allows
12509 * non-zero address during special cycles. However, only
12510 * these ICH bridges are known to drive non-zero addresses
12511 * during special cycles.
12513 * Since special cycles do not cross PCI bridges, we only
12514 * enable this workaround if the 5703 is on the secondary
12515 * bus of these ICH bridges.
12517 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
) ||
12518 (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A2
)) {
12519 static struct tg3_dev_id
{
12523 } ich_chipsets
[] = {
12524 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_8
,
12526 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_8
,
12528 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_11
,
12530 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_6
,
12534 struct tg3_dev_id
*pci_id
= &ich_chipsets
[0];
12535 struct pci_dev
*bridge
= NULL
;
12537 while (pci_id
->vendor
!= 0) {
12538 bridge
= pci_get_device(pci_id
->vendor
, pci_id
->device
,
12544 if (pci_id
->rev
!= PCI_ANY_ID
) {
12545 if (bridge
->revision
> pci_id
->rev
)
12548 if (bridge
->subordinate
&&
12549 (bridge
->subordinate
->number
==
12550 tp
->pdev
->bus
->number
)) {
12552 tp
->tg3_flags2
|= TG3_FLG2_ICH_WORKAROUND
;
12553 pci_dev_put(bridge
);
12559 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
12560 static struct tg3_dev_id
{
12563 } bridge_chipsets
[] = {
12564 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
},
12565 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
},
12568 struct tg3_dev_id
*pci_id
= &bridge_chipsets
[0];
12569 struct pci_dev
*bridge
= NULL
;
12571 while (pci_id
->vendor
!= 0) {
12572 bridge
= pci_get_device(pci_id
->vendor
,
12579 if (bridge
->subordinate
&&
12580 (bridge
->subordinate
->number
<=
12581 tp
->pdev
->bus
->number
) &&
12582 (bridge
->subordinate
->subordinate
>=
12583 tp
->pdev
->bus
->number
)) {
12584 tp
->tg3_flags3
|= TG3_FLG3_5701_DMA_BUG
;
12585 pci_dev_put(bridge
);
12591 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12592 * DMA addresses > 40-bit. This bridge may have other additional
12593 * 57xx devices behind it in some 4-port NIC designs for example.
12594 * Any tg3 device found behind the bridge will also need the 40-bit
12597 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
||
12598 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
12599 tp
->tg3_flags2
|= TG3_FLG2_5780_CLASS
;
12600 tp
->tg3_flags
|= TG3_FLAG_40BIT_DMA_BUG
;
12601 tp
->msi_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_MSI
);
12604 struct pci_dev
*bridge
= NULL
;
12607 bridge
= pci_get_device(PCI_VENDOR_ID_SERVERWORKS
,
12608 PCI_DEVICE_ID_SERVERWORKS_EPB
,
12610 if (bridge
&& bridge
->subordinate
&&
12611 (bridge
->subordinate
->number
<=
12612 tp
->pdev
->bus
->number
) &&
12613 (bridge
->subordinate
->subordinate
>=
12614 tp
->pdev
->bus
->number
)) {
12615 tp
->tg3_flags
|= TG3_FLAG_40BIT_DMA_BUG
;
12616 pci_dev_put(bridge
);
12622 /* Initialize misc host control in PCI block. */
12623 tp
->misc_host_ctrl
|= (misc_ctrl_reg
&
12624 MISC_HOST_CTRL_CHIPREV
);
12625 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
12626 tp
->misc_host_ctrl
);
12628 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
12629 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
||
12630 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
)
12631 tp
->pdev_peer
= tg3_find_peer(tp
);
12633 /* Intentionally exclude ASIC_REV_5906 */
12634 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
12635 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
12636 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
12637 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
12638 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
12639 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
12640 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
)
12641 tp
->tg3_flags3
|= TG3_FLG3_5755_PLUS
;
12643 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
12644 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
12645 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
||
12646 (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
12647 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
12648 tp
->tg3_flags2
|= TG3_FLG2_5750_PLUS
;
12650 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) ||
12651 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
12652 tp
->tg3_flags2
|= TG3_FLG2_5705_PLUS
;
12654 /* 5700 B0 chips do not support checksumming correctly due
12655 * to hardware bugs.
12657 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5700_B0
)
12658 tp
->tg3_flags
|= TG3_FLAG_BROKEN_CHECKSUMS
;
12660 tp
->tg3_flags
|= TG3_FLAG_RX_CHECKSUMS
;
12661 tp
->dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
12662 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
12663 tp
->dev
->features
|= NETIF_F_IPV6_CSUM
;
12666 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
12667 tp
->tg3_flags
|= TG3_FLAG_SUPPORT_MSI
;
12668 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
||
12669 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
||
12670 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
&&
12671 tp
->pci_chip_rev_id
<= CHIPREV_ID_5714_A2
&&
12672 tp
->pdev_peer
== tp
->pdev
))
12673 tp
->tg3_flags
&= ~TG3_FLAG_SUPPORT_MSI
;
12675 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
12676 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
12677 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_2
;
12678 tp
->tg3_flags2
|= TG3_FLG2_1SHOT_MSI
;
12680 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_1
| TG3_FLG2_TSO_BUG
;
12681 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
12683 tp
->pci_chip_rev_id
>= CHIPREV_ID_5750_C2
)
12684 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_BUG
;
12690 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
) {
12691 tp
->tg3_flags
|= TG3_FLAG_SUPPORT_MSIX
;
12692 tp
->irq_max
= TG3_IRQ_MAX_VECS
;
12695 if (!(tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)) {
12696 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
12697 tp
->tg3_flags3
|= TG3_FLG3_SHORT_DMA_BUG
;
12699 tp
->tg3_flags3
|= TG3_FLG3_4G_DMA_BNDRY_BUG
;
12700 tp
->tg3_flags3
|= TG3_FLG3_40BIT_DMA_LIMIT_BUG
;
12704 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
12705 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
12706 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
)
12707 tp
->tg3_flags
|= TG3_FLAG_JUMBO_CAPABLE
;
12709 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
12712 tp
->pcie_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_EXP
);
12713 if (tp
->pcie_cap
!= 0) {
12716 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
12718 pcie_set_readrq(tp
->pdev
, 4096);
12720 pci_read_config_word(tp
->pdev
,
12721 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
12723 if (lnkctl
& PCI_EXP_LNKCTL_CLKREQ_EN
) {
12724 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
12725 tp
->tg3_flags2
&= ~TG3_FLG2_HW_TSO_2
;
12726 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
12727 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
12728 tp
->pci_chip_rev_id
== CHIPREV_ID_57780_A0
||
12729 tp
->pci_chip_rev_id
== CHIPREV_ID_57780_A1
)
12730 tp
->tg3_flags3
|= TG3_FLG3_CLKREQ_BUG
;
12732 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
) {
12733 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
12734 } else if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
12735 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
12736 tp
->pcix_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_PCIX
);
12737 if (!tp
->pcix_cap
) {
12738 printk(KERN_ERR PFX
"Cannot find PCI-X "
12739 "capability, aborting.\n");
12743 if (!(pci_state_reg
& PCISTATE_CONV_PCI_MODE
))
12744 tp
->tg3_flags
|= TG3_FLAG_PCIX_MODE
;
12747 /* If we have an AMD 762 or VIA K8T800 chipset, write
12748 * reordering to the mailbox registers done by the host
12749 * controller can cause major troubles. We read back from
12750 * every mailbox register write to force the writes to be
12751 * posted to the chip in order.
12753 if (pci_dev_present(write_reorder_chipsets
) &&
12754 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
12755 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
12757 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
12758 &tp
->pci_cacheline_sz
);
12759 pci_read_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
12760 &tp
->pci_lat_timer
);
12761 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
12762 tp
->pci_lat_timer
< 64) {
12763 tp
->pci_lat_timer
= 64;
12764 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
12765 tp
->pci_lat_timer
);
12768 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5700_BX
) {
12769 /* 5700 BX chips need to have their TX producer index
12770 * mailboxes written twice to workaround a bug.
12772 tp
->tg3_flags
|= TG3_FLAG_TXD_MBOX_HWBUG
;
12774 /* If we are in PCI-X mode, enable register write workaround.
12776 * The workaround is to use indirect register accesses
12777 * for all chip writes not to mailbox registers.
12779 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
12782 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
12784 /* The chip can have it's power management PCI config
12785 * space registers clobbered due to this bug.
12786 * So explicitly force the chip into D0 here.
12788 pci_read_config_dword(tp
->pdev
,
12789 tp
->pm_cap
+ PCI_PM_CTRL
,
12791 pm_reg
&= ~PCI_PM_CTRL_STATE_MASK
;
12792 pm_reg
|= PCI_PM_CTRL_PME_ENABLE
| 0 /* D0 */;
12793 pci_write_config_dword(tp
->pdev
,
12794 tp
->pm_cap
+ PCI_PM_CTRL
,
12797 /* Also, force SERR#/PERR# in PCI command. */
12798 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
12799 pci_cmd
|= PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
;
12800 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
12804 if ((pci_state_reg
& PCISTATE_BUS_SPEED_HIGH
) != 0)
12805 tp
->tg3_flags
|= TG3_FLAG_PCI_HIGH_SPEED
;
12806 if ((pci_state_reg
& PCISTATE_BUS_32BIT
) != 0)
12807 tp
->tg3_flags
|= TG3_FLAG_PCI_32BIT
;
12809 /* Chip-specific fixup from Broadcom driver */
12810 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
) &&
12811 (!(pci_state_reg
& PCISTATE_RETRY_SAME_DMA
))) {
12812 pci_state_reg
|= PCISTATE_RETRY_SAME_DMA
;
12813 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, pci_state_reg
);
12816 /* Default fast path register access methods */
12817 tp
->read32
= tg3_read32
;
12818 tp
->write32
= tg3_write32
;
12819 tp
->read32_mbox
= tg3_read32
;
12820 tp
->write32_mbox
= tg3_write32
;
12821 tp
->write32_tx_mbox
= tg3_write32
;
12822 tp
->write32_rx_mbox
= tg3_write32
;
12824 /* Various workaround register access methods */
12825 if (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
)
12826 tp
->write32
= tg3_write_indirect_reg32
;
12827 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
||
12828 ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
12829 tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
)) {
12831 * Back to back register writes can cause problems on these
12832 * chips, the workaround is to read back all reg writes
12833 * except those to mailbox regs.
12835 * See tg3_write_indirect_reg32().
12837 tp
->write32
= tg3_write_flush_reg32
;
12840 if ((tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
) ||
12841 (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)) {
12842 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
12843 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
12844 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
12847 if (tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
) {
12848 tp
->read32
= tg3_read_indirect_reg32
;
12849 tp
->write32
= tg3_write_indirect_reg32
;
12850 tp
->read32_mbox
= tg3_read_indirect_mbox
;
12851 tp
->write32_mbox
= tg3_write_indirect_mbox
;
12852 tp
->write32_tx_mbox
= tg3_write_indirect_mbox
;
12853 tp
->write32_rx_mbox
= tg3_write_indirect_mbox
;
12858 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
12859 pci_cmd
&= ~PCI_COMMAND_MEMORY
;
12860 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
12862 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
12863 tp
->read32_mbox
= tg3_read32_mbox_5906
;
12864 tp
->write32_mbox
= tg3_write32_mbox_5906
;
12865 tp
->write32_tx_mbox
= tg3_write32_mbox_5906
;
12866 tp
->write32_rx_mbox
= tg3_write32_mbox_5906
;
12869 if (tp
->write32
== tg3_write_indirect_reg32
||
12870 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
12871 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
12872 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)))
12873 tp
->tg3_flags
|= TG3_FLAG_SRAM_USE_CONFIG
;
12875 /* Get eeprom hw config before calling tg3_set_power_state().
12876 * In particular, the TG3_FLG2_IS_NIC flag must be
12877 * determined before calling tg3_set_power_state() so that
12878 * we know whether or not to switch out of Vaux power.
12879 * When the flag is set, it means that GPIO1 is used for eeprom
12880 * write protect and also implies that it is a LOM where GPIOs
12881 * are not used to switch power.
12883 tg3_get_eeprom_hw_cfg(tp
);
12885 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
12886 /* Allow reads and writes to the
12887 * APE register and memory space.
12889 pci_state_reg
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
12890 PCISTATE_ALLOW_APE_SHMEM_WR
;
12891 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
12895 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
12896 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
12897 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
12898 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
12899 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
)
12900 tp
->tg3_flags
|= TG3_FLAG_CPMU_PRESENT
;
12902 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12903 * GPIO1 driven high will bring 5700's external PHY out of reset.
12904 * It is also used as eeprom write protect on LOMs.
12906 tp
->grc_local_ctrl
= GRC_LCLCTRL_INT_ON_ATTN
| GRC_LCLCTRL_AUTO_SEEPROM
;
12907 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
12908 (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
))
12909 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
12910 GRC_LCLCTRL_GPIO_OUTPUT1
);
12911 /* Unused GPIO3 must be driven as output on 5752 because there
12912 * are no pull-up resistors on unused GPIO pins.
12914 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
12915 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
12917 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
12918 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
12919 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
12921 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
12922 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
) {
12923 /* Turn off the debug UART. */
12924 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
12925 if (tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)
12926 /* Keep VMain power. */
12927 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
12928 GRC_LCLCTRL_GPIO_OUTPUT0
;
12931 /* Force the chip into D0. */
12932 err
= tg3_set_power_state(tp
, PCI_D0
);
12934 printk(KERN_ERR PFX
"(%s) transition to D0 failed\n",
12935 pci_name(tp
->pdev
));
12939 /* Derive initial jumbo mode from MTU assigned in
12940 * ether_setup() via the alloc_etherdev() call
12942 if (tp
->dev
->mtu
> ETH_DATA_LEN
&&
12943 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
12944 tp
->tg3_flags
|= TG3_FLAG_JUMBO_RING_ENABLE
;
12946 /* Determine WakeOnLan speed to use. */
12947 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
12948 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
12949 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
||
12950 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B2
) {
12951 tp
->tg3_flags
&= ~(TG3_FLAG_WOL_SPEED_100MB
);
12953 tp
->tg3_flags
|= TG3_FLAG_WOL_SPEED_100MB
;
12956 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
12957 tp
->tg3_flags3
|= TG3_FLG3_PHY_IS_FET
;
12959 /* A few boards don't want Ethernet@WireSpeed phy feature */
12960 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
12961 ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
12962 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) &&
12963 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A1
)) ||
12964 (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) ||
12965 (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
))
12966 tp
->tg3_flags2
|= TG3_FLG2_NO_ETH_WIRE_SPEED
;
12968 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5703_AX
||
12969 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_AX
)
12970 tp
->tg3_flags2
|= TG3_FLG2_PHY_ADC_BUG
;
12971 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
)
12972 tp
->tg3_flags2
|= TG3_FLG2_PHY_5704_A0_BUG
;
12974 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
12975 !(tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) &&
12976 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
12977 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_57780
&&
12978 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5717
) {
12979 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
12980 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
12981 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
12982 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
) {
12983 if (tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5756
&&
12984 tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5722
)
12985 tp
->tg3_flags2
|= TG3_FLG2_PHY_JITTER_BUG
;
12986 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5755M
)
12987 tp
->tg3_flags2
|= TG3_FLG2_PHY_ADJUST_TRIM
;
12989 tp
->tg3_flags2
|= TG3_FLG2_PHY_BER_BUG
;
12992 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
12993 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) {
12994 tp
->phy_otp
= tg3_read_otp_phycfg(tp
);
12995 if (tp
->phy_otp
== 0)
12996 tp
->phy_otp
= TG3_OTP_DEFAULT
;
12999 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
)
13000 tp
->mi_mode
= MAC_MI_MODE_500KHZ_CONST
;
13002 tp
->mi_mode
= MAC_MI_MODE_BASE
;
13004 tp
->coalesce_mode
= 0;
13005 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_AX
&&
13006 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_BX
)
13007 tp
->coalesce_mode
|= HOSTCC_MODE_32BYTE
;
13009 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
13010 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
13011 tp
->tg3_flags3
|= TG3_FLG3_USE_PHYLIB
;
13013 err
= tg3_mdio_init(tp
);
13017 /* Initialize data/descriptor byte/word swapping. */
13018 val
= tr32(GRC_MODE
);
13019 val
&= GRC_MODE_HOST_STACKUP
;
13020 tw32(GRC_MODE
, val
| tp
->grc_mode
);
13022 tg3_switch_clocks(tp
);
13024 /* Clear this out for sanity. */
13025 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
13027 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
13029 if ((pci_state_reg
& PCISTATE_CONV_PCI_MODE
) == 0 &&
13030 (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) == 0) {
13031 u32 chiprevid
= GET_CHIP_REV_ID(tp
->misc_host_ctrl
);
13033 if (chiprevid
== CHIPREV_ID_5701_A0
||
13034 chiprevid
== CHIPREV_ID_5701_B0
||
13035 chiprevid
== CHIPREV_ID_5701_B2
||
13036 chiprevid
== CHIPREV_ID_5701_B5
) {
13037 void __iomem
*sram_base
;
13039 /* Write some dummy words into the SRAM status block
13040 * area, see if it reads back correctly. If the return
13041 * value is bad, force enable the PCIX workaround.
13043 sram_base
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_STATS_BLK
;
13045 writel(0x00000000, sram_base
);
13046 writel(0x00000000, sram_base
+ 4);
13047 writel(0xffffffff, sram_base
+ 4);
13048 if (readl(sram_base
) != 0x00000000)
13049 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
13054 tg3_nvram_init(tp
);
13056 grc_misc_cfg
= tr32(GRC_MISC_CFG
);
13057 grc_misc_cfg
&= GRC_MISC_CFG_BOARD_ID_MASK
;
13059 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
13060 (grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788
||
13061 grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788M
))
13062 tp
->tg3_flags2
|= TG3_FLG2_IS_5788
;
13064 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
13065 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
))
13066 tp
->tg3_flags
|= TG3_FLAG_TAGGED_STATUS
;
13067 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
13068 tp
->coalesce_mode
|= (HOSTCC_MODE_CLRTICK_RXBD
|
13069 HOSTCC_MODE_CLRTICK_TXBD
);
13071 tp
->misc_host_ctrl
|= MISC_HOST_CTRL_TAGGED_STATUS
;
13072 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
13073 tp
->misc_host_ctrl
);
13076 /* Preserve the APE MAC_MODE bits */
13077 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
13078 tp
->mac_mode
= tr32(MAC_MODE
) |
13079 MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
13081 tp
->mac_mode
= TG3_DEF_MAC_MODE
;
13083 /* these are limited to 10/100 only */
13084 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
13085 (grc_misc_cfg
== 0x8000 || grc_misc_cfg
== 0x4000)) ||
13086 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
13087 tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
13088 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901
||
13089 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901_2
||
13090 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5705F
)) ||
13091 (tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
13092 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5751F
||
13093 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5753F
||
13094 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5787F
)) ||
13095 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57790
||
13096 (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
))
13097 tp
->tg3_flags
|= TG3_FLAG_10_100_ONLY
;
13099 err
= tg3_phy_probe(tp
);
13101 printk(KERN_ERR PFX
"(%s) phy probe failed, err %d\n",
13102 pci_name(tp
->pdev
), err
);
13103 /* ... but do not return immediately ... */
13107 tg3_read_partno(tp
);
13108 tg3_read_fw_ver(tp
);
13110 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
13111 tp
->tg3_flags
&= ~TG3_FLAG_USE_MI_INTERRUPT
;
13113 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
13114 tp
->tg3_flags
|= TG3_FLAG_USE_MI_INTERRUPT
;
13116 tp
->tg3_flags
&= ~TG3_FLAG_USE_MI_INTERRUPT
;
13119 /* 5700 {AX,BX} chips have a broken status block link
13120 * change bit implementation, so we must use the
13121 * status register in those cases.
13123 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
13124 tp
->tg3_flags
|= TG3_FLAG_USE_LINKCHG_REG
;
13126 tp
->tg3_flags
&= ~TG3_FLAG_USE_LINKCHG_REG
;
13128 /* The led_ctrl is set during tg3_phy_probe, here we might
13129 * have to force the link status polling mechanism based
13130 * upon subsystem IDs.
13132 if (tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
&&
13133 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
13134 !(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
13135 tp
->tg3_flags
|= (TG3_FLAG_USE_MI_INTERRUPT
|
13136 TG3_FLAG_USE_LINKCHG_REG
);
13139 /* For all SERDES we poll the MAC status register. */
13140 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
13141 tp
->tg3_flags
|= TG3_FLAG_POLL_SERDES
;
13143 tp
->tg3_flags
&= ~TG3_FLAG_POLL_SERDES
;
13145 tp
->rx_offset
= NET_IP_ALIGN
;
13146 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
13147 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) != 0)
13150 tp
->rx_std_max_post
= TG3_RX_RING_SIZE
;
13152 /* Increment the rx prod index on the rx std ring by at most
13153 * 8 for these chips to workaround hw errata.
13155 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
13156 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
13157 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
13158 tp
->rx_std_max_post
= 8;
13160 if (tp
->tg3_flags
& TG3_FLAG_ASPM_WORKAROUND
)
13161 tp
->pwrmgmt_thresh
= tr32(PCIE_PWR_MGMT_THRESH
) &
13162 PCIE_PWR_MGMT_L1_THRESH_MSK
;
13167 #ifdef CONFIG_SPARC
13168 static int __devinit
tg3_get_macaddr_sparc(struct tg3
*tp
)
13170 struct net_device
*dev
= tp
->dev
;
13171 struct pci_dev
*pdev
= tp
->pdev
;
13172 struct device_node
*dp
= pci_device_to_OF_node(pdev
);
13173 const unsigned char *addr
;
13176 addr
= of_get_property(dp
, "local-mac-address", &len
);
13177 if (addr
&& len
== 6) {
13178 memcpy(dev
->dev_addr
, addr
, 6);
13179 memcpy(dev
->perm_addr
, dev
->dev_addr
, 6);
13185 static int __devinit
tg3_get_default_macaddr_sparc(struct tg3
*tp
)
13187 struct net_device
*dev
= tp
->dev
;
13189 memcpy(dev
->dev_addr
, idprom
->id_ethaddr
, 6);
13190 memcpy(dev
->perm_addr
, idprom
->id_ethaddr
, 6);
13195 static int __devinit
tg3_get_device_address(struct tg3
*tp
)
13197 struct net_device
*dev
= tp
->dev
;
13198 u32 hi
, lo
, mac_offset
;
13201 #ifdef CONFIG_SPARC
13202 if (!tg3_get_macaddr_sparc(tp
))
13207 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) ||
13208 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
13209 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
13211 if (tg3_nvram_lock(tp
))
13212 tw32_f(NVRAM_CMD
, NVRAM_CMD_RESET
);
13214 tg3_nvram_unlock(tp
);
13215 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
) {
13216 if (tr32(TG3_CPMU_STATUS
) & TG3_CPMU_STATUS_PCIE_FUNC
)
13218 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13221 /* First try to get it from MAC address mailbox. */
13222 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_HIGH_MBOX
, &hi
);
13223 if ((hi
>> 16) == 0x484b) {
13224 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
13225 dev
->dev_addr
[1] = (hi
>> 0) & 0xff;
13227 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_LOW_MBOX
, &lo
);
13228 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
13229 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
13230 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
13231 dev
->dev_addr
[5] = (lo
>> 0) & 0xff;
13233 /* Some old bootcode may report a 0 MAC address in SRAM */
13234 addr_ok
= is_valid_ether_addr(&dev
->dev_addr
[0]);
13237 /* Next, try NVRAM. */
13238 if (!(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) &&
13239 !tg3_nvram_read_be32(tp
, mac_offset
+ 0, &hi
) &&
13240 !tg3_nvram_read_be32(tp
, mac_offset
+ 4, &lo
)) {
13241 memcpy(&dev
->dev_addr
[0], ((char *)&hi
) + 2, 2);
13242 memcpy(&dev
->dev_addr
[2], (char *)&lo
, sizeof(lo
));
13244 /* Finally just fetch it out of the MAC control regs. */
13246 hi
= tr32(MAC_ADDR_0_HIGH
);
13247 lo
= tr32(MAC_ADDR_0_LOW
);
13249 dev
->dev_addr
[5] = lo
& 0xff;
13250 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
13251 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
13252 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
13253 dev
->dev_addr
[1] = hi
& 0xff;
13254 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
13258 if (!is_valid_ether_addr(&dev
->dev_addr
[0])) {
13259 #ifdef CONFIG_SPARC
13260 if (!tg3_get_default_macaddr_sparc(tp
))
13265 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
13269 #define BOUNDARY_SINGLE_CACHELINE 1
13270 #define BOUNDARY_MULTI_CACHELINE 2
13272 static u32 __devinit
tg3_calc_dma_bndry(struct tg3
*tp
, u32 val
)
13274 int cacheline_size
;
13278 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
, &byte
);
13280 cacheline_size
= 1024;
13282 cacheline_size
= (int) byte
* 4;
13284 /* On 5703 and later chips, the boundary bits have no
13287 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
13288 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
&&
13289 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
13292 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13293 goal
= BOUNDARY_MULTI_CACHELINE
;
13295 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13296 goal
= BOUNDARY_SINGLE_CACHELINE
;
13305 /* PCI controllers on most RISC systems tend to disconnect
13306 * when a device tries to burst across a cache-line boundary.
13307 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13309 * Unfortunately, for PCI-E there are only limited
13310 * write-side controls for this, and thus for reads
13311 * we will still get the disconnects. We'll also waste
13312 * these PCI cycles for both read and write for chips
13313 * other than 5700 and 5701 which do not implement the
13316 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
13317 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
13318 switch (cacheline_size
) {
13323 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13324 val
|= (DMA_RWCTRL_READ_BNDRY_128_PCIX
|
13325 DMA_RWCTRL_WRITE_BNDRY_128_PCIX
);
13327 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
13328 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
13333 val
|= (DMA_RWCTRL_READ_BNDRY_256_PCIX
|
13334 DMA_RWCTRL_WRITE_BNDRY_256_PCIX
);
13338 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
13339 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
13342 } else if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
13343 switch (cacheline_size
) {
13347 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13348 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
13349 val
|= DMA_RWCTRL_WRITE_BNDRY_64_PCIE
;
13355 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
13356 val
|= DMA_RWCTRL_WRITE_BNDRY_128_PCIE
;
13360 switch (cacheline_size
) {
13362 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13363 val
|= (DMA_RWCTRL_READ_BNDRY_16
|
13364 DMA_RWCTRL_WRITE_BNDRY_16
);
13369 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13370 val
|= (DMA_RWCTRL_READ_BNDRY_32
|
13371 DMA_RWCTRL_WRITE_BNDRY_32
);
13376 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13377 val
|= (DMA_RWCTRL_READ_BNDRY_64
|
13378 DMA_RWCTRL_WRITE_BNDRY_64
);
13383 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13384 val
|= (DMA_RWCTRL_READ_BNDRY_128
|
13385 DMA_RWCTRL_WRITE_BNDRY_128
);
13390 val
|= (DMA_RWCTRL_READ_BNDRY_256
|
13391 DMA_RWCTRL_WRITE_BNDRY_256
);
13394 val
|= (DMA_RWCTRL_READ_BNDRY_512
|
13395 DMA_RWCTRL_WRITE_BNDRY_512
);
13399 val
|= (DMA_RWCTRL_READ_BNDRY_1024
|
13400 DMA_RWCTRL_WRITE_BNDRY_1024
);
13409 static int __devinit
tg3_do_test_dma(struct tg3
*tp
, u32
*buf
, dma_addr_t buf_dma
, int size
, int to_device
)
13411 struct tg3_internal_buffer_desc test_desc
;
13412 u32 sram_dma_descs
;
13415 sram_dma_descs
= NIC_SRAM_DMA_DESC_POOL_BASE
;
13417 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
, 0);
13418 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
, 0);
13419 tw32(RDMAC_STATUS
, 0);
13420 tw32(WDMAC_STATUS
, 0);
13422 tw32(BUFMGR_MODE
, 0);
13423 tw32(FTQ_RESET
, 0);
13425 test_desc
.addr_hi
= ((u64
) buf_dma
) >> 32;
13426 test_desc
.addr_lo
= buf_dma
& 0xffffffff;
13427 test_desc
.nic_mbuf
= 0x00002100;
13428 test_desc
.len
= size
;
13431 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13432 * the *second* time the tg3 driver was getting loaded after an
13435 * Broadcom tells me:
13436 * ...the DMA engine is connected to the GRC block and a DMA
13437 * reset may affect the GRC block in some unpredictable way...
13438 * The behavior of resets to individual blocks has not been tested.
13440 * Broadcom noted the GRC reset will also reset all sub-components.
13443 test_desc
.cqid_sqid
= (13 << 8) | 2;
13445 tw32_f(RDMAC_MODE
, RDMAC_MODE_ENABLE
);
13448 test_desc
.cqid_sqid
= (16 << 8) | 7;
13450 tw32_f(WDMAC_MODE
, WDMAC_MODE_ENABLE
);
13453 test_desc
.flags
= 0x00000005;
13455 for (i
= 0; i
< (sizeof(test_desc
) / sizeof(u32
)); i
++) {
13458 val
= *(((u32
*)&test_desc
) + i
);
13459 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
,
13460 sram_dma_descs
+ (i
* sizeof(u32
)));
13461 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
13463 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
13466 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ
, sram_dma_descs
);
13468 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ
, sram_dma_descs
);
13472 for (i
= 0; i
< 40; i
++) {
13476 val
= tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
);
13478 val
= tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
);
13479 if ((val
& 0xffff) == sram_dma_descs
) {
13490 #define TEST_BUFFER_SIZE 0x2000
13492 static int __devinit
tg3_test_dma(struct tg3
*tp
)
13494 dma_addr_t buf_dma
;
13495 u32
*buf
, saved_dma_rwctrl
;
13498 buf
= pci_alloc_consistent(tp
->pdev
, TEST_BUFFER_SIZE
, &buf_dma
);
13504 tp
->dma_rwctrl
= ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT
) |
13505 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT
));
13507 tp
->dma_rwctrl
= tg3_calc_dma_bndry(tp
, tp
->dma_rwctrl
);
13509 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
13510 /* DMA read watermark not used on PCIE */
13511 tp
->dma_rwctrl
|= 0x00180000;
13512 } else if (!(tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
13513 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
||
13514 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)
13515 tp
->dma_rwctrl
|= 0x003f0000;
13517 tp
->dma_rwctrl
|= 0x003f000f;
13519 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
13520 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
13521 u32 ccval
= (tr32(TG3PCI_CLOCK_CTRL
) & 0x1f);
13522 u32 read_water
= 0x7;
13524 /* If the 5704 is behind the EPB bridge, we can
13525 * do the less restrictive ONE_DMA workaround for
13526 * better performance.
13528 if ((tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
) &&
13529 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
13530 tp
->dma_rwctrl
|= 0x8000;
13531 else if (ccval
== 0x6 || ccval
== 0x7)
13532 tp
->dma_rwctrl
|= DMA_RWCTRL_ONE_DMA
;
13534 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
)
13536 /* Set bit 23 to enable PCIX hw bug fix */
13538 (read_water
<< DMA_RWCTRL_READ_WATER_SHIFT
) |
13539 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT
) |
13541 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
) {
13542 /* 5780 always in PCIX mode */
13543 tp
->dma_rwctrl
|= 0x00144000;
13544 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
13545 /* 5714 always in PCIX mode */
13546 tp
->dma_rwctrl
|= 0x00148000;
13548 tp
->dma_rwctrl
|= 0x001b000f;
13552 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
13553 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
13554 tp
->dma_rwctrl
&= 0xfffffff0;
13556 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
13557 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
13558 /* Remove this if it causes problems for some boards. */
13559 tp
->dma_rwctrl
|= DMA_RWCTRL_USE_MEM_READ_MULT
;
13561 /* On 5700/5701 chips, we need to set this bit.
13562 * Otherwise the chip will issue cacheline transactions
13563 * to streamable DMA memory with not all the byte
13564 * enables turned on. This is an error on several
13565 * RISC PCI controllers, in particular sparc64.
13567 * On 5703/5704 chips, this bit has been reassigned
13568 * a different meaning. In particular, it is used
13569 * on those chips to enable a PCI-X workaround.
13571 tp
->dma_rwctrl
|= DMA_RWCTRL_ASSERT_ALL_BE
;
13574 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
13577 /* Unneeded, already done by tg3_get_invariants. */
13578 tg3_switch_clocks(tp
);
13582 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
13583 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
13586 /* It is best to perform DMA test with maximum write burst size
13587 * to expose the 5700/5701 write DMA bug.
13589 saved_dma_rwctrl
= tp
->dma_rwctrl
;
13590 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
13591 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
13596 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++)
13599 /* Send the buffer to the chip. */
13600 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 1);
13602 printk(KERN_ERR
"tg3_test_dma() Write the buffer failed %d\n", ret
);
13607 /* validate data reached card RAM correctly. */
13608 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
13610 tg3_read_mem(tp
, 0x2100 + (i
*4), &val
);
13611 if (le32_to_cpu(val
) != p
[i
]) {
13612 printk(KERN_ERR
" tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val
, i
);
13613 /* ret = -ENODEV here? */
13618 /* Now read it back. */
13619 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 0);
13621 printk(KERN_ERR
"tg3_test_dma() Read the buffer failed %d\n", ret
);
13627 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
13631 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
13632 DMA_RWCTRL_WRITE_BNDRY_16
) {
13633 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
13634 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
13635 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
13638 printk(KERN_ERR
"tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p
[i
], i
);
13644 if (i
== (TEST_BUFFER_SIZE
/ sizeof(u32
))) {
13650 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
13651 DMA_RWCTRL_WRITE_BNDRY_16
) {
13652 static struct pci_device_id dma_wait_state_chipsets
[] = {
13653 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
,
13654 PCI_DEVICE_ID_APPLE_UNI_N_PCI15
) },
13658 /* DMA test passed without adjusting DMA boundary,
13659 * now look for chipsets that are known to expose the
13660 * DMA bug without failing the test.
13662 if (pci_dev_present(dma_wait_state_chipsets
)) {
13663 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
13664 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
13667 /* Safe to use the calculated DMA boundary. */
13668 tp
->dma_rwctrl
= saved_dma_rwctrl
;
13670 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
13674 pci_free_consistent(tp
->pdev
, TEST_BUFFER_SIZE
, buf
, buf_dma
);
13679 static void __devinit
tg3_init_link_config(struct tg3
*tp
)
13681 tp
->link_config
.advertising
=
13682 (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
13683 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
13684 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
|
13685 ADVERTISED_Autoneg
| ADVERTISED_MII
);
13686 tp
->link_config
.speed
= SPEED_INVALID
;
13687 tp
->link_config
.duplex
= DUPLEX_INVALID
;
13688 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
13689 tp
->link_config
.active_speed
= SPEED_INVALID
;
13690 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
13691 tp
->link_config
.phy_is_low_power
= 0;
13692 tp
->link_config
.orig_speed
= SPEED_INVALID
;
13693 tp
->link_config
.orig_duplex
= DUPLEX_INVALID
;
13694 tp
->link_config
.orig_autoneg
= AUTONEG_INVALID
;
13697 static void __devinit
tg3_init_bufmgr_config(struct tg3
*tp
)
13699 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
&&
13700 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5717
) {
13701 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
13702 DEFAULT_MB_RDMA_LOW_WATER_5705
;
13703 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
13704 DEFAULT_MB_MACRX_LOW_WATER_5705
;
13705 tp
->bufmgr_config
.mbuf_high_water
=
13706 DEFAULT_MB_HIGH_WATER_5705
;
13707 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
13708 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
13709 DEFAULT_MB_MACRX_LOW_WATER_5906
;
13710 tp
->bufmgr_config
.mbuf_high_water
=
13711 DEFAULT_MB_HIGH_WATER_5906
;
13714 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
13715 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780
;
13716 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
13717 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780
;
13718 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
13719 DEFAULT_MB_HIGH_WATER_JUMBO_5780
;
13721 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
13722 DEFAULT_MB_RDMA_LOW_WATER
;
13723 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
13724 DEFAULT_MB_MACRX_LOW_WATER
;
13725 tp
->bufmgr_config
.mbuf_high_water
=
13726 DEFAULT_MB_HIGH_WATER
;
13728 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
13729 DEFAULT_MB_RDMA_LOW_WATER_JUMBO
;
13730 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
13731 DEFAULT_MB_MACRX_LOW_WATER_JUMBO
;
13732 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
13733 DEFAULT_MB_HIGH_WATER_JUMBO
;
13736 tp
->bufmgr_config
.dma_low_water
= DEFAULT_DMA_LOW_WATER
;
13737 tp
->bufmgr_config
.dma_high_water
= DEFAULT_DMA_HIGH_WATER
;
13740 static char * __devinit
tg3_phy_string(struct tg3
*tp
)
13742 switch (tp
->phy_id
& PHY_ID_MASK
) {
13743 case PHY_ID_BCM5400
: return "5400";
13744 case PHY_ID_BCM5401
: return "5401";
13745 case PHY_ID_BCM5411
: return "5411";
13746 case PHY_ID_BCM5701
: return "5701";
13747 case PHY_ID_BCM5703
: return "5703";
13748 case PHY_ID_BCM5704
: return "5704";
13749 case PHY_ID_BCM5705
: return "5705";
13750 case PHY_ID_BCM5750
: return "5750";
13751 case PHY_ID_BCM5752
: return "5752";
13752 case PHY_ID_BCM5714
: return "5714";
13753 case PHY_ID_BCM5780
: return "5780";
13754 case PHY_ID_BCM5755
: return "5755";
13755 case PHY_ID_BCM5787
: return "5787";
13756 case PHY_ID_BCM5784
: return "5784";
13757 case PHY_ID_BCM5756
: return "5722/5756";
13758 case PHY_ID_BCM5906
: return "5906";
13759 case PHY_ID_BCM5761
: return "5761";
13760 case PHY_ID_BCM5717
: return "5717";
13761 case PHY_ID_BCM8002
: return "8002/serdes";
13762 case 0: return "serdes";
13763 default: return "unknown";
13767 static char * __devinit
tg3_bus_string(struct tg3
*tp
, char *str
)
13769 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
13770 strcpy(str
, "PCI Express");
13772 } else if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
13773 u32 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
) & 0x1f;
13775 strcpy(str
, "PCIX:");
13777 if ((clock_ctrl
== 7) ||
13778 ((tr32(GRC_MISC_CFG
) & GRC_MISC_CFG_BOARD_ID_MASK
) ==
13779 GRC_MISC_CFG_BOARD_ID_5704CIOBE
))
13780 strcat(str
, "133MHz");
13781 else if (clock_ctrl
== 0)
13782 strcat(str
, "33MHz");
13783 else if (clock_ctrl
== 2)
13784 strcat(str
, "50MHz");
13785 else if (clock_ctrl
== 4)
13786 strcat(str
, "66MHz");
13787 else if (clock_ctrl
== 6)
13788 strcat(str
, "100MHz");
13790 strcpy(str
, "PCI:");
13791 if (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
)
13792 strcat(str
, "66MHz");
13794 strcat(str
, "33MHz");
13796 if (tp
->tg3_flags
& TG3_FLAG_PCI_32BIT
)
13797 strcat(str
, ":32-bit");
13799 strcat(str
, ":64-bit");
13803 static struct pci_dev
* __devinit
tg3_find_peer(struct tg3
*tp
)
13805 struct pci_dev
*peer
;
13806 unsigned int func
, devnr
= tp
->pdev
->devfn
& ~7;
13808 for (func
= 0; func
< 8; func
++) {
13809 peer
= pci_get_slot(tp
->pdev
->bus
, devnr
| func
);
13810 if (peer
&& peer
!= tp
->pdev
)
13814 /* 5704 can be configured in single-port mode, set peer to
13815 * tp->pdev in that case.
13823 * We don't need to keep the refcount elevated; there's no way
13824 * to remove one half of this device without removing the other
13831 static void __devinit
tg3_init_coal(struct tg3
*tp
)
13833 struct ethtool_coalesce
*ec
= &tp
->coal
;
13835 memset(ec
, 0, sizeof(*ec
));
13836 ec
->cmd
= ETHTOOL_GCOALESCE
;
13837 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS
;
13838 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS
;
13839 ec
->rx_max_coalesced_frames
= LOW_RXMAX_FRAMES
;
13840 ec
->tx_max_coalesced_frames
= LOW_TXMAX_FRAMES
;
13841 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT
;
13842 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT
;
13843 ec
->rx_max_coalesced_frames_irq
= DEFAULT_RXCOAL_MAXF_INT
;
13844 ec
->tx_max_coalesced_frames_irq
= DEFAULT_TXCOAL_MAXF_INT
;
13845 ec
->stats_block_coalesce_usecs
= DEFAULT_STAT_COAL_TICKS
;
13847 if (tp
->coalesce_mode
& (HOSTCC_MODE_CLRTICK_RXBD
|
13848 HOSTCC_MODE_CLRTICK_TXBD
)) {
13849 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS_CLRTCKS
;
13850 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT_CLRTCKS
;
13851 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS_CLRTCKS
;
13852 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT_CLRTCKS
;
13855 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
13856 ec
->rx_coalesce_usecs_irq
= 0;
13857 ec
->tx_coalesce_usecs_irq
= 0;
13858 ec
->stats_block_coalesce_usecs
= 0;
13862 static const struct net_device_ops tg3_netdev_ops
= {
13863 .ndo_open
= tg3_open
,
13864 .ndo_stop
= tg3_close
,
13865 .ndo_start_xmit
= tg3_start_xmit
,
13866 .ndo_get_stats
= tg3_get_stats
,
13867 .ndo_validate_addr
= eth_validate_addr
,
13868 .ndo_set_multicast_list
= tg3_set_rx_mode
,
13869 .ndo_set_mac_address
= tg3_set_mac_addr
,
13870 .ndo_do_ioctl
= tg3_ioctl
,
13871 .ndo_tx_timeout
= tg3_tx_timeout
,
13872 .ndo_change_mtu
= tg3_change_mtu
,
13873 #if TG3_VLAN_TAG_USED
13874 .ndo_vlan_rx_register
= tg3_vlan_rx_register
,
13876 #ifdef CONFIG_NET_POLL_CONTROLLER
13877 .ndo_poll_controller
= tg3_poll_controller
,
13881 static const struct net_device_ops tg3_netdev_ops_dma_bug
= {
13882 .ndo_open
= tg3_open
,
13883 .ndo_stop
= tg3_close
,
13884 .ndo_start_xmit
= tg3_start_xmit_dma_bug
,
13885 .ndo_get_stats
= tg3_get_stats
,
13886 .ndo_validate_addr
= eth_validate_addr
,
13887 .ndo_set_multicast_list
= tg3_set_rx_mode
,
13888 .ndo_set_mac_address
= tg3_set_mac_addr
,
13889 .ndo_do_ioctl
= tg3_ioctl
,
13890 .ndo_tx_timeout
= tg3_tx_timeout
,
13891 .ndo_change_mtu
= tg3_change_mtu
,
13892 #if TG3_VLAN_TAG_USED
13893 .ndo_vlan_rx_register
= tg3_vlan_rx_register
,
13895 #ifdef CONFIG_NET_POLL_CONTROLLER
13896 .ndo_poll_controller
= tg3_poll_controller
,
13900 static int __devinit
tg3_init_one(struct pci_dev
*pdev
,
13901 const struct pci_device_id
*ent
)
13903 static int tg3_version_printed
= 0;
13904 struct net_device
*dev
;
13906 int i
, err
, pm_cap
;
13907 u32 sndmbx
, rcvmbx
, intmbx
;
13909 u64 dma_mask
, persist_dma_mask
;
13911 if (tg3_version_printed
++ == 0)
13912 printk(KERN_INFO
"%s", version
);
13914 err
= pci_enable_device(pdev
);
13916 printk(KERN_ERR PFX
"Cannot enable PCI device, "
13921 err
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
13923 printk(KERN_ERR PFX
"Cannot obtain PCI resources, "
13925 goto err_out_disable_pdev
;
13928 pci_set_master(pdev
);
13930 /* Find power-management capability. */
13931 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
13933 printk(KERN_ERR PFX
"Cannot find PowerManagement capability, "
13936 goto err_out_free_res
;
13939 dev
= alloc_etherdev_mq(sizeof(*tp
), TG3_IRQ_MAX_VECS
);
13941 printk(KERN_ERR PFX
"Etherdev alloc failed, aborting.\n");
13943 goto err_out_free_res
;
13946 SET_NETDEV_DEV(dev
, &pdev
->dev
);
13948 #if TG3_VLAN_TAG_USED
13949 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
13952 tp
= netdev_priv(dev
);
13955 tp
->pm_cap
= pm_cap
;
13956 tp
->rx_mode
= TG3_DEF_RX_MODE
;
13957 tp
->tx_mode
= TG3_DEF_TX_MODE
;
13960 tp
->msg_enable
= tg3_debug
;
13962 tp
->msg_enable
= TG3_DEF_MSG_ENABLE
;
13964 /* The word/byte swap controls here control register access byte
13965 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13968 tp
->misc_host_ctrl
=
13969 MISC_HOST_CTRL_MASK_PCI_INT
|
13970 MISC_HOST_CTRL_WORD_SWAP
|
13971 MISC_HOST_CTRL_INDIR_ACCESS
|
13972 MISC_HOST_CTRL_PCISTATE_RW
;
13974 /* The NONFRM (non-frame) byte/word swap controls take effect
13975 * on descriptor entries, anything which isn't packet data.
13977 * The StrongARM chips on the board (one for tx, one for rx)
13978 * are running in big-endian mode.
13980 tp
->grc_mode
= (GRC_MODE_WSWAP_DATA
| GRC_MODE_BSWAP_DATA
|
13981 GRC_MODE_WSWAP_NONFRM_DATA
);
13982 #ifdef __BIG_ENDIAN
13983 tp
->grc_mode
|= GRC_MODE_BSWAP_NONFRM_DATA
;
13985 spin_lock_init(&tp
->lock
);
13986 spin_lock_init(&tp
->indirect_lock
);
13987 INIT_WORK(&tp
->reset_task
, tg3_reset_task
);
13989 tp
->regs
= pci_ioremap_bar(pdev
, BAR_0
);
13991 printk(KERN_ERR PFX
"Cannot map device registers, "
13994 goto err_out_free_dev
;
13997 tg3_init_link_config(tp
);
13999 tp
->rx_pending
= TG3_DEF_RX_RING_PENDING
;
14000 tp
->rx_jumbo_pending
= TG3_DEF_RX_JUMBO_RING_PENDING
;
14002 intmbx
= MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
;
14003 rcvmbx
= MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
;
14004 sndmbx
= MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
;
14005 for (i
= 0; i
< TG3_IRQ_MAX_VECS
; i
++) {
14006 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
14009 tnapi
->tx_pending
= TG3_DEF_TX_RING_PENDING
;
14011 tnapi
->int_mbox
= intmbx
;
14017 tnapi
->consmbox
= rcvmbx
;
14018 tnapi
->prodmbox
= sndmbx
;
14021 tnapi
->coal_now
= HOSTCC_MODE_COAL_VEC1_NOW
<< (i
- 1);
14023 tnapi
->coal_now
= HOSTCC_MODE_NOW
;
14025 if (!(tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
))
14029 * If we support MSIX, we'll be using RSS. If we're using
14030 * RSS, the first vector only handles link interrupts and the
14031 * remaining vectors handle rx and tx interrupts. Reuse the
14032 * mailbox values for the next iteration. The values we setup
14033 * above are still useful for the single vectored mode.
14046 netif_napi_add(dev
, &tp
->napi
[0].napi
, tg3_poll
, 64);
14047 dev
->ethtool_ops
= &tg3_ethtool_ops
;
14048 dev
->watchdog_timeo
= TG3_TX_TIMEOUT
;
14049 dev
->irq
= pdev
->irq
;
14051 err
= tg3_get_invariants(tp
);
14053 printk(KERN_ERR PFX
"Problem fetching invariants of chip, "
14055 goto err_out_iounmap
;
14058 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
14059 dev
->netdev_ops
= &tg3_netdev_ops
;
14061 dev
->netdev_ops
= &tg3_netdev_ops_dma_bug
;
14064 /* The EPB bridge inside 5714, 5715, and 5780 and any
14065 * device behind the EPB cannot support DMA addresses > 40-bit.
14066 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14067 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14068 * do DMA address check in tg3_start_xmit().
14070 if (tp
->tg3_flags2
& TG3_FLG2_IS_5788
)
14071 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(32);
14072 else if (tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
) {
14073 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(40);
14074 #ifdef CONFIG_HIGHMEM
14075 dma_mask
= DMA_BIT_MASK(64);
14078 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(64);
14080 /* Configure DMA attributes. */
14081 if (dma_mask
> DMA_BIT_MASK(32)) {
14082 err
= pci_set_dma_mask(pdev
, dma_mask
);
14084 dev
->features
|= NETIF_F_HIGHDMA
;
14085 err
= pci_set_consistent_dma_mask(pdev
,
14088 printk(KERN_ERR PFX
"Unable to obtain 64 bit "
14089 "DMA for consistent allocations\n");
14090 goto err_out_iounmap
;
14094 if (err
|| dma_mask
== DMA_BIT_MASK(32)) {
14095 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
14097 printk(KERN_ERR PFX
"No usable DMA configuration, "
14099 goto err_out_iounmap
;
14103 tg3_init_bufmgr_config(tp
);
14105 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
)
14106 tp
->fw_needed
= FIRMWARE_TG3
;
14108 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
14109 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
14111 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
14112 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
||
14113 tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
||
14114 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
||
14115 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0) {
14116 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
14118 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
| TG3_FLG2_TSO_BUG
;
14119 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
)
14120 tp
->fw_needed
= FIRMWARE_TG3TSO5
;
14122 tp
->fw_needed
= FIRMWARE_TG3TSO
;
14125 /* TSO is on by default on chips that support hardware TSO.
14126 * Firmware TSO on older chips gives lower performance, so it
14127 * is off by default, but can be enabled using ethtool.
14129 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
14130 if (dev
->features
& NETIF_F_IP_CSUM
)
14131 dev
->features
|= NETIF_F_TSO
;
14132 if ((dev
->features
& NETIF_F_IPV6_CSUM
) &&
14133 (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
))
14134 dev
->features
|= NETIF_F_TSO6
;
14135 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
14136 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
14137 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) ||
14138 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
14139 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
14140 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
)
14141 dev
->features
|= NETIF_F_TSO_ECN
;
14145 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
&&
14146 !(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) &&
14147 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
)) {
14148 tp
->tg3_flags2
|= TG3_FLG2_MAX_RXPEND_64
;
14149 tp
->rx_pending
= 63;
14152 err
= tg3_get_device_address(tp
);
14154 printk(KERN_ERR PFX
"Could not obtain valid ethernet address, "
14159 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
14160 tp
->aperegs
= pci_ioremap_bar(pdev
, BAR_2
);
14161 if (!tp
->aperegs
) {
14162 printk(KERN_ERR PFX
"Cannot map APE registers, "
14168 tg3_ape_lock_init(tp
);
14170 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)
14171 tg3_read_dash_ver(tp
);
14175 * Reset chip in case UNDI or EFI driver did not shutdown
14176 * DMA self test will enable WDMAC and we'll see (spurious)
14177 * pending DMA on the PCI bus at that point.
14179 if ((tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
) ||
14180 (tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
14181 tw32(MEMARB_MODE
, MEMARB_MODE_ENABLE
);
14182 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
14185 err
= tg3_test_dma(tp
);
14187 printk(KERN_ERR PFX
"DMA engine test failed, aborting.\n");
14188 goto err_out_apeunmap
;
14191 /* flow control autonegotiation is default behavior */
14192 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
14193 tp
->link_config
.flowctrl
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
14197 pci_set_drvdata(pdev
, dev
);
14199 err
= register_netdev(dev
);
14201 printk(KERN_ERR PFX
"Cannot register net device, "
14203 goto err_out_apeunmap
;
14206 printk(KERN_INFO
"%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14208 tp
->board_part_number
,
14209 tp
->pci_chip_rev_id
,
14210 tg3_bus_string(tp
, str
),
14213 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) {
14214 struct phy_device
*phydev
;
14215 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
14217 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14218 tp
->dev
->name
, phydev
->drv
->name
,
14219 dev_name(&phydev
->dev
));
14222 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14223 tp
->dev
->name
, tg3_phy_string(tp
),
14224 ((tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
) ? "10/100Base-TX" :
14225 ((tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
) ? "1000Base-SX" :
14226 "10/100/1000Base-T")),
14227 (tp
->tg3_flags2
& TG3_FLG2_NO_ETH_WIRE_SPEED
) == 0);
14229 printk(KERN_INFO
"%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14231 (tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) != 0,
14232 (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) != 0,
14233 (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
) != 0,
14234 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0,
14235 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) != 0);
14236 printk(KERN_INFO
"%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14237 dev
->name
, tp
->dma_rwctrl
,
14238 (pdev
->dma_mask
== DMA_BIT_MASK(32)) ? 32 :
14239 (((u64
) pdev
->dma_mask
== DMA_BIT_MASK(40)) ? 40 : 64));
14245 iounmap(tp
->aperegs
);
14246 tp
->aperegs
= NULL
;
14251 release_firmware(tp
->fw
);
14263 pci_release_regions(pdev
);
14265 err_out_disable_pdev
:
14266 pci_disable_device(pdev
);
14267 pci_set_drvdata(pdev
, NULL
);
14271 static void __devexit
tg3_remove_one(struct pci_dev
*pdev
)
14273 struct net_device
*dev
= pci_get_drvdata(pdev
);
14276 struct tg3
*tp
= netdev_priv(dev
);
14279 release_firmware(tp
->fw
);
14281 flush_scheduled_work();
14283 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
14288 unregister_netdev(dev
);
14290 iounmap(tp
->aperegs
);
14291 tp
->aperegs
= NULL
;
14298 pci_release_regions(pdev
);
14299 pci_disable_device(pdev
);
14300 pci_set_drvdata(pdev
, NULL
);
14304 static int tg3_suspend(struct pci_dev
*pdev
, pm_message_t state
)
14306 struct net_device
*dev
= pci_get_drvdata(pdev
);
14307 struct tg3
*tp
= netdev_priv(dev
);
14308 pci_power_t target_state
;
14311 /* PCI register 4 needs to be saved whether netif_running() or not.
14312 * MSI address and data need to be saved if using MSI and
14315 pci_save_state(pdev
);
14317 if (!netif_running(dev
))
14320 flush_scheduled_work();
14322 tg3_netif_stop(tp
);
14324 del_timer_sync(&tp
->timer
);
14326 tg3_full_lock(tp
, 1);
14327 tg3_disable_ints(tp
);
14328 tg3_full_unlock(tp
);
14330 netif_device_detach(dev
);
14332 tg3_full_lock(tp
, 0);
14333 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
14334 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
14335 tg3_full_unlock(tp
);
14337 target_state
= pdev
->pm_cap
? pci_target_state(pdev
) : PCI_D3hot
;
14339 err
= tg3_set_power_state(tp
, target_state
);
14343 tg3_full_lock(tp
, 0);
14345 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
14346 err2
= tg3_restart_hw(tp
, 1);
14350 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
14351 add_timer(&tp
->timer
);
14353 netif_device_attach(dev
);
14354 tg3_netif_start(tp
);
14357 tg3_full_unlock(tp
);
14366 static int tg3_resume(struct pci_dev
*pdev
)
14368 struct net_device
*dev
= pci_get_drvdata(pdev
);
14369 struct tg3
*tp
= netdev_priv(dev
);
14372 pci_restore_state(tp
->pdev
);
14374 if (!netif_running(dev
))
14377 err
= tg3_set_power_state(tp
, PCI_D0
);
14381 netif_device_attach(dev
);
14383 tg3_full_lock(tp
, 0);
14385 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
14386 err
= tg3_restart_hw(tp
, 1);
14390 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
14391 add_timer(&tp
->timer
);
14393 tg3_netif_start(tp
);
14396 tg3_full_unlock(tp
);
14404 static struct pci_driver tg3_driver
= {
14405 .name
= DRV_MODULE_NAME
,
14406 .id_table
= tg3_pci_tbl
,
14407 .probe
= tg3_init_one
,
14408 .remove
= __devexit_p(tg3_remove_one
),
14409 .suspend
= tg3_suspend
,
14410 .resume
= tg3_resume
14413 static int __init
tg3_init(void)
14415 return pci_register_driver(&tg3_driver
);
14418 static void __exit
tg3_cleanup(void)
14420 pci_unregister_driver(&tg3_driver
);
14423 module_init(tg3_init
);
14424 module_exit(tg3_cleanup
);