2 * pxa-ssp.c -- ALSA Soc Audio Layer
4 * Copyright 2005,2008 Wolfson Microelectronics PLC.
5 * Author: Liam Girdwood
6 * Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 * o Test network mode for > 16bit sample size
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/slab.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
26 #include <sound/core.h>
27 #include <sound/pcm.h>
28 #include <sound/initval.h>
29 #include <sound/pcm_params.h>
30 #include <sound/soc.h>
31 #include <sound/pxa2xx-lib.h>
33 #include <mach/hardware.h>
35 #include <mach/regs-ssp.h>
36 #include <mach/audio.h>
39 #include "pxa2xx-pcm.h"
43 * SSP audio private data
46 struct ssp_device
*ssp
;
57 static void dump_registers(struct ssp_device
*ssp
)
59 dev_dbg(&ssp
->pdev
->dev
, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
60 ssp_read_reg(ssp
, SSCR0
), ssp_read_reg(ssp
, SSCR1
),
61 ssp_read_reg(ssp
, SSTO
));
63 dev_dbg(&ssp
->pdev
->dev
, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
64 ssp_read_reg(ssp
, SSPSP
), ssp_read_reg(ssp
, SSSR
),
65 ssp_read_reg(ssp
, SSACD
));
68 static void ssp_enable(struct ssp_device
*ssp
)
72 sscr0
= __raw_readl(ssp
->mmio_base
+ SSCR0
) | SSCR0_SSE
;
73 __raw_writel(sscr0
, ssp
->mmio_base
+ SSCR0
);
76 static void ssp_disable(struct ssp_device
*ssp
)
80 sscr0
= __raw_readl(ssp
->mmio_base
+ SSCR0
) & ~SSCR0_SSE
;
81 __raw_writel(sscr0
, ssp
->mmio_base
+ SSCR0
);
84 struct pxa2xx_pcm_dma_data
{
85 struct pxa2xx_pcm_dma_params params
;
89 static struct pxa2xx_pcm_dma_params
*
90 ssp_get_dma_params(struct ssp_device
*ssp
, int width4
, int out
)
92 struct pxa2xx_pcm_dma_data
*dma
;
94 dma
= kzalloc(sizeof(struct pxa2xx_pcm_dma_data
), GFP_KERNEL
);
98 snprintf(dma
->name
, 20, "SSP%d PCM %s %s", ssp
->port_id
,
99 width4
? "32-bit" : "16-bit", out
? "out" : "in");
101 dma
->params
.name
= dma
->name
;
102 dma
->params
.drcmr
= &DRCMR(out
? ssp
->drcmr_tx
: ssp
->drcmr_rx
);
103 dma
->params
.dcmd
= (out
? (DCMD_INCSRCADDR
| DCMD_FLOWTRG
) :
104 (DCMD_INCTRGADDR
| DCMD_FLOWSRC
)) |
105 (width4
? DCMD_WIDTH4
: DCMD_WIDTH2
) | DCMD_BURST16
;
106 dma
->params
.dev_addr
= ssp
->phys_base
+ SSDR
;
111 static int pxa_ssp_startup(struct snd_pcm_substream
*substream
,
112 struct snd_soc_dai
*dai
)
114 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
115 struct snd_soc_dai
*cpu_dai
= rtd
->dai
->cpu_dai
;
116 struct ssp_priv
*priv
= cpu_dai
->private_data
;
117 struct ssp_device
*ssp
= priv
->ssp
;
120 if (!cpu_dai
->active
) {
121 clk_enable(ssp
->clk
);
125 kfree(snd_soc_dai_get_dma_data(cpu_dai
, substream
));
126 snd_soc_dai_set_dma_data(cpu_dai
, substream
, NULL
);
131 static void pxa_ssp_shutdown(struct snd_pcm_substream
*substream
,
132 struct snd_soc_dai
*dai
)
134 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
135 struct snd_soc_dai
*cpu_dai
= rtd
->dai
->cpu_dai
;
136 struct ssp_priv
*priv
= cpu_dai
->private_data
;
137 struct ssp_device
*ssp
= priv
->ssp
;
139 if (!cpu_dai
->active
) {
141 clk_disable(ssp
->clk
);
144 kfree(snd_soc_dai_get_dma_data(cpu_dai
, substream
));
145 snd_soc_dai_set_dma_data(cpu_dai
, substream
, NULL
);
150 static int pxa_ssp_suspend(struct snd_soc_dai
*cpu_dai
)
152 struct ssp_priv
*priv
= cpu_dai
->private_data
;
153 struct ssp_device
*ssp
= priv
->ssp
;
155 if (!cpu_dai
->active
)
156 clk_enable(ssp
->clk
);
158 priv
->cr0
= __raw_readl(ssp
->mmio_base
+ SSCR0
);
159 priv
->cr1
= __raw_readl(ssp
->mmio_base
+ SSCR1
);
160 priv
->to
= __raw_readl(ssp
->mmio_base
+ SSTO
);
161 priv
->psp
= __raw_readl(ssp
->mmio_base
+ SSPSP
);
164 clk_disable(ssp
->clk
);
168 static int pxa_ssp_resume(struct snd_soc_dai
*cpu_dai
)
170 struct ssp_priv
*priv
= cpu_dai
->private_data
;
171 struct ssp_device
*ssp
= priv
->ssp
;
172 uint32_t sssr
= SSSR_ROR
| SSSR_TUR
| SSSR_BCE
;
174 clk_enable(ssp
->clk
);
176 __raw_writel(sssr
, ssp
->mmio_base
+ SSSR
);
177 __raw_writel(priv
->cr0
& ~SSCR0_SSE
, ssp
->mmio_base
+ SSCR0
);
178 __raw_writel(priv
->cr1
, ssp
->mmio_base
+ SSCR1
);
179 __raw_writel(priv
->to
, ssp
->mmio_base
+ SSTO
);
180 __raw_writel(priv
->psp
, ssp
->mmio_base
+ SSPSP
);
185 clk_disable(ssp
->clk
);
191 #define pxa_ssp_suspend NULL
192 #define pxa_ssp_resume NULL
196 * ssp_set_clkdiv - set SSP clock divider
197 * @div: serial clock rate divider
199 static void ssp_set_scr(struct ssp_device
*ssp
, u32 div
)
201 u32 sscr0
= ssp_read_reg(ssp
, SSCR0
);
203 if (cpu_is_pxa25x() && ssp
->type
== PXA25x_SSP
) {
204 sscr0
&= ~0x0000ff00;
205 sscr0
|= ((div
- 2)/2) << 8; /* 2..512 */
207 sscr0
&= ~0x000fff00;
208 sscr0
|= (div
- 1) << 8; /* 1..4096 */
210 ssp_write_reg(ssp
, SSCR0
, sscr0
);
214 * ssp_get_clkdiv - get SSP clock divider
216 static u32
ssp_get_scr(struct ssp_device
*ssp
)
218 u32 sscr0
= ssp_read_reg(ssp
, SSCR0
);
221 if (cpu_is_pxa25x() && ssp
->type
== PXA25x_SSP
)
222 div
= ((sscr0
>> 8) & 0xff) * 2 + 2;
224 div
= ((sscr0
>> 8) & 0xfff) + 1;
229 * Set the SSP ports SYSCLK.
231 static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai
*cpu_dai
,
232 int clk_id
, unsigned int freq
, int dir
)
234 struct ssp_priv
*priv
= cpu_dai
->private_data
;
235 struct ssp_device
*ssp
= priv
->ssp
;
238 u32 sscr0
= ssp_read_reg(ssp
, SSCR0
) &
239 ~(SSCR0_ECS
| SSCR0_NCS
| SSCR0_MOD
| SSCR0_ACS
);
241 dev_dbg(&ssp
->pdev
->dev
,
242 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n",
243 cpu_dai
->id
, clk_id
, freq
);
246 case PXA_SSP_CLK_NET_PLL
:
249 case PXA_SSP_CLK_PLL
:
250 /* Internal PLL is fixed */
252 priv
->sysclk
= 1843200;
254 priv
->sysclk
= 13000000;
256 case PXA_SSP_CLK_EXT
:
260 case PXA_SSP_CLK_NET
:
262 sscr0
|= SSCR0_NCS
| SSCR0_MOD
;
264 case PXA_SSP_CLK_AUDIO
:
273 /* The SSP clock must be disabled when changing SSP clock mode
274 * on PXA2xx. On PXA3xx it must be enabled when doing so. */
275 if (!cpu_is_pxa3xx())
276 clk_disable(ssp
->clk
);
277 val
= ssp_read_reg(ssp
, SSCR0
) | sscr0
;
278 ssp_write_reg(ssp
, SSCR0
, val
);
279 if (!cpu_is_pxa3xx())
280 clk_enable(ssp
->clk
);
286 * Set the SSP clock dividers.
288 static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai
*cpu_dai
,
291 struct ssp_priv
*priv
= cpu_dai
->private_data
;
292 struct ssp_device
*ssp
= priv
->ssp
;
296 case PXA_SSP_AUDIO_DIV_ACDS
:
297 val
= (ssp_read_reg(ssp
, SSACD
) & ~0x7) | SSACD_ACDS(div
);
298 ssp_write_reg(ssp
, SSACD
, val
);
300 case PXA_SSP_AUDIO_DIV_SCDB
:
301 val
= ssp_read_reg(ssp
, SSACD
);
303 #if defined(CONFIG_PXA3xx)
308 case PXA_SSP_CLK_SCDB_1
:
311 case PXA_SSP_CLK_SCDB_4
:
313 #if defined(CONFIG_PXA3xx)
314 case PXA_SSP_CLK_SCDB_8
:
324 ssp_write_reg(ssp
, SSACD
, val
);
326 case PXA_SSP_DIV_SCR
:
327 ssp_set_scr(ssp
, div
);
337 * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
339 static int pxa_ssp_set_dai_pll(struct snd_soc_dai
*cpu_dai
, int pll_id
,
340 int source
, unsigned int freq_in
, unsigned int freq_out
)
342 struct ssp_priv
*priv
= cpu_dai
->private_data
;
343 struct ssp_device
*ssp
= priv
->ssp
;
344 u32 ssacd
= ssp_read_reg(ssp
, SSACD
) & ~0x70;
346 #if defined(CONFIG_PXA3xx)
348 ssp_write_reg(ssp
, SSACDD
, 0);
375 /* PXA3xx has a clock ditherer which can be used to generate
376 * a wider range of frequencies - calculate a value for it.
378 if (cpu_is_pxa3xx()) {
382 do_div(tmp
, freq_out
);
385 val
= (val
<< 16) | 64;
386 ssp_write_reg(ssp
, SSACDD
, val
);
390 dev_dbg(&ssp
->pdev
->dev
,
391 "Using SSACDD %x to supply %uHz\n",
400 ssp_write_reg(ssp
, SSACD
, ssacd
);
406 * Set the active slots in TDM/Network mode
408 static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai
*cpu_dai
,
409 unsigned int tx_mask
, unsigned int rx_mask
, int slots
, int slot_width
)
411 struct ssp_priv
*priv
= cpu_dai
->private_data
;
412 struct ssp_device
*ssp
= priv
->ssp
;
415 sscr0
= ssp_read_reg(ssp
, SSCR0
);
416 sscr0
&= ~(SSCR0_MOD
| SSCR0_SlotsPerFrm(8) | SSCR0_EDSS
| SSCR0_DSS
);
420 sscr0
|= SSCR0_EDSS
| SSCR0_DataSize(slot_width
- 16);
422 sscr0
|= SSCR0_DataSize(slot_width
);
425 /* enable network mode */
428 /* set number of active slots */
429 sscr0
|= SSCR0_SlotsPerFrm(slots
);
431 /* set active slot mask */
432 ssp_write_reg(ssp
, SSTSA
, tx_mask
);
433 ssp_write_reg(ssp
, SSRSA
, rx_mask
);
435 ssp_write_reg(ssp
, SSCR0
, sscr0
);
441 * Tristate the SSP DAI lines
443 static int pxa_ssp_set_dai_tristate(struct snd_soc_dai
*cpu_dai
,
446 struct ssp_priv
*priv
= cpu_dai
->private_data
;
447 struct ssp_device
*ssp
= priv
->ssp
;
450 sscr1
= ssp_read_reg(ssp
, SSCR1
);
455 ssp_write_reg(ssp
, SSCR1
, sscr1
);
461 * Set up the SSP DAI format.
462 * The SSP Port must be inactive before calling this function as the
463 * physical interface format is changed.
465 static int pxa_ssp_set_dai_fmt(struct snd_soc_dai
*cpu_dai
,
468 struct ssp_priv
*priv
= cpu_dai
->private_data
;
469 struct ssp_device
*ssp
= priv
->ssp
;
474 /* check if we need to change anything at all */
475 if (priv
->dai_fmt
== fmt
)
478 /* we can only change the settings if the port is not in use */
479 if (ssp_read_reg(ssp
, SSCR0
) & SSCR0_SSE
) {
480 dev_err(&ssp
->pdev
->dev
,
481 "can't change hardware dai format: stream is in use");
485 /* reset port settings */
486 sscr0
= ssp_read_reg(ssp
, SSCR0
) &
487 (SSCR0_ECS
| SSCR0_NCS
| SSCR0_MOD
| SSCR0_ACS
);
488 sscr1
= SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
491 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
492 case SND_SOC_DAIFMT_CBM_CFM
:
493 sscr1
|= SSCR1_SCLKDIR
| SSCR1_SFRMDIR
;
495 case SND_SOC_DAIFMT_CBM_CFS
:
496 sscr1
|= SSCR1_SCLKDIR
;
498 case SND_SOC_DAIFMT_CBS_CFS
:
504 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
505 case SND_SOC_DAIFMT_NB_NF
:
506 sspsp
|= SSPSP_SFRMP
;
508 case SND_SOC_DAIFMT_NB_IF
:
510 case SND_SOC_DAIFMT_IB_IF
:
511 sspsp
|= SSPSP_SCMODE(2);
513 case SND_SOC_DAIFMT_IB_NF
:
514 sspsp
|= SSPSP_SCMODE(2) | SSPSP_SFRMP
;
520 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
521 case SND_SOC_DAIFMT_I2S
:
523 sscr1
|= SSCR1_RWOT
| SSCR1_TRAIL
;
524 /* See hw_params() */
527 case SND_SOC_DAIFMT_DSP_A
:
529 case SND_SOC_DAIFMT_DSP_B
:
530 sscr0
|= SSCR0_MOD
| SSCR0_PSP
;
531 sscr1
|= SSCR1_TRAIL
| SSCR1_RWOT
;
538 ssp_write_reg(ssp
, SSCR0
, sscr0
);
539 ssp_write_reg(ssp
, SSCR1
, sscr1
);
540 ssp_write_reg(ssp
, SSPSP
, sspsp
);
544 /* Since we are configuring the timings for the format by hand
545 * we have to defer some things until hw_params() where we
546 * know parameters like the sample size.
554 * Set the SSP audio DMA parameters and sample size.
555 * Can be called multiple times by oss emulation.
557 static int pxa_ssp_hw_params(struct snd_pcm_substream
*substream
,
558 struct snd_pcm_hw_params
*params
,
559 struct snd_soc_dai
*dai
)
561 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
562 struct snd_soc_dai
*cpu_dai
= rtd
->dai
->cpu_dai
;
563 struct ssp_priv
*priv
= cpu_dai
->private_data
;
564 struct ssp_device
*ssp
= priv
->ssp
;
565 int chn
= params_channels(params
);
568 int width
= snd_pcm_format_physical_width(params_format(params
));
569 int ttsa
= ssp_read_reg(ssp
, SSTSA
) & 0xf;
570 struct pxa2xx_pcm_dma_params
*dma_data
;
572 dma_data
= snd_soc_dai_get_dma_data(dai
, substream
);
574 /* generate correct DMA params */
577 /* Network mode with one active slot (ttsa == 1) can be used
578 * to force 16-bit frame width on the wire (for S16_LE), even
579 * with two channels. Use 16-bit DMA transfers for this case.
581 dma_data
= ssp_get_dma_params(ssp
,
582 ((chn
== 2) && (ttsa
!= 1)) || (width
== 32),
583 substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
);
585 snd_soc_dai_set_dma_data(dai
, substream
, dma_data
);
587 /* we can only change the settings if the port is not in use */
588 if (ssp_read_reg(ssp
, SSCR0
) & SSCR0_SSE
)
591 /* clear selected SSP bits */
592 sscr0
= ssp_read_reg(ssp
, SSCR0
) & ~(SSCR0_DSS
| SSCR0_EDSS
);
593 ssp_write_reg(ssp
, SSCR0
, sscr0
);
596 sscr0
= ssp_read_reg(ssp
, SSCR0
);
597 switch (params_format(params
)) {
598 case SNDRV_PCM_FORMAT_S16_LE
:
601 sscr0
|= SSCR0_FPCKE
;
603 sscr0
|= SSCR0_DataSize(16);
605 case SNDRV_PCM_FORMAT_S24_LE
:
606 sscr0
|= (SSCR0_EDSS
| SSCR0_DataSize(8));
608 case SNDRV_PCM_FORMAT_S32_LE
:
609 sscr0
|= (SSCR0_EDSS
| SSCR0_DataSize(16));
612 ssp_write_reg(ssp
, SSCR0
, sscr0
);
614 switch (priv
->dai_fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
615 case SND_SOC_DAIFMT_I2S
:
616 sspsp
= ssp_read_reg(ssp
, SSPSP
);
618 if ((ssp_get_scr(ssp
) == 4) && (width
== 16)) {
619 /* This is a special case where the bitclk is 64fs
620 * and we're not dealing with 2*32 bits of audio
623 * The SSP values used for that are all found out by
624 * trying and failing a lot; some of the registers
625 * needed for that mode are only available on PXA3xx.
629 if (!cpu_is_pxa3xx())
632 sspsp
|= SSPSP_SFRMWDTH(width
* 2);
633 sspsp
|= SSPSP_SFRMDLY(width
* 4);
634 sspsp
|= SSPSP_EDMYSTOP(3);
635 sspsp
|= SSPSP_DMYSTOP(3);
636 sspsp
|= SSPSP_DMYSTRT(1);
641 /* The frame width is the width the LRCLK is
642 * asserted for; the delay is expressed in
643 * half cycle units. We need the extra cycle
644 * because the data starts clocking out one BCLK
645 * after LRCLK changes polarity.
647 sspsp
|= SSPSP_SFRMWDTH(width
+ 1);
648 sspsp
|= SSPSP_SFRMDLY((width
+ 1) * 2);
649 sspsp
|= SSPSP_DMYSTRT(1);
652 ssp_write_reg(ssp
, SSPSP
, sspsp
);
658 /* When we use a network mode, we always require TDM slots
659 * - complain loudly and fail if they've not been set up yet.
661 if ((sscr0
& SSCR0_MOD
) && !ttsa
) {
662 dev_err(&ssp
->pdev
->dev
, "No TDM timeslot configured\n");
671 static int pxa_ssp_trigger(struct snd_pcm_substream
*substream
, int cmd
,
672 struct snd_soc_dai
*dai
)
674 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
675 struct snd_soc_dai
*cpu_dai
= rtd
->dai
->cpu_dai
;
677 struct ssp_priv
*priv
= cpu_dai
->private_data
;
678 struct ssp_device
*ssp
= priv
->ssp
;
682 case SNDRV_PCM_TRIGGER_RESUME
:
685 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
686 val
= ssp_read_reg(ssp
, SSCR1
);
687 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
691 ssp_write_reg(ssp
, SSCR1
, val
);
692 val
= ssp_read_reg(ssp
, SSSR
);
693 ssp_write_reg(ssp
, SSSR
, val
);
695 case SNDRV_PCM_TRIGGER_START
:
696 val
= ssp_read_reg(ssp
, SSCR1
);
697 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
701 ssp_write_reg(ssp
, SSCR1
, val
);
704 case SNDRV_PCM_TRIGGER_STOP
:
705 val
= ssp_read_reg(ssp
, SSCR1
);
706 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
710 ssp_write_reg(ssp
, SSCR1
, val
);
712 case SNDRV_PCM_TRIGGER_SUSPEND
:
715 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
716 val
= ssp_read_reg(ssp
, SSCR1
);
717 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
721 ssp_write_reg(ssp
, SSCR1
, val
);
733 static int pxa_ssp_probe(struct platform_device
*pdev
,
734 struct snd_soc_dai
*dai
)
736 struct ssp_priv
*priv
;
739 priv
= kzalloc(sizeof(struct ssp_priv
), GFP_KERNEL
);
743 priv
->ssp
= ssp_request(dai
->id
+ 1, "SoC audio");
744 if (priv
->ssp
== NULL
) {
749 priv
->dai_fmt
= (unsigned int) -1;
750 dai
->private_data
= priv
;
759 static void pxa_ssp_remove(struct platform_device
*pdev
,
760 struct snd_soc_dai
*dai
)
762 struct ssp_priv
*priv
= dai
->private_data
;
766 #define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
767 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
768 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
769 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
771 #define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
772 SNDRV_PCM_FMTBIT_S24_LE | \
773 SNDRV_PCM_FMTBIT_S32_LE)
775 static struct snd_soc_dai_ops pxa_ssp_dai_ops
= {
776 .startup
= pxa_ssp_startup
,
777 .shutdown
= pxa_ssp_shutdown
,
778 .trigger
= pxa_ssp_trigger
,
779 .hw_params
= pxa_ssp_hw_params
,
780 .set_sysclk
= pxa_ssp_set_dai_sysclk
,
781 .set_clkdiv
= pxa_ssp_set_dai_clkdiv
,
782 .set_pll
= pxa_ssp_set_dai_pll
,
783 .set_fmt
= pxa_ssp_set_dai_fmt
,
784 .set_tdm_slot
= pxa_ssp_set_dai_tdm_slot
,
785 .set_tristate
= pxa_ssp_set_dai_tristate
,
788 struct snd_soc_dai pxa_ssp_dai
[] = {
790 .name
= "pxa2xx-ssp1",
792 .probe
= pxa_ssp_probe
,
793 .remove
= pxa_ssp_remove
,
794 .suspend
= pxa_ssp_suspend
,
795 .resume
= pxa_ssp_resume
,
799 .rates
= PXA_SSP_RATES
,
800 .formats
= PXA_SSP_FORMATS
,
805 .rates
= PXA_SSP_RATES
,
806 .formats
= PXA_SSP_FORMATS
,
808 .ops
= &pxa_ssp_dai_ops
,
810 { .name
= "pxa2xx-ssp2",
812 .probe
= pxa_ssp_probe
,
813 .remove
= pxa_ssp_remove
,
814 .suspend
= pxa_ssp_suspend
,
815 .resume
= pxa_ssp_resume
,
819 .rates
= PXA_SSP_RATES
,
820 .formats
= PXA_SSP_FORMATS
,
825 .rates
= PXA_SSP_RATES
,
826 .formats
= PXA_SSP_FORMATS
,
828 .ops
= &pxa_ssp_dai_ops
,
831 .name
= "pxa2xx-ssp3",
833 .probe
= pxa_ssp_probe
,
834 .remove
= pxa_ssp_remove
,
835 .suspend
= pxa_ssp_suspend
,
836 .resume
= pxa_ssp_resume
,
840 .rates
= PXA_SSP_RATES
,
841 .formats
= PXA_SSP_FORMATS
,
846 .rates
= PXA_SSP_RATES
,
847 .formats
= PXA_SSP_FORMATS
,
849 .ops
= &pxa_ssp_dai_ops
,
852 .name
= "pxa2xx-ssp4",
854 .probe
= pxa_ssp_probe
,
855 .remove
= pxa_ssp_remove
,
856 .suspend
= pxa_ssp_suspend
,
857 .resume
= pxa_ssp_resume
,
861 .rates
= PXA_SSP_RATES
,
862 .formats
= PXA_SSP_FORMATS
,
867 .rates
= PXA_SSP_RATES
,
868 .formats
= PXA_SSP_FORMATS
,
870 .ops
= &pxa_ssp_dai_ops
,
873 EXPORT_SYMBOL_GPL(pxa_ssp_dai
);
875 static int __init
pxa_ssp_init(void)
877 return snd_soc_register_dais(pxa_ssp_dai
, ARRAY_SIZE(pxa_ssp_dai
));
879 module_init(pxa_ssp_init
);
881 static void __exit
pxa_ssp_exit(void)
883 snd_soc_unregister_dais(pxa_ssp_dai
, ARRAY_SIZE(pxa_ssp_dai
));
885 module_exit(pxa_ssp_exit
);
887 /* Module information */
888 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
889 MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
890 MODULE_LICENSE("GPL");