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V4L/DVB (7937): pvrusb2: Change several embedded timer constants to defined values
[firewire-audio.git] / drivers / media / video / pvrusb2 / pvrusb2-hdw.c
blobd4d57951cca2577af23aea06ae7e0a1be9c6479e
1 /*
2 *
3 *
4 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 *
19 */
20
21 #include <linux/errno.h>
22 #include <linux/string.h>
23 #include <linux/slab.h>
24 #include <linux/firmware.h>
25 #include <linux/videodev2.h>
26 #include <media/v4l2-common.h>
27 #include "pvrusb2.h"
28 #include "pvrusb2-std.h"
29 #include "pvrusb2-util.h"
30 #include "pvrusb2-hdw.h"
31 #include "pvrusb2-i2c-core.h"
32 #include "pvrusb2-tuner.h"
33 #include "pvrusb2-eeprom.h"
34 #include "pvrusb2-hdw-internal.h"
35 #include "pvrusb2-encoder.h"
36 #include "pvrusb2-debug.h"
37 #include "pvrusb2-fx2-cmd.h"
38
39 #define TV_MIN_FREQ 55250000L
40 #define TV_MAX_FREQ 850000000L
41
42 /* This defines a minimum interval that the decoder must remain quiet
43 before we are allowed to start it running. */
44 #define TIME_MSEC_DECODER_WAIT 50
45
46 /* This defines a minimum interval that the encoder must remain quiet
47 before we are allowed to configure it. */
48 #define TIME_MSEC_ENCODER_WAIT 50
49
50 /* This defines the minimum interval that the encoder must successfully run
51 before we consider that the encoder has run at least once since its
52 firmware has been loaded. This measurement is in important for cases
53 where we can't do something until we know that the encoder has been run
54 at least once. */
55 #define TIME_MSEC_ENCODER_OK 250
56
57 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
58 static DEFINE_MUTEX(pvr2_unit_mtx);
59
60 static int ctlchg;
61 static int initusbreset = 1;
62 static int procreload;
63 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
64 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
65 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
66 static int init_pause_msec;
67
68 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
69 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
70 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
71 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
72 module_param(initusbreset, int, S_IRUGO|S_IWUSR);
73 MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
74 module_param(procreload, int, S_IRUGO|S_IWUSR);
75 MODULE_PARM_DESC(procreload,
76 "Attempt init failure recovery with firmware reload");
77 module_param_array(tuner, int, NULL, 0444);
78 MODULE_PARM_DESC(tuner,"specify installed tuner type");
79 module_param_array(video_std, int, NULL, 0444);
80 MODULE_PARM_DESC(video_std,"specify initial video standard");
81 module_param_array(tolerance, int, NULL, 0444);
82 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
83
84 /* US Broadcast channel 7 (175.25 MHz) */
85 static int default_tv_freq = 175250000L;
86 /* 104.3 MHz, a usable FM station for my area */
87 static int default_radio_freq = 104300000L;
88
89 module_param_named(tv_freq, default_tv_freq, int, 0444);
90 MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
91 module_param_named(radio_freq, default_radio_freq, int, 0444);
92 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
93
94 #define PVR2_CTL_WRITE_ENDPOINT 0x01
95 #define PVR2_CTL_READ_ENDPOINT 0x81
96
97 #define PVR2_GPIO_IN 0x9008
98 #define PVR2_GPIO_OUT 0x900c
99 #define PVR2_GPIO_DIR 0x9020
100
101 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
102
103 #define PVR2_FIRMWARE_ENDPOINT 0x02
104
105 /* size of a firmware chunk */
106 #define FIRMWARE_CHUNK_SIZE 0x2000
107
108 /* Define the list of additional controls we'll dynamically construct based
109 on query of the cx2341x module. */
110 struct pvr2_mpeg_ids {
111 const char *strid;
112 int id;
113 };
114 static const struct pvr2_mpeg_ids mpeg_ids[] = {
115 {
116 .strid = "audio_layer",
117 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
118 },{
119 .strid = "audio_bitrate",
120 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
121 },{
122 /* Already using audio_mode elsewhere :-( */
123 .strid = "mpeg_audio_mode",
124 .id = V4L2_CID_MPEG_AUDIO_MODE,
125 },{
126 .strid = "mpeg_audio_mode_extension",
127 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
128 },{
129 .strid = "audio_emphasis",
130 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
131 },{
132 .strid = "audio_crc",
133 .id = V4L2_CID_MPEG_AUDIO_CRC,
134 },{
135 .strid = "video_aspect",
136 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
137 },{
138 .strid = "video_b_frames",
139 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
140 },{
141 .strid = "video_gop_size",
142 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
143 },{
144 .strid = "video_gop_closure",
145 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
146 },{
147 .strid = "video_bitrate_mode",
148 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
149 },{
150 .strid = "video_bitrate",
151 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
152 },{
153 .strid = "video_bitrate_peak",
154 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
155 },{
156 .strid = "video_temporal_decimation",
157 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
158 },{
159 .strid = "stream_type",
160 .id = V4L2_CID_MPEG_STREAM_TYPE,
161 },{
162 .strid = "video_spatial_filter_mode",
163 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
164 },{
165 .strid = "video_spatial_filter",
166 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
167 },{
168 .strid = "video_luma_spatial_filter_type",
169 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
170 },{
171 .strid = "video_chroma_spatial_filter_type",
172 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
173 },{
174 .strid = "video_temporal_filter_mode",
175 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
176 },{
177 .strid = "video_temporal_filter",
178 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
179 },{
180 .strid = "video_median_filter_type",
181 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
182 },{
183 .strid = "video_luma_median_filter_top",
184 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
185 },{
186 .strid = "video_luma_median_filter_bottom",
187 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
188 },{
189 .strid = "video_chroma_median_filter_top",
190 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
191 },{
192 .strid = "video_chroma_median_filter_bottom",
193 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
194 }
195 };
196 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
197
198
199 static const char *control_values_srate[] = {
200 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
201 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
202 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
203 };
204
205
206
207 static const char *control_values_input[] = {
208 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
209 [PVR2_CVAL_INPUT_DTV] = "dtv",
210 [PVR2_CVAL_INPUT_RADIO] = "radio",
211 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
212 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
213 };
214
215
216 static const char *control_values_audiomode[] = {
217 [V4L2_TUNER_MODE_MONO] = "Mono",
218 [V4L2_TUNER_MODE_STEREO] = "Stereo",
219 [V4L2_TUNER_MODE_LANG1] = "Lang1",
220 [V4L2_TUNER_MODE_LANG2] = "Lang2",
221 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
222 };
223
224
225 static const char *control_values_hsm[] = {
226 [PVR2_CVAL_HSM_FAIL] = "Fail",
227 [PVR2_CVAL_HSM_HIGH] = "High",
228 [PVR2_CVAL_HSM_FULL] = "Full",
229 };
230
231
232 static const char *pvr2_state_names[] = {
233 [PVR2_STATE_NONE] = "none",
234 [PVR2_STATE_DEAD] = "dead",
235 [PVR2_STATE_COLD] = "cold",
236 [PVR2_STATE_WARM] = "warm",
237 [PVR2_STATE_ERROR] = "error",
238 [PVR2_STATE_READY] = "ready",
239 [PVR2_STATE_RUN] = "run",
240 };
241
242
243 struct pvr2_fx2cmd_descdef {
244 unsigned char id;
245 unsigned char *desc;
246 };
247
248 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
249 {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
250 {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
251 {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
252 {FX2CMD_REG_WRITE, "write encoder register"},
253 {FX2CMD_REG_READ, "read encoder register"},
254 {FX2CMD_MEMSEL, "encoder memsel"},
255 {FX2CMD_I2C_WRITE, "i2c write"},
256 {FX2CMD_I2C_READ, "i2c read"},
257 {FX2CMD_GET_USB_SPEED, "get USB speed"},
258 {FX2CMD_STREAMING_ON, "stream on"},
259 {FX2CMD_STREAMING_OFF, "stream off"},
260 {FX2CMD_FWPOST1, "fwpost1"},
261 {FX2CMD_POWER_OFF, "power off"},
262 {FX2CMD_POWER_ON, "power on"},
263 {FX2CMD_DEEP_RESET, "deep reset"},
264 {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
265 {FX2CMD_GET_IR_CODE, "get IR code"},
266 {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
267 {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
268 {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
269 {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
270 {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
271 {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
272 {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
273 };
274
275
276 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
277 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
278 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
279 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
280 static void pvr2_hdw_worker_i2c(struct work_struct *work);
281 static void pvr2_hdw_worker_poll(struct work_struct *work);
282 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
283 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
284 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
285 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
286 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
287 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
288 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
289 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
290 static void pvr2_hdw_quiescent_timeout(unsigned long);
291 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
292 static void pvr2_hdw_encoder_run_timeout(unsigned long);
293 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
294 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
295 unsigned int timeout,int probe_fl,
296 void *write_data,unsigned int write_len,
297 void *read_data,unsigned int read_len);
298
299
300 static void trace_stbit(const char *name,int val)
301 {
302 pvr2_trace(PVR2_TRACE_STBITS,
303 "State bit %s <-- %s",
304 name,(val ? "true" : "false"));
305 }
306
307 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
308 {
309 struct pvr2_hdw *hdw = cptr->hdw;
310 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
311 *vp = hdw->freqTable[hdw->freqProgSlot-1];
312 } else {
313 *vp = 0;
314 }
315 return 0;
316 }
317
318 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
319 {
320 struct pvr2_hdw *hdw = cptr->hdw;
321 unsigned int slotId = hdw->freqProgSlot;
322 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
323 hdw->freqTable[slotId-1] = v;
324 /* Handle side effects correctly - if we're tuned to this
325 slot, then forgot the slot id relation since the stored
326 frequency has been changed. */
327 if (hdw->freqSelector) {
328 if (hdw->freqSlotRadio == slotId) {
329 hdw->freqSlotRadio = 0;
330 }
331 } else {
332 if (hdw->freqSlotTelevision == slotId) {
333 hdw->freqSlotTelevision = 0;
334 }
335 }
336 }
337 return 0;
338 }
339
340 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
341 {
342 *vp = cptr->hdw->freqProgSlot;
343 return 0;
344 }
345
346 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
347 {
348 struct pvr2_hdw *hdw = cptr->hdw;
349 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
350 hdw->freqProgSlot = v;
351 }
352 return 0;
353 }
354
355 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
356 {
357 struct pvr2_hdw *hdw = cptr->hdw;
358 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
359 return 0;
360 }
361
362 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
363 {
364 unsigned freq = 0;
365 struct pvr2_hdw *hdw = cptr->hdw;
366 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
367 if (slotId > 0) {
368 freq = hdw->freqTable[slotId-1];
369 if (!freq) return 0;
370 pvr2_hdw_set_cur_freq(hdw,freq);
371 }
372 if (hdw->freqSelector) {
373 hdw->freqSlotRadio = slotId;
374 } else {
375 hdw->freqSlotTelevision = slotId;
376 }
377 return 0;
378 }
379
380 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
381 {
382 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
383 return 0;
384 }
385
386 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
387 {
388 return cptr->hdw->freqDirty != 0;
389 }
390
391 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
392 {
393 cptr->hdw->freqDirty = 0;
394 }
395
396 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
397 {
398 pvr2_hdw_set_cur_freq(cptr->hdw,v);
399 return 0;
400 }
401
402 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
403 {
404 /* Actual maximum depends on the video standard in effect. */
405 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
406 *vp = 480;
407 } else {
408 *vp = 576;
409 }
410 return 0;
411 }
412
413 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
414 {
415 /* Actual minimum depends on device digitizer type. */
416 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
417 *vp = 75;
418 } else {
419 *vp = 17;
420 }
421 return 0;
422 }
423
424 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
425 {
426 *vp = cptr->hdw->input_val;
427 return 0;
428 }
429
430 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
431 {
432 return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
433 }
434
435 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
436 {
437 return pvr2_hdw_set_input(cptr->hdw,v);
438 }
439
440 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
441 {
442 return cptr->hdw->input_dirty != 0;
443 }
444
445 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
446 {
447 cptr->hdw->input_dirty = 0;
448 }
449
450
451 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
452 {
453 unsigned long fv;
454 struct pvr2_hdw *hdw = cptr->hdw;
455 if (hdw->tuner_signal_stale) {
456 pvr2_i2c_core_status_poll(hdw);
457 }
458 fv = hdw->tuner_signal_info.rangehigh;
459 if (!fv) {
460 /* Safety fallback */
461 *vp = TV_MAX_FREQ;
462 return 0;
463 }
464 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
465 fv = (fv * 125) / 2;
466 } else {
467 fv = fv * 62500;
468 }
469 *vp = fv;
470 return 0;
471 }
472
473 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
474 {
475 unsigned long fv;
476 struct pvr2_hdw *hdw = cptr->hdw;
477 if (hdw->tuner_signal_stale) {
478 pvr2_i2c_core_status_poll(hdw);
479 }
480 fv = hdw->tuner_signal_info.rangelow;
481 if (!fv) {
482 /* Safety fallback */
483 *vp = TV_MIN_FREQ;
484 return 0;
485 }
486 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
487 fv = (fv * 125) / 2;
488 } else {
489 fv = fv * 62500;
490 }
491 *vp = fv;
492 return 0;
493 }
494
495 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
496 {
497 return cptr->hdw->enc_stale != 0;
498 }
499
500 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
501 {
502 cptr->hdw->enc_stale = 0;
503 cptr->hdw->enc_unsafe_stale = 0;
504 }
505
506 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
507 {
508 int ret;
509 struct v4l2_ext_controls cs;
510 struct v4l2_ext_control c1;
511 memset(&cs,0,sizeof(cs));
512 memset(&c1,0,sizeof(c1));
513 cs.controls = &c1;
514 cs.count = 1;
515 c1.id = cptr->info->v4l_id;
516 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
517 VIDIOC_G_EXT_CTRLS);
518 if (ret) return ret;
519 *vp = c1.value;
520 return 0;
521 }
522
523 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
524 {
525 int ret;
526 struct pvr2_hdw *hdw = cptr->hdw;
527 struct v4l2_ext_controls cs;
528 struct v4l2_ext_control c1;
529 memset(&cs,0,sizeof(cs));
530 memset(&c1,0,sizeof(c1));
531 cs.controls = &c1;
532 cs.count = 1;
533 c1.id = cptr->info->v4l_id;
534 c1.value = v;
535 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
536 hdw->state_encoder_run, &cs,
537 VIDIOC_S_EXT_CTRLS);
538 if (ret == -EBUSY) {
539 /* Oops. cx2341x is telling us it's not safe to change
540 this control while we're capturing. Make a note of this
541 fact so that the pipeline will be stopped the next time
542 controls are committed. Then go on ahead and store this
543 change anyway. */
544 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
545 0, &cs,
546 VIDIOC_S_EXT_CTRLS);
547 if (!ret) hdw->enc_unsafe_stale = !0;
548 }
549 if (ret) return ret;
550 hdw->enc_stale = !0;
551 return 0;
552 }
553
554 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
555 {
556 struct v4l2_queryctrl qctrl;
557 struct pvr2_ctl_info *info;
558 qctrl.id = cptr->info->v4l_id;
559 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
560 /* Strip out the const so we can adjust a function pointer. It's
561 OK to do this here because we know this is a dynamically created
562 control, so the underlying storage for the info pointer is (a)
563 private to us, and (b) not in read-only storage. Either we do
564 this or we significantly complicate the underlying control
565 implementation. */
566 info = (struct pvr2_ctl_info *)(cptr->info);
567 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
568 if (info->set_value) {
569 info->set_value = NULL;
570 }
571 } else {
572 if (!(info->set_value)) {
573 info->set_value = ctrl_cx2341x_set;
574 }
575 }
576 return qctrl.flags;
577 }
578
579 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
580 {
581 *vp = cptr->hdw->state_pipeline_req;
582 return 0;
583 }
584
585 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
586 {
587 *vp = cptr->hdw->master_state;
588 return 0;
589 }
590
591 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
592 {
593 int result = pvr2_hdw_is_hsm(cptr->hdw);
594 *vp = PVR2_CVAL_HSM_FULL;
595 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
596 if (result) *vp = PVR2_CVAL_HSM_HIGH;
597 return 0;
598 }
599
600 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
601 {
602 *vp = cptr->hdw->std_mask_avail;
603 return 0;
604 }
605
606 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
607 {
608 struct pvr2_hdw *hdw = cptr->hdw;
609 v4l2_std_id ns;
610 ns = hdw->std_mask_avail;
611 ns = (ns & ~m) | (v & m);
612 if (ns == hdw->std_mask_avail) return 0;
613 hdw->std_mask_avail = ns;
614 pvr2_hdw_internal_set_std_avail(hdw);
615 pvr2_hdw_internal_find_stdenum(hdw);
616 return 0;
617 }
618
619 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
620 char *bufPtr,unsigned int bufSize,
621 unsigned int *len)
622 {
623 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
624 return 0;
625 }
626
627 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
628 const char *bufPtr,unsigned int bufSize,
629 int *mskp,int *valp)
630 {
631 int ret;
632 v4l2_std_id id;
633 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
634 if (ret < 0) return ret;
635 if (mskp) *mskp = id;
636 if (valp) *valp = id;
637 return 0;
638 }
639
640 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
641 {
642 *vp = cptr->hdw->std_mask_cur;
643 return 0;
644 }
645
646 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
647 {
648 struct pvr2_hdw *hdw = cptr->hdw;
649 v4l2_std_id ns;
650 ns = hdw->std_mask_cur;
651 ns = (ns & ~m) | (v & m);
652 if (ns == hdw->std_mask_cur) return 0;
653 hdw->std_mask_cur = ns;
654 hdw->std_dirty = !0;
655 pvr2_hdw_internal_find_stdenum(hdw);
656 return 0;
657 }
658
659 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
660 {
661 return cptr->hdw->std_dirty != 0;
662 }
663
664 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
665 {
666 cptr->hdw->std_dirty = 0;
667 }
668
669 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
670 {
671 struct pvr2_hdw *hdw = cptr->hdw;
672 pvr2_i2c_core_status_poll(hdw);
673 *vp = hdw->tuner_signal_info.signal;
674 return 0;
675 }
676
677 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
678 {
679 int val = 0;
680 unsigned int subchan;
681 struct pvr2_hdw *hdw = cptr->hdw;
682 pvr2_i2c_core_status_poll(hdw);
683 subchan = hdw->tuner_signal_info.rxsubchans;
684 if (subchan & V4L2_TUNER_SUB_MONO) {
685 val |= (1 << V4L2_TUNER_MODE_MONO);
686 }
687 if (subchan & V4L2_TUNER_SUB_STEREO) {
688 val |= (1 << V4L2_TUNER_MODE_STEREO);
689 }
690 if (subchan & V4L2_TUNER_SUB_LANG1) {
691 val |= (1 << V4L2_TUNER_MODE_LANG1);
692 }
693 if (subchan & V4L2_TUNER_SUB_LANG2) {
694 val |= (1 << V4L2_TUNER_MODE_LANG2);
695 }
696 *vp = val;
697 return 0;
698 }
699
700
701 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
702 {
703 struct pvr2_hdw *hdw = cptr->hdw;
704 if (v < 0) return -EINVAL;
705 if (v > hdw->std_enum_cnt) return -EINVAL;
706 hdw->std_enum_cur = v;
707 if (!v) return 0;
708 v--;
709 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
710 hdw->std_mask_cur = hdw->std_defs[v].id;
711 hdw->std_dirty = !0;
712 return 0;
713 }
714
715
716 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
717 {
718 *vp = cptr->hdw->std_enum_cur;
719 return 0;
720 }
721
722
723 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
724 {
725 return cptr->hdw->std_dirty != 0;
726 }
727
728
729 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
730 {
731 cptr->hdw->std_dirty = 0;
732 }
733
734
735 #define DEFINT(vmin,vmax) \
736 .type = pvr2_ctl_int, \
737 .def.type_int.min_value = vmin, \
738 .def.type_int.max_value = vmax
739
740 #define DEFENUM(tab) \
741 .type = pvr2_ctl_enum, \
742 .def.type_enum.count = ARRAY_SIZE(tab), \
743 .def.type_enum.value_names = tab
744
745 #define DEFBOOL \
746 .type = pvr2_ctl_bool
747
748 #define DEFMASK(msk,tab) \
749 .type = pvr2_ctl_bitmask, \
750 .def.type_bitmask.valid_bits = msk, \
751 .def.type_bitmask.bit_names = tab
752
753 #define DEFREF(vname) \
754 .set_value = ctrl_set_##vname, \
755 .get_value = ctrl_get_##vname, \
756 .is_dirty = ctrl_isdirty_##vname, \
757 .clear_dirty = ctrl_cleardirty_##vname
758
759
760 #define VCREATE_FUNCS(vname) \
761 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
762 {*vp = cptr->hdw->vname##_val; return 0;} \
763 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
764 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
765 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
766 {return cptr->hdw->vname##_dirty != 0;} \
767 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
768 {cptr->hdw->vname##_dirty = 0;}
769
770 VCREATE_FUNCS(brightness)
771 VCREATE_FUNCS(contrast)
772 VCREATE_FUNCS(saturation)
773 VCREATE_FUNCS(hue)
774 VCREATE_FUNCS(volume)
775 VCREATE_FUNCS(balance)
776 VCREATE_FUNCS(bass)
777 VCREATE_FUNCS(treble)
778 VCREATE_FUNCS(mute)
779 VCREATE_FUNCS(audiomode)
780 VCREATE_FUNCS(res_hor)
781 VCREATE_FUNCS(res_ver)
782 VCREATE_FUNCS(srate)
783
784 /* Table definition of all controls which can be manipulated */
785 static const struct pvr2_ctl_info control_defs[] = {
786 {
787 .v4l_id = V4L2_CID_BRIGHTNESS,
788 .desc = "Brightness",
789 .name = "brightness",
790 .default_value = 128,
791 DEFREF(brightness),
792 DEFINT(0,255),
793 },{
794 .v4l_id = V4L2_CID_CONTRAST,
795 .desc = "Contrast",
796 .name = "contrast",
797 .default_value = 68,
798 DEFREF(contrast),
799 DEFINT(0,127),
800 },{
801 .v4l_id = V4L2_CID_SATURATION,
802 .desc = "Saturation",
803 .name = "saturation",
804 .default_value = 64,
805 DEFREF(saturation),
806 DEFINT(0,127),
807 },{
808 .v4l_id = V4L2_CID_HUE,
809 .desc = "Hue",
810 .name = "hue",
811 .default_value = 0,
812 DEFREF(hue),
813 DEFINT(-128,127),
814 },{
815 .v4l_id = V4L2_CID_AUDIO_VOLUME,
816 .desc = "Volume",
817 .name = "volume",
818 .default_value = 62000,
819 DEFREF(volume),
820 DEFINT(0,65535),
821 },{
822 .v4l_id = V4L2_CID_AUDIO_BALANCE,
823 .desc = "Balance",
824 .name = "balance",
825 .default_value = 0,
826 DEFREF(balance),
827 DEFINT(-32768,32767),
828 },{
829 .v4l_id = V4L2_CID_AUDIO_BASS,
830 .desc = "Bass",
831 .name = "bass",
832 .default_value = 0,
833 DEFREF(bass),
834 DEFINT(-32768,32767),
835 },{
836 .v4l_id = V4L2_CID_AUDIO_TREBLE,
837 .desc = "Treble",
838 .name = "treble",
839 .default_value = 0,
840 DEFREF(treble),
841 DEFINT(-32768,32767),
842 },{
843 .v4l_id = V4L2_CID_AUDIO_MUTE,
844 .desc = "Mute",
845 .name = "mute",
846 .default_value = 0,
847 DEFREF(mute),
848 DEFBOOL,
849 },{
850 .desc = "Video Source",
851 .name = "input",
852 .internal_id = PVR2_CID_INPUT,
853 .default_value = PVR2_CVAL_INPUT_TV,
854 .check_value = ctrl_check_input,
855 DEFREF(input),
856 DEFENUM(control_values_input),
857 },{
858 .desc = "Audio Mode",
859 .name = "audio_mode",
860 .internal_id = PVR2_CID_AUDIOMODE,
861 .default_value = V4L2_TUNER_MODE_STEREO,
862 DEFREF(audiomode),
863 DEFENUM(control_values_audiomode),
864 },{
865 .desc = "Horizontal capture resolution",
866 .name = "resolution_hor",
867 .internal_id = PVR2_CID_HRES,
868 .default_value = 720,
869 DEFREF(res_hor),
870 DEFINT(19,720),
871 },{
872 .desc = "Vertical capture resolution",
873 .name = "resolution_ver",
874 .internal_id = PVR2_CID_VRES,
875 .default_value = 480,
876 DEFREF(res_ver),
877 DEFINT(17,576),
878 /* Hook in check for video standard and adjust maximum
879 depending on the standard. */
880 .get_max_value = ctrl_vres_max_get,
881 .get_min_value = ctrl_vres_min_get,
882 },{
883 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
884 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
885 .desc = "Audio Sampling Frequency",
886 .name = "srate",
887 DEFREF(srate),
888 DEFENUM(control_values_srate),
889 },{
890 .desc = "Tuner Frequency (Hz)",
891 .name = "frequency",
892 .internal_id = PVR2_CID_FREQUENCY,
893 .default_value = 0,
894 .set_value = ctrl_freq_set,
895 .get_value = ctrl_freq_get,
896 .is_dirty = ctrl_freq_is_dirty,
897 .clear_dirty = ctrl_freq_clear_dirty,
898 DEFINT(0,0),
899 /* Hook in check for input value (tv/radio) and adjust
900 max/min values accordingly */
901 .get_max_value = ctrl_freq_max_get,
902 .get_min_value = ctrl_freq_min_get,
903 },{
904 .desc = "Channel",
905 .name = "channel",
906 .set_value = ctrl_channel_set,
907 .get_value = ctrl_channel_get,
908 DEFINT(0,FREQTABLE_SIZE),
909 },{
910 .desc = "Channel Program Frequency",
911 .name = "freq_table_value",
912 .set_value = ctrl_channelfreq_set,
913 .get_value = ctrl_channelfreq_get,
914 DEFINT(0,0),
915 /* Hook in check for input value (tv/radio) and adjust
916 max/min values accordingly */
917 .get_max_value = ctrl_freq_max_get,
918 .get_min_value = ctrl_freq_min_get,
919 },{
920 .desc = "Channel Program ID",
921 .name = "freq_table_channel",
922 .set_value = ctrl_channelprog_set,
923 .get_value = ctrl_channelprog_get,
924 DEFINT(0,FREQTABLE_SIZE),
925 },{
926 .desc = "Streaming Enabled",
927 .name = "streaming_enabled",
928 .get_value = ctrl_streamingenabled_get,
929 DEFBOOL,
930 },{
931 .desc = "USB Speed",
932 .name = "usb_speed",
933 .get_value = ctrl_hsm_get,
934 DEFENUM(control_values_hsm),
935 },{
936 .desc = "Master State",
937 .name = "master_state",
938 .get_value = ctrl_masterstate_get,
939 DEFENUM(pvr2_state_names),
940 },{
941 .desc = "Signal Present",
942 .name = "signal_present",
943 .get_value = ctrl_signal_get,
944 DEFINT(0,65535),
945 },{
946 .desc = "Audio Modes Present",
947 .name = "audio_modes_present",
948 .get_value = ctrl_audio_modes_present_get,
949 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
950 v4l. Nothing outside of this module cares about this,
951 but I reuse it in order to also reuse the
952 control_values_audiomode string table. */
953 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
954 (1 << V4L2_TUNER_MODE_STEREO)|
955 (1 << V4L2_TUNER_MODE_LANG1)|
956 (1 << V4L2_TUNER_MODE_LANG2)),
957 control_values_audiomode),
958 },{
959 .desc = "Video Standards Available Mask",
960 .name = "video_standard_mask_available",
961 .internal_id = PVR2_CID_STDAVAIL,
962 .skip_init = !0,
963 .get_value = ctrl_stdavail_get,
964 .set_value = ctrl_stdavail_set,
965 .val_to_sym = ctrl_std_val_to_sym,
966 .sym_to_val = ctrl_std_sym_to_val,
967 .type = pvr2_ctl_bitmask,
968 },{
969 .desc = "Video Standards In Use Mask",
970 .name = "video_standard_mask_active",
971 .internal_id = PVR2_CID_STDCUR,
972 .skip_init = !0,
973 .get_value = ctrl_stdcur_get,
974 .set_value = ctrl_stdcur_set,
975 .is_dirty = ctrl_stdcur_is_dirty,
976 .clear_dirty = ctrl_stdcur_clear_dirty,
977 .val_to_sym = ctrl_std_val_to_sym,
978 .sym_to_val = ctrl_std_sym_to_val,
979 .type = pvr2_ctl_bitmask,
980 },{
981 .desc = "Video Standard Name",
982 .name = "video_standard",
983 .internal_id = PVR2_CID_STDENUM,
984 .skip_init = !0,
985 .get_value = ctrl_stdenumcur_get,
986 .set_value = ctrl_stdenumcur_set,
987 .is_dirty = ctrl_stdenumcur_is_dirty,
988 .clear_dirty = ctrl_stdenumcur_clear_dirty,
989 .type = pvr2_ctl_enum,
990 }
991 };
992
993 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
994
995
996 const char *pvr2_config_get_name(enum pvr2_config cfg)
997 {
998 switch (cfg) {
999 case pvr2_config_empty: return "empty";
1000 case pvr2_config_mpeg: return "mpeg";
1001 case pvr2_config_vbi: return "vbi";
1002 case pvr2_config_pcm: return "pcm";
1003 case pvr2_config_rawvideo: return "raw video";
1004 }
1005 return "<unknown>";
1006 }
1007
1008
1009 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1010 {
1011 return hdw->usb_dev;
1012 }
1013
1014
1015 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1016 {
1017 return hdw->serial_number;
1018 }
1019
1020
1021 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1022 {
1023 return hdw->bus_info;
1024 }
1025
1026
1027 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1028 {
1029 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1030 }
1031
1032 /* Set the currently tuned frequency and account for all possible
1033 driver-core side effects of this action. */
1034 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1035 {
1036 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1037 if (hdw->freqSelector) {
1038 /* Swing over to radio frequency selection */
1039 hdw->freqSelector = 0;
1040 hdw->freqDirty = !0;
1041 }
1042 if (hdw->freqValRadio != val) {
1043 hdw->freqValRadio = val;
1044 hdw->freqSlotRadio = 0;
1045 hdw->freqDirty = !0;
1046 }
1047 } else {
1048 if (!(hdw->freqSelector)) {
1049 /* Swing over to television frequency selection */
1050 hdw->freqSelector = 1;
1051 hdw->freqDirty = !0;
1052 }
1053 if (hdw->freqValTelevision != val) {
1054 hdw->freqValTelevision = val;
1055 hdw->freqSlotTelevision = 0;
1056 hdw->freqDirty = !0;
1057 }
1058 }
1059 }
1060
1061 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1062 {
1063 return hdw->unit_number;
1064 }
1065
1066
1067 /* Attempt to locate one of the given set of files. Messages are logged
1068 appropriate to what has been found. The return value will be 0 or
1069 greater on success (it will be the index of the file name found) and
1070 fw_entry will be filled in. Otherwise a negative error is returned on
1071 failure. If the return value is -ENOENT then no viable firmware file
1072 could be located. */
1073 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1074 const struct firmware **fw_entry,
1075 const char *fwtypename,
1076 unsigned int fwcount,
1077 const char *fwnames[])
1078 {
1079 unsigned int idx;
1080 int ret = -EINVAL;
1081 for (idx = 0; idx < fwcount; idx++) {
1082 ret = request_firmware(fw_entry,
1083 fwnames[idx],
1084 &hdw->usb_dev->dev);
1085 if (!ret) {
1086 trace_firmware("Located %s firmware: %s;"
1087 " uploading...",
1088 fwtypename,
1089 fwnames[idx]);
1090 return idx;
1091 }
1092 if (ret == -ENOENT) continue;
1093 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1094 "request_firmware fatal error with code=%d",ret);
1095 return ret;
1096 }
1097 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1098 "***WARNING***"
1099 " Device %s firmware"
1100 " seems to be missing.",
1101 fwtypename);
1102 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1103 "Did you install the pvrusb2 firmware files"
1104 " in their proper location?");
1105 if (fwcount == 1) {
1106 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1107 "request_firmware unable to locate %s file %s",
1108 fwtypename,fwnames[0]);
1109 } else {
1110 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1111 "request_firmware unable to locate"
1112 " one of the following %s files:",
1113 fwtypename);
1114 for (idx = 0; idx < fwcount; idx++) {
1115 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1116 "request_firmware: Failed to find %s",
1117 fwnames[idx]);
1118 }
1119 }
1120 return ret;
1121 }
1122
1123
1124 /*
1125 * pvr2_upload_firmware1().
1126 *
1127 * Send the 8051 firmware to the device. After the upload, arrange for
1128 * device to re-enumerate.
1129 *
1130 * NOTE : the pointer to the firmware data given by request_firmware()
1131 * is not suitable for an usb transaction.
1132 *
1133 */
1134 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1135 {
1136 const struct firmware *fw_entry = NULL;
1137 void *fw_ptr;
1138 unsigned int pipe;
1139 int ret;
1140 u16 address;
1141
1142 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1143 hdw->fw1_state = FW1_STATE_OK;
1144 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1145 "Connected device type defines"
1146 " no firmware to upload; ignoring firmware");
1147 return -ENOTTY;
1148 }
1149
1150 hdw->fw1_state = FW1_STATE_FAILED; // default result
1151
1152 trace_firmware("pvr2_upload_firmware1");
1153
1154 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1155 hdw->hdw_desc->fx2_firmware.cnt,
1156 hdw->hdw_desc->fx2_firmware.lst);
1157 if (ret < 0) {
1158 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1159 return ret;
1160 }
1161
1162 usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1163 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1164
1165 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1166
1167 if (fw_entry->size != 0x2000){
1168 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1169 release_firmware(fw_entry);
1170 return -ENOMEM;
1171 }
1172
1173 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1174 if (fw_ptr == NULL){
1175 release_firmware(fw_entry);
1176 return -ENOMEM;
1177 }
1178
1179 /* We have to hold the CPU during firmware upload. */
1180 pvr2_hdw_cpureset_assert(hdw,1);
1181
1182 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1183 chunk. */
1184
1185 ret = 0;
1186 for(address = 0; address < fw_entry->size; address += 0x800) {
1187 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1188 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1189 0, fw_ptr, 0x800, HZ);
1190 }
1191
1192 trace_firmware("Upload done, releasing device's CPU");
1193
1194 /* Now release the CPU. It will disconnect and reconnect later. */
1195 pvr2_hdw_cpureset_assert(hdw,0);
1196
1197 kfree(fw_ptr);
1198 release_firmware(fw_entry);
1199
1200 trace_firmware("Upload done (%d bytes sent)",ret);
1201
1202 /* We should have written 8192 bytes */
1203 if (ret == 8192) {
1204 hdw->fw1_state = FW1_STATE_RELOAD;
1205 return 0;
1206 }
1207
1208 return -EIO;
1209 }
1210
1211
1212 /*
1213 * pvr2_upload_firmware2()
1214 *
1215 * This uploads encoder firmware on endpoint 2.
1216 *
1217 */
1218
1219 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1220 {
1221 const struct firmware *fw_entry = NULL;
1222 void *fw_ptr;
1223 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1224 int actual_length;
1225 int ret = 0;
1226 int fwidx;
1227 static const char *fw_files[] = {
1228 CX2341X_FIRM_ENC_FILENAME,
1229 };
1230
1231 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1232 return 0;
1233 }
1234
1235 trace_firmware("pvr2_upload_firmware2");
1236
1237 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1238 ARRAY_SIZE(fw_files), fw_files);
1239 if (ret < 0) return ret;
1240 fwidx = ret;
1241 ret = 0;
1242 /* Since we're about to completely reinitialize the encoder,
1243 invalidate our cached copy of its configuration state. Next
1244 time we configure the encoder, then we'll fully configure it. */
1245 hdw->enc_cur_valid = 0;
1246
1247 /* Encoder is about to be reset so note that as far as we're
1248 concerned now, the encoder has never been run. */
1249 del_timer_sync(&hdw->encoder_run_timer);
1250 if (hdw->state_encoder_runok) {
1251 hdw->state_encoder_runok = 0;
1252 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1253 }
1254
1255 /* First prepare firmware loading */
1256 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1257 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1258 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1259 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1260 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1261 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1262 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1263 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1264 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1265 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1266 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1267 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1268 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1269 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1270 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1271 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1272 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1273 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1274
1275 if (ret) {
1276 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1277 "firmware2 upload prep failed, ret=%d",ret);
1278 release_firmware(fw_entry);
1279 goto done;
1280 }
1281
1282 /* Now send firmware */
1283
1284 fw_len = fw_entry->size;
1285
1286 if (fw_len % sizeof(u32)) {
1287 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1288 "size of %s firmware"
1289 " must be a multiple of %zu bytes",
1290 fw_files[fwidx],sizeof(u32));
1291 release_firmware(fw_entry);
1292 ret = -EINVAL;
1293 goto done;
1294 }
1295
1296 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1297 if (fw_ptr == NULL){
1298 release_firmware(fw_entry);
1299 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1300 "failed to allocate memory for firmware2 upload");
1301 ret = -ENOMEM;
1302 goto done;
1303 }
1304
1305 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1306
1307 fw_done = 0;
1308 for (fw_done = 0; fw_done < fw_len;) {
1309 bcnt = fw_len - fw_done;
1310 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1311 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1312 /* Usbsnoop log shows that we must swap bytes... */
1313 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1314 ((u32 *)fw_ptr)[icnt] =
1315 ___swab32(((u32 *)fw_ptr)[icnt]);
1316
1317 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1318 &actual_length, HZ);
1319 ret |= (actual_length != bcnt);
1320 if (ret) break;
1321 fw_done += bcnt;
1322 }
1323
1324 trace_firmware("upload of %s : %i / %i ",
1325 fw_files[fwidx],fw_done,fw_len);
1326
1327 kfree(fw_ptr);
1328 release_firmware(fw_entry);
1329
1330 if (ret) {
1331 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1332 "firmware2 upload transfer failure");
1333 goto done;
1334 }
1335
1336 /* Finish upload */
1337
1338 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1339 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1340 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1341
1342 if (ret) {
1343 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1344 "firmware2 upload post-proc failure");
1345 }
1346
1347 done:
1348 if (hdw->hdw_desc->signal_routing_scheme ==
1349 PVR2_ROUTING_SCHEME_GOTVIEW) {
1350 /* Ensure that GPIO 11 is set to output for GOTVIEW
1351 hardware. */
1352 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1353 }
1354 return ret;
1355 }
1356
1357
1358 static const char *pvr2_get_state_name(unsigned int st)
1359 {
1360 if (st < ARRAY_SIZE(pvr2_state_names)) {
1361 return pvr2_state_names[st];
1362 }
1363 return "???";
1364 }
1365
1366 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1367 {
1368 if (!hdw->decoder_ctrl) {
1369 if (!hdw->flag_decoder_missed) {
1370 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1371 "WARNING: No decoder present");
1372 hdw->flag_decoder_missed = !0;
1373 trace_stbit("flag_decoder_missed",
1374 hdw->flag_decoder_missed);
1375 }
1376 return -EIO;
1377 }
1378 hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt,enablefl);
1379 return 0;
1380 }
1381
1382
1383 void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
1384 {
1385 if (hdw->decoder_ctrl == ptr) return;
1386 hdw->decoder_ctrl = ptr;
1387 if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1388 hdw->flag_decoder_missed = 0;
1389 trace_stbit("flag_decoder_missed",
1390 hdw->flag_decoder_missed);
1391 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1392 "Decoder has appeared");
1393 pvr2_hdw_state_sched(hdw);
1394 }
1395 }
1396
1397
1398 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1399 {
1400 return hdw->master_state;
1401 }
1402
1403
1404 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1405 {
1406 if (!hdw->flag_tripped) return 0;
1407 hdw->flag_tripped = 0;
1408 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1409 "Clearing driver error statuss");
1410 return !0;
1411 }
1412
1413
1414 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1415 {
1416 int fl;
1417 LOCK_TAKE(hdw->big_lock); do {
1418 fl = pvr2_hdw_untrip_unlocked(hdw);
1419 } while (0); LOCK_GIVE(hdw->big_lock);
1420 if (fl) pvr2_hdw_state_sched(hdw);
1421 return 0;
1422 }
1423
1424
1425
1426
1427 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1428 {
1429 return hdw->state_pipeline_req != 0;
1430 }
1431
1432
1433 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1434 {
1435 int ret,st;
1436 LOCK_TAKE(hdw->big_lock); do {
1437 pvr2_hdw_untrip_unlocked(hdw);
1438 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1439 hdw->state_pipeline_req = enable_flag != 0;
1440 pvr2_trace(PVR2_TRACE_START_STOP,
1441 "/*--TRACE_STREAM--*/ %s",
1442 enable_flag ? "enable" : "disable");
1443 }
1444 pvr2_hdw_state_sched(hdw);
1445 } while (0); LOCK_GIVE(hdw->big_lock);
1446 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1447 if (enable_flag) {
1448 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1449 if (st != PVR2_STATE_READY) return -EIO;
1450 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1451 }
1452 }
1453 return 0;
1454 }
1455
1456
1457 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1458 {
1459 int fl;
1460 LOCK_TAKE(hdw->big_lock);
1461 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1462 hdw->desired_stream_type = config;
1463 hdw->state_pipeline_config = 0;
1464 trace_stbit("state_pipeline_config",
1465 hdw->state_pipeline_config);
1466 pvr2_hdw_state_sched(hdw);
1467 }
1468 LOCK_GIVE(hdw->big_lock);
1469 if (fl) return 0;
1470 return pvr2_hdw_wait(hdw,0);
1471 }
1472
1473
1474 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1475 {
1476 int unit_number = hdw->unit_number;
1477 int tp = -1;
1478 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1479 tp = tuner[unit_number];
1480 }
1481 if (tp < 0) return -EINVAL;
1482 hdw->tuner_type = tp;
1483 hdw->tuner_updated = !0;
1484 return 0;
1485 }
1486
1487
1488 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1489 {
1490 int unit_number = hdw->unit_number;
1491 int tp = 0;
1492 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1493 tp = video_std[unit_number];
1494 if (tp) return tp;
1495 }
1496 return 0;
1497 }
1498
1499
1500 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1501 {
1502 int unit_number = hdw->unit_number;
1503 int tp = 0;
1504 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1505 tp = tolerance[unit_number];
1506 }
1507 return tp;
1508 }
1509
1510
1511 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1512 {
1513 /* Try a harmless request to fetch the eeprom's address over
1514 endpoint 1. See what happens. Only the full FX2 image can
1515 respond to this. If this probe fails then likely the FX2
1516 firmware needs be loaded. */
1517 int result;
1518 LOCK_TAKE(hdw->ctl_lock); do {
1519 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1520 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1521 hdw->cmd_buffer,1,
1522 hdw->cmd_buffer,1);
1523 if (result < 0) break;
1524 } while(0); LOCK_GIVE(hdw->ctl_lock);
1525 if (result) {
1526 pvr2_trace(PVR2_TRACE_INIT,
1527 "Probe of device endpoint 1 result status %d",
1528 result);
1529 } else {
1530 pvr2_trace(PVR2_TRACE_INIT,
1531 "Probe of device endpoint 1 succeeded");
1532 }
1533 return result == 0;
1534 }
1535
1536 struct pvr2_std_hack {
1537 v4l2_std_id pat; /* Pattern to match */
1538 v4l2_std_id msk; /* Which bits we care about */
1539 v4l2_std_id std; /* What additional standards or default to set */
1540 };
1541
1542 /* This data structure labels specific combinations of standards from
1543 tveeprom that we'll try to recognize. If we recognize one, then assume
1544 a specified default standard to use. This is here because tveeprom only
1545 tells us about available standards not the intended default standard (if
1546 any) for the device in question. We guess the default based on what has
1547 been reported as available. Note that this is only for guessing a
1548 default - which can always be overridden explicitly - and if the user
1549 has otherwise named a default then that default will always be used in
1550 place of this table. */
1551 static const struct pvr2_std_hack std_eeprom_maps[] = {
1552 { /* PAL(B/G) */
1553 .pat = V4L2_STD_B|V4L2_STD_GH,
1554 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1555 },
1556 { /* NTSC(M) */
1557 .pat = V4L2_STD_MN,
1558 .std = V4L2_STD_NTSC_M,
1559 },
1560 { /* PAL(I) */
1561 .pat = V4L2_STD_PAL_I,
1562 .std = V4L2_STD_PAL_I,
1563 },
1564 { /* SECAM(L/L') */
1565 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1566 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1567 },
1568 { /* PAL(D/D1/K) */
1569 .pat = V4L2_STD_DK,
1570 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1571 },
1572 };
1573
1574 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1575 {
1576 char buf[40];
1577 unsigned int bcnt;
1578 v4l2_std_id std1,std2,std3;
1579
1580 std1 = get_default_standard(hdw);
1581 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1582
1583 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1584 pvr2_trace(PVR2_TRACE_STD,
1585 "Supported video standard(s) reported available"
1586 " in hardware: %.*s",
1587 bcnt,buf);
1588
1589 hdw->std_mask_avail = hdw->std_mask_eeprom;
1590
1591 std2 = (std1|std3) & ~hdw->std_mask_avail;
1592 if (std2) {
1593 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1594 pvr2_trace(PVR2_TRACE_STD,
1595 "Expanding supported video standards"
1596 " to include: %.*s",
1597 bcnt,buf);
1598 hdw->std_mask_avail |= std2;
1599 }
1600
1601 pvr2_hdw_internal_set_std_avail(hdw);
1602
1603 if (std1) {
1604 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1605 pvr2_trace(PVR2_TRACE_STD,
1606 "Initial video standard forced to %.*s",
1607 bcnt,buf);
1608 hdw->std_mask_cur = std1;
1609 hdw->std_dirty = !0;
1610 pvr2_hdw_internal_find_stdenum(hdw);
1611 return;
1612 }
1613 if (std3) {
1614 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1615 pvr2_trace(PVR2_TRACE_STD,
1616 "Initial video standard"
1617 " (determined by device type): %.*s",bcnt,buf);
1618 hdw->std_mask_cur = std3;
1619 hdw->std_dirty = !0;
1620 pvr2_hdw_internal_find_stdenum(hdw);
1621 return;
1622 }
1623
1624 {
1625 unsigned int idx;
1626 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1627 if (std_eeprom_maps[idx].msk ?
1628 ((std_eeprom_maps[idx].pat ^
1629 hdw->std_mask_eeprom) &
1630 std_eeprom_maps[idx].msk) :
1631 (std_eeprom_maps[idx].pat !=
1632 hdw->std_mask_eeprom)) continue;
1633 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1634 std_eeprom_maps[idx].std);
1635 pvr2_trace(PVR2_TRACE_STD,
1636 "Initial video standard guessed as %.*s",
1637 bcnt,buf);
1638 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1639 hdw->std_dirty = !0;
1640 pvr2_hdw_internal_find_stdenum(hdw);
1641 return;
1642 }
1643 }
1644
1645 if (hdw->std_enum_cnt > 1) {
1646 // Autoselect the first listed standard
1647 hdw->std_enum_cur = 1;
1648 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1649 hdw->std_dirty = !0;
1650 pvr2_trace(PVR2_TRACE_STD,
1651 "Initial video standard auto-selected to %s",
1652 hdw->std_defs[hdw->std_enum_cur-1].name);
1653 return;
1654 }
1655
1656 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1657 "Unable to select a viable initial video standard");
1658 }
1659
1660
1661 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1662 {
1663 int ret;
1664 unsigned int idx;
1665 struct pvr2_ctrl *cptr;
1666 int reloadFl = 0;
1667 if (hdw->hdw_desc->fx2_firmware.cnt) {
1668 if (!reloadFl) {
1669 reloadFl =
1670 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1671 == 0);
1672 if (reloadFl) {
1673 pvr2_trace(PVR2_TRACE_INIT,
1674 "USB endpoint config looks strange"
1675 "; possibly firmware needs to be"
1676 " loaded");
1677 }
1678 }
1679 if (!reloadFl) {
1680 reloadFl = !pvr2_hdw_check_firmware(hdw);
1681 if (reloadFl) {
1682 pvr2_trace(PVR2_TRACE_INIT,
1683 "Check for FX2 firmware failed"
1684 "; possibly firmware needs to be"
1685 " loaded");
1686 }
1687 }
1688 if (reloadFl) {
1689 if (pvr2_upload_firmware1(hdw) != 0) {
1690 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1691 "Failure uploading firmware1");
1692 }
1693 return;
1694 }
1695 }
1696 hdw->fw1_state = FW1_STATE_OK;
1697
1698 if (initusbreset) {
1699 pvr2_hdw_device_reset(hdw);
1700 }
1701 if (!pvr2_hdw_dev_ok(hdw)) return;
1702
1703 for (idx = 0; idx < hdw->hdw_desc->client_modules.cnt; idx++) {
1704 request_module(hdw->hdw_desc->client_modules.lst[idx]);
1705 }
1706
1707 if (!hdw->hdw_desc->flag_no_powerup) {
1708 pvr2_hdw_cmd_powerup(hdw);
1709 if (!pvr2_hdw_dev_ok(hdw)) return;
1710 }
1711
1712 // This step MUST happen after the earlier powerup step.
1713 pvr2_i2c_core_init(hdw);
1714 if (!pvr2_hdw_dev_ok(hdw)) return;
1715
1716 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1717 cptr = hdw->controls + idx;
1718 if (cptr->info->skip_init) continue;
1719 if (!cptr->info->set_value) continue;
1720 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1721 }
1722
1723 /* Set up special default values for the television and radio
1724 frequencies here. It's not really important what these defaults
1725 are, but I set them to something usable in the Chicago area just
1726 to make driver testing a little easier. */
1727
1728 hdw->freqValTelevision = default_tv_freq;
1729 hdw->freqValRadio = default_radio_freq;
1730
1731 // Do not use pvr2_reset_ctl_endpoints() here. It is not
1732 // thread-safe against the normal pvr2_send_request() mechanism.
1733 // (We should make it thread safe).
1734
1735 if (hdw->hdw_desc->flag_has_hauppauge_rom) {
1736 ret = pvr2_hdw_get_eeprom_addr(hdw);
1737 if (!pvr2_hdw_dev_ok(hdw)) return;
1738 if (ret < 0) {
1739 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1740 "Unable to determine location of eeprom,"
1741 " skipping");
1742 } else {
1743 hdw->eeprom_addr = ret;
1744 pvr2_eeprom_analyze(hdw);
1745 if (!pvr2_hdw_dev_ok(hdw)) return;
1746 }
1747 } else {
1748 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
1749 hdw->tuner_updated = !0;
1750 hdw->std_mask_eeprom = V4L2_STD_ALL;
1751 }
1752
1753 pvr2_hdw_setup_std(hdw);
1754
1755 if (!get_default_tuner_type(hdw)) {
1756 pvr2_trace(PVR2_TRACE_INIT,
1757 "pvr2_hdw_setup: Tuner type overridden to %d",
1758 hdw->tuner_type);
1759 }
1760
1761 pvr2_i2c_core_check_stale(hdw);
1762 hdw->tuner_updated = 0;
1763
1764 if (!pvr2_hdw_dev_ok(hdw)) return;
1765
1766 if (hdw->hdw_desc->signal_routing_scheme ==
1767 PVR2_ROUTING_SCHEME_GOTVIEW) {
1768 /* Ensure that GPIO 11 is set to output for GOTVIEW
1769 hardware. */
1770 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1771 }
1772
1773 pvr2_hdw_commit_setup(hdw);
1774
1775 hdw->vid_stream = pvr2_stream_create();
1776 if (!pvr2_hdw_dev_ok(hdw)) return;
1777 pvr2_trace(PVR2_TRACE_INIT,
1778 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1779 if (hdw->vid_stream) {
1780 idx = get_default_error_tolerance(hdw);
1781 if (idx) {
1782 pvr2_trace(PVR2_TRACE_INIT,
1783 "pvr2_hdw_setup: video stream %p"
1784 " setting tolerance %u",
1785 hdw->vid_stream,idx);
1786 }
1787 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1788 PVR2_VID_ENDPOINT,idx);
1789 }
1790
1791 if (!pvr2_hdw_dev_ok(hdw)) return;
1792
1793 hdw->flag_init_ok = !0;
1794
1795 pvr2_hdw_state_sched(hdw);
1796 }
1797
1798
1799 /* Set up the structure and attempt to put the device into a usable state.
1800 This can be a time-consuming operation, which is why it is not done
1801 internally as part of the create() step. */
1802 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
1803 {
1804 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
1805 do {
1806 pvr2_hdw_setup_low(hdw);
1807 pvr2_trace(PVR2_TRACE_INIT,
1808 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
1809 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
1810 if (pvr2_hdw_dev_ok(hdw)) {
1811 if (hdw->flag_init_ok) {
1812 pvr2_trace(
1813 PVR2_TRACE_INFO,
1814 "Device initialization"
1815 " completed successfully.");
1816 break;
1817 }
1818 if (hdw->fw1_state == FW1_STATE_RELOAD) {
1819 pvr2_trace(
1820 PVR2_TRACE_INFO,
1821 "Device microcontroller firmware"
1822 " (re)loaded; it should now reset"
1823 " and reconnect.");
1824 break;
1825 }
1826 pvr2_trace(
1827 PVR2_TRACE_ERROR_LEGS,
1828 "Device initialization was not successful.");
1829 if (hdw->fw1_state == FW1_STATE_MISSING) {
1830 pvr2_trace(
1831 PVR2_TRACE_ERROR_LEGS,
1832 "Giving up since device"
1833 " microcontroller firmware"
1834 " appears to be missing.");
1835 break;
1836 }
1837 }
1838 if (procreload) {
1839 pvr2_trace(
1840 PVR2_TRACE_ERROR_LEGS,
1841 "Attempting pvrusb2 recovery by reloading"
1842 " primary firmware.");
1843 pvr2_trace(
1844 PVR2_TRACE_ERROR_LEGS,
1845 "If this works, device should disconnect"
1846 " and reconnect in a sane state.");
1847 hdw->fw1_state = FW1_STATE_UNKNOWN;
1848 pvr2_upload_firmware1(hdw);
1849 } else {
1850 pvr2_trace(
1851 PVR2_TRACE_ERROR_LEGS,
1852 "***WARNING*** pvrusb2 device hardware"
1853 " appears to be jammed"
1854 " and I can't clear it.");
1855 pvr2_trace(
1856 PVR2_TRACE_ERROR_LEGS,
1857 "You might need to power cycle"
1858 " the pvrusb2 device"
1859 " in order to recover.");
1860 }
1861 } while (0);
1862 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
1863 }
1864
1865
1866 /* Perform second stage initialization. Set callback pointer first so that
1867 we can avoid a possible initialization race (if the kernel thread runs
1868 before the callback has been set). */
1869 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
1870 void (*callback_func)(void *),
1871 void *callback_data)
1872 {
1873 LOCK_TAKE(hdw->big_lock); do {
1874 if (hdw->flag_disconnected) {
1875 /* Handle a race here: If we're already
1876 disconnected by this point, then give up. If we
1877 get past this then we'll remain connected for
1878 the duration of initialization since the entire
1879 initialization sequence is now protected by the
1880 big_lock. */
1881 break;
1882 }
1883 hdw->state_data = callback_data;
1884 hdw->state_func = callback_func;
1885 pvr2_hdw_setup(hdw);
1886 } while (0); LOCK_GIVE(hdw->big_lock);
1887 return hdw->flag_init_ok;
1888 }
1889
1890
1891 /* Create, set up, and return a structure for interacting with the
1892 underlying hardware. */
1893 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1894 const struct usb_device_id *devid)
1895 {
1896 unsigned int idx,cnt1,cnt2,m;
1897 struct pvr2_hdw *hdw;
1898 int valid_std_mask;
1899 struct pvr2_ctrl *cptr;
1900 const struct pvr2_device_desc *hdw_desc;
1901 __u8 ifnum;
1902 struct v4l2_queryctrl qctrl;
1903 struct pvr2_ctl_info *ciptr;
1904
1905 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
1906
1907 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
1908 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
1909 hdw,hdw_desc->description);
1910 if (!hdw) goto fail;
1911
1912 init_timer(&hdw->quiescent_timer);
1913 hdw->quiescent_timer.data = (unsigned long)hdw;
1914 hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
1915
1916 init_timer(&hdw->encoder_wait_timer);
1917 hdw->encoder_wait_timer.data = (unsigned long)hdw;
1918 hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
1919
1920 init_timer(&hdw->encoder_run_timer);
1921 hdw->encoder_run_timer.data = (unsigned long)hdw;
1922 hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
1923
1924 hdw->master_state = PVR2_STATE_DEAD;
1925
1926 init_waitqueue_head(&hdw->state_wait_data);
1927
1928 hdw->tuner_signal_stale = !0;
1929 cx2341x_fill_defaults(&hdw->enc_ctl_state);
1930
1931 /* Calculate which inputs are OK */
1932 m = 0;
1933 if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
1934 if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
1935 m |= 1 << PVR2_CVAL_INPUT_DTV;
1936 }
1937 if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
1938 if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
1939 if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
1940 hdw->input_avail_mask = m;
1941 hdw->input_allowed_mask = hdw->input_avail_mask;
1942
1943 /* If not a hybrid device, pathway_state never changes. So
1944 initialize it here to what it should forever be. */
1945 if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
1946 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
1947 } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
1948 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
1949 }
1950
1951 hdw->control_cnt = CTRLDEF_COUNT;
1952 hdw->control_cnt += MPEGDEF_COUNT;
1953 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
1954 GFP_KERNEL);
1955 if (!hdw->controls) goto fail;
1956 hdw->hdw_desc = hdw_desc;
1957 for (idx = 0; idx < hdw->control_cnt; idx++) {
1958 cptr = hdw->controls + idx;
1959 cptr->hdw = hdw;
1960 }
1961 for (idx = 0; idx < 32; idx++) {
1962 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1963 }
1964 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1965 cptr = hdw->controls + idx;
1966 cptr->info = control_defs+idx;
1967 }
1968
1969 /* Ensure that default input choice is a valid one. */
1970 m = hdw->input_avail_mask;
1971 if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
1972 if (!((1 << idx) & m)) continue;
1973 hdw->input_val = idx;
1974 break;
1975 }
1976
1977 /* Define and configure additional controls from cx2341x module. */
1978 hdw->mpeg_ctrl_info = kzalloc(
1979 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
1980 if (!hdw->mpeg_ctrl_info) goto fail;
1981 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
1982 cptr = hdw->controls + idx + CTRLDEF_COUNT;
1983 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
1984 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
1985 ciptr->name = mpeg_ids[idx].strid;
1986 ciptr->v4l_id = mpeg_ids[idx].id;
1987 ciptr->skip_init = !0;
1988 ciptr->get_value = ctrl_cx2341x_get;
1989 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
1990 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
1991 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
1992 qctrl.id = ciptr->v4l_id;
1993 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
1994 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
1995 ciptr->set_value = ctrl_cx2341x_set;
1996 }
1997 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
1998 PVR2_CTLD_INFO_DESC_SIZE);
1999 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2000 ciptr->default_value = qctrl.default_value;
2001 switch (qctrl.type) {
2002 default:
2003 case V4L2_CTRL_TYPE_INTEGER:
2004 ciptr->type = pvr2_ctl_int;
2005 ciptr->def.type_int.min_value = qctrl.minimum;
2006 ciptr->def.type_int.max_value = qctrl.maximum;
2007 break;
2008 case V4L2_CTRL_TYPE_BOOLEAN:
2009 ciptr->type = pvr2_ctl_bool;
2010 break;
2011 case V4L2_CTRL_TYPE_MENU:
2012 ciptr->type = pvr2_ctl_enum;
2013 ciptr->def.type_enum.value_names =
2014 cx2341x_ctrl_get_menu(ciptr->v4l_id);
2015 for (cnt1 = 0;
2016 ciptr->def.type_enum.value_names[cnt1] != NULL;
2017 cnt1++) { }
2018 ciptr->def.type_enum.count = cnt1;
2019 break;
2020 }
2021 cptr->info = ciptr;
2022 }
2023
2024 // Initialize video standard enum dynamic control
2025 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2026 if (cptr) {
2027 memcpy(&hdw->std_info_enum,cptr->info,
2028 sizeof(hdw->std_info_enum));
2029 cptr->info = &hdw->std_info_enum;
2030
2031 }
2032 // Initialize control data regarding video standard masks
2033 valid_std_mask = pvr2_std_get_usable();
2034 for (idx = 0; idx < 32; idx++) {
2035 if (!(valid_std_mask & (1 << idx))) continue;
2036 cnt1 = pvr2_std_id_to_str(
2037 hdw->std_mask_names[idx],
2038 sizeof(hdw->std_mask_names[idx])-1,
2039 1 << idx);
2040 hdw->std_mask_names[idx][cnt1] = 0;
2041 }
2042 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2043 if (cptr) {
2044 memcpy(&hdw->std_info_avail,cptr->info,
2045 sizeof(hdw->std_info_avail));
2046 cptr->info = &hdw->std_info_avail;
2047 hdw->std_info_avail.def.type_bitmask.bit_names =
2048 hdw->std_mask_ptrs;
2049 hdw->std_info_avail.def.type_bitmask.valid_bits =
2050 valid_std_mask;
2051 }
2052 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2053 if (cptr) {
2054 memcpy(&hdw->std_info_cur,cptr->info,
2055 sizeof(hdw->std_info_cur));
2056 cptr->info = &hdw->std_info_cur;
2057 hdw->std_info_cur.def.type_bitmask.bit_names =
2058 hdw->std_mask_ptrs;
2059 hdw->std_info_avail.def.type_bitmask.valid_bits =
2060 valid_std_mask;
2061 }
2062
2063 hdw->eeprom_addr = -1;
2064 hdw->unit_number = -1;
2065 hdw->v4l_minor_number_video = -1;
2066 hdw->v4l_minor_number_vbi = -1;
2067 hdw->v4l_minor_number_radio = -1;
2068 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2069 if (!hdw->ctl_write_buffer) goto fail;
2070 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2071 if (!hdw->ctl_read_buffer) goto fail;
2072 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2073 if (!hdw->ctl_write_urb) goto fail;
2074 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2075 if (!hdw->ctl_read_urb) goto fail;
2076
2077 mutex_lock(&pvr2_unit_mtx); do {
2078 for (idx = 0; idx < PVR_NUM; idx++) {
2079 if (unit_pointers[idx]) continue;
2080 hdw->unit_number = idx;
2081 unit_pointers[idx] = hdw;
2082 break;
2083 }
2084 } while (0); mutex_unlock(&pvr2_unit_mtx);
2085
2086 cnt1 = 0;
2087 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2088 cnt1 += cnt2;
2089 if (hdw->unit_number >= 0) {
2090 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2091 ('a' + hdw->unit_number));
2092 cnt1 += cnt2;
2093 }
2094 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2095 hdw->name[cnt1] = 0;
2096
2097 hdw->workqueue = create_singlethread_workqueue(hdw->name);
2098 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2099 INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
2100
2101 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2102 hdw->unit_number,hdw->name);
2103
2104 hdw->tuner_type = -1;
2105 hdw->flag_ok = !0;
2106
2107 hdw->usb_intf = intf;
2108 hdw->usb_dev = interface_to_usbdev(intf);
2109
2110 scnprintf(hdw->bus_info,sizeof(hdw->bus_info),
2111 "usb %s address %d",
2112 hdw->usb_dev->dev.bus_id,
2113 hdw->usb_dev->devnum);
2114
2115 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2116 usb_set_interface(hdw->usb_dev,ifnum,0);
2117
2118 mutex_init(&hdw->ctl_lock_mutex);
2119 mutex_init(&hdw->big_lock_mutex);
2120
2121 return hdw;
2122 fail:
2123 if (hdw) {
2124 del_timer_sync(&hdw->quiescent_timer);
2125 del_timer_sync(&hdw->encoder_run_timer);
2126 del_timer_sync(&hdw->encoder_wait_timer);
2127 if (hdw->workqueue) {
2128 flush_workqueue(hdw->workqueue);
2129 destroy_workqueue(hdw->workqueue);
2130 hdw->workqueue = NULL;
2131 }
2132 usb_free_urb(hdw->ctl_read_urb);
2133 usb_free_urb(hdw->ctl_write_urb);
2134 kfree(hdw->ctl_read_buffer);
2135 kfree(hdw->ctl_write_buffer);
2136 kfree(hdw->controls);
2137 kfree(hdw->mpeg_ctrl_info);
2138 kfree(hdw->std_defs);
2139 kfree(hdw->std_enum_names);
2140 kfree(hdw);
2141 }
2142 return NULL;
2143 }
2144
2145
2146 /* Remove _all_ associations between this driver and the underlying USB
2147 layer. */
2148 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2149 {
2150 if (hdw->flag_disconnected) return;
2151 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2152 if (hdw->ctl_read_urb) {
2153 usb_kill_urb(hdw->ctl_read_urb);
2154 usb_free_urb(hdw->ctl_read_urb);
2155 hdw->ctl_read_urb = NULL;
2156 }
2157 if (hdw->ctl_write_urb) {
2158 usb_kill_urb(hdw->ctl_write_urb);
2159 usb_free_urb(hdw->ctl_write_urb);
2160 hdw->ctl_write_urb = NULL;
2161 }
2162 if (hdw->ctl_read_buffer) {
2163 kfree(hdw->ctl_read_buffer);
2164 hdw->ctl_read_buffer = NULL;
2165 }
2166 if (hdw->ctl_write_buffer) {
2167 kfree(hdw->ctl_write_buffer);
2168 hdw->ctl_write_buffer = NULL;
2169 }
2170 hdw->flag_disconnected = !0;
2171 hdw->usb_dev = NULL;
2172 hdw->usb_intf = NULL;
2173 pvr2_hdw_render_useless(hdw);
2174 }
2175
2176
2177 /* Destroy hardware interaction structure */
2178 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2179 {
2180 if (!hdw) return;
2181 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2182 if (hdw->workqueue) {
2183 flush_workqueue(hdw->workqueue);
2184 destroy_workqueue(hdw->workqueue);
2185 hdw->workqueue = NULL;
2186 }
2187 del_timer_sync(&hdw->quiescent_timer);
2188 del_timer_sync(&hdw->encoder_run_timer);
2189 del_timer_sync(&hdw->encoder_wait_timer);
2190 if (hdw->fw_buffer) {
2191 kfree(hdw->fw_buffer);
2192 hdw->fw_buffer = NULL;
2193 }
2194 if (hdw->vid_stream) {
2195 pvr2_stream_destroy(hdw->vid_stream);
2196 hdw->vid_stream = NULL;
2197 }
2198 if (hdw->decoder_ctrl) {
2199 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2200 }
2201 pvr2_i2c_core_done(hdw);
2202 pvr2_hdw_remove_usb_stuff(hdw);
2203 mutex_lock(&pvr2_unit_mtx); do {
2204 if ((hdw->unit_number >= 0) &&
2205 (hdw->unit_number < PVR_NUM) &&
2206 (unit_pointers[hdw->unit_number] == hdw)) {
2207 unit_pointers[hdw->unit_number] = NULL;
2208 }
2209 } while (0); mutex_unlock(&pvr2_unit_mtx);
2210 kfree(hdw->controls);
2211 kfree(hdw->mpeg_ctrl_info);
2212 kfree(hdw->std_defs);
2213 kfree(hdw->std_enum_names);
2214 kfree(hdw);
2215 }
2216
2217
2218 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2219 {
2220 return (hdw && hdw->flag_ok);
2221 }
2222
2223
2224 /* Called when hardware has been unplugged */
2225 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2226 {
2227 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2228 LOCK_TAKE(hdw->big_lock);
2229 LOCK_TAKE(hdw->ctl_lock);
2230 pvr2_hdw_remove_usb_stuff(hdw);
2231 LOCK_GIVE(hdw->ctl_lock);
2232 LOCK_GIVE(hdw->big_lock);
2233 }
2234
2235
2236 // Attempt to autoselect an appropriate value for std_enum_cur given
2237 // whatever is currently in std_mask_cur
2238 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2239 {
2240 unsigned int idx;
2241 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2242 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2243 hdw->std_enum_cur = idx;
2244 return;
2245 }
2246 }
2247 hdw->std_enum_cur = 0;
2248 }
2249
2250
2251 // Calculate correct set of enumerated standards based on currently known
2252 // set of available standards bits.
2253 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2254 {
2255 struct v4l2_standard *newstd;
2256 unsigned int std_cnt;
2257 unsigned int idx;
2258
2259 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2260
2261 if (hdw->std_defs) {
2262 kfree(hdw->std_defs);
2263 hdw->std_defs = NULL;
2264 }
2265 hdw->std_enum_cnt = 0;
2266 if (hdw->std_enum_names) {
2267 kfree(hdw->std_enum_names);
2268 hdw->std_enum_names = NULL;
2269 }
2270
2271 if (!std_cnt) {
2272 pvr2_trace(
2273 PVR2_TRACE_ERROR_LEGS,
2274 "WARNING: Failed to identify any viable standards");
2275 }
2276 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2277 hdw->std_enum_names[0] = "none";
2278 for (idx = 0; idx < std_cnt; idx++) {
2279 hdw->std_enum_names[idx+1] =
2280 newstd[idx].name;
2281 }
2282 // Set up the dynamic control for this standard
2283 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2284 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2285 hdw->std_defs = newstd;
2286 hdw->std_enum_cnt = std_cnt+1;
2287 hdw->std_enum_cur = 0;
2288 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2289 }
2290
2291
2292 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2293 struct v4l2_standard *std,
2294 unsigned int idx)
2295 {
2296 int ret = -EINVAL;
2297 if (!idx) return ret;
2298 LOCK_TAKE(hdw->big_lock); do {
2299 if (idx >= hdw->std_enum_cnt) break;
2300 idx--;
2301 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2302 ret = 0;
2303 } while (0); LOCK_GIVE(hdw->big_lock);
2304 return ret;
2305 }
2306
2307
2308 /* Get the number of defined controls */
2309 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2310 {
2311 return hdw->control_cnt;
2312 }
2313
2314
2315 /* Retrieve a control handle given its index (0..count-1) */
2316 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2317 unsigned int idx)
2318 {
2319 if (idx >= hdw->control_cnt) return NULL;
2320 return hdw->controls + idx;
2321 }
2322
2323
2324 /* Retrieve a control handle given its index (0..count-1) */
2325 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2326 unsigned int ctl_id)
2327 {
2328 struct pvr2_ctrl *cptr;
2329 unsigned int idx;
2330 int i;
2331
2332 /* This could be made a lot more efficient, but for now... */
2333 for (idx = 0; idx < hdw->control_cnt; idx++) {
2334 cptr = hdw->controls + idx;
2335 i = cptr->info->internal_id;
2336 if (i && (i == ctl_id)) return cptr;
2337 }
2338 return NULL;
2339 }
2340
2341
2342 /* Given a V4L ID, retrieve the control structure associated with it. */
2343 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2344 {
2345 struct pvr2_ctrl *cptr;
2346 unsigned int idx;
2347 int i;
2348
2349 /* This could be made a lot more efficient, but for now... */
2350 for (idx = 0; idx < hdw->control_cnt; idx++) {
2351 cptr = hdw->controls + idx;
2352 i = cptr->info->v4l_id;
2353 if (i && (i == ctl_id)) return cptr;
2354 }
2355 return NULL;
2356 }
2357
2358
2359 /* Given a V4L ID for its immediate predecessor, retrieve the control
2360 structure associated with it. */
2361 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2362 unsigned int ctl_id)
2363 {
2364 struct pvr2_ctrl *cptr,*cp2;
2365 unsigned int idx;
2366 int i;
2367
2368 /* This could be made a lot more efficient, but for now... */
2369 cp2 = NULL;
2370 for (idx = 0; idx < hdw->control_cnt; idx++) {
2371 cptr = hdw->controls + idx;
2372 i = cptr->info->v4l_id;
2373 if (!i) continue;
2374 if (i <= ctl_id) continue;
2375 if (cp2 && (cp2->info->v4l_id < i)) continue;
2376 cp2 = cptr;
2377 }
2378 return cp2;
2379 return NULL;
2380 }
2381
2382
2383 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2384 {
2385 switch (tp) {
2386 case pvr2_ctl_int: return "integer";
2387 case pvr2_ctl_enum: return "enum";
2388 case pvr2_ctl_bool: return "boolean";
2389 case pvr2_ctl_bitmask: return "bitmask";
2390 }
2391 return "";
2392 }
2393
2394
2395 /* Figure out if we need to commit control changes. If so, mark internal
2396 state flags to indicate this fact and return true. Otherwise do nothing
2397 else and return false. */
2398 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
2399 {
2400 unsigned int idx;
2401 struct pvr2_ctrl *cptr;
2402 int value;
2403 int commit_flag = 0;
2404 char buf[100];
2405 unsigned int bcnt,ccnt;
2406
2407 for (idx = 0; idx < hdw->control_cnt; idx++) {
2408 cptr = hdw->controls + idx;
2409 if (!cptr->info->is_dirty) continue;
2410 if (!cptr->info->is_dirty(cptr)) continue;
2411 commit_flag = !0;
2412
2413 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
2414 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2415 cptr->info->name);
2416 value = 0;
2417 cptr->info->get_value(cptr,&value);
2418 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2419 buf+bcnt,
2420 sizeof(buf)-bcnt,&ccnt);
2421 bcnt += ccnt;
2422 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2423 get_ctrl_typename(cptr->info->type));
2424 pvr2_trace(PVR2_TRACE_CTL,
2425 "/*--TRACE_COMMIT--*/ %.*s",
2426 bcnt,buf);
2427 }
2428
2429 if (!commit_flag) {
2430 /* Nothing has changed */
2431 return 0;
2432 }
2433
2434 hdw->state_pipeline_config = 0;
2435 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2436 pvr2_hdw_state_sched(hdw);
2437
2438 return !0;
2439 }
2440
2441
2442 /* Perform all operations needed to commit all control changes. This must
2443 be performed in synchronization with the pipeline state and is thus
2444 expected to be called as part of the driver's worker thread. Return
2445 true if commit successful, otherwise return false to indicate that
2446 commit isn't possible at this time. */
2447 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
2448 {
2449 unsigned int idx;
2450 struct pvr2_ctrl *cptr;
2451 int disruptive_change;
2452
2453 /* When video standard changes, reset the hres and vres values -
2454 but if the user has pending changes there, then let the changes
2455 take priority. */
2456 if (hdw->std_dirty) {
2457 /* Rewrite the vertical resolution to be appropriate to the
2458 video standard that has been selected. */
2459 int nvres;
2460 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2461 nvres = 480;
2462 } else {
2463 nvres = 576;
2464 }
2465 if (nvres != hdw->res_ver_val) {
2466 hdw->res_ver_val = nvres;
2467 hdw->res_ver_dirty = !0;
2468 }
2469 }
2470
2471 if (hdw->input_dirty && hdw->state_pathway_ok &&
2472 (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
2473 PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
2474 hdw->pathway_state)) {
2475 /* Change of mode being asked for... */
2476 hdw->state_pathway_ok = 0;
2477 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
2478 }
2479 if (!hdw->state_pathway_ok) {
2480 /* Can't commit anything until pathway is ok. */
2481 return 0;
2482 }
2483 /* If any of the below has changed, then we can't do the update
2484 while the pipeline is running. Pipeline must be paused first
2485 and decoder -> encoder connection be made quiescent before we
2486 can proceed. */
2487 disruptive_change =
2488 (hdw->std_dirty ||
2489 hdw->enc_unsafe_stale ||
2490 hdw->srate_dirty ||
2491 hdw->res_ver_dirty ||
2492 hdw->res_hor_dirty ||
2493 hdw->input_dirty ||
2494 (hdw->active_stream_type != hdw->desired_stream_type));
2495 if (disruptive_change && !hdw->state_pipeline_idle) {
2496 /* Pipeline is not idle; we can't proceed. Arrange to
2497 cause pipeline to stop so that we can try this again
2498 later.... */
2499 hdw->state_pipeline_pause = !0;
2500 return 0;
2501 }
2502
2503 if (hdw->srate_dirty) {
2504 /* Write new sample rate into control structure since
2505 * the master copy is stale. We must track srate
2506 * separate from the mpeg control structure because
2507 * other logic also uses this value. */
2508 struct v4l2_ext_controls cs;
2509 struct v4l2_ext_control c1;
2510 memset(&cs,0,sizeof(cs));
2511 memset(&c1,0,sizeof(c1));
2512 cs.controls = &c1;
2513 cs.count = 1;
2514 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
2515 c1.value = hdw->srate_val;
2516 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
2517 }
2518
2519 /* Scan i2c core at this point - before we clear all the dirty
2520 bits. Various parts of the i2c core will notice dirty bits as
2521 appropriate and arrange to broadcast or directly send updates to
2522 the client drivers in order to keep everything in sync */
2523 pvr2_i2c_core_check_stale(hdw);
2524
2525 for (idx = 0; idx < hdw->control_cnt; idx++) {
2526 cptr = hdw->controls + idx;
2527 if (!cptr->info->clear_dirty) continue;
2528 cptr->info->clear_dirty(cptr);
2529 }
2530
2531 if (hdw->active_stream_type != hdw->desired_stream_type) {
2532 /* Handle any side effects of stream config here */
2533 hdw->active_stream_type = hdw->desired_stream_type;
2534 }
2535
2536 if (hdw->hdw_desc->signal_routing_scheme ==
2537 PVR2_ROUTING_SCHEME_GOTVIEW) {
2538 u32 b;
2539 /* Handle GOTVIEW audio switching */
2540 pvr2_hdw_gpio_get_out(hdw,&b);
2541 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2542 /* Set GPIO 11 */
2543 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
2544 } else {
2545 /* Clear GPIO 11 */
2546 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
2547 }
2548 }
2549
2550 /* Now execute i2c core update */
2551 pvr2_i2c_core_sync(hdw);
2552
2553 if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
2554 hdw->state_encoder_run) {
2555 /* If encoder isn't running or it can't be touched, then
2556 this will get worked out later when we start the
2557 encoder. */
2558 if (pvr2_encoder_adjust(hdw) < 0) return !0;
2559 }
2560
2561 hdw->state_pipeline_config = !0;
2562 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2563 return !0;
2564 }
2565
2566
2567 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2568 {
2569 int fl;
2570 LOCK_TAKE(hdw->big_lock);
2571 fl = pvr2_hdw_commit_setup(hdw);
2572 LOCK_GIVE(hdw->big_lock);
2573 if (!fl) return 0;
2574 return pvr2_hdw_wait(hdw,0);
2575 }
2576
2577
2578 static void pvr2_hdw_worker_i2c(struct work_struct *work)
2579 {
2580 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
2581 LOCK_TAKE(hdw->big_lock); do {
2582 pvr2_i2c_core_sync(hdw);
2583 } while (0); LOCK_GIVE(hdw->big_lock);
2584 }
2585
2586
2587 static void pvr2_hdw_worker_poll(struct work_struct *work)
2588 {
2589 int fl = 0;
2590 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
2591 LOCK_TAKE(hdw->big_lock); do {
2592 fl = pvr2_hdw_state_eval(hdw);
2593 } while (0); LOCK_GIVE(hdw->big_lock);
2594 if (fl && hdw->state_func) {
2595 hdw->state_func(hdw->state_data);
2596 }
2597 }
2598
2599
2600 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
2601 {
2602 return wait_event_interruptible(
2603 hdw->state_wait_data,
2604 (hdw->state_stale == 0) &&
2605 (!state || (hdw->master_state != state)));
2606 }
2607
2608
2609 /* Return name for this driver instance */
2610 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2611 {
2612 return hdw->name;
2613 }
2614
2615
2616 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
2617 {
2618 return hdw->hdw_desc->description;
2619 }
2620
2621
2622 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
2623 {
2624 return hdw->hdw_desc->shortname;
2625 }
2626
2627
2628 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2629 {
2630 int result;
2631 LOCK_TAKE(hdw->ctl_lock); do {
2632 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
2633 result = pvr2_send_request(hdw,
2634 hdw->cmd_buffer,1,
2635 hdw->cmd_buffer,1);
2636 if (result < 0) break;
2637 result = (hdw->cmd_buffer[0] != 0);
2638 } while(0); LOCK_GIVE(hdw->ctl_lock);
2639 return result;
2640 }
2641
2642
2643 /* Execute poll of tuner status */
2644 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
2645 {
2646 LOCK_TAKE(hdw->big_lock); do {
2647 pvr2_i2c_core_status_poll(hdw);
2648 } while (0); LOCK_GIVE(hdw->big_lock);
2649 }
2650
2651
2652 /* Return information about the tuner */
2653 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
2654 {
2655 LOCK_TAKE(hdw->big_lock); do {
2656 if (hdw->tuner_signal_stale) {
2657 pvr2_i2c_core_status_poll(hdw);
2658 }
2659 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
2660 } while (0); LOCK_GIVE(hdw->big_lock);
2661 return 0;
2662 }
2663
2664
2665 /* Get handle to video output stream */
2666 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2667 {
2668 return hp->vid_stream;
2669 }
2670
2671
2672 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2673 {
2674 int nr = pvr2_hdw_get_unit_number(hdw);
2675 LOCK_TAKE(hdw->big_lock); do {
2676 hdw->log_requested = !0;
2677 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
2678 pvr2_i2c_core_check_stale(hdw);
2679 hdw->log_requested = 0;
2680 pvr2_i2c_core_sync(hdw);
2681 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
2682 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
2683 pvr2_hdw_state_log_state(hdw);
2684 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
2685 } while (0); LOCK_GIVE(hdw->big_lock);
2686 }
2687
2688
2689 /* Grab EEPROM contents, needed for direct method. */
2690 #define EEPROM_SIZE 8192
2691 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
2692 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
2693 {
2694 struct i2c_msg msg[2];
2695 u8 *eeprom;
2696 u8 iadd[2];
2697 u8 addr;
2698 u16 eepromSize;
2699 unsigned int offs;
2700 int ret;
2701 int mode16 = 0;
2702 unsigned pcnt,tcnt;
2703 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
2704 if (!eeprom) {
2705 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2706 "Failed to allocate memory"
2707 " required to read eeprom");
2708 return NULL;
2709 }
2710
2711 trace_eeprom("Value for eeprom addr from controller was 0x%x",
2712 hdw->eeprom_addr);
2713 addr = hdw->eeprom_addr;
2714 /* Seems that if the high bit is set, then the *real* eeprom
2715 address is shifted right now bit position (noticed this in
2716 newer PVR USB2 hardware) */
2717 if (addr & 0x80) addr >>= 1;
2718
2719 /* FX2 documentation states that a 16bit-addressed eeprom is
2720 expected if the I2C address is an odd number (yeah, this is
2721 strange but it's what they do) */
2722 mode16 = (addr & 1);
2723 eepromSize = (mode16 ? EEPROM_SIZE : 256);
2724 trace_eeprom("Examining %d byte eeprom at location 0x%x"
2725 " using %d bit addressing",eepromSize,addr,
2726 mode16 ? 16 : 8);
2727
2728 msg[0].addr = addr;
2729 msg[0].flags = 0;
2730 msg[0].len = mode16 ? 2 : 1;
2731 msg[0].buf = iadd;
2732 msg[1].addr = addr;
2733 msg[1].flags = I2C_M_RD;
2734
2735 /* We have to do the actual eeprom data fetch ourselves, because
2736 (1) we're only fetching part of the eeprom, and (2) if we were
2737 getting the whole thing our I2C driver can't grab it in one
2738 pass - which is what tveeprom is otherwise going to attempt */
2739 memset(eeprom,0,EEPROM_SIZE);
2740 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
2741 pcnt = 16;
2742 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
2743 offs = tcnt + (eepromSize - EEPROM_SIZE);
2744 if (mode16) {
2745 iadd[0] = offs >> 8;
2746 iadd[1] = offs;
2747 } else {
2748 iadd[0] = offs;
2749 }
2750 msg[1].len = pcnt;
2751 msg[1].buf = eeprom+tcnt;
2752 if ((ret = i2c_transfer(&hdw->i2c_adap,
2753 msg,ARRAY_SIZE(msg))) != 2) {
2754 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2755 "eeprom fetch set offs err=%d",ret);
2756 kfree(eeprom);
2757 return NULL;
2758 }
2759 }
2760 return eeprom;
2761 }
2762
2763
2764 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
2765 int prom_flag,
2766 int enable_flag)
2767 {
2768 int ret;
2769 u16 address;
2770 unsigned int pipe;
2771 LOCK_TAKE(hdw->big_lock); do {
2772 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
2773
2774 if (!enable_flag) {
2775 pvr2_trace(PVR2_TRACE_FIRMWARE,
2776 "Cleaning up after CPU firmware fetch");
2777 kfree(hdw->fw_buffer);
2778 hdw->fw_buffer = NULL;
2779 hdw->fw_size = 0;
2780 if (hdw->fw_cpu_flag) {
2781 /* Now release the CPU. It will disconnect
2782 and reconnect later. */
2783 pvr2_hdw_cpureset_assert(hdw,0);
2784 }
2785 break;
2786 }
2787
2788 hdw->fw_cpu_flag = (prom_flag == 0);
2789 if (hdw->fw_cpu_flag) {
2790 pvr2_trace(PVR2_TRACE_FIRMWARE,
2791 "Preparing to suck out CPU firmware");
2792 hdw->fw_size = 0x2000;
2793 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
2794 if (!hdw->fw_buffer) {
2795 hdw->fw_size = 0;
2796 break;
2797 }
2798
2799 /* We have to hold the CPU during firmware upload. */
2800 pvr2_hdw_cpureset_assert(hdw,1);
2801
2802 /* download the firmware from address 0000-1fff in 2048
2803 (=0x800) bytes chunk. */
2804
2805 pvr2_trace(PVR2_TRACE_FIRMWARE,
2806 "Grabbing CPU firmware");
2807 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2808 for(address = 0; address < hdw->fw_size;
2809 address += 0x800) {
2810 ret = usb_control_msg(hdw->usb_dev,pipe,
2811 0xa0,0xc0,
2812 address,0,
2813 hdw->fw_buffer+address,
2814 0x800,HZ);
2815 if (ret < 0) break;
2816 }
2817
2818 pvr2_trace(PVR2_TRACE_FIRMWARE,
2819 "Done grabbing CPU firmware");
2820 } else {
2821 pvr2_trace(PVR2_TRACE_FIRMWARE,
2822 "Sucking down EEPROM contents");
2823 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
2824 if (!hdw->fw_buffer) {
2825 pvr2_trace(PVR2_TRACE_FIRMWARE,
2826 "EEPROM content suck failed.");
2827 break;
2828 }
2829 hdw->fw_size = EEPROM_SIZE;
2830 pvr2_trace(PVR2_TRACE_FIRMWARE,
2831 "Done sucking down EEPROM contents");
2832 }
2833
2834 } while (0); LOCK_GIVE(hdw->big_lock);
2835 }
2836
2837
2838 /* Return true if we're in a mode for retrieval CPU firmware */
2839 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2840 {
2841 return hdw->fw_buffer != NULL;
2842 }
2843
2844
2845 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2846 char *buf,unsigned int cnt)
2847 {
2848 int ret = -EINVAL;
2849 LOCK_TAKE(hdw->big_lock); do {
2850 if (!buf) break;
2851 if (!cnt) break;
2852
2853 if (!hdw->fw_buffer) {
2854 ret = -EIO;
2855 break;
2856 }
2857
2858 if (offs >= hdw->fw_size) {
2859 pvr2_trace(PVR2_TRACE_FIRMWARE,
2860 "Read firmware data offs=%d EOF",
2861 offs);
2862 ret = 0;
2863 break;
2864 }
2865
2866 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2867
2868 memcpy(buf,hdw->fw_buffer+offs,cnt);
2869
2870 pvr2_trace(PVR2_TRACE_FIRMWARE,
2871 "Read firmware data offs=%d cnt=%d",
2872 offs,cnt);
2873 ret = cnt;
2874 } while (0); LOCK_GIVE(hdw->big_lock);
2875
2876 return ret;
2877 }
2878
2879
2880 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
2881 enum pvr2_v4l_type index)
2882 {
2883 switch (index) {
2884 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
2885 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
2886 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
2887 default: return -1;
2888 }
2889 }
2890
2891
2892 /* Store a v4l minor device number */
2893 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
2894 enum pvr2_v4l_type index,int v)
2895 {
2896 switch (index) {
2897 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
2898 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
2899 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
2900 default: break;
2901 }
2902 }
2903
2904
2905 static void pvr2_ctl_write_complete(struct urb *urb)
2906 {
2907 struct pvr2_hdw *hdw = urb->context;
2908 hdw->ctl_write_pend_flag = 0;
2909 if (hdw->ctl_read_pend_flag) return;
2910 complete(&hdw->ctl_done);
2911 }
2912
2913
2914 static void pvr2_ctl_read_complete(struct urb *urb)
2915 {
2916 struct pvr2_hdw *hdw = urb->context;
2917 hdw->ctl_read_pend_flag = 0;
2918 if (hdw->ctl_write_pend_flag) return;
2919 complete(&hdw->ctl_done);
2920 }
2921
2922
2923 static void pvr2_ctl_timeout(unsigned long data)
2924 {
2925 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2926 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2927 hdw->ctl_timeout_flag = !0;
2928 if (hdw->ctl_write_pend_flag)
2929 usb_unlink_urb(hdw->ctl_write_urb);
2930 if (hdw->ctl_read_pend_flag)
2931 usb_unlink_urb(hdw->ctl_read_urb);
2932 }
2933 }
2934
2935
2936 /* Issue a command and get a response from the device. This extended
2937 version includes a probe flag (which if set means that device errors
2938 should not be logged or treated as fatal) and a timeout in jiffies.
2939 This can be used to non-lethally probe the health of endpoint 1. */
2940 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2941 unsigned int timeout,int probe_fl,
2942 void *write_data,unsigned int write_len,
2943 void *read_data,unsigned int read_len)
2944 {
2945 unsigned int idx;
2946 int status = 0;
2947 struct timer_list timer;
2948 if (!hdw->ctl_lock_held) {
2949 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2950 "Attempted to execute control transfer"
2951 " without lock!!");
2952 return -EDEADLK;
2953 }
2954 if (!hdw->flag_ok && !probe_fl) {
2955 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2956 "Attempted to execute control transfer"
2957 " when device not ok");
2958 return -EIO;
2959 }
2960 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2961 if (!probe_fl) {
2962 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2963 "Attempted to execute control transfer"
2964 " when USB is disconnected");
2965 }
2966 return -ENOTTY;
2967 }
2968
2969 /* Ensure that we have sane parameters */
2970 if (!write_data) write_len = 0;
2971 if (!read_data) read_len = 0;
2972 if (write_len > PVR2_CTL_BUFFSIZE) {
2973 pvr2_trace(
2974 PVR2_TRACE_ERROR_LEGS,
2975 "Attempted to execute %d byte"
2976 " control-write transfer (limit=%d)",
2977 write_len,PVR2_CTL_BUFFSIZE);
2978 return -EINVAL;
2979 }
2980 if (read_len > PVR2_CTL_BUFFSIZE) {
2981 pvr2_trace(
2982 PVR2_TRACE_ERROR_LEGS,
2983 "Attempted to execute %d byte"
2984 " control-read transfer (limit=%d)",
2985 write_len,PVR2_CTL_BUFFSIZE);
2986 return -EINVAL;
2987 }
2988 if ((!write_len) && (!read_len)) {
2989 pvr2_trace(
2990 PVR2_TRACE_ERROR_LEGS,
2991 "Attempted to execute null control transfer?");
2992 return -EINVAL;
2993 }
2994
2995
2996 hdw->cmd_debug_state = 1;
2997 if (write_len) {
2998 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
2999 } else {
3000 hdw->cmd_debug_code = 0;
3001 }
3002 hdw->cmd_debug_write_len = write_len;
3003 hdw->cmd_debug_read_len = read_len;
3004
3005 /* Initialize common stuff */
3006 init_completion(&hdw->ctl_done);
3007 hdw->ctl_timeout_flag = 0;
3008 hdw->ctl_write_pend_flag = 0;
3009 hdw->ctl_read_pend_flag = 0;
3010 init_timer(&timer);
3011 timer.expires = jiffies + timeout;
3012 timer.data = (unsigned long)hdw;
3013 timer.function = pvr2_ctl_timeout;
3014
3015 if (write_len) {
3016 hdw->cmd_debug_state = 2;
3017 /* Transfer write data to internal buffer */
3018 for (idx = 0; idx < write_len; idx++) {
3019 hdw->ctl_write_buffer[idx] =
3020 ((unsigned char *)write_data)[idx];
3021 }
3022 /* Initiate a write request */
3023 usb_fill_bulk_urb(hdw->ctl_write_urb,
3024 hdw->usb_dev,
3025 usb_sndbulkpipe(hdw->usb_dev,
3026 PVR2_CTL_WRITE_ENDPOINT),
3027 hdw->ctl_write_buffer,
3028 write_len,
3029 pvr2_ctl_write_complete,
3030 hdw);
3031 hdw->ctl_write_urb->actual_length = 0;
3032 hdw->ctl_write_pend_flag = !0;
3033 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3034 if (status < 0) {
3035 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3036 "Failed to submit write-control"
3037 " URB status=%d",status);
3038 hdw->ctl_write_pend_flag = 0;
3039 goto done;
3040 }
3041 }
3042
3043 if (read_len) {
3044 hdw->cmd_debug_state = 3;
3045 memset(hdw->ctl_read_buffer,0x43,read_len);
3046 /* Initiate a read request */
3047 usb_fill_bulk_urb(hdw->ctl_read_urb,
3048 hdw->usb_dev,
3049 usb_rcvbulkpipe(hdw->usb_dev,
3050 PVR2_CTL_READ_ENDPOINT),
3051 hdw->ctl_read_buffer,
3052 read_len,
3053 pvr2_ctl_read_complete,
3054 hdw);
3055 hdw->ctl_read_urb->actual_length = 0;
3056 hdw->ctl_read_pend_flag = !0;
3057 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3058 if (status < 0) {
3059 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3060 "Failed to submit read-control"
3061 " URB status=%d",status);
3062 hdw->ctl_read_pend_flag = 0;
3063 goto done;
3064 }
3065 }
3066
3067 /* Start timer */
3068 add_timer(&timer);
3069
3070 /* Now wait for all I/O to complete */
3071 hdw->cmd_debug_state = 4;
3072 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3073 wait_for_completion(&hdw->ctl_done);
3074 }
3075 hdw->cmd_debug_state = 5;
3076
3077 /* Stop timer */
3078 del_timer_sync(&timer);
3079
3080 hdw->cmd_debug_state = 6;
3081 status = 0;
3082
3083 if (hdw->ctl_timeout_flag) {
3084 status = -ETIMEDOUT;
3085 if (!probe_fl) {
3086 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3087 "Timed out control-write");
3088 }
3089 goto done;
3090 }
3091
3092 if (write_len) {
3093 /* Validate results of write request */
3094 if ((hdw->ctl_write_urb->status != 0) &&
3095 (hdw->ctl_write_urb->status != -ENOENT) &&
3096 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3097 (hdw->ctl_write_urb->status != -ECONNRESET)) {
3098 /* USB subsystem is reporting some kind of failure
3099 on the write */
3100 status = hdw->ctl_write_urb->status;
3101 if (!probe_fl) {
3102 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3103 "control-write URB failure,"
3104 " status=%d",
3105 status);
3106 }
3107 goto done;
3108 }
3109 if (hdw->ctl_write_urb->actual_length < write_len) {
3110 /* Failed to write enough data */
3111 status = -EIO;
3112 if (!probe_fl) {
3113 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3114 "control-write URB short,"
3115 " expected=%d got=%d",
3116 write_len,
3117 hdw->ctl_write_urb->actual_length);
3118 }
3119 goto done;
3120 }
3121 }
3122 if (read_len) {
3123 /* Validate results of read request */
3124 if ((hdw->ctl_read_urb->status != 0) &&
3125 (hdw->ctl_read_urb->status != -ENOENT) &&
3126 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3127 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3128 /* USB subsystem is reporting some kind of failure
3129 on the read */
3130 status = hdw->ctl_read_urb->status;
3131 if (!probe_fl) {
3132 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3133 "control-read URB failure,"
3134 " status=%d",
3135 status);
3136 }
3137 goto done;
3138 }
3139 if (hdw->ctl_read_urb->actual_length < read_len) {
3140 /* Failed to read enough data */
3141 status = -EIO;
3142 if (!probe_fl) {
3143 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3144 "control-read URB short,"
3145 " expected=%d got=%d",
3146 read_len,
3147 hdw->ctl_read_urb->actual_length);
3148 }
3149 goto done;
3150 }
3151 /* Transfer retrieved data out from internal buffer */
3152 for (idx = 0; idx < read_len; idx++) {
3153 ((unsigned char *)read_data)[idx] =
3154 hdw->ctl_read_buffer[idx];
3155 }
3156 }
3157
3158 done:
3159
3160 hdw->cmd_debug_state = 0;
3161 if ((status < 0) && (!probe_fl)) {
3162 pvr2_hdw_render_useless(hdw);
3163 }
3164 return status;
3165 }
3166
3167
3168 int pvr2_send_request(struct pvr2_hdw *hdw,
3169 void *write_data,unsigned int write_len,
3170 void *read_data,unsigned int read_len)
3171 {
3172 return pvr2_send_request_ex(hdw,HZ*4,0,
3173 write_data,write_len,
3174 read_data,read_len);
3175 }
3176
3177
3178 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3179 {
3180 int ret;
3181 unsigned int cnt = 1;
3182 unsigned int args = 0;
3183 LOCK_TAKE(hdw->ctl_lock);
3184 hdw->cmd_buffer[0] = cmdcode & 0xffu;
3185 args = (cmdcode >> 8) & 0xffu;
3186 args = (args > 2) ? 2 : args;
3187 if (args) {
3188 cnt += args;
3189 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3190 if (args > 1) {
3191 hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3192 }
3193 }
3194 if (pvrusb2_debug & PVR2_TRACE_INIT) {
3195 unsigned int idx;
3196 unsigned int ccnt,bcnt;
3197 char tbuf[50];
3198 cmdcode &= 0xffu;
3199 bcnt = 0;
3200 ccnt = scnprintf(tbuf+bcnt,
3201 sizeof(tbuf)-bcnt,
3202 "Sending FX2 command 0x%x",cmdcode);
3203 bcnt += ccnt;
3204 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3205 if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3206 ccnt = scnprintf(tbuf+bcnt,
3207 sizeof(tbuf)-bcnt,
3208 " \"%s\"",
3209 pvr2_fx2cmd_desc[idx].desc);
3210 bcnt += ccnt;
3211 break;
3212 }
3213 }
3214 if (args) {
3215 ccnt = scnprintf(tbuf+bcnt,
3216 sizeof(tbuf)-bcnt,
3217 " (%u",hdw->cmd_buffer[1]);
3218 bcnt += ccnt;
3219 if (args > 1) {
3220 ccnt = scnprintf(tbuf+bcnt,
3221 sizeof(tbuf)-bcnt,
3222 ",%u",hdw->cmd_buffer[2]);
3223 bcnt += ccnt;
3224 }
3225 ccnt = scnprintf(tbuf+bcnt,
3226 sizeof(tbuf)-bcnt,
3227 ")");
3228 bcnt += ccnt;
3229 }
3230 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3231 }
3232 ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3233 LOCK_GIVE(hdw->ctl_lock);
3234 return ret;
3235 }
3236
3237
3238 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3239 {
3240 int ret;
3241
3242 LOCK_TAKE(hdw->ctl_lock);
3243
3244 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
3245 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3246 hdw->cmd_buffer[5] = 0;
3247 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3248 hdw->cmd_buffer[7] = reg & 0xff;
3249
3250
3251 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3252
3253 LOCK_GIVE(hdw->ctl_lock);
3254
3255 return ret;
3256 }
3257
3258
3259 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3260 {
3261 int ret = 0;
3262
3263 LOCK_TAKE(hdw->ctl_lock);
3264
3265 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
3266 hdw->cmd_buffer[1] = 0;
3267 hdw->cmd_buffer[2] = 0;
3268 hdw->cmd_buffer[3] = 0;
3269 hdw->cmd_buffer[4] = 0;
3270 hdw->cmd_buffer[5] = 0;
3271 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3272 hdw->cmd_buffer[7] = reg & 0xff;
3273
3274 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3275 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3276
3277 LOCK_GIVE(hdw->ctl_lock);
3278
3279 return ret;
3280 }
3281
3282
3283 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3284 {
3285 if (!hdw->flag_ok) return;
3286 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3287 "Device being rendered inoperable");
3288 if (hdw->vid_stream) {
3289 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3290 }
3291 hdw->flag_ok = 0;
3292 trace_stbit("flag_ok",hdw->flag_ok);
3293 pvr2_hdw_state_sched(hdw);
3294 }
3295
3296
3297 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3298 {
3299 int ret;
3300 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
3301 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
3302 if (ret == 1) {
3303 ret = usb_reset_device(hdw->usb_dev);
3304 usb_unlock_device(hdw->usb_dev);
3305 } else {
3306 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3307 "Failed to lock USB device ret=%d",ret);
3308 }
3309 if (init_pause_msec) {
3310 pvr2_trace(PVR2_TRACE_INFO,
3311 "Waiting %u msec for hardware to settle",
3312 init_pause_msec);
3313 msleep(init_pause_msec);
3314 }
3315
3316 }
3317
3318
3319 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3320 {
3321 char da[1];
3322 unsigned int pipe;
3323 int ret;
3324
3325 if (!hdw->usb_dev) return;
3326
3327 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3328
3329 da[0] = val ? 0x01 : 0x00;
3330
3331 /* Write the CPUCS register on the 8051. The lsb of the register
3332 is the reset bit; a 1 asserts reset while a 0 clears it. */
3333 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3334 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3335 if (ret < 0) {
3336 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3337 "cpureset_assert(%d) error=%d",val,ret);
3338 pvr2_hdw_render_useless(hdw);
3339 }
3340 }
3341
3342
3343 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
3344 {
3345 return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
3346 }
3347
3348
3349 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
3350 {
3351 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
3352 }
3353
3354
3355 int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
3356 {
3357 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
3358 }
3359
3360
3361 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
3362 {
3363 if (!hdw->decoder_ctrl) {
3364 pvr2_trace(PVR2_TRACE_INIT,
3365 "Unable to reset decoder: nothing attached");
3366 return -ENOTTY;
3367 }
3368
3369 if (!hdw->decoder_ctrl->force_reset) {
3370 pvr2_trace(PVR2_TRACE_INIT,
3371 "Unable to reset decoder: not implemented");
3372 return -ENOTTY;
3373 }
3374
3375 pvr2_trace(PVR2_TRACE_INIT,
3376 "Requesting decoder reset");
3377 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
3378 return 0;
3379 }
3380
3381
3382 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
3383 {
3384 hdw->flag_ok = !0;
3385 return pvr2_issue_simple_cmd(hdw,
3386 FX2CMD_HCW_DEMOD_RESETIN |
3387 (1 << 8) |
3388 ((onoff ? 1 : 0) << 16));
3389 }
3390
3391
3392 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
3393 {
3394 hdw->flag_ok = !0;
3395 return pvr2_issue_simple_cmd(hdw,(onoff ?
3396 FX2CMD_ONAIR_DTV_POWER_ON :
3397 FX2CMD_ONAIR_DTV_POWER_OFF));
3398 }
3399
3400
3401 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
3402 int onoff)
3403 {
3404 return pvr2_issue_simple_cmd(hdw,(onoff ?
3405 FX2CMD_ONAIR_DTV_STREAMING_ON :
3406 FX2CMD_ONAIR_DTV_STREAMING_OFF));
3407 }
3408
3409
3410 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
3411 {
3412 int cmode;
3413 /* Compare digital/analog desired setting with current setting. If
3414 they don't match, fix it... */
3415 cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
3416 if (cmode == hdw->pathway_state) {
3417 /* They match; nothing to do */
3418 return;
3419 }
3420
3421 switch (hdw->hdw_desc->digital_control_scheme) {
3422 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
3423 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
3424 if (cmode == PVR2_PATHWAY_ANALOG) {
3425 /* If moving to analog mode, also force the decoder
3426 to reset. If no decoder is attached, then it's
3427 ok to ignore this because if/when the decoder
3428 attaches, it will reset itself at that time. */
3429 pvr2_hdw_cmd_decoder_reset(hdw);
3430 }
3431 break;
3432 case PVR2_DIGITAL_SCHEME_ONAIR:
3433 /* Supposedly we should always have the power on whether in
3434 digital or analog mode. But for now do what appears to
3435 work... */
3436 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
3437 break;
3438 default: break;
3439 }
3440
3441 pvr2_hdw_untrip_unlocked(hdw);
3442 hdw->pathway_state = cmode;
3443 }
3444
3445
3446 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
3447 {
3448 /* change some GPIO data
3449 *
3450 * note: bit d7 of dir appears to control the LED,
3451 * so we shut it off here.
3452 *
3453 */
3454 if (onoff) {
3455 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
3456 } else {
3457 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
3458 }
3459 pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
3460 }
3461
3462
3463 typedef void (*led_method_func)(struct pvr2_hdw *,int);
3464
3465 static led_method_func led_methods[] = {
3466 [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
3467 };
3468
3469
3470 /* Toggle LED */
3471 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
3472 {
3473 unsigned int scheme_id;
3474 led_method_func fp;
3475
3476 if ((!onoff) == (!hdw->led_on)) return;
3477
3478 hdw->led_on = onoff != 0;
3479
3480 scheme_id = hdw->hdw_desc->led_scheme;
3481 if (scheme_id < ARRAY_SIZE(led_methods)) {
3482 fp = led_methods[scheme_id];
3483 } else {
3484 fp = NULL;
3485 }
3486
3487 if (fp) (*fp)(hdw,onoff);
3488 }
3489
3490
3491 /* Stop / start video stream transport */
3492 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
3493 {
3494 int ret;
3495
3496 /* If we're in analog mode, then just issue the usual analog
3497 command. */
3498 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
3499 return pvr2_issue_simple_cmd(hdw,
3500 (runFl ?
3501 FX2CMD_STREAMING_ON :
3502 FX2CMD_STREAMING_OFF));
3503 /*Note: Not reached */
3504 }
3505
3506 if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
3507 /* Whoops, we don't know what mode we're in... */
3508 return -EINVAL;
3509 }
3510
3511 /* To get here we have to be in digital mode. The mechanism here
3512 is unfortunately different for different vendors. So we switch
3513 on the device's digital scheme attribute in order to figure out
3514 what to do. */
3515 switch (hdw->hdw_desc->digital_control_scheme) {
3516 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
3517 return pvr2_issue_simple_cmd(hdw,
3518 (runFl ?
3519 FX2CMD_HCW_DTV_STREAMING_ON :
3520 FX2CMD_HCW_DTV_STREAMING_OFF));
3521 case PVR2_DIGITAL_SCHEME_ONAIR:
3522 ret = pvr2_issue_simple_cmd(hdw,
3523 (runFl ?
3524 FX2CMD_STREAMING_ON :
3525 FX2CMD_STREAMING_OFF));
3526 if (ret) return ret;
3527 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
3528 default:
3529 return -EINVAL;
3530 }
3531 }
3532
3533
3534 /* Evaluate whether or not state_pathway_ok can change */
3535 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
3536 {
3537 if (hdw->state_pathway_ok) {
3538 /* Nothing to do if pathway is already ok */
3539 return 0;
3540 }
3541 if (!hdw->state_pipeline_idle) {
3542 /* Not allowed to change anything if pipeline is not idle */
3543 return 0;
3544 }
3545 pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
3546 hdw->state_pathway_ok = !0;
3547 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
3548 return !0;
3549 }
3550
3551
3552 /* Evaluate whether or not state_encoder_ok can change */
3553 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
3554 {
3555 if (hdw->state_encoder_ok) return 0;
3556 if (hdw->flag_tripped) return 0;
3557 if (hdw->state_encoder_run) return 0;
3558 if (hdw->state_encoder_config) return 0;
3559 if (hdw->state_decoder_run) return 0;
3560 if (hdw->state_usbstream_run) return 0;
3561 if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
3562 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
3563 } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
3564 return 0;
3565 }
3566
3567 if (pvr2_upload_firmware2(hdw) < 0) {
3568 hdw->flag_tripped = !0;
3569 trace_stbit("flag_tripped",hdw->flag_tripped);
3570 return !0;
3571 }
3572 hdw->state_encoder_ok = !0;
3573 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
3574 return !0;
3575 }
3576
3577
3578 /* Evaluate whether or not state_encoder_config can change */
3579 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
3580 {
3581 if (hdw->state_encoder_config) {
3582 if (hdw->state_encoder_ok) {
3583 if (hdw->state_pipeline_req &&
3584 !hdw->state_pipeline_pause) return 0;
3585 }
3586 hdw->state_encoder_config = 0;
3587 hdw->state_encoder_waitok = 0;
3588 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3589 /* paranoia - solve race if timer just completed */
3590 del_timer_sync(&hdw->encoder_wait_timer);
3591 } else {
3592 if (!hdw->state_pathway_ok ||
3593 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
3594 !hdw->state_encoder_ok ||
3595 !hdw->state_pipeline_idle ||
3596 hdw->state_pipeline_pause ||
3597 !hdw->state_pipeline_req ||
3598 !hdw->state_pipeline_config) {
3599 /* We must reset the enforced wait interval if
3600 anything has happened that might have disturbed
3601 the encoder. This should be a rare case. */
3602 if (timer_pending(&hdw->encoder_wait_timer)) {
3603 del_timer_sync(&hdw->encoder_wait_timer);
3604 }
3605 if (hdw->state_encoder_waitok) {
3606 /* Must clear the state - therefore we did
3607 something to a state bit and must also
3608 return true. */
3609 hdw->state_encoder_waitok = 0;
3610 trace_stbit("state_encoder_waitok",
3611 hdw->state_encoder_waitok);
3612 return !0;
3613 }
3614 return 0;
3615 }
3616 if (!hdw->state_encoder_waitok) {
3617 if (!timer_pending(&hdw->encoder_wait_timer)) {
3618 /* waitok flag wasn't set and timer isn't
3619 running. Check flag once more to avoid
3620 a race then start the timer. This is
3621 the point when we measure out a minimal
3622 quiet interval before doing something to
3623 the encoder. */
3624 if (!hdw->state_encoder_waitok) {
3625 hdw->encoder_wait_timer.expires =
3626 jiffies +
3627 (HZ * TIME_MSEC_ENCODER_WAIT
3628 / 1000);
3629 add_timer(&hdw->encoder_wait_timer);
3630 }
3631 }
3632 /* We can't continue until we know we have been
3633 quiet for the interval measured by this
3634 timer. */
3635 return 0;
3636 }
3637 pvr2_encoder_configure(hdw);
3638 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
3639 }
3640 trace_stbit("state_encoder_config",hdw->state_encoder_config);
3641 return !0;
3642 }
3643
3644
3645 /* Return true if the encoder should not be running. */
3646 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
3647 {
3648 if (!hdw->state_encoder_ok) {
3649 /* Encoder isn't healthy at the moment, so stop it. */
3650 return !0;
3651 }
3652 if (!hdw->state_pathway_ok) {
3653 /* Mode is not understood at the moment (i.e. it wants to
3654 change), so encoder must be stopped. */
3655 return !0;
3656 }
3657
3658 switch (hdw->pathway_state) {
3659 case PVR2_PATHWAY_ANALOG:
3660 if (!hdw->state_decoder_run) {
3661 /* We're in analog mode and the decoder is not
3662 running; thus the encoder should be stopped as
3663 well. */
3664 return !0;
3665 }
3666 break;
3667 case PVR2_PATHWAY_DIGITAL:
3668 if (hdw->state_encoder_runok) {
3669 /* This is a funny case. We're in digital mode so
3670 really the encoder should be stopped. However
3671 if it really is running, only kill it after
3672 runok has been set. This gives a chance for the
3673 onair quirk to function (encoder must run
3674 briefly first, at least once, before onair
3675 digital streaming can work). */
3676 return !0;
3677 }
3678 break;
3679 default:
3680 /* Unknown mode; so encoder should be stopped. */
3681 return !0;
3682 }
3683
3684 /* If we get here, we haven't found a reason to stop the
3685 encoder. */
3686 return 0;
3687 }
3688
3689
3690 /* Return true if the encoder should be running. */
3691 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
3692 {
3693 if (!hdw->state_encoder_ok) {
3694 /* Don't run the encoder if it isn't healthy... */
3695 return 0;
3696 }
3697 if (!hdw->state_pathway_ok) {
3698 /* Don't run the encoder if we don't (yet) know what mode
3699 we need to be in... */
3700 return 0;
3701 }
3702
3703 switch (hdw->pathway_state) {
3704 case PVR2_PATHWAY_ANALOG:
3705 if (hdw->state_decoder_run) {
3706 /* In analog mode, if the decoder is running, then
3707 run the encoder. */
3708 return !0;
3709 }
3710 break;
3711 case PVR2_PATHWAY_DIGITAL:
3712 if ((hdw->hdw_desc->digital_control_scheme ==
3713 PVR2_DIGITAL_SCHEME_ONAIR) &&
3714 !hdw->state_encoder_runok) {
3715 /* This is a quirk. OnAir hardware won't stream
3716 digital until the encoder has been run at least
3717 once, for a minimal period of time (empiricially
3718 measured to be 1/4 second). So if we're on
3719 OnAir hardware and the encoder has never been
3720 run at all, then start the encoder. Normal
3721 state machine logic in the driver will
3722 automatically handle the remaining bits. */
3723 return !0;
3724 }
3725 break;
3726 default:
3727 /* For completeness (unknown mode; encoder won't run ever) */
3728 break;
3729 }
3730 /* If we get here, then we haven't found any reason to run the
3731 encoder, so don't run it. */
3732 return 0;
3733 }
3734
3735
3736 /* Evaluate whether or not state_encoder_run can change */
3737 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
3738 {
3739 if (hdw->state_encoder_run) {
3740 if (!state_check_disable_encoder_run(hdw)) return 0;
3741 if (hdw->state_encoder_ok) {
3742 del_timer_sync(&hdw->encoder_run_timer);
3743 if (pvr2_encoder_stop(hdw) < 0) return !0;
3744 }
3745 hdw->state_encoder_run = 0;
3746 } else {
3747 if (!state_check_enable_encoder_run(hdw)) return 0;
3748 if (pvr2_encoder_start(hdw) < 0) return !0;
3749 hdw->state_encoder_run = !0;
3750 if (!hdw->state_encoder_runok) {
3751 hdw->encoder_run_timer.expires =
3752 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
3753 add_timer(&hdw->encoder_run_timer);
3754 }
3755 }
3756 trace_stbit("state_encoder_run",hdw->state_encoder_run);
3757 return !0;
3758 }
3759
3760
3761 /* Timeout function for quiescent timer. */
3762 static void pvr2_hdw_quiescent_timeout(unsigned long data)
3763 {
3764 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3765 hdw->state_decoder_quiescent = !0;
3766 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3767 hdw->state_stale = !0;
3768 queue_work(hdw->workqueue,&hdw->workpoll);
3769 }
3770
3771
3772 /* Timeout function for encoder wait timer. */
3773 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
3774 {
3775 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3776 hdw->state_encoder_waitok = !0;
3777 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3778 hdw->state_stale = !0;
3779 queue_work(hdw->workqueue,&hdw->workpoll);
3780 }
3781
3782
3783 /* Timeout function for encoder run timer. */
3784 static void pvr2_hdw_encoder_run_timeout(unsigned long data)
3785 {
3786 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3787 if (!hdw->state_encoder_runok) {
3788 hdw->state_encoder_runok = !0;
3789 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
3790 hdw->state_stale = !0;
3791 queue_work(hdw->workqueue,&hdw->workpoll);
3792 }
3793 }
3794
3795
3796 /* Evaluate whether or not state_decoder_run can change */
3797 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
3798 {
3799 if (hdw->state_decoder_run) {
3800 if (hdw->state_encoder_ok) {
3801 if (hdw->state_pipeline_req &&
3802 !hdw->state_pipeline_pause &&
3803 hdw->state_pathway_ok) return 0;
3804 }
3805 if (!hdw->flag_decoder_missed) {
3806 pvr2_decoder_enable(hdw,0);
3807 }
3808 hdw->state_decoder_quiescent = 0;
3809 hdw->state_decoder_run = 0;
3810 /* paranoia - solve race if timer just completed */
3811 del_timer_sync(&hdw->quiescent_timer);
3812 } else {
3813 if (!hdw->state_decoder_quiescent) {
3814 if (!timer_pending(&hdw->quiescent_timer)) {
3815 /* We don't do something about the
3816 quiescent timer until right here because
3817 we also want to catch cases where the
3818 decoder was already not running (like
3819 after initialization) as opposed to
3820 knowing that we had just stopped it.
3821 The second flag check is here to cover a
3822 race - the timer could have run and set
3823 this flag just after the previous check
3824 but before we did the pending check. */
3825 if (!hdw->state_decoder_quiescent) {
3826 hdw->quiescent_timer.expires =
3827 jiffies +
3828 (HZ * TIME_MSEC_DECODER_WAIT
3829 / 1000);
3830 add_timer(&hdw->quiescent_timer);
3831 }
3832 }
3833 /* Don't allow decoder to start again until it has
3834 been quiesced first. This little detail should
3835 hopefully further stabilize the encoder. */
3836 return 0;
3837 }
3838 if (!hdw->state_pathway_ok ||
3839 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
3840 !hdw->state_pipeline_req ||
3841 hdw->state_pipeline_pause ||
3842 !hdw->state_pipeline_config ||
3843 !hdw->state_encoder_config ||
3844 !hdw->state_encoder_ok) return 0;
3845 del_timer_sync(&hdw->quiescent_timer);
3846 if (hdw->flag_decoder_missed) return 0;
3847 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
3848 hdw->state_decoder_quiescent = 0;
3849 hdw->state_decoder_run = !0;
3850 }
3851 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3852 trace_stbit("state_decoder_run",hdw->state_decoder_run);
3853 return !0;
3854 }
3855
3856
3857 /* Evaluate whether or not state_usbstream_run can change */
3858 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
3859 {
3860 if (hdw->state_usbstream_run) {
3861 int fl = !0;
3862 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
3863 fl = (hdw->state_encoder_ok &&
3864 hdw->state_encoder_run);
3865 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
3866 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
3867 fl = hdw->state_encoder_ok;
3868 }
3869 if (fl &&
3870 hdw->state_pipeline_req &&
3871 !hdw->state_pipeline_pause &&
3872 hdw->state_pathway_ok) {
3873 return 0;
3874 }
3875 pvr2_hdw_cmd_usbstream(hdw,0);
3876 hdw->state_usbstream_run = 0;
3877 } else {
3878 if (!hdw->state_pipeline_req ||
3879 hdw->state_pipeline_pause ||
3880 !hdw->state_pathway_ok) return 0;
3881 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
3882 if (!hdw->state_encoder_ok ||
3883 !hdw->state_encoder_run) return 0;
3884 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
3885 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
3886 if (!hdw->state_encoder_ok) return 0;
3887 if (hdw->state_encoder_run) return 0;
3888 if (hdw->hdw_desc->digital_control_scheme ==
3889 PVR2_DIGITAL_SCHEME_ONAIR) {
3890 /* OnAir digital receivers won't stream
3891 unless the analog encoder has run first.
3892 Why? I have no idea. But don't even
3893 try until we know the analog side is
3894 known to have run. */
3895 if (!hdw->state_encoder_runok) return 0;
3896 }
3897 }
3898 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
3899 hdw->state_usbstream_run = !0;
3900 }
3901 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
3902 return !0;
3903 }
3904
3905
3906 /* Attempt to configure pipeline, if needed */
3907 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
3908 {
3909 if (hdw->state_pipeline_config ||
3910 hdw->state_pipeline_pause) return 0;
3911 pvr2_hdw_commit_execute(hdw);
3912 return !0;
3913 }
3914
3915
3916 /* Update pipeline idle and pipeline pause tracking states based on other
3917 inputs. This must be called whenever the other relevant inputs have
3918 changed. */
3919 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
3920 {
3921 unsigned int st;
3922 int updatedFl = 0;
3923 /* Update pipeline state */
3924 st = !(hdw->state_encoder_run ||
3925 hdw->state_decoder_run ||
3926 hdw->state_usbstream_run ||
3927 (!hdw->state_decoder_quiescent));
3928 if (!st != !hdw->state_pipeline_idle) {
3929 hdw->state_pipeline_idle = st;
3930 updatedFl = !0;
3931 }
3932 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
3933 hdw->state_pipeline_pause = 0;
3934 updatedFl = !0;
3935 }
3936 return updatedFl;
3937 }
3938
3939
3940 typedef int (*state_eval_func)(struct pvr2_hdw *);
3941
3942 /* Set of functions to be run to evaluate various states in the driver. */
3943 static const state_eval_func eval_funcs[] = {
3944 state_eval_pathway_ok,
3945 state_eval_pipeline_config,
3946 state_eval_encoder_ok,
3947 state_eval_encoder_config,
3948 state_eval_decoder_run,
3949 state_eval_encoder_run,
3950 state_eval_usbstream_run,
3951 };
3952
3953
3954 /* Process various states and return true if we did anything interesting. */
3955 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
3956 {
3957 unsigned int i;
3958 int state_updated = 0;
3959 int check_flag;
3960
3961 if (!hdw->state_stale) return 0;
3962 if ((hdw->fw1_state != FW1_STATE_OK) ||
3963 !hdw->flag_ok) {
3964 hdw->state_stale = 0;
3965 return !0;
3966 }
3967 /* This loop is the heart of the entire driver. It keeps trying to
3968 evaluate various bits of driver state until nothing changes for
3969 one full iteration. Each "bit of state" tracks some global
3970 aspect of the driver, e.g. whether decoder should run, if
3971 pipeline is configured, usb streaming is on, etc. We separately
3972 evaluate each of those questions based on other driver state to
3973 arrive at the correct running configuration. */
3974 do {
3975 check_flag = 0;
3976 state_update_pipeline_state(hdw);
3977 /* Iterate over each bit of state */
3978 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
3979 if ((*eval_funcs[i])(hdw)) {
3980 check_flag = !0;
3981 state_updated = !0;
3982 state_update_pipeline_state(hdw);
3983 }
3984 }
3985 } while (check_flag && hdw->flag_ok);
3986 hdw->state_stale = 0;
3987 trace_stbit("state_stale",hdw->state_stale);
3988 return state_updated;
3989 }
3990
3991
3992 static unsigned int print_input_mask(unsigned int msk,
3993 char *buf,unsigned int acnt)
3994 {
3995 unsigned int idx,ccnt;
3996 unsigned int tcnt = 0;
3997 for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
3998 if (!((1 << idx) & msk)) continue;
3999 ccnt = scnprintf(buf+tcnt,
4000 acnt-tcnt,
4001 "%s%s",
4002 (tcnt ? ", " : ""),
4003 control_values_input[idx]);
4004 tcnt += ccnt;
4005 }
4006 return tcnt;
4007 }
4008
4009
4010 static const char *pvr2_pathway_state_name(int id)
4011 {
4012 switch (id) {
4013 case PVR2_PATHWAY_ANALOG: return "analog";
4014 case PVR2_PATHWAY_DIGITAL: return "digital";
4015 default: return "unknown";
4016 }
4017 }
4018
4019
4020 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4021 char *buf,unsigned int acnt)
4022 {
4023 switch (which) {
4024 case 0:
4025 return scnprintf(
4026 buf,acnt,
4027 "driver:%s%s%s%s%s <mode=%s>",
4028 (hdw->flag_ok ? " <ok>" : " <fail>"),
4029 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4030 (hdw->flag_disconnected ? " <disconnected>" :
4031 " <connected>"),
4032 (hdw->flag_tripped ? " <tripped>" : ""),
4033 (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4034 pvr2_pathway_state_name(hdw->pathway_state));
4035
4036 case 1:
4037 return scnprintf(
4038 buf,acnt,
4039 "pipeline:%s%s%s%s",
4040 (hdw->state_pipeline_idle ? " <idle>" : ""),
4041 (hdw->state_pipeline_config ?
4042 " <configok>" : " <stale>"),
4043 (hdw->state_pipeline_req ? " <req>" : ""),
4044 (hdw->state_pipeline_pause ? " <pause>" : ""));
4045 case 2:
4046 return scnprintf(
4047 buf,acnt,
4048 "worker:%s%s%s%s%s%s%s",
4049 (hdw->state_decoder_run ?
4050 " <decode:run>" :
4051 (hdw->state_decoder_quiescent ?
4052 "" : " <decode:stop>")),
4053 (hdw->state_decoder_quiescent ?
4054 " <decode:quiescent>" : ""),
4055 (hdw->state_encoder_ok ?
4056 "" : " <encode:init>"),
4057 (hdw->state_encoder_run ?
4058 (hdw->state_encoder_runok ?
4059 " <encode:run>" :
4060 " <encode:firstrun>") :
4061 (hdw->state_encoder_runok ?
4062 " <encode:stop>" :
4063 " <encode:virgin>")),
4064 (hdw->state_encoder_config ?
4065 " <encode:configok>" :
4066 (hdw->state_encoder_waitok ?
4067 "" : " <encode:waitok>")),
4068 (hdw->state_usbstream_run ?
4069 " <usb:run>" : " <usb:stop>"),
4070 (hdw->state_pathway_ok ?
4071 " <pathway:ok>" : ""));
4072 case 3:
4073 return scnprintf(
4074 buf,acnt,
4075 "state: %s",
4076 pvr2_get_state_name(hdw->master_state));
4077 case 4: {
4078 unsigned int tcnt = 0;
4079 unsigned int ccnt;
4080
4081 ccnt = scnprintf(buf,
4082 acnt,
4083 "Hardware supported inputs: ");
4084 tcnt += ccnt;
4085 tcnt += print_input_mask(hdw->input_avail_mask,
4086 buf+tcnt,
4087 acnt-tcnt);
4088 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4089 ccnt = scnprintf(buf+tcnt,
4090 acnt-tcnt,
4091 "; allowed inputs: ");
4092 tcnt += ccnt;
4093 tcnt += print_input_mask(hdw->input_allowed_mask,
4094 buf+tcnt,
4095 acnt-tcnt);
4096 }
4097 return tcnt;
4098 }
4099 case 5: {
4100 struct pvr2_stream_stats stats;
4101 if (!hdw->vid_stream) break;
4102 pvr2_stream_get_stats(hdw->vid_stream,
4103 &stats,
4104 0);
4105 return scnprintf(
4106 buf,acnt,
4107 "Bytes streamed=%u"
4108 " URBs: queued=%u idle=%u ready=%u"
4109 " processed=%u failed=%u",
4110 stats.bytes_processed,
4111 stats.buffers_in_queue,
4112 stats.buffers_in_idle,
4113 stats.buffers_in_ready,
4114 stats.buffers_processed,
4115 stats.buffers_failed);
4116 }
4117 default: break;
4118 }
4119 return 0;
4120 }
4121
4122
4123 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4124 char *buf,unsigned int acnt)
4125 {
4126 unsigned int bcnt,ccnt,idx;
4127 bcnt = 0;
4128 LOCK_TAKE(hdw->big_lock);
4129 for (idx = 0; ; idx++) {
4130 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4131 if (!ccnt) break;
4132 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4133 if (!acnt) break;
4134 buf[0] = '\n'; ccnt = 1;
4135 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4136 }
4137 LOCK_GIVE(hdw->big_lock);
4138 return bcnt;
4139 }
4140
4141
4142 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4143 {
4144 char buf[128];
4145 unsigned int idx,ccnt;
4146
4147 for (idx = 0; ; idx++) {
4148 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4149 if (!ccnt) break;
4150 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4151 }
4152 }
4153
4154
4155 /* Evaluate and update the driver's current state, taking various actions
4156 as appropriate for the update. */
4157 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4158 {
4159 unsigned int st;
4160 int state_updated = 0;
4161 int callback_flag = 0;
4162 int analog_mode;
4163
4164 pvr2_trace(PVR2_TRACE_STBITS,
4165 "Drive state check START");
4166 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4167 pvr2_hdw_state_log_state(hdw);
4168 }
4169
4170 /* Process all state and get back over disposition */
4171 state_updated = pvr2_hdw_state_update(hdw);
4172
4173 analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4174
4175 /* Update master state based upon all other states. */
4176 if (!hdw->flag_ok) {
4177 st = PVR2_STATE_DEAD;
4178 } else if (hdw->fw1_state != FW1_STATE_OK) {
4179 st = PVR2_STATE_COLD;
4180 } else if ((analog_mode ||
4181 hdw->hdw_desc->flag_digital_requires_cx23416) &&
4182 !hdw->state_encoder_ok) {
4183 st = PVR2_STATE_WARM;
4184 } else if (hdw->flag_tripped ||
4185 (analog_mode && hdw->flag_decoder_missed)) {
4186 st = PVR2_STATE_ERROR;
4187 } else if (hdw->state_usbstream_run &&
4188 (!analog_mode ||
4189 (hdw->state_encoder_run && hdw->state_decoder_run))) {
4190 st = PVR2_STATE_RUN;
4191 } else {
4192 st = PVR2_STATE_READY;
4193 }
4194 if (hdw->master_state != st) {
4195 pvr2_trace(PVR2_TRACE_STATE,
4196 "Device state change from %s to %s",
4197 pvr2_get_state_name(hdw->master_state),
4198 pvr2_get_state_name(st));
4199 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
4200 hdw->master_state = st;
4201 state_updated = !0;
4202 callback_flag = !0;
4203 }
4204 if (state_updated) {
4205 /* Trigger anyone waiting on any state changes here. */
4206 wake_up(&hdw->state_wait_data);
4207 }
4208
4209 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4210 pvr2_hdw_state_log_state(hdw);
4211 }
4212 pvr2_trace(PVR2_TRACE_STBITS,
4213 "Drive state check DONE callback=%d",callback_flag);
4214
4215 return callback_flag;
4216 }
4217
4218
4219 /* Cause kernel thread to check / update driver state */
4220 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4221 {
4222 if (hdw->state_stale) return;
4223 hdw->state_stale = !0;
4224 trace_stbit("state_stale",hdw->state_stale);
4225 queue_work(hdw->workqueue,&hdw->workpoll);
4226 }
4227
4228
4229 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4230 {
4231 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
4232 }
4233
4234
4235 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
4236 {
4237 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
4238 }
4239
4240
4241 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
4242 {
4243 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
4244 }
4245
4246
4247 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
4248 {
4249 u32 cval,nval;
4250 int ret;
4251 if (~msk) {
4252 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
4253 if (ret) return ret;
4254 nval = (cval & ~msk) | (val & msk);
4255 pvr2_trace(PVR2_TRACE_GPIO,
4256 "GPIO direction changing 0x%x:0x%x"
4257 " from 0x%x to 0x%x",
4258 msk,val,cval,nval);
4259 } else {
4260 nval = val;
4261 pvr2_trace(PVR2_TRACE_GPIO,
4262 "GPIO direction changing to 0x%x",nval);
4263 }
4264 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
4265 }
4266
4267
4268 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
4269 {
4270 u32 cval,nval;
4271 int ret;
4272 if (~msk) {
4273 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
4274 if (ret) return ret;
4275 nval = (cval & ~msk) | (val & msk);
4276 pvr2_trace(PVR2_TRACE_GPIO,
4277 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
4278 msk,val,cval,nval);
4279 } else {
4280 nval = val;
4281 pvr2_trace(PVR2_TRACE_GPIO,
4282 "GPIO output changing to 0x%x",nval);
4283 }
4284 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
4285 }
4286
4287
4288 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
4289 {
4290 return hdw->input_avail_mask;
4291 }
4292
4293
4294 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
4295 {
4296 return hdw->input_allowed_mask;
4297 }
4298
4299
4300 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
4301 {
4302 if (hdw->input_val != v) {
4303 hdw->input_val = v;
4304 hdw->input_dirty = !0;
4305 }
4306
4307 /* Handle side effects - if we switch to a mode that needs the RF
4308 tuner, then select the right frequency choice as well and mark
4309 it dirty. */
4310 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
4311 hdw->freqSelector = 0;
4312 hdw->freqDirty = !0;
4313 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
4314 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
4315 hdw->freqSelector = 1;
4316 hdw->freqDirty = !0;
4317 }
4318 return 0;
4319 }
4320
4321
4322 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
4323 unsigned int change_mask,
4324 unsigned int change_val)
4325 {
4326 int ret = 0;
4327 unsigned int nv,m,idx;
4328 LOCK_TAKE(hdw->big_lock);
4329 do {
4330 nv = hdw->input_allowed_mask & ~change_mask;
4331 nv |= (change_val & change_mask);
4332 nv &= hdw->input_avail_mask;
4333 if (!nv) {
4334 /* No legal modes left; return error instead. */
4335 ret = -EPERM;
4336 break;
4337 }
4338 hdw->input_allowed_mask = nv;
4339 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
4340 /* Current mode is still in the allowed mask, so
4341 we're done. */
4342 break;
4343 }
4344 /* Select and switch to a mode that is still in the allowed
4345 mask */
4346 if (!hdw->input_allowed_mask) {
4347 /* Nothing legal; give up */
4348 break;
4349 }
4350 m = hdw->input_allowed_mask;
4351 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
4352 if (!((1 << idx) & m)) continue;
4353 pvr2_hdw_set_input(hdw,idx);
4354 break;
4355 }
4356 } while (0);
4357 LOCK_GIVE(hdw->big_lock);
4358 return ret;
4359 }
4360
4361
4362 /* Find I2C address of eeprom */
4363 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
4364 {
4365 int result;
4366 LOCK_TAKE(hdw->ctl_lock); do {
4367 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
4368 result = pvr2_send_request(hdw,
4369 hdw->cmd_buffer,1,
4370 hdw->cmd_buffer,1);
4371 if (result < 0) break;
4372 result = hdw->cmd_buffer[0];
4373 } while(0); LOCK_GIVE(hdw->ctl_lock);
4374 return result;
4375 }
4376
4377
4378 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
4379 u32 match_type, u32 match_chip, u64 reg_id,
4380 int setFl,u64 *val_ptr)
4381 {
4382 #ifdef CONFIG_VIDEO_ADV_DEBUG
4383 struct pvr2_i2c_client *cp;
4384 struct v4l2_register req;
4385 int stat = 0;
4386 int okFl = 0;
4387
4388 if (!capable(CAP_SYS_ADMIN)) return -EPERM;
4389
4390 req.match_type = match_type;
4391 req.match_chip = match_chip;
4392 req.reg = reg_id;
4393 if (setFl) req.val = *val_ptr;
4394 mutex_lock(&hdw->i2c_list_lock); do {
4395 list_for_each_entry(cp, &hdw->i2c_clients, list) {
4396 if (!v4l2_chip_match_i2c_client(
4397 cp->client,
4398 req.match_type, req.match_chip)) {
4399 continue;
4400 }
4401 stat = pvr2_i2c_client_cmd(
4402 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
4403 VIDIOC_DBG_G_REGISTER),&req);
4404 if (!setFl) *val_ptr = req.val;
4405 okFl = !0;
4406 break;
4407 }
4408 } while (0); mutex_unlock(&hdw->i2c_list_lock);
4409 if (okFl) {
4410 return stat;
4411 }
4412 return -EINVAL;
4413 #else
4414 return -ENOSYS;
4415 #endif
4416 }
4417
4418
4419 /*
4420 Stuff for Emacs to see, in order to encourage consistent editing style:
4421 *** Local Variables: ***
4422 *** mode: c ***
4423 *** fill-column: 75 ***
4424 *** tab-width: 8 ***
4425 *** c-basic-offset: 8 ***
4426 *** End: ***
4427 */
AMDTP streaming driver for the Linux FireWire stack (Juju)