1 #ifndef __SOUND_ICE1712_H
2 #define __SOUND_ICE1712_H
5 * ALSA driver for ICEnsemble ICE1712 (Envy24)
7 * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <sound/control.h>
26 #include <sound/ac97_codec.h>
27 #include <sound/rawmidi.h>
28 #include <sound/i2c.h>
29 #include <sound/ak4xxx-adda.h>
30 #include <sound/ak4114.h>
31 #include <sound/pcm.h>
32 #include <sound/mpu401.h>
39 #define ICEREG(ice, x) ((ice)->port + ICE1712_REG_##x)
41 #define ICE1712_REG_CONTROL 0x00 /* byte */
42 #define ICE1712_RESET 0x80 /* reset whole chip */
43 #define ICE1712_SERR_LEVEL 0x04 /* SERR# level otherwise edge */
44 #define ICE1712_NATIVE 0x01 /* native mode otherwise SB */
45 #define ICE1712_REG_IRQMASK 0x01 /* byte */
46 #define ICE1712_IRQ_MPU1 0x80
47 #define ICE1712_IRQ_TIMER 0x40
48 #define ICE1712_IRQ_MPU2 0x20
49 #define ICE1712_IRQ_PROPCM 0x10
50 #define ICE1712_IRQ_FM 0x08 /* FM/MIDI - legacy */
51 #define ICE1712_IRQ_PBKDS 0x04 /* playback DS channels */
52 #define ICE1712_IRQ_CONCAP 0x02 /* consumer capture */
53 #define ICE1712_IRQ_CONPBK 0x01 /* consumer playback */
54 #define ICE1712_REG_IRQSTAT 0x02 /* byte */
55 /* look to ICE1712_IRQ_* */
56 #define ICE1712_REG_INDEX 0x03 /* byte - indirect CCIxx regs */
57 #define ICE1712_REG_DATA 0x04 /* byte - indirect CCIxx regs */
58 #define ICE1712_REG_NMI_STAT1 0x05 /* byte */
59 #define ICE1712_REG_NMI_DATA 0x06 /* byte */
60 #define ICE1712_REG_NMI_INDEX 0x07 /* byte */
61 #define ICE1712_REG_AC97_INDEX 0x08 /* byte */
62 #define ICE1712_REG_AC97_CMD 0x09 /* byte */
63 #define ICE1712_AC97_COLD 0x80 /* cold reset */
64 #define ICE1712_AC97_WARM 0x40 /* warm reset */
65 #define ICE1712_AC97_WRITE 0x20 /* W: write, R: write in progress */
66 #define ICE1712_AC97_READ 0x10 /* W: read, R: read in progress */
67 #define ICE1712_AC97_READY 0x08 /* codec ready status bit */
68 #define ICE1712_AC97_PBK_VSR 0x02 /* playback VSR */
69 #define ICE1712_AC97_CAP_VSR 0x01 /* capture VSR */
70 #define ICE1712_REG_AC97_DATA 0x0a /* word (little endian) */
71 #define ICE1712_REG_MPU1_CTRL 0x0c /* byte */
72 #define ICE1712_REG_MPU1_DATA 0x0d /* byte */
73 #define ICE1712_REG_I2C_DEV_ADDR 0x10 /* byte */
74 #define ICE1712_I2C_WRITE 0x01 /* write direction */
75 #define ICE1712_REG_I2C_BYTE_ADDR 0x11 /* byte */
76 #define ICE1712_REG_I2C_DATA 0x12 /* byte */
77 #define ICE1712_REG_I2C_CTRL 0x13 /* byte */
78 #define ICE1712_I2C_EEPROM 0x80 /* EEPROM exists */
79 #define ICE1712_I2C_BUSY 0x01 /* busy bit */
80 #define ICE1712_REG_CONCAP_ADDR 0x14 /* dword - consumer capture */
81 #define ICE1712_REG_CONCAP_COUNT 0x18 /* word - current/base count */
82 #define ICE1712_REG_SERR_SHADOW 0x1b /* byte */
83 #define ICE1712_REG_MPU2_CTRL 0x1c /* byte */
84 #define ICE1712_REG_MPU2_DATA 0x1d /* byte */
85 #define ICE1712_REG_TIMER 0x1e /* word */
91 #define ICE1712_IREG_PBK_COUNT_LO 0x00
92 #define ICE1712_IREG_PBK_COUNT_HI 0x01
93 #define ICE1712_IREG_PBK_CTRL 0x02
94 #define ICE1712_IREG_PBK_LEFT 0x03 /* left volume */
95 #define ICE1712_IREG_PBK_RIGHT 0x04 /* right volume */
96 #define ICE1712_IREG_PBK_SOFT 0x05 /* soft volume */
97 #define ICE1712_IREG_PBK_RATE_LO 0x06
98 #define ICE1712_IREG_PBK_RATE_MID 0x07
99 #define ICE1712_IREG_PBK_RATE_HI 0x08
100 #define ICE1712_IREG_CAP_COUNT_LO 0x10
101 #define ICE1712_IREG_CAP_COUNT_HI 0x11
102 #define ICE1712_IREG_CAP_CTRL 0x12
103 #define ICE1712_IREG_GPIO_DATA 0x20
104 #define ICE1712_IREG_GPIO_WRITE_MASK 0x21
105 #define ICE1712_IREG_GPIO_DIRECTION 0x22
106 #define ICE1712_IREG_CONSUMER_POWERDOWN 0x30
107 #define ICE1712_IREG_PRO_POWERDOWN 0x31
110 * Consumer section direct DMA registers
113 #define ICEDS(ice, x) ((ice)->dmapath_port + ICE1712_DS_##x)
115 #define ICE1712_DS_INTMASK 0x00 /* word - interrupt mask */
116 #define ICE1712_DS_INTSTAT 0x02 /* word - interrupt status */
117 #define ICE1712_DS_DATA 0x04 /* dword - channel data */
118 #define ICE1712_DS_INDEX 0x08 /* dword - channel index */
121 * Consumer section channel registers
124 #define ICE1712_DSC_ADDR0 0x00 /* dword - base address 0 */
125 #define ICE1712_DSC_COUNT0 0x01 /* word - count 0 */
126 #define ICE1712_DSC_ADDR1 0x02 /* dword - base address 1 */
127 #define ICE1712_DSC_COUNT1 0x03 /* word - count 1 */
128 #define ICE1712_DSC_CONTROL 0x04 /* byte - control & status */
129 #define ICE1712_BUFFER1 0x80 /* buffer1 is active */
130 #define ICE1712_BUFFER1_AUTO 0x40 /* buffer1 auto init */
131 #define ICE1712_BUFFER0_AUTO 0x20 /* buffer0 auto init */
132 #define ICE1712_FLUSH 0x10 /* flush FIFO */
133 #define ICE1712_STEREO 0x08 /* stereo */
134 #define ICE1712_16BIT 0x04 /* 16-bit data */
135 #define ICE1712_PAUSE 0x02 /* pause */
136 #define ICE1712_START 0x01 /* start */
137 #define ICE1712_DSC_RATE 0x05 /* dword - rate */
138 #define ICE1712_DSC_VOLUME 0x06 /* word - volume control */
141 * Professional multi-track direct control registers
144 #define ICEMT(ice, x) ((ice)->profi_port + ICE1712_MT_##x)
146 #define ICE1712_MT_IRQ 0x00 /* byte - interrupt mask */
147 #define ICE1712_MULTI_CAPTURE 0x80 /* capture IRQ */
148 #define ICE1712_MULTI_PLAYBACK 0x40 /* playback IRQ */
149 #define ICE1712_MULTI_CAPSTATUS 0x02 /* capture IRQ status */
150 #define ICE1712_MULTI_PBKSTATUS 0x01 /* playback IRQ status */
151 #define ICE1712_MT_RATE 0x01 /* byte - sampling rate select */
152 #define ICE1712_SPDIF_MASTER 0x10 /* S/PDIF input is master clock */
153 #define ICE1712_MT_I2S_FORMAT 0x02 /* byte - I2S data format */
154 #define ICE1712_MT_AC97_INDEX 0x04 /* byte - AC'97 index */
155 #define ICE1712_MT_AC97_CMD 0x05 /* byte - AC'97 command & status */
156 /* look to ICE1712_AC97_* */
157 #define ICE1712_MT_AC97_DATA 0x06 /* word - AC'97 data */
158 #define ICE1712_MT_PLAYBACK_ADDR 0x10 /* dword - playback address */
159 #define ICE1712_MT_PLAYBACK_SIZE 0x14 /* word - playback size */
160 #define ICE1712_MT_PLAYBACK_COUNT 0x16 /* word - playback count */
161 #define ICE1712_MT_PLAYBACK_CONTROL 0x18 /* byte - control */
162 #define ICE1712_CAPTURE_START_SHADOW 0x04 /* capture start */
163 #define ICE1712_PLAYBACK_PAUSE 0x02 /* playback pause */
164 #define ICE1712_PLAYBACK_START 0x01 /* playback start */
165 #define ICE1712_MT_CAPTURE_ADDR 0x20 /* dword - capture address */
166 #define ICE1712_MT_CAPTURE_SIZE 0x24 /* word - capture size */
167 #define ICE1712_MT_CAPTURE_COUNT 0x26 /* word - capture count */
168 #define ICE1712_MT_CAPTURE_CONTROL 0x28 /* byte - control */
169 #define ICE1712_CAPTURE_START 0x01 /* capture start */
170 #define ICE1712_MT_ROUTE_PSDOUT03 0x30 /* word */
171 #define ICE1712_MT_ROUTE_SPDOUT 0x32 /* word */
172 #define ICE1712_MT_ROUTE_CAPTURE 0x34 /* dword */
173 #define ICE1712_MT_MONITOR_VOLUME 0x38 /* word */
174 #define ICE1712_MT_MONITOR_INDEX 0x3a /* byte */
175 #define ICE1712_MT_MONITOR_RATE 0x3b /* byte */
176 #define ICE1712_MT_MONITOR_ROUTECTRL 0x3c /* byte */
177 #define ICE1712_ROUTE_AC97 0x01 /* route digital mixer output to AC'97 */
178 #define ICE1712_MT_MONITOR_PEAKINDEX 0x3e /* byte */
179 #define ICE1712_MT_MONITOR_PEAKDATA 0x3f /* byte */
182 * Codec configuration bits
185 /* PCI[60] System Configuration */
186 #define ICE1712_CFG_CLOCK 0xc0
187 #define ICE1712_CFG_CLOCK512 0x00 /* 22.5692Mhz, 44.1kHz*512 */
188 #define ICE1712_CFG_CLOCK384 0x40 /* 16.9344Mhz, 44.1kHz*384 */
189 #define ICE1712_CFG_EXT 0x80 /* external clock */
190 #define ICE1712_CFG_2xMPU401 0x20 /* two MPU401 UARTs */
191 #define ICE1712_CFG_NO_CON_AC97 0x10 /* consumer AC'97 codec is not present */
192 #define ICE1712_CFG_ADC_MASK 0x0c /* one, two, three, four stereo ADCs */
193 #define ICE1712_CFG_DAC_MASK 0x03 /* one, two, three, four stereo DACs */
194 /* PCI[61] AC-Link Configuration */
195 #define ICE1712_CFG_PRO_I2S 0x80 /* multitrack converter: I2S or AC'97 */
196 #define ICE1712_CFG_AC97_PACKED 0x01 /* split or packed mode - AC'97 */
197 /* PCI[62] I2S Features */
198 #define ICE1712_CFG_I2S_VOLUME 0x80 /* volume/mute capability */
199 #define ICE1712_CFG_I2S_96KHZ 0x40 /* supports 96kHz sampling */
200 #define ICE1712_CFG_I2S_RESMASK 0x30 /* resolution mask, 16,18,20,24-bit */
201 #define ICE1712_CFG_I2S_OTHER 0x0f /* other I2S IDs */
202 /* PCI[63] S/PDIF Configuration */
203 #define ICE1712_CFG_I2S_CHIPID 0xfc /* I2S chip ID */
204 #define ICE1712_CFG_SPDIF_IN 0x02 /* S/PDIF input is present */
205 #define ICE1712_CFG_SPDIF_OUT 0x01 /* S/PDIF output is present */
209 * identical with DMA_XXX on i386 architecture.
211 #define ICE1712_DMA_MODE_WRITE 0x48
212 #define ICE1712_DMA_AUTOINIT 0x10
221 struct snd_ice1712_eeprom
{
222 unsigned int subvendor
; /* PCI[2c-2f] */
223 unsigned char size
; /* size of EEPROM image in bytes */
224 unsigned char version
; /* must be 1 (or 2 for vt1724) */
225 unsigned char data
[32];
226 unsigned int gpiomask
;
227 unsigned int gpiostate
;
228 unsigned int gpiodir
;
232 ICE_EEP1_CODEC
= 0, /* 06 */
233 ICE_EEP1_ACLINK
, /* 07 */
234 ICE_EEP1_I2SID
, /* 08 */
235 ICE_EEP1_SPDIF
, /* 09 */
236 ICE_EEP1_GPIO_MASK
, /* 0a */
237 ICE_EEP1_GPIO_STATE
, /* 0b */
238 ICE_EEP1_GPIO_DIR
, /* 0c */
239 ICE_EEP1_AC97_MAIN_LO
, /* 0d */
240 ICE_EEP1_AC97_MAIN_HI
, /* 0e */
241 ICE_EEP1_AC97_PCM_LO
, /* 0f */
242 ICE_EEP1_AC97_PCM_HI
, /* 10 */
243 ICE_EEP1_AC97_REC_LO
, /* 11 */
244 ICE_EEP1_AC97_REC_HI
, /* 12 */
245 ICE_EEP1_AC97_RECSRC
, /* 13 */
246 ICE_EEP1_DAC_ID
, /* 14 */
250 ICE_EEP1_ADC_ID
, /* 18 */
256 #define ice_has_con_ac97(ice) (!((ice)->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97))
259 struct snd_ak4xxx_private
{
260 unsigned int cif
: 1; /* CIF mode */
261 unsigned char caddr
; /* C0 and C1 bits */
262 unsigned int data_mask
; /* DATA gpio bit */
263 unsigned int clk_mask
; /* CLK gpio bit */
264 unsigned int cs_mask
; /* bit mask for select/deselect address */
265 unsigned int cs_addr
; /* bits to select address */
266 unsigned int cs_none
; /* bits to deselect address */
267 unsigned int add_flags
; /* additional bits at init */
268 unsigned int mask_flags
; /* total mask bits */
269 struct snd_akm4xxx_ops
{
270 void (*set_rate_val
)(struct snd_akm4xxx
*ak
, unsigned int rate
);
274 struct snd_ice1712_spdif
{
275 unsigned char cs8403_bits
;
276 unsigned char cs8403_stream_bits
;
277 struct snd_kcontrol
*stream_ctl
;
279 struct snd_ice1712_spdif_ops
{
280 void (*open
)(struct snd_ice1712
*, struct snd_pcm_substream
*);
281 void (*setup_rate
)(struct snd_ice1712
*, int rate
);
282 void (*close
)(struct snd_ice1712
*, struct snd_pcm_substream
*);
283 void (*default_get
)(struct snd_ice1712
*, struct snd_ctl_elem_value
*ucontrol
);
284 int (*default_put
)(struct snd_ice1712
*, struct snd_ctl_elem_value
*ucontrol
);
285 void (*stream_get
)(struct snd_ice1712
*, struct snd_ctl_elem_value
*ucontrol
);
286 int (*stream_put
)(struct snd_ice1712
*, struct snd_ctl_elem_value
*ucontrol
);
292 unsigned long conp_dma_size
;
293 unsigned long conc_dma_size
;
294 unsigned long prop_dma_size
;
295 unsigned long proc_dma_size
;
299 unsigned long ddma_port
;
300 unsigned long dmapath_port
;
301 unsigned long profi_port
;
304 struct snd_card
*card
;
306 struct snd_pcm
*pcm_ds
;
307 struct snd_pcm
*pcm_pro
;
308 struct snd_pcm_substream
*playback_con_substream
;
309 struct snd_pcm_substream
*playback_con_substream_ds
[6];
310 struct snd_pcm_substream
*capture_con_substream
;
311 struct snd_pcm_substream
*playback_pro_substream
;
312 struct snd_pcm_substream
*capture_pro_substream
;
313 unsigned int playback_pro_size
;
314 unsigned int capture_pro_size
;
315 unsigned int playback_con_virt_addr
[6];
316 unsigned int playback_con_active_buf
[6];
317 unsigned int capture_con_virt_addr
;
318 unsigned int ac97_ext_id
;
319 struct snd_ac97
*ac97
;
320 struct snd_rawmidi
*rmidi
[2];
323 struct snd_info_entry
*proc_entry
;
325 struct snd_ice1712_eeprom eeprom
;
327 unsigned int pro_volumes
[20];
328 unsigned int omni
: 1; /* Delta Omni I/O */
329 unsigned int dxr_enable
: 1; /* Terratec DXR enable for DMX6FIRE */
330 unsigned int vt1724
: 1;
331 unsigned int vt1720
: 1;
332 unsigned int has_spdif
: 1; /* VT1720/4 - has SPDIF I/O */
333 unsigned int force_pdma4
: 1; /* VT1720/4 - PDMA4 as non-spdif */
334 unsigned int force_rdma1
: 1; /* VT1720/4 - RDMA1 as non-spdif */
335 unsigned int num_total_dacs
; /* total DACs */
336 unsigned int num_total_adcs
; /* total ADCs */
337 unsigned int cur_rate
; /* current rate */
339 struct mutex open_mutex
;
340 struct snd_pcm_substream
*pcm_reserved
[4];
341 struct snd_pcm_hw_constraint_list
*hw_rates
; /* card-specific rate constraints */
343 unsigned int akm_codecs
;
344 struct snd_akm4xxx
*akm
;
345 struct snd_ice1712_spdif spdif
;
347 struct mutex i2c_mutex
; /* I2C mutex for ICE1724 registers */
348 struct snd_i2c_bus
*i2c
; /* I2C bus */
349 struct snd_i2c_device
*cs8427
; /* CS8427 I2C device */
350 unsigned int cs8427_timeout
; /* CS8427 reset timeout in HZ/100 */
352 struct ice1712_gpio
{
353 unsigned int direction
; /* current direction bits */
354 unsigned int write_mask
; /* current mask bits */
355 unsigned int saved
[2]; /* for ewx_i2c */
357 void (*set_mask
)(struct snd_ice1712
*ice
, unsigned int data
);
358 void (*set_dir
)(struct snd_ice1712
*ice
, unsigned int data
);
359 void (*set_data
)(struct snd_ice1712
*ice
, unsigned int data
);
360 unsigned int (*get_data
)(struct snd_ice1712
*ice
);
361 /* misc operators - move to another place? */
362 void (*set_pro_rate
)(struct snd_ice1712
*ice
, unsigned int rate
);
363 void (*i2s_mclk_changed
)(struct snd_ice1712
*ice
);
365 struct mutex gpio_mutex
;
367 /* other board-specific data */
369 /* additional i2c devices for EWS boards */
370 struct snd_i2c_device
*i2cdevs
[3];
371 /* AC97 register cache for Aureon */
373 unsigned short stac9744
[64];
374 unsigned int cs8415_mux
;
375 unsigned short master
[2];
376 unsigned short vol
[8];
377 unsigned char pca9554_out
;
379 /* AC97 register cache for Phase28 */
380 struct phase28_spec
{
381 unsigned short master
[2];
382 unsigned short vol
[8];
384 /* Hoontech-specific setting */
385 struct hoontech_spec
{
386 unsigned char boxbits
[4];
388 unsigned short boxconfig
[4];
391 struct ak4114
*ak4114
;
392 unsigned int analog
: 1;
400 * gpio access functions
402 static inline void snd_ice1712_gpio_set_dir(struct snd_ice1712
*ice
, unsigned int bits
)
404 ice
->gpio
.set_dir(ice
, bits
);
407 static inline void snd_ice1712_gpio_set_mask(struct snd_ice1712
*ice
, unsigned int bits
)
409 ice
->gpio
.set_mask(ice
, bits
);
412 static inline void snd_ice1712_gpio_write(struct snd_ice1712
*ice
, unsigned int val
)
414 ice
->gpio
.set_data(ice
, val
);
417 static inline unsigned int snd_ice1712_gpio_read(struct snd_ice1712
*ice
)
419 return ice
->gpio
.get_data(ice
);
423 * save and restore gpio status
424 * The access to gpio will be protected by mutex, so don't forget to
427 static inline void snd_ice1712_save_gpio_status(struct snd_ice1712
*ice
)
429 mutex_lock(&ice
->gpio_mutex
);
430 ice
->gpio
.saved
[0] = ice
->gpio
.direction
;
431 ice
->gpio
.saved
[1] = ice
->gpio
.write_mask
;
434 static inline void snd_ice1712_restore_gpio_status(struct snd_ice1712
*ice
)
436 ice
->gpio
.set_dir(ice
, ice
->gpio
.saved
[0]);
437 ice
->gpio
.set_mask(ice
, ice
->gpio
.saved
[1]);
438 ice
->gpio
.direction
= ice
->gpio
.saved
[0];
439 ice
->gpio
.write_mask
= ice
->gpio
.saved
[1];
440 mutex_unlock(&ice
->gpio_mutex
);
443 /* for bit controls */
444 #define ICE1712_GPIO(xiface, xname, xindex, mask, invert, xaccess) \
445 { .iface = xiface, .name = xname, .access = xaccess, .info = snd_ice1712_gpio_info, \
446 .get = snd_ice1712_gpio_get, .put = snd_ice1712_gpio_put, \
447 .private_value = mask | (invert << 24) }
449 int snd_ice1712_gpio_info(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
);
450 int snd_ice1712_gpio_get(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
);
451 int snd_ice1712_gpio_put(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
);
454 * set gpio direction, write mask and data
456 static inline void snd_ice1712_gpio_write_bits(struct snd_ice1712
*ice
,
457 unsigned int mask
, unsigned int bits
)
459 ice
->gpio
.direction
|= mask
;
460 snd_ice1712_gpio_set_dir(ice
, ice
->gpio
.direction
);
461 snd_ice1712_gpio_set_mask(ice
, ~mask
);
462 snd_ice1712_gpio_write(ice
, mask
& bits
);
465 int snd_ice1712_spdif_build_controls(struct snd_ice1712
*ice
);
467 int snd_ice1712_akm4xxx_init(struct snd_akm4xxx
*ak
, const struct snd_akm4xxx
*template,
468 const struct snd_ak4xxx_private
*priv
, struct snd_ice1712
*ice
);
469 void snd_ice1712_akm4xxx_free(struct snd_ice1712
*ice
);
470 int snd_ice1712_akm4xxx_build_controls(struct snd_ice1712
*ice
);
472 int snd_ice1712_init_cs8427(struct snd_ice1712
*ice
, int addr
);
474 static inline void snd_ice1712_write(struct snd_ice1712
* ice
, u8 addr
, u8 data
)
476 outb(addr
, ICEREG(ice
, INDEX
));
477 outb(data
, ICEREG(ice
, DATA
));
480 static inline u8
snd_ice1712_read(struct snd_ice1712
* ice
, u8 addr
)
482 outb(addr
, ICEREG(ice
, INDEX
));
483 return inb(ICEREG(ice
, DATA
));
491 struct snd_ice1712_card_info
{
492 unsigned int subvendor
;
496 int (*chip_init
)(struct snd_ice1712
*);
497 int (*build_controls
)(struct snd_ice1712
*);
498 unsigned int no_mpu401
: 1;
499 unsigned int mpu401_1_info_flags
;
500 unsigned int mpu401_2_info_flags
;
501 const char *mpu401_1_name
;
502 const char *mpu401_2_name
;
503 unsigned int eeprom_size
;
504 unsigned char *eeprom_data
;
508 #endif /* __SOUND_ICE1712_H */