include/asm-powerpc/pci-bridge.h

   1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H
   2 #define _ASM_POWERPC_PCI_BRIDGE_H
   3 #ifdef __KERNEL__
   4 /*
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version
   8  * 2 of the License, or (at your option) any later version.
   9  */
  10 #include <linux/pci.h>
  11 #include <linux/list.h>
  12 #include <linux/ioport.h>
  13
  14 #ifndef CONFIG_PPC64
  15 /*
  16  * Structure of a PCI controller (host bridge)
  17  */
  18 struct pci_controller {
  19         struct pci_bus *bus;
  20         char is_dynamic;
  21         void *arch_data;
  22         struct list_head list_node;
  23         struct device *parent;
  24
  25         int first_busno;
  26         int last_busno;
  27         int self_busno;
  28
  29         void __iomem *io_base_virt;
  30         resource_size_t io_base_phys;
  31
  32         /* Some machines (PReP) have a non 1:1 mapping of
  33          * the PCI memory space in the CPU bus space
  34          */
  35         resource_size_t pci_mem_offset;
  36
  37         struct pci_ops *ops;
  38         volatile unsigned int __iomem *cfg_addr;
  39         volatile void __iomem *cfg_data;
  40
  41         /*
  42          * Used for variants of PCI indirect handling and possible quirks:
  43          *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
  44          *  EXT_REG - provides access to PCI-e extended registers
  45          *  SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
  46          *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
  47          *   to determine which bus number to match on when generating type0
  48          *   config cycles
  49          *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
  50          *   hanging if we don't have link and try to do config cycles to
  51          *   anything but the PHB.  Only allow talking to the PHB if this is
  52          *   set.
  53          *  BIG_ENDIAN - cfg_addr is a big endian register
  54          */
  55 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE          0x00000001
  56 #define PPC_INDIRECT_TYPE_EXT_REG               0x00000002
  57 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS  0x00000004
  58 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK          0x00000008
  59 #define PPC_INDIRECT_TYPE_BIG_ENDIAN            0x00000010
  60         u32 indirect_type;
  61
  62         /* Currently, we limit ourselves to 1 IO range and 3 mem
  63          * ranges since the common pci_bus structure can't handle more
  64          */
  65         struct resource io_resource;
  66         struct resource mem_resources[3];
  67         int global_number;              /* PCI domain number */
  68 };
  69
  70 static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
  71 {
  72         return bus->sysdata;
  73 }
  74
  75 static inline int isa_vaddr_is_ioport(void __iomem *address)
  76 {
  77         /* No specific ISA handling on ppc32 at this stage, it
  78          * all goes through PCI
  79          */
  80         return 0;
  81 }
  82
  83 /* These are used for config access before all the PCI probing
  84    has been done. */
  85 extern int early_read_config_byte(struct pci_controller *hose, int bus,
  86                         int dev_fn, int where, u8 *val);
  87 extern int early_read_config_word(struct pci_controller *hose, int bus,
  88                         int dev_fn, int where, u16 *val);
  89 extern int early_read_config_dword(struct pci_controller *hose, int bus,
  90                         int dev_fn, int where, u32 *val);
  91 extern int early_write_config_byte(struct pci_controller *hose, int bus,
  92                         int dev_fn, int where, u8 val);
  93 extern int early_write_config_word(struct pci_controller *hose, int bus,
  94                         int dev_fn, int where, u16 val);
  95 extern int early_write_config_dword(struct pci_controller *hose, int bus,
  96                         int dev_fn, int where, u32 val);
  97
  98 extern int early_find_capability(struct pci_controller *hose, int bus,
  99                                  int dev_fn, int cap);
 100
 101 extern void setup_indirect_pci(struct pci_controller* hose,
 102                                resource_size_t cfg_addr,
 103                                resource_size_t cfg_data, u32 flags);
 104 extern void setup_grackle(struct pci_controller *hose);
 105 extern void __init update_bridge_resource(struct pci_dev *dev,
 106                                           struct resource *res);
 107
 108 #else   /* CONFIG_PPC64 */
 109
 110 /*
 111  * Structure of a PCI controller (host bridge)
 112  */
 113 struct pci_controller {
 114         struct pci_bus *bus;
 115         char is_dynamic;
 116         int node;
 117         void *arch_data;
 118         struct list_head list_node;
 119         struct device *parent;
 120
 121         int first_busno;
 122         int last_busno;
 123
 124         void __iomem *io_base_virt;
 125         void *io_base_alloc;
 126         resource_size_t io_base_phys;
 127
 128         /* Some machines have a non 1:1 mapping of
 129          * the PCI memory space in the CPU bus space
 130          */
 131         resource_size_t pci_mem_offset;
 132         unsigned long pci_io_size;
 133
 134         struct pci_ops *ops;
 135         volatile unsigned int __iomem *cfg_addr;
 136         volatile void __iomem *cfg_data;
 137
 138         /* Currently, we limit ourselves to 1 IO range and 3 mem
 139          * ranges since the common pci_bus structure can't handle more
 140          */
 141         struct resource io_resource;
 142         struct resource mem_resources[3];
 143         int global_number;
 144         unsigned long buid;
 145         unsigned long dma_window_base_cur;
 146         unsigned long dma_window_size;
 147
 148         void *private_data;
 149 };
 150
 151 /*
 152  * PCI stuff, for nodes representing PCI devices, pointed to
 153  * by device_node->data.
 154  */
 155 struct iommu_table;
 156 struct device_node;
 157
 158 struct pci_dn {
 159         int     busno;                  /* pci bus number */
 160         int     bussubno;               /* pci subordinate bus number */
 161         int     devfn;                  /* pci device and function number */
 162         int     class_code;             /* pci device class */
 163
 164         struct  pci_controller *phb;    /* for pci devices */
 165         struct  iommu_table *iommu_table;       /* for phb's or bridges */
 166         struct  pci_dev *pcidev;        /* back-pointer to the pci device */
 167         struct  device_node *node;      /* back-pointer to the device_node */
 168
 169         int     pci_ext_config_space;   /* for pci devices */
 170
 171 #ifdef CONFIG_EEH
 172         int     eeh_mode;               /* See eeh.h for possible EEH_MODEs */
 173         int     eeh_config_addr;
 174         int     eeh_pe_config_addr; /* new-style partition endpoint address */
 175         int     eeh_check_count;        /* # times driver ignored error */
 176         int     eeh_freeze_count;       /* # times this device froze up. */
 177         int     eeh_false_positives;    /* # times this device reported #ff's */
 178         u32     config_space[16];       /* saved PCI config space */
 179 #endif
 180 };
 181
 182 /* Get the pointer to a device_node's pci_dn */
 183 #define PCI_DN(dn)      ((struct pci_dn *) (dn)->data)
 184
 185 extern struct device_node *fetch_dev_dn(struct pci_dev *dev);
 186
 187 /* Get a device_node from a pci_dev.  This code must be fast except
 188  * in the case where the sysdata is incorrect and needs to be fixed
 189  * up (this will only happen once).
 190  * In this case the sysdata will have been inherited from a PCI host
 191  * bridge or a PCI-PCI bridge further up the tree, so it will point
 192  * to a valid struct pci_dn, just not the one we want.
 193  */
 194 static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
 195 {
 196         struct device_node *dn = dev->sysdata;
 197         struct pci_dn *pdn = dn->data;
 198
 199         if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number)
 200                 return dn;      /* fast path.  sysdata is good */
 201         return fetch_dev_dn(dev);
 202 }
 203
 204 static inline int pci_device_from_OF_node(struct device_node *np,
 205                                           u8 *bus, u8 *devfn)
 206 {
 207         if (!PCI_DN(np))
 208                 return -ENODEV;
 209         *bus = PCI_DN(np)->busno;
 210         *devfn = PCI_DN(np)->devfn;
 211         return 0;
 212 }
 213
 214 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
 215 {
 216         if (bus->self)
 217                 return pci_device_to_OF_node(bus->self);
 218         else
 219                 return bus->sysdata; /* Must be root bus (PHB) */
 220 }
 221
 222 /** Find the bus corresponding to the indicated device node */
 223 extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
 224
 225 /** Remove all of the PCI devices under this bus */
 226 extern void pcibios_remove_pci_devices(struct pci_bus *bus);
 227
 228 /** Discover new pci devices under this bus, and add them */
 229 extern void pcibios_add_pci_devices(struct pci_bus *bus);
 230 extern void pcibios_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus);
 231
 232 extern int pcibios_remove_root_bus(struct pci_controller *phb);
 233
 234 static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
 235 {
 236         struct device_node *busdn = bus->sysdata;
 237
 238         BUG_ON(busdn == NULL);
 239         return PCI_DN(busdn)->phb;
 240 }
 241
 242
 243 extern void isa_bridge_find_early(struct pci_controller *hose);
 244
 245 static inline int isa_vaddr_is_ioport(void __iomem *address)
 246 {
 247         /* Check if address hits the reserved legacy IO range */
 248         unsigned long ea = (unsigned long)address;
 249         return ea >= ISA_IO_BASE && ea < ISA_IO_END;
 250 }
 251
 252 extern int pcibios_unmap_io_space(struct pci_bus *bus);
 253 extern int pcibios_map_io_space(struct pci_bus *bus);
 254
 255 /* Return values for ppc_md.pci_probe_mode function */
 256 #define PCI_PROBE_NONE          -1      /* Don't look at this bus at all */
 257 #define PCI_PROBE_NORMAL        0       /* Do normal PCI probing */
 258 #define PCI_PROBE_DEVTREE       1       /* Instantiate from device tree */
 259
 260 #ifdef CONFIG_NUMA
 261 #define PHB_SET_NODE(PHB, NODE)         ((PHB)->node = (NODE))
 262 #else
 263 #define PHB_SET_NODE(PHB, NODE)         ((PHB)->node = -1)
 264 #endif
 265
 266 #endif  /* CONFIG_PPC64 */
 267
 268 /* Get the PCI host controller for an OF device */
 269 extern struct pci_controller *pci_find_hose_for_OF_device(
 270                         struct device_node* node);
 271
 272 /* Fill up host controller resources from the OF node */
 273 extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
 274                         struct device_node *dev, int primary);
 275
 276 /* Allocate & free a PCI host bridge structure */
 277 extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
 278 extern void pcibios_free_controller(struct pci_controller *phb);
 279
 280 #ifdef CONFIG_PCI
 281 extern unsigned long pci_address_to_pio(phys_addr_t address);
 282 extern int pcibios_vaddr_is_ioport(void __iomem *address);
 283 #else
 284 static inline unsigned long pci_address_to_pio(phys_addr_t address)
 285 {
 286         return (unsigned long)-1;
 287 }
 288 static inline int pcibios_vaddr_is_ioport(void __iomem *address)
 289 {
 290         return 0;
 291 }
 292 #endif  /* CONFIG_PCI */
 293
 294 #endif  /* __KERNEL__ */
 295 #endif  /* _ASM_POWERPC_PCI_BRIDGE_H */