2 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2003 Red Hat <alan@redhat.com>
4 * Copyright (C) 2007-2008 MontaVista Software, Inc.
5 * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz
7 * May be copied or modified under the terms of the GNU General Public License
9 * Documentation for CMD680:
10 * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2
12 * Documentation for SiI 3112:
13 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
15 * Errata and other documentation only available under NDA.
19 * If you are using Marvell SATA-IDE adapters with Maxtor drives
20 * ensure the system is set up for ATA100/UDMA5, not UDMA6.
22 * If you are using WD drives with SATA bridges you must set the
23 * drive to "Single". "Master" will hang.
25 * If you have strange problems with nVidia chipset systems please
26 * see the SI support documentation and update your system BIOS
29 * The Dell DRAC4 has some interesting features including effectively hot
30 * unplugging/replugging the virtual CD interface when the DRAC is reset.
31 * This often causes drivers/ide/siimage to panic but is ok with the rather
32 * smarter code in libata.
39 #include <linux/types.h>
40 #include <linux/module.h>
41 #include <linux/pci.h>
42 #include <linux/hdreg.h>
43 #include <linux/ide.h>
44 #include <linux/init.h>
47 #define DRV_NAME "siimage"
50 * pdev_is_sata - check if device is SATA
51 * @pdev: PCI device to check
53 * Returns true if this is a SATA controller
56 static int pdev_is_sata(struct pci_dev
*pdev
)
58 #ifdef CONFIG_BLK_DEV_IDE_SATA
59 switch (pdev
->device
) {
60 case PCI_DEVICE_ID_SII_3112
:
61 case PCI_DEVICE_ID_SII_1210SA
:
63 case PCI_DEVICE_ID_SII_680
:
72 * is_sata - check if hwif is SATA
73 * @hwif: interface to check
75 * Returns true if this is a SATA controller
78 static inline int is_sata(ide_hwif_t
*hwif
)
80 return pdev_is_sata(to_pci_dev(hwif
->dev
));
84 * siimage_selreg - return register base
88 * Turn a config register offset into the right address in either
89 * PCI space or MMIO space to access the control register in question
90 * Thankfully this is a configuration operation, so isn't performance
94 static unsigned long siimage_selreg(ide_hwif_t
*hwif
, int r
)
96 unsigned long base
= (unsigned long)hwif
->hwif_data
;
99 if (hwif
->host_flags
& IDE_HFLAG_MMIO
)
100 base
+= hwif
->channel
<< 6;
102 base
+= hwif
->channel
<< 4;
107 * siimage_seldev - return register base
111 * Turn a config register offset into the right address in either
112 * PCI space or MMIO space to access the control register in question
113 * including accounting for the unit shift.
116 static inline unsigned long siimage_seldev(ide_drive_t
*drive
, int r
)
118 ide_hwif_t
*hwif
= HWIF(drive
);
119 unsigned long base
= (unsigned long)hwif
->hwif_data
;
122 if (hwif
->host_flags
& IDE_HFLAG_MMIO
)
123 base
+= hwif
->channel
<< 6;
125 base
+= hwif
->channel
<< 4;
126 base
|= drive
->select
.b
.unit
<< drive
->select
.b
.unit
;
130 static u8
sil_ioread8(struct pci_dev
*dev
, unsigned long addr
)
132 struct ide_host
*host
= pci_get_drvdata(dev
);
136 tmp
= readb((void __iomem
*)addr
);
138 pci_read_config_byte(dev
, addr
, &tmp
);
143 static u16
sil_ioread16(struct pci_dev
*dev
, unsigned long addr
)
145 struct ide_host
*host
= pci_get_drvdata(dev
);
149 tmp
= readw((void __iomem
*)addr
);
151 pci_read_config_word(dev
, addr
, &tmp
);
156 static void sil_iowrite8(struct pci_dev
*dev
, u8 val
, unsigned long addr
)
158 struct ide_host
*host
= pci_get_drvdata(dev
);
161 writeb(val
, (void __iomem
*)addr
);
163 pci_write_config_byte(dev
, addr
, val
);
166 static void sil_iowrite16(struct pci_dev
*dev
, u16 val
, unsigned long addr
)
168 struct ide_host
*host
= pci_get_drvdata(dev
);
171 writew(val
, (void __iomem
*)addr
);
173 pci_write_config_word(dev
, addr
, val
);
176 static void sil_iowrite32(struct pci_dev
*dev
, u32 val
, unsigned long addr
)
178 struct ide_host
*host
= pci_get_drvdata(dev
);
181 writel(val
, (void __iomem
*)addr
);
183 pci_write_config_dword(dev
, addr
, val
);
187 * sil_udma_filter - compute UDMA mask
190 * Compute the available UDMA speeds for the device on the interface.
192 * For the CMD680 this depends on the clocking mode (scsc), for the
193 * SI3112 SATA controller life is a bit simpler.
196 static u8
sil_pata_udma_filter(ide_drive_t
*drive
)
198 ide_hwif_t
*hwif
= drive
->hwif
;
199 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
200 unsigned long base
= (unsigned long)hwif
->hwif_data
;
203 base
+= (hwif
->host_flags
& IDE_HFLAG_MMIO
) ? 0x4A : 0x8A;
205 scsc
= sil_ioread8(dev
, base
);
207 switch (scsc
& 0x30) {
211 case 0x20: /* 2xPCI */
217 default: /* Disabled ? */
224 static u8
sil_sata_udma_filter(ide_drive_t
*drive
)
226 return strstr(drive
->id
->model
, "Maxtor") ? ATA_UDMA5
: ATA_UDMA6
;
230 * sil_set_pio_mode - set host controller for PIO mode
232 * @pio: PIO mode number
234 * Load the timing settings for this device mode into the
235 * controller. If we are in PIO mode 3 or 4 turn on IORDY
236 * monitoring (bit 9). The TF timing is bits 31:16
239 static void sil_set_pio_mode(ide_drive_t
*drive
, u8 pio
)
241 static const u16 tf_speed
[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
242 static const u16 data_speed
[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
244 ide_hwif_t
*hwif
= HWIF(drive
);
245 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
246 ide_drive_t
*pair
= ide_get_paired_drive(drive
);
249 unsigned long addr
= siimage_seldev(drive
, 0x04);
250 unsigned long tfaddr
= siimage_selreg(hwif
, 0x02);
251 unsigned long base
= (unsigned long)hwif
->hwif_data
;
253 u8 mmio
= (hwif
->host_flags
& IDE_HFLAG_MMIO
) ? 1 : 0;
254 u8 addr_mask
= hwif
->channel
? (mmio
? 0xF4 : 0x84)
255 : (mmio
? 0xB4 : 0x80);
257 u8 unit
= drive
->select
.b
.unit
;
259 /* trim *taskfile* PIO to the slowest of the master/slave */
261 u8 pair_pio
= ide_get_best_pio_mode(pair
, 255, 4);
263 if (pair_pio
< tf_pio
)
267 /* cheat for now and use the docs */
268 speedp
= data_speed
[pio
];
269 speedt
= tf_speed
[tf_pio
];
271 sil_iowrite16(dev
, speedp
, addr
);
272 sil_iowrite16(dev
, speedt
, tfaddr
);
274 /* now set up IORDY */
275 speedp
= sil_ioread16(dev
, tfaddr
- 2);
279 sil_iowrite16(dev
, speedp
, tfaddr
- 2);
281 mode
= sil_ioread8(dev
, base
+ addr_mask
);
282 mode
&= ~(unit
? 0x30 : 0x03);
283 mode
|= unit
? 0x10 : 0x01;
284 sil_iowrite8(dev
, mode
, base
+ addr_mask
);
288 * sil_set_dma_mode - set host controller for DMA mode
292 * Tune the SiI chipset for the desired DMA mode.
295 static void sil_set_dma_mode(ide_drive_t
*drive
, const u8 speed
)
297 static const u8 ultra6
[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
298 static const u8 ultra5
[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
299 static const u16 dma
[] = { 0x2208, 0x10C2, 0x10C1 };
301 ide_hwif_t
*hwif
= HWIF(drive
);
302 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
303 u16 ultra
= 0, multi
= 0;
304 u8 mode
= 0, unit
= drive
->select
.b
.unit
;
305 unsigned long base
= (unsigned long)hwif
->hwif_data
;
306 u8 mmio
= (hwif
->host_flags
& IDE_HFLAG_MMIO
) ? 1 : 0;
307 u8 scsc
= 0, addr_mask
= hwif
->channel
? (mmio
? 0xF4 : 0x84)
308 : (mmio
? 0xB4 : 0x80);
309 unsigned long ma
= siimage_seldev(drive
, 0x08);
310 unsigned long ua
= siimage_seldev(drive
, 0x0C);
312 scsc
= sil_ioread8 (dev
, base
+ (mmio
? 0x4A : 0x8A));
313 mode
= sil_ioread8 (dev
, base
+ addr_mask
);
314 multi
= sil_ioread16(dev
, ma
);
315 ultra
= sil_ioread16(dev
, ua
);
317 mode
&= ~(unit
? 0x30 : 0x03);
319 scsc
= ((scsc
& 0x30) == 0x00) ? 0 : 1;
321 scsc
= is_sata(hwif
) ? 1 : scsc
;
323 if (speed
>= XFER_UDMA_0
) {
325 ultra
|= scsc
? ultra6
[speed
- XFER_UDMA_0
] :
326 ultra5
[speed
- XFER_UDMA_0
];
327 mode
|= unit
? 0x30 : 0x03;
329 multi
= dma
[speed
- XFER_MW_DMA_0
];
330 mode
|= unit
? 0x20 : 0x02;
333 sil_iowrite8 (dev
, mode
, base
+ addr_mask
);
334 sil_iowrite16(dev
, multi
, ma
);
335 sil_iowrite16(dev
, ultra
, ua
);
338 /* returns 1 if dma irq issued, 0 otherwise */
339 static int siimage_io_dma_test_irq(ide_drive_t
*drive
)
341 ide_hwif_t
*hwif
= HWIF(drive
);
342 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
344 unsigned long addr
= siimage_selreg(hwif
, 1);
346 /* return 1 if INTR asserted */
347 if (inb(hwif
->dma_base
+ ATA_DMA_STATUS
) & 4)
350 /* return 1 if Device INTR asserted */
351 pci_read_config_byte(dev
, addr
, &dma_altstat
);
353 return 0; /* return 1; */
359 * siimage_mmio_dma_test_irq - check we caused an IRQ
360 * @drive: drive we are testing
362 * Check if we caused an IDE DMA interrupt. We may also have caused
363 * SATA status interrupts, if so we clean them up and continue.
366 static int siimage_mmio_dma_test_irq(ide_drive_t
*drive
)
368 ide_hwif_t
*hwif
= HWIF(drive
);
369 unsigned long addr
= siimage_selreg(hwif
, 0x1);
370 void __iomem
*sata_error_addr
371 = (void __iomem
*)hwif
->sata_scr
[SATA_ERROR_OFFSET
];
373 if (sata_error_addr
) {
374 unsigned long base
= (unsigned long)hwif
->hwif_data
;
375 u32 ext_stat
= readl((void __iomem
*)(base
+ 0x10));
378 if (ext_stat
& ((hwif
->channel
) ? 0x40 : 0x10)) {
379 u32 sata_error
= readl(sata_error_addr
);
381 writel(sata_error
, sata_error_addr
);
382 watchdog
= (sata_error
& 0x00680000) ? 1 : 0;
383 printk(KERN_WARNING
"%s: sata_error = 0x%08x, "
384 "watchdog = %d, %s\n",
385 drive
->name
, sata_error
, watchdog
, __func__
);
387 watchdog
= (ext_stat
& 0x8000) ? 1 : 0;
390 if (!(ext_stat
& 0x0404) && !watchdog
)
394 /* return 1 if INTR asserted */
395 if (readb((void __iomem
*)(hwif
->dma_base
+ ATA_DMA_STATUS
)) & 4)
398 /* return 1 if Device INTR asserted */
399 if (readb((void __iomem
*)addr
) & 8)
400 return 0; /* return 1; */
405 static int siimage_dma_test_irq(ide_drive_t
*drive
)
407 if (drive
->hwif
->host_flags
& IDE_HFLAG_MMIO
)
408 return siimage_mmio_dma_test_irq(drive
);
410 return siimage_io_dma_test_irq(drive
);
414 * sil_sata_reset_poll - wait for SATA reset
415 * @drive: drive we are resetting
417 * Poll the SATA phy and see whether it has come back from the dead
421 static int sil_sata_reset_poll(ide_drive_t
*drive
)
423 ide_hwif_t
*hwif
= drive
->hwif
;
424 void __iomem
*sata_status_addr
425 = (void __iomem
*)hwif
->sata_scr
[SATA_STATUS_OFFSET
];
427 if (sata_status_addr
) {
428 /* SATA Status is available only when in MMIO mode */
429 u32 sata_stat
= readl(sata_status_addr
);
431 if ((sata_stat
& 0x03) != 0x03) {
432 printk(KERN_WARNING
"%s: reset phy dead, status=0x%08x\n",
433 hwif
->name
, sata_stat
);
442 * sil_sata_pre_reset - reset hook
443 * @drive: IDE device being reset
445 * For the SATA devices we need to handle recalibration/geometry
449 static void sil_sata_pre_reset(ide_drive_t
*drive
)
451 if (drive
->media
== ide_disk
) {
452 drive
->special
.b
.set_geometry
= 0;
453 drive
->special
.b
.recalibrate
= 0;
458 * init_chipset_siimage - set up an SI device
461 * Perform the initial PCI set up for this device. Attempt to switch
462 * to 133 MHz clocking if the system isn't already set up to do it.
465 static unsigned int __devinit
init_chipset_siimage(struct pci_dev
*dev
)
467 struct ide_host
*host
= pci_get_drvdata(dev
);
468 void __iomem
*ioaddr
= host
->host_priv
;
469 unsigned long base
, scsc_addr
;
470 u8 rev
= dev
->revision
, tmp
;
472 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, rev
? 1 : 255);
477 base
= (unsigned long)ioaddr
;
479 if (ioaddr
&& pdev_is_sata(dev
)) {
482 /* make sure IDE0/1 interrupts are not masked */
483 irq_mask
= (1 << 22) | (1 << 23);
484 tmp32
= readl(ioaddr
+ 0x48);
485 if (tmp32
& irq_mask
) {
487 writel(tmp32
, ioaddr
+ 0x48);
488 readl(ioaddr
+ 0x48); /* flush */
490 writel(0, ioaddr
+ 0x148);
491 writel(0, ioaddr
+ 0x1C8);
494 sil_iowrite8(dev
, 0, base
? (base
+ 0xB4) : 0x80);
495 sil_iowrite8(dev
, 0, base
? (base
+ 0xF4) : 0x84);
497 scsc_addr
= base
? (base
+ 0x4A) : 0x8A;
498 tmp
= sil_ioread8(dev
, scsc_addr
);
500 switch (tmp
& 0x30) {
502 /* On 100 MHz clocking, try and switch to 133 MHz */
503 sil_iowrite8(dev
, tmp
| 0x10, scsc_addr
);
506 /* Clocking is disabled, attempt to force 133MHz clocking. */
507 sil_iowrite8(dev
, tmp
& ~0x20, scsc_addr
);
509 /* On 133Mhz clocking. */
512 /* On PCIx2 clocking. */
516 tmp
= sil_ioread8(dev
, scsc_addr
);
518 sil_iowrite8 (dev
, 0x72, base
+ 0xA1);
519 sil_iowrite16(dev
, 0x328A, base
+ 0xA2);
520 sil_iowrite32(dev
, 0x62DD62DD, base
+ 0xA4);
521 sil_iowrite32(dev
, 0x43924392, base
+ 0xA8);
522 sil_iowrite32(dev
, 0x40094009, base
+ 0xAC);
523 sil_iowrite8 (dev
, 0x72, base
? (base
+ 0xE1) : 0xB1);
524 sil_iowrite16(dev
, 0x328A, base
? (base
+ 0xE2) : 0xB2);
525 sil_iowrite32(dev
, 0x62DD62DD, base
? (base
+ 0xE4) : 0xB4);
526 sil_iowrite32(dev
, 0x43924392, base
? (base
+ 0xE8) : 0xB8);
527 sil_iowrite32(dev
, 0x40094009, base
? (base
+ 0xEC) : 0xBC);
529 if (base
&& pdev_is_sata(dev
)) {
530 writel(0xFFFF0000, ioaddr
+ 0x108);
531 writel(0xFFFF0000, ioaddr
+ 0x188);
532 writel(0x00680000, ioaddr
+ 0x148);
533 writel(0x00680000, ioaddr
+ 0x1C8);
536 /* report the clocking mode of the controller */
537 if (!pdev_is_sata(dev
)) {
538 static const char *clk_str
[] =
539 { "== 100", "== 133", "== 2X PCI", "DISABLED!" };
542 printk(KERN_INFO DRV_NAME
" %s: BASE CLOCK %s\n",
543 pci_name(dev
), clk_str
[tmp
& 3]);
550 * init_mmio_iops_siimage - set up the iops for MMIO
551 * @hwif: interface to set up
553 * The basic setup here is fairly simple, we can use standard MMIO
554 * operations. However we do have to set the taskfile register offsets
555 * by hand as there isn't a standard defined layout for them this time.
557 * The hardware supports buffered taskfiles and also some rather nice
558 * extended PRD tables. For better SI3112 support use the libata driver
561 static void __devinit
init_mmio_iops_siimage(ide_hwif_t
*hwif
)
563 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
564 struct ide_host
*host
= pci_get_drvdata(dev
);
565 void *addr
= host
->host_priv
;
566 u8 ch
= hwif
->channel
;
567 struct ide_io_ports
*io_ports
= &hwif
->io_ports
;
571 * Fill in the basic hwif bits
573 hwif
->host_flags
|= IDE_HFLAG_MMIO
;
575 hwif
->hwif_data
= addr
;
578 * Now set up the hw. We have to do this ourselves as the
579 * MMIO layout isn't the same as the standard port based I/O.
581 memset(io_ports
, 0, sizeof(*io_ports
));
583 base
= (unsigned long)addr
;
590 * The buffered task file doesn't have status/control, so we
591 * can't currently use it sanely since we want to use LBA48 mode.
593 io_ports
->data_addr
= base
;
594 io_ports
->error_addr
= base
+ 1;
595 io_ports
->nsect_addr
= base
+ 2;
596 io_ports
->lbal_addr
= base
+ 3;
597 io_ports
->lbam_addr
= base
+ 4;
598 io_ports
->lbah_addr
= base
+ 5;
599 io_ports
->device_addr
= base
+ 6;
600 io_ports
->status_addr
= base
+ 7;
601 io_ports
->ctl_addr
= base
+ 10;
603 if (pdev_is_sata(dev
)) {
604 base
= (unsigned long)addr
;
607 hwif
->sata_scr
[SATA_STATUS_OFFSET
] = base
+ 0x104;
608 hwif
->sata_scr
[SATA_ERROR_OFFSET
] = base
+ 0x108;
609 hwif
->sata_scr
[SATA_CONTROL_OFFSET
] = base
+ 0x100;
612 hwif
->irq
= dev
->irq
;
614 hwif
->dma_base
= (unsigned long)addr
+ (ch
? 0x08 : 0x00);
617 static int is_dev_seagate_sata(ide_drive_t
*drive
)
619 const char *s
= &drive
->id
->model
[0];
620 unsigned len
= strnlen(s
, sizeof(drive
->id
->model
));
622 if ((len
> 4) && (!memcmp(s
, "ST", 2)))
623 if ((!memcmp(s
+ len
- 2, "AS", 2)) ||
624 (!memcmp(s
+ len
- 3, "ASL", 3))) {
625 printk(KERN_INFO
"%s: applying pessimistic Seagate "
626 "errata fix\n", drive
->name
);
634 * sil_quirkproc - post probe fixups
637 * Called after drive probe we use this to decide whether the
638 * Seagate fixup must be applied. This used to be in init_iops but
639 * that can occur before we know what drives are present.
642 static void sil_quirkproc(ide_drive_t
*drive
)
644 ide_hwif_t
*hwif
= drive
->hwif
;
646 /* Try and rise the rqsize */
647 if (!is_sata(hwif
) || !is_dev_seagate_sata(drive
))
652 * init_iops_siimage - set up iops
653 * @hwif: interface to set up
655 * Do the basic setup for the SIIMAGE hardware interface
656 * and then do the MMIO setup if we can. This is the first
657 * look in we get for setting up the hwif so that we
658 * can get the iops right before using them.
661 static void __devinit
init_iops_siimage(ide_hwif_t
*hwif
)
663 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
664 struct ide_host
*host
= pci_get_drvdata(dev
);
666 hwif
->hwif_data
= NULL
;
668 /* Pessimal until we finish probing */
672 init_mmio_iops_siimage(hwif
);
676 * sil_cable_detect - cable detection
677 * @hwif: interface to check
679 * Check for the presence of an ATA66 capable cable on the interface.
682 static u8
sil_cable_detect(ide_hwif_t
*hwif
)
684 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
685 unsigned long addr
= siimage_selreg(hwif
, 0);
686 u8 ata66
= sil_ioread8(dev
, addr
);
688 return (ata66
& 0x01) ? ATA_CBL_PATA80
: ATA_CBL_PATA40
;
691 static const struct ide_port_ops sil_pata_port_ops
= {
692 .set_pio_mode
= sil_set_pio_mode
,
693 .set_dma_mode
= sil_set_dma_mode
,
694 .quirkproc
= sil_quirkproc
,
695 .udma_filter
= sil_pata_udma_filter
,
696 .cable_detect
= sil_cable_detect
,
699 static const struct ide_port_ops sil_sata_port_ops
= {
700 .set_pio_mode
= sil_set_pio_mode
,
701 .set_dma_mode
= sil_set_dma_mode
,
702 .reset_poll
= sil_sata_reset_poll
,
703 .pre_reset
= sil_sata_pre_reset
,
704 .quirkproc
= sil_quirkproc
,
705 .udma_filter
= sil_sata_udma_filter
,
706 .cable_detect
= sil_cable_detect
,
709 static const struct ide_dma_ops sil_dma_ops
= {
710 .dma_host_set
= ide_dma_host_set
,
711 .dma_setup
= ide_dma_setup
,
712 .dma_exec_cmd
= ide_dma_exec_cmd
,
713 .dma_start
= ide_dma_start
,
714 .dma_end
= __ide_dma_end
,
715 .dma_test_irq
= siimage_dma_test_irq
,
716 .dma_timeout
= ide_dma_timeout
,
717 .dma_lost_irq
= ide_dma_lost_irq
,
720 #define DECLARE_SII_DEV(p_ops) \
723 .init_chipset = init_chipset_siimage, \
724 .init_iops = init_iops_siimage, \
726 .dma_ops = &sil_dma_ops, \
727 .pio_mask = ATA_PIO4, \
728 .mwdma_mask = ATA_MWDMA2, \
729 .udma_mask = ATA_UDMA6, \
732 static const struct ide_port_info siimage_chipsets
[] __devinitdata
= {
733 /* 0: SiI680 */ DECLARE_SII_DEV(&sil_pata_port_ops
),
734 /* 1: SiI3112 */ DECLARE_SII_DEV(&sil_sata_port_ops
)
738 * siimage_init_one - PCI layer discovery entry
740 * @id: ident table entry
742 * Called by the PCI code when it finds an SiI680 or SiI3112 controller.
743 * We then use the IDE PCI generic helper to do most of the work.
746 static int __devinit
siimage_init_one(struct pci_dev
*dev
,
747 const struct pci_device_id
*id
)
749 void __iomem
*ioaddr
= NULL
;
750 resource_size_t bar5
= pci_resource_start(dev
, 5);
751 unsigned long barsize
= pci_resource_len(dev
, 5);
753 struct ide_port_info d
;
754 u8 idx
= id
->driver_data
;
757 d
= siimage_chipsets
[idx
];
760 static int first
= 1;
763 printk(KERN_INFO DRV_NAME
": For full SATA support you "
764 "should use the libata sata_sil module.\n");
768 d
.host_flags
|= IDE_HFLAG_NO_ATAPI_DMA
;
771 rc
= pci_enable_device(dev
);
775 pci_read_config_byte(dev
, 0x8A, &BA5_EN
);
776 if ((BA5_EN
& 0x01) || bar5
) {
778 * Drop back to PIO if we can't map the MMIO. Some systems
779 * seem to get terminally confused in the PCI spaces.
781 if (!request_mem_region(bar5
, barsize
, d
.name
)) {
782 printk(KERN_WARNING DRV_NAME
" %s: MMIO ports not "
783 "available\n", pci_name(dev
));
785 ioaddr
= ioremap(bar5
, barsize
);
787 release_mem_region(bar5
, barsize
);
791 rc
= ide_pci_init_one(dev
, &d
, ioaddr
);
795 release_mem_region(bar5
, barsize
);
797 pci_disable_device(dev
);
803 static void __devexit
siimage_remove(struct pci_dev
*dev
)
805 struct ide_host
*host
= pci_get_drvdata(dev
);
806 void __iomem
*ioaddr
= host
->host_priv
;
811 resource_size_t bar5
= pci_resource_start(dev
, 5);
812 unsigned long barsize
= pci_resource_len(dev
, 5);
815 release_mem_region(bar5
, barsize
);
818 pci_disable_device(dev
);
821 static const struct pci_device_id siimage_pci_tbl
[] = {
822 { PCI_VDEVICE(CMD
, PCI_DEVICE_ID_SII_680
), 0 },
823 #ifdef CONFIG_BLK_DEV_IDE_SATA
824 { PCI_VDEVICE(CMD
, PCI_DEVICE_ID_SII_3112
), 1 },
825 { PCI_VDEVICE(CMD
, PCI_DEVICE_ID_SII_1210SA
), 1 },
829 MODULE_DEVICE_TABLE(pci
, siimage_pci_tbl
);
831 static struct pci_driver driver
= {
833 .id_table
= siimage_pci_tbl
,
834 .probe
= siimage_init_one
,
835 .remove
= __devexit_p(siimage_remove
),
838 static int __init
siimage_ide_init(void)
840 return ide_pci_register_driver(&driver
);
843 static void __exit
siimage_ide_exit(void)
845 pci_unregister_driver(&driver
);
848 module_init(siimage_ide_init
);
849 module_exit(siimage_ide_exit
);
851 MODULE_AUTHOR("Andre Hedrick, Alan Cox");
852 MODULE_DESCRIPTION("PCI driver module for SiI IDE");
853 MODULE_LICENSE("GPL");