?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
block: use rq complete marking in blk_abort_request()
[firewire-audio.git] / drivers / ide / pci / pdc202xx_old.c
blobde9a27400462a008a4ddceca29c13148d4f268b9
1 /*
2 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2006-2007 MontaVista Software, Inc.
4 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
5 *
6 * Portions Copyright (C) 1999 Promise Technology, Inc.
7 * Author: Frank Tiernan (frankt@promise.com)
8 * Released under terms of General Public License
9 */
10
11 #include <linux/types.h>
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/delay.h>
15 #include <linux/blkdev.h>
16 #include <linux/hdreg.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/ide.h>
20
21 #include <asm/io.h>
22
23 #define DRV_NAME "pdc202xx_old"
24
25 #define PDC202XX_DEBUG_DRIVE_INFO 0
26
27 static const char *pdc_quirk_drives[] = {
28 "QUANTUM FIREBALLlct08 08",
29 "QUANTUM FIREBALLP KA6.4",
30 "QUANTUM FIREBALLP KA9.1",
31 "QUANTUM FIREBALLP LM20.4",
32 "QUANTUM FIREBALLP KX13.6",
33 "QUANTUM FIREBALLP KX20.5",
34 "QUANTUM FIREBALLP KX27.3",
35 "QUANTUM FIREBALLP LM20.5",
36 NULL
37 };
38
39 static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
40
41 static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
42 {
43 ide_hwif_t *hwif = HWIF(drive);
44 struct pci_dev *dev = to_pci_dev(hwif->dev);
45 u8 drive_pci = 0x60 + (drive->dn << 2);
46
47 u8 AP = 0, BP = 0, CP = 0;
48 u8 TA = 0, TB = 0, TC = 0;
49
50 #if PDC202XX_DEBUG_DRIVE_INFO
51 u32 drive_conf = 0;
52 pci_read_config_dword(dev, drive_pci, &drive_conf);
53 #endif
54
55 /*
56 * TODO: do this once per channel
57 */
58 if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
59 pdc_old_disable_66MHz_clock(hwif);
60
61 pci_read_config_byte(dev, drive_pci, &AP);
62 pci_read_config_byte(dev, drive_pci + 1, &BP);
63 pci_read_config_byte(dev, drive_pci + 2, &CP);
64
65 switch(speed) {
66 case XFER_UDMA_5:
67 case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
68 case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
69 case XFER_UDMA_3:
70 case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
71 case XFER_UDMA_0:
72 case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
73 case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
74 case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break;
75 case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
76 case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
77 case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
78 case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
79 case XFER_PIO_0:
80 default: TA = 0x09; TB = 0x13; break;
81 }
82
83 if (speed < XFER_SW_DMA_0) {
84 /*
85 * preserve SYNC_INT / ERDDY_EN bits while clearing
86 * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
87 */
88 AP &= ~0x3f;
89 if (drive->id->capability & 4)
90 AP |= 0x20; /* set IORDY_EN bit */
91 if (drive->media == ide_disk)
92 AP |= 0x10; /* set Prefetch_EN bit */
93 /* clear PB[4:0] bits of register B */
94 BP &= ~0x1f;
95 pci_write_config_byte(dev, drive_pci, AP | TA);
96 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
97 } else {
98 /* clear MB[2:0] bits of register B */
99 BP &= ~0xe0;
100 /* clear MC[3:0] bits of register C */
101 CP &= ~0x0f;
102 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
103 pci_write_config_byte(dev, drive_pci + 2, CP | TC);
104 }
105
106 #if PDC202XX_DEBUG_DRIVE_INFO
107 printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
108 drive->name, ide_xfer_verbose(speed),
109 drive->dn, drive_conf);
110 pci_read_config_dword(dev, drive_pci, &drive_conf);
111 printk("0x%08x\n", drive_conf);
112 #endif
113 }
114
115 static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
116 {
117 pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
118 }
119
120 static u8 pdc2026x_cable_detect(ide_hwif_t *hwif)
121 {
122 struct pci_dev *dev = to_pci_dev(hwif->dev);
123 u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10);
124
125 pci_read_config_word(dev, 0x50, &CIS);
126
127 return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
128 }
129
130 /*
131 * Set the control register to use the 66MHz system
132 * clock for UDMA 3/4/5 mode operation when necessary.
133 *
134 * FIXME: this register is shared by both channels, some locking is needed
135 *
136 * It may also be possible to leave the 66MHz clock on
137 * and readjust the timing parameters.
138 */
139 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
140 {
141 unsigned long clock_reg = hwif->extra_base + 0x01;
142 u8 clock = inb(clock_reg);
143
144 outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
145 }
146
147 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
148 {
149 unsigned long clock_reg = hwif->extra_base + 0x01;
150 u8 clock = inb(clock_reg);
151
152 outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
153 }
154
155 static void pdc202xx_quirkproc(ide_drive_t *drive)
156 {
157 const char **list, *model = drive->id->model;
158
159 for (list = pdc_quirk_drives; *list != NULL; list++)
160 if (strstr(model, *list) != NULL) {
161 drive->quirk_list = 2;
162 return;
163 }
164
165 drive->quirk_list = 0;
166 }
167
168 static void pdc202xx_dma_start(ide_drive_t *drive)
169 {
170 if (drive->current_speed > XFER_UDMA_2)
171 pdc_old_enable_66MHz_clock(drive->hwif);
172 if (drive->media != ide_disk || drive->addressing == 1) {
173 struct request *rq = HWGROUP(drive)->rq;
174 ide_hwif_t *hwif = HWIF(drive);
175 unsigned long high_16 = hwif->extra_base - 16;
176 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
177 u32 word_count = 0;
178 u8 clock = inb(high_16 + 0x11);
179
180 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
181 word_count = (rq->nr_sectors << 8);
182 word_count = (rq_data_dir(rq) == READ) ?
183 word_count | 0x05000000 :
184 word_count | 0x06000000;
185 outl(word_count, atapi_reg);
186 }
187 ide_dma_start(drive);
188 }
189
190 static int pdc202xx_dma_end(ide_drive_t *drive)
191 {
192 if (drive->media != ide_disk || drive->addressing == 1) {
193 ide_hwif_t *hwif = HWIF(drive);
194 unsigned long high_16 = hwif->extra_base - 16;
195 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
196 u8 clock = 0;
197
198 outl(0, atapi_reg); /* zero out extra */
199 clock = inb(high_16 + 0x11);
200 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
201 }
202 if (drive->current_speed > XFER_UDMA_2)
203 pdc_old_disable_66MHz_clock(drive->hwif);
204 return __ide_dma_end(drive);
205 }
206
207 static int pdc202xx_dma_test_irq(ide_drive_t *drive)
208 {
209 ide_hwif_t *hwif = HWIF(drive);
210 unsigned long high_16 = hwif->extra_base - 16;
211 u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
212 u8 sc1d = inb(high_16 + 0x001d);
213
214 if (hwif->channel) {
215 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
216 if ((sc1d & 0x50) == 0x50)
217 goto somebody_else;
218 else if ((sc1d & 0x40) == 0x40)
219 return (dma_stat & 4) == 4;
220 } else {
221 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
222 if ((sc1d & 0x05) == 0x05)
223 goto somebody_else;
224 else if ((sc1d & 0x04) == 0x04)
225 return (dma_stat & 4) == 4;
226 }
227 somebody_else:
228 return (dma_stat & 4) == 4; /* return 1 if INTR asserted */
229 }
230
231 static void pdc202xx_reset_host (ide_hwif_t *hwif)
232 {
233 unsigned long high_16 = hwif->extra_base - 16;
234 u8 udma_speed_flag = inb(high_16 | 0x001f);
235
236 outb(udma_speed_flag | 0x10, high_16 | 0x001f);
237 mdelay(100);
238 outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
239 mdelay(2000); /* 2 seconds ?! */
240
241 printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
242 hwif->channel ? "Secondary" : "Primary");
243 }
244
245 static void pdc202xx_reset (ide_drive_t *drive)
246 {
247 ide_hwif_t *hwif = HWIF(drive);
248 ide_hwif_t *mate = hwif->mate;
249
250 pdc202xx_reset_host(hwif);
251 pdc202xx_reset_host(mate);
252
253 ide_set_max_pio(drive);
254 }
255
256 static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
257 {
258 pdc202xx_reset(drive);
259 ide_dma_lost_irq(drive);
260 }
261
262 static void pdc202xx_dma_timeout(ide_drive_t *drive)
263 {
264 pdc202xx_reset(drive);
265 ide_dma_timeout(drive);
266 }
267
268 static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev)
269 {
270 unsigned long dmabase = pci_resource_start(dev, 4);
271 u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
272
273 if (dmabase == 0)
274 goto out;
275
276 udma_speed_flag = inb(dmabase | 0x1f);
277 primary_mode = inb(dmabase | 0x1a);
278 secondary_mode = inb(dmabase | 0x1b);
279 printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
280 "Primary %s Mode " \
281 "Secondary %s Mode.\n", pci_name(dev),
282 (udma_speed_flag & 1) ? "EN" : "DIS",
283 (primary_mode & 1) ? "MASTER" : "PCI",
284 (secondary_mode & 1) ? "MASTER" : "PCI" );
285
286 if (!(udma_speed_flag & 1)) {
287 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
288 pci_name(dev), udma_speed_flag,
289 (udma_speed_flag|1));
290 outb(udma_speed_flag | 1, dmabase | 0x1f);
291 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
292 }
293 out:
294 return dev->irq;
295 }
296
297 static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
298 const char *name)
299 {
300 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
301 u8 irq = 0, irq2 = 0;
302 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
303 /* 0xbc */
304 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
305 if (irq != irq2) {
306 pci_write_config_byte(dev,
307 (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */
308 printk(KERN_INFO "%s %s: PCI config space interrupt "
309 "mirror fixed\n", name, pci_name(dev));
310 }
311 }
312 }
313
314 #define IDE_HFLAGS_PDC202XX \
315 (IDE_HFLAG_ERROR_STOPS_FIFO | \
316 IDE_HFLAG_OFF_BOARD)
317
318 static const struct ide_port_ops pdc20246_port_ops = {
319 .set_pio_mode = pdc202xx_set_pio_mode,
320 .set_dma_mode = pdc202xx_set_mode,
321 .quirkproc = pdc202xx_quirkproc,
322 };
323
324 static const struct ide_port_ops pdc2026x_port_ops = {
325 .set_pio_mode = pdc202xx_set_pio_mode,
326 .set_dma_mode = pdc202xx_set_mode,
327 .quirkproc = pdc202xx_quirkproc,
328 .resetproc = pdc202xx_reset,
329 .cable_detect = pdc2026x_cable_detect,
330 };
331
332 static const struct ide_dma_ops pdc20246_dma_ops = {
333 .dma_host_set = ide_dma_host_set,
334 .dma_setup = ide_dma_setup,
335 .dma_exec_cmd = ide_dma_exec_cmd,
336 .dma_start = ide_dma_start,
337 .dma_end = __ide_dma_end,
338 .dma_test_irq = pdc202xx_dma_test_irq,
339 .dma_lost_irq = pdc202xx_dma_lost_irq,
340 .dma_timeout = pdc202xx_dma_timeout,
341 };
342
343 static const struct ide_dma_ops pdc2026x_dma_ops = {
344 .dma_host_set = ide_dma_host_set,
345 .dma_setup = ide_dma_setup,
346 .dma_exec_cmd = ide_dma_exec_cmd,
347 .dma_start = pdc202xx_dma_start,
348 .dma_end = pdc202xx_dma_end,
349 .dma_test_irq = pdc202xx_dma_test_irq,
350 .dma_lost_irq = pdc202xx_dma_lost_irq,
351 .dma_timeout = pdc202xx_dma_timeout,
352 };
353
354 #define DECLARE_PDC2026X_DEV(udma, extra_flags) \
355 { \
356 .name = DRV_NAME, \
357 .init_chipset = init_chipset_pdc202xx, \
358 .port_ops = &pdc2026x_port_ops, \
359 .dma_ops = &pdc2026x_dma_ops, \
360 .host_flags = IDE_HFLAGS_PDC202XX | extra_flags, \
361 .pio_mask = ATA_PIO4, \
362 .mwdma_mask = ATA_MWDMA2, \
363 .udma_mask = udma, \
364 }
365
366 static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
367 { /* 0: PDC20246 */
368 .name = DRV_NAME,
369 .init_chipset = init_chipset_pdc202xx,
370 .port_ops = &pdc20246_port_ops,
371 .dma_ops = &pdc20246_dma_ops,
372 .host_flags = IDE_HFLAGS_PDC202XX,
373 .pio_mask = ATA_PIO4,
374 .mwdma_mask = ATA_MWDMA2,
375 .udma_mask = ATA_UDMA2,
376 },
377
378 /* 1: PDC2026{2,3} */
379 DECLARE_PDC2026X_DEV(ATA_UDMA4, 0),
380 /* 2: PDC2026{5,7} */
381 DECLARE_PDC2026X_DEV(ATA_UDMA5, IDE_HFLAG_RQSIZE_256),
382 };
383
384 /**
385 * pdc202xx_init_one - called when a PDC202xx is found
386 * @dev: the pdc202xx device
387 * @id: the matching pci id
388 *
389 * Called when the PCI registration layer (or the IDE initialization)
390 * finds a device matching our IDE device tables.
391 */
392
393 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
394 {
395 const struct ide_port_info *d;
396 u8 idx = id->driver_data;
397
398 d = &pdc202xx_chipsets[idx];
399
400 if (idx < 2)
401 pdc202ata4_fixup_irq(dev, d->name);
402
403 if (dev->vendor == PCI_DEVICE_ID_PROMISE_20265) {
404 struct pci_dev *bridge = dev->bus->self;
405
406 if (bridge &&
407 bridge->vendor == PCI_VENDOR_ID_INTEL &&
408 (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
409 bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
410 printk(KERN_INFO DRV_NAME " %s: skipping Promise "
411 "PDC20265 attached to I2O RAID controller\n",
412 pci_name(dev));
413 return -ENODEV;
414 }
415 }
416
417 return ide_pci_init_one(dev, d, NULL);
418 }
419
420 static const struct pci_device_id pdc202xx_pci_tbl[] = {
421 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
422 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
423 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
424 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
425 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
426 { 0, },
427 };
428 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
429
430 static struct pci_driver driver = {
431 .name = "Promise_Old_IDE",
432 .id_table = pdc202xx_pci_tbl,
433 .probe = pdc202xx_init_one,
434 .remove = ide_pci_remove,
435 };
436
437 static int __init pdc202xx_ide_init(void)
438 {
439 return ide_pci_register_driver(&driver);
440 }
441
442 static void __exit pdc202xx_ide_exit(void)
443 {
444 pci_unregister_driver(&driver);
445 }
446
447 module_init(pdc202xx_ide_init);
448 module_exit(pdc202xx_ide_exit);
449
450 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
451 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
452 MODULE_LICENSE("GPL");
AMDTP streaming driver for the Linux FireWire stack (Juju)