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[ARM] pxa: fix overlay being un-necessarily initialized on pxa25x
[firewire-audio.git] / drivers / video / pxafb.c
blob40a5d9d66755a9c895e9e9dd2a63e81404b0647d
1 /*
2 * linux/drivers/video/pxafb.c
3 *
4 * Copyright (C) 1999 Eric A. Thomas.
5 * Copyright (C) 2004 Jean-Frederic Clere.
6 * Copyright (C) 2004 Ian Campbell.
7 * Copyright (C) 2004 Jeff Lackey.
8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
9 * which in turn is
10 * Based on acornfb.c Copyright (C) Russell King.
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
14 * more details.
15 *
16 * Intel PXA250/210 LCD Controller Frame Buffer Driver
17 *
18 * Please direct your questions and comments on this driver to the following
19 * email address:
20 *
21 * linux-arm-kernel@lists.arm.linux.org.uk
22 *
23 * Add support for overlay1 and overlay2 based on pxafb_overlay.c:
24 *
25 * Copyright (C) 2004, Intel Corporation
26 *
27 * 2003/08/27: <yu.tang@intel.com>
28 * 2004/03/10: <stanley.cai@intel.com>
29 * 2004/10/28: <yan.yin@intel.com>
30 *
31 * Copyright (C) 2006-2008 Marvell International Ltd.
32 * All Rights Reserved
33 */
34
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/kernel.h>
38 #include <linux/sched.h>
39 #include <linux/errno.h>
40 #include <linux/string.h>
41 #include <linux/interrupt.h>
42 #include <linux/slab.h>
43 #include <linux/mm.h>
44 #include <linux/fb.h>
45 #include <linux/delay.h>
46 #include <linux/init.h>
47 #include <linux/ioport.h>
48 #include <linux/cpufreq.h>
49 #include <linux/platform_device.h>
50 #include <linux/dma-mapping.h>
51 #include <linux/clk.h>
52 #include <linux/err.h>
53 #include <linux/completion.h>
54 #include <linux/mutex.h>
55 #include <linux/kthread.h>
56 #include <linux/freezer.h>
57
58 #include <mach/hardware.h>
59 #include <asm/io.h>
60 #include <asm/irq.h>
61 #include <asm/div64.h>
62 #include <mach/pxa-regs.h>
63 #include <mach/bitfield.h>
64 #include <mach/pxafb.h>
65
66 /*
67 * Complain if VAR is out of range.
68 */
69 #define DEBUG_VAR 1
70
71 #include "pxafb.h"
72
73 /* Bits which should not be set in machine configuration structures */
74 #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
75 LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
76 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
77
78 #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
79 LCCR3_PCD | LCCR3_BPP(0xf))
80
81 static int pxafb_activate_var(struct fb_var_screeninfo *var,
82 struct pxafb_info *);
83 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
84 static void setup_base_frame(struct pxafb_info *fbi, int branch);
85 static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
86 unsigned long offset, size_t size);
87
88 static unsigned long video_mem_size = 0;
89
90 static inline unsigned long
91 lcd_readl(struct pxafb_info *fbi, unsigned int off)
92 {
93 return __raw_readl(fbi->mmio_base + off);
94 }
95
96 static inline void
97 lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
98 {
99 __raw_writel(val, fbi->mmio_base + off);
100 }
101
102 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
103 {
104 unsigned long flags;
105
106 local_irq_save(flags);
107 /*
108 * We need to handle two requests being made at the same time.
109 * There are two important cases:
110 * 1. When we are changing VT (C_REENABLE) while unblanking
111 * (C_ENABLE) We must perform the unblanking, which will
112 * do our REENABLE for us.
113 * 2. When we are blanking, but immediately unblank before
114 * we have blanked. We do the "REENABLE" thing here as
115 * well, just to be sure.
116 */
117 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
118 state = (u_int) -1;
119 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
120 state = C_REENABLE;
121
122 if (state != (u_int)-1) {
123 fbi->task_state = state;
124 schedule_work(&fbi->task);
125 }
126 local_irq_restore(flags);
127 }
128
129 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
130 {
131 chan &= 0xffff;
132 chan >>= 16 - bf->length;
133 return chan << bf->offset;
134 }
135
136 static int
137 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
138 u_int trans, struct fb_info *info)
139 {
140 struct pxafb_info *fbi = (struct pxafb_info *)info;
141 u_int val;
142
143 if (regno >= fbi->palette_size)
144 return 1;
145
146 if (fbi->fb.var.grayscale) {
147 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
148 return 0;
149 }
150
151 switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
152 case LCCR4_PAL_FOR_0:
153 val = ((red >> 0) & 0xf800);
154 val |= ((green >> 5) & 0x07e0);
155 val |= ((blue >> 11) & 0x001f);
156 fbi->palette_cpu[regno] = val;
157 break;
158 case LCCR4_PAL_FOR_1:
159 val = ((red << 8) & 0x00f80000);
160 val |= ((green >> 0) & 0x0000fc00);
161 val |= ((blue >> 8) & 0x000000f8);
162 ((u32 *)(fbi->palette_cpu))[regno] = val;
163 break;
164 case LCCR4_PAL_FOR_2:
165 val = ((red << 8) & 0x00fc0000);
166 val |= ((green >> 0) & 0x0000fc00);
167 val |= ((blue >> 8) & 0x000000fc);
168 ((u32 *)(fbi->palette_cpu))[regno] = val;
169 break;
170 case LCCR4_PAL_FOR_3:
171 val = ((red << 8) & 0x00ff0000);
172 val |= ((green >> 0) & 0x0000ff00);
173 val |= ((blue >> 8) & 0x000000ff);
174 ((u32 *)(fbi->palette_cpu))[regno] = val;
175 break;
176 }
177
178 return 0;
179 }
180
181 static int
182 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
183 u_int trans, struct fb_info *info)
184 {
185 struct pxafb_info *fbi = (struct pxafb_info *)info;
186 unsigned int val;
187 int ret = 1;
188
189 /*
190 * If inverse mode was selected, invert all the colours
191 * rather than the register number. The register number
192 * is what you poke into the framebuffer to produce the
193 * colour you requested.
194 */
195 if (fbi->cmap_inverse) {
196 red = 0xffff - red;
197 green = 0xffff - green;
198 blue = 0xffff - blue;
199 }
200
201 /*
202 * If greyscale is true, then we convert the RGB value
203 * to greyscale no matter what visual we are using.
204 */
205 if (fbi->fb.var.grayscale)
206 red = green = blue = (19595 * red + 38470 * green +
207 7471 * blue) >> 16;
208
209 switch (fbi->fb.fix.visual) {
210 case FB_VISUAL_TRUECOLOR:
211 /*
212 * 16-bit True Colour. We encode the RGB value
213 * according to the RGB bitfield information.
214 */
215 if (regno < 16) {
216 u32 *pal = fbi->fb.pseudo_palette;
217
218 val = chan_to_field(red, &fbi->fb.var.red);
219 val |= chan_to_field(green, &fbi->fb.var.green);
220 val |= chan_to_field(blue, &fbi->fb.var.blue);
221
222 pal[regno] = val;
223 ret = 0;
224 }
225 break;
226
227 case FB_VISUAL_STATIC_PSEUDOCOLOR:
228 case FB_VISUAL_PSEUDOCOLOR:
229 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
230 break;
231 }
232
233 return ret;
234 }
235
236 /* calculate pixel depth, transparency bit included, >=16bpp formats _only_ */
237 static inline int var_to_depth(struct fb_var_screeninfo *var)
238 {
239 return var->red.length + var->green.length +
240 var->blue.length + var->transp.length;
241 }
242
243 /* calculate 4-bit BPP value for LCCR3 and OVLxC1 */
244 static int pxafb_var_to_bpp(struct fb_var_screeninfo *var)
245 {
246 int bpp = -EINVAL;
247
248 switch (var->bits_per_pixel) {
249 case 1: bpp = 0; break;
250 case 2: bpp = 1; break;
251 case 4: bpp = 2; break;
252 case 8: bpp = 3; break;
253 case 16: bpp = 4; break;
254 case 24:
255 switch (var_to_depth(var)) {
256 case 18: bpp = 6; break; /* 18-bits/pixel packed */
257 case 19: bpp = 8; break; /* 19-bits/pixel packed */
258 case 24: bpp = 9; break;
259 }
260 break;
261 case 32:
262 switch (var_to_depth(var)) {
263 case 18: bpp = 5; break; /* 18-bits/pixel unpacked */
264 case 19: bpp = 7; break; /* 19-bits/pixel unpacked */
265 case 25: bpp = 10; break;
266 }
267 break;
268 }
269 return bpp;
270 }
271
272 /*
273 * pxafb_var_to_lccr3():
274 * Convert a bits per pixel value to the correct bit pattern for LCCR3
275 *
276 * NOTE: for PXA27x with overlays support, the LCCR3_PDFOR_x bits have an
277 * implication of the acutal use of transparency bit, which we handle it
278 * here separatedly. See PXA27x Developer's Manual, Section <<7.4.6 Pixel
279 * Formats>> for the valid combination of PDFOR, PAL_FOR for various BPP.
280 *
281 * Transparency for palette pixel formats is not supported at the moment.
282 */
283 static uint32_t pxafb_var_to_lccr3(struct fb_var_screeninfo *var)
284 {
285 int bpp = pxafb_var_to_bpp(var);
286 uint32_t lccr3;
287
288 if (bpp < 0)
289 return 0;
290
291 lccr3 = LCCR3_BPP(bpp);
292
293 switch (var_to_depth(var)) {
294 case 16: lccr3 |= var->transp.length ? LCCR3_PDFOR_3 : 0; break;
295 case 18: lccr3 |= LCCR3_PDFOR_3; break;
296 case 24: lccr3 |= var->transp.length ? LCCR3_PDFOR_2 : LCCR3_PDFOR_3;
297 break;
298 case 19:
299 case 25: lccr3 |= LCCR3_PDFOR_0; break;
300 }
301 return lccr3;
302 }
303
304 #define SET_PIXFMT(v, r, g, b, t) \
305 ({ \
306 (v)->transp.offset = (t) ? (r) + (g) + (b) : 0; \
307 (v)->transp.length = (t) ? (t) : 0; \
308 (v)->blue.length = (b); (v)->blue.offset = 0; \
309 (v)->green.length = (g); (v)->green.offset = (b); \
310 (v)->red.length = (r); (v)->red.offset = (b) + (g); \
311 })
312
313 /* set the RGBT bitfields of fb_var_screeninf according to
314 * var->bits_per_pixel and given depth
315 */
316 static void pxafb_set_pixfmt(struct fb_var_screeninfo *var, int depth)
317 {
318 if (depth == 0)
319 depth = var->bits_per_pixel;
320
321 if (var->bits_per_pixel < 16) {
322 /* indexed pixel formats */
323 var->red.offset = 0; var->red.length = 8;
324 var->green.offset = 0; var->green.length = 8;
325 var->blue.offset = 0; var->blue.length = 8;
326 var->transp.offset = 0; var->transp.length = 8;
327 }
328
329 switch (depth) {
330 case 16: var->transp.length ?
331 SET_PIXFMT(var, 5, 5, 5, 1) : /* RGBT555 */
332 SET_PIXFMT(var, 5, 6, 5, 0); break; /* RGB565 */
333 case 18: SET_PIXFMT(var, 6, 6, 6, 0); break; /* RGB666 */
334 case 19: SET_PIXFMT(var, 6, 6, 6, 1); break; /* RGBT666 */
335 case 24: var->transp.length ?
336 SET_PIXFMT(var, 8, 8, 7, 1) : /* RGBT887 */
337 SET_PIXFMT(var, 8, 8, 8, 0); break; /* RGB888 */
338 case 25: SET_PIXFMT(var, 8, 8, 8, 1); break; /* RGBT888 */
339 }
340 }
341
342 #ifdef CONFIG_CPU_FREQ
343 /*
344 * pxafb_display_dma_period()
345 * Calculate the minimum period (in picoseconds) between two DMA
346 * requests for the LCD controller. If we hit this, it means we're
347 * doing nothing but LCD DMA.
348 */
349 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
350 {
351 /*
352 * Period = pixclock * bits_per_byte * bytes_per_transfer
353 * / memory_bits_per_pixel;
354 */
355 return var->pixclock * 8 * 16 / var->bits_per_pixel;
356 }
357 #endif
358
359 /*
360 * Select the smallest mode that allows the desired resolution to be
361 * displayed. If desired parameters can be rounded up.
362 */
363 static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
364 struct fb_var_screeninfo *var)
365 {
366 struct pxafb_mode_info *mode = NULL;
367 struct pxafb_mode_info *modelist = mach->modes;
368 unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
369 unsigned int i;
370
371 for (i = 0; i < mach->num_modes; i++) {
372 if (modelist[i].xres >= var->xres &&
373 modelist[i].yres >= var->yres &&
374 modelist[i].xres < best_x &&
375 modelist[i].yres < best_y &&
376 modelist[i].bpp >= var->bits_per_pixel) {
377 best_x = modelist[i].xres;
378 best_y = modelist[i].yres;
379 mode = &modelist[i];
380 }
381 }
382
383 return mode;
384 }
385
386 static void pxafb_setmode(struct fb_var_screeninfo *var,
387 struct pxafb_mode_info *mode)
388 {
389 var->xres = mode->xres;
390 var->yres = mode->yres;
391 var->bits_per_pixel = mode->bpp;
392 var->pixclock = mode->pixclock;
393 var->hsync_len = mode->hsync_len;
394 var->left_margin = mode->left_margin;
395 var->right_margin = mode->right_margin;
396 var->vsync_len = mode->vsync_len;
397 var->upper_margin = mode->upper_margin;
398 var->lower_margin = mode->lower_margin;
399 var->sync = mode->sync;
400 var->grayscale = mode->cmap_greyscale;
401
402 /* set the initial RGBA bitfields */
403 pxafb_set_pixfmt(var, mode->depth);
404 }
405
406 static int pxafb_adjust_timing(struct pxafb_info *fbi,
407 struct fb_var_screeninfo *var)
408 {
409 int line_length;
410
411 var->xres = max_t(int, var->xres, MIN_XRES);
412 var->yres = max_t(int, var->yres, MIN_YRES);
413
414 if (!(fbi->lccr0 & LCCR0_LCDT)) {
415 clamp_val(var->hsync_len, 1, 64);
416 clamp_val(var->vsync_len, 1, 64);
417 clamp_val(var->left_margin, 1, 255);
418 clamp_val(var->right_margin, 1, 255);
419 clamp_val(var->upper_margin, 1, 255);
420 clamp_val(var->lower_margin, 1, 255);
421 }
422
423 /* make sure each line is aligned on word boundary */
424 line_length = var->xres * var->bits_per_pixel / 8;
425 line_length = ALIGN(line_length, 4);
426 var->xres = line_length * 8 / var->bits_per_pixel;
427
428 /* we don't support xpan, force xres_virtual to be equal to xres */
429 var->xres_virtual = var->xres;
430
431 if (var->accel_flags & FB_ACCELF_TEXT)
432 var->yres_virtual = fbi->fb.fix.smem_len / line_length;
433 else
434 var->yres_virtual = max(var->yres_virtual, var->yres);
435
436 /* check for limits */
437 if (var->xres > MAX_XRES || var->yres > MAX_YRES)
438 return -EINVAL;
439
440 if (var->yres > var->yres_virtual)
441 return -EINVAL;
442
443 return 0;
444 }
445
446 /*
447 * pxafb_check_var():
448 * Get the video params out of 'var'. If a value doesn't fit, round it up,
449 * if it's too big, return -EINVAL.
450 *
451 * Round up in the following order: bits_per_pixel, xres,
452 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
453 * bitfields, horizontal timing, vertical timing.
454 */
455 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
456 {
457 struct pxafb_info *fbi = (struct pxafb_info *)info;
458 struct pxafb_mach_info *inf = fbi->dev->platform_data;
459 int err;
460
461 if (inf->fixed_modes) {
462 struct pxafb_mode_info *mode;
463
464 mode = pxafb_getmode(inf, var);
465 if (!mode)
466 return -EINVAL;
467 pxafb_setmode(var, mode);
468 }
469
470 /* do a test conversion to BPP fields to check the color formats */
471 err = pxafb_var_to_bpp(var);
472 if (err < 0)
473 return err;
474
475 pxafb_set_pixfmt(var, var_to_depth(var));
476
477 err = pxafb_adjust_timing(fbi, var);
478 if (err)
479 return err;
480
481 #ifdef CONFIG_CPU_FREQ
482 pr_debug("pxafb: dma period = %d ps\n",
483 pxafb_display_dma_period(var));
484 #endif
485
486 return 0;
487 }
488
489 /*
490 * pxafb_set_par():
491 * Set the user defined part of the display for the specified console
492 */
493 static int pxafb_set_par(struct fb_info *info)
494 {
495 struct pxafb_info *fbi = (struct pxafb_info *)info;
496 struct fb_var_screeninfo *var = &info->var;
497
498 if (var->bits_per_pixel >= 16)
499 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
500 else if (!fbi->cmap_static)
501 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
502 else {
503 /*
504 * Some people have weird ideas about wanting static
505 * pseudocolor maps. I suspect their user space
506 * applications are broken.
507 */
508 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
509 }
510
511 fbi->fb.fix.line_length = var->xres_virtual *
512 var->bits_per_pixel / 8;
513 if (var->bits_per_pixel >= 16)
514 fbi->palette_size = 0;
515 else
516 fbi->palette_size = var->bits_per_pixel == 1 ?
517 4 : 1 << var->bits_per_pixel;
518
519 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
520
521 if (fbi->fb.var.bits_per_pixel >= 16)
522 fb_dealloc_cmap(&fbi->fb.cmap);
523 else
524 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
525
526 pxafb_activate_var(var, fbi);
527
528 return 0;
529 }
530
531 static int pxafb_pan_display(struct fb_var_screeninfo *var,
532 struct fb_info *info)
533 {
534 struct pxafb_info *fbi = (struct pxafb_info *)info;
535 int dma = DMA_MAX + DMA_BASE;
536
537 if (fbi->state != C_ENABLE)
538 return 0;
539
540 setup_base_frame(fbi, 1);
541
542 if (fbi->lccr0 & LCCR0_SDS)
543 lcd_writel(fbi, FBR1, fbi->fdadr[dma + 1] | 0x1);
544
545 lcd_writel(fbi, FBR0, fbi->fdadr[dma] | 0x1);
546 return 0;
547 }
548
549 /*
550 * pxafb_blank():
551 * Blank the display by setting all palette values to zero. Note, the
552 * 16 bpp mode does not really use the palette, so this will not
553 * blank the display in all modes.
554 */
555 static int pxafb_blank(int blank, struct fb_info *info)
556 {
557 struct pxafb_info *fbi = (struct pxafb_info *)info;
558 int i;
559
560 switch (blank) {
561 case FB_BLANK_POWERDOWN:
562 case FB_BLANK_VSYNC_SUSPEND:
563 case FB_BLANK_HSYNC_SUSPEND:
564 case FB_BLANK_NORMAL:
565 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
566 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
567 for (i = 0; i < fbi->palette_size; i++)
568 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
569
570 pxafb_schedule_work(fbi, C_DISABLE);
571 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
572 break;
573
574 case FB_BLANK_UNBLANK:
575 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
576 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
577 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
578 fb_set_cmap(&fbi->fb.cmap, info);
579 pxafb_schedule_work(fbi, C_ENABLE);
580 }
581 return 0;
582 }
583
584 static struct fb_ops pxafb_ops = {
585 .owner = THIS_MODULE,
586 .fb_check_var = pxafb_check_var,
587 .fb_set_par = pxafb_set_par,
588 .fb_pan_display = pxafb_pan_display,
589 .fb_setcolreg = pxafb_setcolreg,
590 .fb_fillrect = cfb_fillrect,
591 .fb_copyarea = cfb_copyarea,
592 .fb_imageblit = cfb_imageblit,
593 .fb_blank = pxafb_blank,
594 };
595
596 #ifdef CONFIG_FB_PXA_OVERLAY
597 static void overlay1fb_setup(struct pxafb_layer *ofb)
598 {
599 int size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
600 unsigned long start = ofb->video_mem_phys;
601 setup_frame_dma(ofb->fbi, DMA_OV1, PAL_NONE, start, size);
602 }
603
604 /* Depending on the enable status of overlay1/2, the DMA should be
605 * updated from FDADRx (when disabled) or FBRx (when enabled).
606 */
607 static void overlay1fb_enable(struct pxafb_layer *ofb)
608 {
609 int enabled = lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN;
610 uint32_t fdadr1 = ofb->fbi->fdadr[DMA_OV1] | (enabled ? 0x1 : 0);
611
612 lcd_writel(ofb->fbi, enabled ? FBR1 : FDADR1, fdadr1);
613 lcd_writel(ofb->fbi, OVL1C2, ofb->control[1]);
614 lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] | OVLxC1_OEN);
615 }
616
617 static void overlay1fb_disable(struct pxafb_layer *ofb)
618 {
619 uint32_t lccr5 = lcd_readl(ofb->fbi, LCCR5);
620
621 lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] & ~OVLxC1_OEN);
622
623 lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(1));
624 lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(1));
625 lcd_writel(ofb->fbi, FBR1, ofb->fbi->fdadr[DMA_OV1] | 0x3);
626
627 if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
628 pr_warning("%s: timeout disabling overlay1\n", __func__);
629
630 lcd_writel(ofb->fbi, LCCR5, lccr5);
631 }
632
633 static void overlay2fb_setup(struct pxafb_layer *ofb)
634 {
635 int size, div = 1, pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
636 unsigned long start[3] = { ofb->video_mem_phys, 0, 0 };
637
638 if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED) {
639 size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
640 setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
641 } else {
642 size = ofb->fb.var.xres_virtual * ofb->fb.var.yres_virtual;
643 switch (pfor) {
644 case OVERLAY_FORMAT_YUV444_PLANAR: div = 1; break;
645 case OVERLAY_FORMAT_YUV422_PLANAR: div = 2; break;
646 case OVERLAY_FORMAT_YUV420_PLANAR: div = 4; break;
647 }
648 start[1] = start[0] + size;
649 start[2] = start[1] + size / div;
650 setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
651 setup_frame_dma(ofb->fbi, DMA_OV2_Cb, -1, start[1], size / div);
652 setup_frame_dma(ofb->fbi, DMA_OV2_Cr, -1, start[2], size / div);
653 }
654 }
655
656 static void overlay2fb_enable(struct pxafb_layer *ofb)
657 {
658 int pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
659 int enabled = lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN;
660 uint32_t fdadr2 = ofb->fbi->fdadr[DMA_OV2_Y] | (enabled ? 0x1 : 0);
661 uint32_t fdadr3 = ofb->fbi->fdadr[DMA_OV2_Cb] | (enabled ? 0x1 : 0);
662 uint32_t fdadr4 = ofb->fbi->fdadr[DMA_OV2_Cr] | (enabled ? 0x1 : 0);
663
664 if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED)
665 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
666 else {
667 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
668 lcd_writel(ofb->fbi, enabled ? FBR3 : FDADR3, fdadr3);
669 lcd_writel(ofb->fbi, enabled ? FBR4 : FDADR4, fdadr4);
670 }
671 lcd_writel(ofb->fbi, OVL2C2, ofb->control[1]);
672 lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] | OVLxC1_OEN);
673 }
674
675 static void overlay2fb_disable(struct pxafb_layer *ofb)
676 {
677 uint32_t lccr5 = lcd_readl(ofb->fbi, LCCR5);
678
679 lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] & ~OVLxC1_OEN);
680
681 lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(2));
682 lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(2));
683 lcd_writel(ofb->fbi, FBR2, ofb->fbi->fdadr[DMA_OV2_Y] | 0x3);
684 lcd_writel(ofb->fbi, FBR3, ofb->fbi->fdadr[DMA_OV2_Cb] | 0x3);
685 lcd_writel(ofb->fbi, FBR4, ofb->fbi->fdadr[DMA_OV2_Cr] | 0x3);
686
687 if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
688 pr_warning("%s: timeout disabling overlay2\n", __func__);
689 }
690
691 static struct pxafb_layer_ops ofb_ops[] = {
692 [0] = {
693 .enable = overlay1fb_enable,
694 .disable = overlay1fb_disable,
695 .setup = overlay1fb_setup,
696 },
697 [1] = {
698 .enable = overlay2fb_enable,
699 .disable = overlay2fb_disable,
700 .setup = overlay2fb_setup,
701 },
702 };
703
704 static int overlayfb_open(struct fb_info *info, int user)
705 {
706 struct pxafb_layer *ofb = (struct pxafb_layer *)info;
707
708 /* no support for framebuffer console on overlay */
709 if (user == 0)
710 return -ENODEV;
711
712 /* allow only one user at a time */
713 if (atomic_inc_and_test(&ofb->usage))
714 return -EBUSY;
715
716 /* unblank the base framebuffer */
717 fb_blank(&ofb->fbi->fb, FB_BLANK_UNBLANK);
718 return 0;
719 }
720
721 static int overlayfb_release(struct fb_info *info, int user)
722 {
723 struct pxafb_layer *ofb = (struct pxafb_layer*) info;
724
725 atomic_dec(&ofb->usage);
726 ofb->ops->disable(ofb);
727
728 free_pages_exact(ofb->video_mem, ofb->video_mem_size);
729 ofb->video_mem = NULL;
730 ofb->video_mem_size = 0;
731 return 0;
732 }
733
734 static int overlayfb_check_var(struct fb_var_screeninfo *var,
735 struct fb_info *info)
736 {
737 struct pxafb_layer *ofb = (struct pxafb_layer *)info;
738 struct fb_var_screeninfo *base_var = &ofb->fbi->fb.var;
739 int xpos, ypos, pfor, bpp;
740
741 xpos = NONSTD_TO_XPOS(var->nonstd);
742 ypos = NONSTD_TO_XPOS(var->nonstd);
743 pfor = NONSTD_TO_PFOR(var->nonstd);
744
745 bpp = pxafb_var_to_bpp(var);
746 if (bpp < 0)
747 return -EINVAL;
748
749 /* no support for YUV format on overlay1 */
750 if (ofb->id == OVERLAY1 && pfor != 0)
751 return -EINVAL;
752
753 /* for YUV packed formats, bpp = 'minimum bpp of YUV components' */
754 switch (pfor) {
755 case OVERLAY_FORMAT_RGB:
756 bpp = pxafb_var_to_bpp(var);
757 if (bpp < 0)
758 return -EINVAL;
759
760 pxafb_set_pixfmt(var, var_to_depth(var));
761 break;
762 case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
763 case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 8; break;
764 case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 4; break;
765 case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 2; break;
766 default:
767 return -EINVAL;
768 }
769
770 /* each line must start at a 32-bit word boundary */
771 if ((xpos * bpp) % 32)
772 return -EINVAL;
773
774 /* xres must align on 32-bit word boundary */
775 var->xres = roundup(var->xres * bpp, 32) / bpp;
776
777 if ((xpos + var->xres > base_var->xres) ||
778 (ypos + var->yres > base_var->yres))
779 return -EINVAL;
780
781 var->xres_virtual = var->xres;
782 var->yres_virtual = max(var->yres, var->yres_virtual);
783 return 0;
784 }
785
786 static int overlayfb_map_video_memory(struct pxafb_layer *ofb)
787 {
788 struct fb_var_screeninfo *var = &ofb->fb.var;
789 int pfor = NONSTD_TO_PFOR(var->nonstd);
790 int size, bpp = 0;
791
792 switch (pfor) {
793 case OVERLAY_FORMAT_RGB: bpp = var->bits_per_pixel; break;
794 case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
795 case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 24; break;
796 case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 16; break;
797 case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 12; break;
798 }
799
800 ofb->fb.fix.line_length = var->xres_virtual * bpp / 8;
801
802 size = PAGE_ALIGN(ofb->fb.fix.line_length * var->yres_virtual);
803
804 /* don't re-allocate if the original video memory is enough */
805 if (ofb->video_mem) {
806 if (ofb->video_mem_size >= size)
807 return 0;
808
809 free_pages_exact(ofb->video_mem, ofb->video_mem_size);
810 }
811
812 ofb->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
813 if (ofb->video_mem == NULL)
814 return -ENOMEM;
815
816 ofb->video_mem_phys = virt_to_phys(ofb->video_mem);
817 ofb->video_mem_size = size;
818
819 ofb->fb.fix.smem_start = ofb->video_mem_phys;
820 ofb->fb.fix.smem_len = ofb->fb.fix.line_length * var->yres_virtual;
821 ofb->fb.screen_base = ofb->video_mem;
822 return 0;
823 }
824
825 static int overlayfb_set_par(struct fb_info *info)
826 {
827 struct pxafb_layer *ofb = (struct pxafb_layer *)info;
828 struct fb_var_screeninfo *var = &info->var;
829 int xpos, ypos, pfor, bpp, ret;
830
831 ret = overlayfb_map_video_memory(ofb);
832 if (ret)
833 return ret;
834
835 bpp = pxafb_var_to_bpp(var);
836 xpos = NONSTD_TO_XPOS(var->nonstd);
837 ypos = NONSTD_TO_XPOS(var->nonstd);
838 pfor = NONSTD_TO_PFOR(var->nonstd);
839
840 ofb->control[0] = OVLxC1_PPL(var->xres) | OVLxC1_LPO(var->yres) |
841 OVLxC1_BPP(bpp);
842 ofb->control[1] = OVLxC2_XPOS(xpos) | OVLxC2_YPOS(ypos);
843
844 if (ofb->id == OVERLAY2)
845 ofb->control[1] |= OVL2C2_PFOR(pfor);
846
847 ofb->ops->setup(ofb);
848 ofb->ops->enable(ofb);
849 return 0;
850 }
851
852 static struct fb_ops overlay_fb_ops = {
853 .owner = THIS_MODULE,
854 .fb_open = overlayfb_open,
855 .fb_release = overlayfb_release,
856 .fb_check_var = overlayfb_check_var,
857 .fb_set_par = overlayfb_set_par,
858 };
859
860 static void __devinit init_pxafb_overlay(struct pxafb_info *fbi,
861 struct pxafb_layer *ofb, int id)
862 {
863 sprintf(ofb->fb.fix.id, "overlay%d", id + 1);
864
865 ofb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
866 ofb->fb.fix.xpanstep = 0;
867 ofb->fb.fix.ypanstep = 1;
868
869 ofb->fb.var.activate = FB_ACTIVATE_NOW;
870 ofb->fb.var.height = -1;
871 ofb->fb.var.width = -1;
872 ofb->fb.var.vmode = FB_VMODE_NONINTERLACED;
873
874 ofb->fb.fbops = &overlay_fb_ops;
875 ofb->fb.flags = FBINFO_FLAG_DEFAULT;
876 ofb->fb.node = -1;
877 ofb->fb.pseudo_palette = NULL;
878
879 ofb->id = id;
880 ofb->ops = &ofb_ops[id];
881 atomic_set(&ofb->usage, 0);
882 ofb->fbi = fbi;
883 init_completion(&ofb->branch_done);
884 }
885
886 static inline int pxafb_overlay_supported(void)
887 {
888 if (cpu_is_pxa27x() || cpu_is_pxa3xx())
889 return 1;
890
891 return 0;
892 }
893
894 static int __devinit pxafb_overlay_init(struct pxafb_info *fbi)
895 {
896 int i, ret;
897
898 if (!pxafb_overlay_supported())
899 return 0;
900
901 for (i = 0; i < 2; i++) {
902 init_pxafb_overlay(fbi, &fbi->overlay[i], i);
903 ret = register_framebuffer(&fbi->overlay[i].fb);
904 if (ret) {
905 dev_err(fbi->dev, "failed to register overlay %d\n", i);
906 return ret;
907 }
908 }
909
910 /* mask all IU/BS/EOF/SOF interrupts */
911 lcd_writel(fbi, LCCR5, ~0);
912
913 /* place overlay(s) on top of base */
914 fbi->lccr0 |= LCCR0_OUC;
915 pr_info("PXA Overlay driver loaded successfully!\n");
916 return 0;
917 }
918
919 static void __devexit pxafb_overlay_exit(struct pxafb_info *fbi)
920 {
921 int i;
922
923 if (!pxafb_overlay_supported())
924 return;
925
926 for (i = 0; i < 2; i++)
927 unregister_framebuffer(&fbi->overlay[i].fb);
928 }
929 #else
930 static inline void pxafb_overlay_init(struct pxafb_info *fbi) {}
931 static inline void pxafb_overlay_exit(struct pxafb_info *fbi) {}
932 #endif /* CONFIG_FB_PXA_OVERLAY */
933
934 /*
935 * Calculate the PCD value from the clock rate (in picoseconds).
936 * We take account of the PPCR clock setting.
937 * From PXA Developer's Manual:
938 *
939 * PixelClock = LCLK
940 * -------------
941 * 2 ( PCD + 1 )
942 *
943 * PCD = LCLK
944 * ------------- - 1
945 * 2(PixelClock)
946 *
947 * Where:
948 * LCLK = LCD/Memory Clock
949 * PCD = LCCR3[7:0]
950 *
951 * PixelClock here is in Hz while the pixclock argument given is the
952 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
953 *
954 * The function get_lclk_frequency_10khz returns LCLK in units of
955 * 10khz. Calling the result of this function lclk gives us the
956 * following
957 *
958 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
959 * -------------------------------------- - 1
960 * 2
961 *
962 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
963 */
964 static inline unsigned int get_pcd(struct pxafb_info *fbi,
965 unsigned int pixclock)
966 {
967 unsigned long long pcd;
968
969 /* FIXME: Need to take into account Double Pixel Clock mode
970 * (DPC) bit? or perhaps set it based on the various clock
971 * speeds */
972 pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
973 pcd *= pixclock;
974 do_div(pcd, 100000000 * 2);
975 /* no need for this, since we should subtract 1 anyway. they cancel */
976 /* pcd += 1; */ /* make up for integer math truncations */
977 return (unsigned int)pcd;
978 }
979
980 /*
981 * Some touchscreens need hsync information from the video driver to
982 * function correctly. We export it here. Note that 'hsync_time' and
983 * the value returned from pxafb_get_hsync_time() is the *reciprocal*
984 * of the hsync period in seconds.
985 */
986 static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
987 {
988 unsigned long htime;
989
990 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
991 fbi->hsync_time = 0;
992 return;
993 }
994
995 htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
996
997 fbi->hsync_time = htime;
998 }
999
1000 unsigned long pxafb_get_hsync_time(struct device *dev)
1001 {
1002 struct pxafb_info *fbi = dev_get_drvdata(dev);
1003
1004 /* If display is blanked/suspended, hsync isn't active */
1005 if (!fbi || (fbi->state != C_ENABLE))
1006 return 0;
1007
1008 return fbi->hsync_time;
1009 }
1010 EXPORT_SYMBOL(pxafb_get_hsync_time);
1011
1012 static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
1013 unsigned long start, size_t size)
1014 {
1015 struct pxafb_dma_descriptor *dma_desc, *pal_desc;
1016 unsigned int dma_desc_off, pal_desc_off;
1017
1018 if (dma < 0 || dma >= DMA_MAX * 2)
1019 return -EINVAL;
1020
1021 dma_desc = &fbi->dma_buff->dma_desc[dma];
1022 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
1023
1024 dma_desc->fsadr = start;
1025 dma_desc->fidr = 0;
1026 dma_desc->ldcmd = size;
1027
1028 if (pal < 0 || pal >= PAL_MAX * 2) {
1029 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1030 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
1031 } else {
1032 pal_desc = &fbi->dma_buff->pal_desc[pal];
1033 pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]);
1034
1035 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
1036 pal_desc->fidr = 0;
1037
1038 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
1039 pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
1040 else
1041 pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
1042
1043 pal_desc->ldcmd |= LDCMD_PAL;
1044
1045 /* flip back and forth between palette and frame buffer */
1046 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1047 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
1048 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
1049 }
1050
1051 return 0;
1052 }
1053
1054 static void setup_base_frame(struct pxafb_info *fbi, int branch)
1055 {
1056 struct fb_var_screeninfo *var = &fbi->fb.var;
1057 struct fb_fix_screeninfo *fix = &fbi->fb.fix;
1058 int nbytes, dma, pal, bpp = var->bits_per_pixel;
1059 unsigned long offset;
1060
1061 dma = DMA_BASE + (branch ? DMA_MAX : 0);
1062 pal = (bpp >= 16) ? PAL_NONE : PAL_BASE + (branch ? PAL_MAX : 0);
1063
1064 nbytes = fix->line_length * var->yres;
1065 offset = fix->line_length * var->yoffset + fbi->video_mem_phys;
1066
1067 if (fbi->lccr0 & LCCR0_SDS) {
1068 nbytes = nbytes / 2;
1069 setup_frame_dma(fbi, dma + 1, PAL_NONE, offset + nbytes, nbytes);
1070 }
1071
1072 setup_frame_dma(fbi, dma, pal, offset, nbytes);
1073 }
1074
1075 #ifdef CONFIG_FB_PXA_SMARTPANEL
1076 static int setup_smart_dma(struct pxafb_info *fbi)
1077 {
1078 struct pxafb_dma_descriptor *dma_desc;
1079 unsigned long dma_desc_off, cmd_buff_off;
1080
1081 dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
1082 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
1083 cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
1084
1085 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1086 dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
1087 dma_desc->fidr = 0;
1088 dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
1089
1090 fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
1091 return 0;
1092 }
1093
1094 int pxafb_smart_flush(struct fb_info *info)
1095 {
1096 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
1097 uint32_t prsr;
1098 int ret = 0;
1099
1100 /* disable controller until all registers are set up */
1101 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1102
1103 /* 1. make it an even number of commands to align on 32-bit boundary
1104 * 2. add the interrupt command to the end of the chain so we can
1105 * keep track of the end of the transfer
1106 */
1107
1108 while (fbi->n_smart_cmds & 1)
1109 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
1110
1111 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
1112 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
1113 setup_smart_dma(fbi);
1114
1115 /* continue to execute next command */
1116 prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
1117 lcd_writel(fbi, PRSR, prsr);
1118
1119 /* stop the processor in case it executed "wait for sync" cmd */
1120 lcd_writel(fbi, CMDCR, 0x0001);
1121
1122 /* don't send interrupts for fifo underruns on channel 6 */
1123 lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
1124
1125 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1126 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1127 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1128 lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
1129 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1130 lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
1131
1132 /* begin sending */
1133 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1134
1135 if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
1136 pr_warning("%s: timeout waiting for command done\n",
1137 __func__);
1138 ret = -ETIMEDOUT;
1139 }
1140
1141 /* quick disable */
1142 prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
1143 lcd_writel(fbi, PRSR, prsr);
1144 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1145 lcd_writel(fbi, FDADR6, 0);
1146 fbi->n_smart_cmds = 0;
1147 return ret;
1148 }
1149
1150 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
1151 {
1152 int i;
1153 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
1154
1155 for (i = 0; i < n_cmds; i++, cmds++) {
1156 /* if it is a software delay, flush and delay */
1157 if ((*cmds & 0xff00) == SMART_CMD_DELAY) {
1158 pxafb_smart_flush(info);
1159 mdelay(*cmds & 0xff);
1160 continue;
1161 }
1162
1163 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
1164 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
1165 pxafb_smart_flush(info);
1166
1167 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds;
1168 }
1169
1170 return 0;
1171 }
1172
1173 static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
1174 {
1175 unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
1176 return (t == 0) ? 1 : t;
1177 }
1178
1179 static void setup_smart_timing(struct pxafb_info *fbi,
1180 struct fb_var_screeninfo *var)
1181 {
1182 struct pxafb_mach_info *inf = fbi->dev->platform_data;
1183 struct pxafb_mode_info *mode = &inf->modes[0];
1184 unsigned long lclk = clk_get_rate(fbi->clk);
1185 unsigned t1, t2, t3, t4;
1186
1187 t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
1188 t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
1189 t3 = mode->op_hold_time;
1190 t4 = mode->cmd_inh_time;
1191
1192 fbi->reg_lccr1 =
1193 LCCR1_DisWdth(var->xres) |
1194 LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
1195 LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
1196 LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
1197
1198 fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
1199 fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk));
1200 fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0;
1201 fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0;
1202
1203 /* FIXME: make this configurable */
1204 fbi->reg_cmdcr = 1;
1205 }
1206
1207 static int pxafb_smart_thread(void *arg)
1208 {
1209 struct pxafb_info *fbi = arg;
1210 struct pxafb_mach_info *inf = fbi->dev->platform_data;
1211
1212 if (!fbi || !inf->smart_update) {
1213 pr_err("%s: not properly initialized, thread terminated\n",
1214 __func__);
1215 return -EINVAL;
1216 }
1217
1218 pr_debug("%s(): task starting\n", __func__);
1219
1220 set_freezable();
1221 while (!kthread_should_stop()) {
1222
1223 if (try_to_freeze())
1224 continue;
1225
1226 mutex_lock(&fbi->ctrlr_lock);
1227
1228 if (fbi->state == C_ENABLE) {
1229 inf->smart_update(&fbi->fb);
1230 complete(&fbi->refresh_done);
1231 }
1232
1233 mutex_unlock(&fbi->ctrlr_lock);
1234
1235 set_current_state(TASK_INTERRUPTIBLE);
1236 schedule_timeout(30 * HZ / 1000);
1237 }
1238
1239 pr_debug("%s(): task ending\n", __func__);
1240 return 0;
1241 }
1242
1243 static int pxafb_smart_init(struct pxafb_info *fbi)
1244 {
1245 if (!(fbi->lccr0 & LCCR0_LCDT))
1246 return 0;
1247
1248 fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
1249 fbi->n_smart_cmds = 0;
1250
1251 init_completion(&fbi->command_done);
1252 init_completion(&fbi->refresh_done);
1253
1254 fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
1255 "lcd_refresh");
1256 if (IS_ERR(fbi->smart_thread)) {
1257 pr_err("%s: unable to create kernel thread\n", __func__);
1258 return PTR_ERR(fbi->smart_thread);
1259 }
1260
1261 return 0;
1262 }
1263 #else
1264 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
1265 {
1266 return 0;
1267 }
1268
1269 int pxafb_smart_flush(struct fb_info *info)
1270 {
1271 return 0;
1272 }
1273
1274 static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; }
1275 #endif /* CONFIG_FB_PXA_SMARTPANEL */
1276
1277 static void setup_parallel_timing(struct pxafb_info *fbi,
1278 struct fb_var_screeninfo *var)
1279 {
1280 unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
1281
1282 fbi->reg_lccr1 =
1283 LCCR1_DisWdth(var->xres) +
1284 LCCR1_HorSnchWdth(var->hsync_len) +
1285 LCCR1_BegLnDel(var->left_margin) +
1286 LCCR1_EndLnDel(var->right_margin);
1287
1288 /*
1289 * If we have a dual scan LCD, we need to halve
1290 * the YRES parameter.
1291 */
1292 lines_per_panel = var->yres;
1293 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1294 lines_per_panel /= 2;
1295
1296 fbi->reg_lccr2 =
1297 LCCR2_DisHght(lines_per_panel) +
1298 LCCR2_VrtSnchWdth(var->vsync_len) +
1299 LCCR2_BegFrmDel(var->upper_margin) +
1300 LCCR2_EndFrmDel(var->lower_margin);
1301
1302 fbi->reg_lccr3 = fbi->lccr3 |
1303 (var->sync & FB_SYNC_HOR_HIGH_ACT ?
1304 LCCR3_HorSnchH : LCCR3_HorSnchL) |
1305 (var->sync & FB_SYNC_VERT_HIGH_ACT ?
1306 LCCR3_VrtSnchH : LCCR3_VrtSnchL);
1307
1308 if (pcd) {
1309 fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
1310 set_hsync_time(fbi, pcd);
1311 }
1312 }
1313
1314 /*
1315 * pxafb_activate_var():
1316 * Configures LCD Controller based on entries in var parameter.
1317 * Settings are only written to the controller if changes were made.
1318 */
1319 static int pxafb_activate_var(struct fb_var_screeninfo *var,
1320 struct pxafb_info *fbi)
1321 {
1322 u_long flags;
1323
1324 /* Update shadow copy atomically */
1325 local_irq_save(flags);
1326
1327 #ifdef CONFIG_FB_PXA_SMARTPANEL
1328 if (fbi->lccr0 & LCCR0_LCDT)
1329 setup_smart_timing(fbi, var);
1330 else
1331 #endif
1332 setup_parallel_timing(fbi, var);
1333
1334 setup_base_frame(fbi, 0);
1335
1336 fbi->reg_lccr0 = fbi->lccr0 |
1337 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
1338 LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
1339
1340 fbi->reg_lccr3 |= pxafb_var_to_lccr3(var);
1341
1342 fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
1343 fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
1344 local_irq_restore(flags);
1345
1346 /*
1347 * Only update the registers if the controller is enabled
1348 * and something has changed.
1349 */
1350 if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
1351 (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
1352 (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
1353 (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
1354 (lcd_readl(fbi, LCCR4) != fbi->reg_lccr4) ||
1355 (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
1356 (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))
1357 pxafb_schedule_work(fbi, C_REENABLE);
1358
1359 return 0;
1360 }
1361
1362 /*
1363 * NOTE! The following functions are purely helpers for set_ctrlr_state.
1364 * Do not call them directly; set_ctrlr_state does the correct serialisation
1365 * to ensure that things happen in the right way 100% of time time.
1366 * -- rmk
1367 */
1368 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
1369 {
1370 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
1371
1372 if (fbi->backlight_power)
1373 fbi->backlight_power(on);
1374 }
1375
1376 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
1377 {
1378 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
1379
1380 if (fbi->lcd_power)
1381 fbi->lcd_power(on, &fbi->fb.var);
1382 }
1383
1384 static void pxafb_enable_controller(struct pxafb_info *fbi)
1385 {
1386 pr_debug("pxafb: Enabling LCD controller\n");
1387 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
1388 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
1389 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
1390 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
1391 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
1392 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
1393
1394 /* enable LCD controller clock */
1395 clk_enable(fbi->clk);
1396
1397 if (fbi->lccr0 & LCCR0_LCDT)
1398 return;
1399
1400 /* Sequence from 11.7.10 */
1401 lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
1402 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1403 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1404 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1405 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1406
1407 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1408 lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
1409 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1410 }
1411
1412 static void pxafb_disable_controller(struct pxafb_info *fbi)
1413 {
1414 uint32_t lccr0;
1415
1416 #ifdef CONFIG_FB_PXA_SMARTPANEL
1417 if (fbi->lccr0 & LCCR0_LCDT) {
1418 wait_for_completion_timeout(&fbi->refresh_done,
1419 200 * HZ / 1000);
1420 return;
1421 }
1422 #endif
1423
1424 /* Clear LCD Status Register */
1425 lcd_writel(fbi, LCSR, 0xffffffff);
1426
1427 lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
1428 lcd_writel(fbi, LCCR0, lccr0);
1429 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
1430
1431 wait_for_completion_timeout(&fbi->disable_done, 200 * HZ / 1000);
1432
1433 /* disable LCD controller clock */
1434 clk_disable(fbi->clk);
1435 }
1436
1437 /*
1438 * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
1439 */
1440 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1441 {
1442 struct pxafb_info *fbi = dev_id;
1443 unsigned int lccr0, lcsr, lcsr1;
1444
1445 lcsr = lcd_readl(fbi, LCSR);
1446 if (lcsr & LCSR_LDD) {
1447 lccr0 = lcd_readl(fbi, LCCR0);
1448 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
1449 complete(&fbi->disable_done);
1450 }
1451
1452 #ifdef CONFIG_FB_PXA_SMARTPANEL
1453 if (lcsr & LCSR_CMD_INT)
1454 complete(&fbi->command_done);
1455 #endif
1456 lcd_writel(fbi, LCSR, lcsr);
1457
1458 #ifdef CONFIG_FB_PXA_OVERLAY
1459 lcsr1 = lcd_readl(fbi, LCSR1);
1460 if (lcsr1 & LCSR1_BS(1))
1461 complete(&fbi->overlay[0].branch_done);
1462
1463 if (lcsr1 & LCSR1_BS(2))
1464 complete(&fbi->overlay[1].branch_done);
1465
1466 lcd_writel(fbi, LCSR1, lcsr1);
1467 #endif
1468 return IRQ_HANDLED;
1469 }
1470
1471 /*
1472 * This function must be called from task context only, since it will
1473 * sleep when disabling the LCD controller, or if we get two contending
1474 * processes trying to alter state.
1475 */
1476 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1477 {
1478 u_int old_state;
1479
1480 mutex_lock(&fbi->ctrlr_lock);
1481
1482 old_state = fbi->state;
1483
1484 /*
1485 * Hack around fbcon initialisation.
1486 */
1487 if (old_state == C_STARTUP && state == C_REENABLE)
1488 state = C_ENABLE;
1489
1490 switch (state) {
1491 case C_DISABLE_CLKCHANGE:
1492 /*
1493 * Disable controller for clock change. If the
1494 * controller is already disabled, then do nothing.
1495 */
1496 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1497 fbi->state = state;
1498 /* TODO __pxafb_lcd_power(fbi, 0); */
1499 pxafb_disable_controller(fbi);
1500 }
1501 break;
1502
1503 case C_DISABLE_PM:
1504 case C_DISABLE:
1505 /*
1506 * Disable controller
1507 */
1508 if (old_state != C_DISABLE) {
1509 fbi->state = state;
1510 __pxafb_backlight_power(fbi, 0);
1511 __pxafb_lcd_power(fbi, 0);
1512 if (old_state != C_DISABLE_CLKCHANGE)
1513 pxafb_disable_controller(fbi);
1514 }
1515 break;
1516
1517 case C_ENABLE_CLKCHANGE:
1518 /*
1519 * Enable the controller after clock change. Only
1520 * do this if we were disabled for the clock change.
1521 */
1522 if (old_state == C_DISABLE_CLKCHANGE) {
1523 fbi->state = C_ENABLE;
1524 pxafb_enable_controller(fbi);
1525 /* TODO __pxafb_lcd_power(fbi, 1); */
1526 }
1527 break;
1528
1529 case C_REENABLE:
1530 /*
1531 * Re-enable the controller only if it was already
1532 * enabled. This is so we reprogram the control
1533 * registers.
1534 */
1535 if (old_state == C_ENABLE) {
1536 __pxafb_lcd_power(fbi, 0);
1537 pxafb_disable_controller(fbi);
1538 pxafb_enable_controller(fbi);
1539 __pxafb_lcd_power(fbi, 1);
1540 }
1541 break;
1542
1543 case C_ENABLE_PM:
1544 /*
1545 * Re-enable the controller after PM. This is not
1546 * perfect - think about the case where we were doing
1547 * a clock change, and we suspended half-way through.
1548 */
1549 if (old_state != C_DISABLE_PM)
1550 break;
1551 /* fall through */
1552
1553 case C_ENABLE:
1554 /*
1555 * Power up the LCD screen, enable controller, and
1556 * turn on the backlight.
1557 */
1558 if (old_state != C_ENABLE) {
1559 fbi->state = C_ENABLE;
1560 pxafb_enable_controller(fbi);
1561 __pxafb_lcd_power(fbi, 1);
1562 __pxafb_backlight_power(fbi, 1);
1563 }
1564 break;
1565 }
1566 mutex_unlock(&fbi->ctrlr_lock);
1567 }
1568
1569 /*
1570 * Our LCD controller task (which is called when we blank or unblank)
1571 * via keventd.
1572 */
1573 static void pxafb_task(struct work_struct *work)
1574 {
1575 struct pxafb_info *fbi =
1576 container_of(work, struct pxafb_info, task);
1577 u_int state = xchg(&fbi->task_state, -1);
1578
1579 set_ctrlr_state(fbi, state);
1580 }
1581
1582 #ifdef CONFIG_CPU_FREQ
1583 /*
1584 * CPU clock speed change handler. We need to adjust the LCD timing
1585 * parameters when the CPU clock is adjusted by the power management
1586 * subsystem.
1587 *
1588 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
1589 */
1590 static int
1591 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
1592 {
1593 struct pxafb_info *fbi = TO_INF(nb, freq_transition);
1594 /* TODO struct cpufreq_freqs *f = data; */
1595 u_int pcd;
1596
1597 switch (val) {
1598 case CPUFREQ_PRECHANGE:
1599 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1600 break;
1601
1602 case CPUFREQ_POSTCHANGE:
1603 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
1604 set_hsync_time(fbi, pcd);
1605 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
1606 LCCR3_PixClkDiv(pcd);
1607 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1608 break;
1609 }
1610 return 0;
1611 }
1612
1613 static int
1614 pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
1615 {
1616 struct pxafb_info *fbi = TO_INF(nb, freq_policy);
1617 struct fb_var_screeninfo *var = &fbi->fb.var;
1618 struct cpufreq_policy *policy = data;
1619
1620 switch (val) {
1621 case CPUFREQ_ADJUST:
1622 case CPUFREQ_INCOMPATIBLE:
1623 pr_debug("min dma period: %d ps, "
1624 "new clock %d kHz\n", pxafb_display_dma_period(var),
1625 policy->max);
1626 /* TODO: fill in min/max values */
1627 break;
1628 }
1629 return 0;
1630 }
1631 #endif
1632
1633 #ifdef CONFIG_PM
1634 /*
1635 * Power management hooks. Note that we won't be called from IRQ context,
1636 * unlike the blank functions above, so we may sleep.
1637 */
1638 static int pxafb_suspend(struct platform_device *dev, pm_message_t state)
1639 {
1640 struct pxafb_info *fbi = platform_get_drvdata(dev);
1641
1642 set_ctrlr_state(fbi, C_DISABLE_PM);
1643 return 0;
1644 }
1645
1646 static int pxafb_resume(struct platform_device *dev)
1647 {
1648 struct pxafb_info *fbi = platform_get_drvdata(dev);
1649
1650 set_ctrlr_state(fbi, C_ENABLE_PM);
1651 return 0;
1652 }
1653 #else
1654 #define pxafb_suspend NULL
1655 #define pxafb_resume NULL
1656 #endif
1657
1658 static int __devinit pxafb_init_video_memory(struct pxafb_info *fbi)
1659 {
1660 int size = PAGE_ALIGN(fbi->video_mem_size);
1661
1662 fbi->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
1663 if (fbi->video_mem == NULL)
1664 return -ENOMEM;
1665
1666 fbi->video_mem_phys = virt_to_phys(fbi->video_mem);
1667 fbi->video_mem_size = size;
1668
1669 fbi->fb.fix.smem_start = fbi->video_mem_phys;
1670 fbi->fb.fix.smem_len = fbi->video_mem_size;
1671 fbi->fb.screen_base = fbi->video_mem;
1672
1673 return fbi->video_mem ? 0 : -ENOMEM;
1674 }
1675
1676 static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1677 struct pxafb_mach_info *inf)
1678 {
1679 unsigned int lcd_conn = inf->lcd_conn;
1680 struct pxafb_mode_info *m;
1681 int i;
1682
1683 fbi->cmap_inverse = inf->cmap_inverse;
1684 fbi->cmap_static = inf->cmap_static;
1685 fbi->lccr4 = inf->lccr4;
1686
1687 switch (lcd_conn & LCD_TYPE_MASK) {
1688 case LCD_TYPE_MONO_STN:
1689 fbi->lccr0 = LCCR0_CMS;
1690 break;
1691 case LCD_TYPE_MONO_DSTN:
1692 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1693 break;
1694 case LCD_TYPE_COLOR_STN:
1695 fbi->lccr0 = 0;
1696 break;
1697 case LCD_TYPE_COLOR_DSTN:
1698 fbi->lccr0 = LCCR0_SDS;
1699 break;
1700 case LCD_TYPE_COLOR_TFT:
1701 fbi->lccr0 = LCCR0_PAS;
1702 break;
1703 case LCD_TYPE_SMART_PANEL:
1704 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1705 break;
1706 default:
1707 /* fall back to backward compatibility way */
1708 fbi->lccr0 = inf->lccr0;
1709 fbi->lccr3 = inf->lccr3;
1710 goto decode_mode;
1711 }
1712
1713 if (lcd_conn == LCD_MONO_STN_8BPP)
1714 fbi->lccr0 |= LCCR0_DPD;
1715
1716 fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0;
1717
1718 fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1719 fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1720 fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
1721
1722 decode_mode:
1723 pxafb_setmode(&fbi->fb.var, &inf->modes[0]);
1724
1725 /* decide video memory size as follows:
1726 * 1. default to mode of maximum resolution
1727 * 2. allow platform to override
1728 * 3. allow module parameter to override
1729 */
1730 for (i = 0, m = &inf->modes[0]; i < inf->num_modes; i++, m++)
1731 fbi->video_mem_size = max_t(size_t, fbi->video_mem_size,
1732 m->xres * m->yres * m->bpp / 8);
1733
1734 if (inf->video_mem_size > fbi->video_mem_size)
1735 fbi->video_mem_size = inf->video_mem_size;
1736
1737 if (video_mem_size > fbi->video_mem_size)
1738 fbi->video_mem_size = video_mem_size;
1739 }
1740
1741 static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
1742 {
1743 struct pxafb_info *fbi;
1744 void *addr;
1745 struct pxafb_mach_info *inf = dev->platform_data;
1746
1747 /* Alloc the pxafb_info and pseudo_palette in one step */
1748 fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1749 if (!fbi)
1750 return NULL;
1751
1752 memset(fbi, 0, sizeof(struct pxafb_info));
1753 fbi->dev = dev;
1754
1755 fbi->clk = clk_get(dev, NULL);
1756 if (IS_ERR(fbi->clk)) {
1757 kfree(fbi);
1758 return NULL;
1759 }
1760
1761 strcpy(fbi->fb.fix.id, PXA_NAME);
1762
1763 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1764 fbi->fb.fix.type_aux = 0;
1765 fbi->fb.fix.xpanstep = 0;
1766 fbi->fb.fix.ypanstep = 1;
1767 fbi->fb.fix.ywrapstep = 0;
1768 fbi->fb.fix.accel = FB_ACCEL_NONE;
1769
1770 fbi->fb.var.nonstd = 0;
1771 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1772 fbi->fb.var.height = -1;
1773 fbi->fb.var.width = -1;
1774 fbi->fb.var.accel_flags = FB_ACCELF_TEXT;
1775 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1776
1777 fbi->fb.fbops = &pxafb_ops;
1778 fbi->fb.flags = FBINFO_DEFAULT;
1779 fbi->fb.node = -1;
1780
1781 addr = fbi;
1782 addr = addr + sizeof(struct pxafb_info);
1783 fbi->fb.pseudo_palette = addr;
1784
1785 fbi->state = C_STARTUP;
1786 fbi->task_state = (u_char)-1;
1787
1788 pxafb_decode_mach_info(fbi, inf);
1789
1790 init_waitqueue_head(&fbi->ctrlr_wait);
1791 INIT_WORK(&fbi->task, pxafb_task);
1792 mutex_init(&fbi->ctrlr_lock);
1793 init_completion(&fbi->disable_done);
1794
1795 return fbi;
1796 }
1797
1798 #ifdef CONFIG_FB_PXA_PARAMETERS
1799 static int __devinit parse_opt_mode(struct device *dev, const char *this_opt)
1800 {
1801 struct pxafb_mach_info *inf = dev->platform_data;
1802
1803 const char *name = this_opt+5;
1804 unsigned int namelen = strlen(name);
1805 int res_specified = 0, bpp_specified = 0;
1806 unsigned int xres = 0, yres = 0, bpp = 0;
1807 int yres_specified = 0;
1808 int i;
1809 for (i = namelen-1; i >= 0; i--) {
1810 switch (name[i]) {
1811 case '-':
1812 namelen = i;
1813 if (!bpp_specified && !yres_specified) {
1814 bpp = simple_strtoul(&name[i+1], NULL, 0);
1815 bpp_specified = 1;
1816 } else
1817 goto done;
1818 break;
1819 case 'x':
1820 if (!yres_specified) {
1821 yres = simple_strtoul(&name[i+1], NULL, 0);
1822 yres_specified = 1;
1823 } else
1824 goto done;
1825 break;
1826 case '0' ... '9':
1827 break;
1828 default:
1829 goto done;
1830 }
1831 }
1832 if (i < 0 && yres_specified) {
1833 xres = simple_strtoul(name, NULL, 0);
1834 res_specified = 1;
1835 }
1836 done:
1837 if (res_specified) {
1838 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1839 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1840 }
1841 if (bpp_specified)
1842 switch (bpp) {
1843 case 1:
1844 case 2:
1845 case 4:
1846 case 8:
1847 case 16:
1848 inf->modes[0].bpp = bpp;
1849 dev_info(dev, "overriding bit depth: %d\n", bpp);
1850 break;
1851 default:
1852 dev_err(dev, "Depth %d is not valid\n", bpp);
1853 return -EINVAL;
1854 }
1855 return 0;
1856 }
1857
1858 static int __devinit parse_opt(struct device *dev, char *this_opt)
1859 {
1860 struct pxafb_mach_info *inf = dev->platform_data;
1861 struct pxafb_mode_info *mode = &inf->modes[0];
1862 char s[64];
1863
1864 s[0] = '\0';
1865
1866 if (!strncmp(this_opt, "vmem:", 5)) {
1867 video_mem_size = memparse(this_opt + 5, NULL);
1868 } else if (!strncmp(this_opt, "mode:", 5)) {
1869 return parse_opt_mode(dev, this_opt);
1870 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1871 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1872 sprintf(s, "pixclock: %ld\n", mode->pixclock);
1873 } else if (!strncmp(this_opt, "left:", 5)) {
1874 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1875 sprintf(s, "left: %u\n", mode->left_margin);
1876 } else if (!strncmp(this_opt, "right:", 6)) {
1877 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1878 sprintf(s, "right: %u\n", mode->right_margin);
1879 } else if (!strncmp(this_opt, "upper:", 6)) {
1880 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1881 sprintf(s, "upper: %u\n", mode->upper_margin);
1882 } else if (!strncmp(this_opt, "lower:", 6)) {
1883 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1884 sprintf(s, "lower: %u\n", mode->lower_margin);
1885 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1886 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1887 sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1888 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1889 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1890 sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1891 } else if (!strncmp(this_opt, "hsync:", 6)) {
1892 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1893 sprintf(s, "hsync: Active Low\n");
1894 mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1895 } else {
1896 sprintf(s, "hsync: Active High\n");
1897 mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1898 }
1899 } else if (!strncmp(this_opt, "vsync:", 6)) {
1900 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1901 sprintf(s, "vsync: Active Low\n");
1902 mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1903 } else {
1904 sprintf(s, "vsync: Active High\n");
1905 mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1906 }
1907 } else if (!strncmp(this_opt, "dpc:", 4)) {
1908 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1909 sprintf(s, "double pixel clock: false\n");
1910 inf->lccr3 &= ~LCCR3_DPC;
1911 } else {
1912 sprintf(s, "double pixel clock: true\n");
1913 inf->lccr3 |= LCCR3_DPC;
1914 }
1915 } else if (!strncmp(this_opt, "outputen:", 9)) {
1916 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1917 sprintf(s, "output enable: active low\n");
1918 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1919 } else {
1920 sprintf(s, "output enable: active high\n");
1921 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1922 }
1923 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1924 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1925 sprintf(s, "pixel clock polarity: falling edge\n");
1926 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1927 } else {
1928 sprintf(s, "pixel clock polarity: rising edge\n");
1929 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1930 }
1931 } else if (!strncmp(this_opt, "color", 5)) {
1932 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1933 } else if (!strncmp(this_opt, "mono", 4)) {
1934 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1935 } else if (!strncmp(this_opt, "active", 6)) {
1936 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1937 } else if (!strncmp(this_opt, "passive", 7)) {
1938 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1939 } else if (!strncmp(this_opt, "single", 6)) {
1940 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1941 } else if (!strncmp(this_opt, "dual", 4)) {
1942 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1943 } else if (!strncmp(this_opt, "4pix", 4)) {
1944 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1945 } else if (!strncmp(this_opt, "8pix", 4)) {
1946 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1947 } else {
1948 dev_err(dev, "unknown option: %s\n", this_opt);
1949 return -EINVAL;
1950 }
1951
1952 if (s[0] != '\0')
1953 dev_info(dev, "override %s", s);
1954
1955 return 0;
1956 }
1957
1958 static int __devinit pxafb_parse_options(struct device *dev, char *options)
1959 {
1960 char *this_opt;
1961 int ret;
1962
1963 if (!options || !*options)
1964 return 0;
1965
1966 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1967
1968 /* could be made table driven or similar?... */
1969 while ((this_opt = strsep(&options, ",")) != NULL) {
1970 ret = parse_opt(dev, this_opt);
1971 if (ret)
1972 return ret;
1973 }
1974 return 0;
1975 }
1976
1977 static char g_options[256] __devinitdata = "";
1978
1979 #ifndef MODULE
1980 static int __init pxafb_setup_options(void)
1981 {
1982 char *options = NULL;
1983
1984 if (fb_get_options("pxafb", &options))
1985 return -ENODEV;
1986
1987 if (options)
1988 strlcpy(g_options, options, sizeof(g_options));
1989
1990 return 0;
1991 }
1992 #else
1993 #define pxafb_setup_options() (0)
1994
1995 module_param_string(options, g_options, sizeof(g_options), 0);
1996 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1997 #endif
1998
1999 #else
2000 #define pxafb_parse_options(...) (0)
2001 #define pxafb_setup_options() (0)
2002 #endif
2003
2004 #ifdef DEBUG_VAR
2005 /* Check for various illegal bit-combinations. Currently only
2006 * a warning is given. */
2007 static void __devinit pxafb_check_options(struct device *dev,
2008 struct pxafb_mach_info *inf)
2009 {
2010 if (inf->lcd_conn)
2011 return;
2012
2013 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
2014 dev_warn(dev, "machine LCCR0 setting contains "
2015 "illegal bits: %08x\n",
2016 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
2017 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
2018 dev_warn(dev, "machine LCCR3 setting contains "
2019 "illegal bits: %08x\n",
2020 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
2021 if (inf->lccr0 & LCCR0_DPD &&
2022 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
2023 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
2024 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
2025 dev_warn(dev, "Double Pixel Data (DPD) mode is "
2026 "only valid in passive mono"
2027 " single panel mode\n");
2028 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
2029 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
2030 dev_warn(dev, "Dual panel only valid in passive mode\n");
2031 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
2032 (inf->modes->upper_margin || inf->modes->lower_margin))
2033 dev_warn(dev, "Upper and lower margins must be 0 in "
2034 "passive mode\n");
2035 }
2036 #else
2037 #define pxafb_check_options(...) do {} while (0)
2038 #endif
2039
2040 static int __devinit pxafb_probe(struct platform_device *dev)
2041 {
2042 struct pxafb_info *fbi;
2043 struct pxafb_mach_info *inf;
2044 struct resource *r;
2045 int irq, ret;
2046
2047 dev_dbg(&dev->dev, "pxafb_probe\n");
2048
2049 inf = dev->dev.platform_data;
2050 ret = -ENOMEM;
2051 fbi = NULL;
2052 if (!inf)
2053 goto failed;
2054
2055 ret = pxafb_parse_options(&dev->dev, g_options);
2056 if (ret < 0)
2057 goto failed;
2058
2059 pxafb_check_options(&dev->dev, inf);
2060
2061 dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
2062 inf->modes->xres,
2063 inf->modes->yres,
2064 inf->modes->bpp);
2065 if (inf->modes->xres == 0 ||
2066 inf->modes->yres == 0 ||
2067 inf->modes->bpp == 0) {
2068 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
2069 ret = -EINVAL;
2070 goto failed;
2071 }
2072
2073 fbi = pxafb_init_fbinfo(&dev->dev);
2074 if (!fbi) {
2075 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
2076 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
2077 ret = -ENOMEM;
2078 goto failed;
2079 }
2080
2081 fbi->backlight_power = inf->pxafb_backlight_power;
2082 fbi->lcd_power = inf->pxafb_lcd_power;
2083
2084 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
2085 if (r == NULL) {
2086 dev_err(&dev->dev, "no I/O memory resource defined\n");
2087 ret = -ENODEV;
2088 goto failed_fbi;
2089 }
2090
2091 r = request_mem_region(r->start, r->end - r->start + 1, dev->name);
2092 if (r == NULL) {
2093 dev_err(&dev->dev, "failed to request I/O memory\n");
2094 ret = -EBUSY;
2095 goto failed_fbi;
2096 }
2097
2098 fbi->mmio_base = ioremap(r->start, r->end - r->start + 1);
2099 if (fbi->mmio_base == NULL) {
2100 dev_err(&dev->dev, "failed to map I/O memory\n");
2101 ret = -EBUSY;
2102 goto failed_free_res;
2103 }
2104
2105 fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
2106 fbi->dma_buff = dma_alloc_coherent(fbi->dev, fbi->dma_buff_size,
2107 &fbi->dma_buff_phys, GFP_KERNEL);
2108 if (fbi->dma_buff == NULL) {
2109 dev_err(&dev->dev, "failed to allocate memory for DMA\n");
2110 ret = -ENOMEM;
2111 goto failed_free_io;
2112 }
2113
2114 ret = pxafb_init_video_memory(fbi);
2115 if (ret) {
2116 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
2117 ret = -ENOMEM;
2118 goto failed_free_dma;
2119 }
2120
2121 irq = platform_get_irq(dev, 0);
2122 if (irq < 0) {
2123 dev_err(&dev->dev, "no IRQ defined\n");
2124 ret = -ENODEV;
2125 goto failed_free_mem;
2126 }
2127
2128 ret = request_irq(irq, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
2129 if (ret) {
2130 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
2131 ret = -EBUSY;
2132 goto failed_free_mem;
2133 }
2134
2135 ret = pxafb_smart_init(fbi);
2136 if (ret) {
2137 dev_err(&dev->dev, "failed to initialize smartpanel\n");
2138 goto failed_free_irq;
2139 }
2140
2141 /*
2142 * This makes sure that our colour bitfield
2143 * descriptors are correctly initialised.
2144 */
2145 ret = pxafb_check_var(&fbi->fb.var, &fbi->fb);
2146 if (ret) {
2147 dev_err(&dev->dev, "failed to get suitable mode\n");
2148 goto failed_free_irq;
2149 }
2150
2151 ret = pxafb_set_par(&fbi->fb);
2152 if (ret) {
2153 dev_err(&dev->dev, "Failed to set parameters\n");
2154 goto failed_free_irq;
2155 }
2156
2157 platform_set_drvdata(dev, fbi);
2158
2159 ret = register_framebuffer(&fbi->fb);
2160 if (ret < 0) {
2161 dev_err(&dev->dev,
2162 "Failed to register framebuffer device: %d\n", ret);
2163 goto failed_free_cmap;
2164 }
2165
2166 pxafb_overlay_init(fbi);
2167
2168 #ifdef CONFIG_CPU_FREQ
2169 fbi->freq_transition.notifier_call = pxafb_freq_transition;
2170 fbi->freq_policy.notifier_call = pxafb_freq_policy;
2171 cpufreq_register_notifier(&fbi->freq_transition,
2172 CPUFREQ_TRANSITION_NOTIFIER);
2173 cpufreq_register_notifier(&fbi->freq_policy,
2174 CPUFREQ_POLICY_NOTIFIER);
2175 #endif
2176
2177 /*
2178 * Ok, now enable the LCD controller
2179 */
2180 set_ctrlr_state(fbi, C_ENABLE);
2181
2182 return 0;
2183
2184 failed_free_cmap:
2185 if (fbi->fb.cmap.len)
2186 fb_dealloc_cmap(&fbi->fb.cmap);
2187 failed_free_irq:
2188 free_irq(irq, fbi);
2189 failed_free_mem:
2190 free_pages_exact(fbi->video_mem, fbi->video_mem_size);
2191 failed_free_dma:
2192 dma_free_coherent(&dev->dev, fbi->dma_buff_size,
2193 fbi->dma_buff, fbi->dma_buff_phys);
2194 failed_free_io:
2195 iounmap(fbi->mmio_base);
2196 failed_free_res:
2197 release_mem_region(r->start, r->end - r->start + 1);
2198 failed_fbi:
2199 clk_put(fbi->clk);
2200 platform_set_drvdata(dev, NULL);
2201 kfree(fbi);
2202 failed:
2203 return ret;
2204 }
2205
2206 static int __devexit pxafb_remove(struct platform_device *dev)
2207 {
2208 struct pxafb_info *fbi = platform_get_drvdata(dev);
2209 struct resource *r;
2210 int irq;
2211 struct fb_info *info;
2212
2213 if (!fbi)
2214 return 0;
2215
2216 info = &fbi->fb;
2217
2218 pxafb_overlay_exit(fbi);
2219 unregister_framebuffer(info);
2220
2221 pxafb_disable_controller(fbi);
2222
2223 if (fbi->fb.cmap.len)
2224 fb_dealloc_cmap(&fbi->fb.cmap);
2225
2226 irq = platform_get_irq(dev, 0);
2227 free_irq(irq, fbi);
2228
2229 free_pages_exact(fbi->video_mem, fbi->video_mem_size);
2230
2231 dma_free_writecombine(&dev->dev, fbi->dma_buff_size,
2232 fbi->dma_buff, fbi->dma_buff_phys);
2233
2234 iounmap(fbi->mmio_base);
2235
2236 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
2237 release_mem_region(r->start, r->end - r->start + 1);
2238
2239 clk_put(fbi->clk);
2240 kfree(fbi);
2241
2242 return 0;
2243 }
2244
2245 static struct platform_driver pxafb_driver = {
2246 .probe = pxafb_probe,
2247 .remove = pxafb_remove,
2248 .suspend = pxafb_suspend,
2249 .resume = pxafb_resume,
2250 .driver = {
2251 .owner = THIS_MODULE,
2252 .name = "pxa2xx-fb",
2253 },
2254 };
2255
2256 static int __init pxafb_init(void)
2257 {
2258 if (pxafb_setup_options())
2259 return -EINVAL;
2260
2261 return platform_driver_register(&pxafb_driver);
2262 }
2263
2264 static void __exit pxafb_exit(void)
2265 {
2266 platform_driver_unregister(&pxafb_driver);
2267 }
2268
2269 module_init(pxafb_init);
2270 module_exit(pxafb_exit);
2271
2272 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
2273 MODULE_LICENSE("GPL");
AMDTP streaming driver for the Linux FireWire stack (Juju)