2 * Permedia2 framebuffer driver.
5 * Copyright (c) 2003 Jim Hague (jim.hague@acm.org)
8 * Copyright (c) 1998-2000 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
9 * Copyright (c) 1999 Jakub Jelinek (jakub@redhat.com)
11 * and additional input from James Simmon's port of Hannu Mallat's tdfx
14 * I have a Creative Graphics Blaster Exxtreme card - pm2fb on x86. I
15 * have no access to other pm2fb implementations. Sparc (and thus
16 * hopefully other big-endian) devices now work, thanks to a lot of
17 * testing work by Ron Murray. I have no access to CVision hardware,
18 * and therefore for now I am omitting the CVision code.
20 * Multiple boards support has been on the TODO list for ages.
21 * Don't expect this to change.
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive for
30 #include <linux/module.h>
31 #include <linux/moduleparam.h>
32 #include <linux/kernel.h>
33 #include <linux/errno.h>
34 #include <linux/string.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
39 #include <linux/init.h>
40 #include <linux/pci.h>
42 #include <video/permedia2.h>
43 #include <video/cvisionppc.h>
45 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
46 #error "The endianness of the target host has not been defined."
49 #if !defined(CONFIG_PCI)
50 #error "Only generic PCI cards supported."
53 #undef PM2FB_MASTER_DEBUG
54 #ifdef PM2FB_MASTER_DEBUG
55 #define DPRINTK(a,b...) printk(KERN_DEBUG "pm2fb: %s: " a, __FUNCTION__ , ## b)
57 #define DPRINTK(a,b...)
63 static char *mode __devinitdata
= NULL
;
66 * The XFree GLINT driver will (I think to implement hardware cursor
67 * support on TVP4010 and similar where there is no RAMDAC - see
68 * comment in set_video) always request +ve sync regardless of what
69 * the mode requires. This screws me because I have a Sun
70 * fixed-frequency monitor which absolutely has to have -ve sync. So
71 * these flags allow the user to specify that requests for +ve sync
72 * should be silently turned in -ve sync.
78 * The hardware state of the graphics card that isn't part of the
83 pm2type_t type
; /* Board type */
84 u32 fb_size
; /* framebuffer memory size */
85 unsigned char __iomem
*v_fb
; /* virtual address of frame buffer */
86 unsigned char __iomem
*v_regs
;/* virtual address of p_regs */
87 u32 memclock
; /* memclock */
88 u32 video
; /* video flags before blanking */
89 u32 mem_config
; /* MemConfig reg at probe */
90 u32 mem_control
; /* MemControl reg at probe */
91 u32 boot_address
; /* BootAddress reg at probe */
96 * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
97 * if we don't use modedb.
99 static struct fb_fix_screeninfo pm2fb_fix __devinitdata
= {
101 .type
= FB_TYPE_PACKED_PIXELS
,
102 .visual
= FB_VISUAL_PSEUDOCOLOR
,
106 .accel
= FB_ACCEL_NONE
,
110 * Default video mode. In case the modedb doesn't work.
112 static struct fb_var_screeninfo pm2fb_var __devinitdata
= {
113 /* "640x480, 8 bpp @ 60 Hz */
122 .activate
= FB_ACTIVATE_NOW
,
133 .vmode
= FB_VMODE_NONINTERLACED
140 static inline u32
RD32(unsigned char __iomem
*base
, s32 off
)
142 return fb_readl(base
+ off
);
145 static inline void WR32(unsigned char __iomem
*base
, s32 off
, u32 v
)
147 fb_writel(v
, base
+ off
);
150 static inline u32
pm2_RD(struct pm2fb_par
* p
, s32 off
)
152 return RD32(p
->v_regs
, off
);
155 static inline void pm2_WR(struct pm2fb_par
* p
, s32 off
, u32 v
)
157 WR32(p
->v_regs
, off
, v
);
160 static inline u32
pm2_RDAC_RD(struct pm2fb_par
* p
, s32 idx
)
162 int index
= PM2R_RD_INDEXED_DATA
;
164 case PM2_TYPE_PERMEDIA2
:
165 pm2_WR(p
, PM2R_RD_PALETTE_WRITE_ADDRESS
, idx
);
167 case PM2_TYPE_PERMEDIA2V
:
168 pm2_WR(p
, PM2VR_RD_INDEX_LOW
, idx
& 0xff);
169 index
= PM2VR_RD_INDEXED_DATA
;
173 return pm2_RD(p
, index
);
176 static inline void pm2_RDAC_WR(struct pm2fb_par
* p
, s32 idx
, u32 v
)
178 int index
= PM2R_RD_INDEXED_DATA
;
180 case PM2_TYPE_PERMEDIA2
:
181 pm2_WR(p
, PM2R_RD_PALETTE_WRITE_ADDRESS
, idx
);
183 case PM2_TYPE_PERMEDIA2V
:
184 pm2_WR(p
, PM2VR_RD_INDEX_LOW
, idx
& 0xff);
185 index
= PM2VR_RD_INDEXED_DATA
;
192 static inline void pm2v_RDAC_WR(struct pm2fb_par
* p
, s32 idx
, u32 v
)
194 pm2_WR(p
, PM2VR_RD_INDEX_LOW
, idx
& 0xff);
196 pm2_WR(p
, PM2VR_RD_INDEXED_DATA
, v
);
199 #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
200 #define WAIT_FIFO(p,a)
202 static inline void WAIT_FIFO(struct pm2fb_par
* p
, u32 a
)
204 while( pm2_RD(p
, PM2R_IN_FIFO_SPACE
) < a
);
210 * partial products for the supported horizontal resolutions.
212 #define PACKPP(p0,p1,p2) (((p2) << 6) | ((p1) << 3) | (p0))
213 static const struct {
217 { 32, PACKPP(1, 0, 0) }, { 64, PACKPP(1, 1, 0) },
218 { 96, PACKPP(1, 1, 1) }, { 128, PACKPP(2, 1, 1) },
219 { 160, PACKPP(2, 2, 1) }, { 192, PACKPP(2, 2, 2) },
220 { 224, PACKPP(3, 2, 1) }, { 256, PACKPP(3, 2, 2) },
221 { 288, PACKPP(3, 3, 1) }, { 320, PACKPP(3, 3, 2) },
222 { 384, PACKPP(3, 3, 3) }, { 416, PACKPP(4, 3, 1) },
223 { 448, PACKPP(4, 3, 2) }, { 512, PACKPP(4, 3, 3) },
224 { 544, PACKPP(4, 4, 1) }, { 576, PACKPP(4, 4, 2) },
225 { 640, PACKPP(4, 4, 3) }, { 768, PACKPP(4, 4, 4) },
226 { 800, PACKPP(5, 4, 1) }, { 832, PACKPP(5, 4, 2) },
227 { 896, PACKPP(5, 4, 3) }, { 1024, PACKPP(5, 4, 4) },
228 { 1056, PACKPP(5, 5, 1) }, { 1088, PACKPP(5, 5, 2) },
229 { 1152, PACKPP(5, 5, 3) }, { 1280, PACKPP(5, 5, 4) },
230 { 1536, PACKPP(5, 5, 5) }, { 1568, PACKPP(6, 5, 1) },
231 { 1600, PACKPP(6, 5, 2) }, { 1664, PACKPP(6, 5, 3) },
232 { 1792, PACKPP(6, 5, 4) }, { 2048, PACKPP(6, 5, 5) },
235 static u32
partprod(u32 xres
)
239 for (i
= 0; pp_table
[i
].width
&& pp_table
[i
].width
!= xres
; i
++)
241 if ( pp_table
[i
].width
== 0 )
242 DPRINTK("invalid width %u\n", xres
);
243 return pp_table
[i
].pp
;
246 static u32
to3264(u32 timing
, int bpp
, int is64
)
256 timing
= (timing
* 3) >> (2 + is64
);
266 static void pm2_mnp(u32 clk
, unsigned char* mm
, unsigned char* nn
,
277 for (n
= 2; n
< 15; n
++) {
278 for (m
= 2; m
; m
++) {
279 f
= PM2_REFERENCE_CLOCK
* m
/ n
;
280 if (f
>= 150000 && f
<= 300000) {
281 for ( p
= 0; p
< 5; p
++, f
>>= 1) {
282 curr
= ( clk
> f
) ? clk
- f
: f
- clk
;
283 if ( curr
< delta
) {
295 static void pm2v_mnp(u32 clk
, unsigned char* mm
, unsigned char* nn
,
305 for ( m
= 1; m
< 128; m
++) {
306 for (n
= 2 * m
+ 1; n
; n
++) {
307 for ( p
= 0; p
< 2; p
++) {
308 f
= ( PM2_REFERENCE_CLOCK
>> ( p
+ 1 )) * n
/ m
;
309 if ( clk
> f
- delta
&& clk
< f
+ delta
) {
310 delta
= ( clk
> f
) ? clk
- f
: f
- clk
;
320 static void clear_palette(struct pm2fb_par
* p
) {
324 pm2_WR(p
, PM2R_RD_PALETTE_WRITE_ADDRESS
, 0);
328 pm2_WR(p
, PM2R_RD_PALETTE_DATA
, 0);
329 pm2_WR(p
, PM2R_RD_PALETTE_DATA
, 0);
330 pm2_WR(p
, PM2R_RD_PALETTE_DATA
, 0);
334 static void reset_card(struct pm2fb_par
* p
)
336 if (p
->type
== PM2_TYPE_PERMEDIA2V
)
337 pm2_WR(p
, PM2VR_RD_INDEX_HIGH
, 0);
338 pm2_WR(p
, PM2R_RESET_STATUS
, 0);
340 while (pm2_RD(p
, PM2R_RESET_STATUS
) & PM2F_BEING_RESET
)
343 #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
344 DPRINTK("FIFO disconnect enabled\n");
345 pm2_WR(p
, PM2R_FIFO_DISCON
, 1);
349 /* Restore stashed memory config information from probe */
351 pm2_WR(p
, PM2R_MEM_CONTROL
, p
->mem_control
);
352 pm2_WR(p
, PM2R_BOOT_ADDRESS
, p
->boot_address
);
354 pm2_WR(p
, PM2R_MEM_CONFIG
, p
->mem_config
);
357 static void reset_config(struct pm2fb_par
* p
)
360 pm2_WR(p
, PM2R_CHIP_CONFIG
, pm2_RD(p
, PM2R_CHIP_CONFIG
)&
361 ~(PM2F_VGA_ENABLE
|PM2F_VGA_FIXED
));
362 pm2_WR(p
, PM2R_BYPASS_WRITE_MASK
, ~(0L));
363 pm2_WR(p
, PM2R_FRAMEBUFFER_WRITE_MASK
, ~(0L));
364 pm2_WR(p
, PM2R_FIFO_CONTROL
, 0);
365 pm2_WR(p
, PM2R_APERTURE_ONE
, 0);
366 pm2_WR(p
, PM2R_APERTURE_TWO
, 0);
367 pm2_WR(p
, PM2R_RASTERIZER_MODE
, 0);
368 pm2_WR(p
, PM2R_DELTA_MODE
, PM2F_DELTA_ORDER_RGB
);
369 pm2_WR(p
, PM2R_LB_READ_FORMAT
, 0);
370 pm2_WR(p
, PM2R_LB_WRITE_FORMAT
, 0);
371 pm2_WR(p
, PM2R_LB_READ_MODE
, 0);
372 pm2_WR(p
, PM2R_LB_SOURCE_OFFSET
, 0);
373 pm2_WR(p
, PM2R_FB_SOURCE_OFFSET
, 0);
374 pm2_WR(p
, PM2R_FB_PIXEL_OFFSET
, 0);
375 pm2_WR(p
, PM2R_FB_WINDOW_BASE
, 0);
376 pm2_WR(p
, PM2R_LB_WINDOW_BASE
, 0);
377 pm2_WR(p
, PM2R_FB_SOFT_WRITE_MASK
, ~(0L));
378 pm2_WR(p
, PM2R_FB_HARD_WRITE_MASK
, ~(0L));
379 pm2_WR(p
, PM2R_FB_READ_PIXEL
, 0);
380 pm2_WR(p
, PM2R_DITHER_MODE
, 0);
381 pm2_WR(p
, PM2R_AREA_STIPPLE_MODE
, 0);
382 pm2_WR(p
, PM2R_DEPTH_MODE
, 0);
383 pm2_WR(p
, PM2R_STENCIL_MODE
, 0);
384 pm2_WR(p
, PM2R_TEXTURE_ADDRESS_MODE
, 0);
385 pm2_WR(p
, PM2R_TEXTURE_READ_MODE
, 0);
386 pm2_WR(p
, PM2R_TEXEL_LUT_MODE
, 0);
387 pm2_WR(p
, PM2R_YUV_MODE
, 0);
388 pm2_WR(p
, PM2R_COLOR_DDA_MODE
, 0);
389 pm2_WR(p
, PM2R_TEXTURE_COLOR_MODE
, 0);
390 pm2_WR(p
, PM2R_FOG_MODE
, 0);
391 pm2_WR(p
, PM2R_ALPHA_BLEND_MODE
, 0);
392 pm2_WR(p
, PM2R_LOGICAL_OP_MODE
, 0);
393 pm2_WR(p
, PM2R_STATISTICS_MODE
, 0);
394 pm2_WR(p
, PM2R_SCISSOR_MODE
, 0);
395 pm2_WR(p
, PM2R_FILTER_MODE
, PM2F_SYNCHRONIZATION
);
397 case PM2_TYPE_PERMEDIA2
:
398 pm2_RDAC_WR(p
, PM2I_RD_MODE_CONTROL
, 0); /* no overlay */
399 pm2_RDAC_WR(p
, PM2I_RD_CURSOR_CONTROL
, 0);
400 pm2_RDAC_WR(p
, PM2I_RD_MISC_CONTROL
, PM2F_RD_PALETTE_WIDTH_8
);
402 case PM2_TYPE_PERMEDIA2V
:
403 pm2v_RDAC_WR(p
, PM2VI_RD_MISC_CONTROL
, 1); /* 8bit */
406 pm2_RDAC_WR(p
, PM2I_RD_COLOR_KEY_CONTROL
, 0);
407 pm2_RDAC_WR(p
, PM2I_RD_OVERLAY_KEY
, 0);
408 pm2_RDAC_WR(p
, PM2I_RD_RED_KEY
, 0);
409 pm2_RDAC_WR(p
, PM2I_RD_GREEN_KEY
, 0);
410 pm2_RDAC_WR(p
, PM2I_RD_BLUE_KEY
, 0);
413 static void set_aperture(struct pm2fb_par
* p
, u32 depth
)
416 * The hardware is little-endian. When used in big-endian
417 * hosts, the on-chip aperture settings are used where
418 * possible to translate from host to card byte order.
421 #ifdef __LITTLE_ENDIAN
422 pm2_WR(p
, PM2R_APERTURE_ONE
, PM2F_APERTURE_STANDARD
);
425 case 24: /* RGB->BGR */
427 * We can't use the aperture to translate host to
428 * card byte order here, so we switch to BGR mode
429 * in pm2fb_set_par().
432 pm2_WR(p
, PM2R_APERTURE_ONE
, PM2F_APERTURE_STANDARD
);
434 case 16: /* HL->LH */
435 pm2_WR(p
, PM2R_APERTURE_ONE
, PM2F_APERTURE_HALFWORDSWAP
);
437 case 32: /* RGBA->ABGR */
438 pm2_WR(p
, PM2R_APERTURE_ONE
, PM2F_APERTURE_BYTESWAP
);
443 // We don't use aperture two, so this may be superflous
444 pm2_WR(p
, PM2R_APERTURE_TWO
, PM2F_APERTURE_STANDARD
);
447 static void set_color(struct pm2fb_par
* p
, unsigned char regno
,
448 unsigned char r
, unsigned char g
, unsigned char b
)
451 pm2_WR(p
, PM2R_RD_PALETTE_WRITE_ADDRESS
, regno
);
453 pm2_WR(p
, PM2R_RD_PALETTE_DATA
, r
);
455 pm2_WR(p
, PM2R_RD_PALETTE_DATA
, g
);
457 pm2_WR(p
, PM2R_RD_PALETTE_DATA
, b
);
460 static void set_memclock(struct pm2fb_par
* par
, u32 clk
)
463 unsigned char m
, n
, p
;
466 case PM2_TYPE_PERMEDIA2V
:
467 pm2v_mnp(clk
/2, &m
, &n
, &p
);
469 pm2_WR(par
, PM2VR_RD_INDEX_HIGH
, PM2VI_RD_MCLK_CONTROL
>> 8);
470 pm2v_RDAC_WR(par
, PM2VI_RD_MCLK_CONTROL
, 0);
472 pm2v_RDAC_WR(par
, PM2VI_RD_MCLK_PRESCALE
, m
);
473 pm2v_RDAC_WR(par
, PM2VI_RD_MCLK_FEEDBACK
, n
);
474 pm2v_RDAC_WR(par
, PM2VI_RD_MCLK_POSTSCALE
, p
);
476 pm2v_RDAC_WR(par
, PM2VI_RD_MCLK_CONTROL
, 1);
479 i
&& !(pm2_RDAC_RD(par
, PM2VI_RD_MCLK_CONTROL
) & 2);
482 pm2_WR(par
, PM2VR_RD_INDEX_HIGH
, 0);
484 case PM2_TYPE_PERMEDIA2
:
485 pm2_mnp(clk
, &m
, &n
, &p
);
487 pm2_RDAC_WR(par
, PM2I_RD_MEMORY_CLOCK_3
, 6);
489 pm2_RDAC_WR(par
, PM2I_RD_MEMORY_CLOCK_1
, m
);
490 pm2_RDAC_WR(par
, PM2I_RD_MEMORY_CLOCK_2
, n
);
492 pm2_RDAC_WR(par
, PM2I_RD_MEMORY_CLOCK_3
, 8|p
);
494 pm2_RDAC_RD(par
, PM2I_RD_MEMORY_CLOCK_STATUS
);
497 i
&& !(pm2_RD(par
, PM2R_RD_INDEXED_DATA
) & PM2F_PLL_LOCKED
);
504 static void set_pixclock(struct pm2fb_par
* par
, u32 clk
)
507 unsigned char m
, n
, p
;
510 case PM2_TYPE_PERMEDIA2
:
511 pm2_mnp(clk
, &m
, &n
, &p
);
513 pm2_RDAC_WR(par
, PM2I_RD_PIXEL_CLOCK_A3
, 0);
515 pm2_RDAC_WR(par
, PM2I_RD_PIXEL_CLOCK_A1
, m
);
516 pm2_RDAC_WR(par
, PM2I_RD_PIXEL_CLOCK_A2
, n
);
518 pm2_RDAC_WR(par
, PM2I_RD_PIXEL_CLOCK_A3
, 8|p
);
520 pm2_RDAC_RD(par
, PM2I_RD_PIXEL_CLOCK_STATUS
);
523 i
&& !(pm2_RD(par
, PM2R_RD_INDEXED_DATA
) & PM2F_PLL_LOCKED
);
527 case PM2_TYPE_PERMEDIA2V
:
528 pm2v_mnp(clk
/2, &m
, &n
, &p
);
530 pm2_WR(par
, PM2VR_RD_INDEX_HIGH
, PM2VI_RD_CLK0_PRESCALE
>> 8);
531 pm2v_RDAC_WR(par
, PM2VI_RD_CLK0_PRESCALE
, m
);
532 pm2v_RDAC_WR(par
, PM2VI_RD_CLK0_FEEDBACK
, n
);
533 pm2v_RDAC_WR(par
, PM2VI_RD_CLK0_POSTSCALE
, p
);
534 pm2_WR(par
, PM2VR_RD_INDEX_HIGH
, 0);
539 static void set_video(struct pm2fb_par
* p
, u32 video
) {
545 DPRINTK("video = 0x%x\n", video
);
548 * The hardware cursor needs +vsync to recognise vert retrace.
549 * We may not be using the hardware cursor, but the X Glint
550 * driver may well. So always set +hsync/+vsync and then set
551 * the RAMDAC to invert the sync if necessary.
553 vsync
&= ~(PM2F_HSYNC_MASK
|PM2F_VSYNC_MASK
);
554 vsync
|= PM2F_HSYNC_ACT_HIGH
|PM2F_VSYNC_ACT_HIGH
;
557 pm2_WR(p
, PM2R_VIDEO_CONTROL
, vsync
);
560 case PM2_TYPE_PERMEDIA2
:
561 tmp
= PM2F_RD_PALETTE_WIDTH_8
;
562 if ((video
& PM2F_HSYNC_MASK
) == PM2F_HSYNC_ACT_LOW
)
563 tmp
|= 4; /* invert hsync */
564 if ((video
& PM2F_VSYNC_MASK
) == PM2F_VSYNC_ACT_LOW
)
565 tmp
|= 8; /* invert vsync */
566 pm2_RDAC_WR(p
, PM2I_RD_MISC_CONTROL
, tmp
);
568 case PM2_TYPE_PERMEDIA2V
:
570 if ((video
& PM2F_HSYNC_MASK
) == PM2F_HSYNC_ACT_LOW
)
571 tmp
|= 1; /* invert hsync */
572 if ((video
& PM2F_VSYNC_MASK
) == PM2F_VSYNC_ACT_LOW
)
573 tmp
|= 4; /* invert vsync */
574 pm2v_RDAC_WR(p
, PM2VI_RD_SYNC_CONTROL
, tmp
);
575 pm2v_RDAC_WR(p
, PM2VI_RD_MISC_CONTROL
, 1);
585 * pm2fb_check_var - Optional function. Validates a var passed in.
586 * @var: frame buffer variable screen structure
587 * @info: frame buffer structure that represents a single frame buffer
589 * Checks to see if the hardware supports the state requested by
592 * Returns negative errno on error, or zero on success.
594 static int pm2fb_check_var(struct fb_var_screeninfo
*var
, struct fb_info
*info
)
598 if (var
->bits_per_pixel
!= 8 && var
->bits_per_pixel
!= 16 &&
599 var
->bits_per_pixel
!= 24 && var
->bits_per_pixel
!= 32) {
600 DPRINTK("depth not supported: %u\n", var
->bits_per_pixel
);
604 if (var
->xres
!= var
->xres_virtual
) {
605 DPRINTK("virtual x resolution != physical x resolution not supported\n");
609 if (var
->yres
> var
->yres_virtual
) {
610 DPRINTK("virtual y resolution < physical y resolution not possible\n");
615 DPRINTK("xoffset not supported\n");
619 if ((var
->vmode
& FB_VMODE_MASK
) == FB_VMODE_INTERLACED
) {
620 DPRINTK("interlace not supported\n");
624 var
->xres
= (var
->xres
+ 15) & ~15; /* could sometimes be 8 */
625 lpitch
= var
->xres
* ((var
->bits_per_pixel
+ 7)>>3);
627 if (var
->xres
< 320 || var
->xres
> 1600) {
628 DPRINTK("width not supported: %u\n", var
->xres
);
632 if (var
->yres
< 200 || var
->yres
> 1200) {
633 DPRINTK("height not supported: %u\n", var
->yres
);
637 if (lpitch
* var
->yres_virtual
> info
->fix
.smem_len
) {
638 DPRINTK("no memory for screen (%ux%ux%u)\n",
639 var
->xres
, var
->yres_virtual
, var
->bits_per_pixel
);
643 if (PICOS2KHZ(var
->pixclock
) > PM2_MAX_PIXCLOCK
) {
644 DPRINTK("pixclock too high (%ldKHz)\n", PICOS2KHZ(var
->pixclock
));
648 var
->transp
.offset
= 0;
649 var
->transp
.length
= 0;
650 switch(var
->bits_per_pixel
) {
652 var
->red
.length
= var
->green
.length
= var
->blue
.length
= 8;
655 var
->red
.offset
= 11;
657 var
->green
.offset
= 5;
658 var
->green
.length
= 6;
659 var
->blue
.offset
= 0;
660 var
->blue
.length
= 5;
663 var
->transp
.offset
= 24;
664 var
->transp
.length
= 8;
665 var
->red
.offset
= 16;
666 var
->green
.offset
= 8;
667 var
->blue
.offset
= 0;
668 var
->red
.length
= var
->green
.length
= var
->blue
.length
= 8;
673 var
->blue
.offset
= 16;
675 var
->red
.offset
= 16;
676 var
->blue
.offset
= 0;
678 var
->green
.offset
= 8;
679 var
->red
.length
= var
->green
.length
= var
->blue
.length
= 8;
682 var
->height
= var
->width
= -1;
684 var
->accel_flags
= 0; /* Can't mmap if this is on */
686 DPRINTK("Checking graphics mode at %dx%d depth %d\n",
687 var
->xres
, var
->yres
, var
->bits_per_pixel
);
692 * pm2fb_set_par - Alters the hardware state.
693 * @info: frame buffer structure that represents a single frame buffer
695 * Using the fb_var_screeninfo in fb_info we set the resolution of the
696 * this particular framebuffer.
698 static int pm2fb_set_par(struct fb_info
*info
)
700 struct pm2fb_par
*par
= info
->par
;
702 u32 width
, height
, depth
;
703 u32 hsstart
, hsend
, hbend
, htotal
;
704 u32 vsstart
, vsend
, vbend
, vtotal
;
708 u32 clrmode
= PM2F_RD_COLOR_MODE_RGB
| PM2F_RD_GUI_ACTIVE
;
719 set_memclock(par
, par
->memclock
);
721 width
= (info
->var
.xres_virtual
+ 7) & ~7;
722 height
= info
->var
.yres_virtual
;
723 depth
= (info
->var
.bits_per_pixel
+ 7) & ~7;
724 depth
= (depth
> 32) ? 32 : depth
;
725 data64
= depth
> 8 || par
->type
== PM2_TYPE_PERMEDIA2V
;
727 xres
= (info
->var
.xres
+ 31) & ~31;
728 pixclock
= PICOS2KHZ(info
->var
.pixclock
);
729 if (pixclock
> PM2_MAX_PIXCLOCK
) {
730 DPRINTK("pixclock too high (%uKHz)\n", pixclock
);
734 hsstart
= to3264(info
->var
.right_margin
, depth
, data64
);
735 hsend
= hsstart
+ to3264(info
->var
.hsync_len
, depth
, data64
);
736 hbend
= hsend
+ to3264(info
->var
.left_margin
, depth
, data64
);
737 htotal
= to3264(xres
, depth
, data64
) + hbend
- 1;
738 vsstart
= (info
->var
.lower_margin
)
739 ? info
->var
.lower_margin
- 1
741 vsend
= info
->var
.lower_margin
+ info
->var
.vsync_len
- 1;
742 vbend
= info
->var
.lower_margin
+ info
->var
.vsync_len
+ info
->var
.upper_margin
;
743 vtotal
= info
->var
.yres
+ vbend
- 1;
744 stride
= to3264(width
, depth
, 1);
745 base
= to3264(info
->var
.yoffset
* xres
+ info
->var
.xoffset
, depth
, 1);
747 video
|= PM2F_DATA_64_ENABLE
;
749 if (info
->var
.sync
& FB_SYNC_HOR_HIGH_ACT
) {
751 DPRINTK("ignoring +hsync, using -hsync.\n");
752 video
|= PM2F_HSYNC_ACT_LOW
;
754 video
|= PM2F_HSYNC_ACT_HIGH
;
757 video
|= PM2F_HSYNC_ACT_LOW
;
758 if (info
->var
.sync
& FB_SYNC_VERT_HIGH_ACT
) {
760 DPRINTK("ignoring +vsync, using -vsync.\n");
761 video
|= PM2F_VSYNC_ACT_LOW
;
763 video
|= PM2F_VSYNC_ACT_HIGH
;
766 video
|= PM2F_VSYNC_ACT_LOW
;
767 if ((info
->var
.vmode
& FB_VMODE_MASK
)==FB_VMODE_INTERLACED
) {
768 DPRINTK("interlaced not supported\n");
771 if ((info
->var
.vmode
& FB_VMODE_MASK
)==FB_VMODE_DOUBLE
)
772 video
|= PM2F_LINE_DOUBLE
;
773 if ((info
->var
.activate
& FB_ACTIVATE_MASK
)==FB_ACTIVATE_NOW
)
774 video
|= PM2F_VIDEO_ENABLE
;
778 (depth
== 8) ? FB_VISUAL_PSEUDOCOLOR
: FB_VISUAL_TRUECOLOR
;
779 info
->fix
.line_length
= info
->var
.xres
* depth
/ 8;
780 info
->cmap
.len
= 256;
783 * Settings calculated. Now write them out.
785 if (par
->type
== PM2_TYPE_PERMEDIA2V
) {
787 pm2_WR(par
, PM2VR_RD_INDEX_HIGH
, 0);
790 set_aperture(par
, depth
);
794 pm2_RDAC_WR(par
, PM2I_RD_COLOR_KEY_CONTROL
,
795 ( depth
== 8 ) ? 0 : PM2F_COLOR_KEY_TEST_OFF
);
798 pm2_WR(par
, PM2R_FB_READ_PIXEL
, 0);
802 pm2_WR(par
, PM2R_FB_READ_PIXEL
, 1);
803 clrmode
|= PM2F_RD_TRUECOLOR
| PM2F_RD_PIXELFORMAT_RGB565
;
804 txtmap
= PM2F_TEXTEL_SIZE_16
;
809 pm2_WR(par
, PM2R_FB_READ_PIXEL
, 2);
810 clrmode
|= PM2F_RD_TRUECOLOR
| PM2F_RD_PIXELFORMAT_RGBA8888
;
811 txtmap
= PM2F_TEXTEL_SIZE_32
;
816 pm2_WR(par
, PM2R_FB_READ_PIXEL
, 4);
817 clrmode
|= PM2F_RD_TRUECOLOR
| PM2F_RD_PIXELFORMAT_RGB888
;
818 txtmap
= PM2F_TEXTEL_SIZE_24
;
823 pm2_WR(par
, PM2R_FB_WRITE_MODE
, PM2F_FB_WRITE_ENABLE
);
824 pm2_WR(par
, PM2R_FB_READ_MODE
, partprod(xres
));
825 pm2_WR(par
, PM2R_LB_READ_MODE
, partprod(xres
));
826 pm2_WR(par
, PM2R_TEXTURE_MAP_FORMAT
, txtmap
| partprod(xres
));
827 pm2_WR(par
, PM2R_H_TOTAL
, htotal
);
828 pm2_WR(par
, PM2R_HS_START
, hsstart
);
829 pm2_WR(par
, PM2R_HS_END
, hsend
);
830 pm2_WR(par
, PM2R_HG_END
, hbend
);
831 pm2_WR(par
, PM2R_HB_END
, hbend
);
832 pm2_WR(par
, PM2R_V_TOTAL
, vtotal
);
833 pm2_WR(par
, PM2R_VS_START
, vsstart
);
834 pm2_WR(par
, PM2R_VS_END
, vsend
);
835 pm2_WR(par
, PM2R_VB_END
, vbend
);
836 pm2_WR(par
, PM2R_SCREEN_STRIDE
, stride
);
838 pm2_WR(par
, PM2R_WINDOW_ORIGIN
, 0);
839 pm2_WR(par
, PM2R_SCREEN_SIZE
, (height
<< 16) | width
);
840 pm2_WR(par
, PM2R_SCISSOR_MODE
, PM2F_SCREEN_SCISSOR_ENABLE
);
842 pm2_WR(par
, PM2R_SCREEN_BASE
, base
);
844 set_video(par
, video
);
847 case PM2_TYPE_PERMEDIA2
:
848 pm2_RDAC_WR(par
, PM2I_RD_COLOR_MODE
, clrmode
);
850 case PM2_TYPE_PERMEDIA2V
:
851 pm2v_RDAC_WR(par
, PM2VI_RD_PIXEL_SIZE
, pixsize
);
852 pm2v_RDAC_WR(par
, PM2VI_RD_COLOR_FORMAT
, clrformat
);
855 set_pixclock(par
, pixclock
);
856 DPRINTK("Setting graphics mode at %dx%d depth %d\n",
857 info
->var
.xres
, info
->var
.yres
, info
->var
.bits_per_pixel
);
862 * pm2fb_setcolreg - Sets a color register.
863 * @regno: boolean, 0 copy local, 1 get_user() function
864 * @red: frame buffer colormap structure
865 * @green: The green value which can be up to 16 bits wide
866 * @blue: The blue value which can be up to 16 bits wide.
867 * @transp: If supported the alpha value which can be up to 16 bits wide.
868 * @info: frame buffer info structure
870 * Set a single color register. The values supplied have a 16 bit
871 * magnitude which needs to be scaled in this function for the hardware.
872 * Pretty much a direct lift from tdfxfb.c.
874 * Returns negative errno on error, or zero on success.
876 static int pm2fb_setcolreg(unsigned regno
, unsigned red
, unsigned green
,
877 unsigned blue
, unsigned transp
,
878 struct fb_info
*info
)
880 struct pm2fb_par
*par
= info
->par
;
882 if (regno
>= info
->cmap
.len
) /* no. of hw registers */
885 * Program hardware... do anything you want with transp
888 /* grayscale works only partially under directcolor */
889 if (info
->var
.grayscale
) {
890 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
891 red
= green
= blue
= (red
* 77 + green
* 151 + blue
* 28) >> 8;
895 * var->{color}.offset contains start of bitfield
896 * var->{color}.length contains length of bitfield
897 * {hardwarespecific} contains width of DAC
898 * cmap[X] is programmed to
899 * (X << red.offset) | (X << green.offset) | (X << blue.offset)
900 * RAMDAC[X] is programmed to (red, green, blue)
903 * uses offset = 0 && length = DAC register width.
904 * var->{color}.offset is 0
905 * var->{color}.length contains widht of DAC
907 * DAC[X] is programmed to (red, green, blue)
909 * does not use RAMDAC (usually has 3 of them).
910 * var->{color}.offset contains start of bitfield
911 * var->{color}.length contains length of bitfield
912 * cmap is programmed to
913 * (red << red.offset) | (green << green.offset) |
914 * (blue << blue.offset) | (transp << transp.offset)
915 * RAMDAC does not exist
917 #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
918 switch (info
->fix
.visual
) {
919 case FB_VISUAL_TRUECOLOR
:
920 case FB_VISUAL_PSEUDOCOLOR
:
921 red
= CNVT_TOHW(red
, info
->var
.red
.length
);
922 green
= CNVT_TOHW(green
, info
->var
.green
.length
);
923 blue
= CNVT_TOHW(blue
, info
->var
.blue
.length
);
924 transp
= CNVT_TOHW(transp
, info
->var
.transp
.length
);
926 case FB_VISUAL_DIRECTCOLOR
:
927 /* example here assumes 8 bit DAC. Might be different
928 * for your hardware */
929 red
= CNVT_TOHW(red
, 8);
930 green
= CNVT_TOHW(green
, 8);
931 blue
= CNVT_TOHW(blue
, 8);
932 /* hey, there is bug in transp handling... */
933 transp
= CNVT_TOHW(transp
, 8);
937 /* Truecolor has hardware independent palette */
938 if (info
->fix
.visual
== FB_VISUAL_TRUECOLOR
) {
944 v
= (red
<< info
->var
.red
.offset
) |
945 (green
<< info
->var
.green
.offset
) |
946 (blue
<< info
->var
.blue
.offset
) |
947 (transp
<< info
->var
.transp
.offset
);
949 switch (info
->var
.bits_per_pixel
) {
955 par
->palette
[regno
] = v
;
960 else if (info
->fix
.visual
== FB_VISUAL_PSEUDOCOLOR
)
961 set_color(par
, regno
, red
, green
, blue
);
967 * pm2fb_pan_display - Pans the display.
968 * @var: frame buffer variable screen structure
969 * @info: frame buffer structure that represents a single frame buffer
971 * Pan (or wrap, depending on the `vmode' field) the display using the
972 * `xoffset' and `yoffset' fields of the `var' structure.
973 * If the values don't fit, return -EINVAL.
975 * Returns negative errno on error, or zero on success.
978 static int pm2fb_pan_display(struct fb_var_screeninfo
*var
,
979 struct fb_info
*info
)
981 struct pm2fb_par
*p
= info
->par
;
986 xres
= (var
->xres
+ 31) & ~31;
987 depth
= (var
->bits_per_pixel
+ 7) & ~7;
988 depth
= (depth
> 32) ? 32 : depth
;
989 base
= to3264(var
->yoffset
* xres
+ var
->xoffset
, depth
, 1);
991 pm2_WR(p
, PM2R_SCREEN_BASE
, base
);
996 * pm2fb_blank - Blanks the display.
997 * @blank_mode: the blank mode we want.
998 * @info: frame buffer structure that represents a single frame buffer
1000 * Blank the screen if blank_mode != 0, else unblank. Return 0 if
1001 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
1002 * video mode which doesn't support it. Implements VESA suspend
1003 * and powerdown modes on hardware that supports disabling hsync/vsync:
1004 * blank_mode == 2: suspend vsync
1005 * blank_mode == 3: suspend hsync
1006 * blank_mode == 4: powerdown
1008 * Returns negative errno on error, or zero on success.
1011 static int pm2fb_blank(int blank_mode
, struct fb_info
*info
)
1013 struct pm2fb_par
*par
= info
->par
;
1014 u32 video
= par
->video
;
1016 DPRINTK("blank_mode %d\n", blank_mode
);
1018 switch (blank_mode
) {
1019 case FB_BLANK_UNBLANK
:
1021 video
|= PM2F_VIDEO_ENABLE
;
1023 case FB_BLANK_NORMAL
:
1025 video
&= ~PM2F_VIDEO_ENABLE
;
1027 case FB_BLANK_VSYNC_SUSPEND
:
1029 video
&= ~(PM2F_VSYNC_MASK
| PM2F_BLANK_LOW
);
1031 case FB_BLANK_HSYNC_SUSPEND
:
1033 video
&= ~(PM2F_HSYNC_MASK
| PM2F_BLANK_LOW
);
1035 case FB_BLANK_POWERDOWN
:
1036 /* HSync: Off, VSync: Off */
1037 video
&= ~(PM2F_VSYNC_MASK
| PM2F_HSYNC_MASK
| PM2F_BLANK_LOW
);
1040 set_video(par
, video
);
1044 /* ------------ Hardware Independent Functions ------------ */
1047 * Frame buffer operations
1050 static struct fb_ops pm2fb_ops
= {
1051 .owner
= THIS_MODULE
,
1052 .fb_check_var
= pm2fb_check_var
,
1053 .fb_set_par
= pm2fb_set_par
,
1054 .fb_setcolreg
= pm2fb_setcolreg
,
1055 .fb_blank
= pm2fb_blank
,
1056 .fb_pan_display
= pm2fb_pan_display
,
1057 .fb_fillrect
= cfb_fillrect
,
1058 .fb_copyarea
= cfb_copyarea
,
1059 .fb_imageblit
= cfb_imageblit
,
1068 * Device initialisation
1070 * Initialise and allocate resource for PCI device.
1072 * @param pdev PCI device.
1073 * @param id PCI device ID.
1075 static int __devinit
pm2fb_probe(struct pci_dev
*pdev
,
1076 const struct pci_device_id
*id
)
1078 struct pm2fb_par
*default_par
;
1079 struct fb_info
*info
;
1080 int err
, err_retval
= -ENXIO
;
1082 err
= pci_enable_device(pdev
);
1084 printk(KERN_WARNING
"pm2fb: Can't enable pdev: %d\n", err
);
1088 info
= framebuffer_alloc(sizeof(struct pm2fb_par
), &pdev
->dev
);
1091 default_par
= info
->par
;
1093 switch (pdev
->device
) {
1094 case PCI_DEVICE_ID_TI_TVP4020
:
1095 strcpy(pm2fb_fix
.id
, "TVP4020");
1096 default_par
->type
= PM2_TYPE_PERMEDIA2
;
1098 case PCI_DEVICE_ID_3DLABS_PERMEDIA2
:
1099 strcpy(pm2fb_fix
.id
, "Permedia2");
1100 default_par
->type
= PM2_TYPE_PERMEDIA2
;
1102 case PCI_DEVICE_ID_3DLABS_PERMEDIA2V
:
1103 strcpy(pm2fb_fix
.id
, "Permedia2v");
1104 default_par
->type
= PM2_TYPE_PERMEDIA2V
;
1108 pm2fb_fix
.mmio_start
= pci_resource_start(pdev
, 0);
1109 pm2fb_fix
.mmio_len
= PM2_REGS_SIZE
;
1111 #if defined(__BIG_ENDIAN)
1113 * PM2 has a 64k register file, mapped twice in 128k. Lower
1114 * map is little-endian, upper map is big-endian.
1116 pm2fb_fix
.mmio_start
+= PM2_REGS_SIZE
;
1117 DPRINTK("Adjusting register base for big-endian.\n");
1119 DPRINTK("Register base at 0x%lx\n", pm2fb_fix
.mmio_start
);
1121 /* Registers - request region and map it. */
1122 if ( !request_mem_region(pm2fb_fix
.mmio_start
, pm2fb_fix
.mmio_len
,
1123 "pm2fb regbase") ) {
1124 printk(KERN_WARNING
"pm2fb: Can't reserve regbase.\n");
1125 goto err_exit_neither
;
1127 default_par
->v_regs
=
1128 ioremap_nocache(pm2fb_fix
.mmio_start
, pm2fb_fix
.mmio_len
);
1129 if ( !default_par
->v_regs
) {
1130 printk(KERN_WARNING
"pm2fb: Can't remap %s register area.\n",
1132 release_mem_region(pm2fb_fix
.mmio_start
, pm2fb_fix
.mmio_len
);
1133 goto err_exit_neither
;
1136 /* Stash away memory register info for use when we reset the board */
1137 default_par
->mem_control
= pm2_RD(default_par
, PM2R_MEM_CONTROL
);
1138 default_par
->boot_address
= pm2_RD(default_par
, PM2R_BOOT_ADDRESS
);
1139 default_par
->mem_config
= pm2_RD(default_par
, PM2R_MEM_CONFIG
);
1140 DPRINTK("MemControl 0x%x BootAddress 0x%x MemConfig 0x%x\n",
1141 default_par
->mem_control
, default_par
->boot_address
,
1142 default_par
->mem_config
);
1144 default_par
->memclock
= CVPPC_MEMCLOCK
;
1145 if(default_par
->mem_control
== 0 &&
1146 default_par
->boot_address
== 0x31 &&
1147 default_par
->mem_config
== 0x259fffff) {
1148 default_par
->mem_control
=0;
1149 default_par
->boot_address
=0x20;
1150 default_par
->mem_config
=0xe6002021;
1151 if (pdev
->subsystem_vendor
== 0x1048 &&
1152 pdev
->subsystem_device
== 0x0a31) {
1153 DPRINTK("subsystem_vendor: %04x, subsystem_device: %04x\n",
1154 pdev
->subsystem_vendor
, pdev
->subsystem_device
);
1155 DPRINTK("We have not been initialized by VGA BIOS "
1156 "and are running on an Elsa Winner 2000 Office\n");
1157 DPRINTK("Initializing card timings manually...\n");
1158 default_par
->memclock
=70000;
1160 if (pdev
->subsystem_vendor
== 0x3d3d &&
1161 pdev
->subsystem_device
== 0x0100) {
1162 DPRINTK("subsystem_vendor: %04x, subsystem_device: %04x\n",
1163 pdev
->subsystem_vendor
, pdev
->subsystem_device
);
1164 DPRINTK("We have not been initialized by VGA BIOS "
1165 "and are running on an 3dlabs reference board\n");
1166 DPRINTK("Initializing card timings manually...\n");
1167 default_par
->memclock
=70000;
1171 /* Now work out how big lfb is going to be. */
1172 switch(default_par
->mem_config
& PM2F_MEM_CONFIG_RAM_MASK
) {
1173 case PM2F_MEM_BANKS_1
:
1174 default_par
->fb_size
=0x200000;
1176 case PM2F_MEM_BANKS_2
:
1177 default_par
->fb_size
=0x400000;
1179 case PM2F_MEM_BANKS_3
:
1180 default_par
->fb_size
=0x600000;
1182 case PM2F_MEM_BANKS_4
:
1183 default_par
->fb_size
=0x800000;
1186 pm2fb_fix
.smem_start
= pci_resource_start(pdev
, 1);
1187 pm2fb_fix
.smem_len
= default_par
->fb_size
;
1189 /* Linear frame buffer - request region and map it. */
1190 if ( !request_mem_region(pm2fb_fix
.smem_start
, pm2fb_fix
.smem_len
,
1192 printk(KERN_WARNING
"pm2fb: Can't reserve smem.\n");
1195 info
->screen_base
= default_par
->v_fb
=
1196 ioremap_nocache(pm2fb_fix
.smem_start
, pm2fb_fix
.smem_len
);
1197 if ( !default_par
->v_fb
) {
1198 printk(KERN_WARNING
"pm2fb: Can't ioremap smem area.\n");
1199 release_mem_region(pm2fb_fix
.smem_start
, pm2fb_fix
.smem_len
);
1203 info
->fbops
= &pm2fb_ops
;
1204 info
->fix
= pm2fb_fix
;
1205 info
->pseudo_palette
= default_par
->palette
;
1206 info
->flags
= FBINFO_DEFAULT
|
1207 FBINFO_HWACCEL_YPAN
;
1210 mode
= "640x480@60";
1212 err
= fb_find_mode(&info
->var
, info
, mode
, NULL
, 0, NULL
, 8);
1213 if (!err
|| err
== 4)
1214 info
->var
= pm2fb_var
;
1216 if (fb_alloc_cmap(&info
->cmap
, 256, 0) < 0)
1219 if (register_framebuffer(info
) < 0)
1222 printk(KERN_INFO
"fb%d: %s frame buffer device, memory = %dK.\n",
1223 info
->node
, info
->fix
.id
, default_par
->fb_size
/ 1024);
1228 pci_set_drvdata(pdev
, info
);
1233 fb_dealloc_cmap(&info
->cmap
);
1235 iounmap(info
->screen_base
);
1236 release_mem_region(pm2fb_fix
.smem_start
, pm2fb_fix
.smem_len
);
1238 iounmap(default_par
->v_regs
);
1239 release_mem_region(pm2fb_fix
.mmio_start
, pm2fb_fix
.mmio_len
);
1241 framebuffer_release(info
);
1248 * Release all device resources.
1250 * @param pdev PCI device to clean up.
1252 static void __devexit
pm2fb_remove(struct pci_dev
*pdev
)
1254 struct fb_info
* info
= pci_get_drvdata(pdev
);
1255 struct fb_fix_screeninfo
* fix
= &info
->fix
;
1256 struct pm2fb_par
*par
= info
->par
;
1258 unregister_framebuffer(info
);
1260 iounmap(info
->screen_base
);
1261 release_mem_region(fix
->smem_start
, fix
->smem_len
);
1262 iounmap(par
->v_regs
);
1263 release_mem_region(fix
->mmio_start
, fix
->mmio_len
);
1265 pci_set_drvdata(pdev
, NULL
);
1269 static struct pci_device_id pm2fb_id_table
[] = {
1270 { PCI_VENDOR_ID_TI
, PCI_DEVICE_ID_TI_TVP4020
,
1271 PCI_ANY_ID
, PCI_ANY_ID
, PCI_BASE_CLASS_DISPLAY
<< 16,
1273 { PCI_VENDOR_ID_3DLABS
, PCI_DEVICE_ID_3DLABS_PERMEDIA2
,
1274 PCI_ANY_ID
, PCI_ANY_ID
, PCI_BASE_CLASS_DISPLAY
<< 16,
1276 { PCI_VENDOR_ID_3DLABS
, PCI_DEVICE_ID_3DLABS_PERMEDIA2V
,
1277 PCI_ANY_ID
, PCI_ANY_ID
, PCI_BASE_CLASS_DISPLAY
<< 16,
1279 { PCI_VENDOR_ID_3DLABS
, PCI_DEVICE_ID_3DLABS_PERMEDIA2V
,
1280 PCI_ANY_ID
, PCI_ANY_ID
, PCI_CLASS_NOT_DEFINED_VGA
<< 8,
1285 static struct pci_driver pm2fb_driver
= {
1287 .id_table
= pm2fb_id_table
,
1288 .probe
= pm2fb_probe
,
1289 .remove
= __devexit_p(pm2fb_remove
),
1292 MODULE_DEVICE_TABLE(pci
, pm2fb_id_table
);
1297 * Parse user speficied options.
1299 * This is, comma-separated options following `video=pm2fb:'.
1301 static int __init
pm2fb_setup(char *options
)
1305 if (!options
|| !*options
)
1308 while ((this_opt
= strsep(&options
, ",")) != NULL
) {
1311 if(!strcmp(this_opt
, "lowhsync")) {
1313 } else if(!strcmp(this_opt
, "lowvsync")) {
1324 static int __init
pm2fb_init(void)
1327 char *option
= NULL
;
1329 if (fb_get_options("pm2fb", &option
))
1331 pm2fb_setup(option
);
1334 return pci_register_driver(&pm2fb_driver
);
1337 module_init(pm2fb_init
);
1344 static void __exit
pm2fb_exit(void)
1346 pci_unregister_driver(&pm2fb_driver
);
1351 module_exit(pm2fb_exit
);
1353 module_param(mode
, charp
, 0);
1354 MODULE_PARM_DESC(mode
, "Preferred video mode e.g. '648x480-8@60'");
1355 module_param(lowhsync
, bool, 0);
1356 MODULE_PARM_DESC(lowhsync
, "Force horizontal sync low regardless of mode");
1357 module_param(lowvsync
, bool, 0);
1358 MODULE_PARM_DESC(lowvsync
, "Force vertical sync low regardless of mode");
1360 MODULE_AUTHOR("Jim Hague <jim.hague@acm.org>");
1361 MODULE_DESCRIPTION("Permedia2 framebuffer device driver");
1362 MODULE_LICENSE("GPL");