drivers/net/ixgbe/ixgbe.h

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #ifndef _IXGBE_H_
  29 #define _IXGBE_H_
  30
  31 #include <linux/types.h>
  32 #include <linux/pci.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/inet_lro.h>
  35 #include <linux/aer.h>
  36
  37 #include "ixgbe_type.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_dcb.h"
  40 #ifdef CONFIG_IXGBE_DCA
  41 #include <linux/dca.h>
  42 #endif
  43
  44 #define PFX "ixgbe: "
  45 #define DPRINTK(nlevel, klevel, fmt, args...) \
  46         ((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
  47         printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
  48                 __func__ , ## args)))
  49
  50 /* TX/RX descriptor defines */
  51 #define IXGBE_DEFAULT_TXD                  1024
  52 #define IXGBE_MAX_TXD                      4096
  53 #define IXGBE_MIN_TXD                        64
  54
  55 #define IXGBE_DEFAULT_RXD                  1024
  56 #define IXGBE_MAX_RXD                      4096
  57 #define IXGBE_MIN_RXD                        64
  58
  59 /* flow control */
  60 #define IXGBE_DEFAULT_FCRTL             0x10000
  61 #define IXGBE_MIN_FCRTL                    0x40
  62 #define IXGBE_MAX_FCRTL                 0x7FF80
  63 #define IXGBE_DEFAULT_FCRTH             0x20000
  64 #define IXGBE_MIN_FCRTH                   0x600
  65 #define IXGBE_MAX_FCRTH                 0x7FFF0
  66 #define IXGBE_DEFAULT_FCPAUSE            0xFFFF
  67 #define IXGBE_MIN_FCPAUSE                     0
  68 #define IXGBE_MAX_FCPAUSE                0xFFFF
  69
  70 /* Supported Rx Buffer Sizes */
  71 #define IXGBE_RXBUFFER_64    64     /* Used for packet split */
  72 #define IXGBE_RXBUFFER_128   128    /* Used for packet split */
  73 #define IXGBE_RXBUFFER_256   256    /* Used for packet split */
  74 #define IXGBE_RXBUFFER_2048  2048
  75
  76 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
  77
  78 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
  79
  80 /* How many Rx Buffers do we bundle into one write to the hardware ? */
  81 #define IXGBE_RX_BUFFER_WRITE   16      /* Must be power of 2 */
  82
  83 #define IXGBE_TX_FLAGS_CSUM             (u32)(1)
  84 #define IXGBE_TX_FLAGS_VLAN             (u32)(1 << 1)
  85 #define IXGBE_TX_FLAGS_TSO              (u32)(1 << 2)
  86 #define IXGBE_TX_FLAGS_IPV4             (u32)(1 << 3)
  87 #define IXGBE_TX_FLAGS_VLAN_MASK        0xffff0000
  88 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK   0x0000e000
  89 #define IXGBE_TX_FLAGS_VLAN_SHIFT       16
  90
  91 #define IXGBE_MAX_LRO_DESCRIPTORS       8
  92 #define IXGBE_MAX_LRO_AGGREGATE         32
  93
  94 /* wrapper around a pointer to a socket buffer,
  95  * so a DMA handle can be stored along with the buffer */
  96 struct ixgbe_tx_buffer {
  97         struct sk_buff *skb;
  98         dma_addr_t dma;
  99         unsigned long time_stamp;
 100         u16 length;
 101         u16 next_to_watch;
 102 };
 103
 104 struct ixgbe_rx_buffer {
 105         struct sk_buff *skb;
 106         dma_addr_t dma;
 107         struct page *page;
 108         dma_addr_t page_dma;
 109         unsigned int page_offset;
 110 };
 111
 112 struct ixgbe_queue_stats {
 113         u64 packets;
 114         u64 bytes;
 115 };
 116
 117 struct ixgbe_ring {
 118         void *desc;                     /* descriptor ring memory */
 119         dma_addr_t dma;                 /* phys. address of descriptor ring */
 120         unsigned int size;              /* length in bytes */
 121         unsigned int count;             /* amount of descriptors */
 122         unsigned int next_to_use;
 123         unsigned int next_to_clean;
 124
 125         int queue_index; /* needed for multiqueue queue management */
 126         union {
 127                 struct ixgbe_tx_buffer *tx_buffer_info;
 128                 struct ixgbe_rx_buffer *rx_buffer_info;
 129         };
 130
 131         u16 head;
 132         u16 tail;
 133
 134         unsigned int total_bytes;
 135         unsigned int total_packets;
 136
 137         u16 reg_idx; /* holds the special value that gets the hardware register
 138                       * offset associated with this ring, which is different
 139                       * for DCB and RSS modes */
 140
 141 #ifdef CONFIG_IXGBE_DCA
 142         /* cpu for tx queue */
 143         int cpu;
 144 #endif
 145         struct net_lro_mgr lro_mgr;
 146         bool lro_used;
 147         struct ixgbe_queue_stats stats;
 148         u16 v_idx; /* maps directly to the index for this ring in the hardware
 149                    * vector array, can also be used for finding the bit in EICR
 150                    * and friends that represents the vector for this ring */
 151
 152
 153         u16 work_limit;                /* max work per interrupt */
 154         u16 rx_buf_len;
 155 };
 156
 157 #define RING_F_DCB  0
 158 #define RING_F_VMDQ 1
 159 #define RING_F_RSS  2
 160 #define IXGBE_MAX_DCB_INDICES   8
 161 #define IXGBE_MAX_RSS_INDICES  16
 162 #define IXGBE_MAX_VMDQ_INDICES 16
 163 struct ixgbe_ring_feature {
 164         int indices;
 165         int mask;
 166 };
 167
 168 #define MAX_RX_QUEUES 64
 169 #define MAX_TX_QUEUES 32
 170
 171 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
 172                               ? 8 : 1)
 173 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
 174
 175 /* MAX_MSIX_Q_VECTORS of these are allocated,
 176  * but we only use one per queue-specific vector.
 177  */
 178 struct ixgbe_q_vector {
 179         struct ixgbe_adapter *adapter;
 180         struct napi_struct napi;
 181         DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
 182         DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
 183         u8 rxr_count;     /* Rx ring count assigned to this vector */
 184         u8 txr_count;     /* Tx ring count assigned to this vector */
 185         u8 tx_itr;
 186         u8 rx_itr;
 187         u32 eitr;
 188 };
 189
 190 /* Helper macros to switch between ints/sec and what the register uses.
 191  * And yes, it's the same math going both ways.
 192  */
 193 #define EITR_INTS_PER_SEC_TO_REG(_eitr) \
 194         ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 0)
 195 #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
 196
 197 #define IXGBE_DESC_UNUSED(R) \
 198         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 199         (R)->next_to_clean - (R)->next_to_use - 1)
 200
 201 #define IXGBE_RX_DESC_ADV(R, i)     \
 202         (&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
 203 #define IXGBE_TX_DESC_ADV(R, i)     \
 204         (&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
 205 #define IXGBE_TX_CTXTDESC_ADV(R, i)         \
 206         (&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
 207
 208 #define IXGBE_MAX_JUMBO_FRAME_SIZE        16128
 209
 210 #define OTHER_VECTOR 1
 211 #define NON_Q_VECTORS (OTHER_VECTOR)
 212
 213 #define MAX_MSIX_Q_VECTORS 16
 214 #define MIN_MSIX_Q_VECTORS 2
 215 #define MAX_MSIX_COUNT (MAX_MSIX_Q_VECTORS + NON_Q_VECTORS)
 216 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
 217
 218 /* board specific private data structure */
 219 struct ixgbe_adapter {
 220         struct timer_list watchdog_timer;
 221         struct vlan_group *vlgrp;
 222         u16 bd_number;
 223         struct work_struct reset_task;
 224         struct ixgbe_q_vector q_vector[MAX_MSIX_Q_VECTORS];
 225         char name[MAX_MSIX_COUNT][IFNAMSIZ + 5];
 226         struct ixgbe_dcb_config dcb_cfg;
 227         struct ixgbe_dcb_config temp_dcb_cfg;
 228         u8 dcb_set_bitmap;
 229
 230         /* Interrupt Throttle Rate */
 231         u32 itr_setting;
 232         u16 eitr_low;
 233         u16 eitr_high;
 234
 235         /* TX */
 236         struct ixgbe_ring *tx_ring;     /* One per active queue */
 237         int num_tx_queues;
 238         u64 restart_queue;
 239         u64 hw_csum_tx_good;
 240         u64 lsc_int;
 241         u64 hw_tso_ctxt;
 242         u64 hw_tso6_ctxt;
 243         u32 tx_timeout_count;
 244         bool detect_tx_hung;
 245
 246         /* RX */
 247         struct ixgbe_ring *rx_ring;     /* One per active queue */
 248         int num_rx_queues;
 249         u64 hw_csum_rx_error;
 250         u64 hw_csum_rx_good;
 251         u64 non_eop_descs;
 252         int num_msix_vectors;
 253         struct ixgbe_ring_feature ring_feature[3];
 254         struct msix_entry *msix_entries;
 255
 256         u64 rx_hdr_split;
 257         u32 alloc_rx_page_failed;
 258         u32 alloc_rx_buff_failed;
 259
 260         /* Some features need tri-state capability,
 261          * thus the additional *_CAPABLE flags.
 262          */
 263         u32 flags;
 264 #define IXGBE_FLAG_RX_CSUM_ENABLED              (u32)(1)
 265 #define IXGBE_FLAG_MSI_CAPABLE                  (u32)(1 << 1)
 266 #define IXGBE_FLAG_MSI_ENABLED                  (u32)(1 << 2)
 267 #define IXGBE_FLAG_MSIX_CAPABLE                 (u32)(1 << 3)
 268 #define IXGBE_FLAG_MSIX_ENABLED                 (u32)(1 << 4)
 269 #define IXGBE_FLAG_RX_1BUF_CAPABLE              (u32)(1 << 6)
 270 #define IXGBE_FLAG_RX_PS_CAPABLE                (u32)(1 << 7)
 271 #define IXGBE_FLAG_RX_PS_ENABLED                (u32)(1 << 8)
 272 #define IXGBE_FLAG_IN_NETPOLL                   (u32)(1 << 9)
 273 #define IXGBE_FLAG_DCA_ENABLED                  (u32)(1 << 10)
 274 #define IXGBE_FLAG_DCA_CAPABLE                  (u32)(1 << 11)
 275 #define IXGBE_FLAG_IMIR_ENABLED                 (u32)(1 << 12)
 276 #define IXGBE_FLAG_MQ_CAPABLE                   (u32)(1 << 13)
 277 #define IXGBE_FLAG_RSS_ENABLED                  (u32)(1 << 16)
 278 #define IXGBE_FLAG_RSS_CAPABLE                  (u32)(1 << 17)
 279 #define IXGBE_FLAG_VMDQ_CAPABLE                 (u32)(1 << 18)
 280 #define IXGBE_FLAG_VMDQ_ENABLED                 (u32)(1 << 19)
 281 #define IXGBE_FLAG_FAN_FAIL_CAPABLE             (u32)(1 << 20)
 282 #define IXGBE_FLAG_NEED_LINK_UPDATE             (u32)(1 << 22)
 283 #define IXGBE_FLAG_IN_WATCHDOG_TASK             (u32)(1 << 23)
 284 #define IXGBE_FLAG_DCB_ENABLED                  (u32)(1 << 24)
 285
 286 /* default to trying for four seconds */
 287 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
 288
 289         /* OS defined structs */
 290         struct net_device *netdev;
 291         struct pci_dev *pdev;
 292         struct net_device_stats net_stats;
 293
 294         /* structs defined in ixgbe_hw.h */
 295         struct ixgbe_hw hw;
 296         u16 msg_enable;
 297         struct ixgbe_hw_stats stats;
 298
 299         /* Interrupt Throttle Rate */
 300         u32 eitr_param;
 301
 302         unsigned long state;
 303         u64 tx_busy;
 304         u64 lro_aggregated;
 305         u64 lro_flushed;
 306         u64 lro_no_desc;
 307         unsigned int tx_ring_count;
 308         unsigned int rx_ring_count;
 309
 310         u32 link_speed;
 311         bool link_up;
 312         unsigned long link_check_timeout;
 313
 314         struct work_struct watchdog_task;
 315         struct work_struct sfp_task;
 316         struct timer_list sfp_timer;
 317 };
 318
 319 enum ixbge_state_t {
 320         __IXGBE_TESTING,
 321         __IXGBE_RESETTING,
 322         __IXGBE_DOWN,
 323         __IXGBE_SFP_MODULE_NOT_FOUND
 324 };
 325
 326 enum ixgbe_boards {
 327         board_82598,
 328 };
 329
 330 extern struct ixgbe_info ixgbe_82598_info;
 331 #ifdef CONFIG_IXGBE_DCB
 332 extern struct dcbnl_rtnl_ops dcbnl_ops;
 333 extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
 334                               struct ixgbe_dcb_config *dst_dcb_cfg,
 335                               int tc_max);
 336 #endif
 337
 338 extern char ixgbe_driver_name[];
 339 extern const char ixgbe_driver_version[];
 340
 341 extern int ixgbe_up(struct ixgbe_adapter *adapter);
 342 extern void ixgbe_down(struct ixgbe_adapter *adapter);
 343 extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
 344 extern void ixgbe_reset(struct ixgbe_adapter *adapter);
 345 extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
 346 extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
 347 extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
 348 extern void ixgbe_free_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
 349 extern void ixgbe_free_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
 350 extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
 351 extern void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter);
 352 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
 353 void ixgbe_napi_add_all(struct ixgbe_adapter *adapter);
 354 void ixgbe_napi_del_all(struct ixgbe_adapter *adapter);
 355
 356 #endif /* _IXGBE_H_ */