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rt2x00: Add per-interface structure
[firewire-audio.git] / drivers / net / wireless / rt2x00 / rt61pci.h
blobd291c0fe405c3a085b0bd76555af84befb6cc264
1 /*
2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt61pci
23 Abstract: Data structures and registers for the rt61pci module.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
27 #ifndef RT61PCI_H
28 #define RT61PCI_H
29
30 /*
31 * RF chip defines.
32 */
33 #define RF5225 0x0001
34 #define RF5325 0x0002
35 #define RF2527 0x0003
36 #define RF2529 0x0004
37
38 /*
39 * Signal information.
40 * Defaul offset is required for RSSI <-> dBm conversion.
41 */
42 #define MAX_SIGNAL 100
43 #define MAX_RX_SSI -1
44 #define DEFAULT_RSSI_OFFSET 120
45
46 /*
47 * Register layout information.
48 */
49 #define CSR_REG_BASE 0x3000
50 #define CSR_REG_SIZE 0x04b0
51 #define EEPROM_BASE 0x0000
52 #define EEPROM_SIZE 0x0100
53 #define BBP_SIZE 0x0080
54 #define RF_SIZE 0x0014
55
56 /*
57 * PCI registers.
58 */
59
60 /*
61 * PCI Configuration Header
62 */
63 #define PCI_CONFIG_HEADER_VENDOR 0x0000
64 #define PCI_CONFIG_HEADER_DEVICE 0x0002
65
66 /*
67 * HOST_CMD_CSR: For HOST to interrupt embedded processor
68 */
69 #define HOST_CMD_CSR 0x0008
70 #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x0000007f)
71 #define HOST_CMD_CSR_INTERRUPT_MCU FIELD32(0x00000080)
72
73 /*
74 * MCU_CNTL_CSR
75 * SELECT_BANK: Select 8051 program bank.
76 * RESET: Enable 8051 reset state.
77 * READY: Ready state for 8051.
78 */
79 #define MCU_CNTL_CSR 0x000c
80 #define MCU_CNTL_CSR_SELECT_BANK FIELD32(0x00000001)
81 #define MCU_CNTL_CSR_RESET FIELD32(0x00000002)
82 #define MCU_CNTL_CSR_READY FIELD32(0x00000004)
83
84 /*
85 * SOFT_RESET_CSR
86 */
87 #define SOFT_RESET_CSR 0x0010
88
89 /*
90 * MCU_INT_SOURCE_CSR: MCU interrupt source/mask register.
91 */
92 #define MCU_INT_SOURCE_CSR 0x0014
93 #define MCU_INT_SOURCE_CSR_0 FIELD32(0x00000001)
94 #define MCU_INT_SOURCE_CSR_1 FIELD32(0x00000002)
95 #define MCU_INT_SOURCE_CSR_2 FIELD32(0x00000004)
96 #define MCU_INT_SOURCE_CSR_3 FIELD32(0x00000008)
97 #define MCU_INT_SOURCE_CSR_4 FIELD32(0x00000010)
98 #define MCU_INT_SOURCE_CSR_5 FIELD32(0x00000020)
99 #define MCU_INT_SOURCE_CSR_6 FIELD32(0x00000040)
100 #define MCU_INT_SOURCE_CSR_7 FIELD32(0x00000080)
101 #define MCU_INT_SOURCE_CSR_TWAKEUP FIELD32(0x00000100)
102 #define MCU_INT_SOURCE_CSR_TBTT_EXPIRE FIELD32(0x00000200)
103
104 /*
105 * MCU_INT_MASK_CSR: MCU interrupt source/mask register.
106 */
107 #define MCU_INT_MASK_CSR 0x0018
108 #define MCU_INT_MASK_CSR_0 FIELD32(0x00000001)
109 #define MCU_INT_MASK_CSR_1 FIELD32(0x00000002)
110 #define MCU_INT_MASK_CSR_2 FIELD32(0x00000004)
111 #define MCU_INT_MASK_CSR_3 FIELD32(0x00000008)
112 #define MCU_INT_MASK_CSR_4 FIELD32(0x00000010)
113 #define MCU_INT_MASK_CSR_5 FIELD32(0x00000020)
114 #define MCU_INT_MASK_CSR_6 FIELD32(0x00000040)
115 #define MCU_INT_MASK_CSR_7 FIELD32(0x00000080)
116 #define MCU_INT_MASK_CSR_TWAKEUP FIELD32(0x00000100)
117 #define MCU_INT_MASK_CSR_TBTT_EXPIRE FIELD32(0x00000200)
118
119 /*
120 * PCI_USEC_CSR
121 */
122 #define PCI_USEC_CSR 0x001c
123
124 /*
125 * Security key table memory.
126 * 16 entries 32-byte for shared key table
127 * 64 entries 32-byte for pairwise key table
128 * 64 entries 8-byte for pairwise ta key table
129 */
130 #define SHARED_KEY_TABLE_BASE 0x1000
131 #define PAIRWISE_KEY_TABLE_BASE 0x1200
132 #define PAIRWISE_TA_TABLE_BASE 0x1a00
133
134 struct hw_key_entry {
135 u8 key[16];
136 u8 tx_mic[8];
137 u8 rx_mic[8];
138 } __attribute__ ((packed));
139
140 struct hw_pairwise_ta_entry {
141 u8 address[6];
142 u8 reserved[2];
143 } __attribute__ ((packed));
144
145 /*
146 * Other on-chip shared memory space.
147 */
148 #define HW_CIS_BASE 0x2000
149 #define HW_NULL_BASE 0x2b00
150
151 /*
152 * Since NULL frame won't be that long (256 byte),
153 * We steal 16 tail bytes to save debugging settings.
154 */
155 #define HW_DEBUG_SETTING_BASE 0x2bf0
156
157 /*
158 * On-chip BEACON frame space.
159 */
160 #define HW_BEACON_BASE0 0x2c00
161 #define HW_BEACON_BASE1 0x2d00
162 #define HW_BEACON_BASE2 0x2e00
163 #define HW_BEACON_BASE3 0x2f00
164
165 #define HW_BEACON_OFFSET(__index) \
166 ( HW_BEACON_BASE0 + (__index * 0x0100) )
167
168 /*
169 * HOST-MCU shared memory.
170 */
171
172 /*
173 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
174 */
175 #define H2M_MAILBOX_CSR 0x2100
176 #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
177 #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
178 #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
179 #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
180
181 /*
182 * MCU_LEDCS: LED control for MCU Mailbox.
183 */
184 #define MCU_LEDCS_LED_MODE FIELD16(0x001f)
185 #define MCU_LEDCS_RADIO_STATUS FIELD16(0x0020)
186 #define MCU_LEDCS_LINK_BG_STATUS FIELD16(0x0040)
187 #define MCU_LEDCS_LINK_A_STATUS FIELD16(0x0080)
188 #define MCU_LEDCS_POLARITY_GPIO_0 FIELD16(0x0100)
189 #define MCU_LEDCS_POLARITY_GPIO_1 FIELD16(0x0200)
190 #define MCU_LEDCS_POLARITY_GPIO_2 FIELD16(0x0400)
191 #define MCU_LEDCS_POLARITY_GPIO_3 FIELD16(0x0800)
192 #define MCU_LEDCS_POLARITY_GPIO_4 FIELD16(0x1000)
193 #define MCU_LEDCS_POLARITY_ACT FIELD16(0x2000)
194 #define MCU_LEDCS_POLARITY_READY_BG FIELD16(0x4000)
195 #define MCU_LEDCS_POLARITY_READY_A FIELD16(0x8000)
196
197 /*
198 * M2H_CMD_DONE_CSR.
199 */
200 #define M2H_CMD_DONE_CSR 0x2104
201
202 /*
203 * MCU_TXOP_ARRAY_BASE.
204 */
205 #define MCU_TXOP_ARRAY_BASE 0x2110
206
207 /*
208 * MAC Control/Status Registers(CSR).
209 * Some values are set in TU, whereas 1 TU == 1024 us.
210 */
211
212 /*
213 * MAC_CSR0: ASIC revision number.
214 */
215 #define MAC_CSR0 0x3000
216
217 /*
218 * MAC_CSR1: System control register.
219 * SOFT_RESET: Software reset bit, 1: reset, 0: normal.
220 * BBP_RESET: Hardware reset BBP.
221 * HOST_READY: Host is ready after initialization, 1: ready.
222 */
223 #define MAC_CSR1 0x3004
224 #define MAC_CSR1_SOFT_RESET FIELD32(0x00000001)
225 #define MAC_CSR1_BBP_RESET FIELD32(0x00000002)
226 #define MAC_CSR1_HOST_READY FIELD32(0x00000004)
227
228 /*
229 * MAC_CSR2: STA MAC register 0.
230 */
231 #define MAC_CSR2 0x3008
232 #define MAC_CSR2_BYTE0 FIELD32(0x000000ff)
233 #define MAC_CSR2_BYTE1 FIELD32(0x0000ff00)
234 #define MAC_CSR2_BYTE2 FIELD32(0x00ff0000)
235 #define MAC_CSR2_BYTE3 FIELD32(0xff000000)
236
237 /*
238 * MAC_CSR3: STA MAC register 1.
239 * UNICAST_TO_ME_MASK:
240 * Used to mask off bits from byte 5 of the MAC address
241 * to determine the UNICAST_TO_ME bit for RX frames.
242 * The full mask is complemented by BSS_ID_MASK:
243 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
244 */
245 #define MAC_CSR3 0x300c
246 #define MAC_CSR3_BYTE4 FIELD32(0x000000ff)
247 #define MAC_CSR3_BYTE5 FIELD32(0x0000ff00)
248 #define MAC_CSR3_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
249
250 /*
251 * MAC_CSR4: BSSID register 0.
252 */
253 #define MAC_CSR4 0x3010
254 #define MAC_CSR4_BYTE0 FIELD32(0x000000ff)
255 #define MAC_CSR4_BYTE1 FIELD32(0x0000ff00)
256 #define MAC_CSR4_BYTE2 FIELD32(0x00ff0000)
257 #define MAC_CSR4_BYTE3 FIELD32(0xff000000)
258
259 /*
260 * MAC_CSR5: BSSID register 1.
261 * BSS_ID_MASK:
262 * This mask is used to mask off bits 0 and 1 of byte 5 of the
263 * BSSID. This will make sure that those bits will be ignored
264 * when determining the MY_BSS of RX frames.
265 * 0: 1-BSSID mode (BSS index = 0)
266 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
267 * 2: 2-BSSID mode (BSS index: byte5, bit 1)
268 * 3: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
269 */
270 #define MAC_CSR5 0x3014
271 #define MAC_CSR5_BYTE4 FIELD32(0x000000ff)
272 #define MAC_CSR5_BYTE5 FIELD32(0x0000ff00)
273 #define MAC_CSR5_BSS_ID_MASK FIELD32(0x00ff0000)
274
275 /*
276 * MAC_CSR6: Maximum frame length register.
277 */
278 #define MAC_CSR6 0x3018
279 #define MAC_CSR6_MAX_FRAME_UNIT FIELD32(0x00000fff)
280
281 /*
282 * MAC_CSR7: Reserved
283 */
284 #define MAC_CSR7 0x301c
285
286 /*
287 * MAC_CSR8: SIFS/EIFS register.
288 * All units are in US.
289 */
290 #define MAC_CSR8 0x3020
291 #define MAC_CSR8_SIFS FIELD32(0x000000ff)
292 #define MAC_CSR8_SIFS_AFTER_RX_OFDM FIELD32(0x0000ff00)
293 #define MAC_CSR8_EIFS FIELD32(0xffff0000)
294
295 /*
296 * MAC_CSR9: Back-Off control register.
297 * SLOT_TIME: Slot time, default is 20us for 802.11BG.
298 * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
299 * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
300 * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.
301 */
302 #define MAC_CSR9 0x3024
303 #define MAC_CSR9_SLOT_TIME FIELD32(0x000000ff)
304 #define MAC_CSR9_CWMIN FIELD32(0x00000f00)
305 #define MAC_CSR9_CWMAX FIELD32(0x0000f000)
306 #define MAC_CSR9_CW_SELECT FIELD32(0x00010000)
307
308 /*
309 * MAC_CSR10: Power state configuration.
310 */
311 #define MAC_CSR10 0x3028
312
313 /*
314 * MAC_CSR11: Power saving transition time register.
315 * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU.
316 * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
317 * WAKEUP_LATENCY: In unit of TU.
318 */
319 #define MAC_CSR11 0x302c
320 #define MAC_CSR11_DELAY_AFTER_TBCN FIELD32(0x000000ff)
321 #define MAC_CSR11_TBCN_BEFORE_WAKEUP FIELD32(0x00007f00)
322 #define MAC_CSR11_AUTOWAKE FIELD32(0x00008000)
323 #define MAC_CSR11_WAKEUP_LATENCY FIELD32(0x000f0000)
324
325 /*
326 * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1).
327 * CURRENT_STATE: 0:sleep, 1:awake.
328 * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP.
329 * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.
330 */
331 #define MAC_CSR12 0x3030
332 #define MAC_CSR12_CURRENT_STATE FIELD32(0x00000001)
333 #define MAC_CSR12_PUT_TO_SLEEP FIELD32(0x00000002)
334 #define MAC_CSR12_FORCE_WAKEUP FIELD32(0x00000004)
335 #define MAC_CSR12_BBP_CURRENT_STATE FIELD32(0x00000008)
336
337 /*
338 * MAC_CSR13: GPIO.
339 */
340 #define MAC_CSR13 0x3034
341 #define MAC_CSR13_BIT0 FIELD32(0x00000001)
342 #define MAC_CSR13_BIT1 FIELD32(0x00000002)
343 #define MAC_CSR13_BIT2 FIELD32(0x00000004)
344 #define MAC_CSR13_BIT3 FIELD32(0x00000008)
345 #define MAC_CSR13_BIT4 FIELD32(0x00000010)
346 #define MAC_CSR13_BIT5 FIELD32(0x00000020)
347 #define MAC_CSR13_BIT6 FIELD32(0x00000040)
348 #define MAC_CSR13_BIT7 FIELD32(0x00000080)
349 #define MAC_CSR13_BIT8 FIELD32(0x00000100)
350 #define MAC_CSR13_BIT9 FIELD32(0x00000200)
351 #define MAC_CSR13_BIT10 FIELD32(0x00000400)
352 #define MAC_CSR13_BIT11 FIELD32(0x00000800)
353 #define MAC_CSR13_BIT12 FIELD32(0x00001000)
354
355 /*
356 * MAC_CSR14: LED control register.
357 * ON_PERIOD: On period, default 70ms.
358 * OFF_PERIOD: Off period, default 30ms.
359 * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.
360 * SW_LED: s/w LED, 1: ON, 0: OFF.
361 * HW_LED_POLARITY: 0: active low, 1: active high.
362 */
363 #define MAC_CSR14 0x3038
364 #define MAC_CSR14_ON_PERIOD FIELD32(0x000000ff)
365 #define MAC_CSR14_OFF_PERIOD FIELD32(0x0000ff00)
366 #define MAC_CSR14_HW_LED FIELD32(0x00010000)
367 #define MAC_CSR14_SW_LED FIELD32(0x00020000)
368 #define MAC_CSR14_HW_LED_POLARITY FIELD32(0x00040000)
369 #define MAC_CSR14_SW_LED2 FIELD32(0x00080000)
370
371 /*
372 * MAC_CSR15: NAV control.
373 */
374 #define MAC_CSR15 0x303c
375
376 /*
377 * TXRX control registers.
378 * Some values are set in TU, whereas 1 TU == 1024 us.
379 */
380
381 /*
382 * TXRX_CSR0: TX/RX configuration register.
383 * TSF_OFFSET: Default is 24.
384 * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame.
385 * DISABLE_RX: Disable Rx engine.
386 * DROP_CRC: Drop CRC error.
387 * DROP_PHYSICAL: Drop physical error.
388 * DROP_CONTROL: Drop control frame.
389 * DROP_NOT_TO_ME: Drop not to me unicast frame.
390 * DROP_TO_DS: Drop fram ToDs bit is true.
391 * DROP_VERSION_ERROR: Drop version error frame.
392 * DROP_MULTICAST: Drop multicast frames.
393 * DROP_BORADCAST: Drop broadcast frames.
394 * ROP_ACK_CTS: Drop received ACK and CTS.
395 */
396 #define TXRX_CSR0 0x3040
397 #define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff)
398 #define TXRX_CSR0_TSF_OFFSET FIELD32(0x00007e00)
399 #define TXRX_CSR0_AUTO_TX_SEQ FIELD32(0x00008000)
400 #define TXRX_CSR0_DISABLE_RX FIELD32(0x00010000)
401 #define TXRX_CSR0_DROP_CRC FIELD32(0x00020000)
402 #define TXRX_CSR0_DROP_PHYSICAL FIELD32(0x00040000)
403 #define TXRX_CSR0_DROP_CONTROL FIELD32(0x00080000)
404 #define TXRX_CSR0_DROP_NOT_TO_ME FIELD32(0x00100000)
405 #define TXRX_CSR0_DROP_TO_DS FIELD32(0x00200000)
406 #define TXRX_CSR0_DROP_VERSION_ERROR FIELD32(0x00400000)
407 #define TXRX_CSR0_DROP_MULTICAST FIELD32(0x00800000)
408 #define TXRX_CSR0_DROP_BORADCAST FIELD32(0x01000000)
409 #define TXRX_CSR0_DROP_ACK_CTS FIELD32(0x02000000)
410 #define TXRX_CSR0_TX_WITHOUT_WAITING FIELD32(0x04000000)
411
412 /*
413 * TXRX_CSR1
414 */
415 #define TXRX_CSR1 0x3044
416 #define TXRX_CSR1_BBP_ID0 FIELD32(0x0000007f)
417 #define TXRX_CSR1_BBP_ID0_VALID FIELD32(0x00000080)
418 #define TXRX_CSR1_BBP_ID1 FIELD32(0x00007f00)
419 #define TXRX_CSR1_BBP_ID1_VALID FIELD32(0x00008000)
420 #define TXRX_CSR1_BBP_ID2 FIELD32(0x007f0000)
421 #define TXRX_CSR1_BBP_ID2_VALID FIELD32(0x00800000)
422 #define TXRX_CSR1_BBP_ID3 FIELD32(0x7f000000)
423 #define TXRX_CSR1_BBP_ID3_VALID FIELD32(0x80000000)
424
425 /*
426 * TXRX_CSR2
427 */
428 #define TXRX_CSR2 0x3048
429 #define TXRX_CSR2_BBP_ID0 FIELD32(0x0000007f)
430 #define TXRX_CSR2_BBP_ID0_VALID FIELD32(0x00000080)
431 #define TXRX_CSR2_BBP_ID1 FIELD32(0x00007f00)
432 #define TXRX_CSR2_BBP_ID1_VALID FIELD32(0x00008000)
433 #define TXRX_CSR2_BBP_ID2 FIELD32(0x007f0000)
434 #define TXRX_CSR2_BBP_ID2_VALID FIELD32(0x00800000)
435 #define TXRX_CSR2_BBP_ID3 FIELD32(0x7f000000)
436 #define TXRX_CSR2_BBP_ID3_VALID FIELD32(0x80000000)
437
438 /*
439 * TXRX_CSR3
440 */
441 #define TXRX_CSR3 0x304c
442 #define TXRX_CSR3_BBP_ID0 FIELD32(0x0000007f)
443 #define TXRX_CSR3_BBP_ID0_VALID FIELD32(0x00000080)
444 #define TXRX_CSR3_BBP_ID1 FIELD32(0x00007f00)
445 #define TXRX_CSR3_BBP_ID1_VALID FIELD32(0x00008000)
446 #define TXRX_CSR3_BBP_ID2 FIELD32(0x007f0000)
447 #define TXRX_CSR3_BBP_ID2_VALID FIELD32(0x00800000)
448 #define TXRX_CSR3_BBP_ID3 FIELD32(0x7f000000)
449 #define TXRX_CSR3_BBP_ID3_VALID FIELD32(0x80000000)
450
451 /*
452 * TXRX_CSR4: Auto-Responder/Tx-retry register.
453 * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble.
454 * OFDM_TX_RATE_DOWN: 1:enable.
455 * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step.
456 * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M.
457 */
458 #define TXRX_CSR4 0x3050
459 #define TXRX_CSR4_TX_ACK_TIMEOUT FIELD32(0x000000ff)
460 #define TXRX_CSR4_CNTL_ACK_POLICY FIELD32(0x00000700)
461 #define TXRX_CSR4_ACK_CTS_PSM FIELD32(0x00010000)
462 #define TXRX_CSR4_AUTORESPOND_ENABLE FIELD32(0x00020000)
463 #define TXRX_CSR4_AUTORESPOND_PREAMBLE FIELD32(0x00040000)
464 #define TXRX_CSR4_OFDM_TX_RATE_DOWN FIELD32(0x00080000)
465 #define TXRX_CSR4_OFDM_TX_RATE_STEP FIELD32(0x00300000)
466 #define TXRX_CSR4_OFDM_TX_FALLBACK_CCK FIELD32(0x00400000)
467 #define TXRX_CSR4_LONG_RETRY_LIMIT FIELD32(0x0f000000)
468 #define TXRX_CSR4_SHORT_RETRY_LIMIT FIELD32(0xf0000000)
469
470 /*
471 * TXRX_CSR5
472 */
473 #define TXRX_CSR5 0x3054
474
475 /*
476 * TXRX_CSR6: ACK/CTS payload consumed time
477 */
478 #define TXRX_CSR6 0x3058
479
480 /*
481 * TXRX_CSR7: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.
482 */
483 #define TXRX_CSR7 0x305c
484 #define TXRX_CSR7_ACK_CTS_6MBS FIELD32(0x000000ff)
485 #define TXRX_CSR7_ACK_CTS_9MBS FIELD32(0x0000ff00)
486 #define TXRX_CSR7_ACK_CTS_12MBS FIELD32(0x00ff0000)
487 #define TXRX_CSR7_ACK_CTS_18MBS FIELD32(0xff000000)
488
489 /*
490 * TXRX_CSR8: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.
491 */
492 #define TXRX_CSR8 0x3060
493 #define TXRX_CSR8_ACK_CTS_24MBS FIELD32(0x000000ff)
494 #define TXRX_CSR8_ACK_CTS_36MBS FIELD32(0x0000ff00)
495 #define TXRX_CSR8_ACK_CTS_48MBS FIELD32(0x00ff0000)
496 #define TXRX_CSR8_ACK_CTS_54MBS FIELD32(0xff000000)
497
498 /*
499 * TXRX_CSR9: Synchronization control register.
500 * BEACON_INTERVAL: In unit of 1/16 TU.
501 * TSF_TICKING: Enable TSF auto counting.
502 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
503 * BEACON_GEN: Enable beacon generator.
504 */
505 #define TXRX_CSR9 0x3064
506 #define TXRX_CSR9_BEACON_INTERVAL FIELD32(0x0000ffff)
507 #define TXRX_CSR9_TSF_TICKING FIELD32(0x00010000)
508 #define TXRX_CSR9_TSF_SYNC FIELD32(0x00060000)
509 #define TXRX_CSR9_TBTT_ENABLE FIELD32(0x00080000)
510 #define TXRX_CSR9_BEACON_GEN FIELD32(0x00100000)
511 #define TXRX_CSR9_TIMESTAMP_COMPENSATE FIELD32(0xff000000)
512
513 /*
514 * TXRX_CSR10: BEACON alignment.
515 */
516 #define TXRX_CSR10 0x3068
517
518 /*
519 * TXRX_CSR11: AES mask.
520 */
521 #define TXRX_CSR11 0x306c
522
523 /*
524 * TXRX_CSR12: TSF low 32.
525 */
526 #define TXRX_CSR12 0x3070
527 #define TXRX_CSR12_LOW_TSFTIMER FIELD32(0xffffffff)
528
529 /*
530 * TXRX_CSR13: TSF high 32.
531 */
532 #define TXRX_CSR13 0x3074
533 #define TXRX_CSR13_HIGH_TSFTIMER FIELD32(0xffffffff)
534
535 /*
536 * TXRX_CSR14: TBTT timer.
537 */
538 #define TXRX_CSR14 0x3078
539
540 /*
541 * TXRX_CSR15: TKIP MIC priority byte "AND" mask.
542 */
543 #define TXRX_CSR15 0x307c
544
545 /*
546 * PHY control registers.
547 * Some values are set in TU, whereas 1 TU == 1024 us.
548 */
549
550 /*
551 * PHY_CSR0: RF/PS control.
552 */
553 #define PHY_CSR0 0x3080
554 #define PHY_CSR0_PA_PE_BG FIELD32(0x00010000)
555 #define PHY_CSR0_PA_PE_A FIELD32(0x00020000)
556
557 /*
558 * PHY_CSR1
559 */
560 #define PHY_CSR1 0x3084
561
562 /*
563 * PHY_CSR2: Pre-TX BBP control.
564 */
565 #define PHY_CSR2 0x3088
566
567 /*
568 * PHY_CSR3: BBP serial control register.
569 * VALUE: Register value to program into BBP.
570 * REG_NUM: Selected BBP register.
571 * READ_CONTROL: 0: Write BBP, 1: Read BBP.
572 * BUSY: 1: ASIC is busy execute BBP programming.
573 */
574 #define PHY_CSR3 0x308c
575 #define PHY_CSR3_VALUE FIELD32(0x000000ff)
576 #define PHY_CSR3_REGNUM FIELD32(0x00007f00)
577 #define PHY_CSR3_READ_CONTROL FIELD32(0x00008000)
578 #define PHY_CSR3_BUSY FIELD32(0x00010000)
579
580 /*
581 * PHY_CSR4: RF serial control register
582 * VALUE: Register value (include register id) serial out to RF/IF chip.
583 * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22).
584 * IF_SELECT: 1: select IF to program, 0: select RF to program.
585 * PLL_LD: RF PLL_LD status.
586 * BUSY: 1: ASIC is busy execute RF programming.
587 */
588 #define PHY_CSR4 0x3090
589 #define PHY_CSR4_VALUE FIELD32(0x00ffffff)
590 #define PHY_CSR4_NUMBER_OF_BITS FIELD32(0x1f000000)
591 #define PHY_CSR4_IF_SELECT FIELD32(0x20000000)
592 #define PHY_CSR4_PLL_LD FIELD32(0x40000000)
593 #define PHY_CSR4_BUSY FIELD32(0x80000000)
594
595 /*
596 * PHY_CSR5: RX to TX signal switch timing control.
597 */
598 #define PHY_CSR5 0x3094
599 #define PHY_CSR5_IQ_FLIP FIELD32(0x00000004)
600
601 /*
602 * PHY_CSR6: TX to RX signal timing control.
603 */
604 #define PHY_CSR6 0x3098
605 #define PHY_CSR6_IQ_FLIP FIELD32(0x00000004)
606
607 /*
608 * PHY_CSR7: TX DAC switching timing control.
609 */
610 #define PHY_CSR7 0x309c
611
612 /*
613 * Security control register.
614 */
615
616 /*
617 * SEC_CSR0: Shared key table control.
618 */
619 #define SEC_CSR0 0x30a0
620 #define SEC_CSR0_BSS0_KEY0_VALID FIELD32(0x00000001)
621 #define SEC_CSR0_BSS0_KEY1_VALID FIELD32(0x00000002)
622 #define SEC_CSR0_BSS0_KEY2_VALID FIELD32(0x00000004)
623 #define SEC_CSR0_BSS0_KEY3_VALID FIELD32(0x00000008)
624 #define SEC_CSR0_BSS1_KEY0_VALID FIELD32(0x00000010)
625 #define SEC_CSR0_BSS1_KEY1_VALID FIELD32(0x00000020)
626 #define SEC_CSR0_BSS1_KEY2_VALID FIELD32(0x00000040)
627 #define SEC_CSR0_BSS1_KEY3_VALID FIELD32(0x00000080)
628 #define SEC_CSR0_BSS2_KEY0_VALID FIELD32(0x00000100)
629 #define SEC_CSR0_BSS2_KEY1_VALID FIELD32(0x00000200)
630 #define SEC_CSR0_BSS2_KEY2_VALID FIELD32(0x00000400)
631 #define SEC_CSR0_BSS2_KEY3_VALID FIELD32(0x00000800)
632 #define SEC_CSR0_BSS3_KEY0_VALID FIELD32(0x00001000)
633 #define SEC_CSR0_BSS3_KEY1_VALID FIELD32(0x00002000)
634 #define SEC_CSR0_BSS3_KEY2_VALID FIELD32(0x00004000)
635 #define SEC_CSR0_BSS3_KEY3_VALID FIELD32(0x00008000)
636
637 /*
638 * SEC_CSR1: Shared key table security mode register.
639 */
640 #define SEC_CSR1 0x30a4
641 #define SEC_CSR1_BSS0_KEY0_CIPHER_ALG FIELD32(0x00000007)
642 #define SEC_CSR1_BSS0_KEY1_CIPHER_ALG FIELD32(0x00000070)
643 #define SEC_CSR1_BSS0_KEY2_CIPHER_ALG FIELD32(0x00000700)
644 #define SEC_CSR1_BSS0_KEY3_CIPHER_ALG FIELD32(0x00007000)
645 #define SEC_CSR1_BSS1_KEY0_CIPHER_ALG FIELD32(0x00070000)
646 #define SEC_CSR1_BSS1_KEY1_CIPHER_ALG FIELD32(0x00700000)
647 #define SEC_CSR1_BSS1_KEY2_CIPHER_ALG FIELD32(0x07000000)
648 #define SEC_CSR1_BSS1_KEY3_CIPHER_ALG FIELD32(0x70000000)
649
650 /*
651 * Pairwise key table valid bitmap registers.
652 * SEC_CSR2: pairwise key table valid bitmap 0.
653 * SEC_CSR3: pairwise key table valid bitmap 1.
654 */
655 #define SEC_CSR2 0x30a8
656 #define SEC_CSR3 0x30ac
657
658 /*
659 * SEC_CSR4: Pairwise key table lookup control.
660 */
661 #define SEC_CSR4 0x30b0
662
663 /*
664 * SEC_CSR5: shared key table security mode register.
665 */
666 #define SEC_CSR5 0x30b4
667 #define SEC_CSR5_BSS2_KEY0_CIPHER_ALG FIELD32(0x00000007)
668 #define SEC_CSR5_BSS2_KEY1_CIPHER_ALG FIELD32(0x00000070)
669 #define SEC_CSR5_BSS2_KEY2_CIPHER_ALG FIELD32(0x00000700)
670 #define SEC_CSR5_BSS2_KEY3_CIPHER_ALG FIELD32(0x00007000)
671 #define SEC_CSR5_BSS3_KEY0_CIPHER_ALG FIELD32(0x00070000)
672 #define SEC_CSR5_BSS3_KEY1_CIPHER_ALG FIELD32(0x00700000)
673 #define SEC_CSR5_BSS3_KEY2_CIPHER_ALG FIELD32(0x07000000)
674 #define SEC_CSR5_BSS3_KEY3_CIPHER_ALG FIELD32(0x70000000)
675
676 /*
677 * STA control registers.
678 */
679
680 /*
681 * STA_CSR0: RX PLCP error count & RX FCS error count.
682 */
683 #define STA_CSR0 0x30c0
684 #define STA_CSR0_FCS_ERROR FIELD32(0x0000ffff)
685 #define STA_CSR0_PLCP_ERROR FIELD32(0xffff0000)
686
687 /*
688 * STA_CSR1: RX False CCA count & RX LONG frame count.
689 */
690 #define STA_CSR1 0x30c4
691 #define STA_CSR1_PHYSICAL_ERROR FIELD32(0x0000ffff)
692 #define STA_CSR1_FALSE_CCA_ERROR FIELD32(0xffff0000)
693
694 /*
695 * STA_CSR2: TX Beacon count and RX FIFO overflow count.
696 */
697 #define STA_CSR2 0x30c8
698 #define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
699 #define STA_CSR2_RX_OVERFLOW_COUNT FIELD32(0xffff0000)
700
701 /*
702 * STA_CSR3: TX Beacon count.
703 */
704 #define STA_CSR3 0x30cc
705 #define STA_CSR3_TX_BEACON_COUNT FIELD32(0x0000ffff)
706
707 /*
708 * STA_CSR4: TX Result status register.
709 * VALID: 1:This register contains a valid TX result.
710 */
711 #define STA_CSR4 0x30d0
712 #define STA_CSR4_VALID FIELD32(0x00000001)
713 #define STA_CSR4_TX_RESULT FIELD32(0x0000000e)
714 #define STA_CSR4_RETRY_COUNT FIELD32(0x000000f0)
715 #define STA_CSR4_PID_SUBTYPE FIELD32(0x00001f00)
716 #define STA_CSR4_PID_TYPE FIELD32(0x0000e000)
717 #define STA_CSR4_TXRATE FIELD32(0x000f0000)
718
719 /*
720 * QOS control registers.
721 */
722
723 /*
724 * QOS_CSR0: TXOP holder MAC address register.
725 */
726 #define QOS_CSR0 0x30e0
727 #define QOS_CSR0_BYTE0 FIELD32(0x000000ff)
728 #define QOS_CSR0_BYTE1 FIELD32(0x0000ff00)
729 #define QOS_CSR0_BYTE2 FIELD32(0x00ff0000)
730 #define QOS_CSR0_BYTE3 FIELD32(0xff000000)
731
732 /*
733 * QOS_CSR1: TXOP holder MAC address register.
734 */
735 #define QOS_CSR1 0x30e4
736 #define QOS_CSR1_BYTE4 FIELD32(0x000000ff)
737 #define QOS_CSR1_BYTE5 FIELD32(0x0000ff00)
738
739 /*
740 * QOS_CSR2: TXOP holder timeout register.
741 */
742 #define QOS_CSR2 0x30e8
743
744 /*
745 * RX QOS-CFPOLL MAC address register.
746 * QOS_CSR3: RX QOS-CFPOLL MAC address 0.
747 * QOS_CSR4: RX QOS-CFPOLL MAC address 1.
748 */
749 #define QOS_CSR3 0x30ec
750 #define QOS_CSR4 0x30f0
751
752 /*
753 * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL.
754 */
755 #define QOS_CSR5 0x30f4
756
757 /*
758 * Host DMA registers.
759 */
760
761 /*
762 * AC0_BASE_CSR: AC_BK base address.
763 */
764 #define AC0_BASE_CSR 0x3400
765 #define AC0_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
766
767 /*
768 * AC1_BASE_CSR: AC_BE base address.
769 */
770 #define AC1_BASE_CSR 0x3404
771 #define AC1_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
772
773 /*
774 * AC2_BASE_CSR: AC_VI base address.
775 */
776 #define AC2_BASE_CSR 0x3408
777 #define AC2_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
778
779 /*
780 * AC3_BASE_CSR: AC_VO base address.
781 */
782 #define AC3_BASE_CSR 0x340c
783 #define AC3_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
784
785 /*
786 * MGMT_BASE_CSR: MGMT ring base address.
787 */
788 #define MGMT_BASE_CSR 0x3410
789 #define MGMT_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
790
791 /*
792 * TX_RING_CSR0: TX Ring size for AC_BK, AC_BE, AC_VI, AC_VO.
793 */
794 #define TX_RING_CSR0 0x3418
795 #define TX_RING_CSR0_AC0_RING_SIZE FIELD32(0x000000ff)
796 #define TX_RING_CSR0_AC1_RING_SIZE FIELD32(0x0000ff00)
797 #define TX_RING_CSR0_AC2_RING_SIZE FIELD32(0x00ff0000)
798 #define TX_RING_CSR0_AC3_RING_SIZE FIELD32(0xff000000)
799
800 /*
801 * TX_RING_CSR1: TX Ring size for MGMT Ring, HCCA Ring
802 * TXD_SIZE: In unit of 32-bit.
803 */
804 #define TX_RING_CSR1 0x341c
805 #define TX_RING_CSR1_MGMT_RING_SIZE FIELD32(0x000000ff)
806 #define TX_RING_CSR1_HCCA_RING_SIZE FIELD32(0x0000ff00)
807 #define TX_RING_CSR1_TXD_SIZE FIELD32(0x003f0000)
808
809 /*
810 * AIFSN_CSR: AIFSN for each EDCA AC.
811 * AIFSN0: For AC_BK.
812 * AIFSN1: For AC_BE.
813 * AIFSN2: For AC_VI.
814 * AIFSN3: For AC_VO.
815 */
816 #define AIFSN_CSR 0x3420
817 #define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f)
818 #define AIFSN_CSR_AIFSN1 FIELD32(0x000000f0)
819 #define AIFSN_CSR_AIFSN2 FIELD32(0x00000f00)
820 #define AIFSN_CSR_AIFSN3 FIELD32(0x0000f000)
821
822 /*
823 * CWMIN_CSR: CWmin for each EDCA AC.
824 * CWMIN0: For AC_BK.
825 * CWMIN1: For AC_BE.
826 * CWMIN2: For AC_VI.
827 * CWMIN3: For AC_VO.
828 */
829 #define CWMIN_CSR 0x3424
830 #define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f)
831 #define CWMIN_CSR_CWMIN1 FIELD32(0x000000f0)
832 #define CWMIN_CSR_CWMIN2 FIELD32(0x00000f00)
833 #define CWMIN_CSR_CWMIN3 FIELD32(0x0000f000)
834
835 /*
836 * CWMAX_CSR: CWmax for each EDCA AC.
837 * CWMAX0: For AC_BK.
838 * CWMAX1: For AC_BE.
839 * CWMAX2: For AC_VI.
840 * CWMAX3: For AC_VO.
841 */
842 #define CWMAX_CSR 0x3428
843 #define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f)
844 #define CWMAX_CSR_CWMAX1 FIELD32(0x000000f0)
845 #define CWMAX_CSR_CWMAX2 FIELD32(0x00000f00)
846 #define CWMAX_CSR_CWMAX3 FIELD32(0x0000f000)
847
848 /*
849 * TX_DMA_DST_CSR: TX DMA destination
850 * 0: TX ring0, 1: TX ring1, 2: TX ring2 3: invalid
851 */
852 #define TX_DMA_DST_CSR 0x342c
853 #define TX_DMA_DST_CSR_DEST_AC0 FIELD32(0x00000003)
854 #define TX_DMA_DST_CSR_DEST_AC1 FIELD32(0x0000000c)
855 #define TX_DMA_DST_CSR_DEST_AC2 FIELD32(0x00000030)
856 #define TX_DMA_DST_CSR_DEST_AC3 FIELD32(0x000000c0)
857 #define TX_DMA_DST_CSR_DEST_MGMT FIELD32(0x00000300)
858
859 /*
860 * TX_CNTL_CSR: KICK/Abort TX.
861 * KICK_TX_AC0: For AC_BK.
862 * KICK_TX_AC1: For AC_BE.
863 * KICK_TX_AC2: For AC_VI.
864 * KICK_TX_AC3: For AC_VO.
865 * ABORT_TX_AC0: For AC_BK.
866 * ABORT_TX_AC1: For AC_BE.
867 * ABORT_TX_AC2: For AC_VI.
868 * ABORT_TX_AC3: For AC_VO.
869 */
870 #define TX_CNTL_CSR 0x3430
871 #define TX_CNTL_CSR_KICK_TX_AC0 FIELD32(0x00000001)
872 #define TX_CNTL_CSR_KICK_TX_AC1 FIELD32(0x00000002)
873 #define TX_CNTL_CSR_KICK_TX_AC2 FIELD32(0x00000004)
874 #define TX_CNTL_CSR_KICK_TX_AC3 FIELD32(0x00000008)
875 #define TX_CNTL_CSR_KICK_TX_MGMT FIELD32(0x00000010)
876 #define TX_CNTL_CSR_ABORT_TX_AC0 FIELD32(0x00010000)
877 #define TX_CNTL_CSR_ABORT_TX_AC1 FIELD32(0x00020000)
878 #define TX_CNTL_CSR_ABORT_TX_AC2 FIELD32(0x00040000)
879 #define TX_CNTL_CSR_ABORT_TX_AC3 FIELD32(0x00080000)
880 #define TX_CNTL_CSR_ABORT_TX_MGMT FIELD32(0x00100000)
881
882 /*
883 * LOAD_TX_RING_CSR: Load RX de
884 */
885 #define LOAD_TX_RING_CSR 0x3434
886 #define LOAD_TX_RING_CSR_LOAD_TXD_AC0 FIELD32(0x00000001)
887 #define LOAD_TX_RING_CSR_LOAD_TXD_AC1 FIELD32(0x00000002)
888 #define LOAD_TX_RING_CSR_LOAD_TXD_AC2 FIELD32(0x00000004)
889 #define LOAD_TX_RING_CSR_LOAD_TXD_AC3 FIELD32(0x00000008)
890 #define LOAD_TX_RING_CSR_LOAD_TXD_MGMT FIELD32(0x00000010)
891
892 /*
893 * Several read-only registers, for debugging.
894 */
895 #define AC0_TXPTR_CSR 0x3438
896 #define AC1_TXPTR_CSR 0x343c
897 #define AC2_TXPTR_CSR 0x3440
898 #define AC3_TXPTR_CSR 0x3444
899 #define MGMT_TXPTR_CSR 0x3448
900
901 /*
902 * RX_BASE_CSR
903 */
904 #define RX_BASE_CSR 0x3450
905 #define RX_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
906
907 /*
908 * RX_RING_CSR.
909 * RXD_SIZE: In unit of 32-bit.
910 */
911 #define RX_RING_CSR 0x3454
912 #define RX_RING_CSR_RING_SIZE FIELD32(0x000000ff)
913 #define RX_RING_CSR_RXD_SIZE FIELD32(0x00003f00)
914 #define RX_RING_CSR_RXD_WRITEBACK_SIZE FIELD32(0x00070000)
915
916 /*
917 * RX_CNTL_CSR
918 */
919 #define RX_CNTL_CSR 0x3458
920 #define RX_CNTL_CSR_ENABLE_RX_DMA FIELD32(0x00000001)
921 #define RX_CNTL_CSR_LOAD_RXD FIELD32(0x00000002)
922
923 /*
924 * RXPTR_CSR: Read-only, for debugging.
925 */
926 #define RXPTR_CSR 0x345c
927
928 /*
929 * PCI_CFG_CSR
930 */
931 #define PCI_CFG_CSR 0x3460
932
933 /*
934 * BUF_FORMAT_CSR
935 */
936 #define BUF_FORMAT_CSR 0x3464
937
938 /*
939 * INT_SOURCE_CSR: Interrupt source register.
940 * Write one to clear corresponding bit.
941 */
942 #define INT_SOURCE_CSR 0x3468
943 #define INT_SOURCE_CSR_TXDONE FIELD32(0x00000001)
944 #define INT_SOURCE_CSR_RXDONE FIELD32(0x00000002)
945 #define INT_SOURCE_CSR_BEACON_DONE FIELD32(0x00000004)
946 #define INT_SOURCE_CSR_TX_ABORT_DONE FIELD32(0x00000010)
947 #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00010000)
948 #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00020000)
949 #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00040000)
950 #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00080000)
951 #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00100000)
952 #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00200000)
953
954 /*
955 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
956 * MITIGATION_PERIOD: Interrupt mitigation in unit of 32 PCI clock.
957 */
958 #define INT_MASK_CSR 0x346c
959 #define INT_MASK_CSR_TXDONE FIELD32(0x00000001)
960 #define INT_MASK_CSR_RXDONE FIELD32(0x00000002)
961 #define INT_MASK_CSR_BEACON_DONE FIELD32(0x00000004)
962 #define INT_MASK_CSR_TX_ABORT_DONE FIELD32(0x00000010)
963 #define INT_MASK_CSR_ENABLE_MITIGATION FIELD32(0x00000080)
964 #define INT_MASK_CSR_MITIGATION_PERIOD FIELD32(0x0000ff00)
965 #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00010000)
966 #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00020000)
967 #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00040000)
968 #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00080000)
969 #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00100000)
970 #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00200000)
971
972 /*
973 * E2PROM_CSR: EEPROM control register.
974 * RELOAD: Write 1 to reload eeprom content.
975 * TYPE_93C46: 1: 93c46, 0:93c66.
976 * LOAD_STATUS: 1:loading, 0:done.
977 */
978 #define E2PROM_CSR 0x3470
979 #define E2PROM_CSR_RELOAD FIELD32(0x00000001)
980 #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000002)
981 #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000004)
982 #define E2PROM_CSR_DATA_IN FIELD32(0x00000008)
983 #define E2PROM_CSR_DATA_OUT FIELD32(0x00000010)
984 #define E2PROM_CSR_TYPE_93C46 FIELD32(0x00000020)
985 #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
986
987 /*
988 * AC_TXOP_CSR0: AC_BK/AC_BE TXOP register.
989 * AC0_TX_OP: For AC_BK, in unit of 32us.
990 * AC1_TX_OP: For AC_BE, in unit of 32us.
991 */
992 #define AC_TXOP_CSR0 0x3474
993 #define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff)
994 #define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000)
995
996 /*
997 * AC_TXOP_CSR1: AC_VO/AC_VI TXOP register.
998 * AC2_TX_OP: For AC_VI, in unit of 32us.
999 * AC3_TX_OP: For AC_VO, in unit of 32us.
1000 */
1001 #define AC_TXOP_CSR1 0x3478
1002 #define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff)
1003 #define AC_TXOP_CSR1_AC3_TX_OP FIELD32(0xffff0000)
1004
1005 /*
1006 * DMA_STATUS_CSR
1007 */
1008 #define DMA_STATUS_CSR 0x3480
1009
1010 /*
1011 * TEST_MODE_CSR
1012 */
1013 #define TEST_MODE_CSR 0x3484
1014
1015 /*
1016 * UART0_TX_CSR
1017 */
1018 #define UART0_TX_CSR 0x3488
1019
1020 /*
1021 * UART0_RX_CSR
1022 */
1023 #define UART0_RX_CSR 0x348c
1024
1025 /*
1026 * UART0_FRAME_CSR
1027 */
1028 #define UART0_FRAME_CSR 0x3490
1029
1030 /*
1031 * UART0_BUFFER_CSR
1032 */
1033 #define UART0_BUFFER_CSR 0x3494
1034
1035 /*
1036 * IO_CNTL_CSR
1037 */
1038 #define IO_CNTL_CSR 0x3498
1039
1040 /*
1041 * UART_INT_SOURCE_CSR
1042 */
1043 #define UART_INT_SOURCE_CSR 0x34a8
1044
1045 /*
1046 * UART_INT_MASK_CSR
1047 */
1048 #define UART_INT_MASK_CSR 0x34ac
1049
1050 /*
1051 * PBF_QUEUE_CSR
1052 */
1053 #define PBF_QUEUE_CSR 0x34b0
1054
1055 /*
1056 * Firmware DMA registers.
1057 * Firmware DMA registers are dedicated for MCU usage
1058 * and should not be touched by host driver.
1059 * Therefore we skip the definition of these registers.
1060 */
1061 #define FW_TX_BASE_CSR 0x34c0
1062 #define FW_TX_START_CSR 0x34c4
1063 #define FW_TX_LAST_CSR 0x34c8
1064 #define FW_MODE_CNTL_CSR 0x34cc
1065 #define FW_TXPTR_CSR 0x34d0
1066
1067 /*
1068 * 8051 firmware image.
1069 */
1070 #define FIRMWARE_RT2561 "rt2561.bin"
1071 #define FIRMWARE_RT2561s "rt2561s.bin"
1072 #define FIRMWARE_RT2661 "rt2661.bin"
1073 #define FIRMWARE_IMAGE_BASE 0x4000
1074
1075 /*
1076 * BBP registers.
1077 * The wordsize of the BBP is 8 bits.
1078 */
1079
1080 /*
1081 * R2
1082 */
1083 #define BBP_R2_BG_MODE FIELD8(0x20)
1084
1085 /*
1086 * R3
1087 */
1088 #define BBP_R3_SMART_MODE FIELD8(0x01)
1089
1090 /*
1091 * R4: RX antenna control
1092 * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529)
1093 */
1094
1095 /*
1096 * ANTENNA_CONTROL semantics (guessed):
1097 * 0x1: Software controlled antenna switching (fixed or SW diversity)
1098 * 0x2: Hardware diversity.
1099 */
1100 #define BBP_R4_RX_ANTENNA_CONTROL FIELD8(0x03)
1101 #define BBP_R4_RX_FRAME_END FIELD8(0x20)
1102
1103 /*
1104 * R77
1105 */
1106 #define BBP_R77_RX_ANTENNA FIELD8(0x03)
1107
1108 /*
1109 * RF registers
1110 */
1111
1112 /*
1113 * RF 3
1114 */
1115 #define RF3_TXPOWER FIELD32(0x00003e00)
1116
1117 /*
1118 * RF 4
1119 */
1120 #define RF4_FREQ_OFFSET FIELD32(0x0003f000)
1121
1122 /*
1123 * EEPROM content.
1124 * The wordsize of the EEPROM is 16 bits.
1125 */
1126
1127 /*
1128 * HW MAC address.
1129 */
1130 #define EEPROM_MAC_ADDR_0 0x0002
1131 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1132 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1133 #define EEPROM_MAC_ADDR1 0x0004
1134 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1135 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1136 #define EEPROM_MAC_ADDR_2 0x0006
1137 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1138 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1139
1140 /*
1141 * EEPROM antenna.
1142 * ANTENNA_NUM: Number of antenna's.
1143 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1144 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1145 * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only.
1146 * DYN_TXAGC: Dynamic TX AGC control.
1147 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
1148 * RF_TYPE: Rf_type of this adapter.
1149 */
1150 #define EEPROM_ANTENNA 0x0010
1151 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
1152 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
1153 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
1154 #define EEPROM_ANTENNA_FRAME_TYPE FIELD16(0x0040)
1155 #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
1156 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
1157 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
1158
1159 /*
1160 * EEPROM NIC config.
1161 * ENABLE_DIVERSITY: 1:enable, 0:disable.
1162 * EXTERNAL_LNA_BG: External LNA enable for 2.4G.
1163 * CARDBUS_ACCEL: 0:enable, 1:disable.
1164 * EXTERNAL_LNA_A: External LNA enable for 5G.
1165 */
1166 #define EEPROM_NIC 0x0011
1167 #define EEPROM_NIC_ENABLE_DIVERSITY FIELD16(0x0001)
1168 #define EEPROM_NIC_TX_DIVERSITY FIELD16(0x0002)
1169 #define EEPROM_NIC_TX_RX_FIXED FIELD16(0x000c)
1170 #define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0010)
1171 #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0020)
1172 #define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0040)
1173
1174 /*
1175 * EEPROM geography.
1176 * GEO_A: Default geographical setting for 5GHz band
1177 * GEO: Default geographical setting.
1178 */
1179 #define EEPROM_GEOGRAPHY 0x0012
1180 #define EEPROM_GEOGRAPHY_GEO_A FIELD16(0x00ff)
1181 #define EEPROM_GEOGRAPHY_GEO FIELD16(0xff00)
1182
1183 /*
1184 * EEPROM BBP.
1185 */
1186 #define EEPROM_BBP_START 0x0013
1187 #define EEPROM_BBP_SIZE 16
1188 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
1189 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
1190
1191 /*
1192 * EEPROM TXPOWER 802.11G
1193 */
1194 #define EEPROM_TXPOWER_G_START 0x0023
1195 #define EEPROM_TXPOWER_G_SIZE 7
1196 #define EEPROM_TXPOWER_G_1 FIELD16(0x00ff)
1197 #define EEPROM_TXPOWER_G_2 FIELD16(0xff00)
1198
1199 /*
1200 * EEPROM Frequency
1201 */
1202 #define EEPROM_FREQ 0x002f
1203 #define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
1204 #define EEPROM_FREQ_SEQ_MASK FIELD16(0xff00)
1205 #define EEPROM_FREQ_SEQ FIELD16(0x0300)
1206
1207 /*
1208 * EEPROM LED.
1209 * POLARITY_RDY_G: Polarity RDY_G setting.
1210 * POLARITY_RDY_A: Polarity RDY_A setting.
1211 * POLARITY_ACT: Polarity ACT setting.
1212 * POLARITY_GPIO_0: Polarity GPIO0 setting.
1213 * POLARITY_GPIO_1: Polarity GPIO1 setting.
1214 * POLARITY_GPIO_2: Polarity GPIO2 setting.
1215 * POLARITY_GPIO_3: Polarity GPIO3 setting.
1216 * POLARITY_GPIO_4: Polarity GPIO4 setting.
1217 * LED_MODE: Led mode.
1218 */
1219 #define EEPROM_LED 0x0030
1220 #define EEPROM_LED_POLARITY_RDY_G FIELD16(0x0001)
1221 #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
1222 #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
1223 #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
1224 #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
1225 #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
1226 #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
1227 #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
1228 #define EEPROM_LED_LED_MODE FIELD16(0x1f00)
1229
1230 /*
1231 * EEPROM TXPOWER 802.11A
1232 */
1233 #define EEPROM_TXPOWER_A_START 0x0031
1234 #define EEPROM_TXPOWER_A_SIZE 12
1235 #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
1236 #define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
1237
1238 /*
1239 * EEPROM RSSI offset 802.11BG
1240 */
1241 #define EEPROM_RSSI_OFFSET_BG 0x004d
1242 #define EEPROM_RSSI_OFFSET_BG_1 FIELD16(0x00ff)
1243 #define EEPROM_RSSI_OFFSET_BG_2 FIELD16(0xff00)
1244
1245 /*
1246 * EEPROM RSSI offset 802.11A
1247 */
1248 #define EEPROM_RSSI_OFFSET_A 0x004e
1249 #define EEPROM_RSSI_OFFSET_A_1 FIELD16(0x00ff)
1250 #define EEPROM_RSSI_OFFSET_A_2 FIELD16(0xff00)
1251
1252 /*
1253 * MCU mailbox commands.
1254 */
1255 #define MCU_SLEEP 0x30
1256 #define MCU_WAKEUP 0x31
1257 #define MCU_LED 0x50
1258 #define MCU_LED_STRENGTH 0x52
1259
1260 /*
1261 * DMA descriptor defines.
1262 */
1263 #define TXD_DESC_SIZE ( 16 * sizeof(__le32) )
1264 #define TXINFO_SIZE ( 6 * sizeof(__le32) )
1265 #define RXD_DESC_SIZE ( 16 * sizeof(__le32) )
1266
1267 /*
1268 * TX descriptor format for TX, PRIO and Beacon Ring.
1269 */
1270
1271 /*
1272 * Word0
1273 * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used.
1274 * KEY_TABLE: Use per-client pairwise KEY table.
1275 * KEY_INDEX:
1276 * Key index (0~31) to the pairwise KEY table.
1277 * 0~3 to shared KEY table 0 (BSS0).
1278 * 4~7 to shared KEY table 1 (BSS1).
1279 * 8~11 to shared KEY table 2 (BSS2).
1280 * 12~15 to shared KEY table 3 (BSS3).
1281 * BURST: Next frame belongs to same "burst" event.
1282 */
1283 #define TXD_W0_OWNER_NIC FIELD32(0x00000001)
1284 #define TXD_W0_VALID FIELD32(0x00000002)
1285 #define TXD_W0_MORE_FRAG FIELD32(0x00000004)
1286 #define TXD_W0_ACK FIELD32(0x00000008)
1287 #define TXD_W0_TIMESTAMP FIELD32(0x00000010)
1288 #define TXD_W0_OFDM FIELD32(0x00000020)
1289 #define TXD_W0_IFS FIELD32(0x00000040)
1290 #define TXD_W0_RETRY_MODE FIELD32(0x00000080)
1291 #define TXD_W0_TKIP_MIC FIELD32(0x00000100)
1292 #define TXD_W0_KEY_TABLE FIELD32(0x00000200)
1293 #define TXD_W0_KEY_INDEX FIELD32(0x0000fc00)
1294 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1295 #define TXD_W0_BURST FIELD32(0x10000000)
1296 #define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1297
1298 /*
1299 * Word1
1300 * HOST_Q_ID: EDCA/HCCA queue ID.
1301 * HW_SEQUENCE: MAC overwrites the frame sequence number.
1302 * BUFFER_COUNT: Number of buffers in this TXD.
1303 */
1304 #define TXD_W1_HOST_Q_ID FIELD32(0x0000000f)
1305 #define TXD_W1_AIFSN FIELD32(0x000000f0)
1306 #define TXD_W1_CWMIN FIELD32(0x00000f00)
1307 #define TXD_W1_CWMAX FIELD32(0x0000f000)
1308 #define TXD_W1_IV_OFFSET FIELD32(0x003f0000)
1309 #define TXD_W1_PIGGY_BACK FIELD32(0x01000000)
1310 #define TXD_W1_HW_SEQUENCE FIELD32(0x10000000)
1311 #define TXD_W1_BUFFER_COUNT FIELD32(0xe0000000)
1312
1313 /*
1314 * Word2: PLCP information
1315 */
1316 #define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
1317 #define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
1318 #define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
1319 #define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
1320
1321 /*
1322 * Word3
1323 */
1324 #define TXD_W3_IV FIELD32(0xffffffff)
1325
1326 /*
1327 * Word4
1328 */
1329 #define TXD_W4_EIV FIELD32(0xffffffff)
1330
1331 /*
1332 * Word5
1333 * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field).
1334 * TXD_W5_PID_SUBTYPE: Driver assigned packet ID index for txdone handler.
1335 * TXD_W5_PID_TYPE: Driver assigned packet ID type for txdone handler.
1336 * WAITING_DMA_DONE_INT: TXD been filled with data
1337 * and waiting for TxDoneISR housekeeping.
1338 */
1339 #define TXD_W5_FRAME_OFFSET FIELD32(0x000000ff)
1340 #define TXD_W5_PID_SUBTYPE FIELD32(0x00001f00)
1341 #define TXD_W5_PID_TYPE FIELD32(0x0000e000)
1342 #define TXD_W5_TX_POWER FIELD32(0x00ff0000)
1343 #define TXD_W5_WAITING_DMA_DONE_INT FIELD32(0x01000000)
1344
1345 /*
1346 * the above 24-byte is called TXINFO and will be DMAed to MAC block
1347 * through TXFIFO. MAC block use this TXINFO to control the transmission
1348 * behavior of this frame.
1349 * The following fields are not used by MAC block.
1350 * They are used by DMA block and HOST driver only.
1351 * Once a frame has been DMA to ASIC, all the following fields are useless
1352 * to ASIC.
1353 */
1354
1355 /*
1356 * Word6-10: Buffer physical address
1357 */
1358 #define TXD_W6_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1359 #define TXD_W7_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1360 #define TXD_W8_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1361 #define TXD_W9_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1362 #define TXD_W10_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1363
1364 /*
1365 * Word11-13: Buffer length
1366 */
1367 #define TXD_W11_BUFFER_LENGTH0 FIELD32(0x00000fff)
1368 #define TXD_W11_BUFFER_LENGTH1 FIELD32(0x0fff0000)
1369 #define TXD_W12_BUFFER_LENGTH2 FIELD32(0x00000fff)
1370 #define TXD_W12_BUFFER_LENGTH3 FIELD32(0x0fff0000)
1371 #define TXD_W13_BUFFER_LENGTH4 FIELD32(0x00000fff)
1372
1373 /*
1374 * Word14
1375 */
1376 #define TXD_W14_SK_BUFFER FIELD32(0xffffffff)
1377
1378 /*
1379 * Word15
1380 */
1381 #define TXD_W15_NEXT_SK_BUFFER FIELD32(0xffffffff)
1382
1383 /*
1384 * RX descriptor format for RX Ring.
1385 */
1386
1387 /*
1388 * Word0
1389 * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key.
1390 * KEY_INDEX: Decryption key actually used.
1391 */
1392 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
1393 #define RXD_W0_DROP FIELD32(0x00000002)
1394 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000004)
1395 #define RXD_W0_MULTICAST FIELD32(0x00000008)
1396 #define RXD_W0_BROADCAST FIELD32(0x00000010)
1397 #define RXD_W0_MY_BSS FIELD32(0x00000020)
1398 #define RXD_W0_CRC_ERROR FIELD32(0x00000040)
1399 #define RXD_W0_OFDM FIELD32(0x00000080)
1400 #define RXD_W0_CIPHER_ERROR FIELD32(0x00000300)
1401 #define RXD_W0_KEY_INDEX FIELD32(0x0000fc00)
1402 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1403 #define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1404
1405 /*
1406 * Word1
1407 * SIGNAL: RX raw data rate reported by BBP.
1408 */
1409 #define RXD_W1_SIGNAL FIELD32(0x000000ff)
1410 #define RXD_W1_RSSI_AGC FIELD32(0x00001f00)
1411 #define RXD_W1_RSSI_LNA FIELD32(0x00006000)
1412 #define RXD_W1_FRAME_OFFSET FIELD32(0x7f000000)
1413
1414 /*
1415 * Word2
1416 * IV: Received IV of originally encrypted.
1417 */
1418 #define RXD_W2_IV FIELD32(0xffffffff)
1419
1420 /*
1421 * Word3
1422 * EIV: Received EIV of originally encrypted.
1423 */
1424 #define RXD_W3_EIV FIELD32(0xffffffff)
1425
1426 /*
1427 * Word4
1428 */
1429 #define RXD_W4_RESERVED FIELD32(0xffffffff)
1430
1431 /*
1432 * the above 20-byte is called RXINFO and will be DMAed to MAC RX block
1433 * and passed to the HOST driver.
1434 * The following fields are for DMA block and HOST usage only.
1435 * Can't be touched by ASIC MAC block.
1436 */
1437
1438 /*
1439 * Word5
1440 */
1441 #define RXD_W5_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1442
1443 /*
1444 * Word6-15: Reserved
1445 */
1446 #define RXD_W6_RESERVED FIELD32(0xffffffff)
1447 #define RXD_W7_RESERVED FIELD32(0xffffffff)
1448 #define RXD_W8_RESERVED FIELD32(0xffffffff)
1449 #define RXD_W9_RESERVED FIELD32(0xffffffff)
1450 #define RXD_W10_RESERVED FIELD32(0xffffffff)
1451 #define RXD_W11_RESERVED FIELD32(0xffffffff)
1452 #define RXD_W12_RESERVED FIELD32(0xffffffff)
1453 #define RXD_W13_RESERVED FIELD32(0xffffffff)
1454 #define RXD_W14_RESERVED FIELD32(0xffffffff)
1455 #define RXD_W15_RESERVED FIELD32(0xffffffff)
1456
1457 /*
1458 * Macro's for converting txpower from EEPROM to dscape value
1459 * and from dscape value to register value.
1460 */
1461 #define MIN_TXPOWER 0
1462 #define MAX_TXPOWER 31
1463 #define DEFAULT_TXPOWER 24
1464
1465 #define TXPOWER_FROM_DEV(__txpower) \
1466 ({ \
1467 ((__txpower) > MAX_TXPOWER) ? \
1468 DEFAULT_TXPOWER : (__txpower); \
1469 })
1470
1471 #define TXPOWER_TO_DEV(__txpower) \
1472 ({ \
1473 ((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER : \
1474 (((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER : \
1475 (__txpower)); \
1476 })
1477
1478 #endif /* RT61PCI_H */
AMDTP streaming driver for the Linux FireWire stack (Juju)