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[PATCH] Kprobes/IA64: fix race when break hits and kprobe not found
[firewire-audio.git] / arch / ia64 / kernel / ptrace.c
blobbbb8bc7c0552cdb860a466df3e302698b35da58c
1 /*
2 * Kernel support for the ptrace() and syscall tracing interfaces.
3 *
4 * Copyright (C) 1999-2005 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
6 *
7 * Derived from the x86 and Alpha versions.
8 */
9 #include <linux/config.h>
10 #include <linux/kernel.h>
11 #include <linux/sched.h>
12 #include <linux/slab.h>
13 #include <linux/mm.h>
14 #include <linux/errno.h>
15 #include <linux/ptrace.h>
16 #include <linux/smp_lock.h>
17 #include <linux/user.h>
18 #include <linux/security.h>
19 #include <linux/audit.h>
20 #include <linux/signal.h>
21
22 #include <asm/pgtable.h>
23 #include <asm/processor.h>
24 #include <asm/ptrace_offsets.h>
25 #include <asm/rse.h>
26 #include <asm/system.h>
27 #include <asm/uaccess.h>
28 #include <asm/unwind.h>
29 #ifdef CONFIG_PERFMON
30 #include <asm/perfmon.h>
31 #endif
32
33 #include "entry.h"
34
35 /*
36 * Bits in the PSR that we allow ptrace() to change:
37 * be, up, ac, mfl, mfh (the user mask; five bits total)
38 * db (debug breakpoint fault; one bit)
39 * id (instruction debug fault disable; one bit)
40 * dd (data debug fault disable; one bit)
41 * ri (restart instruction; two bits)
42 * is (instruction set; one bit)
43 */
44 #define IPSR_MASK (IA64_PSR_UM | IA64_PSR_DB | IA64_PSR_IS \
45 | IA64_PSR_ID | IA64_PSR_DD | IA64_PSR_RI)
46
47 #define MASK(nbits) ((1UL << (nbits)) - 1) /* mask with NBITS bits set */
48 #define PFM_MASK MASK(38)
49
50 #define PTRACE_DEBUG 0
51
52 #if PTRACE_DEBUG
53 # define dprintk(format...) printk(format)
54 # define inline
55 #else
56 # define dprintk(format...)
57 #endif
58
59 /* Return TRUE if PT was created due to kernel-entry via a system-call. */
60
61 static inline int
62 in_syscall (struct pt_regs *pt)
63 {
64 return (long) pt->cr_ifs >= 0;
65 }
66
67 /*
68 * Collect the NaT bits for r1-r31 from scratch_unat and return a NaT
69 * bitset where bit i is set iff the NaT bit of register i is set.
70 */
71 unsigned long
72 ia64_get_scratch_nat_bits (struct pt_regs *pt, unsigned long scratch_unat)
73 {
74 # define GET_BITS(first, last, unat) \
75 ({ \
76 unsigned long bit = ia64_unat_pos(&pt->r##first); \
77 unsigned long nbits = (last - first + 1); \
78 unsigned long mask = MASK(nbits) << first; \
79 unsigned long dist; \
80 if (bit < first) \
81 dist = 64 + bit - first; \
82 else \
83 dist = bit - first; \
84 ia64_rotr(unat, dist) & mask; \
85 })
86 unsigned long val;
87
88 /*
89 * Registers that are stored consecutively in struct pt_regs
90 * can be handled in parallel. If the register order in
91 * struct_pt_regs changes, this code MUST be updated.
92 */
93 val = GET_BITS( 1, 1, scratch_unat);
94 val |= GET_BITS( 2, 3, scratch_unat);
95 val |= GET_BITS(12, 13, scratch_unat);
96 val |= GET_BITS(14, 14, scratch_unat);
97 val |= GET_BITS(15, 15, scratch_unat);
98 val |= GET_BITS( 8, 11, scratch_unat);
99 val |= GET_BITS(16, 31, scratch_unat);
100 return val;
101
102 # undef GET_BITS
103 }
104
105 /*
106 * Set the NaT bits for the scratch registers according to NAT and
107 * return the resulting unat (assuming the scratch registers are
108 * stored in PT).
109 */
110 unsigned long
111 ia64_put_scratch_nat_bits (struct pt_regs *pt, unsigned long nat)
112 {
113 # define PUT_BITS(first, last, nat) \
114 ({ \
115 unsigned long bit = ia64_unat_pos(&pt->r##first); \
116 unsigned long nbits = (last - first + 1); \
117 unsigned long mask = MASK(nbits) << first; \
118 long dist; \
119 if (bit < first) \
120 dist = 64 + bit - first; \
121 else \
122 dist = bit - first; \
123 ia64_rotl(nat & mask, dist); \
124 })
125 unsigned long scratch_unat;
126
127 /*
128 * Registers that are stored consecutively in struct pt_regs
129 * can be handled in parallel. If the register order in
130 * struct_pt_regs changes, this code MUST be updated.
131 */
132 scratch_unat = PUT_BITS( 1, 1, nat);
133 scratch_unat |= PUT_BITS( 2, 3, nat);
134 scratch_unat |= PUT_BITS(12, 13, nat);
135 scratch_unat |= PUT_BITS(14, 14, nat);
136 scratch_unat |= PUT_BITS(15, 15, nat);
137 scratch_unat |= PUT_BITS( 8, 11, nat);
138 scratch_unat |= PUT_BITS(16, 31, nat);
139
140 return scratch_unat;
141
142 # undef PUT_BITS
143 }
144
145 #define IA64_MLX_TEMPLATE 0x2
146 #define IA64_MOVL_OPCODE 6
147
148 void
149 ia64_increment_ip (struct pt_regs *regs)
150 {
151 unsigned long w0, ri = ia64_psr(regs)->ri + 1;
152
153 if (ri > 2) {
154 ri = 0;
155 regs->cr_iip += 16;
156 } else if (ri == 2) {
157 get_user(w0, (char __user *) regs->cr_iip + 0);
158 if (((w0 >> 1) & 0xf) == IA64_MLX_TEMPLATE) {
159 /*
160 * rfi'ing to slot 2 of an MLX bundle causes
161 * an illegal operation fault. We don't want
162 * that to happen...
163 */
164 ri = 0;
165 regs->cr_iip += 16;
166 }
167 }
168 ia64_psr(regs)->ri = ri;
169 }
170
171 void
172 ia64_decrement_ip (struct pt_regs *regs)
173 {
174 unsigned long w0, ri = ia64_psr(regs)->ri - 1;
175
176 if (ia64_psr(regs)->ri == 0) {
177 regs->cr_iip -= 16;
178 ri = 2;
179 get_user(w0, (char __user *) regs->cr_iip + 0);
180 if (((w0 >> 1) & 0xf) == IA64_MLX_TEMPLATE) {
181 /*
182 * rfi'ing to slot 2 of an MLX bundle causes
183 * an illegal operation fault. We don't want
184 * that to happen...
185 */
186 ri = 1;
187 }
188 }
189 ia64_psr(regs)->ri = ri;
190 }
191
192 /*
193 * This routine is used to read an rnat bits that are stored on the
194 * kernel backing store. Since, in general, the alignment of the user
195 * and kernel are different, this is not completely trivial. In
196 * essence, we need to construct the user RNAT based on up to two
197 * kernel RNAT values and/or the RNAT value saved in the child's
198 * pt_regs.
199 *
200 * user rbs
201 *
202 * +--------+ <-- lowest address
203 * | slot62 |
204 * +--------+
205 * | rnat | 0x....1f8
206 * +--------+
207 * | slot00 | \
208 * +--------+ |
209 * | slot01 | > child_regs->ar_rnat
210 * +--------+ |
211 * | slot02 | / kernel rbs
212 * +--------+ +--------+
213 * <- child_regs->ar_bspstore | slot61 | <-- krbs
214 * +- - - - + +--------+
215 * | slot62 |
216 * +- - - - + +--------+
217 * | rnat |
218 * +- - - - + +--------+
219 * vrnat | slot00 |
220 * +- - - - + +--------+
221 * = =
222 * +--------+
223 * | slot00 | \
224 * +--------+ |
225 * | slot01 | > child_stack->ar_rnat
226 * +--------+ |
227 * | slot02 | /
228 * +--------+
229 * <--- child_stack->ar_bspstore
230 *
231 * The way to think of this code is as follows: bit 0 in the user rnat
232 * corresponds to some bit N (0 <= N <= 62) in one of the kernel rnat
233 * value. The kernel rnat value holding this bit is stored in
234 * variable rnat0. rnat1 is loaded with the kernel rnat value that
235 * form the upper bits of the user rnat value.
236 *
237 * Boundary cases:
238 *
239 * o when reading the rnat "below" the first rnat slot on the kernel
240 * backing store, rnat0/rnat1 are set to 0 and the low order bits are
241 * merged in from pt->ar_rnat.
242 *
243 * o when reading the rnat "above" the last rnat slot on the kernel
244 * backing store, rnat0/rnat1 gets its value from sw->ar_rnat.
245 */
246 static unsigned long
247 get_rnat (struct task_struct *task, struct switch_stack *sw,
248 unsigned long *krbs, unsigned long *urnat_addr,
249 unsigned long *urbs_end)
250 {
251 unsigned long rnat0 = 0, rnat1 = 0, urnat = 0, *slot0_kaddr;
252 unsigned long umask = 0, mask, m;
253 unsigned long *kbsp, *ubspstore, *rnat0_kaddr, *rnat1_kaddr, shift;
254 long num_regs, nbits;
255 struct pt_regs *pt;
256
257 pt = ia64_task_regs(task);
258 kbsp = (unsigned long *) sw->ar_bspstore;
259 ubspstore = (unsigned long *) pt->ar_bspstore;
260
261 if (urbs_end < urnat_addr)
262 nbits = ia64_rse_num_regs(urnat_addr - 63, urbs_end);
263 else
264 nbits = 63;
265 mask = MASK(nbits);
266 /*
267 * First, figure out which bit number slot 0 in user-land maps
268 * to in the kernel rnat. Do this by figuring out how many
269 * register slots we're beyond the user's backingstore and
270 * then computing the equivalent address in kernel space.
271 */
272 num_regs = ia64_rse_num_regs(ubspstore, urnat_addr + 1);
273 slot0_kaddr = ia64_rse_skip_regs(krbs, num_regs);
274 shift = ia64_rse_slot_num(slot0_kaddr);
275 rnat1_kaddr = ia64_rse_rnat_addr(slot0_kaddr);
276 rnat0_kaddr = rnat1_kaddr - 64;
277
278 if (ubspstore + 63 > urnat_addr) {
279 /* some bits need to be merged in from pt->ar_rnat */
280 umask = MASK(ia64_rse_slot_num(ubspstore)) & mask;
281 urnat = (pt->ar_rnat & umask);
282 mask &= ~umask;
283 if (!mask)
284 return urnat;
285 }
286
287 m = mask << shift;
288 if (rnat0_kaddr >= kbsp)
289 rnat0 = sw->ar_rnat;
290 else if (rnat0_kaddr > krbs)
291 rnat0 = *rnat0_kaddr;
292 urnat |= (rnat0 & m) >> shift;
293
294 m = mask >> (63 - shift);
295 if (rnat1_kaddr >= kbsp)
296 rnat1 = sw->ar_rnat;
297 else if (rnat1_kaddr > krbs)
298 rnat1 = *rnat1_kaddr;
299 urnat |= (rnat1 & m) << (63 - shift);
300 return urnat;
301 }
302
303 /*
304 * The reverse of get_rnat.
305 */
306 static void
307 put_rnat (struct task_struct *task, struct switch_stack *sw,
308 unsigned long *krbs, unsigned long *urnat_addr, unsigned long urnat,
309 unsigned long *urbs_end)
310 {
311 unsigned long rnat0 = 0, rnat1 = 0, *slot0_kaddr, umask = 0, mask, m;
312 unsigned long *kbsp, *ubspstore, *rnat0_kaddr, *rnat1_kaddr, shift;
313 long num_regs, nbits;
314 struct pt_regs *pt;
315 unsigned long cfm, *urbs_kargs;
316
317 pt = ia64_task_regs(task);
318 kbsp = (unsigned long *) sw->ar_bspstore;
319 ubspstore = (unsigned long *) pt->ar_bspstore;
320
321 urbs_kargs = urbs_end;
322 if (in_syscall(pt)) {
323 /*
324 * If entered via syscall, don't allow user to set rnat bits
325 * for syscall args.
326 */
327 cfm = pt->cr_ifs;
328 urbs_kargs = ia64_rse_skip_regs(urbs_end, -(cfm & 0x7f));
329 }
330
331 if (urbs_kargs >= urnat_addr)
332 nbits = 63;
333 else {
334 if ((urnat_addr - 63) >= urbs_kargs)
335 return;
336 nbits = ia64_rse_num_regs(urnat_addr - 63, urbs_kargs);
337 }
338 mask = MASK(nbits);
339
340 /*
341 * First, figure out which bit number slot 0 in user-land maps
342 * to in the kernel rnat. Do this by figuring out how many
343 * register slots we're beyond the user's backingstore and
344 * then computing the equivalent address in kernel space.
345 */
346 num_regs = ia64_rse_num_regs(ubspstore, urnat_addr + 1);
347 slot0_kaddr = ia64_rse_skip_regs(krbs, num_regs);
348 shift = ia64_rse_slot_num(slot0_kaddr);
349 rnat1_kaddr = ia64_rse_rnat_addr(slot0_kaddr);
350 rnat0_kaddr = rnat1_kaddr - 64;
351
352 if (ubspstore + 63 > urnat_addr) {
353 /* some bits need to be place in pt->ar_rnat: */
354 umask = MASK(ia64_rse_slot_num(ubspstore)) & mask;
355 pt->ar_rnat = (pt->ar_rnat & ~umask) | (urnat & umask);
356 mask &= ~umask;
357 if (!mask)
358 return;
359 }
360 /*
361 * Note: Section 11.1 of the EAS guarantees that bit 63 of an
362 * rnat slot is ignored. so we don't have to clear it here.
363 */
364 rnat0 = (urnat << shift);
365 m = mask << shift;
366 if (rnat0_kaddr >= kbsp)
367 sw->ar_rnat = (sw->ar_rnat & ~m) | (rnat0 & m);
368 else if (rnat0_kaddr > krbs)
369 *rnat0_kaddr = ((*rnat0_kaddr & ~m) | (rnat0 & m));
370
371 rnat1 = (urnat >> (63 - shift));
372 m = mask >> (63 - shift);
373 if (rnat1_kaddr >= kbsp)
374 sw->ar_rnat = (sw->ar_rnat & ~m) | (rnat1 & m);
375 else if (rnat1_kaddr > krbs)
376 *rnat1_kaddr = ((*rnat1_kaddr & ~m) | (rnat1 & m));
377 }
378
379 static inline int
380 on_kernel_rbs (unsigned long addr, unsigned long bspstore,
381 unsigned long urbs_end)
382 {
383 unsigned long *rnat_addr = ia64_rse_rnat_addr((unsigned long *)
384 urbs_end);
385 return (addr >= bspstore && addr <= (unsigned long) rnat_addr);
386 }
387
388 /*
389 * Read a word from the user-level backing store of task CHILD. ADDR
390 * is the user-level address to read the word from, VAL a pointer to
391 * the return value, and USER_BSP gives the end of the user-level
392 * backing store (i.e., it's the address that would be in ar.bsp after
393 * the user executed a "cover" instruction).
394 *
395 * This routine takes care of accessing the kernel register backing
396 * store for those registers that got spilled there. It also takes
397 * care of calculating the appropriate RNaT collection words.
398 */
399 long
400 ia64_peek (struct task_struct *child, struct switch_stack *child_stack,
401 unsigned long user_rbs_end, unsigned long addr, long *val)
402 {
403 unsigned long *bspstore, *krbs, regnum, *laddr, *urbs_end, *rnat_addr;
404 struct pt_regs *child_regs;
405 size_t copied;
406 long ret;
407
408 urbs_end = (long *) user_rbs_end;
409 laddr = (unsigned long *) addr;
410 child_regs = ia64_task_regs(child);
411 bspstore = (unsigned long *) child_regs->ar_bspstore;
412 krbs = (unsigned long *) child + IA64_RBS_OFFSET/8;
413 if (on_kernel_rbs(addr, (unsigned long) bspstore,
414 (unsigned long) urbs_end))
415 {
416 /*
417 * Attempt to read the RBS in an area that's actually
418 * on the kernel RBS => read the corresponding bits in
419 * the kernel RBS.
420 */
421 rnat_addr = ia64_rse_rnat_addr(laddr);
422 ret = get_rnat(child, child_stack, krbs, rnat_addr, urbs_end);
423
424 if (laddr == rnat_addr) {
425 /* return NaT collection word itself */
426 *val = ret;
427 return 0;
428 }
429
430 if (((1UL << ia64_rse_slot_num(laddr)) & ret) != 0) {
431 /*
432 * It is implementation dependent whether the
433 * data portion of a NaT value gets saved on a
434 * st8.spill or RSE spill (e.g., see EAS 2.6,
435 * 4.4.4.6 Register Spill and Fill). To get
436 * consistent behavior across all possible
437 * IA-64 implementations, we return zero in
438 * this case.
439 */
440 *val = 0;
441 return 0;
442 }
443
444 if (laddr < urbs_end) {
445 /*
446 * The desired word is on the kernel RBS and
447 * is not a NaT.
448 */
449 regnum = ia64_rse_num_regs(bspstore, laddr);
450 *val = *ia64_rse_skip_regs(krbs, regnum);
451 return 0;
452 }
453 }
454 copied = access_process_vm(child, addr, &ret, sizeof(ret), 0);
455 if (copied != sizeof(ret))
456 return -EIO;
457 *val = ret;
458 return 0;
459 }
460
461 long
462 ia64_poke (struct task_struct *child, struct switch_stack *child_stack,
463 unsigned long user_rbs_end, unsigned long addr, long val)
464 {
465 unsigned long *bspstore, *krbs, regnum, *laddr;
466 unsigned long *urbs_end = (long *) user_rbs_end;
467 struct pt_regs *child_regs;
468
469 laddr = (unsigned long *) addr;
470 child_regs = ia64_task_regs(child);
471 bspstore = (unsigned long *) child_regs->ar_bspstore;
472 krbs = (unsigned long *) child + IA64_RBS_OFFSET/8;
473 if (on_kernel_rbs(addr, (unsigned long) bspstore,
474 (unsigned long) urbs_end))
475 {
476 /*
477 * Attempt to write the RBS in an area that's actually
478 * on the kernel RBS => write the corresponding bits
479 * in the kernel RBS.
480 */
481 if (ia64_rse_is_rnat_slot(laddr))
482 put_rnat(child, child_stack, krbs, laddr, val,
483 urbs_end);
484 else {
485 if (laddr < urbs_end) {
486 regnum = ia64_rse_num_regs(bspstore, laddr);
487 *ia64_rse_skip_regs(krbs, regnum) = val;
488 }
489 }
490 } else if (access_process_vm(child, addr, &val, sizeof(val), 1)
491 != sizeof(val))
492 return -EIO;
493 return 0;
494 }
495
496 /*
497 * Calculate the address of the end of the user-level register backing
498 * store. This is the address that would have been stored in ar.bsp
499 * if the user had executed a "cover" instruction right before
500 * entering the kernel. If CFMP is not NULL, it is used to return the
501 * "current frame mask" that was active at the time the kernel was
502 * entered.
503 */
504 unsigned long
505 ia64_get_user_rbs_end (struct task_struct *child, struct pt_regs *pt,
506 unsigned long *cfmp)
507 {
508 unsigned long *krbs, *bspstore, cfm = pt->cr_ifs;
509 long ndirty;
510
511 krbs = (unsigned long *) child + IA64_RBS_OFFSET/8;
512 bspstore = (unsigned long *) pt->ar_bspstore;
513 ndirty = ia64_rse_num_regs(krbs, krbs + (pt->loadrs >> 19));
514
515 if (in_syscall(pt))
516 ndirty += (cfm & 0x7f);
517 else
518 cfm &= ~(1UL << 63); /* clear valid bit */
519
520 if (cfmp)
521 *cfmp = cfm;
522 return (unsigned long) ia64_rse_skip_regs(bspstore, ndirty);
523 }
524
525 /*
526 * Synchronize (i.e, write) the RSE backing store living in kernel
527 * space to the VM of the CHILD task. SW and PT are the pointers to
528 * the switch_stack and pt_regs structures, respectively.
529 * USER_RBS_END is the user-level address at which the backing store
530 * ends.
531 */
532 long
533 ia64_sync_user_rbs (struct task_struct *child, struct switch_stack *sw,
534 unsigned long user_rbs_start, unsigned long user_rbs_end)
535 {
536 unsigned long addr, val;
537 long ret;
538
539 /* now copy word for word from kernel rbs to user rbs: */
540 for (addr = user_rbs_start; addr < user_rbs_end; addr += 8) {
541 ret = ia64_peek(child, sw, user_rbs_end, addr, &val);
542 if (ret < 0)
543 return ret;
544 if (access_process_vm(child, addr, &val, sizeof(val), 1)
545 != sizeof(val))
546 return -EIO;
547 }
548 return 0;
549 }
550
551 static inline int
552 thread_matches (struct task_struct *thread, unsigned long addr)
553 {
554 unsigned long thread_rbs_end;
555 struct pt_regs *thread_regs;
556
557 if (ptrace_check_attach(thread, 0) < 0)
558 /*
559 * If the thread is not in an attachable state, we'll
560 * ignore it. The net effect is that if ADDR happens
561 * to overlap with the portion of the thread's
562 * register backing store that is currently residing
563 * on the thread's kernel stack, then ptrace() may end
564 * up accessing a stale value. But if the thread
565 * isn't stopped, that's a problem anyhow, so we're
566 * doing as well as we can...
567 */
568 return 0;
569
570 thread_regs = ia64_task_regs(thread);
571 thread_rbs_end = ia64_get_user_rbs_end(thread, thread_regs, NULL);
572 if (!on_kernel_rbs(addr, thread_regs->ar_bspstore, thread_rbs_end))
573 return 0;
574
575 return 1; /* looks like we've got a winner */
576 }
577
578 /*
579 * GDB apparently wants to be able to read the register-backing store
580 * of any thread when attached to a given process. If we are peeking
581 * or poking an address that happens to reside in the kernel-backing
582 * store of another thread, we need to attach to that thread, because
583 * otherwise we end up accessing stale data.
584 *
585 * task_list_lock must be read-locked before calling this routine!
586 */
587 static struct task_struct *
588 find_thread_for_addr (struct task_struct *child, unsigned long addr)
589 {
590 struct task_struct *g, *p;
591 struct mm_struct *mm;
592 int mm_users;
593
594 if (!(mm = get_task_mm(child)))
595 return child;
596
597 /* -1 because of our get_task_mm(): */
598 mm_users = atomic_read(&mm->mm_users) - 1;
599 if (mm_users <= 1)
600 goto out; /* not multi-threaded */
601
602 /*
603 * First, traverse the child's thread-list. Good for scalability with
604 * NPTL-threads.
605 */
606 p = child;
607 do {
608 if (thread_matches(p, addr)) {
609 child = p;
610 goto out;
611 }
612 if (mm_users-- <= 1)
613 goto out;
614 } while ((p = next_thread(p)) != child);
615
616 do_each_thread(g, p) {
617 if (child->mm != mm)
618 continue;
619
620 if (thread_matches(p, addr)) {
621 child = p;
622 goto out;
623 }
624 } while_each_thread(g, p);
625 out:
626 mmput(mm);
627 return child;
628 }
629
630 /*
631 * Write f32-f127 back to task->thread.fph if it has been modified.
632 */
633 inline void
634 ia64_flush_fph (struct task_struct *task)
635 {
636 struct ia64_psr *psr = ia64_psr(ia64_task_regs(task));
637
638 /*
639 * Prevent migrating this task while
640 * we're fiddling with the FPU state
641 */
642 preempt_disable();
643 if (ia64_is_local_fpu_owner(task) && psr->mfh) {
644 psr->mfh = 0;
645 task->thread.flags |= IA64_THREAD_FPH_VALID;
646 ia64_save_fpu(&task->thread.fph[0]);
647 }
648 preempt_enable();
649 }
650
651 /*
652 * Sync the fph state of the task so that it can be manipulated
653 * through thread.fph. If necessary, f32-f127 are written back to
654 * thread.fph or, if the fph state hasn't been used before, thread.fph
655 * is cleared to zeroes. Also, access to f32-f127 is disabled to
656 * ensure that the task picks up the state from thread.fph when it
657 * executes again.
658 */
659 void
660 ia64_sync_fph (struct task_struct *task)
661 {
662 struct ia64_psr *psr = ia64_psr(ia64_task_regs(task));
663
664 ia64_flush_fph(task);
665 if (!(task->thread.flags & IA64_THREAD_FPH_VALID)) {
666 task->thread.flags |= IA64_THREAD_FPH_VALID;
667 memset(&task->thread.fph, 0, sizeof(task->thread.fph));
668 }
669 ia64_drop_fpu(task);
670 psr->dfh = 1;
671 }
672
673 static int
674 access_fr (struct unw_frame_info *info, int regnum, int hi,
675 unsigned long *data, int write_access)
676 {
677 struct ia64_fpreg fpval;
678 int ret;
679
680 ret = unw_get_fr(info, regnum, &fpval);
681 if (ret < 0)
682 return ret;
683
684 if (write_access) {
685 fpval.u.bits[hi] = *data;
686 ret = unw_set_fr(info, regnum, fpval);
687 } else
688 *data = fpval.u.bits[hi];
689 return ret;
690 }
691
692 /*
693 * Change the machine-state of CHILD such that it will return via the normal
694 * kernel exit-path, rather than the syscall-exit path.
695 */
696 static void
697 convert_to_non_syscall (struct task_struct *child, struct pt_regs *pt,
698 unsigned long cfm)
699 {
700 struct unw_frame_info info, prev_info;
701 unsigned long ip, sp, pr;
702
703 unw_init_from_blocked_task(&info, child);
704 while (1) {
705 prev_info = info;
706 if (unw_unwind(&info) < 0)
707 return;
708
709 unw_get_sp(&info, &sp);
710 if ((long)((unsigned long)child + IA64_STK_OFFSET - sp)
711 < IA64_PT_REGS_SIZE) {
712 dprintk("ptrace.%s: ran off the top of the kernel "
713 "stack\n", __FUNCTION__);
714 return;
715 }
716 if (unw_get_pr (&prev_info, &pr) < 0) {
717 unw_get_rp(&prev_info, &ip);
718 dprintk("ptrace.%s: failed to read "
719 "predicate register (ip=0x%lx)\n",
720 __FUNCTION__, ip);
721 return;
722 }
723 if (unw_is_intr_frame(&info)
724 && (pr & (1UL << PRED_USER_STACK)))
725 break;
726 }
727
728 /*
729 * Note: at the time of this call, the target task is blocked
730 * in notify_resume_user() and by clearling PRED_LEAVE_SYSCALL
731 * (aka, "pLvSys") we redirect execution from
732 * .work_pending_syscall_end to .work_processed_kernel.
733 */
734 unw_get_pr(&prev_info, &pr);
735 pr &= ~((1UL << PRED_SYSCALL) | (1UL << PRED_LEAVE_SYSCALL));
736 pr |= (1UL << PRED_NON_SYSCALL);
737 unw_set_pr(&prev_info, pr);
738
739 pt->cr_ifs = (1UL << 63) | cfm;
740 /*
741 * Clear the memory that is NOT written on syscall-entry to
742 * ensure we do not leak kernel-state to user when execution
743 * resumes.
744 */
745 pt->r2 = 0;
746 pt->r3 = 0;
747 pt->r14 = 0;
748 memset(&pt->r16, 0, 16*8); /* clear r16-r31 */
749 memset(&pt->f6, 0, 6*16); /* clear f6-f11 */
750 pt->b7 = 0;
751 pt->ar_ccv = 0;
752 pt->ar_csd = 0;
753 pt->ar_ssd = 0;
754 }
755
756 static int
757 access_nat_bits (struct task_struct *child, struct pt_regs *pt,
758 struct unw_frame_info *info,
759 unsigned long *data, int write_access)
760 {
761 unsigned long regnum, nat_bits, scratch_unat, dummy = 0;
762 char nat = 0;
763
764 if (write_access) {
765 nat_bits = *data;
766 scratch_unat = ia64_put_scratch_nat_bits(pt, nat_bits);
767 if (unw_set_ar(info, UNW_AR_UNAT, scratch_unat) < 0) {
768 dprintk("ptrace: failed to set ar.unat\n");
769 return -1;
770 }
771 for (regnum = 4; regnum <= 7; ++regnum) {
772 unw_get_gr(info, regnum, &dummy, &nat);
773 unw_set_gr(info, regnum, dummy,
774 (nat_bits >> regnum) & 1);
775 }
776 } else {
777 if (unw_get_ar(info, UNW_AR_UNAT, &scratch_unat) < 0) {
778 dprintk("ptrace: failed to read ar.unat\n");
779 return -1;
780 }
781 nat_bits = ia64_get_scratch_nat_bits(pt, scratch_unat);
782 for (regnum = 4; regnum <= 7; ++regnum) {
783 unw_get_gr(info, regnum, &dummy, &nat);
784 nat_bits |= (nat != 0) << regnum;
785 }
786 *data = nat_bits;
787 }
788 return 0;
789 }
790
791 static int
792 access_uarea (struct task_struct *child, unsigned long addr,
793 unsigned long *data, int write_access)
794 {
795 unsigned long *ptr, regnum, urbs_end, rnat_addr, cfm;
796 struct switch_stack *sw;
797 struct pt_regs *pt;
798 # define pt_reg_addr(pt, reg) ((void *) \
799 ((unsigned long) (pt) \
800 + offsetof(struct pt_regs, reg)))
801
802
803 pt = ia64_task_regs(child);
804 sw = (struct switch_stack *) (child->thread.ksp + 16);
805
806 if ((addr & 0x7) != 0) {
807 dprintk("ptrace: unaligned register address 0x%lx\n", addr);
808 return -1;
809 }
810
811 if (addr < PT_F127 + 16) {
812 /* accessing fph */
813 if (write_access)
814 ia64_sync_fph(child);
815 else
816 ia64_flush_fph(child);
817 ptr = (unsigned long *)
818 ((unsigned long) &child->thread.fph + addr);
819 } else if ((addr >= PT_F10) && (addr < PT_F11 + 16)) {
820 /* scratch registers untouched by kernel (saved in pt_regs) */
821 ptr = pt_reg_addr(pt, f10) + (addr - PT_F10);
822 } else if (addr >= PT_F12 && addr < PT_F15 + 16) {
823 /*
824 * Scratch registers untouched by kernel (saved in
825 * switch_stack).
826 */
827 ptr = (unsigned long *) ((long) sw
828 + (addr - PT_NAT_BITS - 32));
829 } else if (addr < PT_AR_LC + 8) {
830 /* preserved state: */
831 struct unw_frame_info info;
832 char nat = 0;
833 int ret;
834
835 unw_init_from_blocked_task(&info, child);
836 if (unw_unwind_to_user(&info) < 0)
837 return -1;
838
839 switch (addr) {
840 case PT_NAT_BITS:
841 return access_nat_bits(child, pt, &info,
842 data, write_access);
843
844 case PT_R4: case PT_R5: case PT_R6: case PT_R7:
845 if (write_access) {
846 /* read NaT bit first: */
847 unsigned long dummy;
848
849 ret = unw_get_gr(&info, (addr - PT_R4)/8 + 4,
850 &dummy, &nat);
851 if (ret < 0)
852 return ret;
853 }
854 return unw_access_gr(&info, (addr - PT_R4)/8 + 4, data,
855 &nat, write_access);
856
857 case PT_B1: case PT_B2: case PT_B3:
858 case PT_B4: case PT_B5:
859 return unw_access_br(&info, (addr - PT_B1)/8 + 1, data,
860 write_access);
861
862 case PT_AR_EC:
863 return unw_access_ar(&info, UNW_AR_EC, data,
864 write_access);
865
866 case PT_AR_LC:
867 return unw_access_ar(&info, UNW_AR_LC, data,
868 write_access);
869
870 default:
871 if (addr >= PT_F2 && addr < PT_F5 + 16)
872 return access_fr(&info, (addr - PT_F2)/16 + 2,
873 (addr & 8) != 0, data,
874 write_access);
875 else if (addr >= PT_F16 && addr < PT_F31 + 16)
876 return access_fr(&info,
877 (addr - PT_F16)/16 + 16,
878 (addr & 8) != 0,
879 data, write_access);
880 else {
881 dprintk("ptrace: rejecting access to register "
882 "address 0x%lx\n", addr);
883 return -1;
884 }
885 }
886 } else if (addr < PT_F9+16) {
887 /* scratch state */
888 switch (addr) {
889 case PT_AR_BSP:
890 /*
891 * By convention, we use PT_AR_BSP to refer to
892 * the end of the user-level backing store.
893 * Use ia64_rse_skip_regs(PT_AR_BSP, -CFM.sof)
894 * to get the real value of ar.bsp at the time
895 * the kernel was entered.
896 *
897 * Furthermore, when changing the contents of
898 * PT_AR_BSP (or PT_CFM) we MUST copy any
899 * users-level stacked registers that are
900 * stored on the kernel stack back to
901 * user-space because otherwise, we might end
902 * up clobbering kernel stacked registers.
903 * Also, if this happens while the task is
904 * blocked in a system call, which convert the
905 * state such that the non-system-call exit
906 * path is used. This ensures that the proper
907 * state will be picked up when resuming
908 * execution. However, it *also* means that
909 * once we write PT_AR_BSP/PT_CFM, it won't be
910 * possible to modify the syscall arguments of
911 * the pending system call any longer. This
912 * shouldn't be an issue because modifying
913 * PT_AR_BSP/PT_CFM generally implies that
914 * we're either abandoning the pending system
915 * call or that we defer it's re-execution
916 * (e.g., due to GDB doing an inferior
917 * function call).
918 */
919 urbs_end = ia64_get_user_rbs_end(child, pt, &cfm);
920 if (write_access) {
921 if (*data != urbs_end) {
922 if (ia64_sync_user_rbs(child, sw,
923 pt->ar_bspstore,
924 urbs_end) < 0)
925 return -1;
926 if (in_syscall(pt))
927 convert_to_non_syscall(child,
928 pt,
929 cfm);
930 /*
931 * Simulate user-level write
932 * of ar.bsp:
933 */
934 pt->loadrs = 0;
935 pt->ar_bspstore = *data;
936 }
937 } else
938 *data = urbs_end;
939 return 0;
940
941 case PT_CFM:
942 urbs_end = ia64_get_user_rbs_end(child, pt, &cfm);
943 if (write_access) {
944 if (((cfm ^ *data) & PFM_MASK) != 0) {
945 if (ia64_sync_user_rbs(child, sw,
946 pt->ar_bspstore,
947 urbs_end) < 0)
948 return -1;
949 if (in_syscall(pt))
950 convert_to_non_syscall(child,
951 pt,
952 cfm);
953 pt->cr_ifs = ((pt->cr_ifs & ~PFM_MASK)
954 | (*data & PFM_MASK));
955 }
956 } else
957 *data = cfm;
958 return 0;
959
960 case PT_CR_IPSR:
961 if (write_access)
962 pt->cr_ipsr = ((*data & IPSR_MASK)
963 | (pt->cr_ipsr & ~IPSR_MASK));
964 else
965 *data = (pt->cr_ipsr & IPSR_MASK);
966 return 0;
967
968 case PT_AR_RSC:
969 if (write_access)
970 pt->ar_rsc = *data | (3 << 2); /* force PL3 */
971 else
972 *data = pt->ar_rsc;
973 return 0;
974
975 case PT_AR_RNAT:
976 urbs_end = ia64_get_user_rbs_end(child, pt, NULL);
977 rnat_addr = (long) ia64_rse_rnat_addr((long *)
978 urbs_end);
979 if (write_access)
980 return ia64_poke(child, sw, urbs_end,
981 rnat_addr, *data);
982 else
983 return ia64_peek(child, sw, urbs_end,
984 rnat_addr, data);
985
986 case PT_R1:
987 ptr = pt_reg_addr(pt, r1);
988 break;
989 case PT_R2: case PT_R3:
990 ptr = pt_reg_addr(pt, r2) + (addr - PT_R2);
991 break;
992 case PT_R8: case PT_R9: case PT_R10: case PT_R11:
993 ptr = pt_reg_addr(pt, r8) + (addr - PT_R8);
994 break;
995 case PT_R12: case PT_R13:
996 ptr = pt_reg_addr(pt, r12) + (addr - PT_R12);
997 break;
998 case PT_R14:
999 ptr = pt_reg_addr(pt, r14);
1000 break;
1001 case PT_R15:
1002 ptr = pt_reg_addr(pt, r15);
1003 break;
1004 case PT_R16: case PT_R17: case PT_R18: case PT_R19:
1005 case PT_R20: case PT_R21: case PT_R22: case PT_R23:
1006 case PT_R24: case PT_R25: case PT_R26: case PT_R27:
1007 case PT_R28: case PT_R29: case PT_R30: case PT_R31:
1008 ptr = pt_reg_addr(pt, r16) + (addr - PT_R16);
1009 break;
1010 case PT_B0:
1011 ptr = pt_reg_addr(pt, b0);
1012 break;
1013 case PT_B6:
1014 ptr = pt_reg_addr(pt, b6);
1015 break;
1016 case PT_B7:
1017 ptr = pt_reg_addr(pt, b7);
1018 break;
1019 case PT_F6: case PT_F6+8: case PT_F7: case PT_F7+8:
1020 case PT_F8: case PT_F8+8: case PT_F9: case PT_F9+8:
1021 ptr = pt_reg_addr(pt, f6) + (addr - PT_F6);
1022 break;
1023 case PT_AR_BSPSTORE:
1024 ptr = pt_reg_addr(pt, ar_bspstore);
1025 break;
1026 case PT_AR_UNAT:
1027 ptr = pt_reg_addr(pt, ar_unat);
1028 break;
1029 case PT_AR_PFS:
1030 ptr = pt_reg_addr(pt, ar_pfs);
1031 break;
1032 case PT_AR_CCV:
1033 ptr = pt_reg_addr(pt, ar_ccv);
1034 break;
1035 case PT_AR_FPSR:
1036 ptr = pt_reg_addr(pt, ar_fpsr);
1037 break;
1038 case PT_CR_IIP:
1039 ptr = pt_reg_addr(pt, cr_iip);
1040 break;
1041 case PT_PR:
1042 ptr = pt_reg_addr(pt, pr);
1043 break;
1044 /* scratch register */
1045
1046 default:
1047 /* disallow accessing anything else... */
1048 dprintk("ptrace: rejecting access to register "
1049 "address 0x%lx\n", addr);
1050 return -1;
1051 }
1052 } else if (addr <= PT_AR_SSD) {
1053 ptr = pt_reg_addr(pt, ar_csd) + (addr - PT_AR_CSD);
1054 } else {
1055 /* access debug registers */
1056
1057 if (addr >= PT_IBR) {
1058 regnum = (addr - PT_IBR) >> 3;
1059 ptr = &child->thread.ibr[0];
1060 } else {
1061 regnum = (addr - PT_DBR) >> 3;
1062 ptr = &child->thread.dbr[0];
1063 }
1064
1065 if (regnum >= 8) {
1066 dprintk("ptrace: rejecting access to register "
1067 "address 0x%lx\n", addr);
1068 return -1;
1069 }
1070 #ifdef CONFIG_PERFMON
1071 /*
1072 * Check if debug registers are used by perfmon. This
1073 * test must be done once we know that we can do the
1074 * operation, i.e. the arguments are all valid, but
1075 * before we start modifying the state.
1076 *
1077 * Perfmon needs to keep a count of how many processes
1078 * are trying to modify the debug registers for system
1079 * wide monitoring sessions.
1080 *
1081 * We also include read access here, because they may
1082 * cause the PMU-installed debug register state
1083 * (dbr[], ibr[]) to be reset. The two arrays are also
1084 * used by perfmon, but we do not use
1085 * IA64_THREAD_DBG_VALID. The registers are restored
1086 * by the PMU context switch code.
1087 */
1088 if (pfm_use_debug_registers(child)) return -1;
1089 #endif
1090
1091 if (!(child->thread.flags & IA64_THREAD_DBG_VALID)) {
1092 child->thread.flags |= IA64_THREAD_DBG_VALID;
1093 memset(child->thread.dbr, 0,
1094 sizeof(child->thread.dbr));
1095 memset(child->thread.ibr, 0,
1096 sizeof(child->thread.ibr));
1097 }
1098
1099 ptr += regnum;
1100
1101 if ((regnum & 1) && write_access) {
1102 /* don't let the user set kernel-level breakpoints: */
1103 *ptr = *data & ~(7UL << 56);
1104 return 0;
1105 }
1106 }
1107 if (write_access)
1108 *ptr = *data;
1109 else
1110 *data = *ptr;
1111 return 0;
1112 }
1113
1114 static long
1115 ptrace_getregs (struct task_struct *child, struct pt_all_user_regs __user *ppr)
1116 {
1117 unsigned long psr, ec, lc, rnat, bsp, cfm, nat_bits, val;
1118 struct unw_frame_info info;
1119 struct ia64_fpreg fpval;
1120 struct switch_stack *sw;
1121 struct pt_regs *pt;
1122 long ret, retval = 0;
1123 char nat = 0;
1124 int i;
1125
1126 if (!access_ok(VERIFY_WRITE, ppr, sizeof(struct pt_all_user_regs)))
1127 return -EIO;
1128
1129 pt = ia64_task_regs(child);
1130 sw = (struct switch_stack *) (child->thread.ksp + 16);
1131 unw_init_from_blocked_task(&info, child);
1132 if (unw_unwind_to_user(&info) < 0) {
1133 return -EIO;
1134 }
1135
1136 if (((unsigned long) ppr & 0x7) != 0) {
1137 dprintk("ptrace:unaligned register address %p\n", ppr);
1138 return -EIO;
1139 }
1140
1141 if (access_uarea(child, PT_CR_IPSR, &psr, 0) < 0
1142 || access_uarea(child, PT_AR_EC, &ec, 0) < 0
1143 || access_uarea(child, PT_AR_LC, &lc, 0) < 0
1144 || access_uarea(child, PT_AR_RNAT, &rnat, 0) < 0
1145 || access_uarea(child, PT_AR_BSP, &bsp, 0) < 0
1146 || access_uarea(child, PT_CFM, &cfm, 0)
1147 || access_uarea(child, PT_NAT_BITS, &nat_bits, 0))
1148 return -EIO;
1149
1150 /* control regs */
1151
1152 retval |= __put_user(pt->cr_iip, &ppr->cr_iip);
1153 retval |= __put_user(psr, &ppr->cr_ipsr);
1154
1155 /* app regs */
1156
1157 retval |= __put_user(pt->ar_pfs, &ppr->ar[PT_AUR_PFS]);
1158 retval |= __put_user(pt->ar_rsc, &ppr->ar[PT_AUR_RSC]);
1159 retval |= __put_user(pt->ar_bspstore, &ppr->ar[PT_AUR_BSPSTORE]);
1160 retval |= __put_user(pt->ar_unat, &ppr->ar[PT_AUR_UNAT]);
1161 retval |= __put_user(pt->ar_ccv, &ppr->ar[PT_AUR_CCV]);
1162 retval |= __put_user(pt->ar_fpsr, &ppr->ar[PT_AUR_FPSR]);
1163
1164 retval |= __put_user(ec, &ppr->ar[PT_AUR_EC]);
1165 retval |= __put_user(lc, &ppr->ar[PT_AUR_LC]);
1166 retval |= __put_user(rnat, &ppr->ar[PT_AUR_RNAT]);
1167 retval |= __put_user(bsp, &ppr->ar[PT_AUR_BSP]);
1168 retval |= __put_user(cfm, &ppr->cfm);
1169
1170 /* gr1-gr3 */
1171
1172 retval |= __copy_to_user(&ppr->gr[1], &pt->r1, sizeof(long));
1173 retval |= __copy_to_user(&ppr->gr[2], &pt->r2, sizeof(long) *2);
1174
1175 /* gr4-gr7 */
1176
1177 for (i = 4; i < 8; i++) {
1178 if (unw_access_gr(&info, i, &val, &nat, 0) < 0)
1179 return -EIO;
1180 retval |= __put_user(val, &ppr->gr[i]);
1181 }
1182
1183 /* gr8-gr11 */
1184
1185 retval |= __copy_to_user(&ppr->gr[8], &pt->r8, sizeof(long) * 4);
1186
1187 /* gr12-gr15 */
1188
1189 retval |= __copy_to_user(&ppr->gr[12], &pt->r12, sizeof(long) * 2);
1190 retval |= __copy_to_user(&ppr->gr[14], &pt->r14, sizeof(long));
1191 retval |= __copy_to_user(&ppr->gr[15], &pt->r15, sizeof(long));
1192
1193 /* gr16-gr31 */
1194
1195 retval |= __copy_to_user(&ppr->gr[16], &pt->r16, sizeof(long) * 16);
1196
1197 /* b0 */
1198
1199 retval |= __put_user(pt->b0, &ppr->br[0]);
1200
1201 /* b1-b5 */
1202
1203 for (i = 1; i < 6; i++) {
1204 if (unw_access_br(&info, i, &val, 0) < 0)
1205 return -EIO;
1206 __put_user(val, &ppr->br[i]);
1207 }
1208
1209 /* b6-b7 */
1210
1211 retval |= __put_user(pt->b6, &ppr->br[6]);
1212 retval |= __put_user(pt->b7, &ppr->br[7]);
1213
1214 /* fr2-fr5 */
1215
1216 for (i = 2; i < 6; i++) {
1217 if (unw_get_fr(&info, i, &fpval) < 0)
1218 return -EIO;
1219 retval |= __copy_to_user(&ppr->fr[i], &fpval, sizeof (fpval));
1220 }
1221
1222 /* fr6-fr11 */
1223
1224 retval |= __copy_to_user(&ppr->fr[6], &pt->f6,
1225 sizeof(struct ia64_fpreg) * 6);
1226
1227 /* fp scratch regs(12-15) */
1228
1229 retval |= __copy_to_user(&ppr->fr[12], &sw->f12,
1230 sizeof(struct ia64_fpreg) * 4);
1231
1232 /* fr16-fr31 */
1233
1234 for (i = 16; i < 32; i++) {
1235 if (unw_get_fr(&info, i, &fpval) < 0)
1236 return -EIO;
1237 retval |= __copy_to_user(&ppr->fr[i], &fpval, sizeof (fpval));
1238 }
1239
1240 /* fph */
1241
1242 ia64_flush_fph(child);
1243 retval |= __copy_to_user(&ppr->fr[32], &child->thread.fph,
1244 sizeof(ppr->fr[32]) * 96);
1245
1246 /* preds */
1247
1248 retval |= __put_user(pt->pr, &ppr->pr);
1249
1250 /* nat bits */
1251
1252 retval |= __put_user(nat_bits, &ppr->nat);
1253
1254 ret = retval ? -EIO : 0;
1255 return ret;
1256 }
1257
1258 static long
1259 ptrace_setregs (struct task_struct *child, struct pt_all_user_regs __user *ppr)
1260 {
1261 unsigned long psr, rsc, ec, lc, rnat, bsp, cfm, nat_bits, val = 0;
1262 struct unw_frame_info info;
1263 struct switch_stack *sw;
1264 struct ia64_fpreg fpval;
1265 struct pt_regs *pt;
1266 long ret, retval = 0;
1267 int i;
1268
1269 memset(&fpval, 0, sizeof(fpval));
1270
1271 if (!access_ok(VERIFY_READ, ppr, sizeof(struct pt_all_user_regs)))
1272 return -EIO;
1273
1274 pt = ia64_task_regs(child);
1275 sw = (struct switch_stack *) (child->thread.ksp + 16);
1276 unw_init_from_blocked_task(&info, child);
1277 if (unw_unwind_to_user(&info) < 0) {
1278 return -EIO;
1279 }
1280
1281 if (((unsigned long) ppr & 0x7) != 0) {
1282 dprintk("ptrace:unaligned register address %p\n", ppr);
1283 return -EIO;
1284 }
1285
1286 /* control regs */
1287
1288 retval |= __get_user(pt->cr_iip, &ppr->cr_iip);
1289 retval |= __get_user(psr, &ppr->cr_ipsr);
1290
1291 /* app regs */
1292
1293 retval |= __get_user(pt->ar_pfs, &ppr->ar[PT_AUR_PFS]);
1294 retval |= __get_user(rsc, &ppr->ar[PT_AUR_RSC]);
1295 retval |= __get_user(pt->ar_bspstore, &ppr->ar[PT_AUR_BSPSTORE]);
1296 retval |= __get_user(pt->ar_unat, &ppr->ar[PT_AUR_UNAT]);
1297 retval |= __get_user(pt->ar_ccv, &ppr->ar[PT_AUR_CCV]);
1298 retval |= __get_user(pt->ar_fpsr, &ppr->ar[PT_AUR_FPSR]);
1299
1300 retval |= __get_user(ec, &ppr->ar[PT_AUR_EC]);
1301 retval |= __get_user(lc, &ppr->ar[PT_AUR_LC]);
1302 retval |= __get_user(rnat, &ppr->ar[PT_AUR_RNAT]);
1303 retval |= __get_user(bsp, &ppr->ar[PT_AUR_BSP]);
1304 retval |= __get_user(cfm, &ppr->cfm);
1305
1306 /* gr1-gr3 */
1307
1308 retval |= __copy_from_user(&pt->r1, &ppr->gr[1], sizeof(long));
1309 retval |= __copy_from_user(&pt->r2, &ppr->gr[2], sizeof(long) * 2);
1310
1311 /* gr4-gr7 */
1312
1313 for (i = 4; i < 8; i++) {
1314 retval |= __get_user(val, &ppr->gr[i]);
1315 /* NaT bit will be set via PT_NAT_BITS: */
1316 if (unw_set_gr(&info, i, val, 0) < 0)
1317 return -EIO;
1318 }
1319
1320 /* gr8-gr11 */
1321
1322 retval |= __copy_from_user(&pt->r8, &ppr->gr[8], sizeof(long) * 4);
1323
1324 /* gr12-gr15 */
1325
1326 retval |= __copy_from_user(&pt->r12, &ppr->gr[12], sizeof(long) * 2);
1327 retval |= __copy_from_user(&pt->r14, &ppr->gr[14], sizeof(long));
1328 retval |= __copy_from_user(&pt->r15, &ppr->gr[15], sizeof(long));
1329
1330 /* gr16-gr31 */
1331
1332 retval |= __copy_from_user(&pt->r16, &ppr->gr[16], sizeof(long) * 16);
1333
1334 /* b0 */
1335
1336 retval |= __get_user(pt->b0, &ppr->br[0]);
1337
1338 /* b1-b5 */
1339
1340 for (i = 1; i < 6; i++) {
1341 retval |= __get_user(val, &ppr->br[i]);
1342 unw_set_br(&info, i, val);
1343 }
1344
1345 /* b6-b7 */
1346
1347 retval |= __get_user(pt->b6, &ppr->br[6]);
1348 retval |= __get_user(pt->b7, &ppr->br[7]);
1349
1350 /* fr2-fr5 */
1351
1352 for (i = 2; i < 6; i++) {
1353 retval |= __copy_from_user(&fpval, &ppr->fr[i], sizeof(fpval));
1354 if (unw_set_fr(&info, i, fpval) < 0)
1355 return -EIO;
1356 }
1357
1358 /* fr6-fr11 */
1359
1360 retval |= __copy_from_user(&pt->f6, &ppr->fr[6],
1361 sizeof(ppr->fr[6]) * 6);
1362
1363 /* fp scratch regs(12-15) */
1364
1365 retval |= __copy_from_user(&sw->f12, &ppr->fr[12],
1366 sizeof(ppr->fr[12]) * 4);
1367
1368 /* fr16-fr31 */
1369
1370 for (i = 16; i < 32; i++) {
1371 retval |= __copy_from_user(&fpval, &ppr->fr[i],
1372 sizeof(fpval));
1373 if (unw_set_fr(&info, i, fpval) < 0)
1374 return -EIO;
1375 }
1376
1377 /* fph */
1378
1379 ia64_sync_fph(child);
1380 retval |= __copy_from_user(&child->thread.fph, &ppr->fr[32],
1381 sizeof(ppr->fr[32]) * 96);
1382
1383 /* preds */
1384
1385 retval |= __get_user(pt->pr, &ppr->pr);
1386
1387 /* nat bits */
1388
1389 retval |= __get_user(nat_bits, &ppr->nat);
1390
1391 retval |= access_uarea(child, PT_CR_IPSR, &psr, 1);
1392 retval |= access_uarea(child, PT_AR_RSC, &rsc, 1);
1393 retval |= access_uarea(child, PT_AR_EC, &ec, 1);
1394 retval |= access_uarea(child, PT_AR_LC, &lc, 1);
1395 retval |= access_uarea(child, PT_AR_RNAT, &rnat, 1);
1396 retval |= access_uarea(child, PT_AR_BSP, &bsp, 1);
1397 retval |= access_uarea(child, PT_CFM, &cfm, 1);
1398 retval |= access_uarea(child, PT_NAT_BITS, &nat_bits, 1);
1399
1400 ret = retval ? -EIO : 0;
1401 return ret;
1402 }
1403
1404 /*
1405 * Called by kernel/ptrace.c when detaching..
1406 *
1407 * Make sure the single step bit is not set.
1408 */
1409 void
1410 ptrace_disable (struct task_struct *child)
1411 {
1412 struct ia64_psr *child_psr = ia64_psr(ia64_task_regs(child));
1413
1414 /* make sure the single step/taken-branch trap bits are not set: */
1415 child_psr->ss = 0;
1416 child_psr->tb = 0;
1417 }
1418
1419 asmlinkage long
1420 sys_ptrace (long request, pid_t pid, unsigned long addr, unsigned long data)
1421 {
1422 struct pt_regs *pt;
1423 unsigned long urbs_end, peek_or_poke;
1424 struct task_struct *child;
1425 struct switch_stack *sw;
1426 long ret;
1427
1428 lock_kernel();
1429 ret = -EPERM;
1430 if (request == PTRACE_TRACEME) {
1431 /* are we already being traced? */
1432 if (current->ptrace & PT_PTRACED)
1433 goto out;
1434 ret = security_ptrace(current->parent, current);
1435 if (ret)
1436 goto out;
1437 current->ptrace |= PT_PTRACED;
1438 ret = 0;
1439 goto out;
1440 }
1441
1442 peek_or_poke = (request == PTRACE_PEEKTEXT
1443 || request == PTRACE_PEEKDATA
1444 || request == PTRACE_POKETEXT
1445 || request == PTRACE_POKEDATA);
1446 ret = -ESRCH;
1447 read_lock(&tasklist_lock);
1448 {
1449 child = find_task_by_pid(pid);
1450 if (child) {
1451 if (peek_or_poke)
1452 child = find_thread_for_addr(child, addr);
1453 get_task_struct(child);
1454 }
1455 }
1456 read_unlock(&tasklist_lock);
1457 if (!child)
1458 goto out;
1459 ret = -EPERM;
1460 if (pid == 1) /* no messing around with init! */
1461 goto out_tsk;
1462
1463 if (request == PTRACE_ATTACH) {
1464 ret = ptrace_attach(child);
1465 goto out_tsk;
1466 }
1467
1468 ret = ptrace_check_attach(child, request == PTRACE_KILL);
1469 if (ret < 0)
1470 goto out_tsk;
1471
1472 pt = ia64_task_regs(child);
1473 sw = (struct switch_stack *) (child->thread.ksp + 16);
1474
1475 switch (request) {
1476 case PTRACE_PEEKTEXT:
1477 case PTRACE_PEEKDATA:
1478 /* read word at location addr */
1479 urbs_end = ia64_get_user_rbs_end(child, pt, NULL);
1480 ret = ia64_peek(child, sw, urbs_end, addr, &data);
1481 if (ret == 0) {
1482 ret = data;
1483 /* ensure "ret" is not mistaken as an error code: */
1484 force_successful_syscall_return();
1485 }
1486 goto out_tsk;
1487
1488 case PTRACE_POKETEXT:
1489 case PTRACE_POKEDATA:
1490 /* write the word at location addr */
1491 urbs_end = ia64_get_user_rbs_end(child, pt, NULL);
1492 ret = ia64_poke(child, sw, urbs_end, addr, data);
1493 goto out_tsk;
1494
1495 case PTRACE_PEEKUSR:
1496 /* read the word at addr in the USER area */
1497 if (access_uarea(child, addr, &data, 0) < 0) {
1498 ret = -EIO;
1499 goto out_tsk;
1500 }
1501 ret = data;
1502 /* ensure "ret" is not mistaken as an error code */
1503 force_successful_syscall_return();
1504 goto out_tsk;
1505
1506 case PTRACE_POKEUSR:
1507 /* write the word at addr in the USER area */
1508 if (access_uarea(child, addr, &data, 1) < 0) {
1509 ret = -EIO;
1510 goto out_tsk;
1511 }
1512 ret = 0;
1513 goto out_tsk;
1514
1515 case PTRACE_OLD_GETSIGINFO:
1516 /* for backwards-compatibility */
1517 ret = ptrace_request(child, PTRACE_GETSIGINFO, addr, data);
1518 goto out_tsk;
1519
1520 case PTRACE_OLD_SETSIGINFO:
1521 /* for backwards-compatibility */
1522 ret = ptrace_request(child, PTRACE_SETSIGINFO, addr, data);
1523 goto out_tsk;
1524
1525 case PTRACE_SYSCALL:
1526 /* continue and stop at next (return from) syscall */
1527 case PTRACE_CONT:
1528 /* restart after signal. */
1529 ret = -EIO;
1530 if (!valid_signal(data))
1531 goto out_tsk;
1532 if (request == PTRACE_SYSCALL)
1533 set_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
1534 else
1535 clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
1536 child->exit_code = data;
1537
1538 /*
1539 * Make sure the single step/taken-branch trap bits
1540 * are not set:
1541 */
1542 ia64_psr(pt)->ss = 0;
1543 ia64_psr(pt)->tb = 0;
1544
1545 wake_up_process(child);
1546 ret = 0;
1547 goto out_tsk;
1548
1549 case PTRACE_KILL:
1550 /*
1551 * Make the child exit. Best I can do is send it a
1552 * sigkill. Perhaps it should be put in the status
1553 * that it wants to exit.
1554 */
1555 if (child->exit_state == EXIT_ZOMBIE)
1556 /* already dead */
1557 goto out_tsk;
1558 child->exit_code = SIGKILL;
1559
1560 ptrace_disable(child);
1561 wake_up_process(child);
1562 ret = 0;
1563 goto out_tsk;
1564
1565 case PTRACE_SINGLESTEP:
1566 /* let child execute for one instruction */
1567 case PTRACE_SINGLEBLOCK:
1568 ret = -EIO;
1569 if (!valid_signal(data))
1570 goto out_tsk;
1571
1572 clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
1573 if (request == PTRACE_SINGLESTEP) {
1574 ia64_psr(pt)->ss = 1;
1575 } else {
1576 ia64_psr(pt)->tb = 1;
1577 }
1578 child->exit_code = data;
1579
1580 /* give it a chance to run. */
1581 wake_up_process(child);
1582 ret = 0;
1583 goto out_tsk;
1584
1585 case PTRACE_DETACH:
1586 /* detach a process that was attached. */
1587 ret = ptrace_detach(child, data);
1588 goto out_tsk;
1589
1590 case PTRACE_GETREGS:
1591 ret = ptrace_getregs(child,
1592 (struct pt_all_user_regs __user *) data);
1593 goto out_tsk;
1594
1595 case PTRACE_SETREGS:
1596 ret = ptrace_setregs(child,
1597 (struct pt_all_user_regs __user *) data);
1598 goto out_tsk;
1599
1600 default:
1601 ret = ptrace_request(child, request, addr, data);
1602 goto out_tsk;
1603 }
1604 out_tsk:
1605 put_task_struct(child);
1606 out:
1607 unlock_kernel();
1608 return ret;
1609 }
1610
1611
1612 void
1613 syscall_trace (void)
1614 {
1615 if (!test_thread_flag(TIF_SYSCALL_TRACE))
1616 return;
1617 if (!(current->ptrace & PT_PTRACED))
1618 return;
1619 /*
1620 * The 0x80 provides a way for the tracing parent to
1621 * distinguish between a syscall stop and SIGTRAP delivery.
1622 */
1623 ptrace_notify(SIGTRAP
1624 | ((current->ptrace & PT_TRACESYSGOOD) ? 0x80 : 0));
1625
1626 /*
1627 * This isn't the same as continuing with a signal, but it
1628 * will do for normal use. strace only continues with a
1629 * signal if the stopping signal is not SIGTRAP. -brl
1630 */
1631 if (current->exit_code) {
1632 send_sig(current->exit_code, current, 1);
1633 current->exit_code = 0;
1634 }
1635 }
1636
1637 /* "asmlinkage" so the input arguments are preserved... */
1638
1639 asmlinkage void
1640 syscall_trace_enter (long arg0, long arg1, long arg2, long arg3,
1641 long arg4, long arg5, long arg6, long arg7,
1642 struct pt_regs regs)
1643 {
1644 if (test_thread_flag(TIF_SYSCALL_TRACE)
1645 && (current->ptrace & PT_PTRACED))
1646 syscall_trace();
1647
1648 if (unlikely(current->audit_context)) {
1649 long syscall;
1650 int arch;
1651
1652 if (IS_IA32_PROCESS(&regs)) {
1653 syscall = regs.r1;
1654 arch = AUDIT_ARCH_I386;
1655 } else {
1656 syscall = regs.r15;
1657 arch = AUDIT_ARCH_IA64;
1658 }
1659
1660 audit_syscall_entry(current, arch, syscall, arg0, arg1, arg2, arg3);
1661 }
1662
1663 }
1664
1665 /* "asmlinkage" so the input arguments are preserved... */
1666
1667 asmlinkage void
1668 syscall_trace_leave (long arg0, long arg1, long arg2, long arg3,
1669 long arg4, long arg5, long arg6, long arg7,
1670 struct pt_regs regs)
1671 {
1672 if (unlikely(current->audit_context))
1673 audit_syscall_exit(current, AUDITSC_RESULT(regs.r10), regs.r8);
1674
1675 if (test_thread_flag(TIF_SYSCALL_TRACE)
1676 && (current->ptrace & PT_PTRACED))
1677 syscall_trace();
1678 }
AMDTP streaming driver for the Linux FireWire stack (Juju)