2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2009 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
45 #include <net/checksum.h>
48 #include <asm/system.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
54 #include <asm/idprom.h>
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
64 #define TG3_VLAN_TAG_USED 0
69 #define DRV_MODULE_NAME "tg3"
70 #define PFX DRV_MODULE_NAME ": "
71 #define DRV_MODULE_VERSION "3.99"
72 #define DRV_MODULE_RELDATE "April 20, 2009"
74 #define TG3_DEF_MAC_MODE 0
75 #define TG3_DEF_RX_MODE 0
76 #define TG3_DEF_TX_MODE 0
77 #define TG3_DEF_MSG_ENABLE \
87 /* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
90 #define TG3_TX_TIMEOUT (5 * HZ)
92 /* hardware minimum and maximum for a single frame's data payload */
93 #define TG3_MIN_MTU 60
94 #define TG3_MAX_MTU(tp) \
95 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
97 /* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
101 #define TG3_RX_RING_SIZE 512
102 #define TG3_DEF_RX_RING_PENDING 200
103 #define TG3_RX_JUMBO_RING_SIZE 256
104 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
106 /* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
112 #define TG3_RX_RCB_RING_SIZE(tp) \
113 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
115 #define TG3_TX_RING_SIZE 512
116 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
118 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_JUMBO_RING_SIZE)
122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
123 TG3_RX_RCB_RING_SIZE(tp))
124 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
126 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
128 #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
129 #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
131 /* minimum number of free TX descriptors required to wake up TX process */
132 #define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
134 #define TG3_RAW_IP_ALIGN 2
136 /* number of ETHTOOL_GSTATS u64's */
137 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
139 #define TG3_NUM_TEST 6
141 #define FIRMWARE_TG3 "tigon/tg3.bin"
142 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
143 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
145 static char version
[] __devinitdata
=
146 DRV_MODULE_NAME
".c:v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")\n";
148 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
149 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
150 MODULE_LICENSE("GPL");
151 MODULE_VERSION(DRV_MODULE_VERSION
);
152 MODULE_FIRMWARE(FIRMWARE_TG3
);
153 MODULE_FIRMWARE(FIRMWARE_TG3TSO
);
154 MODULE_FIRMWARE(FIRMWARE_TG3TSO5
);
157 static int tg3_debug
= -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
158 module_param(tg3_debug
, int, 0);
159 MODULE_PARM_DESC(tg3_debug
, "Tigon3 bitmapped debugging message enable value");
161 static struct pci_device_id tg3_pci_tbl
[] = {
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5700
)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5701
)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702
)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703
)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704
)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702FE
)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705
)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705_2
)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M
)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M_2
)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702X
)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703X
)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S
)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702A3
)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703A3
)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5782
)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5788
)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5789
)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901
)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901_2
)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S_2
)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705F
)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5720
)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5721
)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5722
)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5750
)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751
)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5750M
)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751M
)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751F
)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752
)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752M
)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753
)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753M
)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753F
)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754
)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754M
)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755
)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755M
)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5756
)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5786
)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787
)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787M
)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787F
)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714
)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714S
)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715
)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715S
)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780
)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780S
)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5781
)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906
)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906M
)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5784
)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5764
)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5723
)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761
)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761E
)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761S
)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761SE
)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5785
)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57780
)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57760
)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57790
)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57720
)},
227 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9DXX
)},
228 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9MXX
)},
229 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1000
)},
230 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1001
)},
231 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1003
)},
232 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC9100
)},
233 {PCI_DEVICE(PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_TIGON3
)},
237 MODULE_DEVICE_TABLE(pci
, tg3_pci_tbl
);
239 static const struct {
240 const char string
[ETH_GSTRING_LEN
];
241 } ethtool_stats_keys
[TG3_NUM_STATS
] = {
244 { "rx_ucast_packets" },
245 { "rx_mcast_packets" },
246 { "rx_bcast_packets" },
248 { "rx_align_errors" },
249 { "rx_xon_pause_rcvd" },
250 { "rx_xoff_pause_rcvd" },
251 { "rx_mac_ctrl_rcvd" },
252 { "rx_xoff_entered" },
253 { "rx_frame_too_long_errors" },
255 { "rx_undersize_packets" },
256 { "rx_in_length_errors" },
257 { "rx_out_length_errors" },
258 { "rx_64_or_less_octet_packets" },
259 { "rx_65_to_127_octet_packets" },
260 { "rx_128_to_255_octet_packets" },
261 { "rx_256_to_511_octet_packets" },
262 { "rx_512_to_1023_octet_packets" },
263 { "rx_1024_to_1522_octet_packets" },
264 { "rx_1523_to_2047_octet_packets" },
265 { "rx_2048_to_4095_octet_packets" },
266 { "rx_4096_to_8191_octet_packets" },
267 { "rx_8192_to_9022_octet_packets" },
274 { "tx_flow_control" },
276 { "tx_single_collisions" },
277 { "tx_mult_collisions" },
279 { "tx_excessive_collisions" },
280 { "tx_late_collisions" },
281 { "tx_collide_2times" },
282 { "tx_collide_3times" },
283 { "tx_collide_4times" },
284 { "tx_collide_5times" },
285 { "tx_collide_6times" },
286 { "tx_collide_7times" },
287 { "tx_collide_8times" },
288 { "tx_collide_9times" },
289 { "tx_collide_10times" },
290 { "tx_collide_11times" },
291 { "tx_collide_12times" },
292 { "tx_collide_13times" },
293 { "tx_collide_14times" },
294 { "tx_collide_15times" },
295 { "tx_ucast_packets" },
296 { "tx_mcast_packets" },
297 { "tx_bcast_packets" },
298 { "tx_carrier_sense_errors" },
302 { "dma_writeq_full" },
303 { "dma_write_prioq_full" },
307 { "rx_threshold_hit" },
309 { "dma_readq_full" },
310 { "dma_read_prioq_full" },
311 { "tx_comp_queue_full" },
313 { "ring_set_send_prod_index" },
314 { "ring_status_update" },
316 { "nic_avoided_irqs" },
317 { "nic_tx_threshold_hit" }
320 static const struct {
321 const char string
[ETH_GSTRING_LEN
];
322 } ethtool_test_keys
[TG3_NUM_TEST
] = {
323 { "nvram test (online) " },
324 { "link test (online) " },
325 { "register test (offline)" },
326 { "memory test (offline)" },
327 { "loopback test (offline)" },
328 { "interrupt test (offline)" },
331 static void tg3_write32(struct tg3
*tp
, u32 off
, u32 val
)
333 writel(val
, tp
->regs
+ off
);
336 static u32
tg3_read32(struct tg3
*tp
, u32 off
)
338 return (readl(tp
->regs
+ off
));
341 static void tg3_ape_write32(struct tg3
*tp
, u32 off
, u32 val
)
343 writel(val
, tp
->aperegs
+ off
);
346 static u32
tg3_ape_read32(struct tg3
*tp
, u32 off
)
348 return (readl(tp
->aperegs
+ off
));
351 static void tg3_write_indirect_reg32(struct tg3
*tp
, u32 off
, u32 val
)
355 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
356 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
357 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
358 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
361 static void tg3_write_flush_reg32(struct tg3
*tp
, u32 off
, u32 val
)
363 writel(val
, tp
->regs
+ off
);
364 readl(tp
->regs
+ off
);
367 static u32
tg3_read_indirect_reg32(struct tg3
*tp
, u32 off
)
372 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
373 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
374 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
375 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
379 static void tg3_write_indirect_mbox(struct tg3
*tp
, u32 off
, u32 val
)
383 if (off
== (MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
)) {
384 pci_write_config_dword(tp
->pdev
, TG3PCI_RCV_RET_RING_CON_IDX
+
385 TG3_64BIT_REG_LOW
, val
);
388 if (off
== (MAILBOX_RCV_STD_PROD_IDX
+ TG3_64BIT_REG_LOW
)) {
389 pci_write_config_dword(tp
->pdev
, TG3PCI_STD_RING_PROD_IDX
+
390 TG3_64BIT_REG_LOW
, val
);
394 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
395 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
396 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
397 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
399 /* In indirect mode when disabling interrupts, we also need
400 * to clear the interrupt bit in the GRC local ctrl register.
402 if ((off
== (MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
)) &&
404 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_LOCAL_CTRL
,
405 tp
->grc_local_ctrl
|GRC_LCLCTRL_CLEARINT
);
409 static u32
tg3_read_indirect_mbox(struct tg3
*tp
, u32 off
)
414 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
415 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
416 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
417 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
421 /* usec_wait specifies the wait time in usec when writing to certain registers
422 * where it is unsafe to read back the register without some delay.
423 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
424 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
426 static void _tw32_flush(struct tg3
*tp
, u32 off
, u32 val
, u32 usec_wait
)
428 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) ||
429 (tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
))
430 /* Non-posted methods */
431 tp
->write32(tp
, off
, val
);
434 tg3_write32(tp
, off
, val
);
439 /* Wait again after the read for the posted method to guarantee that
440 * the wait time is met.
446 static inline void tw32_mailbox_flush(struct tg3
*tp
, u32 off
, u32 val
)
448 tp
->write32_mbox(tp
, off
, val
);
449 if (!(tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
) &&
450 !(tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
))
451 tp
->read32_mbox(tp
, off
);
454 static void tg3_write32_tx_mbox(struct tg3
*tp
, u32 off
, u32 val
)
456 void __iomem
*mbox
= tp
->regs
+ off
;
458 if (tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
)
460 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
464 static u32
tg3_read32_mbox_5906(struct tg3
*tp
, u32 off
)
466 return (readl(tp
->regs
+ off
+ GRCMBOX_BASE
));
469 static void tg3_write32_mbox_5906(struct tg3
*tp
, u32 off
, u32 val
)
471 writel(val
, tp
->regs
+ off
+ GRCMBOX_BASE
);
474 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
475 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
476 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
477 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
478 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
480 #define tw32(reg,val) tp->write32(tp, reg, val)
481 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
482 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
483 #define tr32(reg) tp->read32(tp, reg)
485 static void tg3_write_mem(struct tg3
*tp
, u32 off
, u32 val
)
489 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) &&
490 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
))
493 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
494 if (tp
->tg3_flags
& TG3_FLAG_SRAM_USE_CONFIG
) {
495 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
496 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
498 /* Always leave this as zero. */
499 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
501 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
502 tw32_f(TG3PCI_MEM_WIN_DATA
, val
);
504 /* Always leave this as zero. */
505 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
507 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
510 static void tg3_read_mem(struct tg3
*tp
, u32 off
, u32
*val
)
514 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) &&
515 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
)) {
520 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
521 if (tp
->tg3_flags
& TG3_FLAG_SRAM_USE_CONFIG
) {
522 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
523 pci_read_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
525 /* Always leave this as zero. */
526 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
528 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
529 *val
= tr32(TG3PCI_MEM_WIN_DATA
);
531 /* Always leave this as zero. */
532 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
534 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
537 static void tg3_ape_lock_init(struct tg3
*tp
)
541 /* Make sure the driver hasn't any stale locks. */
542 for (i
= 0; i
< 8; i
++)
543 tg3_ape_write32(tp
, TG3_APE_LOCK_GRANT
+ 4 * i
,
544 APE_LOCK_GRANT_DRIVER
);
547 static int tg3_ape_lock(struct tg3
*tp
, int locknum
)
553 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
557 case TG3_APE_LOCK_GRC
:
558 case TG3_APE_LOCK_MEM
:
566 tg3_ape_write32(tp
, TG3_APE_LOCK_REQ
+ off
, APE_LOCK_REQ_DRIVER
);
568 /* Wait for up to 1 millisecond to acquire lock. */
569 for (i
= 0; i
< 100; i
++) {
570 status
= tg3_ape_read32(tp
, TG3_APE_LOCK_GRANT
+ off
);
571 if (status
== APE_LOCK_GRANT_DRIVER
)
576 if (status
!= APE_LOCK_GRANT_DRIVER
) {
577 /* Revoke the lock request. */
578 tg3_ape_write32(tp
, TG3_APE_LOCK_GRANT
+ off
,
579 APE_LOCK_GRANT_DRIVER
);
587 static void tg3_ape_unlock(struct tg3
*tp
, int locknum
)
591 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
595 case TG3_APE_LOCK_GRC
:
596 case TG3_APE_LOCK_MEM
:
603 tg3_ape_write32(tp
, TG3_APE_LOCK_GRANT
+ off
, APE_LOCK_GRANT_DRIVER
);
606 static void tg3_disable_ints(struct tg3
*tp
)
608 tw32(TG3PCI_MISC_HOST_CTRL
,
609 (tp
->misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
));
610 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
613 static inline void tg3_cond_int(struct tg3
*tp
)
615 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
616 (tp
->hw_status
->status
& SD_STATUS_UPDATED
))
617 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
619 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
620 (HOSTCC_MODE_ENABLE
| HOSTCC_MODE_NOW
));
623 static void tg3_enable_ints(struct tg3
*tp
)
628 tw32(TG3PCI_MISC_HOST_CTRL
,
629 (tp
->misc_host_ctrl
& ~MISC_HOST_CTRL_MASK_PCI_INT
));
630 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
631 (tp
->last_tag
<< 24));
632 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)
633 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
634 (tp
->last_tag
<< 24));
638 static inline unsigned int tg3_has_work(struct tg3
*tp
)
640 struct tg3_hw_status
*sblk
= tp
->hw_status
;
641 unsigned int work_exists
= 0;
643 /* check for phy events */
644 if (!(tp
->tg3_flags
&
645 (TG3_FLAG_USE_LINKCHG_REG
|
646 TG3_FLAG_POLL_SERDES
))) {
647 if (sblk
->status
& SD_STATUS_LINK_CHG
)
650 /* check for RX/TX work to do */
651 if (sblk
->idx
[0].tx_consumer
!= tp
->tx_cons
||
652 sblk
->idx
[0].rx_producer
!= tp
->rx_rcb_ptr
)
659 * similar to tg3_enable_ints, but it accurately determines whether there
660 * is new work pending and can return without flushing the PIO write
661 * which reenables interrupts
663 static void tg3_restart_ints(struct tg3
*tp
)
665 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
669 /* When doing tagged status, this work check is unnecessary.
670 * The last_tag we write above tells the chip which piece of
671 * work we've completed.
673 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
675 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
676 (HOSTCC_MODE_ENABLE
| HOSTCC_MODE_NOW
));
679 static inline void tg3_netif_stop(struct tg3
*tp
)
681 tp
->dev
->trans_start
= jiffies
; /* prevent tx timeout */
682 napi_disable(&tp
->napi
);
683 netif_tx_disable(tp
->dev
);
686 static inline void tg3_netif_start(struct tg3
*tp
)
688 netif_wake_queue(tp
->dev
);
689 /* NOTE: unconditional netif_wake_queue is only appropriate
690 * so long as all callers are assured to have free tx slots
691 * (such as after tg3_init_hw)
693 napi_enable(&tp
->napi
);
694 tp
->hw_status
->status
|= SD_STATUS_UPDATED
;
698 static void tg3_switch_clocks(struct tg3
*tp
)
700 u32 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
);
703 if ((tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
704 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
707 orig_clock_ctrl
= clock_ctrl
;
708 clock_ctrl
&= (CLOCK_CTRL_FORCE_CLKRUN
|
709 CLOCK_CTRL_CLKRUN_OENABLE
|
711 tp
->pci_clock_ctrl
= clock_ctrl
;
713 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
714 if (orig_clock_ctrl
& CLOCK_CTRL_625_CORE
) {
715 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
716 clock_ctrl
| CLOCK_CTRL_625_CORE
, 40);
718 } else if ((orig_clock_ctrl
& CLOCK_CTRL_44MHZ_CORE
) != 0) {
719 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
721 (CLOCK_CTRL_44MHZ_CORE
| CLOCK_CTRL_ALTCLK
),
723 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
724 clock_ctrl
| (CLOCK_CTRL_ALTCLK
),
727 tw32_wait_f(TG3PCI_CLOCK_CTRL
, clock_ctrl
, 40);
730 #define PHY_BUSY_LOOPS 5000
732 static int tg3_readphy(struct tg3
*tp
, int reg
, u32
*val
)
738 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
740 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
746 frame_val
= ((PHY_ADDR
<< MI_COM_PHY_ADDR_SHIFT
) &
747 MI_COM_PHY_ADDR_MASK
);
748 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
749 MI_COM_REG_ADDR_MASK
);
750 frame_val
|= (MI_COM_CMD_READ
| MI_COM_START
);
752 tw32_f(MAC_MI_COM
, frame_val
);
754 loops
= PHY_BUSY_LOOPS
;
757 frame_val
= tr32(MAC_MI_COM
);
759 if ((frame_val
& MI_COM_BUSY
) == 0) {
761 frame_val
= tr32(MAC_MI_COM
);
769 *val
= frame_val
& MI_COM_DATA_MASK
;
773 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
774 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
781 static int tg3_writephy(struct tg3
*tp
, int reg
, u32 val
)
787 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
&&
788 (reg
== MII_TG3_CTRL
|| reg
== MII_TG3_AUX_CTRL
))
791 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
793 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
797 frame_val
= ((PHY_ADDR
<< MI_COM_PHY_ADDR_SHIFT
) &
798 MI_COM_PHY_ADDR_MASK
);
799 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
800 MI_COM_REG_ADDR_MASK
);
801 frame_val
|= (val
& MI_COM_DATA_MASK
);
802 frame_val
|= (MI_COM_CMD_WRITE
| MI_COM_START
);
804 tw32_f(MAC_MI_COM
, frame_val
);
806 loops
= PHY_BUSY_LOOPS
;
809 frame_val
= tr32(MAC_MI_COM
);
810 if ((frame_val
& MI_COM_BUSY
) == 0) {
812 frame_val
= tr32(MAC_MI_COM
);
822 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
823 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
830 static int tg3_bmcr_reset(struct tg3
*tp
)
835 /* OK, reset it, and poll the BMCR_RESET bit until it
836 * clears or we time out.
838 phy_control
= BMCR_RESET
;
839 err
= tg3_writephy(tp
, MII_BMCR
, phy_control
);
845 err
= tg3_readphy(tp
, MII_BMCR
, &phy_control
);
849 if ((phy_control
& BMCR_RESET
) == 0) {
861 static int tg3_mdio_read(struct mii_bus
*bp
, int mii_id
, int reg
)
863 struct tg3
*tp
= bp
->priv
;
866 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_PAUSED
)
869 if (tg3_readphy(tp
, reg
, &val
))
875 static int tg3_mdio_write(struct mii_bus
*bp
, int mii_id
, int reg
, u16 val
)
877 struct tg3
*tp
= bp
->priv
;
879 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_PAUSED
)
882 if (tg3_writephy(tp
, reg
, val
))
888 static int tg3_mdio_reset(struct mii_bus
*bp
)
893 static void tg3_mdio_config_5785(struct tg3
*tp
)
896 struct phy_device
*phydev
;
898 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
899 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
900 case TG3_PHY_ID_BCM50610
:
901 val
= MAC_PHYCFG2_50610_LED_MODES
;
903 case TG3_PHY_ID_BCMAC131
:
904 val
= MAC_PHYCFG2_AC131_LED_MODES
;
906 case TG3_PHY_ID_RTL8211C
:
907 val
= MAC_PHYCFG2_RTL8211C_LED_MODES
;
909 case TG3_PHY_ID_RTL8201E
:
910 val
= MAC_PHYCFG2_RTL8201E_LED_MODES
;
916 if (phydev
->interface
!= PHY_INTERFACE_MODE_RGMII
) {
917 tw32(MAC_PHYCFG2
, val
);
919 val
= tr32(MAC_PHYCFG1
);
920 val
&= ~MAC_PHYCFG1_RGMII_INT
;
921 tw32(MAC_PHYCFG1
, val
);
926 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_STD_IBND_DISABLE
))
927 val
|= MAC_PHYCFG2_EMODE_MASK_MASK
|
928 MAC_PHYCFG2_FMODE_MASK_MASK
|
929 MAC_PHYCFG2_GMODE_MASK_MASK
|
930 MAC_PHYCFG2_ACT_MASK_MASK
|
931 MAC_PHYCFG2_QUAL_MASK_MASK
|
932 MAC_PHYCFG2_INBAND_ENABLE
;
934 tw32(MAC_PHYCFG2
, val
);
936 val
= tr32(MAC_PHYCFG1
) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC
|
937 MAC_PHYCFG1_RGMII_SND_STAT_EN
);
938 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_STD_IBND_DISABLE
) {
939 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
940 val
|= MAC_PHYCFG1_RGMII_EXT_RX_DEC
;
941 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
942 val
|= MAC_PHYCFG1_RGMII_SND_STAT_EN
;
944 tw32(MAC_PHYCFG1
, val
| MAC_PHYCFG1_RGMII_INT
| MAC_PHYCFG1_TXC_DRV
);
946 val
= tr32(MAC_EXT_RGMII_MODE
);
947 val
&= ~(MAC_RGMII_MODE_RX_INT_B
|
948 MAC_RGMII_MODE_RX_QUALITY
|
949 MAC_RGMII_MODE_RX_ACTIVITY
|
950 MAC_RGMII_MODE_RX_ENG_DET
|
951 MAC_RGMII_MODE_TX_ENABLE
|
952 MAC_RGMII_MODE_TX_LOWPWR
|
953 MAC_RGMII_MODE_TX_RESET
);
954 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_STD_IBND_DISABLE
)) {
955 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
956 val
|= MAC_RGMII_MODE_RX_INT_B
|
957 MAC_RGMII_MODE_RX_QUALITY
|
958 MAC_RGMII_MODE_RX_ACTIVITY
|
959 MAC_RGMII_MODE_RX_ENG_DET
;
960 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
961 val
|= MAC_RGMII_MODE_TX_ENABLE
|
962 MAC_RGMII_MODE_TX_LOWPWR
|
963 MAC_RGMII_MODE_TX_RESET
;
965 tw32(MAC_EXT_RGMII_MODE
, val
);
968 static void tg3_mdio_start(struct tg3
*tp
)
970 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) {
971 mutex_lock(&tp
->mdio_bus
->mdio_lock
);
972 tp
->tg3_flags3
&= ~TG3_FLG3_MDIOBUS_PAUSED
;
973 mutex_unlock(&tp
->mdio_bus
->mdio_lock
);
976 tp
->mi_mode
&= ~MAC_MI_MODE_AUTO_POLL
;
977 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
980 if ((tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) &&
981 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
982 tg3_mdio_config_5785(tp
);
985 static void tg3_mdio_stop(struct tg3
*tp
)
987 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) {
988 mutex_lock(&tp
->mdio_bus
->mdio_lock
);
989 tp
->tg3_flags3
|= TG3_FLG3_MDIOBUS_PAUSED
;
990 mutex_unlock(&tp
->mdio_bus
->mdio_lock
);
994 static int tg3_mdio_init(struct tg3
*tp
)
998 struct phy_device
*phydev
;
1002 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) ||
1003 (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
))
1006 tp
->mdio_bus
= mdiobus_alloc();
1007 if (tp
->mdio_bus
== NULL
)
1010 tp
->mdio_bus
->name
= "tg3 mdio bus";
1011 snprintf(tp
->mdio_bus
->id
, MII_BUS_ID_SIZE
, "%x",
1012 (tp
->pdev
->bus
->number
<< 8) | tp
->pdev
->devfn
);
1013 tp
->mdio_bus
->priv
= tp
;
1014 tp
->mdio_bus
->parent
= &tp
->pdev
->dev
;
1015 tp
->mdio_bus
->read
= &tg3_mdio_read
;
1016 tp
->mdio_bus
->write
= &tg3_mdio_write
;
1017 tp
->mdio_bus
->reset
= &tg3_mdio_reset
;
1018 tp
->mdio_bus
->phy_mask
= ~(1 << PHY_ADDR
);
1019 tp
->mdio_bus
->irq
= &tp
->mdio_irq
[0];
1021 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
1022 tp
->mdio_bus
->irq
[i
] = PHY_POLL
;
1024 /* The bus registration will look for all the PHYs on the mdio bus.
1025 * Unfortunately, it does not ensure the PHY is powered up before
1026 * accessing the PHY ID registers. A chip reset is the
1027 * quickest way to bring the device back to an operational state..
1029 if (tg3_readphy(tp
, MII_BMCR
, ®
) || (reg
& BMCR_PDOWN
))
1032 i
= mdiobus_register(tp
->mdio_bus
);
1034 printk(KERN_WARNING
"%s: mdiobus_reg failed (0x%x)\n",
1036 mdiobus_free(tp
->mdio_bus
);
1040 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
1042 if (!phydev
|| !phydev
->drv
) {
1043 printk(KERN_WARNING
"%s: No PHY devices\n", tp
->dev
->name
);
1044 mdiobus_unregister(tp
->mdio_bus
);
1045 mdiobus_free(tp
->mdio_bus
);
1049 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
1050 case TG3_PHY_ID_BCM57780
:
1051 phydev
->interface
= PHY_INTERFACE_MODE_GMII
;
1053 case TG3_PHY_ID_BCM50610
:
1054 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_STD_IBND_DISABLE
)
1055 phydev
->dev_flags
|= PHY_BRCM_STD_IBND_DISABLE
;
1056 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1057 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_RX_ENABLE
;
1058 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1059 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_TX_ENABLE
;
1061 case TG3_PHY_ID_RTL8211C
:
1062 phydev
->interface
= PHY_INTERFACE_MODE_RGMII
;
1064 case TG3_PHY_ID_RTL8201E
:
1065 case TG3_PHY_ID_BCMAC131
:
1066 phydev
->interface
= PHY_INTERFACE_MODE_MII
;
1070 tp
->tg3_flags3
|= TG3_FLG3_MDIOBUS_INITED
;
1072 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
1073 tg3_mdio_config_5785(tp
);
1078 static void tg3_mdio_fini(struct tg3
*tp
)
1080 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) {
1081 tp
->tg3_flags3
&= ~TG3_FLG3_MDIOBUS_INITED
;
1082 mdiobus_unregister(tp
->mdio_bus
);
1083 mdiobus_free(tp
->mdio_bus
);
1084 tp
->tg3_flags3
&= ~TG3_FLG3_MDIOBUS_PAUSED
;
1088 /* tp->lock is held. */
1089 static inline void tg3_generate_fw_event(struct tg3
*tp
)
1093 val
= tr32(GRC_RX_CPU_EVENT
);
1094 val
|= GRC_RX_CPU_DRIVER_EVENT
;
1095 tw32_f(GRC_RX_CPU_EVENT
, val
);
1097 tp
->last_event_jiffies
= jiffies
;
1100 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1102 /* tp->lock is held. */
1103 static void tg3_wait_for_event_ack(struct tg3
*tp
)
1106 unsigned int delay_cnt
;
1109 /* If enough time has passed, no wait is necessary. */
1110 time_remain
= (long)(tp
->last_event_jiffies
+ 1 +
1111 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC
)) -
1113 if (time_remain
< 0)
1116 /* Check if we can shorten the wait time. */
1117 delay_cnt
= jiffies_to_usecs(time_remain
);
1118 if (delay_cnt
> TG3_FW_EVENT_TIMEOUT_USEC
)
1119 delay_cnt
= TG3_FW_EVENT_TIMEOUT_USEC
;
1120 delay_cnt
= (delay_cnt
>> 3) + 1;
1122 for (i
= 0; i
< delay_cnt
; i
++) {
1123 if (!(tr32(GRC_RX_CPU_EVENT
) & GRC_RX_CPU_DRIVER_EVENT
))
1129 /* tp->lock is held. */
1130 static void tg3_ump_link_report(struct tg3
*tp
)
1135 if (!(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
1136 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
1139 tg3_wait_for_event_ack(tp
);
1141 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_LINK_UPDATE
);
1143 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 14);
1146 if (!tg3_readphy(tp
, MII_BMCR
, ®
))
1148 if (!tg3_readphy(tp
, MII_BMSR
, ®
))
1149 val
|= (reg
& 0xffff);
1150 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
, val
);
1153 if (!tg3_readphy(tp
, MII_ADVERTISE
, ®
))
1155 if (!tg3_readphy(tp
, MII_LPA
, ®
))
1156 val
|= (reg
& 0xffff);
1157 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 4, val
);
1160 if (!(tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)) {
1161 if (!tg3_readphy(tp
, MII_CTRL1000
, ®
))
1163 if (!tg3_readphy(tp
, MII_STAT1000
, ®
))
1164 val
|= (reg
& 0xffff);
1166 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 8, val
);
1168 if (!tg3_readphy(tp
, MII_PHYADDR
, ®
))
1172 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 12, val
);
1174 tg3_generate_fw_event(tp
);
1177 static void tg3_link_report(struct tg3
*tp
)
1179 if (!netif_carrier_ok(tp
->dev
)) {
1180 if (netif_msg_link(tp
))
1181 printk(KERN_INFO PFX
"%s: Link is down.\n",
1183 tg3_ump_link_report(tp
);
1184 } else if (netif_msg_link(tp
)) {
1185 printk(KERN_INFO PFX
"%s: Link is up at %d Mbps, %s duplex.\n",
1187 (tp
->link_config
.active_speed
== SPEED_1000
?
1189 (tp
->link_config
.active_speed
== SPEED_100
?
1191 (tp
->link_config
.active_duplex
== DUPLEX_FULL
?
1194 printk(KERN_INFO PFX
1195 "%s: Flow control is %s for TX and %s for RX.\n",
1197 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
) ?
1199 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
) ?
1201 tg3_ump_link_report(tp
);
1205 static u16
tg3_advert_flowctrl_1000T(u8 flow_ctrl
)
1209 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1210 miireg
= ADVERTISE_PAUSE_CAP
;
1211 else if (flow_ctrl
& FLOW_CTRL_TX
)
1212 miireg
= ADVERTISE_PAUSE_ASYM
;
1213 else if (flow_ctrl
& FLOW_CTRL_RX
)
1214 miireg
= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1221 static u16
tg3_advert_flowctrl_1000X(u8 flow_ctrl
)
1225 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1226 miireg
= ADVERTISE_1000XPAUSE
;
1227 else if (flow_ctrl
& FLOW_CTRL_TX
)
1228 miireg
= ADVERTISE_1000XPSE_ASYM
;
1229 else if (flow_ctrl
& FLOW_CTRL_RX
)
1230 miireg
= ADVERTISE_1000XPAUSE
| ADVERTISE_1000XPSE_ASYM
;
1237 static u8
tg3_resolve_flowctrl_1000X(u16 lcladv
, u16 rmtadv
)
1241 if (lcladv
& ADVERTISE_1000XPAUSE
) {
1242 if (lcladv
& ADVERTISE_1000XPSE_ASYM
) {
1243 if (rmtadv
& LPA_1000XPAUSE
)
1244 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1245 else if (rmtadv
& LPA_1000XPAUSE_ASYM
)
1248 if (rmtadv
& LPA_1000XPAUSE
)
1249 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1251 } else if (lcladv
& ADVERTISE_1000XPSE_ASYM
) {
1252 if ((rmtadv
& LPA_1000XPAUSE
) && (rmtadv
& LPA_1000XPAUSE_ASYM
))
1259 static void tg3_setup_flow_control(struct tg3
*tp
, u32 lcladv
, u32 rmtadv
)
1263 u32 old_rx_mode
= tp
->rx_mode
;
1264 u32 old_tx_mode
= tp
->tx_mode
;
1266 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)
1267 autoneg
= tp
->mdio_bus
->phy_map
[PHY_ADDR
]->autoneg
;
1269 autoneg
= tp
->link_config
.autoneg
;
1271 if (autoneg
== AUTONEG_ENABLE
&&
1272 (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
)) {
1273 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)
1274 flowctrl
= tg3_resolve_flowctrl_1000X(lcladv
, rmtadv
);
1276 flowctrl
= mii_resolve_flowctrl_fdx(lcladv
, rmtadv
);
1278 flowctrl
= tp
->link_config
.flowctrl
;
1280 tp
->link_config
.active_flowctrl
= flowctrl
;
1282 if (flowctrl
& FLOW_CTRL_RX
)
1283 tp
->rx_mode
|= RX_MODE_FLOW_CTRL_ENABLE
;
1285 tp
->rx_mode
&= ~RX_MODE_FLOW_CTRL_ENABLE
;
1287 if (old_rx_mode
!= tp
->rx_mode
)
1288 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
1290 if (flowctrl
& FLOW_CTRL_TX
)
1291 tp
->tx_mode
|= TX_MODE_FLOW_CTRL_ENABLE
;
1293 tp
->tx_mode
&= ~TX_MODE_FLOW_CTRL_ENABLE
;
1295 if (old_tx_mode
!= tp
->tx_mode
)
1296 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
1299 static void tg3_adjust_link(struct net_device
*dev
)
1301 u8 oldflowctrl
, linkmesg
= 0;
1302 u32 mac_mode
, lcl_adv
, rmt_adv
;
1303 struct tg3
*tp
= netdev_priv(dev
);
1304 struct phy_device
*phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
1306 spin_lock(&tp
->lock
);
1308 mac_mode
= tp
->mac_mode
& ~(MAC_MODE_PORT_MODE_MASK
|
1309 MAC_MODE_HALF_DUPLEX
);
1311 oldflowctrl
= tp
->link_config
.active_flowctrl
;
1317 if (phydev
->speed
== SPEED_100
|| phydev
->speed
== SPEED_10
)
1318 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
1320 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1322 if (phydev
->duplex
== DUPLEX_HALF
)
1323 mac_mode
|= MAC_MODE_HALF_DUPLEX
;
1325 lcl_adv
= tg3_advert_flowctrl_1000T(
1326 tp
->link_config
.flowctrl
);
1329 rmt_adv
= LPA_PAUSE_CAP
;
1330 if (phydev
->asym_pause
)
1331 rmt_adv
|= LPA_PAUSE_ASYM
;
1334 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
1336 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1338 if (mac_mode
!= tp
->mac_mode
) {
1339 tp
->mac_mode
= mac_mode
;
1340 tw32_f(MAC_MODE
, tp
->mac_mode
);
1344 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
) {
1345 if (phydev
->speed
== SPEED_10
)
1347 MAC_MI_STAT_10MBPS_MODE
|
1348 MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
1350 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
1353 if (phydev
->speed
== SPEED_1000
&& phydev
->duplex
== DUPLEX_HALF
)
1354 tw32(MAC_TX_LENGTHS
,
1355 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
1356 (6 << TX_LENGTHS_IPG_SHIFT
) |
1357 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
1359 tw32(MAC_TX_LENGTHS
,
1360 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
1361 (6 << TX_LENGTHS_IPG_SHIFT
) |
1362 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
1364 if ((phydev
->link
&& tp
->link_config
.active_speed
== SPEED_INVALID
) ||
1365 (!phydev
->link
&& tp
->link_config
.active_speed
!= SPEED_INVALID
) ||
1366 phydev
->speed
!= tp
->link_config
.active_speed
||
1367 phydev
->duplex
!= tp
->link_config
.active_duplex
||
1368 oldflowctrl
!= tp
->link_config
.active_flowctrl
)
1371 tp
->link_config
.active_speed
= phydev
->speed
;
1372 tp
->link_config
.active_duplex
= phydev
->duplex
;
1374 spin_unlock(&tp
->lock
);
1377 tg3_link_report(tp
);
1380 static int tg3_phy_init(struct tg3
*tp
)
1382 struct phy_device
*phydev
;
1384 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
)
1387 /* Bring the PHY back to a known state. */
1390 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
1392 /* Attach the MAC to the PHY. */
1393 phydev
= phy_connect(tp
->dev
, dev_name(&phydev
->dev
), tg3_adjust_link
,
1394 phydev
->dev_flags
, phydev
->interface
);
1395 if (IS_ERR(phydev
)) {
1396 printk(KERN_ERR
"%s: Could not attach to PHY\n", tp
->dev
->name
);
1397 return PTR_ERR(phydev
);
1400 /* Mask with MAC supported features. */
1401 switch (phydev
->interface
) {
1402 case PHY_INTERFACE_MODE_GMII
:
1403 case PHY_INTERFACE_MODE_RGMII
:
1404 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
1405 phydev
->supported
&= (PHY_GBIT_FEATURES
|
1407 SUPPORTED_Asym_Pause
);
1411 case PHY_INTERFACE_MODE_MII
:
1412 phydev
->supported
&= (PHY_BASIC_FEATURES
|
1414 SUPPORTED_Asym_Pause
);
1417 phy_disconnect(tp
->mdio_bus
->phy_map
[PHY_ADDR
]);
1421 tp
->tg3_flags3
|= TG3_FLG3_PHY_CONNECTED
;
1423 phydev
->advertising
= phydev
->supported
;
1428 static void tg3_phy_start(struct tg3
*tp
)
1430 struct phy_device
*phydev
;
1432 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
1435 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
1437 if (tp
->link_config
.phy_is_low_power
) {
1438 tp
->link_config
.phy_is_low_power
= 0;
1439 phydev
->speed
= tp
->link_config
.orig_speed
;
1440 phydev
->duplex
= tp
->link_config
.orig_duplex
;
1441 phydev
->autoneg
= tp
->link_config
.orig_autoneg
;
1442 phydev
->advertising
= tp
->link_config
.orig_advertising
;
1447 phy_start_aneg(phydev
);
1450 static void tg3_phy_stop(struct tg3
*tp
)
1452 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
1455 phy_stop(tp
->mdio_bus
->phy_map
[PHY_ADDR
]);
1458 static void tg3_phy_fini(struct tg3
*tp
)
1460 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) {
1461 phy_disconnect(tp
->mdio_bus
->phy_map
[PHY_ADDR
]);
1462 tp
->tg3_flags3
&= ~TG3_FLG3_PHY_CONNECTED
;
1466 static void tg3_phydsp_write(struct tg3
*tp
, u32 reg
, u32 val
)
1468 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, reg
);
1469 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, val
);
1472 static void tg3_phy_toggle_apd(struct tg3
*tp
, bool enable
)
1476 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
1477 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
1480 reg
= MII_TG3_MISC_SHDW_WREN
|
1481 MII_TG3_MISC_SHDW_SCR5_SEL
|
1482 MII_TG3_MISC_SHDW_SCR5_LPED
|
1483 MII_TG3_MISC_SHDW_SCR5_DLPTLM
|
1484 MII_TG3_MISC_SHDW_SCR5_SDTL
|
1485 MII_TG3_MISC_SHDW_SCR5_C125OE
;
1486 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5784
|| !enable
)
1487 reg
|= MII_TG3_MISC_SHDW_SCR5_DLLAPD
;
1489 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
1492 reg
= MII_TG3_MISC_SHDW_WREN
|
1493 MII_TG3_MISC_SHDW_APD_SEL
|
1494 MII_TG3_MISC_SHDW_APD_WKTM_84MS
;
1496 reg
|= MII_TG3_MISC_SHDW_APD_ENABLE
;
1498 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
1501 static void tg3_phy_toggle_automdix(struct tg3
*tp
, int enable
)
1505 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
1506 (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
))
1509 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
1512 if (!tg3_readphy(tp
, MII_TG3_EPHY_TEST
, &ephy
)) {
1513 tg3_writephy(tp
, MII_TG3_EPHY_TEST
,
1514 ephy
| MII_TG3_EPHY_SHADOW_EN
);
1515 if (!tg3_readphy(tp
, MII_TG3_EPHYTST_MISCCTRL
, &phy
)) {
1517 phy
|= MII_TG3_EPHYTST_MISCCTRL_MDIX
;
1519 phy
&= ~MII_TG3_EPHYTST_MISCCTRL_MDIX
;
1520 tg3_writephy(tp
, MII_TG3_EPHYTST_MISCCTRL
, phy
);
1522 tg3_writephy(tp
, MII_TG3_EPHY_TEST
, ephy
);
1525 phy
= MII_TG3_AUXCTL_MISC_RDSEL_MISC
|
1526 MII_TG3_AUXCTL_SHDWSEL_MISC
;
1527 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
) &&
1528 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &phy
)) {
1530 phy
|= MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
1532 phy
&= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
1533 phy
|= MII_TG3_AUXCTL_MISC_WREN
;
1534 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1539 static void tg3_phy_set_wirespeed(struct tg3
*tp
)
1543 if (tp
->tg3_flags2
& TG3_FLG2_NO_ETH_WIRE_SPEED
)
1546 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x7007) &&
1547 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
))
1548 tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
1549 (val
| (1 << 15) | (1 << 4)));
1552 static void tg3_phy_apply_otp(struct tg3
*tp
)
1561 /* Enable SM_DSP clock and tx 6dB coding. */
1562 phy
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1563 MII_TG3_AUXCTL_ACTL_SMDSP_ENA
|
1564 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1565 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1567 phy
= ((otp
& TG3_OTP_AGCTGT_MASK
) >> TG3_OTP_AGCTGT_SHIFT
);
1568 phy
|= MII_TG3_DSP_TAP1_AGCTGT_DFLT
;
1569 tg3_phydsp_write(tp
, MII_TG3_DSP_TAP1
, phy
);
1571 phy
= ((otp
& TG3_OTP_HPFFLTR_MASK
) >> TG3_OTP_HPFFLTR_SHIFT
) |
1572 ((otp
& TG3_OTP_HPFOVER_MASK
) >> TG3_OTP_HPFOVER_SHIFT
);
1573 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH0
, phy
);
1575 phy
= ((otp
& TG3_OTP_LPFDIS_MASK
) >> TG3_OTP_LPFDIS_SHIFT
);
1576 phy
|= MII_TG3_DSP_AADJ1CH3_ADCCKADJ
;
1577 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH3
, phy
);
1579 phy
= ((otp
& TG3_OTP_VDAC_MASK
) >> TG3_OTP_VDAC_SHIFT
);
1580 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP75
, phy
);
1582 phy
= ((otp
& TG3_OTP_10BTAMP_MASK
) >> TG3_OTP_10BTAMP_SHIFT
);
1583 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP96
, phy
);
1585 phy
= ((otp
& TG3_OTP_ROFF_MASK
) >> TG3_OTP_ROFF_SHIFT
) |
1586 ((otp
& TG3_OTP_RCOFF_MASK
) >> TG3_OTP_RCOFF_SHIFT
);
1587 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP97
, phy
);
1589 /* Turn off SM_DSP clock. */
1590 phy
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1591 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1592 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1595 static int tg3_wait_macro_done(struct tg3
*tp
)
1602 if (!tg3_readphy(tp
, 0x16, &tmp32
)) {
1603 if ((tmp32
& 0x1000) == 0)
1613 static int tg3_phy_write_and_check_testpat(struct tg3
*tp
, int *resetp
)
1615 static const u32 test_pat
[4][6] = {
1616 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1617 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1618 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1619 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1623 for (chan
= 0; chan
< 4; chan
++) {
1626 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1627 (chan
* 0x2000) | 0x0200);
1628 tg3_writephy(tp
, 0x16, 0x0002);
1630 for (i
= 0; i
< 6; i
++)
1631 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
,
1634 tg3_writephy(tp
, 0x16, 0x0202);
1635 if (tg3_wait_macro_done(tp
)) {
1640 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1641 (chan
* 0x2000) | 0x0200);
1642 tg3_writephy(tp
, 0x16, 0x0082);
1643 if (tg3_wait_macro_done(tp
)) {
1648 tg3_writephy(tp
, 0x16, 0x0802);
1649 if (tg3_wait_macro_done(tp
)) {
1654 for (i
= 0; i
< 6; i
+= 2) {
1657 if (tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &low
) ||
1658 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &high
) ||
1659 tg3_wait_macro_done(tp
)) {
1665 if (low
!= test_pat
[chan
][i
] ||
1666 high
!= test_pat
[chan
][i
+1]) {
1667 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000b);
1668 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4001);
1669 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4005);
1679 static int tg3_phy_reset_chanpat(struct tg3
*tp
)
1683 for (chan
= 0; chan
< 4; chan
++) {
1686 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1687 (chan
* 0x2000) | 0x0200);
1688 tg3_writephy(tp
, 0x16, 0x0002);
1689 for (i
= 0; i
< 6; i
++)
1690 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x000);
1691 tg3_writephy(tp
, 0x16, 0x0202);
1692 if (tg3_wait_macro_done(tp
))
1699 static int tg3_phy_reset_5703_4_5(struct tg3
*tp
)
1701 u32 reg32
, phy9_orig
;
1702 int retries
, do_phy_reset
, err
;
1708 err
= tg3_bmcr_reset(tp
);
1714 /* Disable transmitter and interrupt. */
1715 if (tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
))
1719 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
1721 /* Set full-duplex, 1000 mbps. */
1722 tg3_writephy(tp
, MII_BMCR
,
1723 BMCR_FULLDPLX
| TG3_BMCR_SPEED1000
);
1725 /* Set to master mode. */
1726 if (tg3_readphy(tp
, MII_TG3_CTRL
, &phy9_orig
))
1729 tg3_writephy(tp
, MII_TG3_CTRL
,
1730 (MII_TG3_CTRL_AS_MASTER
|
1731 MII_TG3_CTRL_ENABLE_AS_MASTER
));
1733 /* Enable SM_DSP_CLOCK and 6dB. */
1734 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1736 /* Block the PHY control access. */
1737 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8005);
1738 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0800);
1740 err
= tg3_phy_write_and_check_testpat(tp
, &do_phy_reset
);
1743 } while (--retries
);
1745 err
= tg3_phy_reset_chanpat(tp
);
1749 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8005);
1750 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0000);
1752 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8200);
1753 tg3_writephy(tp
, 0x16, 0x0000);
1755 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
1756 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
1757 /* Set Extended packet length bit for jumbo frames */
1758 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4400);
1761 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1764 tg3_writephy(tp
, MII_TG3_CTRL
, phy9_orig
);
1766 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
)) {
1768 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
1775 /* This will reset the tigon3 PHY if there is no valid
1776 * link unless the FORCE argument is non-zero.
1778 static int tg3_phy_reset(struct tg3
*tp
)
1784 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
1787 val
= tr32(GRC_MISC_CFG
);
1788 tw32_f(GRC_MISC_CFG
, val
& ~GRC_MISC_CFG_EPHY_IDDQ
);
1791 err
= tg3_readphy(tp
, MII_BMSR
, &phy_status
);
1792 err
|= tg3_readphy(tp
, MII_BMSR
, &phy_status
);
1796 if (netif_running(tp
->dev
) && netif_carrier_ok(tp
->dev
)) {
1797 netif_carrier_off(tp
->dev
);
1798 tg3_link_report(tp
);
1801 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
1802 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
1803 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
1804 err
= tg3_phy_reset_5703_4_5(tp
);
1811 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
1812 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) {
1813 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
1814 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
)
1816 cpmuctrl
& ~CPMU_CTRL_GPHY_10MB_RXONLY
);
1819 err
= tg3_bmcr_reset(tp
);
1823 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
) {
1826 phy
= MII_TG3_DSP_EXP8_AEDW
| MII_TG3_DSP_EXP8_REJ2MHz
;
1827 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP8
, phy
);
1829 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
1832 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
||
1833 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5761_AX
) {
1836 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
1837 if ((val
& CPMU_LSPD_1000MB_MACCLK_MASK
) ==
1838 CPMU_LSPD_1000MB_MACCLK_12_5
) {
1839 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
1841 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
1845 tg3_phy_apply_otp(tp
);
1847 if (tp
->tg3_flags3
& TG3_FLG3_PHY_ENABLE_APD
)
1848 tg3_phy_toggle_apd(tp
, true);
1850 tg3_phy_toggle_apd(tp
, false);
1853 if (tp
->tg3_flags2
& TG3_FLG2_PHY_ADC_BUG
) {
1854 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1855 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
1856 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x2aaa);
1857 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
1858 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0323);
1859 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1861 if (tp
->tg3_flags2
& TG3_FLG2_PHY_5704_A0_BUG
) {
1862 tg3_writephy(tp
, 0x1c, 0x8d68);
1863 tg3_writephy(tp
, 0x1c, 0x8d68);
1865 if (tp
->tg3_flags2
& TG3_FLG2_PHY_BER_BUG
) {
1866 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1867 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
1868 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x310b);
1869 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
1870 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x9506);
1871 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x401f);
1872 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x14e2);
1873 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1875 else if (tp
->tg3_flags2
& TG3_FLG2_PHY_JITTER_BUG
) {
1876 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1877 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
1878 if (tp
->tg3_flags2
& TG3_FLG2_PHY_ADJUST_TRIM
) {
1879 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x110b);
1880 tg3_writephy(tp
, MII_TG3_TEST1
,
1881 MII_TG3_TEST1_TRIM_EN
| 0x4);
1883 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x010b);
1884 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1886 /* Set Extended packet length bit (bit 14) on all chips that */
1887 /* support jumbo frames */
1888 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
) {
1889 /* Cannot do read-modify-write on 5401 */
1890 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
1891 } else if (tp
->tg3_flags2
& TG3_FLG2_JUMBO_CAPABLE
) {
1894 /* Set bit 14 with read-modify-write to preserve other bits */
1895 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0007) &&
1896 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &phy_reg
))
1897 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy_reg
| 0x4000);
1900 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1901 * jumbo frames transmission.
1903 if (tp
->tg3_flags2
& TG3_FLG2_JUMBO_CAPABLE
) {
1906 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, &phy_reg
))
1907 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
1908 phy_reg
| MII_TG3_EXT_CTRL_FIFO_ELASTIC
);
1911 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
1912 /* adjust output voltage */
1913 tg3_writephy(tp
, MII_TG3_EPHY_PTEST
, 0x12);
1916 tg3_phy_toggle_automdix(tp
, 1);
1917 tg3_phy_set_wirespeed(tp
);
1921 static void tg3_frob_aux_power(struct tg3
*tp
)
1923 struct tg3
*tp_peer
= tp
;
1925 if ((tp
->tg3_flags2
& TG3_FLG2_IS_NIC
) == 0)
1928 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) ||
1929 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
)) {
1930 struct net_device
*dev_peer
;
1932 dev_peer
= pci_get_drvdata(tp
->pdev_peer
);
1933 /* remove_one() may have been run on the peer. */
1937 tp_peer
= netdev_priv(dev_peer
);
1940 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) != 0 ||
1941 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0 ||
1942 (tp_peer
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) != 0 ||
1943 (tp_peer
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0) {
1944 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
1945 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
1946 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
1947 (GRC_LCLCTRL_GPIO_OE0
|
1948 GRC_LCLCTRL_GPIO_OE1
|
1949 GRC_LCLCTRL_GPIO_OE2
|
1950 GRC_LCLCTRL_GPIO_OUTPUT0
|
1951 GRC_LCLCTRL_GPIO_OUTPUT1
),
1953 } else if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
1954 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
) {
1955 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1956 u32 grc_local_ctrl
= GRC_LCLCTRL_GPIO_OE0
|
1957 GRC_LCLCTRL_GPIO_OE1
|
1958 GRC_LCLCTRL_GPIO_OE2
|
1959 GRC_LCLCTRL_GPIO_OUTPUT0
|
1960 GRC_LCLCTRL_GPIO_OUTPUT1
|
1962 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
1964 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT2
;
1965 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
1967 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT0
;
1968 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
1971 u32 grc_local_ctrl
= 0;
1973 if (tp_peer
!= tp
&&
1974 (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) != 0)
1977 /* Workaround to prevent overdrawing Amps. */
1978 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
1980 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
1981 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
1982 grc_local_ctrl
, 100);
1985 /* On 5753 and variants, GPIO2 cannot be used. */
1986 no_gpio2
= tp
->nic_sram_data_cfg
&
1987 NIC_SRAM_DATA_CFG_NO_GPIO2
;
1989 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
1990 GRC_LCLCTRL_GPIO_OE1
|
1991 GRC_LCLCTRL_GPIO_OE2
|
1992 GRC_LCLCTRL_GPIO_OUTPUT1
|
1993 GRC_LCLCTRL_GPIO_OUTPUT2
;
1995 grc_local_ctrl
&= ~(GRC_LCLCTRL_GPIO_OE2
|
1996 GRC_LCLCTRL_GPIO_OUTPUT2
);
1998 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
1999 grc_local_ctrl
, 100);
2001 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT0
;
2003 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2004 grc_local_ctrl
, 100);
2007 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT2
;
2008 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2009 grc_local_ctrl
, 100);
2013 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
2014 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
2015 if (tp_peer
!= tp
&&
2016 (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) != 0)
2019 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2020 (GRC_LCLCTRL_GPIO_OE1
|
2021 GRC_LCLCTRL_GPIO_OUTPUT1
), 100);
2023 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2024 GRC_LCLCTRL_GPIO_OE1
, 100);
2026 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2027 (GRC_LCLCTRL_GPIO_OE1
|
2028 GRC_LCLCTRL_GPIO_OUTPUT1
), 100);
2033 static int tg3_5700_link_polarity(struct tg3
*tp
, u32 speed
)
2035 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_2
)
2037 else if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5411
) {
2038 if (speed
!= SPEED_10
)
2040 } else if (speed
== SPEED_10
)
2046 static int tg3_setup_phy(struct tg3
*, int);
2048 #define RESET_KIND_SHUTDOWN 0
2049 #define RESET_KIND_INIT 1
2050 #define RESET_KIND_SUSPEND 2
2052 static void tg3_write_sig_post_reset(struct tg3
*, int);
2053 static int tg3_halt_cpu(struct tg3
*, u32
);
2055 static void tg3_power_down_phy(struct tg3
*tp
, bool do_low_power
)
2059 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
2060 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
2061 u32 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
2062 u32 serdes_cfg
= tr32(MAC_SERDES_CFG
);
2065 SG_DIG_USING_HW_AUTONEG
| SG_DIG_SOFT_RESET
;
2066 tw32(SG_DIG_CTRL
, sg_dig_ctrl
);
2067 tw32(MAC_SERDES_CFG
, serdes_cfg
| (1 << 15));
2072 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2074 val
= tr32(GRC_MISC_CFG
);
2075 tw32_f(GRC_MISC_CFG
, val
| GRC_MISC_CFG_EPHY_IDDQ
);
2078 } else if (do_low_power
) {
2079 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
2080 MII_TG3_EXT_CTRL_FORCE_LED_OFF
);
2082 tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
2083 MII_TG3_AUXCTL_SHDWSEL_PWRCTL
|
2084 MII_TG3_AUXCTL_PCTL_100TX_LPWR
|
2085 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE
|
2086 MII_TG3_AUXCTL_PCTL_VREG_11V
);
2089 /* The PHY should not be powered down on some chips because
2092 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2093 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2094 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
&&
2095 (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)))
2098 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
||
2099 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5761_AX
) {
2100 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
2101 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
2102 val
|= CPMU_LSPD_1000MB_MACCLK_12_5
;
2103 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
2106 tg3_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
2109 /* tp->lock is held. */
2110 static int tg3_nvram_lock(struct tg3
*tp
)
2112 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
2115 if (tp
->nvram_lock_cnt
== 0) {
2116 tw32(NVRAM_SWARB
, SWARB_REQ_SET1
);
2117 for (i
= 0; i
< 8000; i
++) {
2118 if (tr32(NVRAM_SWARB
) & SWARB_GNT1
)
2123 tw32(NVRAM_SWARB
, SWARB_REQ_CLR1
);
2127 tp
->nvram_lock_cnt
++;
2132 /* tp->lock is held. */
2133 static void tg3_nvram_unlock(struct tg3
*tp
)
2135 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
2136 if (tp
->nvram_lock_cnt
> 0)
2137 tp
->nvram_lock_cnt
--;
2138 if (tp
->nvram_lock_cnt
== 0)
2139 tw32_f(NVRAM_SWARB
, SWARB_REQ_CLR1
);
2143 /* tp->lock is held. */
2144 static void tg3_enable_nvram_access(struct tg3
*tp
)
2146 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2147 !(tp
->tg3_flags2
& TG3_FLG2_PROTECTED_NVRAM
)) {
2148 u32 nvaccess
= tr32(NVRAM_ACCESS
);
2150 tw32(NVRAM_ACCESS
, nvaccess
| ACCESS_ENABLE
);
2154 /* tp->lock is held. */
2155 static void tg3_disable_nvram_access(struct tg3
*tp
)
2157 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2158 !(tp
->tg3_flags2
& TG3_FLG2_PROTECTED_NVRAM
)) {
2159 u32 nvaccess
= tr32(NVRAM_ACCESS
);
2161 tw32(NVRAM_ACCESS
, nvaccess
& ~ACCESS_ENABLE
);
2165 static int tg3_nvram_read_using_eeprom(struct tg3
*tp
,
2166 u32 offset
, u32
*val
)
2171 if (offset
> EEPROM_ADDR_ADDR_MASK
|| (offset
% 4) != 0)
2174 tmp
= tr32(GRC_EEPROM_ADDR
) & ~(EEPROM_ADDR_ADDR_MASK
|
2175 EEPROM_ADDR_DEVID_MASK
|
2177 tw32(GRC_EEPROM_ADDR
,
2179 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
2180 ((offset
<< EEPROM_ADDR_ADDR_SHIFT
) &
2181 EEPROM_ADDR_ADDR_MASK
) |
2182 EEPROM_ADDR_READ
| EEPROM_ADDR_START
);
2184 for (i
= 0; i
< 1000; i
++) {
2185 tmp
= tr32(GRC_EEPROM_ADDR
);
2187 if (tmp
& EEPROM_ADDR_COMPLETE
)
2191 if (!(tmp
& EEPROM_ADDR_COMPLETE
))
2194 tmp
= tr32(GRC_EEPROM_DATA
);
2197 * The data will always be opposite the native endian
2198 * format. Perform a blind byteswap to compensate.
2205 #define NVRAM_CMD_TIMEOUT 10000
2207 static int tg3_nvram_exec_cmd(struct tg3
*tp
, u32 nvram_cmd
)
2211 tw32(NVRAM_CMD
, nvram_cmd
);
2212 for (i
= 0; i
< NVRAM_CMD_TIMEOUT
; i
++) {
2214 if (tr32(NVRAM_CMD
) & NVRAM_CMD_DONE
) {
2220 if (i
== NVRAM_CMD_TIMEOUT
)
2226 static u32
tg3_nvram_phys_addr(struct tg3
*tp
, u32 addr
)
2228 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM
) &&
2229 (tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
2230 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
2231 !(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM_ADDR_TRANS
) &&
2232 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
2234 addr
= ((addr
/ tp
->nvram_pagesize
) <<
2235 ATMEL_AT45DB0X1B_PAGE_POS
) +
2236 (addr
% tp
->nvram_pagesize
);
2241 static u32
tg3_nvram_logical_addr(struct tg3
*tp
, u32 addr
)
2243 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM
) &&
2244 (tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
2245 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
2246 !(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM_ADDR_TRANS
) &&
2247 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
2249 addr
= ((addr
>> ATMEL_AT45DB0X1B_PAGE_POS
) *
2250 tp
->nvram_pagesize
) +
2251 (addr
& ((1 << ATMEL_AT45DB0X1B_PAGE_POS
) - 1));
2256 /* NOTE: Data read in from NVRAM is byteswapped according to
2257 * the byteswapping settings for all other register accesses.
2258 * tg3 devices are BE devices, so on a BE machine, the data
2259 * returned will be exactly as it is seen in NVRAM. On a LE
2260 * machine, the 32-bit value will be byteswapped.
2262 static int tg3_nvram_read(struct tg3
*tp
, u32 offset
, u32
*val
)
2266 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
))
2267 return tg3_nvram_read_using_eeprom(tp
, offset
, val
);
2269 offset
= tg3_nvram_phys_addr(tp
, offset
);
2271 if (offset
> NVRAM_ADDR_MSK
)
2274 ret
= tg3_nvram_lock(tp
);
2278 tg3_enable_nvram_access(tp
);
2280 tw32(NVRAM_ADDR
, offset
);
2281 ret
= tg3_nvram_exec_cmd(tp
, NVRAM_CMD_RD
| NVRAM_CMD_GO
|
2282 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_DONE
);
2285 *val
= tr32(NVRAM_RDDATA
);
2287 tg3_disable_nvram_access(tp
);
2289 tg3_nvram_unlock(tp
);
2294 /* Ensures NVRAM data is in bytestream format. */
2295 static int tg3_nvram_read_be32(struct tg3
*tp
, u32 offset
, __be32
*val
)
2298 int res
= tg3_nvram_read(tp
, offset
, &v
);
2300 *val
= cpu_to_be32(v
);
2304 /* tp->lock is held. */
2305 static void __tg3_set_mac_addr(struct tg3
*tp
, int skip_mac_1
)
2307 u32 addr_high
, addr_low
;
2310 addr_high
= ((tp
->dev
->dev_addr
[0] << 8) |
2311 tp
->dev
->dev_addr
[1]);
2312 addr_low
= ((tp
->dev
->dev_addr
[2] << 24) |
2313 (tp
->dev
->dev_addr
[3] << 16) |
2314 (tp
->dev
->dev_addr
[4] << 8) |
2315 (tp
->dev
->dev_addr
[5] << 0));
2316 for (i
= 0; i
< 4; i
++) {
2317 if (i
== 1 && skip_mac_1
)
2319 tw32(MAC_ADDR_0_HIGH
+ (i
* 8), addr_high
);
2320 tw32(MAC_ADDR_0_LOW
+ (i
* 8), addr_low
);
2323 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
2324 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
2325 for (i
= 0; i
< 12; i
++) {
2326 tw32(MAC_EXTADDR_0_HIGH
+ (i
* 8), addr_high
);
2327 tw32(MAC_EXTADDR_0_LOW
+ (i
* 8), addr_low
);
2331 addr_high
= (tp
->dev
->dev_addr
[0] +
2332 tp
->dev
->dev_addr
[1] +
2333 tp
->dev
->dev_addr
[2] +
2334 tp
->dev
->dev_addr
[3] +
2335 tp
->dev
->dev_addr
[4] +
2336 tp
->dev
->dev_addr
[5]) &
2337 TX_BACKOFF_SEED_MASK
;
2338 tw32(MAC_TX_BACKOFF_SEED
, addr_high
);
2341 static int tg3_set_power_state(struct tg3
*tp
, pci_power_t state
)
2344 bool device_should_wake
, do_low_power
;
2346 /* Make sure register accesses (indirect or otherwise)
2347 * will function correctly.
2349 pci_write_config_dword(tp
->pdev
,
2350 TG3PCI_MISC_HOST_CTRL
,
2351 tp
->misc_host_ctrl
);
2355 pci_enable_wake(tp
->pdev
, state
, false);
2356 pci_set_power_state(tp
->pdev
, PCI_D0
);
2358 /* Switch out of Vaux if it is a NIC */
2359 if (tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)
2360 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
, 100);
2370 printk(KERN_ERR PFX
"%s: Invalid power state (D%d) requested\n",
2371 tp
->dev
->name
, state
);
2375 /* Restore the CLKREQ setting. */
2376 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
) {
2379 pci_read_config_word(tp
->pdev
,
2380 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2382 lnkctl
|= PCI_EXP_LNKCTL_CLKREQ_EN
;
2383 pci_write_config_word(tp
->pdev
,
2384 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2388 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
2389 tw32(TG3PCI_MISC_HOST_CTRL
,
2390 misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
);
2392 device_should_wake
= pci_pme_capable(tp
->pdev
, state
) &&
2393 device_may_wakeup(&tp
->pdev
->dev
) &&
2394 (tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
2396 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
2397 do_low_power
= false;
2398 if ((tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) &&
2399 !tp
->link_config
.phy_is_low_power
) {
2400 struct phy_device
*phydev
;
2401 u32 phyid
, advertising
;
2403 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
2405 tp
->link_config
.phy_is_low_power
= 1;
2407 tp
->link_config
.orig_speed
= phydev
->speed
;
2408 tp
->link_config
.orig_duplex
= phydev
->duplex
;
2409 tp
->link_config
.orig_autoneg
= phydev
->autoneg
;
2410 tp
->link_config
.orig_advertising
= phydev
->advertising
;
2412 advertising
= ADVERTISED_TP
|
2414 ADVERTISED_Autoneg
|
2415 ADVERTISED_10baseT_Half
;
2417 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
2418 device_should_wake
) {
2419 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
2421 ADVERTISED_100baseT_Half
|
2422 ADVERTISED_100baseT_Full
|
2423 ADVERTISED_10baseT_Full
;
2425 advertising
|= ADVERTISED_10baseT_Full
;
2428 phydev
->advertising
= advertising
;
2430 phy_start_aneg(phydev
);
2432 phyid
= phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
;
2433 if (phyid
!= TG3_PHY_ID_BCMAC131
) {
2434 phyid
&= TG3_PHY_OUI_MASK
;
2435 if (phyid
== TG3_PHY_OUI_1
||
2436 phyid
== TG3_PHY_OUI_2
||
2437 phyid
== TG3_PHY_OUI_3
)
2438 do_low_power
= true;
2442 do_low_power
= true;
2444 if (tp
->link_config
.phy_is_low_power
== 0) {
2445 tp
->link_config
.phy_is_low_power
= 1;
2446 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
2447 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
2448 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
2451 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)) {
2452 tp
->link_config
.speed
= SPEED_10
;
2453 tp
->link_config
.duplex
= DUPLEX_HALF
;
2454 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
2455 tg3_setup_phy(tp
, 0);
2459 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2462 val
= tr32(GRC_VCPU_EXT_CTRL
);
2463 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_DISABLE_WOL
);
2464 } else if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
2468 for (i
= 0; i
< 200; i
++) {
2469 tg3_read_mem(tp
, NIC_SRAM_FW_ASF_STATUS_MBOX
, &val
);
2470 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
2475 if (tp
->tg3_flags
& TG3_FLAG_WOL_CAP
)
2476 tg3_write_mem(tp
, NIC_SRAM_WOL_MBOX
, WOL_SIGNATURE
|
2477 WOL_DRV_STATE_SHUTDOWN
|
2481 if (device_should_wake
) {
2484 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
2486 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x5a);
2490 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)
2491 mac_mode
= MAC_MODE_PORT_MODE_GMII
;
2493 mac_mode
= MAC_MODE_PORT_MODE_MII
;
2495 mac_mode
|= tp
->mac_mode
& MAC_MODE_LINK_POLARITY
;
2496 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
2498 u32 speed
= (tp
->tg3_flags
&
2499 TG3_FLAG_WOL_SPEED_100MB
) ?
2500 SPEED_100
: SPEED_10
;
2501 if (tg3_5700_link_polarity(tp
, speed
))
2502 mac_mode
|= MAC_MODE_LINK_POLARITY
;
2504 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
2507 mac_mode
= MAC_MODE_PORT_MODE_TBI
;
2510 if (!(tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
2511 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
2513 mac_mode
|= MAC_MODE_MAGIC_PKT_ENABLE
;
2514 if (((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
2515 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) &&
2516 ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
2517 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)))
2518 mac_mode
|= MAC_MODE_KEEP_FRAME_IN_WOL
;
2520 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
2521 mac_mode
|= tp
->mac_mode
&
2522 (MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
);
2523 if (mac_mode
& MAC_MODE_APE_TX_EN
)
2524 mac_mode
|= MAC_MODE_TDE_ENABLE
;
2527 tw32_f(MAC_MODE
, mac_mode
);
2530 tw32_f(MAC_RX_MODE
, RX_MODE_ENABLE
);
2534 if (!(tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
) &&
2535 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2536 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
2539 base_val
= tp
->pci_clock_ctrl
;
2540 base_val
|= (CLOCK_CTRL_RXCLK_DISABLE
|
2541 CLOCK_CTRL_TXCLK_DISABLE
);
2543 tw32_wait_f(TG3PCI_CLOCK_CTRL
, base_val
| CLOCK_CTRL_ALTCLK
|
2544 CLOCK_CTRL_PWRDOWN_PLL133
, 40);
2545 } else if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
2546 (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
2547 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)) {
2549 } else if (!((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2550 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))) {
2551 u32 newbits1
, newbits2
;
2553 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2554 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2555 newbits1
= (CLOCK_CTRL_RXCLK_DISABLE
|
2556 CLOCK_CTRL_TXCLK_DISABLE
|
2558 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
2559 } else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
2560 newbits1
= CLOCK_CTRL_625_CORE
;
2561 newbits2
= newbits1
| CLOCK_CTRL_ALTCLK
;
2563 newbits1
= CLOCK_CTRL_ALTCLK
;
2564 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
2567 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits1
,
2570 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits2
,
2573 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
2576 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2577 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2578 newbits3
= (CLOCK_CTRL_RXCLK_DISABLE
|
2579 CLOCK_CTRL_TXCLK_DISABLE
|
2580 CLOCK_CTRL_44MHZ_CORE
);
2582 newbits3
= CLOCK_CTRL_44MHZ_CORE
;
2585 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
2586 tp
->pci_clock_ctrl
| newbits3
, 40);
2590 if (!(device_should_wake
) &&
2591 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
2592 tg3_power_down_phy(tp
, do_low_power
);
2594 tg3_frob_aux_power(tp
);
2596 /* Workaround for unstable PLL clock */
2597 if ((GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
) ||
2598 (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
)) {
2599 u32 val
= tr32(0x7d00);
2601 val
&= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2603 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
2606 err
= tg3_nvram_lock(tp
);
2607 tg3_halt_cpu(tp
, RX_CPU_BASE
);
2609 tg3_nvram_unlock(tp
);
2613 tg3_write_sig_post_reset(tp
, RESET_KIND_SHUTDOWN
);
2615 if (device_should_wake
)
2616 pci_enable_wake(tp
->pdev
, state
, true);
2618 /* Finally, set the new power state. */
2619 pci_set_power_state(tp
->pdev
, state
);
2624 static void tg3_aux_stat_to_speed_duplex(struct tg3
*tp
, u32 val
, u16
*speed
, u8
*duplex
)
2626 switch (val
& MII_TG3_AUX_STAT_SPDMASK
) {
2627 case MII_TG3_AUX_STAT_10HALF
:
2629 *duplex
= DUPLEX_HALF
;
2632 case MII_TG3_AUX_STAT_10FULL
:
2634 *duplex
= DUPLEX_FULL
;
2637 case MII_TG3_AUX_STAT_100HALF
:
2639 *duplex
= DUPLEX_HALF
;
2642 case MII_TG3_AUX_STAT_100FULL
:
2644 *duplex
= DUPLEX_FULL
;
2647 case MII_TG3_AUX_STAT_1000HALF
:
2648 *speed
= SPEED_1000
;
2649 *duplex
= DUPLEX_HALF
;
2652 case MII_TG3_AUX_STAT_1000FULL
:
2653 *speed
= SPEED_1000
;
2654 *duplex
= DUPLEX_FULL
;
2658 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2659 *speed
= (val
& MII_TG3_AUX_STAT_100
) ? SPEED_100
:
2661 *duplex
= (val
& MII_TG3_AUX_STAT_FULL
) ? DUPLEX_FULL
:
2665 *speed
= SPEED_INVALID
;
2666 *duplex
= DUPLEX_INVALID
;
2671 static void tg3_phy_copper_begin(struct tg3
*tp
)
2676 if (tp
->link_config
.phy_is_low_power
) {
2677 /* Entering low power mode. Disable gigabit and
2678 * 100baseT advertisements.
2680 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
2682 new_adv
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
2683 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
2684 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
2685 new_adv
|= (ADVERTISE_100HALF
| ADVERTISE_100FULL
);
2687 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2688 } else if (tp
->link_config
.speed
== SPEED_INVALID
) {
2689 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
2690 tp
->link_config
.advertising
&=
2691 ~(ADVERTISED_1000baseT_Half
|
2692 ADVERTISED_1000baseT_Full
);
2694 new_adv
= ADVERTISE_CSMA
;
2695 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Half
)
2696 new_adv
|= ADVERTISE_10HALF
;
2697 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Full
)
2698 new_adv
|= ADVERTISE_10FULL
;
2699 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Half
)
2700 new_adv
|= ADVERTISE_100HALF
;
2701 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Full
)
2702 new_adv
|= ADVERTISE_100FULL
;
2704 new_adv
|= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2706 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2708 if (tp
->link_config
.advertising
&
2709 (ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
)) {
2711 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
2712 new_adv
|= MII_TG3_CTRL_ADV_1000_HALF
;
2713 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
2714 new_adv
|= MII_TG3_CTRL_ADV_1000_FULL
;
2715 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
) &&
2716 (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2717 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
))
2718 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
2719 MII_TG3_CTRL_ENABLE_AS_MASTER
);
2720 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
2722 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
2725 new_adv
= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2726 new_adv
|= ADVERTISE_CSMA
;
2728 /* Asking for a specific link mode. */
2729 if (tp
->link_config
.speed
== SPEED_1000
) {
2730 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2732 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2733 new_adv
= MII_TG3_CTRL_ADV_1000_FULL
;
2735 new_adv
= MII_TG3_CTRL_ADV_1000_HALF
;
2736 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2737 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
2738 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
2739 MII_TG3_CTRL_ENABLE_AS_MASTER
);
2741 if (tp
->link_config
.speed
== SPEED_100
) {
2742 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2743 new_adv
|= ADVERTISE_100FULL
;
2745 new_adv
|= ADVERTISE_100HALF
;
2747 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2748 new_adv
|= ADVERTISE_10FULL
;
2750 new_adv
|= ADVERTISE_10HALF
;
2752 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2757 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
2760 if (tp
->link_config
.autoneg
== AUTONEG_DISABLE
&&
2761 tp
->link_config
.speed
!= SPEED_INVALID
) {
2762 u32 bmcr
, orig_bmcr
;
2764 tp
->link_config
.active_speed
= tp
->link_config
.speed
;
2765 tp
->link_config
.active_duplex
= tp
->link_config
.duplex
;
2768 switch (tp
->link_config
.speed
) {
2774 bmcr
|= BMCR_SPEED100
;
2778 bmcr
|= TG3_BMCR_SPEED1000
;
2782 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2783 bmcr
|= BMCR_FULLDPLX
;
2785 if (!tg3_readphy(tp
, MII_BMCR
, &orig_bmcr
) &&
2786 (bmcr
!= orig_bmcr
)) {
2787 tg3_writephy(tp
, MII_BMCR
, BMCR_LOOPBACK
);
2788 for (i
= 0; i
< 1500; i
++) {
2792 if (tg3_readphy(tp
, MII_BMSR
, &tmp
) ||
2793 tg3_readphy(tp
, MII_BMSR
, &tmp
))
2795 if (!(tmp
& BMSR_LSTATUS
)) {
2800 tg3_writephy(tp
, MII_BMCR
, bmcr
);
2804 tg3_writephy(tp
, MII_BMCR
,
2805 BMCR_ANENABLE
| BMCR_ANRESTART
);
2809 static int tg3_init_5401phy_dsp(struct tg3
*tp
)
2813 /* Turn off tap power management. */
2814 /* Set Extended packet length bit */
2815 err
= tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
2817 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x0012);
2818 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x1804);
2820 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x0013);
2821 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x1204);
2823 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8006);
2824 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0132);
2826 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8006);
2827 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0232);
2829 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
2830 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0a20);
2837 static int tg3_copper_is_advertising_all(struct tg3
*tp
, u32 mask
)
2839 u32 adv_reg
, all_mask
= 0;
2841 if (mask
& ADVERTISED_10baseT_Half
)
2842 all_mask
|= ADVERTISE_10HALF
;
2843 if (mask
& ADVERTISED_10baseT_Full
)
2844 all_mask
|= ADVERTISE_10FULL
;
2845 if (mask
& ADVERTISED_100baseT_Half
)
2846 all_mask
|= ADVERTISE_100HALF
;
2847 if (mask
& ADVERTISED_100baseT_Full
)
2848 all_mask
|= ADVERTISE_100FULL
;
2850 if (tg3_readphy(tp
, MII_ADVERTISE
, &adv_reg
))
2853 if ((adv_reg
& all_mask
) != all_mask
)
2855 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
2859 if (mask
& ADVERTISED_1000baseT_Half
)
2860 all_mask
|= ADVERTISE_1000HALF
;
2861 if (mask
& ADVERTISED_1000baseT_Full
)
2862 all_mask
|= ADVERTISE_1000FULL
;
2864 if (tg3_readphy(tp
, MII_TG3_CTRL
, &tg3_ctrl
))
2867 if ((tg3_ctrl
& all_mask
) != all_mask
)
2873 static int tg3_adv_1000T_flowctrl_ok(struct tg3
*tp
, u32
*lcladv
, u32
*rmtadv
)
2877 if (tg3_readphy(tp
, MII_ADVERTISE
, lcladv
))
2880 curadv
= *lcladv
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
2881 reqadv
= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2883 if (tp
->link_config
.active_duplex
== DUPLEX_FULL
) {
2884 if (curadv
!= reqadv
)
2887 if (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
)
2888 tg3_readphy(tp
, MII_LPA
, rmtadv
);
2890 /* Reprogram the advertisement register, even if it
2891 * does not affect the current link. If the link
2892 * gets renegotiated in the future, we can save an
2893 * additional renegotiation cycle by advertising
2894 * it correctly in the first place.
2896 if (curadv
!= reqadv
) {
2897 *lcladv
&= ~(ADVERTISE_PAUSE_CAP
|
2898 ADVERTISE_PAUSE_ASYM
);
2899 tg3_writephy(tp
, MII_ADVERTISE
, *lcladv
| reqadv
);
2906 static int tg3_setup_copper_phy(struct tg3
*tp
, int force_reset
)
2908 int current_link_up
;
2910 u32 lcl_adv
, rmt_adv
;
2918 (MAC_STATUS_SYNC_CHANGED
|
2919 MAC_STATUS_CFG_CHANGED
|
2920 MAC_STATUS_MI_COMPLETION
|
2921 MAC_STATUS_LNKSTATE_CHANGED
));
2924 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
2926 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
2930 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x02);
2932 /* Some third-party PHYs need to be reset on link going
2935 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
2936 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2937 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
2938 netif_carrier_ok(tp
->dev
)) {
2939 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
2940 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
2941 !(bmsr
& BMSR_LSTATUS
))
2947 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
) {
2948 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
2949 if (tg3_readphy(tp
, MII_BMSR
, &bmsr
) ||
2950 !(tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
))
2953 if (!(bmsr
& BMSR_LSTATUS
)) {
2954 err
= tg3_init_5401phy_dsp(tp
);
2958 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
2959 for (i
= 0; i
< 1000; i
++) {
2961 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
2962 (bmsr
& BMSR_LSTATUS
)) {
2968 if ((tp
->phy_id
& PHY_ID_REV_MASK
) == PHY_REV_BCM5401_B0
&&
2969 !(bmsr
& BMSR_LSTATUS
) &&
2970 tp
->link_config
.active_speed
== SPEED_1000
) {
2971 err
= tg3_phy_reset(tp
);
2973 err
= tg3_init_5401phy_dsp(tp
);
2978 } else if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2979 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
) {
2980 /* 5701 {A0,B0} CRC bug workaround */
2981 tg3_writephy(tp
, 0x15, 0x0a75);
2982 tg3_writephy(tp
, 0x1c, 0x8c68);
2983 tg3_writephy(tp
, 0x1c, 0x8d68);
2984 tg3_writephy(tp
, 0x1c, 0x8c68);
2987 /* Clear pending interrupts... */
2988 tg3_readphy(tp
, MII_TG3_ISTAT
, &dummy
);
2989 tg3_readphy(tp
, MII_TG3_ISTAT
, &dummy
);
2991 if (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
)
2992 tg3_writephy(tp
, MII_TG3_IMASK
, ~MII_TG3_INT_LINKCHG
);
2993 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5906
)
2994 tg3_writephy(tp
, MII_TG3_IMASK
, ~0);
2996 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2997 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2998 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_1
)
2999 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
3000 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
3002 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, 0);
3005 current_link_up
= 0;
3006 current_speed
= SPEED_INVALID
;
3007 current_duplex
= DUPLEX_INVALID
;
3009 if (tp
->tg3_flags2
& TG3_FLG2_CAPACITIVE_COUPLING
) {
3012 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4007);
3013 tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
);
3014 if (!(val
& (1 << 10))) {
3016 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, val
);
3022 for (i
= 0; i
< 100; i
++) {
3023 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3024 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3025 (bmsr
& BMSR_LSTATUS
))
3030 if (bmsr
& BMSR_LSTATUS
) {
3033 tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
);
3034 for (i
= 0; i
< 2000; i
++) {
3036 if (!tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
) &&
3041 tg3_aux_stat_to_speed_duplex(tp
, aux_stat
,
3046 for (i
= 0; i
< 200; i
++) {
3047 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
3048 if (tg3_readphy(tp
, MII_BMCR
, &bmcr
))
3050 if (bmcr
&& bmcr
!= 0x7fff)
3058 tp
->link_config
.active_speed
= current_speed
;
3059 tp
->link_config
.active_duplex
= current_duplex
;
3061 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3062 if ((bmcr
& BMCR_ANENABLE
) &&
3063 tg3_copper_is_advertising_all(tp
,
3064 tp
->link_config
.advertising
)) {
3065 if (tg3_adv_1000T_flowctrl_ok(tp
, &lcl_adv
,
3067 current_link_up
= 1;
3070 if (!(bmcr
& BMCR_ANENABLE
) &&
3071 tp
->link_config
.speed
== current_speed
&&
3072 tp
->link_config
.duplex
== current_duplex
&&
3073 tp
->link_config
.flowctrl
==
3074 tp
->link_config
.active_flowctrl
) {
3075 current_link_up
= 1;
3079 if (current_link_up
== 1 &&
3080 tp
->link_config
.active_duplex
== DUPLEX_FULL
)
3081 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
3085 if (current_link_up
== 0 || tp
->link_config
.phy_is_low_power
) {
3088 tg3_phy_copper_begin(tp
);
3090 tg3_readphy(tp
, MII_BMSR
, &tmp
);
3091 if (!tg3_readphy(tp
, MII_BMSR
, &tmp
) &&
3092 (tmp
& BMSR_LSTATUS
))
3093 current_link_up
= 1;
3096 tp
->mac_mode
&= ~MAC_MODE_PORT_MODE_MASK
;
3097 if (current_link_up
== 1) {
3098 if (tp
->link_config
.active_speed
== SPEED_100
||
3099 tp
->link_config
.active_speed
== SPEED_10
)
3100 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
3102 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3104 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3106 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
3107 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
3108 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
3110 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
3111 if (current_link_up
== 1 &&
3112 tg3_5700_link_polarity(tp
, tp
->link_config
.active_speed
))
3113 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
3115 tp
->mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
3118 /* ??? Without this setting Netgear GA302T PHY does not
3119 * ??? send/receive packets...
3121 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5411
&&
3122 tp
->pci_chip_rev_id
== CHIPREV_ID_5700_ALTIMA
) {
3123 tp
->mi_mode
|= MAC_MI_MODE_AUTO_POLL
;
3124 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
3128 tw32_f(MAC_MODE
, tp
->mac_mode
);
3131 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
3132 /* Polled via timer. */
3133 tw32_f(MAC_EVENT
, 0);
3135 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
3139 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
&&
3140 current_link_up
== 1 &&
3141 tp
->link_config
.active_speed
== SPEED_1000
&&
3142 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) ||
3143 (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
))) {
3146 (MAC_STATUS_SYNC_CHANGED
|
3147 MAC_STATUS_CFG_CHANGED
));
3150 NIC_SRAM_FIRMWARE_MBOX
,
3151 NIC_SRAM_FIRMWARE_MBOX_MAGIC2
);
3154 /* Prevent send BD corruption. */
3155 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
) {
3156 u16 oldlnkctl
, newlnkctl
;
3158 pci_read_config_word(tp
->pdev
,
3159 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
3161 if (tp
->link_config
.active_speed
== SPEED_100
||
3162 tp
->link_config
.active_speed
== SPEED_10
)
3163 newlnkctl
= oldlnkctl
& ~PCI_EXP_LNKCTL_CLKREQ_EN
;
3165 newlnkctl
= oldlnkctl
| PCI_EXP_LNKCTL_CLKREQ_EN
;
3166 if (newlnkctl
!= oldlnkctl
)
3167 pci_write_config_word(tp
->pdev
,
3168 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
3172 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
3173 if (current_link_up
)
3174 netif_carrier_on(tp
->dev
);
3176 netif_carrier_off(tp
->dev
);
3177 tg3_link_report(tp
);
3183 struct tg3_fiber_aneginfo
{
3185 #define ANEG_STATE_UNKNOWN 0
3186 #define ANEG_STATE_AN_ENABLE 1
3187 #define ANEG_STATE_RESTART_INIT 2
3188 #define ANEG_STATE_RESTART 3
3189 #define ANEG_STATE_DISABLE_LINK_OK 4
3190 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3191 #define ANEG_STATE_ABILITY_DETECT 6
3192 #define ANEG_STATE_ACK_DETECT_INIT 7
3193 #define ANEG_STATE_ACK_DETECT 8
3194 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3195 #define ANEG_STATE_COMPLETE_ACK 10
3196 #define ANEG_STATE_IDLE_DETECT_INIT 11
3197 #define ANEG_STATE_IDLE_DETECT 12
3198 #define ANEG_STATE_LINK_OK 13
3199 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3200 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3203 #define MR_AN_ENABLE 0x00000001
3204 #define MR_RESTART_AN 0x00000002
3205 #define MR_AN_COMPLETE 0x00000004
3206 #define MR_PAGE_RX 0x00000008
3207 #define MR_NP_LOADED 0x00000010
3208 #define MR_TOGGLE_TX 0x00000020
3209 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3210 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3211 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3212 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3213 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3214 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3215 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3216 #define MR_TOGGLE_RX 0x00002000
3217 #define MR_NP_RX 0x00004000
3219 #define MR_LINK_OK 0x80000000
3221 unsigned long link_time
, cur_time
;
3223 u32 ability_match_cfg
;
3224 int ability_match_count
;
3226 char ability_match
, idle_match
, ack_match
;
3228 u32 txconfig
, rxconfig
;
3229 #define ANEG_CFG_NP 0x00000080
3230 #define ANEG_CFG_ACK 0x00000040
3231 #define ANEG_CFG_RF2 0x00000020
3232 #define ANEG_CFG_RF1 0x00000010
3233 #define ANEG_CFG_PS2 0x00000001
3234 #define ANEG_CFG_PS1 0x00008000
3235 #define ANEG_CFG_HD 0x00004000
3236 #define ANEG_CFG_FD 0x00002000
3237 #define ANEG_CFG_INVAL 0x00001f06
3242 #define ANEG_TIMER_ENAB 2
3243 #define ANEG_FAILED -1
3245 #define ANEG_STATE_SETTLE_TIME 10000
3247 static int tg3_fiber_aneg_smachine(struct tg3
*tp
,
3248 struct tg3_fiber_aneginfo
*ap
)
3251 unsigned long delta
;
3255 if (ap
->state
== ANEG_STATE_UNKNOWN
) {
3259 ap
->ability_match_cfg
= 0;
3260 ap
->ability_match_count
= 0;
3261 ap
->ability_match
= 0;
3267 if (tr32(MAC_STATUS
) & MAC_STATUS_RCVD_CFG
) {
3268 rx_cfg_reg
= tr32(MAC_RX_AUTO_NEG
);
3270 if (rx_cfg_reg
!= ap
->ability_match_cfg
) {
3271 ap
->ability_match_cfg
= rx_cfg_reg
;
3272 ap
->ability_match
= 0;
3273 ap
->ability_match_count
= 0;
3275 if (++ap
->ability_match_count
> 1) {
3276 ap
->ability_match
= 1;
3277 ap
->ability_match_cfg
= rx_cfg_reg
;
3280 if (rx_cfg_reg
& ANEG_CFG_ACK
)
3288 ap
->ability_match_cfg
= 0;
3289 ap
->ability_match_count
= 0;
3290 ap
->ability_match
= 0;
3296 ap
->rxconfig
= rx_cfg_reg
;
3300 case ANEG_STATE_UNKNOWN
:
3301 if (ap
->flags
& (MR_AN_ENABLE
| MR_RESTART_AN
))
3302 ap
->state
= ANEG_STATE_AN_ENABLE
;
3305 case ANEG_STATE_AN_ENABLE
:
3306 ap
->flags
&= ~(MR_AN_COMPLETE
| MR_PAGE_RX
);
3307 if (ap
->flags
& MR_AN_ENABLE
) {
3310 ap
->ability_match_cfg
= 0;
3311 ap
->ability_match_count
= 0;
3312 ap
->ability_match
= 0;
3316 ap
->state
= ANEG_STATE_RESTART_INIT
;
3318 ap
->state
= ANEG_STATE_DISABLE_LINK_OK
;
3322 case ANEG_STATE_RESTART_INIT
:
3323 ap
->link_time
= ap
->cur_time
;
3324 ap
->flags
&= ~(MR_NP_LOADED
);
3326 tw32(MAC_TX_AUTO_NEG
, 0);
3327 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3328 tw32_f(MAC_MODE
, tp
->mac_mode
);
3331 ret
= ANEG_TIMER_ENAB
;
3332 ap
->state
= ANEG_STATE_RESTART
;
3335 case ANEG_STATE_RESTART
:
3336 delta
= ap
->cur_time
- ap
->link_time
;
3337 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3338 ap
->state
= ANEG_STATE_ABILITY_DETECT_INIT
;
3340 ret
= ANEG_TIMER_ENAB
;
3344 case ANEG_STATE_DISABLE_LINK_OK
:
3348 case ANEG_STATE_ABILITY_DETECT_INIT
:
3349 ap
->flags
&= ~(MR_TOGGLE_TX
);
3350 ap
->txconfig
= ANEG_CFG_FD
;
3351 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3352 if (flowctrl
& ADVERTISE_1000XPAUSE
)
3353 ap
->txconfig
|= ANEG_CFG_PS1
;
3354 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
3355 ap
->txconfig
|= ANEG_CFG_PS2
;
3356 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
3357 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3358 tw32_f(MAC_MODE
, tp
->mac_mode
);
3361 ap
->state
= ANEG_STATE_ABILITY_DETECT
;
3364 case ANEG_STATE_ABILITY_DETECT
:
3365 if (ap
->ability_match
!= 0 && ap
->rxconfig
!= 0) {
3366 ap
->state
= ANEG_STATE_ACK_DETECT_INIT
;
3370 case ANEG_STATE_ACK_DETECT_INIT
:
3371 ap
->txconfig
|= ANEG_CFG_ACK
;
3372 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
3373 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3374 tw32_f(MAC_MODE
, tp
->mac_mode
);
3377 ap
->state
= ANEG_STATE_ACK_DETECT
;
3380 case ANEG_STATE_ACK_DETECT
:
3381 if (ap
->ack_match
!= 0) {
3382 if ((ap
->rxconfig
& ~ANEG_CFG_ACK
) ==
3383 (ap
->ability_match_cfg
& ~ANEG_CFG_ACK
)) {
3384 ap
->state
= ANEG_STATE_COMPLETE_ACK_INIT
;
3386 ap
->state
= ANEG_STATE_AN_ENABLE
;
3388 } else if (ap
->ability_match
!= 0 &&
3389 ap
->rxconfig
== 0) {
3390 ap
->state
= ANEG_STATE_AN_ENABLE
;
3394 case ANEG_STATE_COMPLETE_ACK_INIT
:
3395 if (ap
->rxconfig
& ANEG_CFG_INVAL
) {
3399 ap
->flags
&= ~(MR_LP_ADV_FULL_DUPLEX
|
3400 MR_LP_ADV_HALF_DUPLEX
|
3401 MR_LP_ADV_SYM_PAUSE
|
3402 MR_LP_ADV_ASYM_PAUSE
|
3403 MR_LP_ADV_REMOTE_FAULT1
|
3404 MR_LP_ADV_REMOTE_FAULT2
|
3405 MR_LP_ADV_NEXT_PAGE
|
3408 if (ap
->rxconfig
& ANEG_CFG_FD
)
3409 ap
->flags
|= MR_LP_ADV_FULL_DUPLEX
;
3410 if (ap
->rxconfig
& ANEG_CFG_HD
)
3411 ap
->flags
|= MR_LP_ADV_HALF_DUPLEX
;
3412 if (ap
->rxconfig
& ANEG_CFG_PS1
)
3413 ap
->flags
|= MR_LP_ADV_SYM_PAUSE
;
3414 if (ap
->rxconfig
& ANEG_CFG_PS2
)
3415 ap
->flags
|= MR_LP_ADV_ASYM_PAUSE
;
3416 if (ap
->rxconfig
& ANEG_CFG_RF1
)
3417 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT1
;
3418 if (ap
->rxconfig
& ANEG_CFG_RF2
)
3419 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT2
;
3420 if (ap
->rxconfig
& ANEG_CFG_NP
)
3421 ap
->flags
|= MR_LP_ADV_NEXT_PAGE
;
3423 ap
->link_time
= ap
->cur_time
;
3425 ap
->flags
^= (MR_TOGGLE_TX
);
3426 if (ap
->rxconfig
& 0x0008)
3427 ap
->flags
|= MR_TOGGLE_RX
;
3428 if (ap
->rxconfig
& ANEG_CFG_NP
)
3429 ap
->flags
|= MR_NP_RX
;
3430 ap
->flags
|= MR_PAGE_RX
;
3432 ap
->state
= ANEG_STATE_COMPLETE_ACK
;
3433 ret
= ANEG_TIMER_ENAB
;
3436 case ANEG_STATE_COMPLETE_ACK
:
3437 if (ap
->ability_match
!= 0 &&
3438 ap
->rxconfig
== 0) {
3439 ap
->state
= ANEG_STATE_AN_ENABLE
;
3442 delta
= ap
->cur_time
- ap
->link_time
;
3443 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3444 if (!(ap
->flags
& (MR_LP_ADV_NEXT_PAGE
))) {
3445 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
3447 if ((ap
->txconfig
& ANEG_CFG_NP
) == 0 &&
3448 !(ap
->flags
& MR_NP_RX
)) {
3449 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
3457 case ANEG_STATE_IDLE_DETECT_INIT
:
3458 ap
->link_time
= ap
->cur_time
;
3459 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
3460 tw32_f(MAC_MODE
, tp
->mac_mode
);
3463 ap
->state
= ANEG_STATE_IDLE_DETECT
;
3464 ret
= ANEG_TIMER_ENAB
;
3467 case ANEG_STATE_IDLE_DETECT
:
3468 if (ap
->ability_match
!= 0 &&
3469 ap
->rxconfig
== 0) {
3470 ap
->state
= ANEG_STATE_AN_ENABLE
;
3473 delta
= ap
->cur_time
- ap
->link_time
;
3474 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3475 /* XXX another gem from the Broadcom driver :( */
3476 ap
->state
= ANEG_STATE_LINK_OK
;
3480 case ANEG_STATE_LINK_OK
:
3481 ap
->flags
|= (MR_AN_COMPLETE
| MR_LINK_OK
);
3485 case ANEG_STATE_NEXT_PAGE_WAIT_INIT
:
3486 /* ??? unimplemented */
3489 case ANEG_STATE_NEXT_PAGE_WAIT
:
3490 /* ??? unimplemented */
3501 static int fiber_autoneg(struct tg3
*tp
, u32
*txflags
, u32
*rxflags
)
3504 struct tg3_fiber_aneginfo aninfo
;
3505 int status
= ANEG_FAILED
;
3509 tw32_f(MAC_TX_AUTO_NEG
, 0);
3511 tmp
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
3512 tw32_f(MAC_MODE
, tmp
| MAC_MODE_PORT_MODE_GMII
);
3515 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
);
3518 memset(&aninfo
, 0, sizeof(aninfo
));
3519 aninfo
.flags
|= MR_AN_ENABLE
;
3520 aninfo
.state
= ANEG_STATE_UNKNOWN
;
3521 aninfo
.cur_time
= 0;
3523 while (++tick
< 195000) {
3524 status
= tg3_fiber_aneg_smachine(tp
, &aninfo
);
3525 if (status
== ANEG_DONE
|| status
== ANEG_FAILED
)
3531 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
3532 tw32_f(MAC_MODE
, tp
->mac_mode
);
3535 *txflags
= aninfo
.txconfig
;
3536 *rxflags
= aninfo
.flags
;
3538 if (status
== ANEG_DONE
&&
3539 (aninfo
.flags
& (MR_AN_COMPLETE
| MR_LINK_OK
|
3540 MR_LP_ADV_FULL_DUPLEX
)))
3546 static void tg3_init_bcm8002(struct tg3
*tp
)
3548 u32 mac_status
= tr32(MAC_STATUS
);
3551 /* Reset when initting first time or we have a link. */
3552 if ((tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) &&
3553 !(mac_status
& MAC_STATUS_PCS_SYNCED
))
3556 /* Set PLL lock range. */
3557 tg3_writephy(tp
, 0x16, 0x8007);
3560 tg3_writephy(tp
, MII_BMCR
, BMCR_RESET
);
3562 /* Wait for reset to complete. */
3563 /* XXX schedule_timeout() ... */
3564 for (i
= 0; i
< 500; i
++)
3567 /* Config mode; select PMA/Ch 1 regs. */
3568 tg3_writephy(tp
, 0x10, 0x8411);
3570 /* Enable auto-lock and comdet, select txclk for tx. */
3571 tg3_writephy(tp
, 0x11, 0x0a10);
3573 tg3_writephy(tp
, 0x18, 0x00a0);
3574 tg3_writephy(tp
, 0x16, 0x41ff);
3576 /* Assert and deassert POR. */
3577 tg3_writephy(tp
, 0x13, 0x0400);
3579 tg3_writephy(tp
, 0x13, 0x0000);
3581 tg3_writephy(tp
, 0x11, 0x0a50);
3583 tg3_writephy(tp
, 0x11, 0x0a10);
3585 /* Wait for signal to stabilize */
3586 /* XXX schedule_timeout() ... */
3587 for (i
= 0; i
< 15000; i
++)
3590 /* Deselect the channel register so we can read the PHYID
3593 tg3_writephy(tp
, 0x10, 0x8011);
3596 static int tg3_setup_fiber_hw_autoneg(struct tg3
*tp
, u32 mac_status
)
3599 u32 sg_dig_ctrl
, sg_dig_status
;
3600 u32 serdes_cfg
, expected_sg_dig_ctrl
;
3601 int workaround
, port_a
;
3602 int current_link_up
;
3605 expected_sg_dig_ctrl
= 0;
3608 current_link_up
= 0;
3610 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A0
&&
3611 tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A1
) {
3613 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
3616 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3617 /* preserve bits 20-23 for voltage regulator */
3618 serdes_cfg
= tr32(MAC_SERDES_CFG
) & 0x00f06fff;
3621 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
3623 if (tp
->link_config
.autoneg
!= AUTONEG_ENABLE
) {
3624 if (sg_dig_ctrl
& SG_DIG_USING_HW_AUTONEG
) {
3626 u32 val
= serdes_cfg
;
3632 tw32_f(MAC_SERDES_CFG
, val
);
3635 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
3637 if (mac_status
& MAC_STATUS_PCS_SYNCED
) {
3638 tg3_setup_flow_control(tp
, 0, 0);
3639 current_link_up
= 1;
3644 /* Want auto-negotiation. */
3645 expected_sg_dig_ctrl
= SG_DIG_USING_HW_AUTONEG
| SG_DIG_COMMON_SETUP
;
3647 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3648 if (flowctrl
& ADVERTISE_1000XPAUSE
)
3649 expected_sg_dig_ctrl
|= SG_DIG_PAUSE_CAP
;
3650 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
3651 expected_sg_dig_ctrl
|= SG_DIG_ASYM_PAUSE
;
3653 if (sg_dig_ctrl
!= expected_sg_dig_ctrl
) {
3654 if ((tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
) &&
3655 tp
->serdes_counter
&&
3656 ((mac_status
& (MAC_STATUS_PCS_SYNCED
|
3657 MAC_STATUS_RCVD_CFG
)) ==
3658 MAC_STATUS_PCS_SYNCED
)) {
3659 tp
->serdes_counter
--;
3660 current_link_up
= 1;
3665 tw32_f(MAC_SERDES_CFG
, serdes_cfg
| 0xc011000);
3666 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
| SG_DIG_SOFT_RESET
);
3668 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
);
3670 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
3671 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3672 } else if (mac_status
& (MAC_STATUS_PCS_SYNCED
|
3673 MAC_STATUS_SIGNAL_DET
)) {
3674 sg_dig_status
= tr32(SG_DIG_STATUS
);
3675 mac_status
= tr32(MAC_STATUS
);
3677 if ((sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
) &&
3678 (mac_status
& MAC_STATUS_PCS_SYNCED
)) {
3679 u32 local_adv
= 0, remote_adv
= 0;
3681 if (sg_dig_ctrl
& SG_DIG_PAUSE_CAP
)
3682 local_adv
|= ADVERTISE_1000XPAUSE
;
3683 if (sg_dig_ctrl
& SG_DIG_ASYM_PAUSE
)
3684 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
3686 if (sg_dig_status
& SG_DIG_PARTNER_PAUSE_CAPABLE
)
3687 remote_adv
|= LPA_1000XPAUSE
;
3688 if (sg_dig_status
& SG_DIG_PARTNER_ASYM_PAUSE
)
3689 remote_adv
|= LPA_1000XPAUSE_ASYM
;
3691 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
3692 current_link_up
= 1;
3693 tp
->serdes_counter
= 0;
3694 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3695 } else if (!(sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
)) {
3696 if (tp
->serdes_counter
)
3697 tp
->serdes_counter
--;
3700 u32 val
= serdes_cfg
;
3707 tw32_f(MAC_SERDES_CFG
, val
);
3710 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
3713 /* Link parallel detection - link is up */
3714 /* only if we have PCS_SYNC and not */
3715 /* receiving config code words */
3716 mac_status
= tr32(MAC_STATUS
);
3717 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) &&
3718 !(mac_status
& MAC_STATUS_RCVD_CFG
)) {
3719 tg3_setup_flow_control(tp
, 0, 0);
3720 current_link_up
= 1;
3722 TG3_FLG2_PARALLEL_DETECT
;
3723 tp
->serdes_counter
=
3724 SERDES_PARALLEL_DET_TIMEOUT
;
3726 goto restart_autoneg
;
3730 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
3731 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3735 return current_link_up
;
3738 static int tg3_setup_fiber_by_hand(struct tg3
*tp
, u32 mac_status
)
3740 int current_link_up
= 0;
3742 if (!(mac_status
& MAC_STATUS_PCS_SYNCED
))
3745 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3746 u32 txflags
, rxflags
;
3749 if (fiber_autoneg(tp
, &txflags
, &rxflags
)) {
3750 u32 local_adv
= 0, remote_adv
= 0;
3752 if (txflags
& ANEG_CFG_PS1
)
3753 local_adv
|= ADVERTISE_1000XPAUSE
;
3754 if (txflags
& ANEG_CFG_PS2
)
3755 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
3757 if (rxflags
& MR_LP_ADV_SYM_PAUSE
)
3758 remote_adv
|= LPA_1000XPAUSE
;
3759 if (rxflags
& MR_LP_ADV_ASYM_PAUSE
)
3760 remote_adv
|= LPA_1000XPAUSE_ASYM
;
3762 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
3764 current_link_up
= 1;
3766 for (i
= 0; i
< 30; i
++) {
3769 (MAC_STATUS_SYNC_CHANGED
|
3770 MAC_STATUS_CFG_CHANGED
));
3772 if ((tr32(MAC_STATUS
) &
3773 (MAC_STATUS_SYNC_CHANGED
|
3774 MAC_STATUS_CFG_CHANGED
)) == 0)
3778 mac_status
= tr32(MAC_STATUS
);
3779 if (current_link_up
== 0 &&
3780 (mac_status
& MAC_STATUS_PCS_SYNCED
) &&
3781 !(mac_status
& MAC_STATUS_RCVD_CFG
))
3782 current_link_up
= 1;
3784 tg3_setup_flow_control(tp
, 0, 0);
3786 /* Forcing 1000FD link up. */
3787 current_link_up
= 1;
3789 tw32_f(MAC_MODE
, (tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
));
3792 tw32_f(MAC_MODE
, tp
->mac_mode
);
3797 return current_link_up
;
3800 static int tg3_setup_fiber_phy(struct tg3
*tp
, int force_reset
)
3803 u16 orig_active_speed
;
3804 u8 orig_active_duplex
;
3806 int current_link_up
;
3809 orig_pause_cfg
= tp
->link_config
.active_flowctrl
;
3810 orig_active_speed
= tp
->link_config
.active_speed
;
3811 orig_active_duplex
= tp
->link_config
.active_duplex
;
3813 if (!(tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
) &&
3814 netif_carrier_ok(tp
->dev
) &&
3815 (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
)) {
3816 mac_status
= tr32(MAC_STATUS
);
3817 mac_status
&= (MAC_STATUS_PCS_SYNCED
|
3818 MAC_STATUS_SIGNAL_DET
|
3819 MAC_STATUS_CFG_CHANGED
|
3820 MAC_STATUS_RCVD_CFG
);
3821 if (mac_status
== (MAC_STATUS_PCS_SYNCED
|
3822 MAC_STATUS_SIGNAL_DET
)) {
3823 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
3824 MAC_STATUS_CFG_CHANGED
));
3829 tw32_f(MAC_TX_AUTO_NEG
, 0);
3831 tp
->mac_mode
&= ~(MAC_MODE_PORT_MODE_MASK
| MAC_MODE_HALF_DUPLEX
);
3832 tp
->mac_mode
|= MAC_MODE_PORT_MODE_TBI
;
3833 tw32_f(MAC_MODE
, tp
->mac_mode
);
3836 if (tp
->phy_id
== PHY_ID_BCM8002
)
3837 tg3_init_bcm8002(tp
);
3839 /* Enable link change event even when serdes polling. */
3840 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
3843 current_link_up
= 0;
3844 mac_status
= tr32(MAC_STATUS
);
3846 if (tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
)
3847 current_link_up
= tg3_setup_fiber_hw_autoneg(tp
, mac_status
);
3849 current_link_up
= tg3_setup_fiber_by_hand(tp
, mac_status
);
3851 tp
->hw_status
->status
=
3852 (SD_STATUS_UPDATED
|
3853 (tp
->hw_status
->status
& ~SD_STATUS_LINK_CHG
));
3855 for (i
= 0; i
< 100; i
++) {
3856 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
3857 MAC_STATUS_CFG_CHANGED
));
3859 if ((tr32(MAC_STATUS
) & (MAC_STATUS_SYNC_CHANGED
|
3860 MAC_STATUS_CFG_CHANGED
|
3861 MAC_STATUS_LNKSTATE_CHANGED
)) == 0)
3865 mac_status
= tr32(MAC_STATUS
);
3866 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) == 0) {
3867 current_link_up
= 0;
3868 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
&&
3869 tp
->serdes_counter
== 0) {
3870 tw32_f(MAC_MODE
, (tp
->mac_mode
|
3871 MAC_MODE_SEND_CONFIGS
));
3873 tw32_f(MAC_MODE
, tp
->mac_mode
);
3877 if (current_link_up
== 1) {
3878 tp
->link_config
.active_speed
= SPEED_1000
;
3879 tp
->link_config
.active_duplex
= DUPLEX_FULL
;
3880 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
3881 LED_CTRL_LNKLED_OVERRIDE
|
3882 LED_CTRL_1000MBPS_ON
));
3884 tp
->link_config
.active_speed
= SPEED_INVALID
;
3885 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
3886 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
3887 LED_CTRL_LNKLED_OVERRIDE
|
3888 LED_CTRL_TRAFFIC_OVERRIDE
));
3891 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
3892 if (current_link_up
)
3893 netif_carrier_on(tp
->dev
);
3895 netif_carrier_off(tp
->dev
);
3896 tg3_link_report(tp
);
3898 u32 now_pause_cfg
= tp
->link_config
.active_flowctrl
;
3899 if (orig_pause_cfg
!= now_pause_cfg
||
3900 orig_active_speed
!= tp
->link_config
.active_speed
||
3901 orig_active_duplex
!= tp
->link_config
.active_duplex
)
3902 tg3_link_report(tp
);
3908 static int tg3_setup_fiber_mii_phy(struct tg3
*tp
, int force_reset
)
3910 int current_link_up
, err
= 0;
3914 u32 local_adv
, remote_adv
;
3916 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3917 tw32_f(MAC_MODE
, tp
->mac_mode
);
3923 (MAC_STATUS_SYNC_CHANGED
|
3924 MAC_STATUS_CFG_CHANGED
|
3925 MAC_STATUS_MI_COMPLETION
|
3926 MAC_STATUS_LNKSTATE_CHANGED
));
3932 current_link_up
= 0;
3933 current_speed
= SPEED_INVALID
;
3934 current_duplex
= DUPLEX_INVALID
;
3936 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3937 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3938 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
3939 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
3940 bmsr
|= BMSR_LSTATUS
;
3942 bmsr
&= ~BMSR_LSTATUS
;
3945 err
|= tg3_readphy(tp
, MII_BMCR
, &bmcr
);
3947 if ((tp
->link_config
.autoneg
== AUTONEG_ENABLE
) && !force_reset
&&
3948 (tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
)) {
3949 /* do nothing, just check for link up at the end */
3950 } else if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3953 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
3954 new_adv
= adv
& ~(ADVERTISE_1000XFULL
| ADVERTISE_1000XHALF
|
3955 ADVERTISE_1000XPAUSE
|
3956 ADVERTISE_1000XPSE_ASYM
|
3959 new_adv
|= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3961 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
3962 new_adv
|= ADVERTISE_1000XHALF
;
3963 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
3964 new_adv
|= ADVERTISE_1000XFULL
;
3966 if ((new_adv
!= adv
) || !(bmcr
& BMCR_ANENABLE
)) {
3967 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
3968 bmcr
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
3969 tg3_writephy(tp
, MII_BMCR
, bmcr
);
3971 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
3972 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5714S
;
3973 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3980 bmcr
&= ~BMCR_SPEED1000
;
3981 new_bmcr
= bmcr
& ~(BMCR_ANENABLE
| BMCR_FULLDPLX
);
3983 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
3984 new_bmcr
|= BMCR_FULLDPLX
;
3986 if (new_bmcr
!= bmcr
) {
3987 /* BMCR_SPEED1000 is a reserved bit that needs
3988 * to be set on write.
3990 new_bmcr
|= BMCR_SPEED1000
;
3992 /* Force a linkdown */
3993 if (netif_carrier_ok(tp
->dev
)) {
3996 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
3997 adv
&= ~(ADVERTISE_1000XFULL
|
3998 ADVERTISE_1000XHALF
|
4000 tg3_writephy(tp
, MII_ADVERTISE
, adv
);
4001 tg3_writephy(tp
, MII_BMCR
, bmcr
|
4005 netif_carrier_off(tp
->dev
);
4007 tg3_writephy(tp
, MII_BMCR
, new_bmcr
);
4009 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4010 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4011 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
4013 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
4014 bmsr
|= BMSR_LSTATUS
;
4016 bmsr
&= ~BMSR_LSTATUS
;
4018 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4022 if (bmsr
& BMSR_LSTATUS
) {
4023 current_speed
= SPEED_1000
;
4024 current_link_up
= 1;
4025 if (bmcr
& BMCR_FULLDPLX
)
4026 current_duplex
= DUPLEX_FULL
;
4028 current_duplex
= DUPLEX_HALF
;
4033 if (bmcr
& BMCR_ANENABLE
) {
4036 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &local_adv
);
4037 err
|= tg3_readphy(tp
, MII_LPA
, &remote_adv
);
4038 common
= local_adv
& remote_adv
;
4039 if (common
& (ADVERTISE_1000XHALF
|
4040 ADVERTISE_1000XFULL
)) {
4041 if (common
& ADVERTISE_1000XFULL
)
4042 current_duplex
= DUPLEX_FULL
;
4044 current_duplex
= DUPLEX_HALF
;
4047 current_link_up
= 0;
4051 if (current_link_up
== 1 && current_duplex
== DUPLEX_FULL
)
4052 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
4054 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
4055 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
4056 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
4058 tw32_f(MAC_MODE
, tp
->mac_mode
);
4061 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
4063 tp
->link_config
.active_speed
= current_speed
;
4064 tp
->link_config
.active_duplex
= current_duplex
;
4066 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
4067 if (current_link_up
)
4068 netif_carrier_on(tp
->dev
);
4070 netif_carrier_off(tp
->dev
);
4071 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4073 tg3_link_report(tp
);
4078 static void tg3_serdes_parallel_detect(struct tg3
*tp
)
4080 if (tp
->serdes_counter
) {
4081 /* Give autoneg time to complete. */
4082 tp
->serdes_counter
--;
4085 if (!netif_carrier_ok(tp
->dev
) &&
4086 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
)) {
4089 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4090 if (bmcr
& BMCR_ANENABLE
) {
4093 /* Select shadow register 0x1f */
4094 tg3_writephy(tp
, 0x1c, 0x7c00);
4095 tg3_readphy(tp
, 0x1c, &phy1
);
4097 /* Select expansion interrupt status register */
4098 tg3_writephy(tp
, 0x17, 0x0f01);
4099 tg3_readphy(tp
, 0x15, &phy2
);
4100 tg3_readphy(tp
, 0x15, &phy2
);
4102 if ((phy1
& 0x10) && !(phy2
& 0x20)) {
4103 /* We have signal detect and not receiving
4104 * config code words, link is up by parallel
4108 bmcr
&= ~BMCR_ANENABLE
;
4109 bmcr
|= BMCR_SPEED1000
| BMCR_FULLDPLX
;
4110 tg3_writephy(tp
, MII_BMCR
, bmcr
);
4111 tp
->tg3_flags2
|= TG3_FLG2_PARALLEL_DETECT
;
4115 else if (netif_carrier_ok(tp
->dev
) &&
4116 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) &&
4117 (tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
)) {
4120 /* Select expansion interrupt status register */
4121 tg3_writephy(tp
, 0x17, 0x0f01);
4122 tg3_readphy(tp
, 0x15, &phy2
);
4126 /* Config code words received, turn on autoneg. */
4127 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4128 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANENABLE
);
4130 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4136 static int tg3_setup_phy(struct tg3
*tp
, int force_reset
)
4140 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
4141 err
= tg3_setup_fiber_phy(tp
, force_reset
);
4142 } else if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
4143 err
= tg3_setup_fiber_mii_phy(tp
, force_reset
);
4145 err
= tg3_setup_copper_phy(tp
, force_reset
);
4148 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
) {
4151 val
= tr32(TG3_CPMU_CLCK_STAT
) & CPMU_CLCK_STAT_MAC_CLCK_MASK
;
4152 if (val
== CPMU_CLCK_STAT_MAC_CLCK_62_5
)
4154 else if (val
== CPMU_CLCK_STAT_MAC_CLCK_6_25
)
4159 val
= tr32(GRC_MISC_CFG
) & ~GRC_MISC_CFG_PRESCALAR_MASK
;
4160 val
|= (scale
<< GRC_MISC_CFG_PRESCALAR_SHIFT
);
4161 tw32(GRC_MISC_CFG
, val
);
4164 if (tp
->link_config
.active_speed
== SPEED_1000
&&
4165 tp
->link_config
.active_duplex
== DUPLEX_HALF
)
4166 tw32(MAC_TX_LENGTHS
,
4167 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
4168 (6 << TX_LENGTHS_IPG_SHIFT
) |
4169 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
4171 tw32(MAC_TX_LENGTHS
,
4172 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
4173 (6 << TX_LENGTHS_IPG_SHIFT
) |
4174 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
4176 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
4177 if (netif_carrier_ok(tp
->dev
)) {
4178 tw32(HOSTCC_STAT_COAL_TICKS
,
4179 tp
->coal
.stats_block_coalesce_usecs
);
4181 tw32(HOSTCC_STAT_COAL_TICKS
, 0);
4185 if (tp
->tg3_flags
& TG3_FLAG_ASPM_WORKAROUND
) {
4186 u32 val
= tr32(PCIE_PWR_MGMT_THRESH
);
4187 if (!netif_carrier_ok(tp
->dev
))
4188 val
= (val
& ~PCIE_PWR_MGMT_L1_THRESH_MSK
) |
4191 val
|= PCIE_PWR_MGMT_L1_THRESH_MSK
;
4192 tw32(PCIE_PWR_MGMT_THRESH
, val
);
4198 /* This is called whenever we suspect that the system chipset is re-
4199 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4200 * is bogus tx completions. We try to recover by setting the
4201 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4204 static void tg3_tx_recover(struct tg3
*tp
)
4206 BUG_ON((tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
) ||
4207 tp
->write32_tx_mbox
== tg3_write_indirect_mbox
);
4209 printk(KERN_WARNING PFX
"%s: The system may be re-ordering memory-"
4210 "mapped I/O cycles to the network device, attempting to "
4211 "recover. Please report the problem to the driver maintainer "
4212 "and include system chipset information.\n", tp
->dev
->name
);
4214 spin_lock(&tp
->lock
);
4215 tp
->tg3_flags
|= TG3_FLAG_TX_RECOVERY_PENDING
;
4216 spin_unlock(&tp
->lock
);
4219 static inline u32
tg3_tx_avail(struct tg3
*tp
)
4222 return (tp
->tx_pending
-
4223 ((tp
->tx_prod
- tp
->tx_cons
) & (TG3_TX_RING_SIZE
- 1)));
4226 /* Tigon3 never reports partial packet sends. So we do not
4227 * need special logic to handle SKBs that have not had all
4228 * of their frags sent yet, like SunGEM does.
4230 static void tg3_tx(struct tg3
*tp
)
4232 u32 hw_idx
= tp
->hw_status
->idx
[0].tx_consumer
;
4233 u32 sw_idx
= tp
->tx_cons
;
4235 while (sw_idx
!= hw_idx
) {
4236 struct tx_ring_info
*ri
= &tp
->tx_buffers
[sw_idx
];
4237 struct sk_buff
*skb
= ri
->skb
;
4240 if (unlikely(skb
== NULL
)) {
4245 skb_dma_unmap(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
);
4249 sw_idx
= NEXT_TX(sw_idx
);
4251 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
4252 ri
= &tp
->tx_buffers
[sw_idx
];
4253 if (unlikely(ri
->skb
!= NULL
|| sw_idx
== hw_idx
))
4255 sw_idx
= NEXT_TX(sw_idx
);
4260 if (unlikely(tx_bug
)) {
4266 tp
->tx_cons
= sw_idx
;
4268 /* Need to make the tx_cons update visible to tg3_start_xmit()
4269 * before checking for netif_queue_stopped(). Without the
4270 * memory barrier, there is a small possibility that tg3_start_xmit()
4271 * will miss it and cause the queue to be stopped forever.
4275 if (unlikely(netif_queue_stopped(tp
->dev
) &&
4276 (tg3_tx_avail(tp
) > TG3_TX_WAKEUP_THRESH(tp
)))) {
4277 netif_tx_lock(tp
->dev
);
4278 if (netif_queue_stopped(tp
->dev
) &&
4279 (tg3_tx_avail(tp
) > TG3_TX_WAKEUP_THRESH(tp
)))
4280 netif_wake_queue(tp
->dev
);
4281 netif_tx_unlock(tp
->dev
);
4285 /* Returns size of skb allocated or < 0 on error.
4287 * We only need to fill in the address because the other members
4288 * of the RX descriptor are invariant, see tg3_init_rings.
4290 * Note the purposeful assymetry of cpu vs. chip accesses. For
4291 * posting buffers we only dirty the first cache line of the RX
4292 * descriptor (containing the address). Whereas for the RX status
4293 * buffers the cpu only reads the last cacheline of the RX descriptor
4294 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4296 static int tg3_alloc_rx_skb(struct tg3
*tp
, u32 opaque_key
,
4297 int src_idx
, u32 dest_idx_unmasked
)
4299 struct tg3_rx_buffer_desc
*desc
;
4300 struct ring_info
*map
, *src_map
;
4301 struct sk_buff
*skb
;
4303 int skb_size
, dest_idx
;
4306 switch (opaque_key
) {
4307 case RXD_OPAQUE_RING_STD
:
4308 dest_idx
= dest_idx_unmasked
% TG3_RX_RING_SIZE
;
4309 desc
= &tp
->rx_std
[dest_idx
];
4310 map
= &tp
->rx_std_buffers
[dest_idx
];
4312 src_map
= &tp
->rx_std_buffers
[src_idx
];
4313 skb_size
= tp
->rx_pkt_buf_sz
;
4316 case RXD_OPAQUE_RING_JUMBO
:
4317 dest_idx
= dest_idx_unmasked
% TG3_RX_JUMBO_RING_SIZE
;
4318 desc
= &tp
->rx_jumbo
[dest_idx
];
4319 map
= &tp
->rx_jumbo_buffers
[dest_idx
];
4321 src_map
= &tp
->rx_jumbo_buffers
[src_idx
];
4322 skb_size
= RX_JUMBO_PKT_BUF_SZ
;
4329 /* Do not overwrite any of the map or rp information
4330 * until we are sure we can commit to a new buffer.
4332 * Callers depend upon this behavior and assume that
4333 * we leave everything unchanged if we fail.
4335 skb
= netdev_alloc_skb(tp
->dev
, skb_size
);
4339 skb_reserve(skb
, tp
->rx_offset
);
4341 mapping
= pci_map_single(tp
->pdev
, skb
->data
,
4342 skb_size
- tp
->rx_offset
,
4343 PCI_DMA_FROMDEVICE
);
4346 pci_unmap_addr_set(map
, mapping
, mapping
);
4348 if (src_map
!= NULL
)
4349 src_map
->skb
= NULL
;
4351 desc
->addr_hi
= ((u64
)mapping
>> 32);
4352 desc
->addr_lo
= ((u64
)mapping
& 0xffffffff);
4357 /* We only need to move over in the address because the other
4358 * members of the RX descriptor are invariant. See notes above
4359 * tg3_alloc_rx_skb for full details.
4361 static void tg3_recycle_rx(struct tg3
*tp
, u32 opaque_key
,
4362 int src_idx
, u32 dest_idx_unmasked
)
4364 struct tg3_rx_buffer_desc
*src_desc
, *dest_desc
;
4365 struct ring_info
*src_map
, *dest_map
;
4368 switch (opaque_key
) {
4369 case RXD_OPAQUE_RING_STD
:
4370 dest_idx
= dest_idx_unmasked
% TG3_RX_RING_SIZE
;
4371 dest_desc
= &tp
->rx_std
[dest_idx
];
4372 dest_map
= &tp
->rx_std_buffers
[dest_idx
];
4373 src_desc
= &tp
->rx_std
[src_idx
];
4374 src_map
= &tp
->rx_std_buffers
[src_idx
];
4377 case RXD_OPAQUE_RING_JUMBO
:
4378 dest_idx
= dest_idx_unmasked
% TG3_RX_JUMBO_RING_SIZE
;
4379 dest_desc
= &tp
->rx_jumbo
[dest_idx
];
4380 dest_map
= &tp
->rx_jumbo_buffers
[dest_idx
];
4381 src_desc
= &tp
->rx_jumbo
[src_idx
];
4382 src_map
= &tp
->rx_jumbo_buffers
[src_idx
];
4389 dest_map
->skb
= src_map
->skb
;
4390 pci_unmap_addr_set(dest_map
, mapping
,
4391 pci_unmap_addr(src_map
, mapping
));
4392 dest_desc
->addr_hi
= src_desc
->addr_hi
;
4393 dest_desc
->addr_lo
= src_desc
->addr_lo
;
4395 src_map
->skb
= NULL
;
4398 #if TG3_VLAN_TAG_USED
4399 static int tg3_vlan_rx(struct tg3
*tp
, struct sk_buff
*skb
, u16 vlan_tag
)
4401 return vlan_gro_receive(&tp
->napi
, tp
->vlgrp
, vlan_tag
, skb
);
4405 /* The RX ring scheme is composed of multiple rings which post fresh
4406 * buffers to the chip, and one special ring the chip uses to report
4407 * status back to the host.
4409 * The special ring reports the status of received packets to the
4410 * host. The chip does not write into the original descriptor the
4411 * RX buffer was obtained from. The chip simply takes the original
4412 * descriptor as provided by the host, updates the status and length
4413 * field, then writes this into the next status ring entry.
4415 * Each ring the host uses to post buffers to the chip is described
4416 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4417 * it is first placed into the on-chip ram. When the packet's length
4418 * is known, it walks down the TG3_BDINFO entries to select the ring.
4419 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4420 * which is within the range of the new packet's length is chosen.
4422 * The "separate ring for rx status" scheme may sound queer, but it makes
4423 * sense from a cache coherency perspective. If only the host writes
4424 * to the buffer post rings, and only the chip writes to the rx status
4425 * rings, then cache lines never move beyond shared-modified state.
4426 * If both the host and chip were to write into the same ring, cache line
4427 * eviction could occur since both entities want it in an exclusive state.
4429 static int tg3_rx(struct tg3
*tp
, int budget
)
4431 u32 work_mask
, rx_std_posted
= 0;
4432 u32 sw_idx
= tp
->rx_rcb_ptr
;
4436 hw_idx
= tp
->hw_status
->idx
[0].rx_producer
;
4438 * We need to order the read of hw_idx and the read of
4439 * the opaque cookie.
4444 while (sw_idx
!= hw_idx
&& budget
> 0) {
4445 struct tg3_rx_buffer_desc
*desc
= &tp
->rx_rcb
[sw_idx
];
4447 struct sk_buff
*skb
;
4448 dma_addr_t dma_addr
;
4449 u32 opaque_key
, desc_idx
, *post_ptr
;
4451 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
4452 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
4453 if (opaque_key
== RXD_OPAQUE_RING_STD
) {
4454 dma_addr
= pci_unmap_addr(&tp
->rx_std_buffers
[desc_idx
],
4456 skb
= tp
->rx_std_buffers
[desc_idx
].skb
;
4457 post_ptr
= &tp
->rx_std_ptr
;
4459 } else if (opaque_key
== RXD_OPAQUE_RING_JUMBO
) {
4460 dma_addr
= pci_unmap_addr(&tp
->rx_jumbo_buffers
[desc_idx
],
4462 skb
= tp
->rx_jumbo_buffers
[desc_idx
].skb
;
4463 post_ptr
= &tp
->rx_jumbo_ptr
;
4466 goto next_pkt_nopost
;
4469 work_mask
|= opaque_key
;
4471 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
4472 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
)) {
4474 tg3_recycle_rx(tp
, opaque_key
,
4475 desc_idx
, *post_ptr
);
4477 /* Other statistics kept track of by card. */
4478 tp
->net_stats
.rx_dropped
++;
4482 len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) -
4485 if (len
> RX_COPY_THRESHOLD
4486 && tp
->rx_offset
== NET_IP_ALIGN
4487 /* rx_offset will likely not equal NET_IP_ALIGN
4488 * if this is a 5701 card running in PCI-X mode
4489 * [see tg3_get_invariants()]
4494 skb_size
= tg3_alloc_rx_skb(tp
, opaque_key
,
4495 desc_idx
, *post_ptr
);
4499 pci_unmap_single(tp
->pdev
, dma_addr
,
4500 skb_size
- tp
->rx_offset
,
4501 PCI_DMA_FROMDEVICE
);
4505 struct sk_buff
*copy_skb
;
4507 tg3_recycle_rx(tp
, opaque_key
,
4508 desc_idx
, *post_ptr
);
4510 copy_skb
= netdev_alloc_skb(tp
->dev
,
4511 len
+ TG3_RAW_IP_ALIGN
);
4512 if (copy_skb
== NULL
)
4513 goto drop_it_no_recycle
;
4515 skb_reserve(copy_skb
, TG3_RAW_IP_ALIGN
);
4516 skb_put(copy_skb
, len
);
4517 pci_dma_sync_single_for_cpu(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
4518 skb_copy_from_linear_data(skb
, copy_skb
->data
, len
);
4519 pci_dma_sync_single_for_device(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
4521 /* We'll reuse the original ring buffer. */
4525 if ((tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) &&
4526 (desc
->type_flags
& RXD_FLAG_TCPUDP_CSUM
) &&
4527 (((desc
->ip_tcp_csum
& RXD_TCPCSUM_MASK
)
4528 >> RXD_TCPCSUM_SHIFT
) == 0xffff))
4529 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
4531 skb
->ip_summed
= CHECKSUM_NONE
;
4533 skb
->protocol
= eth_type_trans(skb
, tp
->dev
);
4535 if (len
> (tp
->dev
->mtu
+ ETH_HLEN
) &&
4536 skb
->protocol
!= htons(ETH_P_8021Q
)) {
4541 #if TG3_VLAN_TAG_USED
4542 if (tp
->vlgrp
!= NULL
&&
4543 desc
->type_flags
& RXD_FLAG_VLAN
) {
4544 tg3_vlan_rx(tp
, skb
,
4545 desc
->err_vlan
& RXD_VLAN_MASK
);
4548 napi_gro_receive(&tp
->napi
, skb
);
4556 if (unlikely(rx_std_posted
>= tp
->rx_std_max_post
)) {
4557 u32 idx
= *post_ptr
% TG3_RX_RING_SIZE
;
4559 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX
+
4560 TG3_64BIT_REG_LOW
, idx
);
4561 work_mask
&= ~RXD_OPAQUE_RING_STD
;
4566 sw_idx
&= (TG3_RX_RCB_RING_SIZE(tp
) - 1);
4568 /* Refresh hw_idx to see if there is new work */
4569 if (sw_idx
== hw_idx
) {
4570 hw_idx
= tp
->hw_status
->idx
[0].rx_producer
;
4575 /* ACK the status ring. */
4576 tp
->rx_rcb_ptr
= sw_idx
;
4577 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
, sw_idx
);
4579 /* Refill RX ring(s). */
4580 if (work_mask
& RXD_OPAQUE_RING_STD
) {
4581 sw_idx
= tp
->rx_std_ptr
% TG3_RX_RING_SIZE
;
4582 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX
+ TG3_64BIT_REG_LOW
,
4585 if (work_mask
& RXD_OPAQUE_RING_JUMBO
) {
4586 sw_idx
= tp
->rx_jumbo_ptr
% TG3_RX_JUMBO_RING_SIZE
;
4587 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX
+ TG3_64BIT_REG_LOW
,
4595 static int tg3_poll_work(struct tg3
*tp
, int work_done
, int budget
)
4597 struct tg3_hw_status
*sblk
= tp
->hw_status
;
4599 /* handle link change and other phy events */
4600 if (!(tp
->tg3_flags
&
4601 (TG3_FLAG_USE_LINKCHG_REG
|
4602 TG3_FLAG_POLL_SERDES
))) {
4603 if (sblk
->status
& SD_STATUS_LINK_CHG
) {
4604 sblk
->status
= SD_STATUS_UPDATED
|
4605 (sblk
->status
& ~SD_STATUS_LINK_CHG
);
4606 spin_lock(&tp
->lock
);
4607 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
4609 (MAC_STATUS_SYNC_CHANGED
|
4610 MAC_STATUS_CFG_CHANGED
|
4611 MAC_STATUS_MI_COMPLETION
|
4612 MAC_STATUS_LNKSTATE_CHANGED
));
4615 tg3_setup_phy(tp
, 0);
4616 spin_unlock(&tp
->lock
);
4620 /* run TX completion thread */
4621 if (sblk
->idx
[0].tx_consumer
!= tp
->tx_cons
) {
4623 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
4627 /* run RX thread, within the bounds set by NAPI.
4628 * All RX "locking" is done by ensuring outside
4629 * code synchronizes with tg3->napi.poll()
4631 if (sblk
->idx
[0].rx_producer
!= tp
->rx_rcb_ptr
)
4632 work_done
+= tg3_rx(tp
, budget
- work_done
);
4637 static int tg3_poll(struct napi_struct
*napi
, int budget
)
4639 struct tg3
*tp
= container_of(napi
, struct tg3
, napi
);
4641 struct tg3_hw_status
*sblk
= tp
->hw_status
;
4644 work_done
= tg3_poll_work(tp
, work_done
, budget
);
4646 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
4649 if (unlikely(work_done
>= budget
))
4652 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
4653 /* tp->last_tag is used in tg3_restart_ints() below
4654 * to tell the hw how much work has been processed,
4655 * so we must read it before checking for more work.
4657 tp
->last_tag
= sblk
->status_tag
;
4658 tp
->last_irq_tag
= tp
->last_tag
;
4661 sblk
->status
&= ~SD_STATUS_UPDATED
;
4663 if (likely(!tg3_has_work(tp
))) {
4664 napi_complete(napi
);
4665 tg3_restart_ints(tp
);
4673 /* work_done is guaranteed to be less than budget. */
4674 napi_complete(napi
);
4675 schedule_work(&tp
->reset_task
);
4679 static void tg3_irq_quiesce(struct tg3
*tp
)
4681 BUG_ON(tp
->irq_sync
);
4686 synchronize_irq(tp
->pdev
->irq
);
4689 static inline int tg3_irq_sync(struct tg3
*tp
)
4691 return tp
->irq_sync
;
4694 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4695 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4696 * with as well. Most of the time, this is not necessary except when
4697 * shutting down the device.
4699 static inline void tg3_full_lock(struct tg3
*tp
, int irq_sync
)
4701 spin_lock_bh(&tp
->lock
);
4703 tg3_irq_quiesce(tp
);
4706 static inline void tg3_full_unlock(struct tg3
*tp
)
4708 spin_unlock_bh(&tp
->lock
);
4711 /* One-shot MSI handler - Chip automatically disables interrupt
4712 * after sending MSI so driver doesn't have to do it.
4714 static irqreturn_t
tg3_msi_1shot(int irq
, void *dev_id
)
4716 struct net_device
*dev
= dev_id
;
4717 struct tg3
*tp
= netdev_priv(dev
);
4719 prefetch(tp
->hw_status
);
4720 prefetch(&tp
->rx_rcb
[tp
->rx_rcb_ptr
]);
4722 if (likely(!tg3_irq_sync(tp
)))
4723 napi_schedule(&tp
->napi
);
4728 /* MSI ISR - No need to check for interrupt sharing and no need to
4729 * flush status block and interrupt mailbox. PCI ordering rules
4730 * guarantee that MSI will arrive after the status block.
4732 static irqreturn_t
tg3_msi(int irq
, void *dev_id
)
4734 struct net_device
*dev
= dev_id
;
4735 struct tg3
*tp
= netdev_priv(dev
);
4737 prefetch(tp
->hw_status
);
4738 prefetch(&tp
->rx_rcb
[tp
->rx_rcb_ptr
]);
4740 * Writing any value to intr-mbox-0 clears PCI INTA# and
4741 * chip-internal interrupt pending events.
4742 * Writing non-zero to intr-mbox-0 additional tells the
4743 * NIC to stop sending us irqs, engaging "in-intr-handler"
4746 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
4747 if (likely(!tg3_irq_sync(tp
)))
4748 napi_schedule(&tp
->napi
);
4750 return IRQ_RETVAL(1);
4753 static irqreturn_t
tg3_interrupt(int irq
, void *dev_id
)
4755 struct net_device
*dev
= dev_id
;
4756 struct tg3
*tp
= netdev_priv(dev
);
4757 struct tg3_hw_status
*sblk
= tp
->hw_status
;
4758 unsigned int handled
= 1;
4760 /* In INTx mode, it is possible for the interrupt to arrive at
4761 * the CPU before the status block posted prior to the interrupt.
4762 * Reading the PCI State register will confirm whether the
4763 * interrupt is ours and will flush the status block.
4765 if (unlikely(!(sblk
->status
& SD_STATUS_UPDATED
))) {
4766 if ((tp
->tg3_flags
& TG3_FLAG_CHIP_RESETTING
) ||
4767 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
4774 * Writing any value to intr-mbox-0 clears PCI INTA# and
4775 * chip-internal interrupt pending events.
4776 * Writing non-zero to intr-mbox-0 additional tells the
4777 * NIC to stop sending us irqs, engaging "in-intr-handler"
4780 * Flush the mailbox to de-assert the IRQ immediately to prevent
4781 * spurious interrupts. The flush impacts performance but
4782 * excessive spurious interrupts can be worse in some cases.
4784 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
4785 if (tg3_irq_sync(tp
))
4787 sblk
->status
&= ~SD_STATUS_UPDATED
;
4788 if (likely(tg3_has_work(tp
))) {
4789 prefetch(&tp
->rx_rcb
[tp
->rx_rcb_ptr
]);
4790 napi_schedule(&tp
->napi
);
4792 /* No work, shared interrupt perhaps? re-enable
4793 * interrupts, and flush that PCI write
4795 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
4799 return IRQ_RETVAL(handled
);
4802 static irqreturn_t
tg3_interrupt_tagged(int irq
, void *dev_id
)
4804 struct net_device
*dev
= dev_id
;
4805 struct tg3
*tp
= netdev_priv(dev
);
4806 struct tg3_hw_status
*sblk
= tp
->hw_status
;
4807 unsigned int handled
= 1;
4809 /* In INTx mode, it is possible for the interrupt to arrive at
4810 * the CPU before the status block posted prior to the interrupt.
4811 * Reading the PCI State register will confirm whether the
4812 * interrupt is ours and will flush the status block.
4814 if (unlikely(sblk
->status_tag
== tp
->last_irq_tag
)) {
4815 if ((tp
->tg3_flags
& TG3_FLAG_CHIP_RESETTING
) ||
4816 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
4823 * writing any value to intr-mbox-0 clears PCI INTA# and
4824 * chip-internal interrupt pending events.
4825 * writing non-zero to intr-mbox-0 additional tells the
4826 * NIC to stop sending us irqs, engaging "in-intr-handler"
4829 * Flush the mailbox to de-assert the IRQ immediately to prevent
4830 * spurious interrupts. The flush impacts performance but
4831 * excessive spurious interrupts can be worse in some cases.
4833 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
4836 * In a shared interrupt configuration, sometimes other devices'
4837 * interrupts will scream. We record the current status tag here
4838 * so that the above check can report that the screaming interrupts
4839 * are unhandled. Eventually they will be silenced.
4841 tp
->last_irq_tag
= sblk
->status_tag
;
4843 if (tg3_irq_sync(tp
))
4846 prefetch(&tp
->rx_rcb
[tp
->rx_rcb_ptr
]);
4848 napi_schedule(&tp
->napi
);
4851 return IRQ_RETVAL(handled
);
4854 /* ISR for interrupt test */
4855 static irqreturn_t
tg3_test_isr(int irq
, void *dev_id
)
4857 struct net_device
*dev
= dev_id
;
4858 struct tg3
*tp
= netdev_priv(dev
);
4859 struct tg3_hw_status
*sblk
= tp
->hw_status
;
4861 if ((sblk
->status
& SD_STATUS_UPDATED
) ||
4862 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
4863 tg3_disable_ints(tp
);
4864 return IRQ_RETVAL(1);
4866 return IRQ_RETVAL(0);
4869 static int tg3_init_hw(struct tg3
*, int);
4870 static int tg3_halt(struct tg3
*, int, int);
4872 /* Restart hardware after configuration changes, self-test, etc.
4873 * Invoked with tp->lock held.
4875 static int tg3_restart_hw(struct tg3
*tp
, int reset_phy
)
4876 __releases(tp
->lock
)
4877 __acquires(tp
->lock
)
4881 err
= tg3_init_hw(tp
, reset_phy
);
4883 printk(KERN_ERR PFX
"%s: Failed to re-initialize device, "
4884 "aborting.\n", tp
->dev
->name
);
4885 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
4886 tg3_full_unlock(tp
);
4887 del_timer_sync(&tp
->timer
);
4889 napi_enable(&tp
->napi
);
4891 tg3_full_lock(tp
, 0);
4896 #ifdef CONFIG_NET_POLL_CONTROLLER
4897 static void tg3_poll_controller(struct net_device
*dev
)
4899 struct tg3
*tp
= netdev_priv(dev
);
4901 tg3_interrupt(tp
->pdev
->irq
, dev
);
4905 static void tg3_reset_task(struct work_struct
*work
)
4907 struct tg3
*tp
= container_of(work
, struct tg3
, reset_task
);
4909 unsigned int restart_timer
;
4911 tg3_full_lock(tp
, 0);
4913 if (!netif_running(tp
->dev
)) {
4914 tg3_full_unlock(tp
);
4918 tg3_full_unlock(tp
);
4924 tg3_full_lock(tp
, 1);
4926 restart_timer
= tp
->tg3_flags2
& TG3_FLG2_RESTART_TIMER
;
4927 tp
->tg3_flags2
&= ~TG3_FLG2_RESTART_TIMER
;
4929 if (tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
) {
4930 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
4931 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
4932 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
4933 tp
->tg3_flags
&= ~TG3_FLAG_TX_RECOVERY_PENDING
;
4936 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 0);
4937 err
= tg3_init_hw(tp
, 1);
4941 tg3_netif_start(tp
);
4944 mod_timer(&tp
->timer
, jiffies
+ 1);
4947 tg3_full_unlock(tp
);
4953 static void tg3_dump_short_state(struct tg3
*tp
)
4955 printk(KERN_ERR PFX
"DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4956 tr32(MAC_TX_STATUS
), tr32(MAC_RX_STATUS
));
4957 printk(KERN_ERR PFX
"DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4958 tr32(RDMAC_STATUS
), tr32(WDMAC_STATUS
));
4961 static void tg3_tx_timeout(struct net_device
*dev
)
4963 struct tg3
*tp
= netdev_priv(dev
);
4965 if (netif_msg_tx_err(tp
)) {
4966 printk(KERN_ERR PFX
"%s: transmit timed out, resetting\n",
4968 tg3_dump_short_state(tp
);
4971 schedule_work(&tp
->reset_task
);
4974 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4975 static inline int tg3_4g_overflow_test(dma_addr_t mapping
, int len
)
4977 u32 base
= (u32
) mapping
& 0xffffffff;
4979 return ((base
> 0xffffdcc0) &&
4980 (base
+ len
+ 8 < base
));
4983 /* Test for DMA addresses > 40-bit */
4984 static inline int tg3_40bit_overflow_test(struct tg3
*tp
, dma_addr_t mapping
,
4987 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
4988 if (tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
)
4989 return (((u64
) mapping
+ len
) > DMA_BIT_MASK(40));
4996 static void tg3_set_txd(struct tg3
*, int, dma_addr_t
, int, u32
, u32
);
4998 /* Workaround 4GB and 40-bit hardware DMA bugs. */
4999 static int tigon3_dma_hwbug_workaround(struct tg3
*tp
, struct sk_buff
*skb
,
5000 u32 last_plus_one
, u32
*start
,
5001 u32 base_flags
, u32 mss
)
5003 struct sk_buff
*new_skb
;
5004 dma_addr_t new_addr
= 0;
5008 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
5009 new_skb
= skb_copy(skb
, GFP_ATOMIC
);
5011 int more_headroom
= 4 - ((unsigned long)skb
->data
& 3);
5013 new_skb
= skb_copy_expand(skb
,
5014 skb_headroom(skb
) + more_headroom
,
5015 skb_tailroom(skb
), GFP_ATOMIC
);
5021 /* New SKB is guaranteed to be linear. */
5023 ret
= skb_dma_map(&tp
->pdev
->dev
, new_skb
, DMA_TO_DEVICE
);
5024 new_addr
= skb_shinfo(new_skb
)->dma_maps
[0];
5026 /* Make sure new skb does not cross any 4G boundaries.
5027 * Drop the packet if it does.
5029 if (ret
|| tg3_4g_overflow_test(new_addr
, new_skb
->len
)) {
5031 skb_dma_unmap(&tp
->pdev
->dev
, new_skb
,
5034 dev_kfree_skb(new_skb
);
5037 tg3_set_txd(tp
, entry
, new_addr
, new_skb
->len
,
5038 base_flags
, 1 | (mss
<< 1));
5039 *start
= NEXT_TX(entry
);
5043 /* Now clean up the sw ring entries. */
5045 while (entry
!= last_plus_one
) {
5047 tp
->tx_buffers
[entry
].skb
= new_skb
;
5049 tp
->tx_buffers
[entry
].skb
= NULL
;
5051 entry
= NEXT_TX(entry
);
5055 skb_dma_unmap(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
);
5061 static void tg3_set_txd(struct tg3
*tp
, int entry
,
5062 dma_addr_t mapping
, int len
, u32 flags
,
5065 struct tg3_tx_buffer_desc
*txd
= &tp
->tx_ring
[entry
];
5066 int is_end
= (mss_and_is_end
& 0x1);
5067 u32 mss
= (mss_and_is_end
>> 1);
5071 flags
|= TXD_FLAG_END
;
5072 if (flags
& TXD_FLAG_VLAN
) {
5073 vlan_tag
= flags
>> 16;
5076 vlan_tag
|= (mss
<< TXD_MSS_SHIFT
);
5078 txd
->addr_hi
= ((u64
) mapping
>> 32);
5079 txd
->addr_lo
= ((u64
) mapping
& 0xffffffff);
5080 txd
->len_flags
= (len
<< TXD_LEN_SHIFT
) | flags
;
5081 txd
->vlan_tag
= vlan_tag
<< TXD_VLAN_TAG_SHIFT
;
5084 /* hard_start_xmit for devices that don't have any bugs and
5085 * support TG3_FLG2_HW_TSO_2 only.
5087 static int tg3_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
5089 struct tg3
*tp
= netdev_priv(dev
);
5090 u32 len
, entry
, base_flags
, mss
;
5091 struct skb_shared_info
*sp
;
5094 len
= skb_headlen(skb
);
5096 /* We are running in BH disabled context with netif_tx_lock
5097 * and TX reclaim runs via tp->napi.poll inside of a software
5098 * interrupt. Furthermore, IRQ processing runs lockless so we have
5099 * no IRQ context deadlocks to worry about either. Rejoice!
5101 if (unlikely(tg3_tx_avail(tp
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
5102 if (!netif_queue_stopped(dev
)) {
5103 netif_stop_queue(dev
);
5105 /* This is a hard error, log it. */
5106 printk(KERN_ERR PFX
"%s: BUG! Tx Ring full when "
5107 "queue awake!\n", dev
->name
);
5109 return NETDEV_TX_BUSY
;
5112 entry
= tp
->tx_prod
;
5115 if ((mss
= skb_shinfo(skb
)->gso_size
) != 0) {
5116 int tcp_opt_len
, ip_tcp_len
;
5118 if (skb_header_cloned(skb
) &&
5119 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
5124 if (skb_shinfo(skb
)->gso_type
& SKB_GSO_TCPV6
)
5125 mss
|= (skb_headlen(skb
) - ETH_HLEN
) << 9;
5127 struct iphdr
*iph
= ip_hdr(skb
);
5129 tcp_opt_len
= tcp_optlen(skb
);
5130 ip_tcp_len
= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
5133 iph
->tot_len
= htons(mss
+ ip_tcp_len
+ tcp_opt_len
);
5134 mss
|= (ip_tcp_len
+ tcp_opt_len
) << 9;
5137 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
5138 TXD_FLAG_CPU_POST_DMA
);
5140 tcp_hdr(skb
)->check
= 0;
5143 else if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
5144 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
5145 #if TG3_VLAN_TAG_USED
5146 if (tp
->vlgrp
!= NULL
&& vlan_tx_tag_present(skb
))
5147 base_flags
|= (TXD_FLAG_VLAN
|
5148 (vlan_tx_tag_get(skb
) << 16));
5151 if (skb_dma_map(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
)) {
5156 sp
= skb_shinfo(skb
);
5158 mapping
= sp
->dma_maps
[0];
5160 tp
->tx_buffers
[entry
].skb
= skb
;
5162 tg3_set_txd(tp
, entry
, mapping
, len
, base_flags
,
5163 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
5165 entry
= NEXT_TX(entry
);
5167 /* Now loop through additional data fragments, and queue them. */
5168 if (skb_shinfo(skb
)->nr_frags
> 0) {
5169 unsigned int i
, last
;
5171 last
= skb_shinfo(skb
)->nr_frags
- 1;
5172 for (i
= 0; i
<= last
; i
++) {
5173 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5176 mapping
= sp
->dma_maps
[i
+ 1];
5177 tp
->tx_buffers
[entry
].skb
= NULL
;
5179 tg3_set_txd(tp
, entry
, mapping
, len
,
5180 base_flags
, (i
== last
) | (mss
<< 1));
5182 entry
= NEXT_TX(entry
);
5186 /* Packets are ready, update Tx producer idx local and on card. */
5187 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
), entry
);
5189 tp
->tx_prod
= entry
;
5190 if (unlikely(tg3_tx_avail(tp
) <= (MAX_SKB_FRAGS
+ 1))) {
5191 netif_stop_queue(dev
);
5192 if (tg3_tx_avail(tp
) > TG3_TX_WAKEUP_THRESH(tp
))
5193 netif_wake_queue(tp
->dev
);
5199 dev
->trans_start
= jiffies
;
5201 return NETDEV_TX_OK
;
5204 static int tg3_start_xmit_dma_bug(struct sk_buff
*, struct net_device
*);
5206 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5207 * TSO header is greater than 80 bytes.
5209 static int tg3_tso_bug(struct tg3
*tp
, struct sk_buff
*skb
)
5211 struct sk_buff
*segs
, *nskb
;
5213 /* Estimate the number of fragments in the worst case */
5214 if (unlikely(tg3_tx_avail(tp
) <= (skb_shinfo(skb
)->gso_segs
* 3))) {
5215 netif_stop_queue(tp
->dev
);
5216 if (tg3_tx_avail(tp
) <= (skb_shinfo(skb
)->gso_segs
* 3))
5217 return NETDEV_TX_BUSY
;
5219 netif_wake_queue(tp
->dev
);
5222 segs
= skb_gso_segment(skb
, tp
->dev
->features
& ~NETIF_F_TSO
);
5224 goto tg3_tso_bug_end
;
5230 tg3_start_xmit_dma_bug(nskb
, tp
->dev
);
5236 return NETDEV_TX_OK
;
5239 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5240 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5242 static int tg3_start_xmit_dma_bug(struct sk_buff
*skb
, struct net_device
*dev
)
5244 struct tg3
*tp
= netdev_priv(dev
);
5245 u32 len
, entry
, base_flags
, mss
;
5246 struct skb_shared_info
*sp
;
5247 int would_hit_hwbug
;
5250 len
= skb_headlen(skb
);
5252 /* We are running in BH disabled context with netif_tx_lock
5253 * and TX reclaim runs via tp->napi.poll inside of a software
5254 * interrupt. Furthermore, IRQ processing runs lockless so we have
5255 * no IRQ context deadlocks to worry about either. Rejoice!
5257 if (unlikely(tg3_tx_avail(tp
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
5258 if (!netif_queue_stopped(dev
)) {
5259 netif_stop_queue(dev
);
5261 /* This is a hard error, log it. */
5262 printk(KERN_ERR PFX
"%s: BUG! Tx Ring full when "
5263 "queue awake!\n", dev
->name
);
5265 return NETDEV_TX_BUSY
;
5268 entry
= tp
->tx_prod
;
5270 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
5271 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
5273 if ((mss
= skb_shinfo(skb
)->gso_size
) != 0) {
5275 int tcp_opt_len
, ip_tcp_len
, hdr_len
;
5277 if (skb_header_cloned(skb
) &&
5278 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
5283 tcp_opt_len
= tcp_optlen(skb
);
5284 ip_tcp_len
= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
5286 hdr_len
= ip_tcp_len
+ tcp_opt_len
;
5287 if (unlikely((ETH_HLEN
+ hdr_len
) > 80) &&
5288 (tp
->tg3_flags2
& TG3_FLG2_TSO_BUG
))
5289 return (tg3_tso_bug(tp
, skb
));
5291 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
5292 TXD_FLAG_CPU_POST_DMA
);
5296 iph
->tot_len
= htons(mss
+ hdr_len
);
5297 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
5298 tcp_hdr(skb
)->check
= 0;
5299 base_flags
&= ~TXD_FLAG_TCPUDP_CSUM
;
5301 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
5306 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) ||
5307 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
)) {
5308 if (tcp_opt_len
|| iph
->ihl
> 5) {
5311 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
5312 mss
|= (tsflags
<< 11);
5315 if (tcp_opt_len
|| iph
->ihl
> 5) {
5318 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
5319 base_flags
|= tsflags
<< 12;
5323 #if TG3_VLAN_TAG_USED
5324 if (tp
->vlgrp
!= NULL
&& vlan_tx_tag_present(skb
))
5325 base_flags
|= (TXD_FLAG_VLAN
|
5326 (vlan_tx_tag_get(skb
) << 16));
5329 if (skb_dma_map(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
)) {
5334 sp
= skb_shinfo(skb
);
5336 mapping
= sp
->dma_maps
[0];
5338 tp
->tx_buffers
[entry
].skb
= skb
;
5340 would_hit_hwbug
= 0;
5342 if (tp
->tg3_flags3
& TG3_FLG3_5701_DMA_BUG
)
5343 would_hit_hwbug
= 1;
5344 else if (tg3_4g_overflow_test(mapping
, len
))
5345 would_hit_hwbug
= 1;
5347 tg3_set_txd(tp
, entry
, mapping
, len
, base_flags
,
5348 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
5350 entry
= NEXT_TX(entry
);
5352 /* Now loop through additional data fragments, and queue them. */
5353 if (skb_shinfo(skb
)->nr_frags
> 0) {
5354 unsigned int i
, last
;
5356 last
= skb_shinfo(skb
)->nr_frags
- 1;
5357 for (i
= 0; i
<= last
; i
++) {
5358 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5361 mapping
= sp
->dma_maps
[i
+ 1];
5363 tp
->tx_buffers
[entry
].skb
= NULL
;
5365 if (tg3_4g_overflow_test(mapping
, len
))
5366 would_hit_hwbug
= 1;
5368 if (tg3_40bit_overflow_test(tp
, mapping
, len
))
5369 would_hit_hwbug
= 1;
5371 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
5372 tg3_set_txd(tp
, entry
, mapping
, len
,
5373 base_flags
, (i
== last
)|(mss
<< 1));
5375 tg3_set_txd(tp
, entry
, mapping
, len
,
5376 base_flags
, (i
== last
));
5378 entry
= NEXT_TX(entry
);
5382 if (would_hit_hwbug
) {
5383 u32 last_plus_one
= entry
;
5386 start
= entry
- 1 - skb_shinfo(skb
)->nr_frags
;
5387 start
&= (TG3_TX_RING_SIZE
- 1);
5389 /* If the workaround fails due to memory/mapping
5390 * failure, silently drop this packet.
5392 if (tigon3_dma_hwbug_workaround(tp
, skb
, last_plus_one
,
5393 &start
, base_flags
, mss
))
5399 /* Packets are ready, update Tx producer idx local and on card. */
5400 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
), entry
);
5402 tp
->tx_prod
= entry
;
5403 if (unlikely(tg3_tx_avail(tp
) <= (MAX_SKB_FRAGS
+ 1))) {
5404 netif_stop_queue(dev
);
5405 if (tg3_tx_avail(tp
) > TG3_TX_WAKEUP_THRESH(tp
))
5406 netif_wake_queue(tp
->dev
);
5412 dev
->trans_start
= jiffies
;
5414 return NETDEV_TX_OK
;
5417 static inline void tg3_set_mtu(struct net_device
*dev
, struct tg3
*tp
,
5422 if (new_mtu
> ETH_DATA_LEN
) {
5423 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
5424 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
5425 ethtool_op_set_tso(dev
, 0);
5428 tp
->tg3_flags
|= TG3_FLAG_JUMBO_RING_ENABLE
;
5430 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
5431 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
5432 tp
->tg3_flags
&= ~TG3_FLAG_JUMBO_RING_ENABLE
;
5436 static int tg3_change_mtu(struct net_device
*dev
, int new_mtu
)
5438 struct tg3
*tp
= netdev_priv(dev
);
5441 if (new_mtu
< TG3_MIN_MTU
|| new_mtu
> TG3_MAX_MTU(tp
))
5444 if (!netif_running(dev
)) {
5445 /* We'll just catch it later when the
5448 tg3_set_mtu(dev
, tp
, new_mtu
);
5456 tg3_full_lock(tp
, 1);
5458 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
5460 tg3_set_mtu(dev
, tp
, new_mtu
);
5462 err
= tg3_restart_hw(tp
, 0);
5465 tg3_netif_start(tp
);
5467 tg3_full_unlock(tp
);
5475 /* Free up pending packets in all rx/tx rings.
5477 * The chip has been shut down and the driver detached from
5478 * the networking, so no interrupts or new tx packets will
5479 * end up in the driver. tp->{tx,}lock is not held and we are not
5480 * in an interrupt context and thus may sleep.
5482 static void tg3_free_rings(struct tg3
*tp
)
5484 struct ring_info
*rxp
;
5487 for (i
= 0; i
< TG3_RX_RING_SIZE
; i
++) {
5488 rxp
= &tp
->rx_std_buffers
[i
];
5490 if (rxp
->skb
== NULL
)
5492 pci_unmap_single(tp
->pdev
,
5493 pci_unmap_addr(rxp
, mapping
),
5494 tp
->rx_pkt_buf_sz
- tp
->rx_offset
,
5495 PCI_DMA_FROMDEVICE
);
5496 dev_kfree_skb_any(rxp
->skb
);
5500 for (i
= 0; i
< TG3_RX_JUMBO_RING_SIZE
; i
++) {
5501 rxp
= &tp
->rx_jumbo_buffers
[i
];
5503 if (rxp
->skb
== NULL
)
5505 pci_unmap_single(tp
->pdev
,
5506 pci_unmap_addr(rxp
, mapping
),
5507 RX_JUMBO_PKT_BUF_SZ
- tp
->rx_offset
,
5508 PCI_DMA_FROMDEVICE
);
5509 dev_kfree_skb_any(rxp
->skb
);
5513 for (i
= 0; i
< TG3_TX_RING_SIZE
; ) {
5514 struct tx_ring_info
*txp
;
5515 struct sk_buff
*skb
;
5517 txp
= &tp
->tx_buffers
[i
];
5525 skb_dma_unmap(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
);
5529 i
+= skb_shinfo(skb
)->nr_frags
+ 1;
5531 dev_kfree_skb_any(skb
);
5535 /* Initialize tx/rx rings for packet processing.
5537 * The chip has been shut down and the driver detached from
5538 * the networking, so no interrupts or new tx packets will
5539 * end up in the driver. tp->{tx,}lock are held and thus
5542 static int tg3_init_rings(struct tg3
*tp
)
5546 /* Free up all the SKBs. */
5549 /* Zero out all descriptors. */
5550 memset(tp
->rx_std
, 0, TG3_RX_RING_BYTES
);
5551 memset(tp
->rx_jumbo
, 0, TG3_RX_JUMBO_RING_BYTES
);
5552 memset(tp
->rx_rcb
, 0, TG3_RX_RCB_RING_BYTES(tp
));
5553 memset(tp
->tx_ring
, 0, TG3_TX_RING_BYTES
);
5555 tp
->rx_pkt_buf_sz
= RX_PKT_BUF_SZ
;
5556 if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) &&
5557 (tp
->dev
->mtu
> ETH_DATA_LEN
))
5558 tp
->rx_pkt_buf_sz
= RX_JUMBO_PKT_BUF_SZ
;
5560 /* Initialize invariants of the rings, we only set this
5561 * stuff once. This works because the card does not
5562 * write into the rx buffer posting rings.
5564 for (i
= 0; i
< TG3_RX_RING_SIZE
; i
++) {
5565 struct tg3_rx_buffer_desc
*rxd
;
5567 rxd
= &tp
->rx_std
[i
];
5568 rxd
->idx_len
= (tp
->rx_pkt_buf_sz
- tp
->rx_offset
- 64)
5570 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
);
5571 rxd
->opaque
= (RXD_OPAQUE_RING_STD
|
5572 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
5575 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) {
5576 for (i
= 0; i
< TG3_RX_JUMBO_RING_SIZE
; i
++) {
5577 struct tg3_rx_buffer_desc
*rxd
;
5579 rxd
= &tp
->rx_jumbo
[i
];
5580 rxd
->idx_len
= (RX_JUMBO_PKT_BUF_SZ
- tp
->rx_offset
- 64)
5582 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
) |
5584 rxd
->opaque
= (RXD_OPAQUE_RING_JUMBO
|
5585 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
5589 /* Now allocate fresh SKBs for each rx ring. */
5590 for (i
= 0; i
< tp
->rx_pending
; i
++) {
5591 if (tg3_alloc_rx_skb(tp
, RXD_OPAQUE_RING_STD
, -1, i
) < 0) {
5592 printk(KERN_WARNING PFX
5593 "%s: Using a smaller RX standard ring, "
5594 "only %d out of %d buffers were allocated "
5596 tp
->dev
->name
, i
, tp
->rx_pending
);
5604 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) {
5605 for (i
= 0; i
< tp
->rx_jumbo_pending
; i
++) {
5606 if (tg3_alloc_rx_skb(tp
, RXD_OPAQUE_RING_JUMBO
,
5608 printk(KERN_WARNING PFX
5609 "%s: Using a smaller RX jumbo ring, "
5610 "only %d out of %d buffers were "
5611 "allocated successfully.\n",
5612 tp
->dev
->name
, i
, tp
->rx_jumbo_pending
);
5617 tp
->rx_jumbo_pending
= i
;
5626 * Must not be invoked with interrupt sources disabled and
5627 * the hardware shutdown down.
5629 static void tg3_free_consistent(struct tg3
*tp
)
5631 kfree(tp
->rx_std_buffers
);
5632 tp
->rx_std_buffers
= NULL
;
5634 pci_free_consistent(tp
->pdev
, TG3_RX_RING_BYTES
,
5635 tp
->rx_std
, tp
->rx_std_mapping
);
5639 pci_free_consistent(tp
->pdev
, TG3_RX_JUMBO_RING_BYTES
,
5640 tp
->rx_jumbo
, tp
->rx_jumbo_mapping
);
5641 tp
->rx_jumbo
= NULL
;
5644 pci_free_consistent(tp
->pdev
, TG3_RX_RCB_RING_BYTES(tp
),
5645 tp
->rx_rcb
, tp
->rx_rcb_mapping
);
5649 pci_free_consistent(tp
->pdev
, TG3_TX_RING_BYTES
,
5650 tp
->tx_ring
, tp
->tx_desc_mapping
);
5653 if (tp
->hw_status
) {
5654 pci_free_consistent(tp
->pdev
, TG3_HW_STATUS_SIZE
,
5655 tp
->hw_status
, tp
->status_mapping
);
5656 tp
->hw_status
= NULL
;
5659 pci_free_consistent(tp
->pdev
, sizeof(struct tg3_hw_stats
),
5660 tp
->hw_stats
, tp
->stats_mapping
);
5661 tp
->hw_stats
= NULL
;
5666 * Must not be invoked with interrupt sources disabled and
5667 * the hardware shutdown down. Can sleep.
5669 static int tg3_alloc_consistent(struct tg3
*tp
)
5671 tp
->rx_std_buffers
= kzalloc((sizeof(struct ring_info
) *
5673 TG3_RX_JUMBO_RING_SIZE
)) +
5674 (sizeof(struct tx_ring_info
) *
5677 if (!tp
->rx_std_buffers
)
5680 tp
->rx_jumbo_buffers
= &tp
->rx_std_buffers
[TG3_RX_RING_SIZE
];
5681 tp
->tx_buffers
= (struct tx_ring_info
*)
5682 &tp
->rx_jumbo_buffers
[TG3_RX_JUMBO_RING_SIZE
];
5684 tp
->rx_std
= pci_alloc_consistent(tp
->pdev
, TG3_RX_RING_BYTES
,
5685 &tp
->rx_std_mapping
);
5689 tp
->rx_jumbo
= pci_alloc_consistent(tp
->pdev
, TG3_RX_JUMBO_RING_BYTES
,
5690 &tp
->rx_jumbo_mapping
);
5695 tp
->rx_rcb
= pci_alloc_consistent(tp
->pdev
, TG3_RX_RCB_RING_BYTES(tp
),
5696 &tp
->rx_rcb_mapping
);
5700 tp
->tx_ring
= pci_alloc_consistent(tp
->pdev
, TG3_TX_RING_BYTES
,
5701 &tp
->tx_desc_mapping
);
5705 tp
->hw_status
= pci_alloc_consistent(tp
->pdev
,
5707 &tp
->status_mapping
);
5711 tp
->hw_stats
= pci_alloc_consistent(tp
->pdev
,
5712 sizeof(struct tg3_hw_stats
),
5713 &tp
->stats_mapping
);
5717 memset(tp
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
5718 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
5723 tg3_free_consistent(tp
);
5727 #define MAX_WAIT_CNT 1000
5729 /* To stop a block, clear the enable bit and poll till it
5730 * clears. tp->lock is held.
5732 static int tg3_stop_block(struct tg3
*tp
, unsigned long ofs
, u32 enable_bit
, int silent
)
5737 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
5744 /* We can't enable/disable these bits of the
5745 * 5705/5750, just say success.
5758 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
5761 if ((val
& enable_bit
) == 0)
5765 if (i
== MAX_WAIT_CNT
&& !silent
) {
5766 printk(KERN_ERR PFX
"tg3_stop_block timed out, "
5767 "ofs=%lx enable_bit=%x\n",
5775 /* tp->lock is held. */
5776 static int tg3_abort_hw(struct tg3
*tp
, int silent
)
5780 tg3_disable_ints(tp
);
5782 tp
->rx_mode
&= ~RX_MODE_ENABLE
;
5783 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
5786 err
= tg3_stop_block(tp
, RCVBDI_MODE
, RCVBDI_MODE_ENABLE
, silent
);
5787 err
|= tg3_stop_block(tp
, RCVLPC_MODE
, RCVLPC_MODE_ENABLE
, silent
);
5788 err
|= tg3_stop_block(tp
, RCVLSC_MODE
, RCVLSC_MODE_ENABLE
, silent
);
5789 err
|= tg3_stop_block(tp
, RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
, silent
);
5790 err
|= tg3_stop_block(tp
, RCVDCC_MODE
, RCVDCC_MODE_ENABLE
, silent
);
5791 err
|= tg3_stop_block(tp
, RCVCC_MODE
, RCVCC_MODE_ENABLE
, silent
);
5793 err
|= tg3_stop_block(tp
, SNDBDS_MODE
, SNDBDS_MODE_ENABLE
, silent
);
5794 err
|= tg3_stop_block(tp
, SNDBDI_MODE
, SNDBDI_MODE_ENABLE
, silent
);
5795 err
|= tg3_stop_block(tp
, SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
, silent
);
5796 err
|= tg3_stop_block(tp
, RDMAC_MODE
, RDMAC_MODE_ENABLE
, silent
);
5797 err
|= tg3_stop_block(tp
, SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
, silent
);
5798 err
|= tg3_stop_block(tp
, DMAC_MODE
, DMAC_MODE_ENABLE
, silent
);
5799 err
|= tg3_stop_block(tp
, SNDBDC_MODE
, SNDBDC_MODE_ENABLE
, silent
);
5801 tp
->mac_mode
&= ~MAC_MODE_TDE_ENABLE
;
5802 tw32_f(MAC_MODE
, tp
->mac_mode
);
5805 tp
->tx_mode
&= ~TX_MODE_ENABLE
;
5806 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
5808 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
5810 if (!(tr32(MAC_TX_MODE
) & TX_MODE_ENABLE
))
5813 if (i
>= MAX_WAIT_CNT
) {
5814 printk(KERN_ERR PFX
"tg3_abort_hw timed out for %s, "
5815 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5816 tp
->dev
->name
, tr32(MAC_TX_MODE
));
5820 err
|= tg3_stop_block(tp
, HOSTCC_MODE
, HOSTCC_MODE_ENABLE
, silent
);
5821 err
|= tg3_stop_block(tp
, WDMAC_MODE
, WDMAC_MODE_ENABLE
, silent
);
5822 err
|= tg3_stop_block(tp
, MBFREE_MODE
, MBFREE_MODE_ENABLE
, silent
);
5824 tw32(FTQ_RESET
, 0xffffffff);
5825 tw32(FTQ_RESET
, 0x00000000);
5827 err
|= tg3_stop_block(tp
, BUFMGR_MODE
, BUFMGR_MODE_ENABLE
, silent
);
5828 err
|= tg3_stop_block(tp
, MEMARB_MODE
, MEMARB_MODE_ENABLE
, silent
);
5831 memset(tp
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
5833 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
5838 static void tg3_ape_send_event(struct tg3
*tp
, u32 event
)
5843 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
5844 if (apedata
!= APE_SEG_SIG_MAGIC
)
5847 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
5848 if (!(apedata
& APE_FW_STATUS_READY
))
5851 /* Wait for up to 1 millisecond for APE to service previous event. */
5852 for (i
= 0; i
< 10; i
++) {
5853 if (tg3_ape_lock(tp
, TG3_APE_LOCK_MEM
))
5856 apedata
= tg3_ape_read32(tp
, TG3_APE_EVENT_STATUS
);
5858 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
5859 tg3_ape_write32(tp
, TG3_APE_EVENT_STATUS
,
5860 event
| APE_EVENT_STATUS_EVENT_PENDING
);
5862 tg3_ape_unlock(tp
, TG3_APE_LOCK_MEM
);
5864 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
5870 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
5871 tg3_ape_write32(tp
, TG3_APE_EVENT
, APE_EVENT_1
);
5874 static void tg3_ape_driver_state_change(struct tg3
*tp
, int kind
)
5879 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
5883 case RESET_KIND_INIT
:
5884 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
,
5885 APE_HOST_SEG_SIG_MAGIC
);
5886 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_LEN
,
5887 APE_HOST_SEG_LEN_MAGIC
);
5888 apedata
= tg3_ape_read32(tp
, TG3_APE_HOST_INIT_COUNT
);
5889 tg3_ape_write32(tp
, TG3_APE_HOST_INIT_COUNT
, ++apedata
);
5890 tg3_ape_write32(tp
, TG3_APE_HOST_DRIVER_ID
,
5891 APE_HOST_DRIVER_ID_MAGIC
);
5892 tg3_ape_write32(tp
, TG3_APE_HOST_BEHAVIOR
,
5893 APE_HOST_BEHAV_NO_PHYLOCK
);
5895 event
= APE_EVENT_STATUS_STATE_START
;
5897 case RESET_KIND_SHUTDOWN
:
5898 /* With the interface we are currently using,
5899 * APE does not track driver state. Wiping
5900 * out the HOST SEGMENT SIGNATURE forces
5901 * the APE to assume OS absent status.
5903 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
, 0x0);
5905 event
= APE_EVENT_STATUS_STATE_UNLOAD
;
5907 case RESET_KIND_SUSPEND
:
5908 event
= APE_EVENT_STATUS_STATE_SUSPEND
;
5914 event
|= APE_EVENT_STATUS_DRIVER_EVNT
| APE_EVENT_STATUS_STATE_CHNGE
;
5916 tg3_ape_send_event(tp
, event
);
5919 /* tp->lock is held. */
5920 static void tg3_write_sig_pre_reset(struct tg3
*tp
, int kind
)
5922 tg3_write_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
,
5923 NIC_SRAM_FIRMWARE_MBOX_MAGIC1
);
5925 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
5927 case RESET_KIND_INIT
:
5928 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
5932 case RESET_KIND_SHUTDOWN
:
5933 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
5937 case RESET_KIND_SUSPEND
:
5938 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
5947 if (kind
== RESET_KIND_INIT
||
5948 kind
== RESET_KIND_SUSPEND
)
5949 tg3_ape_driver_state_change(tp
, kind
);
5952 /* tp->lock is held. */
5953 static void tg3_write_sig_post_reset(struct tg3
*tp
, int kind
)
5955 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
5957 case RESET_KIND_INIT
:
5958 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
5959 DRV_STATE_START_DONE
);
5962 case RESET_KIND_SHUTDOWN
:
5963 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
5964 DRV_STATE_UNLOAD_DONE
);
5972 if (kind
== RESET_KIND_SHUTDOWN
)
5973 tg3_ape_driver_state_change(tp
, kind
);
5976 /* tp->lock is held. */
5977 static void tg3_write_sig_legacy(struct tg3
*tp
, int kind
)
5979 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
5981 case RESET_KIND_INIT
:
5982 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
5986 case RESET_KIND_SHUTDOWN
:
5987 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
5991 case RESET_KIND_SUSPEND
:
5992 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6002 static int tg3_poll_fw(struct tg3
*tp
)
6007 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6008 /* Wait up to 20ms for init done. */
6009 for (i
= 0; i
< 200; i
++) {
6010 if (tr32(VCPU_STATUS
) & VCPU_STATUS_INIT_DONE
)
6017 /* Wait for firmware initialization to complete. */
6018 for (i
= 0; i
< 100000; i
++) {
6019 tg3_read_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
, &val
);
6020 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
6025 /* Chip might not be fitted with firmware. Some Sun onboard
6026 * parts are configured like that. So don't signal the timeout
6027 * of the above loop as an error, but do report the lack of
6028 * running firmware once.
6031 !(tp
->tg3_flags2
& TG3_FLG2_NO_FWARE_REPORTED
)) {
6032 tp
->tg3_flags2
|= TG3_FLG2_NO_FWARE_REPORTED
;
6034 printk(KERN_INFO PFX
"%s: No firmware running.\n",
6041 /* Save PCI command register before chip reset */
6042 static void tg3_save_pci_state(struct tg3
*tp
)
6044 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &tp
->pci_cmd
);
6047 /* Restore PCI state after chip reset */
6048 static void tg3_restore_pci_state(struct tg3
*tp
)
6052 /* Re-enable indirect register accesses. */
6053 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
6054 tp
->misc_host_ctrl
);
6056 /* Set MAX PCI retry to zero. */
6057 val
= (PCISTATE_ROM_ENABLE
| PCISTATE_ROM_RETRY_ENABLE
);
6058 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
6059 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
))
6060 val
|= PCISTATE_RETRY_SAME_DMA
;
6061 /* Allow reads and writes to the APE register and memory space. */
6062 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
6063 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
6064 PCISTATE_ALLOW_APE_SHMEM_WR
;
6065 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, val
);
6067 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, tp
->pci_cmd
);
6069 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
) {
6070 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
6071 pcie_set_readrq(tp
->pdev
, 4096);
6073 pci_write_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
6074 tp
->pci_cacheline_sz
);
6075 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
6080 /* Make sure PCI-X relaxed ordering bit is clear. */
6081 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
6084 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
6086 pcix_cmd
&= ~PCI_X_CMD_ERO
;
6087 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
6091 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
6093 /* Chip reset on 5780 will reset MSI enable bit,
6094 * so need to restore it.
6096 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
6099 pci_read_config_word(tp
->pdev
,
6100 tp
->msi_cap
+ PCI_MSI_FLAGS
,
6102 pci_write_config_word(tp
->pdev
,
6103 tp
->msi_cap
+ PCI_MSI_FLAGS
,
6104 ctrl
| PCI_MSI_FLAGS_ENABLE
);
6105 val
= tr32(MSGINT_MODE
);
6106 tw32(MSGINT_MODE
, val
| MSGINT_MODE_ENABLE
);
6111 static void tg3_stop_fw(struct tg3
*);
6113 /* tp->lock is held. */
6114 static int tg3_chip_reset(struct tg3
*tp
)
6117 void (*write_op
)(struct tg3
*, u32
, u32
);
6124 tg3_ape_lock(tp
, TG3_APE_LOCK_GRC
);
6126 /* No matching tg3_nvram_unlock() after this because
6127 * chip reset below will undo the nvram lock.
6129 tp
->nvram_lock_cnt
= 0;
6131 /* GRC_MISC_CFG core clock reset will clear the memory
6132 * enable bit in PCI register 4 and the MSI enable bit
6133 * on some chips, so we save relevant registers here.
6135 tg3_save_pci_state(tp
);
6137 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
6138 (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
))
6139 tw32(GRC_FASTBOOT_PC
, 0);
6142 * We must avoid the readl() that normally takes place.
6143 * It locks machines, causes machine checks, and other
6144 * fun things. So, temporarily disable the 5701
6145 * hardware workaround, while we do the reset.
6147 write_op
= tp
->write32
;
6148 if (write_op
== tg3_write_flush_reg32
)
6149 tp
->write32
= tg3_write32
;
6151 /* Prevent the irq handler from reading or writing PCI registers
6152 * during chip reset when the memory enable bit in the PCI command
6153 * register may be cleared. The chip does not generate interrupt
6154 * at this time, but the irq handler may still be called due to irq
6155 * sharing or irqpoll.
6157 tp
->tg3_flags
|= TG3_FLAG_CHIP_RESETTING
;
6158 if (tp
->hw_status
) {
6159 tp
->hw_status
->status
= 0;
6160 tp
->hw_status
->status_tag
= 0;
6163 tp
->last_irq_tag
= 0;
6165 synchronize_irq(tp
->pdev
->irq
);
6168 val
= GRC_MISC_CFG_CORECLK_RESET
;
6170 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
6171 if (tr32(0x7e2c) == 0x60) {
6174 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
) {
6175 tw32(GRC_MISC_CFG
, (1 << 29));
6180 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6181 tw32(VCPU_STATUS
, tr32(VCPU_STATUS
) | VCPU_STATUS_DRV_RESET
);
6182 tw32(GRC_VCPU_EXT_CTRL
,
6183 tr32(GRC_VCPU_EXT_CTRL
) & ~GRC_VCPU_EXT_CTRL_HALT_CPU
);
6186 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
6187 val
|= GRC_MISC_CFG_KEEP_GPHY_POWER
;
6188 tw32(GRC_MISC_CFG
, val
);
6190 /* restore 5701 hardware bug workaround write method */
6191 tp
->write32
= write_op
;
6193 /* Unfortunately, we have to delay before the PCI read back.
6194 * Some 575X chips even will not respond to a PCI cfg access
6195 * when the reset command is given to the chip.
6197 * How do these hardware designers expect things to work
6198 * properly if the PCI write is posted for a long period
6199 * of time? It is always necessary to have some method by
6200 * which a register read back can occur to push the write
6201 * out which does the reset.
6203 * For most tg3 variants the trick below was working.
6208 /* Flush PCI posted writes. The normal MMIO registers
6209 * are inaccessible at this time so this is the only
6210 * way to make this reliably (actually, this is no longer
6211 * the case, see above). I tried to use indirect
6212 * register read/write but this upset some 5701 variants.
6214 pci_read_config_dword(tp
->pdev
, PCI_COMMAND
, &val
);
6218 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) && tp
->pcie_cap
) {
6219 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
) {
6223 /* Wait for link training to complete. */
6224 for (i
= 0; i
< 5000; i
++)
6227 pci_read_config_dword(tp
->pdev
, 0xc4, &cfg_val
);
6228 pci_write_config_dword(tp
->pdev
, 0xc4,
6229 cfg_val
| (1 << 15));
6232 /* Set PCIE max payload size to 128 bytes and
6233 * clear the "no snoop" and "relaxed ordering" bits.
6235 pci_write_config_word(tp
->pdev
,
6236 tp
->pcie_cap
+ PCI_EXP_DEVCTL
,
6239 pcie_set_readrq(tp
->pdev
, 4096);
6241 /* Clear error status */
6242 pci_write_config_word(tp
->pdev
,
6243 tp
->pcie_cap
+ PCI_EXP_DEVSTA
,
6244 PCI_EXP_DEVSTA_CED
|
6245 PCI_EXP_DEVSTA_NFED
|
6246 PCI_EXP_DEVSTA_FED
|
6247 PCI_EXP_DEVSTA_URD
);
6250 tg3_restore_pci_state(tp
);
6252 tp
->tg3_flags
&= ~TG3_FLAG_CHIP_RESETTING
;
6255 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
6256 val
= tr32(MEMARB_MODE
);
6257 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
6259 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A3
) {
6261 tw32(0x5000, 0x400);
6264 tw32(GRC_MODE
, tp
->grc_mode
);
6266 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
) {
6269 tw32(0xc4, val
| (1 << 15));
6272 if ((tp
->nic_sram_data_cfg
& NIC_SRAM_DATA_CFG_MINI_PCI
) != 0 &&
6273 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
6274 tp
->pci_clock_ctrl
|= CLOCK_CTRL_CLKRUN_OENABLE
;
6275 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
)
6276 tp
->pci_clock_ctrl
|= CLOCK_CTRL_FORCE_CLKRUN
;
6277 tw32(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
6280 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
6281 tp
->mac_mode
= MAC_MODE_PORT_MODE_TBI
;
6282 tw32_f(MAC_MODE
, tp
->mac_mode
);
6283 } else if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
6284 tp
->mac_mode
= MAC_MODE_PORT_MODE_GMII
;
6285 tw32_f(MAC_MODE
, tp
->mac_mode
);
6286 } else if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
6287 tp
->mac_mode
&= (MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
);
6288 if (tp
->mac_mode
& MAC_MODE_APE_TX_EN
)
6289 tp
->mac_mode
|= MAC_MODE_TDE_ENABLE
;
6290 tw32_f(MAC_MODE
, tp
->mac_mode
);
6292 tw32_f(MAC_MODE
, 0);
6297 tg3_ape_unlock(tp
, TG3_APE_LOCK_GRC
);
6299 err
= tg3_poll_fw(tp
);
6303 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
6304 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
) {
6307 tw32(0x7c00, val
| (1 << 25));
6310 /* Reprobe ASF enable state. */
6311 tp
->tg3_flags
&= ~TG3_FLAG_ENABLE_ASF
;
6312 tp
->tg3_flags2
&= ~TG3_FLG2_ASF_NEW_HANDSHAKE
;
6313 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
6314 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
6317 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
6318 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
6319 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
6320 tp
->last_event_jiffies
= jiffies
;
6321 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
6322 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
6329 /* tp->lock is held. */
6330 static void tg3_stop_fw(struct tg3
*tp
)
6332 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
6333 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
6334 /* Wait for RX cpu to ACK the previous event. */
6335 tg3_wait_for_event_ack(tp
);
6337 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_PAUSE_FW
);
6339 tg3_generate_fw_event(tp
);
6341 /* Wait for RX cpu to ACK this event. */
6342 tg3_wait_for_event_ack(tp
);
6346 /* tp->lock is held. */
6347 static int tg3_halt(struct tg3
*tp
, int kind
, int silent
)
6353 tg3_write_sig_pre_reset(tp
, kind
);
6355 tg3_abort_hw(tp
, silent
);
6356 err
= tg3_chip_reset(tp
);
6358 __tg3_set_mac_addr(tp
, 0);
6360 tg3_write_sig_legacy(tp
, kind
);
6361 tg3_write_sig_post_reset(tp
, kind
);
6369 #define RX_CPU_SCRATCH_BASE 0x30000
6370 #define RX_CPU_SCRATCH_SIZE 0x04000
6371 #define TX_CPU_SCRATCH_BASE 0x34000
6372 #define TX_CPU_SCRATCH_SIZE 0x04000
6374 /* tp->lock is held. */
6375 static int tg3_halt_cpu(struct tg3
*tp
, u32 offset
)
6379 BUG_ON(offset
== TX_CPU_BASE
&&
6380 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
));
6382 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6383 u32 val
= tr32(GRC_VCPU_EXT_CTRL
);
6385 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_HALT_CPU
);
6388 if (offset
== RX_CPU_BASE
) {
6389 for (i
= 0; i
< 10000; i
++) {
6390 tw32(offset
+ CPU_STATE
, 0xffffffff);
6391 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
6392 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
6396 tw32(offset
+ CPU_STATE
, 0xffffffff);
6397 tw32_f(offset
+ CPU_MODE
, CPU_MODE_HALT
);
6400 for (i
= 0; i
< 10000; i
++) {
6401 tw32(offset
+ CPU_STATE
, 0xffffffff);
6402 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
6403 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
6409 printk(KERN_ERR PFX
"tg3_reset_cpu timed out for %s, "
6412 (offset
== RX_CPU_BASE
? "RX" : "TX"));
6416 /* Clear firmware's nvram arbitration. */
6417 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
6418 tw32(NVRAM_SWARB
, SWARB_REQ_CLR0
);
6423 unsigned int fw_base
;
6424 unsigned int fw_len
;
6425 const __be32
*fw_data
;
6428 /* tp->lock is held. */
6429 static int tg3_load_firmware_cpu(struct tg3
*tp
, u32 cpu_base
, u32 cpu_scratch_base
,
6430 int cpu_scratch_size
, struct fw_info
*info
)
6432 int err
, lock_err
, i
;
6433 void (*write_op
)(struct tg3
*, u32
, u32
);
6435 if (cpu_base
== TX_CPU_BASE
&&
6436 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
6437 printk(KERN_ERR PFX
"tg3_load_firmware_cpu: Trying to load "
6438 "TX cpu firmware on %s which is 5705.\n",
6443 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
6444 write_op
= tg3_write_mem
;
6446 write_op
= tg3_write_indirect_reg32
;
6448 /* It is possible that bootcode is still loading at this point.
6449 * Get the nvram lock first before halting the cpu.
6451 lock_err
= tg3_nvram_lock(tp
);
6452 err
= tg3_halt_cpu(tp
, cpu_base
);
6454 tg3_nvram_unlock(tp
);
6458 for (i
= 0; i
< cpu_scratch_size
; i
+= sizeof(u32
))
6459 write_op(tp
, cpu_scratch_base
+ i
, 0);
6460 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
6461 tw32(cpu_base
+ CPU_MODE
, tr32(cpu_base
+CPU_MODE
)|CPU_MODE_HALT
);
6462 for (i
= 0; i
< (info
->fw_len
/ sizeof(u32
)); i
++)
6463 write_op(tp
, (cpu_scratch_base
+
6464 (info
->fw_base
& 0xffff) +
6466 be32_to_cpu(info
->fw_data
[i
]));
6474 /* tp->lock is held. */
6475 static int tg3_load_5701_a0_firmware_fix(struct tg3
*tp
)
6477 struct fw_info info
;
6478 const __be32
*fw_data
;
6481 fw_data
= (void *)tp
->fw
->data
;
6483 /* Firmware blob starts with version numbers, followed by
6484 start address and length. We are setting complete length.
6485 length = end_address_of_bss - start_address_of_text.
6486 Remainder is the blob to be loaded contiguously
6487 from start address. */
6489 info
.fw_base
= be32_to_cpu(fw_data
[1]);
6490 info
.fw_len
= tp
->fw
->size
- 12;
6491 info
.fw_data
= &fw_data
[3];
6493 err
= tg3_load_firmware_cpu(tp
, RX_CPU_BASE
,
6494 RX_CPU_SCRATCH_BASE
, RX_CPU_SCRATCH_SIZE
,
6499 err
= tg3_load_firmware_cpu(tp
, TX_CPU_BASE
,
6500 TX_CPU_SCRATCH_BASE
, TX_CPU_SCRATCH_SIZE
,
6505 /* Now startup only the RX cpu. */
6506 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
6507 tw32_f(RX_CPU_BASE
+ CPU_PC
, info
.fw_base
);
6509 for (i
= 0; i
< 5; i
++) {
6510 if (tr32(RX_CPU_BASE
+ CPU_PC
) == info
.fw_base
)
6512 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
6513 tw32(RX_CPU_BASE
+ CPU_MODE
, CPU_MODE_HALT
);
6514 tw32_f(RX_CPU_BASE
+ CPU_PC
, info
.fw_base
);
6518 printk(KERN_ERR PFX
"tg3_load_firmware fails for %s "
6519 "to set RX CPU PC, is %08x should be %08x\n",
6520 tp
->dev
->name
, tr32(RX_CPU_BASE
+ CPU_PC
),
6524 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
6525 tw32_f(RX_CPU_BASE
+ CPU_MODE
, 0x00000000);
6530 /* 5705 needs a special version of the TSO firmware. */
6532 /* tp->lock is held. */
6533 static int tg3_load_tso_firmware(struct tg3
*tp
)
6535 struct fw_info info
;
6536 const __be32
*fw_data
;
6537 unsigned long cpu_base
, cpu_scratch_base
, cpu_scratch_size
;
6540 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
6543 fw_data
= (void *)tp
->fw
->data
;
6545 /* Firmware blob starts with version numbers, followed by
6546 start address and length. We are setting complete length.
6547 length = end_address_of_bss - start_address_of_text.
6548 Remainder is the blob to be loaded contiguously
6549 from start address. */
6551 info
.fw_base
= be32_to_cpu(fw_data
[1]);
6552 cpu_scratch_size
= tp
->fw_len
;
6553 info
.fw_len
= tp
->fw
->size
- 12;
6554 info
.fw_data
= &fw_data
[3];
6556 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
6557 cpu_base
= RX_CPU_BASE
;
6558 cpu_scratch_base
= NIC_SRAM_MBUF_POOL_BASE5705
;
6560 cpu_base
= TX_CPU_BASE
;
6561 cpu_scratch_base
= TX_CPU_SCRATCH_BASE
;
6562 cpu_scratch_size
= TX_CPU_SCRATCH_SIZE
;
6565 err
= tg3_load_firmware_cpu(tp
, cpu_base
,
6566 cpu_scratch_base
, cpu_scratch_size
,
6571 /* Now startup the cpu. */
6572 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
6573 tw32_f(cpu_base
+ CPU_PC
, info
.fw_base
);
6575 for (i
= 0; i
< 5; i
++) {
6576 if (tr32(cpu_base
+ CPU_PC
) == info
.fw_base
)
6578 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
6579 tw32(cpu_base
+ CPU_MODE
, CPU_MODE_HALT
);
6580 tw32_f(cpu_base
+ CPU_PC
, info
.fw_base
);
6584 printk(KERN_ERR PFX
"tg3_load_tso_firmware fails for %s "
6585 "to set CPU PC, is %08x should be %08x\n",
6586 tp
->dev
->name
, tr32(cpu_base
+ CPU_PC
),
6590 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
6591 tw32_f(cpu_base
+ CPU_MODE
, 0x00000000);
6596 static int tg3_set_mac_addr(struct net_device
*dev
, void *p
)
6598 struct tg3
*tp
= netdev_priv(dev
);
6599 struct sockaddr
*addr
= p
;
6600 int err
= 0, skip_mac_1
= 0;
6602 if (!is_valid_ether_addr(addr
->sa_data
))
6605 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
6607 if (!netif_running(dev
))
6610 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
6611 u32 addr0_high
, addr0_low
, addr1_high
, addr1_low
;
6613 addr0_high
= tr32(MAC_ADDR_0_HIGH
);
6614 addr0_low
= tr32(MAC_ADDR_0_LOW
);
6615 addr1_high
= tr32(MAC_ADDR_1_HIGH
);
6616 addr1_low
= tr32(MAC_ADDR_1_LOW
);
6618 /* Skip MAC addr 1 if ASF is using it. */
6619 if ((addr0_high
!= addr1_high
|| addr0_low
!= addr1_low
) &&
6620 !(addr1_high
== 0 && addr1_low
== 0))
6623 spin_lock_bh(&tp
->lock
);
6624 __tg3_set_mac_addr(tp
, skip_mac_1
);
6625 spin_unlock_bh(&tp
->lock
);
6630 /* tp->lock is held. */
6631 static void tg3_set_bdinfo(struct tg3
*tp
, u32 bdinfo_addr
,
6632 dma_addr_t mapping
, u32 maxlen_flags
,
6636 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
6637 ((u64
) mapping
>> 32));
6639 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
),
6640 ((u64
) mapping
& 0xffffffff));
6642 (bdinfo_addr
+ TG3_BDINFO_MAXLEN_FLAGS
),
6645 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
6647 (bdinfo_addr
+ TG3_BDINFO_NIC_ADDR
),
6651 static void __tg3_set_rx_mode(struct net_device
*);
6652 static void __tg3_set_coalesce(struct tg3
*tp
, struct ethtool_coalesce
*ec
)
6654 tw32(HOSTCC_RXCOL_TICKS
, ec
->rx_coalesce_usecs
);
6655 tw32(HOSTCC_TXCOL_TICKS
, ec
->tx_coalesce_usecs
);
6656 tw32(HOSTCC_RXMAX_FRAMES
, ec
->rx_max_coalesced_frames
);
6657 tw32(HOSTCC_TXMAX_FRAMES
, ec
->tx_max_coalesced_frames
);
6658 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
6659 tw32(HOSTCC_RXCOAL_TICK_INT
, ec
->rx_coalesce_usecs_irq
);
6660 tw32(HOSTCC_TXCOAL_TICK_INT
, ec
->tx_coalesce_usecs_irq
);
6662 tw32(HOSTCC_RXCOAL_MAXF_INT
, ec
->rx_max_coalesced_frames_irq
);
6663 tw32(HOSTCC_TXCOAL_MAXF_INT
, ec
->tx_max_coalesced_frames_irq
);
6664 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
6665 u32 val
= ec
->stats_block_coalesce_usecs
;
6667 if (!netif_carrier_ok(tp
->dev
))
6670 tw32(HOSTCC_STAT_COAL_TICKS
, val
);
6674 /* tp->lock is held. */
6675 static int tg3_reset_hw(struct tg3
*tp
, int reset_phy
)
6677 u32 val
, rdmac_mode
;
6680 tg3_disable_ints(tp
);
6684 tg3_write_sig_pre_reset(tp
, RESET_KIND_INIT
);
6686 if (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) {
6687 tg3_abort_hw(tp
, 1);
6691 !(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
))
6694 err
= tg3_chip_reset(tp
);
6698 tg3_write_sig_legacy(tp
, RESET_KIND_INIT
);
6700 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
) {
6701 val
= tr32(TG3_CPMU_CTRL
);
6702 val
&= ~(CPMU_CTRL_LINK_AWARE_MODE
| CPMU_CTRL_LINK_IDLE_MODE
);
6703 tw32(TG3_CPMU_CTRL
, val
);
6705 val
= tr32(TG3_CPMU_LSPD_10MB_CLK
);
6706 val
&= ~CPMU_LSPD_10MB_MACCLK_MASK
;
6707 val
|= CPMU_LSPD_10MB_MACCLK_6_25
;
6708 tw32(TG3_CPMU_LSPD_10MB_CLK
, val
);
6710 val
= tr32(TG3_CPMU_LNK_AWARE_PWRMD
);
6711 val
&= ~CPMU_LNK_AWARE_MACCLK_MASK
;
6712 val
|= CPMU_LNK_AWARE_MACCLK_6_25
;
6713 tw32(TG3_CPMU_LNK_AWARE_PWRMD
, val
);
6715 val
= tr32(TG3_CPMU_HST_ACC
);
6716 val
&= ~CPMU_HST_ACC_MACCLK_MASK
;
6717 val
|= CPMU_HST_ACC_MACCLK_6_25
;
6718 tw32(TG3_CPMU_HST_ACC
, val
);
6721 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
6722 val
= tr32(PCIE_PWR_MGMT_THRESH
) & ~PCIE_PWR_MGMT_L1_THRESH_MSK
;
6723 val
|= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN
|
6724 PCIE_PWR_MGMT_L1_THRESH_4MS
;
6725 tw32(PCIE_PWR_MGMT_THRESH
, val
);
6728 /* This works around an issue with Athlon chipsets on
6729 * B3 tigon3 silicon. This bit has no effect on any
6730 * other revision. But do not set this on PCI Express
6731 * chips and don't even touch the clocks if the CPMU is present.
6733 if (!(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
)) {
6734 if (!(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
6735 tp
->pci_clock_ctrl
|= CLOCK_CTRL_DELAY_PCI_GRANT
;
6736 tw32_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
6739 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
6740 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
6741 val
= tr32(TG3PCI_PCISTATE
);
6742 val
|= PCISTATE_RETRY_SAME_DMA
;
6743 tw32(TG3PCI_PCISTATE
, val
);
6746 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
6747 /* Allow reads and writes to the
6748 * APE register and memory space.
6750 val
= tr32(TG3PCI_PCISTATE
);
6751 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
6752 PCISTATE_ALLOW_APE_SHMEM_WR
;
6753 tw32(TG3PCI_PCISTATE
, val
);
6756 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_BX
) {
6757 /* Enable some hw fixes. */
6758 val
= tr32(TG3PCI_MSI_DATA
);
6759 val
|= (1 << 26) | (1 << 28) | (1 << 29);
6760 tw32(TG3PCI_MSI_DATA
, val
);
6763 /* Descriptor ring init may make accesses to the
6764 * NIC SRAM area to setup the TX descriptors, so we
6765 * can only do this after the hardware has been
6766 * successfully reset.
6768 err
= tg3_init_rings(tp
);
6772 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5784
&&
6773 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5761
) {
6774 /* This value is determined during the probe time DMA
6775 * engine test, tg3_test_dma.
6777 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
6780 tp
->grc_mode
&= ~(GRC_MODE_HOST_SENDBDS
|
6781 GRC_MODE_4X_NIC_SEND_RINGS
|
6782 GRC_MODE_NO_TX_PHDR_CSUM
|
6783 GRC_MODE_NO_RX_PHDR_CSUM
);
6784 tp
->grc_mode
|= GRC_MODE_HOST_SENDBDS
;
6786 /* Pseudo-header checksum is done by hardware logic and not
6787 * the offload processers, so make the chip do the pseudo-
6788 * header checksums on receive. For transmit it is more
6789 * convenient to do the pseudo-header checksum in software
6790 * as Linux does that on transmit for us in all cases.
6792 tp
->grc_mode
|= GRC_MODE_NO_TX_PHDR_CSUM
;
6796 (GRC_MODE_IRQ_ON_MAC_ATTN
| GRC_MODE_HOST_STACKUP
));
6798 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6799 val
= tr32(GRC_MISC_CFG
);
6801 val
|= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT
);
6802 tw32(GRC_MISC_CFG
, val
);
6804 /* Initialize MBUF/DESC pool. */
6805 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
6807 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5705
) {
6808 tw32(BUFMGR_MB_POOL_ADDR
, NIC_SRAM_MBUF_POOL_BASE
);
6809 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
6810 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE64
);
6812 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE96
);
6813 tw32(BUFMGR_DMA_DESC_POOL_ADDR
, NIC_SRAM_DMA_DESC_POOL_BASE
);
6814 tw32(BUFMGR_DMA_DESC_POOL_SIZE
, NIC_SRAM_DMA_DESC_POOL_SIZE
);
6816 else if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
6819 fw_len
= tp
->fw_len
;
6820 fw_len
= (fw_len
+ (0x80 - 1)) & ~(0x80 - 1);
6821 tw32(BUFMGR_MB_POOL_ADDR
,
6822 NIC_SRAM_MBUF_POOL_BASE5705
+ fw_len
);
6823 tw32(BUFMGR_MB_POOL_SIZE
,
6824 NIC_SRAM_MBUF_POOL_SIZE5705
- fw_len
- 0xa00);
6827 if (tp
->dev
->mtu
<= ETH_DATA_LEN
) {
6828 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
6829 tp
->bufmgr_config
.mbuf_read_dma_low_water
);
6830 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
6831 tp
->bufmgr_config
.mbuf_mac_rx_low_water
);
6832 tw32(BUFMGR_MB_HIGH_WATER
,
6833 tp
->bufmgr_config
.mbuf_high_water
);
6835 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
6836 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
);
6837 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
6838 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
);
6839 tw32(BUFMGR_MB_HIGH_WATER
,
6840 tp
->bufmgr_config
.mbuf_high_water_jumbo
);
6842 tw32(BUFMGR_DMA_LOW_WATER
,
6843 tp
->bufmgr_config
.dma_low_water
);
6844 tw32(BUFMGR_DMA_HIGH_WATER
,
6845 tp
->bufmgr_config
.dma_high_water
);
6847 tw32(BUFMGR_MODE
, BUFMGR_MODE_ENABLE
| BUFMGR_MODE_ATTN_ENABLE
);
6848 for (i
= 0; i
< 2000; i
++) {
6849 if (tr32(BUFMGR_MODE
) & BUFMGR_MODE_ENABLE
)
6854 printk(KERN_ERR PFX
"tg3_reset_hw cannot enable BUFMGR for %s.\n",
6859 /* Setup replenish threshold. */
6860 val
= tp
->rx_pending
/ 8;
6863 else if (val
> tp
->rx_std_max_post
)
6864 val
= tp
->rx_std_max_post
;
6865 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6866 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5906_A1
)
6867 tw32(ISO_PKT_TX
, (tr32(ISO_PKT_TX
) & ~0x3) | 0x2);
6869 if (val
> (TG3_RX_INTERNAL_RING_SZ_5906
/ 2))
6870 val
= TG3_RX_INTERNAL_RING_SZ_5906
/ 2;
6873 tw32(RCVBDI_STD_THRESH
, val
);
6875 /* Initialize TG3_BDINFO's at:
6876 * RCVDBDI_STD_BD: standard eth size rx ring
6877 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6878 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6881 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6882 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6883 * ring attribute flags
6884 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6886 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6887 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6889 * The size of each ring is fixed in the firmware, but the location is
6892 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
6893 ((u64
) tp
->rx_std_mapping
>> 32));
6894 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
6895 ((u64
) tp
->rx_std_mapping
& 0xffffffff));
6896 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_NIC_ADDR
,
6897 NIC_SRAM_RX_BUFFER_DESC
);
6899 /* Don't even try to program the JUMBO/MINI buffer descriptor
6902 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
6903 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
6904 RX_STD_MAX_SIZE_5705
<< BDINFO_FLAGS_MAXLEN_SHIFT
);
6906 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
6907 RX_STD_MAX_SIZE
<< BDINFO_FLAGS_MAXLEN_SHIFT
);
6909 tw32(RCVDBDI_MINI_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
6910 BDINFO_FLAGS_DISABLED
);
6912 /* Setup replenish threshold. */
6913 tw32(RCVBDI_JUMBO_THRESH
, tp
->rx_jumbo_pending
/ 8);
6915 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) {
6916 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
6917 ((u64
) tp
->rx_jumbo_mapping
>> 32));
6918 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
6919 ((u64
) tp
->rx_jumbo_mapping
& 0xffffffff));
6920 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
6921 RX_JUMBO_MAX_SIZE
<< BDINFO_FLAGS_MAXLEN_SHIFT
);
6922 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_NIC_ADDR
,
6923 NIC_SRAM_RX_JUMBO_BUFFER_DESC
);
6925 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
6926 BDINFO_FLAGS_DISABLED
);
6931 /* There is only one send ring on 5705/5750, no need to explicitly
6932 * disable the others.
6934 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
6935 /* Clear out send RCB ring in SRAM. */
6936 for (i
= NIC_SRAM_SEND_RCB
; i
< NIC_SRAM_RCV_RET_RCB
; i
+= TG3_BDINFO_SIZE
)
6937 tg3_write_mem(tp
, i
+ TG3_BDINFO_MAXLEN_FLAGS
,
6938 BDINFO_FLAGS_DISABLED
);
6943 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
, 0);
6944 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0
+ TG3_64BIT_REG_LOW
, 0);
6946 tg3_set_bdinfo(tp
, NIC_SRAM_SEND_RCB
,
6947 tp
->tx_desc_mapping
,
6948 (TG3_TX_RING_SIZE
<<
6949 BDINFO_FLAGS_MAXLEN_SHIFT
),
6950 NIC_SRAM_TX_BUFFER_DESC
);
6952 /* There is only one receive return ring on 5705/5750, no need
6953 * to explicitly disable the others.
6955 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
6956 for (i
= NIC_SRAM_RCV_RET_RCB
; i
< NIC_SRAM_STATS_BLK
;
6957 i
+= TG3_BDINFO_SIZE
) {
6958 tg3_write_mem(tp
, i
+ TG3_BDINFO_MAXLEN_FLAGS
,
6959 BDINFO_FLAGS_DISABLED
);
6964 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
, 0);
6966 tg3_set_bdinfo(tp
, NIC_SRAM_RCV_RET_RCB
,
6968 (TG3_RX_RCB_RING_SIZE(tp
) <<
6969 BDINFO_FLAGS_MAXLEN_SHIFT
),
6972 tp
->rx_std_ptr
= tp
->rx_pending
;
6973 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX
+ TG3_64BIT_REG_LOW
,
6976 tp
->rx_jumbo_ptr
= (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) ?
6977 tp
->rx_jumbo_pending
: 0;
6978 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX
+ TG3_64BIT_REG_LOW
,
6981 /* Initialize MAC address and backoff seed. */
6982 __tg3_set_mac_addr(tp
, 0);
6984 /* MTU + ethernet header + FCS + optional VLAN tag */
6985 tw32(MAC_RX_MTU_SIZE
,
6986 tp
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ VLAN_HLEN
);
6988 /* The slot time is changed by tg3_setup_phy if we
6989 * run at gigabit with half duplex.
6991 tw32(MAC_TX_LENGTHS
,
6992 (2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
6993 (6 << TX_LENGTHS_IPG_SHIFT
) |
6994 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
));
6996 /* Receive rules. */
6997 tw32(MAC_RCV_RULE_CFG
, RCV_RULE_CFG_DEFAULT_CLASS
);
6998 tw32(RCVLPC_CONFIG
, 0x0181);
7000 /* Calculate RDMAC_MODE setting early, we need it to determine
7001 * the RCVLPC_STATE_ENABLE mask.
7003 rdmac_mode
= (RDMAC_MODE_ENABLE
| RDMAC_MODE_TGTABORT_ENAB
|
7004 RDMAC_MODE_MSTABORT_ENAB
| RDMAC_MODE_PARITYERR_ENAB
|
7005 RDMAC_MODE_ADDROFLOW_ENAB
| RDMAC_MODE_FIFOOFLOW_ENAB
|
7006 RDMAC_MODE_FIFOURUN_ENAB
| RDMAC_MODE_FIFOOREAD_ENAB
|
7007 RDMAC_MODE_LNGREAD_ENAB
);
7009 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
7010 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
7011 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
7012 rdmac_mode
|= RDMAC_MODE_BD_SBD_CRPT_ENAB
|
7013 RDMAC_MODE_MBUF_RBD_CRPT_ENAB
|
7014 RDMAC_MODE_MBUF_SBD_CRPT_ENAB
;
7016 /* If statement applies to 5705 and 5750 PCI devices only */
7017 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
7018 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) ||
7019 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)) {
7020 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
&&
7021 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
7022 rdmac_mode
|= RDMAC_MODE_FIFO_SIZE_128
;
7023 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
7024 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
)) {
7025 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
7029 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
7030 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
7032 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
7033 rdmac_mode
|= RDMAC_MODE_IPV4_LSO_EN
;
7035 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
7036 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
7037 rdmac_mode
|= RDMAC_MODE_IPV6_LSO_EN
;
7039 /* Receive/send statistics. */
7040 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
7041 val
= tr32(RCVLPC_STATS_ENABLE
);
7042 val
&= ~RCVLPC_STATSENAB_DACK_FIX
;
7043 tw32(RCVLPC_STATS_ENABLE
, val
);
7044 } else if ((rdmac_mode
& RDMAC_MODE_FIFO_SIZE_128
) &&
7045 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
7046 val
= tr32(RCVLPC_STATS_ENABLE
);
7047 val
&= ~RCVLPC_STATSENAB_LNGBRST_RFIX
;
7048 tw32(RCVLPC_STATS_ENABLE
, val
);
7050 tw32(RCVLPC_STATS_ENABLE
, 0xffffff);
7052 tw32(RCVLPC_STATSCTRL
, RCVLPC_STATSCTRL_ENABLE
);
7053 tw32(SNDDATAI_STATSENAB
, 0xffffff);
7054 tw32(SNDDATAI_STATSCTRL
,
7055 (SNDDATAI_SCTRL_ENABLE
|
7056 SNDDATAI_SCTRL_FASTUPD
));
7058 /* Setup host coalescing engine. */
7059 tw32(HOSTCC_MODE
, 0);
7060 for (i
= 0; i
< 2000; i
++) {
7061 if (!(tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
))
7066 __tg3_set_coalesce(tp
, &tp
->coal
);
7068 /* set status block DMA address */
7069 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7070 ((u64
) tp
->status_mapping
>> 32));
7071 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7072 ((u64
) tp
->status_mapping
& 0xffffffff));
7074 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7075 /* Status/statistics block address. See tg3_timer,
7076 * the tg3_periodic_fetch_stats call there, and
7077 * tg3_get_stats to see how this works for 5705/5750 chips.
7079 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7080 ((u64
) tp
->stats_mapping
>> 32));
7081 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7082 ((u64
) tp
->stats_mapping
& 0xffffffff));
7083 tw32(HOSTCC_STATS_BLK_NIC_ADDR
, NIC_SRAM_STATS_BLK
);
7084 tw32(HOSTCC_STATUS_BLK_NIC_ADDR
, NIC_SRAM_STATUS_BLK
);
7087 tw32(HOSTCC_MODE
, HOSTCC_MODE_ENABLE
| tp
->coalesce_mode
);
7089 tw32(RCVCC_MODE
, RCVCC_MODE_ENABLE
| RCVCC_MODE_ATTN_ENABLE
);
7090 tw32(RCVLPC_MODE
, RCVLPC_MODE_ENABLE
);
7091 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7092 tw32(RCVLSC_MODE
, RCVLSC_MODE_ENABLE
| RCVLSC_MODE_ATTN_ENABLE
);
7094 /* Clear statistics/status block in chip, and status block in ram. */
7095 for (i
= NIC_SRAM_STATS_BLK
;
7096 i
< NIC_SRAM_STATUS_BLK
+ TG3_HW_STATUS_SIZE
;
7098 tg3_write_mem(tp
, i
, 0);
7101 memset(tp
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
7103 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
7104 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
7105 /* reset to prevent losing 1st rx packet intermittently */
7106 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
7110 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
7111 tp
->mac_mode
&= MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
7114 tp
->mac_mode
|= MAC_MODE_TXSTAT_ENABLE
| MAC_MODE_RXSTAT_ENABLE
|
7115 MAC_MODE_TDE_ENABLE
| MAC_MODE_RDE_ENABLE
| MAC_MODE_FHDE_ENABLE
;
7116 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
7117 !(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
7118 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
)
7119 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
7120 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_RXSTAT_CLEAR
| MAC_MODE_TXSTAT_CLEAR
);
7123 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7124 * If TG3_FLG2_IS_NIC is zero, we should read the
7125 * register to preserve the GPIO settings for LOMs. The GPIOs,
7126 * whether used as inputs or outputs, are set by boot code after
7129 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)) {
7132 gpio_mask
= GRC_LCLCTRL_GPIO_OE0
| GRC_LCLCTRL_GPIO_OE1
|
7133 GRC_LCLCTRL_GPIO_OE2
| GRC_LCLCTRL_GPIO_OUTPUT0
|
7134 GRC_LCLCTRL_GPIO_OUTPUT1
| GRC_LCLCTRL_GPIO_OUTPUT2
;
7136 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
7137 gpio_mask
|= GRC_LCLCTRL_GPIO_OE3
|
7138 GRC_LCLCTRL_GPIO_OUTPUT3
;
7140 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
7141 gpio_mask
|= GRC_LCLCTRL_GPIO_UART_SEL
;
7143 tp
->grc_local_ctrl
&= ~gpio_mask
;
7144 tp
->grc_local_ctrl
|= tr32(GRC_LOCAL_CTRL
) & gpio_mask
;
7146 /* GPIO1 must be driven high for eeprom write protect */
7147 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
)
7148 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
7149 GRC_LCLCTRL_GPIO_OUTPUT1
);
7151 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
7154 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0);
7156 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7157 tw32_f(DMAC_MODE
, DMAC_MODE_ENABLE
);
7161 val
= (WDMAC_MODE_ENABLE
| WDMAC_MODE_TGTABORT_ENAB
|
7162 WDMAC_MODE_MSTABORT_ENAB
| WDMAC_MODE_PARITYERR_ENAB
|
7163 WDMAC_MODE_ADDROFLOW_ENAB
| WDMAC_MODE_FIFOOFLOW_ENAB
|
7164 WDMAC_MODE_FIFOURUN_ENAB
| WDMAC_MODE_FIFOOREAD_ENAB
|
7165 WDMAC_MODE_LNGREAD_ENAB
);
7167 /* If statement applies to 5705 and 5750 PCI devices only */
7168 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
7169 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) ||
7170 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) {
7171 if ((tp
->tg3_flags
& TG3_FLG2_TSO_CAPABLE
) &&
7172 (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
||
7173 tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A2
)) {
7175 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
7176 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
7177 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
7178 val
|= WDMAC_MODE_RX_ACCEL
;
7182 /* Enable host coalescing bug fix */
7183 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
7184 val
|= WDMAC_MODE_STATUS_TAG_FIX
;
7186 tw32_f(WDMAC_MODE
, val
);
7189 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
7192 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
7194 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
) {
7195 pcix_cmd
&= ~PCI_X_CMD_MAX_READ
;
7196 pcix_cmd
|= PCI_X_CMD_READ_2K
;
7197 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
7198 pcix_cmd
&= ~(PCI_X_CMD_MAX_SPLIT
| PCI_X_CMD_MAX_READ
);
7199 pcix_cmd
|= PCI_X_CMD_READ_2K
;
7201 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
7205 tw32_f(RDMAC_MODE
, rdmac_mode
);
7208 tw32(RCVDCC_MODE
, RCVDCC_MODE_ENABLE
| RCVDCC_MODE_ATTN_ENABLE
);
7209 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7210 tw32(MBFREE_MODE
, MBFREE_MODE_ENABLE
);
7212 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
7214 SNDDATAC_MODE_ENABLE
| SNDDATAC_MODE_CDELAY
);
7216 tw32(SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
);
7218 tw32(SNDBDC_MODE
, SNDBDC_MODE_ENABLE
| SNDBDC_MODE_ATTN_ENABLE
);
7219 tw32(RCVBDI_MODE
, RCVBDI_MODE_ENABLE
| RCVBDI_MODE_RCB_ATTN_ENAB
);
7220 tw32(RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
| RCVDBDI_MODE_INV_RING_SZ
);
7221 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
);
7222 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
7223 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
| 0x8);
7224 tw32(SNDBDI_MODE
, SNDBDI_MODE_ENABLE
| SNDBDI_MODE_ATTN_ENABLE
);
7225 tw32(SNDBDS_MODE
, SNDBDS_MODE_ENABLE
| SNDBDS_MODE_ATTN_ENABLE
);
7227 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
7228 err
= tg3_load_5701_a0_firmware_fix(tp
);
7233 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
7234 err
= tg3_load_tso_firmware(tp
);
7239 tp
->tx_mode
= TX_MODE_ENABLE
;
7240 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
7243 tp
->rx_mode
= RX_MODE_ENABLE
;
7244 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
7245 tp
->rx_mode
|= RX_MODE_IPV6_CSUM_ENABLE
;
7247 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
7250 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
7252 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
7253 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
7254 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
7257 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
7260 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
7261 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) &&
7262 !(tp
->tg3_flags2
& TG3_FLG2_SERDES_PREEMPHASIS
)) {
7263 /* Set drive transmission level to 1.2V */
7264 /* only if the signal pre-emphasis bit is not set */
7265 val
= tr32(MAC_SERDES_CFG
);
7268 tw32(MAC_SERDES_CFG
, val
);
7270 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
)
7271 tw32(MAC_SERDES_CFG
, 0x616000);
7274 /* Prevent chip from dropping frames when flow control
7277 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME
, 2);
7279 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
&&
7280 (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
7281 /* Use hardware link auto-negotiation */
7282 tp
->tg3_flags2
|= TG3_FLG2_HW_AUTONEG
;
7285 if ((tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) &&
7286 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
)) {
7289 tmp
= tr32(SERDES_RX_CTRL
);
7290 tw32(SERDES_RX_CTRL
, tmp
| SERDES_RX_SIG_DETECT
);
7291 tp
->grc_local_ctrl
&= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT
;
7292 tp
->grc_local_ctrl
|= GRC_LCLCTRL_USE_SIG_DETECT
;
7293 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
7296 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)) {
7297 if (tp
->link_config
.phy_is_low_power
) {
7298 tp
->link_config
.phy_is_low_power
= 0;
7299 tp
->link_config
.speed
= tp
->link_config
.orig_speed
;
7300 tp
->link_config
.duplex
= tp
->link_config
.orig_duplex
;
7301 tp
->link_config
.autoneg
= tp
->link_config
.orig_autoneg
;
7304 err
= tg3_setup_phy(tp
, 0);
7308 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
7309 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5906
) {
7312 /* Clear CRC stats. */
7313 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &tmp
)) {
7314 tg3_writephy(tp
, MII_TG3_TEST1
,
7315 tmp
| MII_TG3_TEST1_CRC_EN
);
7316 tg3_readphy(tp
, 0x14, &tmp
);
7321 __tg3_set_rx_mode(tp
->dev
);
7323 /* Initialize receive rules. */
7324 tw32(MAC_RCV_RULE_0
, 0xc2000000 & RCV_RULE_DISABLE_MASK
);
7325 tw32(MAC_RCV_VALUE_0
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
7326 tw32(MAC_RCV_RULE_1
, 0x86000004 & RCV_RULE_DISABLE_MASK
);
7327 tw32(MAC_RCV_VALUE_1
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
7329 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
7330 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
7334 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)
7338 tw32(MAC_RCV_RULE_15
, 0); tw32(MAC_RCV_VALUE_15
, 0);
7340 tw32(MAC_RCV_RULE_14
, 0); tw32(MAC_RCV_VALUE_14
, 0);
7342 tw32(MAC_RCV_RULE_13
, 0); tw32(MAC_RCV_VALUE_13
, 0);
7344 tw32(MAC_RCV_RULE_12
, 0); tw32(MAC_RCV_VALUE_12
, 0);
7346 tw32(MAC_RCV_RULE_11
, 0); tw32(MAC_RCV_VALUE_11
, 0);
7348 tw32(MAC_RCV_RULE_10
, 0); tw32(MAC_RCV_VALUE_10
, 0);
7350 tw32(MAC_RCV_RULE_9
, 0); tw32(MAC_RCV_VALUE_9
, 0);
7352 tw32(MAC_RCV_RULE_8
, 0); tw32(MAC_RCV_VALUE_8
, 0);
7354 tw32(MAC_RCV_RULE_7
, 0); tw32(MAC_RCV_VALUE_7
, 0);
7356 tw32(MAC_RCV_RULE_6
, 0); tw32(MAC_RCV_VALUE_6
, 0);
7358 tw32(MAC_RCV_RULE_5
, 0); tw32(MAC_RCV_VALUE_5
, 0);
7360 tw32(MAC_RCV_RULE_4
, 0); tw32(MAC_RCV_VALUE_4
, 0);
7362 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7364 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7372 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
7373 /* Write our heartbeat update interval to APE. */
7374 tg3_ape_write32(tp
, TG3_APE_HOST_HEARTBEAT_INT_MS
,
7375 APE_HOST_HEARTBEAT_INT_DISABLE
);
7377 tg3_write_sig_post_reset(tp
, RESET_KIND_INIT
);
7382 /* Called at device open time to get the chip ready for
7383 * packet processing. Invoked with tp->lock held.
7385 static int tg3_init_hw(struct tg3
*tp
, int reset_phy
)
7387 tg3_switch_clocks(tp
);
7389 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
7391 return tg3_reset_hw(tp
, reset_phy
);
7394 #define TG3_STAT_ADD32(PSTAT, REG) \
7395 do { u32 __val = tr32(REG); \
7396 (PSTAT)->low += __val; \
7397 if ((PSTAT)->low < __val) \
7398 (PSTAT)->high += 1; \
7401 static void tg3_periodic_fetch_stats(struct tg3
*tp
)
7403 struct tg3_hw_stats
*sp
= tp
->hw_stats
;
7405 if (!netif_carrier_ok(tp
->dev
))
7408 TG3_STAT_ADD32(&sp
->tx_octets
, MAC_TX_STATS_OCTETS
);
7409 TG3_STAT_ADD32(&sp
->tx_collisions
, MAC_TX_STATS_COLLISIONS
);
7410 TG3_STAT_ADD32(&sp
->tx_xon_sent
, MAC_TX_STATS_XON_SENT
);
7411 TG3_STAT_ADD32(&sp
->tx_xoff_sent
, MAC_TX_STATS_XOFF_SENT
);
7412 TG3_STAT_ADD32(&sp
->tx_mac_errors
, MAC_TX_STATS_MAC_ERRORS
);
7413 TG3_STAT_ADD32(&sp
->tx_single_collisions
, MAC_TX_STATS_SINGLE_COLLISIONS
);
7414 TG3_STAT_ADD32(&sp
->tx_mult_collisions
, MAC_TX_STATS_MULT_COLLISIONS
);
7415 TG3_STAT_ADD32(&sp
->tx_deferred
, MAC_TX_STATS_DEFERRED
);
7416 TG3_STAT_ADD32(&sp
->tx_excessive_collisions
, MAC_TX_STATS_EXCESSIVE_COL
);
7417 TG3_STAT_ADD32(&sp
->tx_late_collisions
, MAC_TX_STATS_LATE_COL
);
7418 TG3_STAT_ADD32(&sp
->tx_ucast_packets
, MAC_TX_STATS_UCAST
);
7419 TG3_STAT_ADD32(&sp
->tx_mcast_packets
, MAC_TX_STATS_MCAST
);
7420 TG3_STAT_ADD32(&sp
->tx_bcast_packets
, MAC_TX_STATS_BCAST
);
7422 TG3_STAT_ADD32(&sp
->rx_octets
, MAC_RX_STATS_OCTETS
);
7423 TG3_STAT_ADD32(&sp
->rx_fragments
, MAC_RX_STATS_FRAGMENTS
);
7424 TG3_STAT_ADD32(&sp
->rx_ucast_packets
, MAC_RX_STATS_UCAST
);
7425 TG3_STAT_ADD32(&sp
->rx_mcast_packets
, MAC_RX_STATS_MCAST
);
7426 TG3_STAT_ADD32(&sp
->rx_bcast_packets
, MAC_RX_STATS_BCAST
);
7427 TG3_STAT_ADD32(&sp
->rx_fcs_errors
, MAC_RX_STATS_FCS_ERRORS
);
7428 TG3_STAT_ADD32(&sp
->rx_align_errors
, MAC_RX_STATS_ALIGN_ERRORS
);
7429 TG3_STAT_ADD32(&sp
->rx_xon_pause_rcvd
, MAC_RX_STATS_XON_PAUSE_RECVD
);
7430 TG3_STAT_ADD32(&sp
->rx_xoff_pause_rcvd
, MAC_RX_STATS_XOFF_PAUSE_RECVD
);
7431 TG3_STAT_ADD32(&sp
->rx_mac_ctrl_rcvd
, MAC_RX_STATS_MAC_CTRL_RECVD
);
7432 TG3_STAT_ADD32(&sp
->rx_xoff_entered
, MAC_RX_STATS_XOFF_ENTERED
);
7433 TG3_STAT_ADD32(&sp
->rx_frame_too_long_errors
, MAC_RX_STATS_FRAME_TOO_LONG
);
7434 TG3_STAT_ADD32(&sp
->rx_jabbers
, MAC_RX_STATS_JABBERS
);
7435 TG3_STAT_ADD32(&sp
->rx_undersize_packets
, MAC_RX_STATS_UNDERSIZE
);
7437 TG3_STAT_ADD32(&sp
->rxbds_empty
, RCVLPC_NO_RCV_BD_CNT
);
7438 TG3_STAT_ADD32(&sp
->rx_discards
, RCVLPC_IN_DISCARDS_CNT
);
7439 TG3_STAT_ADD32(&sp
->rx_errors
, RCVLPC_IN_ERRORS_CNT
);
7442 static void tg3_timer(unsigned long __opaque
)
7444 struct tg3
*tp
= (struct tg3
*) __opaque
;
7449 spin_lock(&tp
->lock
);
7451 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
7452 /* All of this garbage is because when using non-tagged
7453 * IRQ status the mailbox/status_block protocol the chip
7454 * uses with the cpu is race prone.
7456 if (tp
->hw_status
->status
& SD_STATUS_UPDATED
) {
7457 tw32(GRC_LOCAL_CTRL
,
7458 tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
7460 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
7461 (HOSTCC_MODE_ENABLE
| HOSTCC_MODE_NOW
));
7464 if (!(tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
7465 tp
->tg3_flags2
|= TG3_FLG2_RESTART_TIMER
;
7466 spin_unlock(&tp
->lock
);
7467 schedule_work(&tp
->reset_task
);
7472 /* This part only runs once per second. */
7473 if (!--tp
->timer_counter
) {
7474 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
7475 tg3_periodic_fetch_stats(tp
);
7477 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
7481 mac_stat
= tr32(MAC_STATUS
);
7484 if (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
) {
7485 if (mac_stat
& MAC_STATUS_MI_INTERRUPT
)
7487 } else if (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)
7491 tg3_setup_phy(tp
, 0);
7492 } else if (tp
->tg3_flags
& TG3_FLAG_POLL_SERDES
) {
7493 u32 mac_stat
= tr32(MAC_STATUS
);
7496 if (netif_carrier_ok(tp
->dev
) &&
7497 (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)) {
7500 if (! netif_carrier_ok(tp
->dev
) &&
7501 (mac_stat
& (MAC_STATUS_PCS_SYNCED
|
7502 MAC_STATUS_SIGNAL_DET
))) {
7506 if (!tp
->serdes_counter
) {
7509 ~MAC_MODE_PORT_MODE_MASK
));
7511 tw32_f(MAC_MODE
, tp
->mac_mode
);
7514 tg3_setup_phy(tp
, 0);
7516 } else if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)
7517 tg3_serdes_parallel_detect(tp
);
7519 tp
->timer_counter
= tp
->timer_multiplier
;
7522 /* Heartbeat is only sent once every 2 seconds.
7524 * The heartbeat is to tell the ASF firmware that the host
7525 * driver is still alive. In the event that the OS crashes,
7526 * ASF needs to reset the hardware to free up the FIFO space
7527 * that may be filled with rx packets destined for the host.
7528 * If the FIFO is full, ASF will no longer function properly.
7530 * Unintended resets have been reported on real time kernels
7531 * where the timer doesn't run on time. Netpoll will also have
7534 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7535 * to check the ring condition when the heartbeat is expiring
7536 * before doing the reset. This will prevent most unintended
7539 if (!--tp
->asf_counter
) {
7540 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
7541 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
7542 tg3_wait_for_event_ack(tp
);
7544 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
,
7545 FWCMD_NICDRV_ALIVE3
);
7546 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 4);
7547 /* 5 seconds timeout */
7548 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
, 5);
7550 tg3_generate_fw_event(tp
);
7552 tp
->asf_counter
= tp
->asf_multiplier
;
7555 spin_unlock(&tp
->lock
);
7558 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
7559 add_timer(&tp
->timer
);
7562 static int tg3_request_irq(struct tg3
*tp
)
7565 unsigned long flags
;
7566 struct net_device
*dev
= tp
->dev
;
7568 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
7570 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)
7572 flags
= IRQF_SAMPLE_RANDOM
;
7575 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
7576 fn
= tg3_interrupt_tagged
;
7577 flags
= IRQF_SHARED
| IRQF_SAMPLE_RANDOM
;
7579 return (request_irq(tp
->pdev
->irq
, fn
, flags
, dev
->name
, dev
));
7582 static int tg3_test_interrupt(struct tg3
*tp
)
7584 struct net_device
*dev
= tp
->dev
;
7585 int err
, i
, intr_ok
= 0;
7587 if (!netif_running(dev
))
7590 tg3_disable_ints(tp
);
7592 free_irq(tp
->pdev
->irq
, dev
);
7594 err
= request_irq(tp
->pdev
->irq
, tg3_test_isr
,
7595 IRQF_SHARED
| IRQF_SAMPLE_RANDOM
, dev
->name
, dev
);
7599 tp
->hw_status
->status
&= ~SD_STATUS_UPDATED
;
7600 tg3_enable_ints(tp
);
7602 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
7605 for (i
= 0; i
< 5; i
++) {
7606 u32 int_mbox
, misc_host_ctrl
;
7608 int_mbox
= tr32_mailbox(MAILBOX_INTERRUPT_0
+
7610 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
7612 if ((int_mbox
!= 0) ||
7613 (misc_host_ctrl
& MISC_HOST_CTRL_MASK_PCI_INT
)) {
7621 tg3_disable_ints(tp
);
7623 free_irq(tp
->pdev
->irq
, dev
);
7625 err
= tg3_request_irq(tp
);
7636 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7637 * successfully restored
7639 static int tg3_test_msi(struct tg3
*tp
)
7641 struct net_device
*dev
= tp
->dev
;
7645 if (!(tp
->tg3_flags2
& TG3_FLG2_USING_MSI
))
7648 /* Turn off SERR reporting in case MSI terminates with Master
7651 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
7652 pci_write_config_word(tp
->pdev
, PCI_COMMAND
,
7653 pci_cmd
& ~PCI_COMMAND_SERR
);
7655 err
= tg3_test_interrupt(tp
);
7657 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
7662 /* other failures */
7666 /* MSI test failed, go back to INTx mode */
7667 printk(KERN_WARNING PFX
"%s: No interrupt was generated using MSI, "
7668 "switching to INTx mode. Please report this failure to "
7669 "the PCI maintainer and include system chipset information.\n",
7672 free_irq(tp
->pdev
->irq
, dev
);
7673 pci_disable_msi(tp
->pdev
);
7675 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
7677 err
= tg3_request_irq(tp
);
7681 /* Need to reset the chip because the MSI cycle may have terminated
7682 * with Master Abort.
7684 tg3_full_lock(tp
, 1);
7686 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
7687 err
= tg3_init_hw(tp
, 1);
7689 tg3_full_unlock(tp
);
7692 free_irq(tp
->pdev
->irq
, dev
);
7697 static int tg3_request_firmware(struct tg3
*tp
)
7699 const __be32
*fw_data
;
7701 if (request_firmware(&tp
->fw
, tp
->fw_needed
, &tp
->pdev
->dev
)) {
7702 printk(KERN_ERR
"%s: Failed to load firmware \"%s\"\n",
7703 tp
->dev
->name
, tp
->fw_needed
);
7707 fw_data
= (void *)tp
->fw
->data
;
7709 /* Firmware blob starts with version numbers, followed by
7710 * start address and _full_ length including BSS sections
7711 * (which must be longer than the actual data, of course
7714 tp
->fw_len
= be32_to_cpu(fw_data
[2]); /* includes bss */
7715 if (tp
->fw_len
< (tp
->fw
->size
- 12)) {
7716 printk(KERN_ERR
"%s: bogus length %d in \"%s\"\n",
7717 tp
->dev
->name
, tp
->fw_len
, tp
->fw_needed
);
7718 release_firmware(tp
->fw
);
7723 /* We no longer need firmware; we have it. */
7724 tp
->fw_needed
= NULL
;
7728 static int tg3_open(struct net_device
*dev
)
7730 struct tg3
*tp
= netdev_priv(dev
);
7733 if (tp
->fw_needed
) {
7734 err
= tg3_request_firmware(tp
);
7735 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
7739 printk(KERN_WARNING
"%s: TSO capability disabled.\n",
7741 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
7742 } else if (!(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
7743 printk(KERN_NOTICE
"%s: TSO capability restored.\n",
7745 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
7749 netif_carrier_off(tp
->dev
);
7751 err
= tg3_set_power_state(tp
, PCI_D0
);
7755 tg3_full_lock(tp
, 0);
7757 tg3_disable_ints(tp
);
7758 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
7760 tg3_full_unlock(tp
);
7762 /* The placement of this call is tied
7763 * to the setup and use of Host TX descriptors.
7765 err
= tg3_alloc_consistent(tp
);
7769 if (tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSI
) {
7770 /* All MSI supporting chips should support tagged
7771 * status. Assert that this is the case.
7773 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
7774 printk(KERN_WARNING PFX
"%s: MSI without TAGGED? "
7775 "Not using MSI.\n", tp
->dev
->name
);
7776 } else if (pci_enable_msi(tp
->pdev
) == 0) {
7779 msi_mode
= tr32(MSGINT_MODE
);
7780 tw32(MSGINT_MODE
, msi_mode
| MSGINT_MODE_ENABLE
);
7781 tp
->tg3_flags2
|= TG3_FLG2_USING_MSI
;
7784 err
= tg3_request_irq(tp
);
7787 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
7788 pci_disable_msi(tp
->pdev
);
7789 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
7791 tg3_free_consistent(tp
);
7795 napi_enable(&tp
->napi
);
7797 tg3_full_lock(tp
, 0);
7799 err
= tg3_init_hw(tp
, 1);
7801 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
7804 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
7805 tp
->timer_offset
= HZ
;
7807 tp
->timer_offset
= HZ
/ 10;
7809 BUG_ON(tp
->timer_offset
> HZ
);
7810 tp
->timer_counter
= tp
->timer_multiplier
=
7811 (HZ
/ tp
->timer_offset
);
7812 tp
->asf_counter
= tp
->asf_multiplier
=
7813 ((HZ
/ tp
->timer_offset
) * 2);
7815 init_timer(&tp
->timer
);
7816 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
7817 tp
->timer
.data
= (unsigned long) tp
;
7818 tp
->timer
.function
= tg3_timer
;
7821 tg3_full_unlock(tp
);
7824 napi_disable(&tp
->napi
);
7825 free_irq(tp
->pdev
->irq
, dev
);
7826 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
7827 pci_disable_msi(tp
->pdev
);
7828 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
7830 tg3_free_consistent(tp
);
7834 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
7835 err
= tg3_test_msi(tp
);
7838 tg3_full_lock(tp
, 0);
7840 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
7841 pci_disable_msi(tp
->pdev
);
7842 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
7844 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
7846 tg3_free_consistent(tp
);
7848 tg3_full_unlock(tp
);
7850 napi_disable(&tp
->napi
);
7855 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
7856 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
) {
7857 u32 val
= tr32(PCIE_TRANSACTION_CFG
);
7859 tw32(PCIE_TRANSACTION_CFG
,
7860 val
| PCIE_TRANS_CFG_1SHOT_MSI
);
7867 tg3_full_lock(tp
, 0);
7869 add_timer(&tp
->timer
);
7870 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
7871 tg3_enable_ints(tp
);
7873 tg3_full_unlock(tp
);
7875 netif_start_queue(dev
);
7881 /*static*/ void tg3_dump_state(struct tg3
*tp
)
7883 u32 val32
, val32_2
, val32_3
, val32_4
, val32_5
;
7887 pci_read_config_word(tp
->pdev
, PCI_STATUS
, &val16
);
7888 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, &val32
);
7889 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7893 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7894 tr32(MAC_MODE
), tr32(MAC_STATUS
));
7895 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7896 tr32(MAC_EVENT
), tr32(MAC_LED_CTRL
));
7897 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7898 tr32(MAC_TX_MODE
), tr32(MAC_TX_STATUS
));
7899 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7900 tr32(MAC_RX_MODE
), tr32(MAC_RX_STATUS
));
7902 /* Send data initiator control block */
7903 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7904 tr32(SNDDATAI_MODE
), tr32(SNDDATAI_STATUS
));
7905 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7906 tr32(SNDDATAI_STATSCTRL
));
7908 /* Send data completion control block */
7909 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE
));
7911 /* Send BD ring selector block */
7912 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7913 tr32(SNDBDS_MODE
), tr32(SNDBDS_STATUS
));
7915 /* Send BD initiator control block */
7916 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7917 tr32(SNDBDI_MODE
), tr32(SNDBDI_STATUS
));
7919 /* Send BD completion control block */
7920 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE
));
7922 /* Receive list placement control block */
7923 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7924 tr32(RCVLPC_MODE
), tr32(RCVLPC_STATUS
));
7925 printk(" RCVLPC_STATSCTRL[%08x]\n",
7926 tr32(RCVLPC_STATSCTRL
));
7928 /* Receive data and receive BD initiator control block */
7929 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7930 tr32(RCVDBDI_MODE
), tr32(RCVDBDI_STATUS
));
7932 /* Receive data completion control block */
7933 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7936 /* Receive BD initiator control block */
7937 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7938 tr32(RCVBDI_MODE
), tr32(RCVBDI_STATUS
));
7940 /* Receive BD completion control block */
7941 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7942 tr32(RCVCC_MODE
), tr32(RCVCC_STATUS
));
7944 /* Receive list selector control block */
7945 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7946 tr32(RCVLSC_MODE
), tr32(RCVLSC_STATUS
));
7948 /* Mbuf cluster free block */
7949 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7950 tr32(MBFREE_MODE
), tr32(MBFREE_STATUS
));
7952 /* Host coalescing control block */
7953 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7954 tr32(HOSTCC_MODE
), tr32(HOSTCC_STATUS
));
7955 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7956 tr32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
7957 tr32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
));
7958 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7959 tr32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
7960 tr32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
));
7961 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7962 tr32(HOSTCC_STATS_BLK_NIC_ADDR
));
7963 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7964 tr32(HOSTCC_STATUS_BLK_NIC_ADDR
));
7966 /* Memory arbiter control block */
7967 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7968 tr32(MEMARB_MODE
), tr32(MEMARB_STATUS
));
7970 /* Buffer manager control block */
7971 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7972 tr32(BUFMGR_MODE
), tr32(BUFMGR_STATUS
));
7973 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7974 tr32(BUFMGR_MB_POOL_ADDR
), tr32(BUFMGR_MB_POOL_SIZE
));
7975 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7976 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7977 tr32(BUFMGR_DMA_DESC_POOL_ADDR
),
7978 tr32(BUFMGR_DMA_DESC_POOL_SIZE
));
7980 /* Read DMA control block */
7981 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7982 tr32(RDMAC_MODE
), tr32(RDMAC_STATUS
));
7984 /* Write DMA control block */
7985 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7986 tr32(WDMAC_MODE
), tr32(WDMAC_STATUS
));
7988 /* DMA completion block */
7989 printk("DEBUG: DMAC_MODE[%08x]\n",
7993 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7994 tr32(GRC_MODE
), tr32(GRC_MISC_CFG
));
7995 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7996 tr32(GRC_LOCAL_CTRL
));
7999 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8000 tr32(RCVDBDI_JUMBO_BD
+ 0x0),
8001 tr32(RCVDBDI_JUMBO_BD
+ 0x4),
8002 tr32(RCVDBDI_JUMBO_BD
+ 0x8),
8003 tr32(RCVDBDI_JUMBO_BD
+ 0xc));
8004 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8005 tr32(RCVDBDI_STD_BD
+ 0x0),
8006 tr32(RCVDBDI_STD_BD
+ 0x4),
8007 tr32(RCVDBDI_STD_BD
+ 0x8),
8008 tr32(RCVDBDI_STD_BD
+ 0xc));
8009 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8010 tr32(RCVDBDI_MINI_BD
+ 0x0),
8011 tr32(RCVDBDI_MINI_BD
+ 0x4),
8012 tr32(RCVDBDI_MINI_BD
+ 0x8),
8013 tr32(RCVDBDI_MINI_BD
+ 0xc));
8015 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0x0, &val32
);
8016 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0x4, &val32_2
);
8017 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0x8, &val32_3
);
8018 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0xc, &val32_4
);
8019 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8020 val32
, val32_2
, val32_3
, val32_4
);
8022 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0x0, &val32
);
8023 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0x4, &val32_2
);
8024 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0x8, &val32_3
);
8025 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0xc, &val32_4
);
8026 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8027 val32
, val32_2
, val32_3
, val32_4
);
8029 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x0, &val32
);
8030 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x4, &val32_2
);
8031 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x8, &val32_3
);
8032 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0xc, &val32_4
);
8033 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x10, &val32_5
);
8034 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8035 val32
, val32_2
, val32_3
, val32_4
, val32_5
);
8037 /* SW status block */
8038 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8039 tp
->hw_status
->status
,
8040 tp
->hw_status
->status_tag
,
8041 tp
->hw_status
->rx_jumbo_consumer
,
8042 tp
->hw_status
->rx_consumer
,
8043 tp
->hw_status
->rx_mini_consumer
,
8044 tp
->hw_status
->idx
[0].rx_producer
,
8045 tp
->hw_status
->idx
[0].tx_consumer
);
8047 /* SW statistics block */
8048 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8049 ((u32
*)tp
->hw_stats
)[0],
8050 ((u32
*)tp
->hw_stats
)[1],
8051 ((u32
*)tp
->hw_stats
)[2],
8052 ((u32
*)tp
->hw_stats
)[3]);
8055 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8056 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0
+ 0x0),
8057 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0
+ 0x4),
8058 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0
+ 0x0),
8059 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0
+ 0x4));
8061 /* NIC side send descriptors. */
8062 for (i
= 0; i
< 6; i
++) {
8065 txd
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_TX_BUFFER_DESC
8066 + (i
* sizeof(struct tg3_tx_buffer_desc
));
8067 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8069 readl(txd
+ 0x0), readl(txd
+ 0x4),
8070 readl(txd
+ 0x8), readl(txd
+ 0xc));
8073 /* NIC side RX descriptors. */
8074 for (i
= 0; i
< 6; i
++) {
8077 rxd
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_RX_BUFFER_DESC
8078 + (i
* sizeof(struct tg3_rx_buffer_desc
));
8079 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8081 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
8082 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
8083 rxd
+= (4 * sizeof(u32
));
8084 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8086 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
8087 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
8090 for (i
= 0; i
< 6; i
++) {
8093 rxd
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_RX_JUMBO_BUFFER_DESC
8094 + (i
* sizeof(struct tg3_rx_buffer_desc
));
8095 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8097 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
8098 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
8099 rxd
+= (4 * sizeof(u32
));
8100 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8102 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
8103 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
8108 static struct net_device_stats
*tg3_get_stats(struct net_device
*);
8109 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*);
8111 static int tg3_close(struct net_device
*dev
)
8113 struct tg3
*tp
= netdev_priv(dev
);
8115 napi_disable(&tp
->napi
);
8116 cancel_work_sync(&tp
->reset_task
);
8118 netif_stop_queue(dev
);
8120 del_timer_sync(&tp
->timer
);
8122 tg3_full_lock(tp
, 1);
8127 tg3_disable_ints(tp
);
8129 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8131 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
8133 tg3_full_unlock(tp
);
8135 free_irq(tp
->pdev
->irq
, dev
);
8136 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
8137 pci_disable_msi(tp
->pdev
);
8138 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
8141 memcpy(&tp
->net_stats_prev
, tg3_get_stats(tp
->dev
),
8142 sizeof(tp
->net_stats_prev
));
8143 memcpy(&tp
->estats_prev
, tg3_get_estats(tp
),
8144 sizeof(tp
->estats_prev
));
8146 tg3_free_consistent(tp
);
8148 tg3_set_power_state(tp
, PCI_D3hot
);
8150 netif_carrier_off(tp
->dev
);
8155 static inline unsigned long get_stat64(tg3_stat64_t
*val
)
8159 #if (BITS_PER_LONG == 32)
8162 ret
= ((u64
)val
->high
<< 32) | ((u64
)val
->low
);
8167 static inline u64
get_estat64(tg3_stat64_t
*val
)
8169 return ((u64
)val
->high
<< 32) | ((u64
)val
->low
);
8172 static unsigned long calc_crc_errors(struct tg3
*tp
)
8174 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
8176 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
8177 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
8178 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
8181 spin_lock_bh(&tp
->lock
);
8182 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &val
)) {
8183 tg3_writephy(tp
, MII_TG3_TEST1
,
8184 val
| MII_TG3_TEST1_CRC_EN
);
8185 tg3_readphy(tp
, 0x14, &val
);
8188 spin_unlock_bh(&tp
->lock
);
8190 tp
->phy_crc_errors
+= val
;
8192 return tp
->phy_crc_errors
;
8195 return get_stat64(&hw_stats
->rx_fcs_errors
);
8198 #define ESTAT_ADD(member) \
8199 estats->member = old_estats->member + \
8200 get_estat64(&hw_stats->member)
8202 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*tp
)
8204 struct tg3_ethtool_stats
*estats
= &tp
->estats
;
8205 struct tg3_ethtool_stats
*old_estats
= &tp
->estats_prev
;
8206 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
8211 ESTAT_ADD(rx_octets
);
8212 ESTAT_ADD(rx_fragments
);
8213 ESTAT_ADD(rx_ucast_packets
);
8214 ESTAT_ADD(rx_mcast_packets
);
8215 ESTAT_ADD(rx_bcast_packets
);
8216 ESTAT_ADD(rx_fcs_errors
);
8217 ESTAT_ADD(rx_align_errors
);
8218 ESTAT_ADD(rx_xon_pause_rcvd
);
8219 ESTAT_ADD(rx_xoff_pause_rcvd
);
8220 ESTAT_ADD(rx_mac_ctrl_rcvd
);
8221 ESTAT_ADD(rx_xoff_entered
);
8222 ESTAT_ADD(rx_frame_too_long_errors
);
8223 ESTAT_ADD(rx_jabbers
);
8224 ESTAT_ADD(rx_undersize_packets
);
8225 ESTAT_ADD(rx_in_length_errors
);
8226 ESTAT_ADD(rx_out_length_errors
);
8227 ESTAT_ADD(rx_64_or_less_octet_packets
);
8228 ESTAT_ADD(rx_65_to_127_octet_packets
);
8229 ESTAT_ADD(rx_128_to_255_octet_packets
);
8230 ESTAT_ADD(rx_256_to_511_octet_packets
);
8231 ESTAT_ADD(rx_512_to_1023_octet_packets
);
8232 ESTAT_ADD(rx_1024_to_1522_octet_packets
);
8233 ESTAT_ADD(rx_1523_to_2047_octet_packets
);
8234 ESTAT_ADD(rx_2048_to_4095_octet_packets
);
8235 ESTAT_ADD(rx_4096_to_8191_octet_packets
);
8236 ESTAT_ADD(rx_8192_to_9022_octet_packets
);
8238 ESTAT_ADD(tx_octets
);
8239 ESTAT_ADD(tx_collisions
);
8240 ESTAT_ADD(tx_xon_sent
);
8241 ESTAT_ADD(tx_xoff_sent
);
8242 ESTAT_ADD(tx_flow_control
);
8243 ESTAT_ADD(tx_mac_errors
);
8244 ESTAT_ADD(tx_single_collisions
);
8245 ESTAT_ADD(tx_mult_collisions
);
8246 ESTAT_ADD(tx_deferred
);
8247 ESTAT_ADD(tx_excessive_collisions
);
8248 ESTAT_ADD(tx_late_collisions
);
8249 ESTAT_ADD(tx_collide_2times
);
8250 ESTAT_ADD(tx_collide_3times
);
8251 ESTAT_ADD(tx_collide_4times
);
8252 ESTAT_ADD(tx_collide_5times
);
8253 ESTAT_ADD(tx_collide_6times
);
8254 ESTAT_ADD(tx_collide_7times
);
8255 ESTAT_ADD(tx_collide_8times
);
8256 ESTAT_ADD(tx_collide_9times
);
8257 ESTAT_ADD(tx_collide_10times
);
8258 ESTAT_ADD(tx_collide_11times
);
8259 ESTAT_ADD(tx_collide_12times
);
8260 ESTAT_ADD(tx_collide_13times
);
8261 ESTAT_ADD(tx_collide_14times
);
8262 ESTAT_ADD(tx_collide_15times
);
8263 ESTAT_ADD(tx_ucast_packets
);
8264 ESTAT_ADD(tx_mcast_packets
);
8265 ESTAT_ADD(tx_bcast_packets
);
8266 ESTAT_ADD(tx_carrier_sense_errors
);
8267 ESTAT_ADD(tx_discards
);
8268 ESTAT_ADD(tx_errors
);
8270 ESTAT_ADD(dma_writeq_full
);
8271 ESTAT_ADD(dma_write_prioq_full
);
8272 ESTAT_ADD(rxbds_empty
);
8273 ESTAT_ADD(rx_discards
);
8274 ESTAT_ADD(rx_errors
);
8275 ESTAT_ADD(rx_threshold_hit
);
8277 ESTAT_ADD(dma_readq_full
);
8278 ESTAT_ADD(dma_read_prioq_full
);
8279 ESTAT_ADD(tx_comp_queue_full
);
8281 ESTAT_ADD(ring_set_send_prod_index
);
8282 ESTAT_ADD(ring_status_update
);
8283 ESTAT_ADD(nic_irqs
);
8284 ESTAT_ADD(nic_avoided_irqs
);
8285 ESTAT_ADD(nic_tx_threshold_hit
);
8290 static struct net_device_stats
*tg3_get_stats(struct net_device
*dev
)
8292 struct tg3
*tp
= netdev_priv(dev
);
8293 struct net_device_stats
*stats
= &tp
->net_stats
;
8294 struct net_device_stats
*old_stats
= &tp
->net_stats_prev
;
8295 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
8300 stats
->rx_packets
= old_stats
->rx_packets
+
8301 get_stat64(&hw_stats
->rx_ucast_packets
) +
8302 get_stat64(&hw_stats
->rx_mcast_packets
) +
8303 get_stat64(&hw_stats
->rx_bcast_packets
);
8305 stats
->tx_packets
= old_stats
->tx_packets
+
8306 get_stat64(&hw_stats
->tx_ucast_packets
) +
8307 get_stat64(&hw_stats
->tx_mcast_packets
) +
8308 get_stat64(&hw_stats
->tx_bcast_packets
);
8310 stats
->rx_bytes
= old_stats
->rx_bytes
+
8311 get_stat64(&hw_stats
->rx_octets
);
8312 stats
->tx_bytes
= old_stats
->tx_bytes
+
8313 get_stat64(&hw_stats
->tx_octets
);
8315 stats
->rx_errors
= old_stats
->rx_errors
+
8316 get_stat64(&hw_stats
->rx_errors
);
8317 stats
->tx_errors
= old_stats
->tx_errors
+
8318 get_stat64(&hw_stats
->tx_errors
) +
8319 get_stat64(&hw_stats
->tx_mac_errors
) +
8320 get_stat64(&hw_stats
->tx_carrier_sense_errors
) +
8321 get_stat64(&hw_stats
->tx_discards
);
8323 stats
->multicast
= old_stats
->multicast
+
8324 get_stat64(&hw_stats
->rx_mcast_packets
);
8325 stats
->collisions
= old_stats
->collisions
+
8326 get_stat64(&hw_stats
->tx_collisions
);
8328 stats
->rx_length_errors
= old_stats
->rx_length_errors
+
8329 get_stat64(&hw_stats
->rx_frame_too_long_errors
) +
8330 get_stat64(&hw_stats
->rx_undersize_packets
);
8332 stats
->rx_over_errors
= old_stats
->rx_over_errors
+
8333 get_stat64(&hw_stats
->rxbds_empty
);
8334 stats
->rx_frame_errors
= old_stats
->rx_frame_errors
+
8335 get_stat64(&hw_stats
->rx_align_errors
);
8336 stats
->tx_aborted_errors
= old_stats
->tx_aborted_errors
+
8337 get_stat64(&hw_stats
->tx_discards
);
8338 stats
->tx_carrier_errors
= old_stats
->tx_carrier_errors
+
8339 get_stat64(&hw_stats
->tx_carrier_sense_errors
);
8341 stats
->rx_crc_errors
= old_stats
->rx_crc_errors
+
8342 calc_crc_errors(tp
);
8344 stats
->rx_missed_errors
= old_stats
->rx_missed_errors
+
8345 get_stat64(&hw_stats
->rx_discards
);
8350 static inline u32
calc_crc(unsigned char *buf
, int len
)
8358 for (j
= 0; j
< len
; j
++) {
8361 for (k
= 0; k
< 8; k
++) {
8375 static void tg3_set_multi(struct tg3
*tp
, unsigned int accept_all
)
8377 /* accept or reject all multicast frames */
8378 tw32(MAC_HASH_REG_0
, accept_all
? 0xffffffff : 0);
8379 tw32(MAC_HASH_REG_1
, accept_all
? 0xffffffff : 0);
8380 tw32(MAC_HASH_REG_2
, accept_all
? 0xffffffff : 0);
8381 tw32(MAC_HASH_REG_3
, accept_all
? 0xffffffff : 0);
8384 static void __tg3_set_rx_mode(struct net_device
*dev
)
8386 struct tg3
*tp
= netdev_priv(dev
);
8389 rx_mode
= tp
->rx_mode
& ~(RX_MODE_PROMISC
|
8390 RX_MODE_KEEP_VLAN_TAG
);
8392 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8395 #if TG3_VLAN_TAG_USED
8397 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
8398 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
8400 /* By definition, VLAN is disabled always in this
8403 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
8404 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
8407 if (dev
->flags
& IFF_PROMISC
) {
8408 /* Promiscuous mode. */
8409 rx_mode
|= RX_MODE_PROMISC
;
8410 } else if (dev
->flags
& IFF_ALLMULTI
) {
8411 /* Accept all multicast. */
8412 tg3_set_multi (tp
, 1);
8413 } else if (dev
->mc_count
< 1) {
8414 /* Reject all multicast. */
8415 tg3_set_multi (tp
, 0);
8417 /* Accept one or more multicast(s). */
8418 struct dev_mc_list
*mclist
;
8420 u32 mc_filter
[4] = { 0, };
8425 for (i
= 0, mclist
= dev
->mc_list
; mclist
&& i
< dev
->mc_count
;
8426 i
++, mclist
= mclist
->next
) {
8428 crc
= calc_crc (mclist
->dmi_addr
, ETH_ALEN
);
8430 regidx
= (bit
& 0x60) >> 5;
8432 mc_filter
[regidx
] |= (1 << bit
);
8435 tw32(MAC_HASH_REG_0
, mc_filter
[0]);
8436 tw32(MAC_HASH_REG_1
, mc_filter
[1]);
8437 tw32(MAC_HASH_REG_2
, mc_filter
[2]);
8438 tw32(MAC_HASH_REG_3
, mc_filter
[3]);
8441 if (rx_mode
!= tp
->rx_mode
) {
8442 tp
->rx_mode
= rx_mode
;
8443 tw32_f(MAC_RX_MODE
, rx_mode
);
8448 static void tg3_set_rx_mode(struct net_device
*dev
)
8450 struct tg3
*tp
= netdev_priv(dev
);
8452 if (!netif_running(dev
))
8455 tg3_full_lock(tp
, 0);
8456 __tg3_set_rx_mode(dev
);
8457 tg3_full_unlock(tp
);
8460 #define TG3_REGDUMP_LEN (32 * 1024)
8462 static int tg3_get_regs_len(struct net_device
*dev
)
8464 return TG3_REGDUMP_LEN
;
8467 static void tg3_get_regs(struct net_device
*dev
,
8468 struct ethtool_regs
*regs
, void *_p
)
8471 struct tg3
*tp
= netdev_priv(dev
);
8477 memset(p
, 0, TG3_REGDUMP_LEN
);
8479 if (tp
->link_config
.phy_is_low_power
)
8482 tg3_full_lock(tp
, 0);
8484 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
8485 #define GET_REG32_LOOP(base,len) \
8486 do { p = (u32 *)(orig_p + (base)); \
8487 for (i = 0; i < len; i += 4) \
8488 __GET_REG32((base) + i); \
8490 #define GET_REG32_1(reg) \
8491 do { p = (u32 *)(orig_p + (reg)); \
8492 __GET_REG32((reg)); \
8495 GET_REG32_LOOP(TG3PCI_VENDOR
, 0xb0);
8496 GET_REG32_LOOP(MAILBOX_INTERRUPT_0
, 0x200);
8497 GET_REG32_LOOP(MAC_MODE
, 0x4f0);
8498 GET_REG32_LOOP(SNDDATAI_MODE
, 0xe0);
8499 GET_REG32_1(SNDDATAC_MODE
);
8500 GET_REG32_LOOP(SNDBDS_MODE
, 0x80);
8501 GET_REG32_LOOP(SNDBDI_MODE
, 0x48);
8502 GET_REG32_1(SNDBDC_MODE
);
8503 GET_REG32_LOOP(RCVLPC_MODE
, 0x20);
8504 GET_REG32_LOOP(RCVLPC_SELLST_BASE
, 0x15c);
8505 GET_REG32_LOOP(RCVDBDI_MODE
, 0x0c);
8506 GET_REG32_LOOP(RCVDBDI_JUMBO_BD
, 0x3c);
8507 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0
, 0x44);
8508 GET_REG32_1(RCVDCC_MODE
);
8509 GET_REG32_LOOP(RCVBDI_MODE
, 0x20);
8510 GET_REG32_LOOP(RCVCC_MODE
, 0x14);
8511 GET_REG32_LOOP(RCVLSC_MODE
, 0x08);
8512 GET_REG32_1(MBFREE_MODE
);
8513 GET_REG32_LOOP(HOSTCC_MODE
, 0x100);
8514 GET_REG32_LOOP(MEMARB_MODE
, 0x10);
8515 GET_REG32_LOOP(BUFMGR_MODE
, 0x58);
8516 GET_REG32_LOOP(RDMAC_MODE
, 0x08);
8517 GET_REG32_LOOP(WDMAC_MODE
, 0x08);
8518 GET_REG32_1(RX_CPU_MODE
);
8519 GET_REG32_1(RX_CPU_STATE
);
8520 GET_REG32_1(RX_CPU_PGMCTR
);
8521 GET_REG32_1(RX_CPU_HWBKPT
);
8522 GET_REG32_1(TX_CPU_MODE
);
8523 GET_REG32_1(TX_CPU_STATE
);
8524 GET_REG32_1(TX_CPU_PGMCTR
);
8525 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0
, 0x110);
8526 GET_REG32_LOOP(FTQ_RESET
, 0x120);
8527 GET_REG32_LOOP(MSGINT_MODE
, 0x0c);
8528 GET_REG32_1(DMAC_MODE
);
8529 GET_REG32_LOOP(GRC_MODE
, 0x4c);
8530 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
8531 GET_REG32_LOOP(NVRAM_CMD
, 0x24);
8534 #undef GET_REG32_LOOP
8537 tg3_full_unlock(tp
);
8540 static int tg3_get_eeprom_len(struct net_device
*dev
)
8542 struct tg3
*tp
= netdev_priv(dev
);
8544 return tp
->nvram_size
;
8547 static int tg3_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
8549 struct tg3
*tp
= netdev_priv(dev
);
8552 u32 i
, offset
, len
, b_offset
, b_count
;
8555 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
)
8558 if (tp
->link_config
.phy_is_low_power
)
8561 offset
= eeprom
->offset
;
8565 eeprom
->magic
= TG3_EEPROM_MAGIC
;
8568 /* adjustments to start on required 4 byte boundary */
8569 b_offset
= offset
& 3;
8570 b_count
= 4 - b_offset
;
8571 if (b_count
> len
) {
8572 /* i.e. offset=1 len=2 */
8575 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &val
);
8578 memcpy(data
, ((char*)&val
) + b_offset
, b_count
);
8581 eeprom
->len
+= b_count
;
8584 /* read bytes upto the last 4 byte boundary */
8585 pd
= &data
[eeprom
->len
];
8586 for (i
= 0; i
< (len
- (len
& 3)); i
+= 4) {
8587 ret
= tg3_nvram_read_be32(tp
, offset
+ i
, &val
);
8592 memcpy(pd
+ i
, &val
, 4);
8597 /* read last bytes not ending on 4 byte boundary */
8598 pd
= &data
[eeprom
->len
];
8600 b_offset
= offset
+ len
- b_count
;
8601 ret
= tg3_nvram_read_be32(tp
, b_offset
, &val
);
8604 memcpy(pd
, &val
, b_count
);
8605 eeprom
->len
+= b_count
;
8610 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
);
8612 static int tg3_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
8614 struct tg3
*tp
= netdev_priv(dev
);
8616 u32 offset
, len
, b_offset
, odd_len
;
8620 if (tp
->link_config
.phy_is_low_power
)
8623 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
8624 eeprom
->magic
!= TG3_EEPROM_MAGIC
)
8627 offset
= eeprom
->offset
;
8630 if ((b_offset
= (offset
& 3))) {
8631 /* adjustments to start on required 4 byte boundary */
8632 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &start
);
8643 /* adjustments to end on required 4 byte boundary */
8645 len
= (len
+ 3) & ~3;
8646 ret
= tg3_nvram_read_be32(tp
, offset
+len
-4, &end
);
8652 if (b_offset
|| odd_len
) {
8653 buf
= kmalloc(len
, GFP_KERNEL
);
8657 memcpy(buf
, &start
, 4);
8659 memcpy(buf
+len
-4, &end
, 4);
8660 memcpy(buf
+ b_offset
, data
, eeprom
->len
);
8663 ret
= tg3_nvram_write_block(tp
, offset
, len
, buf
);
8671 static int tg3_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
8673 struct tg3
*tp
= netdev_priv(dev
);
8675 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
8676 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
8678 return phy_ethtool_gset(tp
->mdio_bus
->phy_map
[PHY_ADDR
], cmd
);
8681 cmd
->supported
= (SUPPORTED_Autoneg
);
8683 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
8684 cmd
->supported
|= (SUPPORTED_1000baseT_Half
|
8685 SUPPORTED_1000baseT_Full
);
8687 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)) {
8688 cmd
->supported
|= (SUPPORTED_100baseT_Half
|
8689 SUPPORTED_100baseT_Full
|
8690 SUPPORTED_10baseT_Half
|
8691 SUPPORTED_10baseT_Full
|
8693 cmd
->port
= PORT_TP
;
8695 cmd
->supported
|= SUPPORTED_FIBRE
;
8696 cmd
->port
= PORT_FIBRE
;
8699 cmd
->advertising
= tp
->link_config
.advertising
;
8700 if (netif_running(dev
)) {
8701 cmd
->speed
= tp
->link_config
.active_speed
;
8702 cmd
->duplex
= tp
->link_config
.active_duplex
;
8704 cmd
->phy_address
= PHY_ADDR
;
8705 cmd
->transceiver
= XCVR_INTERNAL
;
8706 cmd
->autoneg
= tp
->link_config
.autoneg
;
8712 static int tg3_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
8714 struct tg3
*tp
= netdev_priv(dev
);
8716 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
8717 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
8719 return phy_ethtool_sset(tp
->mdio_bus
->phy_map
[PHY_ADDR
], cmd
);
8722 if (cmd
->autoneg
!= AUTONEG_ENABLE
&&
8723 cmd
->autoneg
!= AUTONEG_DISABLE
)
8726 if (cmd
->autoneg
== AUTONEG_DISABLE
&&
8727 cmd
->duplex
!= DUPLEX_FULL
&&
8728 cmd
->duplex
!= DUPLEX_HALF
)
8731 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
8732 u32 mask
= ADVERTISED_Autoneg
|
8734 ADVERTISED_Asym_Pause
;
8736 if (!(tp
->tg3_flags2
& TG3_FLAG_10_100_ONLY
))
8737 mask
|= ADVERTISED_1000baseT_Half
|
8738 ADVERTISED_1000baseT_Full
;
8740 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
))
8741 mask
|= ADVERTISED_100baseT_Half
|
8742 ADVERTISED_100baseT_Full
|
8743 ADVERTISED_10baseT_Half
|
8744 ADVERTISED_10baseT_Full
|
8747 mask
|= ADVERTISED_FIBRE
;
8749 if (cmd
->advertising
& ~mask
)
8752 mask
&= (ADVERTISED_1000baseT_Half
|
8753 ADVERTISED_1000baseT_Full
|
8754 ADVERTISED_100baseT_Half
|
8755 ADVERTISED_100baseT_Full
|
8756 ADVERTISED_10baseT_Half
|
8757 ADVERTISED_10baseT_Full
);
8759 cmd
->advertising
&= mask
;
8761 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
) {
8762 if (cmd
->speed
!= SPEED_1000
)
8765 if (cmd
->duplex
!= DUPLEX_FULL
)
8768 if (cmd
->speed
!= SPEED_100
&&
8769 cmd
->speed
!= SPEED_10
)
8774 tg3_full_lock(tp
, 0);
8776 tp
->link_config
.autoneg
= cmd
->autoneg
;
8777 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
8778 tp
->link_config
.advertising
= (cmd
->advertising
|
8779 ADVERTISED_Autoneg
);
8780 tp
->link_config
.speed
= SPEED_INVALID
;
8781 tp
->link_config
.duplex
= DUPLEX_INVALID
;
8783 tp
->link_config
.advertising
= 0;
8784 tp
->link_config
.speed
= cmd
->speed
;
8785 tp
->link_config
.duplex
= cmd
->duplex
;
8788 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
8789 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
8790 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
8792 if (netif_running(dev
))
8793 tg3_setup_phy(tp
, 1);
8795 tg3_full_unlock(tp
);
8800 static void tg3_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
8802 struct tg3
*tp
= netdev_priv(dev
);
8804 strcpy(info
->driver
, DRV_MODULE_NAME
);
8805 strcpy(info
->version
, DRV_MODULE_VERSION
);
8806 strcpy(info
->fw_version
, tp
->fw_ver
);
8807 strcpy(info
->bus_info
, pci_name(tp
->pdev
));
8810 static void tg3_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
8812 struct tg3
*tp
= netdev_priv(dev
);
8814 if ((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) &&
8815 device_can_wakeup(&tp
->pdev
->dev
))
8816 wol
->supported
= WAKE_MAGIC
;
8820 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) &&
8821 device_can_wakeup(&tp
->pdev
->dev
))
8822 wol
->wolopts
= WAKE_MAGIC
;
8823 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
8826 static int tg3_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
8828 struct tg3
*tp
= netdev_priv(dev
);
8829 struct device
*dp
= &tp
->pdev
->dev
;
8831 if (wol
->wolopts
& ~WAKE_MAGIC
)
8833 if ((wol
->wolopts
& WAKE_MAGIC
) &&
8834 !((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) && device_can_wakeup(dp
)))
8837 spin_lock_bh(&tp
->lock
);
8838 if (wol
->wolopts
& WAKE_MAGIC
) {
8839 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
8840 device_set_wakeup_enable(dp
, true);
8842 tp
->tg3_flags
&= ~TG3_FLAG_WOL_ENABLE
;
8843 device_set_wakeup_enable(dp
, false);
8845 spin_unlock_bh(&tp
->lock
);
8850 static u32
tg3_get_msglevel(struct net_device
*dev
)
8852 struct tg3
*tp
= netdev_priv(dev
);
8853 return tp
->msg_enable
;
8856 static void tg3_set_msglevel(struct net_device
*dev
, u32 value
)
8858 struct tg3
*tp
= netdev_priv(dev
);
8859 tp
->msg_enable
= value
;
8862 static int tg3_set_tso(struct net_device
*dev
, u32 value
)
8864 struct tg3
*tp
= netdev_priv(dev
);
8866 if (!(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
8871 if ((dev
->features
& NETIF_F_IPV6_CSUM
) &&
8872 (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
)) {
8874 dev
->features
|= NETIF_F_TSO6
;
8875 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
8876 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
8877 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) ||
8878 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
8879 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
8880 dev
->features
|= NETIF_F_TSO_ECN
;
8882 dev
->features
&= ~(NETIF_F_TSO6
| NETIF_F_TSO_ECN
);
8884 return ethtool_op_set_tso(dev
, value
);
8887 static int tg3_nway_reset(struct net_device
*dev
)
8889 struct tg3
*tp
= netdev_priv(dev
);
8892 if (!netif_running(dev
))
8895 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
8898 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
8899 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
8901 r
= phy_start_aneg(tp
->mdio_bus
->phy_map
[PHY_ADDR
]);
8905 spin_lock_bh(&tp
->lock
);
8907 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
8908 if (!tg3_readphy(tp
, MII_BMCR
, &bmcr
) &&
8909 ((bmcr
& BMCR_ANENABLE
) ||
8910 (tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
))) {
8911 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANRESTART
|
8915 spin_unlock_bh(&tp
->lock
);
8921 static void tg3_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
8923 struct tg3
*tp
= netdev_priv(dev
);
8925 ering
->rx_max_pending
= TG3_RX_RING_SIZE
- 1;
8926 ering
->rx_mini_max_pending
= 0;
8927 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
)
8928 ering
->rx_jumbo_max_pending
= TG3_RX_JUMBO_RING_SIZE
- 1;
8930 ering
->rx_jumbo_max_pending
= 0;
8932 ering
->tx_max_pending
= TG3_TX_RING_SIZE
- 1;
8934 ering
->rx_pending
= tp
->rx_pending
;
8935 ering
->rx_mini_pending
= 0;
8936 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
)
8937 ering
->rx_jumbo_pending
= tp
->rx_jumbo_pending
;
8939 ering
->rx_jumbo_pending
= 0;
8941 ering
->tx_pending
= tp
->tx_pending
;
8944 static int tg3_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
8946 struct tg3
*tp
= netdev_priv(dev
);
8947 int irq_sync
= 0, err
= 0;
8949 if ((ering
->rx_pending
> TG3_RX_RING_SIZE
- 1) ||
8950 (ering
->rx_jumbo_pending
> TG3_RX_JUMBO_RING_SIZE
- 1) ||
8951 (ering
->tx_pending
> TG3_TX_RING_SIZE
- 1) ||
8952 (ering
->tx_pending
<= MAX_SKB_FRAGS
) ||
8953 ((tp
->tg3_flags2
& TG3_FLG2_TSO_BUG
) &&
8954 (ering
->tx_pending
<= (MAX_SKB_FRAGS
* 3))))
8957 if (netif_running(dev
)) {
8963 tg3_full_lock(tp
, irq_sync
);
8965 tp
->rx_pending
= ering
->rx_pending
;
8967 if ((tp
->tg3_flags2
& TG3_FLG2_MAX_RXPEND_64
) &&
8968 tp
->rx_pending
> 63)
8969 tp
->rx_pending
= 63;
8970 tp
->rx_jumbo_pending
= ering
->rx_jumbo_pending
;
8971 tp
->tx_pending
= ering
->tx_pending
;
8973 if (netif_running(dev
)) {
8974 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8975 err
= tg3_restart_hw(tp
, 1);
8977 tg3_netif_start(tp
);
8980 tg3_full_unlock(tp
);
8982 if (irq_sync
&& !err
)
8988 static void tg3_get_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
8990 struct tg3
*tp
= netdev_priv(dev
);
8992 epause
->autoneg
= (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
) != 0;
8994 if (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
)
8995 epause
->rx_pause
= 1;
8997 epause
->rx_pause
= 0;
8999 if (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
)
9000 epause
->tx_pause
= 1;
9002 epause
->tx_pause
= 0;
9005 static int tg3_set_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
9007 struct tg3
*tp
= netdev_priv(dev
);
9010 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9011 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
9014 if (epause
->autoneg
) {
9016 struct phy_device
*phydev
;
9018 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
9020 if (epause
->rx_pause
) {
9021 if (epause
->tx_pause
)
9022 newadv
= ADVERTISED_Pause
;
9024 newadv
= ADVERTISED_Pause
|
9025 ADVERTISED_Asym_Pause
;
9026 } else if (epause
->tx_pause
) {
9027 newadv
= ADVERTISED_Asym_Pause
;
9031 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) {
9032 u32 oldadv
= phydev
->advertising
&
9034 ADVERTISED_Asym_Pause
);
9035 if (oldadv
!= newadv
) {
9036 phydev
->advertising
&=
9037 ~(ADVERTISED_Pause
|
9038 ADVERTISED_Asym_Pause
);
9039 phydev
->advertising
|= newadv
;
9040 err
= phy_start_aneg(phydev
);
9043 tp
->link_config
.advertising
&=
9044 ~(ADVERTISED_Pause
|
9045 ADVERTISED_Asym_Pause
);
9046 tp
->link_config
.advertising
|= newadv
;
9049 if (epause
->rx_pause
)
9050 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
9052 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_RX
;
9054 if (epause
->tx_pause
)
9055 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
9057 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_TX
;
9059 if (netif_running(dev
))
9060 tg3_setup_flow_control(tp
, 0, 0);
9065 if (netif_running(dev
)) {
9070 tg3_full_lock(tp
, irq_sync
);
9072 if (epause
->autoneg
)
9073 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
9075 tp
->tg3_flags
&= ~TG3_FLAG_PAUSE_AUTONEG
;
9076 if (epause
->rx_pause
)
9077 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
9079 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_RX
;
9080 if (epause
->tx_pause
)
9081 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
9083 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_TX
;
9085 if (netif_running(dev
)) {
9086 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9087 err
= tg3_restart_hw(tp
, 1);
9089 tg3_netif_start(tp
);
9092 tg3_full_unlock(tp
);
9098 static u32
tg3_get_rx_csum(struct net_device
*dev
)
9100 struct tg3
*tp
= netdev_priv(dev
);
9101 return (tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) != 0;
9104 static int tg3_set_rx_csum(struct net_device
*dev
, u32 data
)
9106 struct tg3
*tp
= netdev_priv(dev
);
9108 if (tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) {
9114 spin_lock_bh(&tp
->lock
);
9116 tp
->tg3_flags
|= TG3_FLAG_RX_CHECKSUMS
;
9118 tp
->tg3_flags
&= ~TG3_FLAG_RX_CHECKSUMS
;
9119 spin_unlock_bh(&tp
->lock
);
9124 static int tg3_set_tx_csum(struct net_device
*dev
, u32 data
)
9126 struct tg3
*tp
= netdev_priv(dev
);
9128 if (tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) {
9134 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
9135 ethtool_op_set_tx_ipv6_csum(dev
, data
);
9137 ethtool_op_set_tx_csum(dev
, data
);
9142 static int tg3_get_sset_count (struct net_device
*dev
, int sset
)
9146 return TG3_NUM_TEST
;
9148 return TG3_NUM_STATS
;
9154 static void tg3_get_strings (struct net_device
*dev
, u32 stringset
, u8
*buf
)
9156 switch (stringset
) {
9158 memcpy(buf
, ðtool_stats_keys
, sizeof(ethtool_stats_keys
));
9161 memcpy(buf
, ðtool_test_keys
, sizeof(ethtool_test_keys
));
9164 WARN_ON(1); /* we need a WARN() */
9169 static int tg3_phys_id(struct net_device
*dev
, u32 data
)
9171 struct tg3
*tp
= netdev_priv(dev
);
9174 if (!netif_running(tp
->dev
))
9178 data
= UINT_MAX
/ 2;
9180 for (i
= 0; i
< (data
* 2); i
++) {
9182 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
9183 LED_CTRL_1000MBPS_ON
|
9184 LED_CTRL_100MBPS_ON
|
9185 LED_CTRL_10MBPS_ON
|
9186 LED_CTRL_TRAFFIC_OVERRIDE
|
9187 LED_CTRL_TRAFFIC_BLINK
|
9188 LED_CTRL_TRAFFIC_LED
);
9191 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
9192 LED_CTRL_TRAFFIC_OVERRIDE
);
9194 if (msleep_interruptible(500))
9197 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
9201 static void tg3_get_ethtool_stats (struct net_device
*dev
,
9202 struct ethtool_stats
*estats
, u64
*tmp_stats
)
9204 struct tg3
*tp
= netdev_priv(dev
);
9205 memcpy(tmp_stats
, tg3_get_estats(tp
), sizeof(tp
->estats
));
9208 #define NVRAM_TEST_SIZE 0x100
9209 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9210 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9211 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
9212 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9213 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9215 static int tg3_test_nvram(struct tg3
*tp
)
9219 int i
, j
, k
, err
= 0, size
;
9221 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
)
9224 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
9227 if (magic
== TG3_EEPROM_MAGIC
)
9228 size
= NVRAM_TEST_SIZE
;
9229 else if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
) {
9230 if ((magic
& TG3_EEPROM_SB_FORMAT_MASK
) ==
9231 TG3_EEPROM_SB_FORMAT_1
) {
9232 switch (magic
& TG3_EEPROM_SB_REVISION_MASK
) {
9233 case TG3_EEPROM_SB_REVISION_0
:
9234 size
= NVRAM_SELFBOOT_FORMAT1_0_SIZE
;
9236 case TG3_EEPROM_SB_REVISION_2
:
9237 size
= NVRAM_SELFBOOT_FORMAT1_2_SIZE
;
9239 case TG3_EEPROM_SB_REVISION_3
:
9240 size
= NVRAM_SELFBOOT_FORMAT1_3_SIZE
;
9247 } else if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
9248 size
= NVRAM_SELFBOOT_HW_SIZE
;
9252 buf
= kmalloc(size
, GFP_KERNEL
);
9257 for (i
= 0, j
= 0; i
< size
; i
+= 4, j
++) {
9258 err
= tg3_nvram_read_be32(tp
, i
, &buf
[j
]);
9265 /* Selfboot format */
9266 magic
= be32_to_cpu(buf
[0]);
9267 if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) ==
9268 TG3_EEPROM_MAGIC_FW
) {
9269 u8
*buf8
= (u8
*) buf
, csum8
= 0;
9271 if ((magic
& TG3_EEPROM_SB_REVISION_MASK
) ==
9272 TG3_EEPROM_SB_REVISION_2
) {
9273 /* For rev 2, the csum doesn't include the MBA. */
9274 for (i
= 0; i
< TG3_EEPROM_SB_F1R2_MBA_OFF
; i
++)
9276 for (i
= TG3_EEPROM_SB_F1R2_MBA_OFF
+ 4; i
< size
; i
++)
9279 for (i
= 0; i
< size
; i
++)
9292 if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) ==
9293 TG3_EEPROM_MAGIC_HW
) {
9294 u8 data
[NVRAM_SELFBOOT_DATA_SIZE
];
9295 u8 parity
[NVRAM_SELFBOOT_DATA_SIZE
];
9296 u8
*buf8
= (u8
*) buf
;
9298 /* Separate the parity bits and the data bytes. */
9299 for (i
= 0, j
= 0, k
= 0; i
< NVRAM_SELFBOOT_HW_SIZE
; i
++) {
9300 if ((i
== 0) || (i
== 8)) {
9304 for (l
= 0, msk
= 0x80; l
< 7; l
++, msk
>>= 1)
9305 parity
[k
++] = buf8
[i
] & msk
;
9312 for (l
= 0, msk
= 0x20; l
< 6; l
++, msk
>>= 1)
9313 parity
[k
++] = buf8
[i
] & msk
;
9316 for (l
= 0, msk
= 0x80; l
< 8; l
++, msk
>>= 1)
9317 parity
[k
++] = buf8
[i
] & msk
;
9320 data
[j
++] = buf8
[i
];
9324 for (i
= 0; i
< NVRAM_SELFBOOT_DATA_SIZE
; i
++) {
9325 u8 hw8
= hweight8(data
[i
]);
9327 if ((hw8
& 0x1) && parity
[i
])
9329 else if (!(hw8
& 0x1) && !parity
[i
])
9336 /* Bootstrap checksum at offset 0x10 */
9337 csum
= calc_crc((unsigned char *) buf
, 0x10);
9338 if (csum
!= be32_to_cpu(buf
[0x10/4]))
9341 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9342 csum
= calc_crc((unsigned char *) &buf
[0x74/4], 0x88);
9343 if (csum
!= be32_to_cpu(buf
[0xfc/4]))
9353 #define TG3_SERDES_TIMEOUT_SEC 2
9354 #define TG3_COPPER_TIMEOUT_SEC 6
9356 static int tg3_test_link(struct tg3
*tp
)
9360 if (!netif_running(tp
->dev
))
9363 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)
9364 max
= TG3_SERDES_TIMEOUT_SEC
;
9366 max
= TG3_COPPER_TIMEOUT_SEC
;
9368 for (i
= 0; i
< max
; i
++) {
9369 if (netif_carrier_ok(tp
->dev
))
9372 if (msleep_interruptible(1000))
9379 /* Only test the commonly used registers */
9380 static int tg3_test_registers(struct tg3
*tp
)
9382 int i
, is_5705
, is_5750
;
9383 u32 offset
, read_mask
, write_mask
, val
, save_val
, read_val
;
9387 #define TG3_FL_5705 0x1
9388 #define TG3_FL_NOT_5705 0x2
9389 #define TG3_FL_NOT_5788 0x4
9390 #define TG3_FL_NOT_5750 0x8
9394 /* MAC Control Registers */
9395 { MAC_MODE
, TG3_FL_NOT_5705
,
9396 0x00000000, 0x00ef6f8c },
9397 { MAC_MODE
, TG3_FL_5705
,
9398 0x00000000, 0x01ef6b8c },
9399 { MAC_STATUS
, TG3_FL_NOT_5705
,
9400 0x03800107, 0x00000000 },
9401 { MAC_STATUS
, TG3_FL_5705
,
9402 0x03800100, 0x00000000 },
9403 { MAC_ADDR_0_HIGH
, 0x0000,
9404 0x00000000, 0x0000ffff },
9405 { MAC_ADDR_0_LOW
, 0x0000,
9406 0x00000000, 0xffffffff },
9407 { MAC_RX_MTU_SIZE
, 0x0000,
9408 0x00000000, 0x0000ffff },
9409 { MAC_TX_MODE
, 0x0000,
9410 0x00000000, 0x00000070 },
9411 { MAC_TX_LENGTHS
, 0x0000,
9412 0x00000000, 0x00003fff },
9413 { MAC_RX_MODE
, TG3_FL_NOT_5705
,
9414 0x00000000, 0x000007fc },
9415 { MAC_RX_MODE
, TG3_FL_5705
,
9416 0x00000000, 0x000007dc },
9417 { MAC_HASH_REG_0
, 0x0000,
9418 0x00000000, 0xffffffff },
9419 { MAC_HASH_REG_1
, 0x0000,
9420 0x00000000, 0xffffffff },
9421 { MAC_HASH_REG_2
, 0x0000,
9422 0x00000000, 0xffffffff },
9423 { MAC_HASH_REG_3
, 0x0000,
9424 0x00000000, 0xffffffff },
9426 /* Receive Data and Receive BD Initiator Control Registers. */
9427 { RCVDBDI_JUMBO_BD
+0, TG3_FL_NOT_5705
,
9428 0x00000000, 0xffffffff },
9429 { RCVDBDI_JUMBO_BD
+4, TG3_FL_NOT_5705
,
9430 0x00000000, 0xffffffff },
9431 { RCVDBDI_JUMBO_BD
+8, TG3_FL_NOT_5705
,
9432 0x00000000, 0x00000003 },
9433 { RCVDBDI_JUMBO_BD
+0xc, TG3_FL_NOT_5705
,
9434 0x00000000, 0xffffffff },
9435 { RCVDBDI_STD_BD
+0, 0x0000,
9436 0x00000000, 0xffffffff },
9437 { RCVDBDI_STD_BD
+4, 0x0000,
9438 0x00000000, 0xffffffff },
9439 { RCVDBDI_STD_BD
+8, 0x0000,
9440 0x00000000, 0xffff0002 },
9441 { RCVDBDI_STD_BD
+0xc, 0x0000,
9442 0x00000000, 0xffffffff },
9444 /* Receive BD Initiator Control Registers. */
9445 { RCVBDI_STD_THRESH
, TG3_FL_NOT_5705
,
9446 0x00000000, 0xffffffff },
9447 { RCVBDI_STD_THRESH
, TG3_FL_5705
,
9448 0x00000000, 0x000003ff },
9449 { RCVBDI_JUMBO_THRESH
, TG3_FL_NOT_5705
,
9450 0x00000000, 0xffffffff },
9452 /* Host Coalescing Control Registers. */
9453 { HOSTCC_MODE
, TG3_FL_NOT_5705
,
9454 0x00000000, 0x00000004 },
9455 { HOSTCC_MODE
, TG3_FL_5705
,
9456 0x00000000, 0x000000f6 },
9457 { HOSTCC_RXCOL_TICKS
, TG3_FL_NOT_5705
,
9458 0x00000000, 0xffffffff },
9459 { HOSTCC_RXCOL_TICKS
, TG3_FL_5705
,
9460 0x00000000, 0x000003ff },
9461 { HOSTCC_TXCOL_TICKS
, TG3_FL_NOT_5705
,
9462 0x00000000, 0xffffffff },
9463 { HOSTCC_TXCOL_TICKS
, TG3_FL_5705
,
9464 0x00000000, 0x000003ff },
9465 { HOSTCC_RXMAX_FRAMES
, TG3_FL_NOT_5705
,
9466 0x00000000, 0xffffffff },
9467 { HOSTCC_RXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
9468 0x00000000, 0x000000ff },
9469 { HOSTCC_TXMAX_FRAMES
, TG3_FL_NOT_5705
,
9470 0x00000000, 0xffffffff },
9471 { HOSTCC_TXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
9472 0x00000000, 0x000000ff },
9473 { HOSTCC_RXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
9474 0x00000000, 0xffffffff },
9475 { HOSTCC_TXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
9476 0x00000000, 0xffffffff },
9477 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
9478 0x00000000, 0xffffffff },
9479 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
9480 0x00000000, 0x000000ff },
9481 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
9482 0x00000000, 0xffffffff },
9483 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
9484 0x00000000, 0x000000ff },
9485 { HOSTCC_STAT_COAL_TICKS
, TG3_FL_NOT_5705
,
9486 0x00000000, 0xffffffff },
9487 { HOSTCC_STATS_BLK_HOST_ADDR
, TG3_FL_NOT_5705
,
9488 0x00000000, 0xffffffff },
9489 { HOSTCC_STATS_BLK_HOST_ADDR
+4, TG3_FL_NOT_5705
,
9490 0x00000000, 0xffffffff },
9491 { HOSTCC_STATUS_BLK_HOST_ADDR
, 0x0000,
9492 0x00000000, 0xffffffff },
9493 { HOSTCC_STATUS_BLK_HOST_ADDR
+4, 0x0000,
9494 0x00000000, 0xffffffff },
9495 { HOSTCC_STATS_BLK_NIC_ADDR
, 0x0000,
9496 0xffffffff, 0x00000000 },
9497 { HOSTCC_STATUS_BLK_NIC_ADDR
, 0x0000,
9498 0xffffffff, 0x00000000 },
9500 /* Buffer Manager Control Registers. */
9501 { BUFMGR_MB_POOL_ADDR
, TG3_FL_NOT_5750
,
9502 0x00000000, 0x007fff80 },
9503 { BUFMGR_MB_POOL_SIZE
, TG3_FL_NOT_5750
,
9504 0x00000000, 0x007fffff },
9505 { BUFMGR_MB_RDMA_LOW_WATER
, 0x0000,
9506 0x00000000, 0x0000003f },
9507 { BUFMGR_MB_MACRX_LOW_WATER
, 0x0000,
9508 0x00000000, 0x000001ff },
9509 { BUFMGR_MB_HIGH_WATER
, 0x0000,
9510 0x00000000, 0x000001ff },
9511 { BUFMGR_DMA_DESC_POOL_ADDR
, TG3_FL_NOT_5705
,
9512 0xffffffff, 0x00000000 },
9513 { BUFMGR_DMA_DESC_POOL_SIZE
, TG3_FL_NOT_5705
,
9514 0xffffffff, 0x00000000 },
9516 /* Mailbox Registers */
9517 { GRCMBOX_RCVSTD_PROD_IDX
+4, 0x0000,
9518 0x00000000, 0x000001ff },
9519 { GRCMBOX_RCVJUMBO_PROD_IDX
+4, TG3_FL_NOT_5705
,
9520 0x00000000, 0x000001ff },
9521 { GRCMBOX_RCVRET_CON_IDX_0
+4, 0x0000,
9522 0x00000000, 0x000007ff },
9523 { GRCMBOX_SNDHOST_PROD_IDX_0
+4, 0x0000,
9524 0x00000000, 0x000001ff },
9526 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9529 is_5705
= is_5750
= 0;
9530 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
9532 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
9536 for (i
= 0; reg_tbl
[i
].offset
!= 0xffff; i
++) {
9537 if (is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5705
))
9540 if (!is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_5705
))
9543 if ((tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
9544 (reg_tbl
[i
].flags
& TG3_FL_NOT_5788
))
9547 if (is_5750
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5750
))
9550 offset
= (u32
) reg_tbl
[i
].offset
;
9551 read_mask
= reg_tbl
[i
].read_mask
;
9552 write_mask
= reg_tbl
[i
].write_mask
;
9554 /* Save the original register content */
9555 save_val
= tr32(offset
);
9557 /* Determine the read-only value. */
9558 read_val
= save_val
& read_mask
;
9560 /* Write zero to the register, then make sure the read-only bits
9561 * are not changed and the read/write bits are all zeros.
9567 /* Test the read-only and read/write bits. */
9568 if (((val
& read_mask
) != read_val
) || (val
& write_mask
))
9571 /* Write ones to all the bits defined by RdMask and WrMask, then
9572 * make sure the read-only bits are not changed and the
9573 * read/write bits are all ones.
9575 tw32(offset
, read_mask
| write_mask
);
9579 /* Test the read-only bits. */
9580 if ((val
& read_mask
) != read_val
)
9583 /* Test the read/write bits. */
9584 if ((val
& write_mask
) != write_mask
)
9587 tw32(offset
, save_val
);
9593 if (netif_msg_hw(tp
))
9594 printk(KERN_ERR PFX
"Register test failed at offset %x\n",
9596 tw32(offset
, save_val
);
9600 static int tg3_do_mem_test(struct tg3
*tp
, u32 offset
, u32 len
)
9602 static const u32 test_pattern
[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9606 for (i
= 0; i
< ARRAY_SIZE(test_pattern
); i
++) {
9607 for (j
= 0; j
< len
; j
+= 4) {
9610 tg3_write_mem(tp
, offset
+ j
, test_pattern
[i
]);
9611 tg3_read_mem(tp
, offset
+ j
, &val
);
9612 if (val
!= test_pattern
[i
])
9619 static int tg3_test_memory(struct tg3
*tp
)
9621 static struct mem_entry
{
9624 } mem_tbl_570x
[] = {
9625 { 0x00000000, 0x00b50},
9626 { 0x00002000, 0x1c000},
9627 { 0xffffffff, 0x00000}
9628 }, mem_tbl_5705
[] = {
9629 { 0x00000100, 0x0000c},
9630 { 0x00000200, 0x00008},
9631 { 0x00004000, 0x00800},
9632 { 0x00006000, 0x01000},
9633 { 0x00008000, 0x02000},
9634 { 0x00010000, 0x0e000},
9635 { 0xffffffff, 0x00000}
9636 }, mem_tbl_5755
[] = {
9637 { 0x00000200, 0x00008},
9638 { 0x00004000, 0x00800},
9639 { 0x00006000, 0x00800},
9640 { 0x00008000, 0x02000},
9641 { 0x00010000, 0x0c000},
9642 { 0xffffffff, 0x00000}
9643 }, mem_tbl_5906
[] = {
9644 { 0x00000200, 0x00008},
9645 { 0x00004000, 0x00400},
9646 { 0x00006000, 0x00400},
9647 { 0x00008000, 0x01000},
9648 { 0x00010000, 0x01000},
9649 { 0xffffffff, 0x00000}
9651 struct mem_entry
*mem_tbl
;
9655 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
9656 mem_tbl
= mem_tbl_5755
;
9657 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
9658 mem_tbl
= mem_tbl_5906
;
9659 else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
9660 mem_tbl
= mem_tbl_5705
;
9662 mem_tbl
= mem_tbl_570x
;
9664 for (i
= 0; mem_tbl
[i
].offset
!= 0xffffffff; i
++) {
9665 if ((err
= tg3_do_mem_test(tp
, mem_tbl
[i
].offset
,
9666 mem_tbl
[i
].len
)) != 0)
9673 #define TG3_MAC_LOOPBACK 0
9674 #define TG3_PHY_LOOPBACK 1
9676 static int tg3_run_loopback(struct tg3
*tp
, int loopback_mode
)
9678 u32 mac_mode
, rx_start_idx
, rx_idx
, tx_idx
, opaque_key
;
9680 struct sk_buff
*skb
, *rx_skb
;
9683 int num_pkts
, tx_len
, rx_len
, i
, err
;
9684 struct tg3_rx_buffer_desc
*desc
;
9686 if (loopback_mode
== TG3_MAC_LOOPBACK
) {
9687 /* HW errata - mac loopback fails in some cases on 5780.
9688 * Normal traffic and PHY loopback are not affected by
9691 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
)
9694 mac_mode
= (tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
) |
9695 MAC_MODE_PORT_INT_LPBACK
;
9696 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
9697 mac_mode
|= MAC_MODE_LINK_POLARITY
;
9698 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
9699 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
9701 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
9702 tw32(MAC_MODE
, mac_mode
);
9703 } else if (loopback_mode
== TG3_PHY_LOOPBACK
) {
9706 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
9709 if (!tg3_readphy(tp
, MII_TG3_EPHY_TEST
, &phytest
)) {
9712 tg3_writephy(tp
, MII_TG3_EPHY_TEST
,
9713 phytest
| MII_TG3_EPHY_SHADOW_EN
);
9714 if (!tg3_readphy(tp
, 0x1b, &phy
))
9715 tg3_writephy(tp
, 0x1b, phy
& ~0x20);
9716 tg3_writephy(tp
, MII_TG3_EPHY_TEST
, phytest
);
9718 val
= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED100
;
9720 val
= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED1000
;
9722 tg3_phy_toggle_automdix(tp
, 0);
9724 tg3_writephy(tp
, MII_BMCR
, val
);
9727 mac_mode
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
9728 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
9729 tg3_writephy(tp
, MII_TG3_EPHY_PTEST
, 0x1800);
9730 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
9732 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
9734 /* reset to prevent losing 1st rx packet intermittently */
9735 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
9736 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
9738 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
9740 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
9741 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
)
9742 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
9743 else if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5411
)
9744 mac_mode
|= MAC_MODE_LINK_POLARITY
;
9745 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
9746 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
9748 tw32(MAC_MODE
, mac_mode
);
9756 skb
= netdev_alloc_skb(tp
->dev
, tx_len
);
9760 tx_data
= skb_put(skb
, tx_len
);
9761 memcpy(tx_data
, tp
->dev
->dev_addr
, 6);
9762 memset(tx_data
+ 6, 0x0, 8);
9764 tw32(MAC_RX_MTU_SIZE
, tx_len
+ 4);
9766 for (i
= 14; i
< tx_len
; i
++)
9767 tx_data
[i
] = (u8
) (i
& 0xff);
9769 map
= pci_map_single(tp
->pdev
, skb
->data
, tx_len
, PCI_DMA_TODEVICE
);
9771 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
9776 rx_start_idx
= tp
->hw_status
->idx
[0].rx_producer
;
9780 tg3_set_txd(tp
, tp
->tx_prod
, map
, tx_len
, 0, 1);
9785 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
,
9787 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
);
9791 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
9792 for (i
= 0; i
< 25; i
++) {
9793 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
9798 tx_idx
= tp
->hw_status
->idx
[0].tx_consumer
;
9799 rx_idx
= tp
->hw_status
->idx
[0].rx_producer
;
9800 if ((tx_idx
== tp
->tx_prod
) &&
9801 (rx_idx
== (rx_start_idx
+ num_pkts
)))
9805 pci_unmap_single(tp
->pdev
, map
, tx_len
, PCI_DMA_TODEVICE
);
9808 if (tx_idx
!= tp
->tx_prod
)
9811 if (rx_idx
!= rx_start_idx
+ num_pkts
)
9814 desc
= &tp
->rx_rcb
[rx_start_idx
];
9815 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
9816 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
9817 if (opaque_key
!= RXD_OPAQUE_RING_STD
)
9820 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
9821 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
))
9824 rx_len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) - 4;
9825 if (rx_len
!= tx_len
)
9828 rx_skb
= tp
->rx_std_buffers
[desc_idx
].skb
;
9830 map
= pci_unmap_addr(&tp
->rx_std_buffers
[desc_idx
], mapping
);
9831 pci_dma_sync_single_for_cpu(tp
->pdev
, map
, rx_len
, PCI_DMA_FROMDEVICE
);
9833 for (i
= 14; i
< tx_len
; i
++) {
9834 if (*(rx_skb
->data
+ i
) != (u8
) (i
& 0xff))
9839 /* tg3_free_rings will unmap and free the rx_skb */
9844 #define TG3_MAC_LOOPBACK_FAILED 1
9845 #define TG3_PHY_LOOPBACK_FAILED 2
9846 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
9847 TG3_PHY_LOOPBACK_FAILED)
9849 static int tg3_test_loopback(struct tg3
*tp
)
9854 if (!netif_running(tp
->dev
))
9855 return TG3_LOOPBACK_FAILED
;
9857 err
= tg3_reset_hw(tp
, 1);
9859 return TG3_LOOPBACK_FAILED
;
9861 /* Turn off gphy autopowerdown. */
9862 if (tp
->tg3_flags3
& TG3_FLG3_PHY_ENABLE_APD
)
9863 tg3_phy_toggle_apd(tp
, false);
9865 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) {
9869 tw32(TG3_CPMU_MUTEX_REQ
, CPMU_MUTEX_REQ_DRIVER
);
9871 /* Wait for up to 40 microseconds to acquire lock. */
9872 for (i
= 0; i
< 4; i
++) {
9873 status
= tr32(TG3_CPMU_MUTEX_GNT
);
9874 if (status
== CPMU_MUTEX_GNT_DRIVER
)
9879 if (status
!= CPMU_MUTEX_GNT_DRIVER
)
9880 return TG3_LOOPBACK_FAILED
;
9882 /* Turn off link-based power management. */
9883 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
9885 cpmuctrl
& ~(CPMU_CTRL_LINK_SPEED_MODE
|
9886 CPMU_CTRL_LINK_AWARE_MODE
));
9889 if (tg3_run_loopback(tp
, TG3_MAC_LOOPBACK
))
9890 err
|= TG3_MAC_LOOPBACK_FAILED
;
9892 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) {
9893 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
9895 /* Release the mutex */
9896 tw32(TG3_CPMU_MUTEX_GNT
, CPMU_MUTEX_GNT_DRIVER
);
9899 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
9900 !(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)) {
9901 if (tg3_run_loopback(tp
, TG3_PHY_LOOPBACK
))
9902 err
|= TG3_PHY_LOOPBACK_FAILED
;
9905 /* Re-enable gphy autopowerdown. */
9906 if (tp
->tg3_flags3
& TG3_FLG3_PHY_ENABLE_APD
)
9907 tg3_phy_toggle_apd(tp
, true);
9912 static void tg3_self_test(struct net_device
*dev
, struct ethtool_test
*etest
,
9915 struct tg3
*tp
= netdev_priv(dev
);
9917 if (tp
->link_config
.phy_is_low_power
)
9918 tg3_set_power_state(tp
, PCI_D0
);
9920 memset(data
, 0, sizeof(u64
) * TG3_NUM_TEST
);
9922 if (tg3_test_nvram(tp
) != 0) {
9923 etest
->flags
|= ETH_TEST_FL_FAILED
;
9926 if (tg3_test_link(tp
) != 0) {
9927 etest
->flags
|= ETH_TEST_FL_FAILED
;
9930 if (etest
->flags
& ETH_TEST_FL_OFFLINE
) {
9931 int err
, err2
= 0, irq_sync
= 0;
9933 if (netif_running(dev
)) {
9939 tg3_full_lock(tp
, irq_sync
);
9941 tg3_halt(tp
, RESET_KIND_SUSPEND
, 1);
9942 err
= tg3_nvram_lock(tp
);
9943 tg3_halt_cpu(tp
, RX_CPU_BASE
);
9944 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
9945 tg3_halt_cpu(tp
, TX_CPU_BASE
);
9947 tg3_nvram_unlock(tp
);
9949 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)
9952 if (tg3_test_registers(tp
) != 0) {
9953 etest
->flags
|= ETH_TEST_FL_FAILED
;
9956 if (tg3_test_memory(tp
) != 0) {
9957 etest
->flags
|= ETH_TEST_FL_FAILED
;
9960 if ((data
[4] = tg3_test_loopback(tp
)) != 0)
9961 etest
->flags
|= ETH_TEST_FL_FAILED
;
9963 tg3_full_unlock(tp
);
9965 if (tg3_test_interrupt(tp
) != 0) {
9966 etest
->flags
|= ETH_TEST_FL_FAILED
;
9970 tg3_full_lock(tp
, 0);
9972 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9973 if (netif_running(dev
)) {
9974 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
9975 err2
= tg3_restart_hw(tp
, 1);
9977 tg3_netif_start(tp
);
9980 tg3_full_unlock(tp
);
9982 if (irq_sync
&& !err2
)
9985 if (tp
->link_config
.phy_is_low_power
)
9986 tg3_set_power_state(tp
, PCI_D3hot
);
9990 static int tg3_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
9992 struct mii_ioctl_data
*data
= if_mii(ifr
);
9993 struct tg3
*tp
= netdev_priv(dev
);
9996 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9997 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
9999 return phy_mii_ioctl(tp
->mdio_bus
->phy_map
[PHY_ADDR
], data
, cmd
);
10004 data
->phy_id
= PHY_ADDR
;
10007 case SIOCGMIIREG
: {
10010 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
10011 break; /* We have no PHY */
10013 if (tp
->link_config
.phy_is_low_power
)
10016 spin_lock_bh(&tp
->lock
);
10017 err
= tg3_readphy(tp
, data
->reg_num
& 0x1f, &mii_regval
);
10018 spin_unlock_bh(&tp
->lock
);
10020 data
->val_out
= mii_regval
;
10026 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
10027 break; /* We have no PHY */
10029 if (!capable(CAP_NET_ADMIN
))
10032 if (tp
->link_config
.phy_is_low_power
)
10035 spin_lock_bh(&tp
->lock
);
10036 err
= tg3_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
10037 spin_unlock_bh(&tp
->lock
);
10045 return -EOPNOTSUPP
;
10048 #if TG3_VLAN_TAG_USED
10049 static void tg3_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
10051 struct tg3
*tp
= netdev_priv(dev
);
10053 if (!netif_running(dev
)) {
10058 tg3_netif_stop(tp
);
10060 tg3_full_lock(tp
, 0);
10064 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10065 __tg3_set_rx_mode(dev
);
10067 tg3_netif_start(tp
);
10069 tg3_full_unlock(tp
);
10073 static int tg3_get_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
10075 struct tg3
*tp
= netdev_priv(dev
);
10077 memcpy(ec
, &tp
->coal
, sizeof(*ec
));
10081 static int tg3_set_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
10083 struct tg3
*tp
= netdev_priv(dev
);
10084 u32 max_rxcoal_tick_int
= 0, max_txcoal_tick_int
= 0;
10085 u32 max_stat_coal_ticks
= 0, min_stat_coal_ticks
= 0;
10087 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
10088 max_rxcoal_tick_int
= MAX_RXCOAL_TICK_INT
;
10089 max_txcoal_tick_int
= MAX_TXCOAL_TICK_INT
;
10090 max_stat_coal_ticks
= MAX_STAT_COAL_TICKS
;
10091 min_stat_coal_ticks
= MIN_STAT_COAL_TICKS
;
10094 if ((ec
->rx_coalesce_usecs
> MAX_RXCOL_TICKS
) ||
10095 (ec
->tx_coalesce_usecs
> MAX_TXCOL_TICKS
) ||
10096 (ec
->rx_max_coalesced_frames
> MAX_RXMAX_FRAMES
) ||
10097 (ec
->tx_max_coalesced_frames
> MAX_TXMAX_FRAMES
) ||
10098 (ec
->rx_coalesce_usecs_irq
> max_rxcoal_tick_int
) ||
10099 (ec
->tx_coalesce_usecs_irq
> max_txcoal_tick_int
) ||
10100 (ec
->rx_max_coalesced_frames_irq
> MAX_RXCOAL_MAXF_INT
) ||
10101 (ec
->tx_max_coalesced_frames_irq
> MAX_TXCOAL_MAXF_INT
) ||
10102 (ec
->stats_block_coalesce_usecs
> max_stat_coal_ticks
) ||
10103 (ec
->stats_block_coalesce_usecs
< min_stat_coal_ticks
))
10106 /* No rx interrupts will be generated if both are zero */
10107 if ((ec
->rx_coalesce_usecs
== 0) &&
10108 (ec
->rx_max_coalesced_frames
== 0))
10111 /* No tx interrupts will be generated if both are zero */
10112 if ((ec
->tx_coalesce_usecs
== 0) &&
10113 (ec
->tx_max_coalesced_frames
== 0))
10116 /* Only copy relevant parameters, ignore all others. */
10117 tp
->coal
.rx_coalesce_usecs
= ec
->rx_coalesce_usecs
;
10118 tp
->coal
.tx_coalesce_usecs
= ec
->tx_coalesce_usecs
;
10119 tp
->coal
.rx_max_coalesced_frames
= ec
->rx_max_coalesced_frames
;
10120 tp
->coal
.tx_max_coalesced_frames
= ec
->tx_max_coalesced_frames
;
10121 tp
->coal
.rx_coalesce_usecs_irq
= ec
->rx_coalesce_usecs_irq
;
10122 tp
->coal
.tx_coalesce_usecs_irq
= ec
->tx_coalesce_usecs_irq
;
10123 tp
->coal
.rx_max_coalesced_frames_irq
= ec
->rx_max_coalesced_frames_irq
;
10124 tp
->coal
.tx_max_coalesced_frames_irq
= ec
->tx_max_coalesced_frames_irq
;
10125 tp
->coal
.stats_block_coalesce_usecs
= ec
->stats_block_coalesce_usecs
;
10127 if (netif_running(dev
)) {
10128 tg3_full_lock(tp
, 0);
10129 __tg3_set_coalesce(tp
, &tp
->coal
);
10130 tg3_full_unlock(tp
);
10135 static const struct ethtool_ops tg3_ethtool_ops
= {
10136 .get_settings
= tg3_get_settings
,
10137 .set_settings
= tg3_set_settings
,
10138 .get_drvinfo
= tg3_get_drvinfo
,
10139 .get_regs_len
= tg3_get_regs_len
,
10140 .get_regs
= tg3_get_regs
,
10141 .get_wol
= tg3_get_wol
,
10142 .set_wol
= tg3_set_wol
,
10143 .get_msglevel
= tg3_get_msglevel
,
10144 .set_msglevel
= tg3_set_msglevel
,
10145 .nway_reset
= tg3_nway_reset
,
10146 .get_link
= ethtool_op_get_link
,
10147 .get_eeprom_len
= tg3_get_eeprom_len
,
10148 .get_eeprom
= tg3_get_eeprom
,
10149 .set_eeprom
= tg3_set_eeprom
,
10150 .get_ringparam
= tg3_get_ringparam
,
10151 .set_ringparam
= tg3_set_ringparam
,
10152 .get_pauseparam
= tg3_get_pauseparam
,
10153 .set_pauseparam
= tg3_set_pauseparam
,
10154 .get_rx_csum
= tg3_get_rx_csum
,
10155 .set_rx_csum
= tg3_set_rx_csum
,
10156 .set_tx_csum
= tg3_set_tx_csum
,
10157 .set_sg
= ethtool_op_set_sg
,
10158 .set_tso
= tg3_set_tso
,
10159 .self_test
= tg3_self_test
,
10160 .get_strings
= tg3_get_strings
,
10161 .phys_id
= tg3_phys_id
,
10162 .get_ethtool_stats
= tg3_get_ethtool_stats
,
10163 .get_coalesce
= tg3_get_coalesce
,
10164 .set_coalesce
= tg3_set_coalesce
,
10165 .get_sset_count
= tg3_get_sset_count
,
10168 static void __devinit
tg3_get_eeprom_size(struct tg3
*tp
)
10170 u32 cursize
, val
, magic
;
10172 tp
->nvram_size
= EEPROM_CHIP_SIZE
;
10174 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
10177 if ((magic
!= TG3_EEPROM_MAGIC
) &&
10178 ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) != TG3_EEPROM_MAGIC_FW
) &&
10179 ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) != TG3_EEPROM_MAGIC_HW
))
10183 * Size the chip by reading offsets at increasing powers of two.
10184 * When we encounter our validation signature, we know the addressing
10185 * has wrapped around, and thus have our chip size.
10189 while (cursize
< tp
->nvram_size
) {
10190 if (tg3_nvram_read(tp
, cursize
, &val
) != 0)
10199 tp
->nvram_size
= cursize
;
10202 static void __devinit
tg3_get_nvram_size(struct tg3
*tp
)
10206 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
10207 tg3_nvram_read(tp
, 0, &val
) != 0)
10210 /* Selfboot format */
10211 if (val
!= TG3_EEPROM_MAGIC
) {
10212 tg3_get_eeprom_size(tp
);
10216 if (tg3_nvram_read(tp
, 0xf0, &val
) == 0) {
10218 /* This is confusing. We want to operate on the
10219 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10220 * call will read from NVRAM and byteswap the data
10221 * according to the byteswapping settings for all
10222 * other register accesses. This ensures the data we
10223 * want will always reside in the lower 16-bits.
10224 * However, the data in NVRAM is in LE format, which
10225 * means the data from the NVRAM read will always be
10226 * opposite the endianness of the CPU. The 16-bit
10227 * byteswap then brings the data to CPU endianness.
10229 tp
->nvram_size
= swab16((u16
)(val
& 0x0000ffff)) * 1024;
10233 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
10236 static void __devinit
tg3_get_nvram_info(struct tg3
*tp
)
10240 nvcfg1
= tr32(NVRAM_CFG1
);
10241 if (nvcfg1
& NVRAM_CFG1_FLASHIF_ENAB
) {
10242 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10245 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
10246 tw32(NVRAM_CFG1
, nvcfg1
);
10249 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) ||
10250 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
10251 switch (nvcfg1
& NVRAM_CFG1_VENDOR_MASK
) {
10252 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED
:
10253 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10254 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
10255 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10257 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED
:
10258 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10259 tp
->nvram_pagesize
= ATMEL_AT25F512_PAGE_SIZE
;
10261 case FLASH_VENDOR_ATMEL_EEPROM
:
10262 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10263 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
10264 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10266 case FLASH_VENDOR_ST
:
10267 tp
->nvram_jedecnum
= JEDEC_ST
;
10268 tp
->nvram_pagesize
= ST_M45PEX0_PAGE_SIZE
;
10269 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10271 case FLASH_VENDOR_SAIFUN
:
10272 tp
->nvram_jedecnum
= JEDEC_SAIFUN
;
10273 tp
->nvram_pagesize
= SAIFUN_SA25F0XX_PAGE_SIZE
;
10275 case FLASH_VENDOR_SST_SMALL
:
10276 case FLASH_VENDOR_SST_LARGE
:
10277 tp
->nvram_jedecnum
= JEDEC_SST
;
10278 tp
->nvram_pagesize
= SST_25VF0X0_PAGE_SIZE
;
10283 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10284 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
10285 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10289 static void __devinit
tg3_get_5752_nvram_info(struct tg3
*tp
)
10293 nvcfg1
= tr32(NVRAM_CFG1
);
10295 /* NVRAM protection for TPM */
10296 if (nvcfg1
& (1 << 27))
10297 tp
->tg3_flags2
|= TG3_FLG2_PROTECTED_NVRAM
;
10299 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
10300 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ
:
10301 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ
:
10302 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10303 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10305 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
10306 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10307 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10308 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10310 case FLASH_5752VENDOR_ST_M45PE10
:
10311 case FLASH_5752VENDOR_ST_M45PE20
:
10312 case FLASH_5752VENDOR_ST_M45PE40
:
10313 tp
->nvram_jedecnum
= JEDEC_ST
;
10314 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10315 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10319 if (tp
->tg3_flags2
& TG3_FLG2_FLASH
) {
10320 switch (nvcfg1
& NVRAM_CFG1_5752PAGE_SIZE_MASK
) {
10321 case FLASH_5752PAGE_SIZE_256
:
10322 tp
->nvram_pagesize
= 256;
10324 case FLASH_5752PAGE_SIZE_512
:
10325 tp
->nvram_pagesize
= 512;
10327 case FLASH_5752PAGE_SIZE_1K
:
10328 tp
->nvram_pagesize
= 1024;
10330 case FLASH_5752PAGE_SIZE_2K
:
10331 tp
->nvram_pagesize
= 2048;
10333 case FLASH_5752PAGE_SIZE_4K
:
10334 tp
->nvram_pagesize
= 4096;
10336 case FLASH_5752PAGE_SIZE_264
:
10337 tp
->nvram_pagesize
= 264;
10342 /* For eeprom, set pagesize to maximum eeprom size */
10343 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
10345 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
10346 tw32(NVRAM_CFG1
, nvcfg1
);
10350 static void __devinit
tg3_get_5755_nvram_info(struct tg3
*tp
)
10352 u32 nvcfg1
, protect
= 0;
10354 nvcfg1
= tr32(NVRAM_CFG1
);
10356 /* NVRAM protection for TPM */
10357 if (nvcfg1
& (1 << 27)) {
10358 tp
->tg3_flags2
|= TG3_FLG2_PROTECTED_NVRAM
;
10362 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
10364 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
10365 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
10366 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
10367 case FLASH_5755VENDOR_ATMEL_FLASH_5
:
10368 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10369 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10370 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10371 tp
->nvram_pagesize
= 264;
10372 if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_1
||
10373 nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_5
)
10374 tp
->nvram_size
= (protect
? 0x3e200 :
10375 TG3_NVRAM_SIZE_512KB
);
10376 else if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_2
)
10377 tp
->nvram_size
= (protect
? 0x1f200 :
10378 TG3_NVRAM_SIZE_256KB
);
10380 tp
->nvram_size
= (protect
? 0x1f200 :
10381 TG3_NVRAM_SIZE_128KB
);
10383 case FLASH_5752VENDOR_ST_M45PE10
:
10384 case FLASH_5752VENDOR_ST_M45PE20
:
10385 case FLASH_5752VENDOR_ST_M45PE40
:
10386 tp
->nvram_jedecnum
= JEDEC_ST
;
10387 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10388 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10389 tp
->nvram_pagesize
= 256;
10390 if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE10
)
10391 tp
->nvram_size
= (protect
?
10392 TG3_NVRAM_SIZE_64KB
:
10393 TG3_NVRAM_SIZE_128KB
);
10394 else if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE20
)
10395 tp
->nvram_size
= (protect
?
10396 TG3_NVRAM_SIZE_64KB
:
10397 TG3_NVRAM_SIZE_256KB
);
10399 tp
->nvram_size
= (protect
?
10400 TG3_NVRAM_SIZE_128KB
:
10401 TG3_NVRAM_SIZE_512KB
);
10406 static void __devinit
tg3_get_5787_nvram_info(struct tg3
*tp
)
10410 nvcfg1
= tr32(NVRAM_CFG1
);
10412 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
10413 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ
:
10414 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
10415 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ
:
10416 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
10417 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10418 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10419 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
10421 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
10422 tw32(NVRAM_CFG1
, nvcfg1
);
10424 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
10425 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
10426 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
10427 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
10428 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10429 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10430 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10431 tp
->nvram_pagesize
= 264;
10433 case FLASH_5752VENDOR_ST_M45PE10
:
10434 case FLASH_5752VENDOR_ST_M45PE20
:
10435 case FLASH_5752VENDOR_ST_M45PE40
:
10436 tp
->nvram_jedecnum
= JEDEC_ST
;
10437 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10438 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10439 tp
->nvram_pagesize
= 256;
10444 static void __devinit
tg3_get_5761_nvram_info(struct tg3
*tp
)
10446 u32 nvcfg1
, protect
= 0;
10448 nvcfg1
= tr32(NVRAM_CFG1
);
10450 /* NVRAM protection for TPM */
10451 if (nvcfg1
& (1 << 27)) {
10452 tp
->tg3_flags2
|= TG3_FLG2_PROTECTED_NVRAM
;
10456 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
10458 case FLASH_5761VENDOR_ATMEL_ADB021D
:
10459 case FLASH_5761VENDOR_ATMEL_ADB041D
:
10460 case FLASH_5761VENDOR_ATMEL_ADB081D
:
10461 case FLASH_5761VENDOR_ATMEL_ADB161D
:
10462 case FLASH_5761VENDOR_ATMEL_MDB021D
:
10463 case FLASH_5761VENDOR_ATMEL_MDB041D
:
10464 case FLASH_5761VENDOR_ATMEL_MDB081D
:
10465 case FLASH_5761VENDOR_ATMEL_MDB161D
:
10466 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10467 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10468 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10469 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10470 tp
->nvram_pagesize
= 256;
10472 case FLASH_5761VENDOR_ST_A_M45PE20
:
10473 case FLASH_5761VENDOR_ST_A_M45PE40
:
10474 case FLASH_5761VENDOR_ST_A_M45PE80
:
10475 case FLASH_5761VENDOR_ST_A_M45PE16
:
10476 case FLASH_5761VENDOR_ST_M_M45PE20
:
10477 case FLASH_5761VENDOR_ST_M_M45PE40
:
10478 case FLASH_5761VENDOR_ST_M_M45PE80
:
10479 case FLASH_5761VENDOR_ST_M_M45PE16
:
10480 tp
->nvram_jedecnum
= JEDEC_ST
;
10481 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10482 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10483 tp
->nvram_pagesize
= 256;
10488 tp
->nvram_size
= tr32(NVRAM_ADDR_LOCKOUT
);
10491 case FLASH_5761VENDOR_ATMEL_ADB161D
:
10492 case FLASH_5761VENDOR_ATMEL_MDB161D
:
10493 case FLASH_5761VENDOR_ST_A_M45PE16
:
10494 case FLASH_5761VENDOR_ST_M_M45PE16
:
10495 tp
->nvram_size
= TG3_NVRAM_SIZE_2MB
;
10497 case FLASH_5761VENDOR_ATMEL_ADB081D
:
10498 case FLASH_5761VENDOR_ATMEL_MDB081D
:
10499 case FLASH_5761VENDOR_ST_A_M45PE80
:
10500 case FLASH_5761VENDOR_ST_M_M45PE80
:
10501 tp
->nvram_size
= TG3_NVRAM_SIZE_1MB
;
10503 case FLASH_5761VENDOR_ATMEL_ADB041D
:
10504 case FLASH_5761VENDOR_ATMEL_MDB041D
:
10505 case FLASH_5761VENDOR_ST_A_M45PE40
:
10506 case FLASH_5761VENDOR_ST_M_M45PE40
:
10507 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
10509 case FLASH_5761VENDOR_ATMEL_ADB021D
:
10510 case FLASH_5761VENDOR_ATMEL_MDB021D
:
10511 case FLASH_5761VENDOR_ST_A_M45PE20
:
10512 case FLASH_5761VENDOR_ST_M_M45PE20
:
10513 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
10519 static void __devinit
tg3_get_5906_nvram_info(struct tg3
*tp
)
10521 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10522 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10523 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
10526 static void __devinit
tg3_get_57780_nvram_info(struct tg3
*tp
)
10530 nvcfg1
= tr32(NVRAM_CFG1
);
10532 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
10533 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
10534 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
10535 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10536 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10537 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
10539 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
10540 tw32(NVRAM_CFG1
, nvcfg1
);
10542 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
10543 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
10544 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
10545 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
10546 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
10547 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
10548 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
10549 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10550 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10551 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10553 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
10554 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
10555 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
10556 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
10557 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
10559 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
10560 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
10561 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
10563 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
10564 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
10565 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
10569 case FLASH_5752VENDOR_ST_M45PE10
:
10570 case FLASH_5752VENDOR_ST_M45PE20
:
10571 case FLASH_5752VENDOR_ST_M45PE40
:
10572 tp
->nvram_jedecnum
= JEDEC_ST
;
10573 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10574 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10576 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
10577 case FLASH_5752VENDOR_ST_M45PE10
:
10578 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
10580 case FLASH_5752VENDOR_ST_M45PE20
:
10581 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
10583 case FLASH_5752VENDOR_ST_M45PE40
:
10584 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
10589 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM
;
10593 switch (nvcfg1
& NVRAM_CFG1_5752PAGE_SIZE_MASK
) {
10594 case FLASH_5752PAGE_SIZE_256
:
10595 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10596 tp
->nvram_pagesize
= 256;
10598 case FLASH_5752PAGE_SIZE_512
:
10599 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10600 tp
->nvram_pagesize
= 512;
10602 case FLASH_5752PAGE_SIZE_1K
:
10603 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10604 tp
->nvram_pagesize
= 1024;
10606 case FLASH_5752PAGE_SIZE_2K
:
10607 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10608 tp
->nvram_pagesize
= 2048;
10610 case FLASH_5752PAGE_SIZE_4K
:
10611 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10612 tp
->nvram_pagesize
= 4096;
10614 case FLASH_5752PAGE_SIZE_264
:
10615 tp
->nvram_pagesize
= 264;
10617 case FLASH_5752PAGE_SIZE_528
:
10618 tp
->nvram_pagesize
= 528;
10623 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
10624 static void __devinit
tg3_nvram_init(struct tg3
*tp
)
10626 tw32_f(GRC_EEPROM_ADDR
,
10627 (EEPROM_ADDR_FSM_RESET
|
10628 (EEPROM_DEFAULT_CLOCK_PERIOD
<<
10629 EEPROM_ADDR_CLKPERD_SHIFT
)));
10633 /* Enable seeprom accesses. */
10634 tw32_f(GRC_LOCAL_CTRL
,
10635 tr32(GRC_LOCAL_CTRL
) | GRC_LCLCTRL_AUTO_SEEPROM
);
10638 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
10639 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
10640 tp
->tg3_flags
|= TG3_FLAG_NVRAM
;
10642 if (tg3_nvram_lock(tp
)) {
10643 printk(KERN_WARNING PFX
"%s: Cannot get nvarm lock, "
10644 "tg3_nvram_init failed.\n", tp
->dev
->name
);
10647 tg3_enable_nvram_access(tp
);
10649 tp
->nvram_size
= 0;
10651 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
10652 tg3_get_5752_nvram_info(tp
);
10653 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
10654 tg3_get_5755_nvram_info(tp
);
10655 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
10656 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
10657 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
10658 tg3_get_5787_nvram_info(tp
);
10659 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
10660 tg3_get_5761_nvram_info(tp
);
10661 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
10662 tg3_get_5906_nvram_info(tp
);
10663 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
10664 tg3_get_57780_nvram_info(tp
);
10666 tg3_get_nvram_info(tp
);
10668 if (tp
->nvram_size
== 0)
10669 tg3_get_nvram_size(tp
);
10671 tg3_disable_nvram_access(tp
);
10672 tg3_nvram_unlock(tp
);
10675 tp
->tg3_flags
&= ~(TG3_FLAG_NVRAM
| TG3_FLAG_NVRAM_BUFFERED
);
10677 tg3_get_eeprom_size(tp
);
10681 static int tg3_nvram_write_block_using_eeprom(struct tg3
*tp
,
10682 u32 offset
, u32 len
, u8
*buf
)
10687 for (i
= 0; i
< len
; i
+= 4) {
10693 memcpy(&data
, buf
+ i
, 4);
10696 * The SEEPROM interface expects the data to always be opposite
10697 * the native endian format. We accomplish this by reversing
10698 * all the operations that would have been performed on the
10699 * data from a call to tg3_nvram_read_be32().
10701 tw32(GRC_EEPROM_DATA
, swab32(be32_to_cpu(data
)));
10703 val
= tr32(GRC_EEPROM_ADDR
);
10704 tw32(GRC_EEPROM_ADDR
, val
| EEPROM_ADDR_COMPLETE
);
10706 val
&= ~(EEPROM_ADDR_ADDR_MASK
| EEPROM_ADDR_DEVID_MASK
|
10708 tw32(GRC_EEPROM_ADDR
, val
|
10709 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
10710 (addr
& EEPROM_ADDR_ADDR_MASK
) |
10711 EEPROM_ADDR_START
|
10712 EEPROM_ADDR_WRITE
);
10714 for (j
= 0; j
< 1000; j
++) {
10715 val
= tr32(GRC_EEPROM_ADDR
);
10717 if (val
& EEPROM_ADDR_COMPLETE
)
10721 if (!(val
& EEPROM_ADDR_COMPLETE
)) {
10730 /* offset and length are dword aligned */
10731 static int tg3_nvram_write_block_unbuffered(struct tg3
*tp
, u32 offset
, u32 len
,
10735 u32 pagesize
= tp
->nvram_pagesize
;
10736 u32 pagemask
= pagesize
- 1;
10740 tmp
= kmalloc(pagesize
, GFP_KERNEL
);
10746 u32 phy_addr
, page_off
, size
;
10748 phy_addr
= offset
& ~pagemask
;
10750 for (j
= 0; j
< pagesize
; j
+= 4) {
10751 ret
= tg3_nvram_read_be32(tp
, phy_addr
+ j
,
10752 (__be32
*) (tmp
+ j
));
10759 page_off
= offset
& pagemask
;
10766 memcpy(tmp
+ page_off
, buf
, size
);
10768 offset
= offset
+ (pagesize
- page_off
);
10770 tg3_enable_nvram_access(tp
);
10773 * Before we can erase the flash page, we need
10774 * to issue a special "write enable" command.
10776 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
10778 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
10781 /* Erase the target page */
10782 tw32(NVRAM_ADDR
, phy_addr
);
10784 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
|
10785 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_ERASE
;
10787 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
10790 /* Issue another write enable to start the write. */
10791 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
10793 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
10796 for (j
= 0; j
< pagesize
; j
+= 4) {
10799 data
= *((__be32
*) (tmp
+ j
));
10801 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
10803 tw32(NVRAM_ADDR
, phy_addr
+ j
);
10805 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
|
10809 nvram_cmd
|= NVRAM_CMD_FIRST
;
10810 else if (j
== (pagesize
- 4))
10811 nvram_cmd
|= NVRAM_CMD_LAST
;
10813 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
10820 nvram_cmd
= NVRAM_CMD_WRDI
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
10821 tg3_nvram_exec_cmd(tp
, nvram_cmd
);
10828 /* offset and length are dword aligned */
10829 static int tg3_nvram_write_block_buffered(struct tg3
*tp
, u32 offset
, u32 len
,
10834 for (i
= 0; i
< len
; i
+= 4, offset
+= 4) {
10835 u32 page_off
, phy_addr
, nvram_cmd
;
10838 memcpy(&data
, buf
+ i
, 4);
10839 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
10841 page_off
= offset
% tp
->nvram_pagesize
;
10843 phy_addr
= tg3_nvram_phys_addr(tp
, offset
);
10845 tw32(NVRAM_ADDR
, phy_addr
);
10847 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
;
10849 if ((page_off
== 0) || (i
== 0))
10850 nvram_cmd
|= NVRAM_CMD_FIRST
;
10851 if (page_off
== (tp
->nvram_pagesize
- 4))
10852 nvram_cmd
|= NVRAM_CMD_LAST
;
10854 if (i
== (len
- 4))
10855 nvram_cmd
|= NVRAM_CMD_LAST
;
10857 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5752
&&
10858 !(tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) &&
10859 (tp
->nvram_jedecnum
== JEDEC_ST
) &&
10860 (nvram_cmd
& NVRAM_CMD_FIRST
)) {
10862 if ((ret
= tg3_nvram_exec_cmd(tp
,
10863 NVRAM_CMD_WREN
| NVRAM_CMD_GO
|
10868 if (!(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
10869 /* We always do complete word writes to eeprom. */
10870 nvram_cmd
|= (NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
);
10873 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
10879 /* offset and length are dword aligned */
10880 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
)
10884 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
10885 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
&
10886 ~GRC_LCLCTRL_GPIO_OUTPUT1
);
10890 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
)) {
10891 ret
= tg3_nvram_write_block_using_eeprom(tp
, offset
, len
, buf
);
10896 ret
= tg3_nvram_lock(tp
);
10900 tg3_enable_nvram_access(tp
);
10901 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
10902 !(tp
->tg3_flags2
& TG3_FLG2_PROTECTED_NVRAM
))
10903 tw32(NVRAM_WRITE1
, 0x406);
10905 grc_mode
= tr32(GRC_MODE
);
10906 tw32(GRC_MODE
, grc_mode
| GRC_MODE_NVRAM_WR_ENABLE
);
10908 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) ||
10909 !(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
10911 ret
= tg3_nvram_write_block_buffered(tp
, offset
, len
,
10915 ret
= tg3_nvram_write_block_unbuffered(tp
, offset
, len
,
10919 grc_mode
= tr32(GRC_MODE
);
10920 tw32(GRC_MODE
, grc_mode
& ~GRC_MODE_NVRAM_WR_ENABLE
);
10922 tg3_disable_nvram_access(tp
);
10923 tg3_nvram_unlock(tp
);
10926 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
10927 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
10934 struct subsys_tbl_ent
{
10935 u16 subsys_vendor
, subsys_devid
;
10939 static struct subsys_tbl_ent subsys_id_to_phy_id
[] = {
10940 /* Broadcom boards. */
10941 { PCI_VENDOR_ID_BROADCOM
, 0x1644, PHY_ID_BCM5401
}, /* BCM95700A6 */
10942 { PCI_VENDOR_ID_BROADCOM
, 0x0001, PHY_ID_BCM5701
}, /* BCM95701A5 */
10943 { PCI_VENDOR_ID_BROADCOM
, 0x0002, PHY_ID_BCM8002
}, /* BCM95700T6 */
10944 { PCI_VENDOR_ID_BROADCOM
, 0x0003, 0 }, /* BCM95700A9 */
10945 { PCI_VENDOR_ID_BROADCOM
, 0x0005, PHY_ID_BCM5701
}, /* BCM95701T1 */
10946 { PCI_VENDOR_ID_BROADCOM
, 0x0006, PHY_ID_BCM5701
}, /* BCM95701T8 */
10947 { PCI_VENDOR_ID_BROADCOM
, 0x0007, 0 }, /* BCM95701A7 */
10948 { PCI_VENDOR_ID_BROADCOM
, 0x0008, PHY_ID_BCM5701
}, /* BCM95701A10 */
10949 { PCI_VENDOR_ID_BROADCOM
, 0x8008, PHY_ID_BCM5701
}, /* BCM95701A12 */
10950 { PCI_VENDOR_ID_BROADCOM
, 0x0009, PHY_ID_BCM5703
}, /* BCM95703Ax1 */
10951 { PCI_VENDOR_ID_BROADCOM
, 0x8009, PHY_ID_BCM5703
}, /* BCM95703Ax2 */
10954 { PCI_VENDOR_ID_3COM
, 0x1000, PHY_ID_BCM5401
}, /* 3C996T */
10955 { PCI_VENDOR_ID_3COM
, 0x1006, PHY_ID_BCM5701
}, /* 3C996BT */
10956 { PCI_VENDOR_ID_3COM
, 0x1004, 0 }, /* 3C996SX */
10957 { PCI_VENDOR_ID_3COM
, 0x1007, PHY_ID_BCM5701
}, /* 3C1000T */
10958 { PCI_VENDOR_ID_3COM
, 0x1008, PHY_ID_BCM5701
}, /* 3C940BR01 */
10961 { PCI_VENDOR_ID_DELL
, 0x00d1, PHY_ID_BCM5401
}, /* VIPER */
10962 { PCI_VENDOR_ID_DELL
, 0x0106, PHY_ID_BCM5401
}, /* JAGUAR */
10963 { PCI_VENDOR_ID_DELL
, 0x0109, PHY_ID_BCM5411
}, /* MERLOT */
10964 { PCI_VENDOR_ID_DELL
, 0x010a, PHY_ID_BCM5411
}, /* SLIM_MERLOT */
10966 /* Compaq boards. */
10967 { PCI_VENDOR_ID_COMPAQ
, 0x007c, PHY_ID_BCM5701
}, /* BANSHEE */
10968 { PCI_VENDOR_ID_COMPAQ
, 0x009a, PHY_ID_BCM5701
}, /* BANSHEE_2 */
10969 { PCI_VENDOR_ID_COMPAQ
, 0x007d, 0 }, /* CHANGELING */
10970 { PCI_VENDOR_ID_COMPAQ
, 0x0085, PHY_ID_BCM5701
}, /* NC7780 */
10971 { PCI_VENDOR_ID_COMPAQ
, 0x0099, PHY_ID_BCM5701
}, /* NC7780_2 */
10974 { PCI_VENDOR_ID_IBM
, 0x0281, 0 } /* IBM??? */
10977 static inline struct subsys_tbl_ent
*lookup_by_subsys(struct tg3
*tp
)
10981 for (i
= 0; i
< ARRAY_SIZE(subsys_id_to_phy_id
); i
++) {
10982 if ((subsys_id_to_phy_id
[i
].subsys_vendor
==
10983 tp
->pdev
->subsystem_vendor
) &&
10984 (subsys_id_to_phy_id
[i
].subsys_devid
==
10985 tp
->pdev
->subsystem_device
))
10986 return &subsys_id_to_phy_id
[i
];
10991 static void __devinit
tg3_get_eeprom_hw_cfg(struct tg3
*tp
)
10996 /* On some early chips the SRAM cannot be accessed in D3hot state,
10997 * so need make sure we're in D0.
10999 pci_read_config_word(tp
->pdev
, tp
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
11000 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
11001 pci_write_config_word(tp
->pdev
, tp
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
11004 /* Make sure register accesses (indirect or otherwise)
11005 * will function correctly.
11007 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
11008 tp
->misc_host_ctrl
);
11010 /* The memory arbiter has to be enabled in order for SRAM accesses
11011 * to succeed. Normally on powerup the tg3 chip firmware will make
11012 * sure it is enabled, but other entities such as system netboot
11013 * code might disable it.
11015 val
= tr32(MEMARB_MODE
);
11016 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
11018 tp
->phy_id
= PHY_ID_INVALID
;
11019 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
11021 /* Assume an onboard device and WOL capable by default. */
11022 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
| TG3_FLAG_WOL_CAP
;
11024 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
11025 if (!(tr32(PCIE_TRANSACTION_CFG
) & PCIE_TRANS_CFG_LOM
)) {
11026 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
11027 tp
->tg3_flags2
|= TG3_FLG2_IS_NIC
;
11029 val
= tr32(VCPU_CFGSHDW
);
11030 if (val
& VCPU_CFGSHDW_ASPM_DBNC
)
11031 tp
->tg3_flags
|= TG3_FLAG_ASPM_WORKAROUND
;
11032 if ((val
& VCPU_CFGSHDW_WOL_ENABLE
) &&
11033 (val
& VCPU_CFGSHDW_WOL_MAGPKT
))
11034 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
11038 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
11039 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
11040 u32 nic_cfg
, led_cfg
;
11041 u32 nic_phy_id
, ver
, cfg2
= 0, cfg4
= 0, eeprom_phy_id
;
11042 int eeprom_phy_serdes
= 0;
11044 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
11045 tp
->nic_sram_data_cfg
= nic_cfg
;
11047 tg3_read_mem(tp
, NIC_SRAM_DATA_VER
, &ver
);
11048 ver
>>= NIC_SRAM_DATA_VER_SHIFT
;
11049 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
) &&
11050 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) &&
11051 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5703
) &&
11052 (ver
> 0) && (ver
< 0x100))
11053 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_2
, &cfg2
);
11055 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
11056 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_4
, &cfg4
);
11058 if ((nic_cfg
& NIC_SRAM_DATA_CFG_PHY_TYPE_MASK
) ==
11059 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER
)
11060 eeprom_phy_serdes
= 1;
11062 tg3_read_mem(tp
, NIC_SRAM_DATA_PHY_ID
, &nic_phy_id
);
11063 if (nic_phy_id
!= 0) {
11064 u32 id1
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID1_MASK
;
11065 u32 id2
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID2_MASK
;
11067 eeprom_phy_id
= (id1
>> 16) << 10;
11068 eeprom_phy_id
|= (id2
& 0xfc00) << 16;
11069 eeprom_phy_id
|= (id2
& 0x03ff) << 0;
11073 tp
->phy_id
= eeprom_phy_id
;
11074 if (eeprom_phy_serdes
) {
11075 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
11076 tp
->tg3_flags2
|= TG3_FLG2_MII_SERDES
;
11078 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
11081 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
11082 led_cfg
= cfg2
& (NIC_SRAM_DATA_CFG_LED_MODE_MASK
|
11083 SHASTA_EXT_LED_MODE_MASK
);
11085 led_cfg
= nic_cfg
& NIC_SRAM_DATA_CFG_LED_MODE_MASK
;
11089 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1
:
11090 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
11093 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2
:
11094 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
11097 case NIC_SRAM_DATA_CFG_LED_MODE_MAC
:
11098 tp
->led_ctrl
= LED_CTRL_MODE_MAC
;
11100 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11101 * read on some older 5700/5701 bootcode.
11103 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
11105 GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
11107 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
11111 case SHASTA_EXT_LED_SHARED
:
11112 tp
->led_ctrl
= LED_CTRL_MODE_SHARED
;
11113 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
&&
11114 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A1
)
11115 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
11116 LED_CTRL_MODE_PHY_2
);
11119 case SHASTA_EXT_LED_MAC
:
11120 tp
->led_ctrl
= LED_CTRL_MODE_SHASTA_MAC
;
11123 case SHASTA_EXT_LED_COMBO
:
11124 tp
->led_ctrl
= LED_CTRL_MODE_COMBO
;
11125 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
)
11126 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
11127 LED_CTRL_MODE_PHY_2
);
11132 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
11133 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) &&
11134 tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
)
11135 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
11137 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
)
11138 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
11140 if (nic_cfg
& NIC_SRAM_DATA_CFG_EEPROM_WP
) {
11141 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
;
11142 if ((tp
->pdev
->subsystem_vendor
==
11143 PCI_VENDOR_ID_ARIMA
) &&
11144 (tp
->pdev
->subsystem_device
== 0x205a ||
11145 tp
->pdev
->subsystem_device
== 0x2063))
11146 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
11148 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
11149 tp
->tg3_flags2
|= TG3_FLG2_IS_NIC
;
11152 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
11153 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
11154 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
11155 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
11158 if ((nic_cfg
& NIC_SRAM_DATA_CFG_APE_ENABLE
) &&
11159 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
11160 tp
->tg3_flags3
|= TG3_FLG3_ENABLE_APE
;
11162 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
&&
11163 !(nic_cfg
& NIC_SRAM_DATA_CFG_FIBER_WOL
))
11164 tp
->tg3_flags
&= ~TG3_FLAG_WOL_CAP
;
11166 if ((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) &&
11167 (nic_cfg
& NIC_SRAM_DATA_CFG_WOL_ENABLE
))
11168 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
11170 if (cfg2
& (1 << 17))
11171 tp
->tg3_flags2
|= TG3_FLG2_CAPACITIVE_COUPLING
;
11173 /* serdes signal pre-emphasis in register 0x590 set by */
11174 /* bootcode if bit 18 is set */
11175 if (cfg2
& (1 << 18))
11176 tp
->tg3_flags2
|= TG3_FLG2_SERDES_PREEMPHASIS
;
11178 if (((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
11179 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
)) &&
11180 (cfg2
& NIC_SRAM_DATA_CFG_2_APD_EN
))
11181 tp
->tg3_flags3
|= TG3_FLG3_PHY_ENABLE_APD
;
11183 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
11186 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_3
, &cfg3
);
11187 if (cfg3
& NIC_SRAM_ASPM_DEBOUNCE
)
11188 tp
->tg3_flags
|= TG3_FLAG_ASPM_WORKAROUND
;
11191 if (cfg4
& NIC_SRAM_RGMII_STD_IBND_DISABLE
)
11192 tp
->tg3_flags3
|= TG3_FLG3_RGMII_STD_IBND_DISABLE
;
11193 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_RX_EN
)
11194 tp
->tg3_flags3
|= TG3_FLG3_RGMII_EXT_IBND_RX_EN
;
11195 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_TX_EN
)
11196 tp
->tg3_flags3
|= TG3_FLG3_RGMII_EXT_IBND_TX_EN
;
11199 device_init_wakeup(&tp
->pdev
->dev
, tp
->tg3_flags
& TG3_FLAG_WOL_CAP
);
11200 device_set_wakeup_enable(&tp
->pdev
->dev
,
11201 tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
11204 static int __devinit
tg3_issue_otp_command(struct tg3
*tp
, u32 cmd
)
11209 tw32(OTP_CTRL
, cmd
| OTP_CTRL_OTP_CMD_START
);
11210 tw32(OTP_CTRL
, cmd
);
11212 /* Wait for up to 1 ms for command to execute. */
11213 for (i
= 0; i
< 100; i
++) {
11214 val
= tr32(OTP_STATUS
);
11215 if (val
& OTP_STATUS_CMD_DONE
)
11220 return (val
& OTP_STATUS_CMD_DONE
) ? 0 : -EBUSY
;
11223 /* Read the gphy configuration from the OTP region of the chip. The gphy
11224 * configuration is a 32-bit value that straddles the alignment boundary.
11225 * We do two 32-bit reads and then shift and merge the results.
11227 static u32 __devinit
tg3_read_otp_phycfg(struct tg3
*tp
)
11229 u32 bhalf_otp
, thalf_otp
;
11231 tw32(OTP_MODE
, OTP_MODE_OTP_THRU_GRC
);
11233 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_INIT
))
11236 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC1
);
11238 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
11241 thalf_otp
= tr32(OTP_READ_DATA
);
11243 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC2
);
11245 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
11248 bhalf_otp
= tr32(OTP_READ_DATA
);
11250 return ((thalf_otp
& 0x0000ffff) << 16) | (bhalf_otp
>> 16);
11253 static int __devinit
tg3_phy_probe(struct tg3
*tp
)
11255 u32 hw_phy_id_1
, hw_phy_id_2
;
11256 u32 hw_phy_id
, hw_phy_id_masked
;
11259 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)
11260 return tg3_phy_init(tp
);
11262 /* Reading the PHY ID register can conflict with ASF
11263 * firmware access to the PHY hardware.
11266 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
11267 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
11268 hw_phy_id
= hw_phy_id_masked
= PHY_ID_INVALID
;
11270 /* Now read the physical PHY_ID from the chip and verify
11271 * that it is sane. If it doesn't look good, we fall back
11272 * to either the hard-coded table based PHY_ID and failing
11273 * that the value found in the eeprom area.
11275 err
|= tg3_readphy(tp
, MII_PHYSID1
, &hw_phy_id_1
);
11276 err
|= tg3_readphy(tp
, MII_PHYSID2
, &hw_phy_id_2
);
11278 hw_phy_id
= (hw_phy_id_1
& 0xffff) << 10;
11279 hw_phy_id
|= (hw_phy_id_2
& 0xfc00) << 16;
11280 hw_phy_id
|= (hw_phy_id_2
& 0x03ff) << 0;
11282 hw_phy_id_masked
= hw_phy_id
& PHY_ID_MASK
;
11285 if (!err
&& KNOWN_PHY_ID(hw_phy_id_masked
)) {
11286 tp
->phy_id
= hw_phy_id
;
11287 if (hw_phy_id_masked
== PHY_ID_BCM8002
)
11288 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
11290 tp
->tg3_flags2
&= ~TG3_FLG2_PHY_SERDES
;
11292 if (tp
->phy_id
!= PHY_ID_INVALID
) {
11293 /* Do nothing, phy ID already set up in
11294 * tg3_get_eeprom_hw_cfg().
11297 struct subsys_tbl_ent
*p
;
11299 /* No eeprom signature? Try the hardcoded
11300 * subsys device table.
11302 p
= lookup_by_subsys(tp
);
11306 tp
->phy_id
= p
->phy_id
;
11308 tp
->phy_id
== PHY_ID_BCM8002
)
11309 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
11313 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
) &&
11314 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) &&
11315 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
11316 u32 bmsr
, adv_reg
, tg3_ctrl
, mask
;
11318 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
11319 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
11320 (bmsr
& BMSR_LSTATUS
))
11321 goto skip_phy_reset
;
11323 err
= tg3_phy_reset(tp
);
11327 adv_reg
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
11328 ADVERTISE_100HALF
| ADVERTISE_100FULL
|
11329 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
11331 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
11332 tg3_ctrl
= (MII_TG3_CTRL_ADV_1000_HALF
|
11333 MII_TG3_CTRL_ADV_1000_FULL
);
11334 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
11335 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
11336 tg3_ctrl
|= (MII_TG3_CTRL_AS_MASTER
|
11337 MII_TG3_CTRL_ENABLE_AS_MASTER
);
11340 mask
= (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
11341 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
11342 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
);
11343 if (!tg3_copper_is_advertising_all(tp
, mask
)) {
11344 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
11346 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
11347 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
11349 tg3_writephy(tp
, MII_BMCR
,
11350 BMCR_ANENABLE
| BMCR_ANRESTART
);
11352 tg3_phy_set_wirespeed(tp
);
11354 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
11355 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
11356 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
11360 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
) {
11361 err
= tg3_init_5401phy_dsp(tp
);
11366 if (!err
&& ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
)) {
11367 err
= tg3_init_5401phy_dsp(tp
);
11370 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)
11371 tp
->link_config
.advertising
=
11372 (ADVERTISED_1000baseT_Half
|
11373 ADVERTISED_1000baseT_Full
|
11374 ADVERTISED_Autoneg
|
11376 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
11377 tp
->link_config
.advertising
&=
11378 ~(ADVERTISED_1000baseT_Half
|
11379 ADVERTISED_1000baseT_Full
);
11384 static void __devinit
tg3_read_partno(struct tg3
*tp
)
11386 unsigned char vpd_data
[256]; /* in little-endian format */
11390 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
11391 tg3_nvram_read(tp
, 0x0, &magic
))
11392 goto out_not_found
;
11394 if (magic
== TG3_EEPROM_MAGIC
) {
11395 for (i
= 0; i
< 256; i
+= 4) {
11398 /* The data is in little-endian format in NVRAM.
11399 * Use the big-endian read routines to preserve
11400 * the byte order as it exists in NVRAM.
11402 if (tg3_nvram_read_be32(tp
, 0x100 + i
, &tmp
))
11403 goto out_not_found
;
11405 memcpy(&vpd_data
[i
], &tmp
, sizeof(tmp
));
11410 vpd_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_VPD
);
11411 for (i
= 0; i
< 256; i
+= 4) {
11416 pci_write_config_word(tp
->pdev
, vpd_cap
+ PCI_VPD_ADDR
,
11418 while (j
++ < 100) {
11419 pci_read_config_word(tp
->pdev
, vpd_cap
+
11420 PCI_VPD_ADDR
, &tmp16
);
11421 if (tmp16
& 0x8000)
11425 if (!(tmp16
& 0x8000))
11426 goto out_not_found
;
11428 pci_read_config_dword(tp
->pdev
, vpd_cap
+ PCI_VPD_DATA
,
11430 v
= cpu_to_le32(tmp
);
11431 memcpy(&vpd_data
[i
], &v
, sizeof(v
));
11435 /* Now parse and find the part number. */
11436 for (i
= 0; i
< 254; ) {
11437 unsigned char val
= vpd_data
[i
];
11438 unsigned int block_end
;
11440 if (val
== 0x82 || val
== 0x91) {
11443 (vpd_data
[i
+ 2] << 8)));
11448 goto out_not_found
;
11450 block_end
= (i
+ 3 +
11452 (vpd_data
[i
+ 2] << 8)));
11455 if (block_end
> 256)
11456 goto out_not_found
;
11458 while (i
< (block_end
- 2)) {
11459 if (vpd_data
[i
+ 0] == 'P' &&
11460 vpd_data
[i
+ 1] == 'N') {
11461 int partno_len
= vpd_data
[i
+ 2];
11464 if (partno_len
> 24 || (partno_len
+ i
) > 256)
11465 goto out_not_found
;
11467 memcpy(tp
->board_part_number
,
11468 &vpd_data
[i
], partno_len
);
11473 i
+= 3 + vpd_data
[i
+ 2];
11476 /* Part number not found. */
11477 goto out_not_found
;
11481 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
11482 strcpy(tp
->board_part_number
, "BCM95906");
11483 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
11484 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57780
)
11485 strcpy(tp
->board_part_number
, "BCM57780");
11486 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
11487 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57760
)
11488 strcpy(tp
->board_part_number
, "BCM57760");
11489 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
11490 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57790
)
11491 strcpy(tp
->board_part_number
, "BCM57790");
11493 strcpy(tp
->board_part_number
, "none");
11496 static int __devinit
tg3_fw_img_is_valid(struct tg3
*tp
, u32 offset
)
11500 if (tg3_nvram_read(tp
, offset
, &val
) ||
11501 (val
& 0xfc000000) != 0x0c000000 ||
11502 tg3_nvram_read(tp
, offset
+ 4, &val
) ||
11509 static void __devinit
tg3_read_bc_ver(struct tg3
*tp
)
11511 u32 val
, offset
, start
, ver_offset
;
11513 bool newver
= false;
11515 if (tg3_nvram_read(tp
, 0xc, &offset
) ||
11516 tg3_nvram_read(tp
, 0x4, &start
))
11519 offset
= tg3_nvram_logical_addr(tp
, offset
);
11521 if (tg3_nvram_read(tp
, offset
, &val
))
11524 if ((val
& 0xfc000000) == 0x0c000000) {
11525 if (tg3_nvram_read(tp
, offset
+ 4, &val
))
11533 if (tg3_nvram_read(tp
, offset
+ 8, &ver_offset
))
11536 offset
= offset
+ ver_offset
- start
;
11537 for (i
= 0; i
< 16; i
+= 4) {
11539 if (tg3_nvram_read_be32(tp
, offset
+ i
, &v
))
11542 memcpy(tp
->fw_ver
+ i
, &v
, sizeof(v
));
11547 if (tg3_nvram_read(tp
, TG3_NVM_PTREV_BCVER
, &ver_offset
))
11550 major
= (ver_offset
& TG3_NVM_BCVER_MAJMSK
) >>
11551 TG3_NVM_BCVER_MAJSFT
;
11552 minor
= ver_offset
& TG3_NVM_BCVER_MINMSK
;
11553 snprintf(&tp
->fw_ver
[0], 32, "v%d.%02d", major
, minor
);
11557 static void __devinit
tg3_read_hwsb_ver(struct tg3
*tp
)
11559 u32 val
, major
, minor
;
11561 /* Use native endian representation */
11562 if (tg3_nvram_read(tp
, TG3_NVM_HWSB_CFG1
, &val
))
11565 major
= (val
& TG3_NVM_HWSB_CFG1_MAJMSK
) >>
11566 TG3_NVM_HWSB_CFG1_MAJSFT
;
11567 minor
= (val
& TG3_NVM_HWSB_CFG1_MINMSK
) >>
11568 TG3_NVM_HWSB_CFG1_MINSFT
;
11570 snprintf(&tp
->fw_ver
[0], 32, "sb v%d.%02d", major
, minor
);
11573 static void __devinit
tg3_read_sb_ver(struct tg3
*tp
, u32 val
)
11575 u32 offset
, major
, minor
, build
;
11577 tp
->fw_ver
[0] = 's';
11578 tp
->fw_ver
[1] = 'b';
11579 tp
->fw_ver
[2] = '\0';
11581 if ((val
& TG3_EEPROM_SB_FORMAT_MASK
) != TG3_EEPROM_SB_FORMAT_1
)
11584 switch (val
& TG3_EEPROM_SB_REVISION_MASK
) {
11585 case TG3_EEPROM_SB_REVISION_0
:
11586 offset
= TG3_EEPROM_SB_F1R0_EDH_OFF
;
11588 case TG3_EEPROM_SB_REVISION_2
:
11589 offset
= TG3_EEPROM_SB_F1R2_EDH_OFF
;
11591 case TG3_EEPROM_SB_REVISION_3
:
11592 offset
= TG3_EEPROM_SB_F1R3_EDH_OFF
;
11598 if (tg3_nvram_read(tp
, offset
, &val
))
11601 build
= (val
& TG3_EEPROM_SB_EDH_BLD_MASK
) >>
11602 TG3_EEPROM_SB_EDH_BLD_SHFT
;
11603 major
= (val
& TG3_EEPROM_SB_EDH_MAJ_MASK
) >>
11604 TG3_EEPROM_SB_EDH_MAJ_SHFT
;
11605 minor
= val
& TG3_EEPROM_SB_EDH_MIN_MASK
;
11607 if (minor
> 99 || build
> 26)
11610 snprintf(&tp
->fw_ver
[2], 30, " v%d.%02d", major
, minor
);
11613 tp
->fw_ver
[8] = 'a' + build
- 1;
11614 tp
->fw_ver
[9] = '\0';
11618 static void __devinit
tg3_read_mgmtfw_ver(struct tg3
*tp
)
11620 u32 val
, offset
, start
;
11623 for (offset
= TG3_NVM_DIR_START
;
11624 offset
< TG3_NVM_DIR_END
;
11625 offset
+= TG3_NVM_DIRENT_SIZE
) {
11626 if (tg3_nvram_read(tp
, offset
, &val
))
11629 if ((val
>> TG3_NVM_DIRTYPE_SHIFT
) == TG3_NVM_DIRTYPE_ASFINI
)
11633 if (offset
== TG3_NVM_DIR_END
)
11636 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
11637 start
= 0x08000000;
11638 else if (tg3_nvram_read(tp
, offset
- 4, &start
))
11641 if (tg3_nvram_read(tp
, offset
+ 4, &offset
) ||
11642 !tg3_fw_img_is_valid(tp
, offset
) ||
11643 tg3_nvram_read(tp
, offset
+ 8, &val
))
11646 offset
+= val
- start
;
11648 vlen
= strlen(tp
->fw_ver
);
11650 tp
->fw_ver
[vlen
++] = ',';
11651 tp
->fw_ver
[vlen
++] = ' ';
11653 for (i
= 0; i
< 4; i
++) {
11655 if (tg3_nvram_read_be32(tp
, offset
, &v
))
11658 offset
+= sizeof(v
);
11660 if (vlen
> TG3_VER_SIZE
- sizeof(v
)) {
11661 memcpy(&tp
->fw_ver
[vlen
], &v
, TG3_VER_SIZE
- vlen
);
11665 memcpy(&tp
->fw_ver
[vlen
], &v
, sizeof(v
));
11670 static void __devinit
tg3_read_dash_ver(struct tg3
*tp
)
11675 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) ||
11676 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
11679 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
11680 if (apedata
!= APE_SEG_SIG_MAGIC
)
11683 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
11684 if (!(apedata
& APE_FW_STATUS_READY
))
11687 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_VERSION
);
11689 vlen
= strlen(tp
->fw_ver
);
11691 snprintf(&tp
->fw_ver
[vlen
], TG3_VER_SIZE
- vlen
, " DASH v%d.%d.%d.%d",
11692 (apedata
& APE_FW_VERSION_MAJMSK
) >> APE_FW_VERSION_MAJSFT
,
11693 (apedata
& APE_FW_VERSION_MINMSK
) >> APE_FW_VERSION_MINSFT
,
11694 (apedata
& APE_FW_VERSION_REVMSK
) >> APE_FW_VERSION_REVSFT
,
11695 (apedata
& APE_FW_VERSION_BLDMSK
));
11698 static void __devinit
tg3_read_fw_ver(struct tg3
*tp
)
11702 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) {
11703 tp
->fw_ver
[0] = 's';
11704 tp
->fw_ver
[1] = 'b';
11705 tp
->fw_ver
[2] = '\0';
11710 if (tg3_nvram_read(tp
, 0, &val
))
11713 if (val
== TG3_EEPROM_MAGIC
)
11714 tg3_read_bc_ver(tp
);
11715 else if ((val
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
)
11716 tg3_read_sb_ver(tp
, val
);
11717 else if ((val
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
11718 tg3_read_hwsb_ver(tp
);
11722 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
11723 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
11726 tg3_read_mgmtfw_ver(tp
);
11728 tp
->fw_ver
[TG3_VER_SIZE
- 1] = 0;
11731 static struct pci_dev
* __devinit
tg3_find_peer(struct tg3
*);
11733 static int __devinit
tg3_get_invariants(struct tg3
*tp
)
11735 static struct pci_device_id write_reorder_chipsets
[] = {
11736 { PCI_DEVICE(PCI_VENDOR_ID_AMD
,
11737 PCI_DEVICE_ID_AMD_FE_GATE_700C
) },
11738 { PCI_DEVICE(PCI_VENDOR_ID_AMD
,
11739 PCI_DEVICE_ID_AMD_8131_BRIDGE
) },
11740 { PCI_DEVICE(PCI_VENDOR_ID_VIA
,
11741 PCI_DEVICE_ID_VIA_8385_0
) },
11745 u32 pci_state_reg
, grc_misc_cfg
;
11750 /* Force memory write invalidate off. If we leave it on,
11751 * then on 5700_BX chips we have to enable a workaround.
11752 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11753 * to match the cacheline size. The Broadcom driver have this
11754 * workaround but turns MWI off all the times so never uses
11755 * it. This seems to suggest that the workaround is insufficient.
11757 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
11758 pci_cmd
&= ~PCI_COMMAND_INVALIDATE
;
11759 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
11761 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11762 * has the register indirect write enable bit set before
11763 * we try to access any of the MMIO registers. It is also
11764 * critical that the PCI-X hw workaround situation is decided
11765 * before that as well.
11767 pci_read_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
11770 tp
->pci_chip_rev_id
= (misc_ctrl_reg
>>
11771 MISC_HOST_CTRL_CHIPREV_SHIFT
);
11772 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_USE_PROD_ID_REG
) {
11773 u32 prod_id_asic_rev
;
11775 pci_read_config_dword(tp
->pdev
, TG3PCI_PRODID_ASICREV
,
11776 &prod_id_asic_rev
);
11777 tp
->pci_chip_rev_id
= prod_id_asic_rev
;
11780 /* Wrong chip ID in 5752 A0. This code can be removed later
11781 * as A0 is not in production.
11783 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5752_A0_HW
)
11784 tp
->pci_chip_rev_id
= CHIPREV_ID_5752_A0
;
11786 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11787 * we need to disable memory and use config. cycles
11788 * only to access all registers. The 5702/03 chips
11789 * can mistakenly decode the special cycles from the
11790 * ICH chipsets as memory write cycles, causing corruption
11791 * of register and memory space. Only certain ICH bridges
11792 * will drive special cycles with non-zero data during the
11793 * address phase which can fall within the 5703's address
11794 * range. This is not an ICH bug as the PCI spec allows
11795 * non-zero address during special cycles. However, only
11796 * these ICH bridges are known to drive non-zero addresses
11797 * during special cycles.
11799 * Since special cycles do not cross PCI bridges, we only
11800 * enable this workaround if the 5703 is on the secondary
11801 * bus of these ICH bridges.
11803 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
) ||
11804 (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A2
)) {
11805 static struct tg3_dev_id
{
11809 } ich_chipsets
[] = {
11810 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_8
,
11812 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_8
,
11814 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_11
,
11816 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_6
,
11820 struct tg3_dev_id
*pci_id
= &ich_chipsets
[0];
11821 struct pci_dev
*bridge
= NULL
;
11823 while (pci_id
->vendor
!= 0) {
11824 bridge
= pci_get_device(pci_id
->vendor
, pci_id
->device
,
11830 if (pci_id
->rev
!= PCI_ANY_ID
) {
11831 if (bridge
->revision
> pci_id
->rev
)
11834 if (bridge
->subordinate
&&
11835 (bridge
->subordinate
->number
==
11836 tp
->pdev
->bus
->number
)) {
11838 tp
->tg3_flags2
|= TG3_FLG2_ICH_WORKAROUND
;
11839 pci_dev_put(bridge
);
11845 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
11846 static struct tg3_dev_id
{
11849 } bridge_chipsets
[] = {
11850 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
},
11851 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
},
11854 struct tg3_dev_id
*pci_id
= &bridge_chipsets
[0];
11855 struct pci_dev
*bridge
= NULL
;
11857 while (pci_id
->vendor
!= 0) {
11858 bridge
= pci_get_device(pci_id
->vendor
,
11865 if (bridge
->subordinate
&&
11866 (bridge
->subordinate
->number
<=
11867 tp
->pdev
->bus
->number
) &&
11868 (bridge
->subordinate
->subordinate
>=
11869 tp
->pdev
->bus
->number
)) {
11870 tp
->tg3_flags3
|= TG3_FLG3_5701_DMA_BUG
;
11871 pci_dev_put(bridge
);
11877 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11878 * DMA addresses > 40-bit. This bridge may have other additional
11879 * 57xx devices behind it in some 4-port NIC designs for example.
11880 * Any tg3 device found behind the bridge will also need the 40-bit
11883 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
||
11884 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
11885 tp
->tg3_flags2
|= TG3_FLG2_5780_CLASS
;
11886 tp
->tg3_flags
|= TG3_FLAG_40BIT_DMA_BUG
;
11887 tp
->msi_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_MSI
);
11890 struct pci_dev
*bridge
= NULL
;
11893 bridge
= pci_get_device(PCI_VENDOR_ID_SERVERWORKS
,
11894 PCI_DEVICE_ID_SERVERWORKS_EPB
,
11896 if (bridge
&& bridge
->subordinate
&&
11897 (bridge
->subordinate
->number
<=
11898 tp
->pdev
->bus
->number
) &&
11899 (bridge
->subordinate
->subordinate
>=
11900 tp
->pdev
->bus
->number
)) {
11901 tp
->tg3_flags
|= TG3_FLAG_40BIT_DMA_BUG
;
11902 pci_dev_put(bridge
);
11908 /* Initialize misc host control in PCI block. */
11909 tp
->misc_host_ctrl
|= (misc_ctrl_reg
&
11910 MISC_HOST_CTRL_CHIPREV
);
11911 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
11912 tp
->misc_host_ctrl
);
11914 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) ||
11915 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
))
11916 tp
->pdev_peer
= tg3_find_peer(tp
);
11918 /* Intentionally exclude ASIC_REV_5906 */
11919 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
11920 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
11921 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
11922 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
11923 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
11924 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
11925 tp
->tg3_flags3
|= TG3_FLG3_5755_PLUS
;
11927 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
11928 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
11929 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
||
11930 (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
11931 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
11932 tp
->tg3_flags2
|= TG3_FLG2_5750_PLUS
;
11934 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) ||
11935 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
11936 tp
->tg3_flags2
|= TG3_FLG2_5705_PLUS
;
11938 /* 5700 B0 chips do not support checksumming correctly due
11939 * to hardware bugs.
11941 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5700_B0
)
11942 tp
->tg3_flags
|= TG3_FLAG_BROKEN_CHECKSUMS
;
11944 tp
->tg3_flags
|= TG3_FLAG_RX_CHECKSUMS
;
11945 tp
->dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
11946 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
11947 tp
->dev
->features
|= NETIF_F_IPV6_CSUM
;
11950 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
11951 tp
->tg3_flags
|= TG3_FLAG_SUPPORT_MSI
;
11952 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
||
11953 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
||
11954 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
&&
11955 tp
->pci_chip_rev_id
<= CHIPREV_ID_5714_A2
&&
11956 tp
->pdev_peer
== tp
->pdev
))
11957 tp
->tg3_flags
&= ~TG3_FLAG_SUPPORT_MSI
;
11959 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
11960 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
11961 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_2
;
11962 tp
->tg3_flags2
|= TG3_FLG2_1SHOT_MSI
;
11964 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_1
| TG3_FLG2_TSO_BUG
;
11965 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
11967 tp
->pci_chip_rev_id
>= CHIPREV_ID_5750_C2
)
11968 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_BUG
;
11972 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
11973 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
11974 tp
->tg3_flags2
|= TG3_FLG2_JUMBO_CAPABLE
;
11976 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
11979 tp
->pcie_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_EXP
);
11980 if (tp
->pcie_cap
!= 0) {
11983 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
11985 pcie_set_readrq(tp
->pdev
, 4096);
11987 pci_read_config_word(tp
->pdev
,
11988 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
11990 if (lnkctl
& PCI_EXP_LNKCTL_CLKREQ_EN
) {
11991 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
11992 tp
->tg3_flags2
&= ~TG3_FLG2_HW_TSO_2
;
11993 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
11994 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
11995 tp
->pci_chip_rev_id
== CHIPREV_ID_57780_A0
||
11996 tp
->pci_chip_rev_id
== CHIPREV_ID_57780_A1
)
11997 tp
->tg3_flags3
|= TG3_FLG3_CLKREQ_BUG
;
11999 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
) {
12000 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
12001 } else if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
12002 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
12003 tp
->pcix_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_PCIX
);
12004 if (!tp
->pcix_cap
) {
12005 printk(KERN_ERR PFX
"Cannot find PCI-X "
12006 "capability, aborting.\n");
12010 if (!(pci_state_reg
& PCISTATE_CONV_PCI_MODE
))
12011 tp
->tg3_flags
|= TG3_FLAG_PCIX_MODE
;
12014 /* If we have an AMD 762 or VIA K8T800 chipset, write
12015 * reordering to the mailbox registers done by the host
12016 * controller can cause major troubles. We read back from
12017 * every mailbox register write to force the writes to be
12018 * posted to the chip in order.
12020 if (pci_dev_present(write_reorder_chipsets
) &&
12021 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
12022 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
12024 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
12025 &tp
->pci_cacheline_sz
);
12026 pci_read_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
12027 &tp
->pci_lat_timer
);
12028 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
12029 tp
->pci_lat_timer
< 64) {
12030 tp
->pci_lat_timer
= 64;
12031 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
12032 tp
->pci_lat_timer
);
12035 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5700_BX
) {
12036 /* 5700 BX chips need to have their TX producer index
12037 * mailboxes written twice to workaround a bug.
12039 tp
->tg3_flags
|= TG3_FLAG_TXD_MBOX_HWBUG
;
12041 /* If we are in PCI-X mode, enable register write workaround.
12043 * The workaround is to use indirect register accesses
12044 * for all chip writes not to mailbox registers.
12046 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
12049 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
12051 /* The chip can have it's power management PCI config
12052 * space registers clobbered due to this bug.
12053 * So explicitly force the chip into D0 here.
12055 pci_read_config_dword(tp
->pdev
,
12056 tp
->pm_cap
+ PCI_PM_CTRL
,
12058 pm_reg
&= ~PCI_PM_CTRL_STATE_MASK
;
12059 pm_reg
|= PCI_PM_CTRL_PME_ENABLE
| 0 /* D0 */;
12060 pci_write_config_dword(tp
->pdev
,
12061 tp
->pm_cap
+ PCI_PM_CTRL
,
12064 /* Also, force SERR#/PERR# in PCI command. */
12065 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
12066 pci_cmd
|= PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
;
12067 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
12071 if ((pci_state_reg
& PCISTATE_BUS_SPEED_HIGH
) != 0)
12072 tp
->tg3_flags
|= TG3_FLAG_PCI_HIGH_SPEED
;
12073 if ((pci_state_reg
& PCISTATE_BUS_32BIT
) != 0)
12074 tp
->tg3_flags
|= TG3_FLAG_PCI_32BIT
;
12076 /* Chip-specific fixup from Broadcom driver */
12077 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
) &&
12078 (!(pci_state_reg
& PCISTATE_RETRY_SAME_DMA
))) {
12079 pci_state_reg
|= PCISTATE_RETRY_SAME_DMA
;
12080 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, pci_state_reg
);
12083 /* Default fast path register access methods */
12084 tp
->read32
= tg3_read32
;
12085 tp
->write32
= tg3_write32
;
12086 tp
->read32_mbox
= tg3_read32
;
12087 tp
->write32_mbox
= tg3_write32
;
12088 tp
->write32_tx_mbox
= tg3_write32
;
12089 tp
->write32_rx_mbox
= tg3_write32
;
12091 /* Various workaround register access methods */
12092 if (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
)
12093 tp
->write32
= tg3_write_indirect_reg32
;
12094 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
||
12095 ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
12096 tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
)) {
12098 * Back to back register writes can cause problems on these
12099 * chips, the workaround is to read back all reg writes
12100 * except those to mailbox regs.
12102 * See tg3_write_indirect_reg32().
12104 tp
->write32
= tg3_write_flush_reg32
;
12108 if ((tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
) ||
12109 (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)) {
12110 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
12111 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
12112 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
12115 if (tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
) {
12116 tp
->read32
= tg3_read_indirect_reg32
;
12117 tp
->write32
= tg3_write_indirect_reg32
;
12118 tp
->read32_mbox
= tg3_read_indirect_mbox
;
12119 tp
->write32_mbox
= tg3_write_indirect_mbox
;
12120 tp
->write32_tx_mbox
= tg3_write_indirect_mbox
;
12121 tp
->write32_rx_mbox
= tg3_write_indirect_mbox
;
12126 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
12127 pci_cmd
&= ~PCI_COMMAND_MEMORY
;
12128 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
12130 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
12131 tp
->read32_mbox
= tg3_read32_mbox_5906
;
12132 tp
->write32_mbox
= tg3_write32_mbox_5906
;
12133 tp
->write32_tx_mbox
= tg3_write32_mbox_5906
;
12134 tp
->write32_rx_mbox
= tg3_write32_mbox_5906
;
12137 if (tp
->write32
== tg3_write_indirect_reg32
||
12138 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
12139 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
12140 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)))
12141 tp
->tg3_flags
|= TG3_FLAG_SRAM_USE_CONFIG
;
12143 /* Get eeprom hw config before calling tg3_set_power_state().
12144 * In particular, the TG3_FLG2_IS_NIC flag must be
12145 * determined before calling tg3_set_power_state() so that
12146 * we know whether or not to switch out of Vaux power.
12147 * When the flag is set, it means that GPIO1 is used for eeprom
12148 * write protect and also implies that it is a LOM where GPIOs
12149 * are not used to switch power.
12151 tg3_get_eeprom_hw_cfg(tp
);
12153 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
12154 /* Allow reads and writes to the
12155 * APE register and memory space.
12157 pci_state_reg
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
12158 PCISTATE_ALLOW_APE_SHMEM_WR
;
12159 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
12163 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
12164 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
12165 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
12166 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
12167 tp
->tg3_flags
|= TG3_FLAG_CPMU_PRESENT
;
12169 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12170 * GPIO1 driven high will bring 5700's external PHY out of reset.
12171 * It is also used as eeprom write protect on LOMs.
12173 tp
->grc_local_ctrl
= GRC_LCLCTRL_INT_ON_ATTN
| GRC_LCLCTRL_AUTO_SEEPROM
;
12174 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
12175 (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
))
12176 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
12177 GRC_LCLCTRL_GPIO_OUTPUT1
);
12178 /* Unused GPIO3 must be driven as output on 5752 because there
12179 * are no pull-up resistors on unused GPIO pins.
12181 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
12182 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
12184 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
12185 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
12186 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
12188 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
12189 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
) {
12190 /* Turn off the debug UART. */
12191 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
12192 if (tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)
12193 /* Keep VMain power. */
12194 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
12195 GRC_LCLCTRL_GPIO_OUTPUT0
;
12198 /* Force the chip into D0. */
12199 err
= tg3_set_power_state(tp
, PCI_D0
);
12201 printk(KERN_ERR PFX
"(%s) transition to D0 failed\n",
12202 pci_name(tp
->pdev
));
12206 /* Derive initial jumbo mode from MTU assigned in
12207 * ether_setup() via the alloc_etherdev() call
12209 if (tp
->dev
->mtu
> ETH_DATA_LEN
&&
12210 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
12211 tp
->tg3_flags
|= TG3_FLAG_JUMBO_RING_ENABLE
;
12213 /* Determine WakeOnLan speed to use. */
12214 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
12215 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
12216 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
||
12217 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B2
) {
12218 tp
->tg3_flags
&= ~(TG3_FLAG_WOL_SPEED_100MB
);
12220 tp
->tg3_flags
|= TG3_FLAG_WOL_SPEED_100MB
;
12223 /* A few boards don't want Ethernet@WireSpeed phy feature */
12224 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
12225 ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
12226 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) &&
12227 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A1
)) ||
12228 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) ||
12229 (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
))
12230 tp
->tg3_flags2
|= TG3_FLG2_NO_ETH_WIRE_SPEED
;
12232 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5703_AX
||
12233 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_AX
)
12234 tp
->tg3_flags2
|= TG3_FLG2_PHY_ADC_BUG
;
12235 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
)
12236 tp
->tg3_flags2
|= TG3_FLG2_PHY_5704_A0_BUG
;
12238 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
12239 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5906
&&
12240 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
12241 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_57780
) {
12242 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
12243 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
12244 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
12245 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
) {
12246 if (tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5756
&&
12247 tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5722
)
12248 tp
->tg3_flags2
|= TG3_FLG2_PHY_JITTER_BUG
;
12249 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5755M
)
12250 tp
->tg3_flags2
|= TG3_FLG2_PHY_ADJUST_TRIM
;
12252 tp
->tg3_flags2
|= TG3_FLG2_PHY_BER_BUG
;
12255 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
12256 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) {
12257 tp
->phy_otp
= tg3_read_otp_phycfg(tp
);
12258 if (tp
->phy_otp
== 0)
12259 tp
->phy_otp
= TG3_OTP_DEFAULT
;
12262 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
)
12263 tp
->mi_mode
= MAC_MI_MODE_500KHZ_CONST
;
12265 tp
->mi_mode
= MAC_MI_MODE_BASE
;
12267 tp
->coalesce_mode
= 0;
12268 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_AX
&&
12269 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_BX
)
12270 tp
->coalesce_mode
|= HOSTCC_MODE_32BYTE
;
12272 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
12273 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
12274 tp
->tg3_flags3
|= TG3_FLG3_USE_PHYLIB
;
12276 err
= tg3_mdio_init(tp
);
12280 /* Initialize data/descriptor byte/word swapping. */
12281 val
= tr32(GRC_MODE
);
12282 val
&= GRC_MODE_HOST_STACKUP
;
12283 tw32(GRC_MODE
, val
| tp
->grc_mode
);
12285 tg3_switch_clocks(tp
);
12287 /* Clear this out for sanity. */
12288 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
12290 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
12292 if ((pci_state_reg
& PCISTATE_CONV_PCI_MODE
) == 0 &&
12293 (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) == 0) {
12294 u32 chiprevid
= GET_CHIP_REV_ID(tp
->misc_host_ctrl
);
12296 if (chiprevid
== CHIPREV_ID_5701_A0
||
12297 chiprevid
== CHIPREV_ID_5701_B0
||
12298 chiprevid
== CHIPREV_ID_5701_B2
||
12299 chiprevid
== CHIPREV_ID_5701_B5
) {
12300 void __iomem
*sram_base
;
12302 /* Write some dummy words into the SRAM status block
12303 * area, see if it reads back correctly. If the return
12304 * value is bad, force enable the PCIX workaround.
12306 sram_base
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_STATS_BLK
;
12308 writel(0x00000000, sram_base
);
12309 writel(0x00000000, sram_base
+ 4);
12310 writel(0xffffffff, sram_base
+ 4);
12311 if (readl(sram_base
) != 0x00000000)
12312 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
12317 tg3_nvram_init(tp
);
12319 grc_misc_cfg
= tr32(GRC_MISC_CFG
);
12320 grc_misc_cfg
&= GRC_MISC_CFG_BOARD_ID_MASK
;
12322 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
12323 (grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788
||
12324 grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788M
))
12325 tp
->tg3_flags2
|= TG3_FLG2_IS_5788
;
12327 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
12328 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
))
12329 tp
->tg3_flags
|= TG3_FLAG_TAGGED_STATUS
;
12330 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
12331 tp
->coalesce_mode
|= (HOSTCC_MODE_CLRTICK_RXBD
|
12332 HOSTCC_MODE_CLRTICK_TXBD
);
12334 tp
->misc_host_ctrl
|= MISC_HOST_CTRL_TAGGED_STATUS
;
12335 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
12336 tp
->misc_host_ctrl
);
12339 /* Preserve the APE MAC_MODE bits */
12340 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
12341 tp
->mac_mode
= tr32(MAC_MODE
) |
12342 MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
12344 tp
->mac_mode
= TG3_DEF_MAC_MODE
;
12346 /* these are limited to 10/100 only */
12347 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
12348 (grc_misc_cfg
== 0x8000 || grc_misc_cfg
== 0x4000)) ||
12349 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
12350 tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
12351 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901
||
12352 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901_2
||
12353 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5705F
)) ||
12354 (tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
12355 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5751F
||
12356 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5753F
||
12357 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5787F
)) ||
12358 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57790
||
12359 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
12360 tp
->tg3_flags
|= TG3_FLAG_10_100_ONLY
;
12362 err
= tg3_phy_probe(tp
);
12364 printk(KERN_ERR PFX
"(%s) phy probe failed, err %d\n",
12365 pci_name(tp
->pdev
), err
);
12366 /* ... but do not return immediately ... */
12370 tg3_read_partno(tp
);
12371 tg3_read_fw_ver(tp
);
12373 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
12374 tp
->tg3_flags
&= ~TG3_FLAG_USE_MI_INTERRUPT
;
12376 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
12377 tp
->tg3_flags
|= TG3_FLAG_USE_MI_INTERRUPT
;
12379 tp
->tg3_flags
&= ~TG3_FLAG_USE_MI_INTERRUPT
;
12382 /* 5700 {AX,BX} chips have a broken status block link
12383 * change bit implementation, so we must use the
12384 * status register in those cases.
12386 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
12387 tp
->tg3_flags
|= TG3_FLAG_USE_LINKCHG_REG
;
12389 tp
->tg3_flags
&= ~TG3_FLAG_USE_LINKCHG_REG
;
12391 /* The led_ctrl is set during tg3_phy_probe, here we might
12392 * have to force the link status polling mechanism based
12393 * upon subsystem IDs.
12395 if (tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
&&
12396 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
12397 !(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
12398 tp
->tg3_flags
|= (TG3_FLAG_USE_MI_INTERRUPT
|
12399 TG3_FLAG_USE_LINKCHG_REG
);
12402 /* For all SERDES we poll the MAC status register. */
12403 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
12404 tp
->tg3_flags
|= TG3_FLAG_POLL_SERDES
;
12406 tp
->tg3_flags
&= ~TG3_FLAG_POLL_SERDES
;
12408 tp
->rx_offset
= NET_IP_ALIGN
;
12409 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
12410 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) != 0)
12413 tp
->rx_std_max_post
= TG3_RX_RING_SIZE
;
12415 /* Increment the rx prod index on the rx std ring by at most
12416 * 8 for these chips to workaround hw errata.
12418 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
12419 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
12420 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
12421 tp
->rx_std_max_post
= 8;
12423 if (tp
->tg3_flags
& TG3_FLAG_ASPM_WORKAROUND
)
12424 tp
->pwrmgmt_thresh
= tr32(PCIE_PWR_MGMT_THRESH
) &
12425 PCIE_PWR_MGMT_L1_THRESH_MSK
;
12430 #ifdef CONFIG_SPARC
12431 static int __devinit
tg3_get_macaddr_sparc(struct tg3
*tp
)
12433 struct net_device
*dev
= tp
->dev
;
12434 struct pci_dev
*pdev
= tp
->pdev
;
12435 struct device_node
*dp
= pci_device_to_OF_node(pdev
);
12436 const unsigned char *addr
;
12439 addr
= of_get_property(dp
, "local-mac-address", &len
);
12440 if (addr
&& len
== 6) {
12441 memcpy(dev
->dev_addr
, addr
, 6);
12442 memcpy(dev
->perm_addr
, dev
->dev_addr
, 6);
12448 static int __devinit
tg3_get_default_macaddr_sparc(struct tg3
*tp
)
12450 struct net_device
*dev
= tp
->dev
;
12452 memcpy(dev
->dev_addr
, idprom
->id_ethaddr
, 6);
12453 memcpy(dev
->perm_addr
, idprom
->id_ethaddr
, 6);
12458 static int __devinit
tg3_get_device_address(struct tg3
*tp
)
12460 struct net_device
*dev
= tp
->dev
;
12461 u32 hi
, lo
, mac_offset
;
12464 #ifdef CONFIG_SPARC
12465 if (!tg3_get_macaddr_sparc(tp
))
12470 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) ||
12471 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
12472 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
12474 if (tg3_nvram_lock(tp
))
12475 tw32_f(NVRAM_CMD
, NVRAM_CMD_RESET
);
12477 tg3_nvram_unlock(tp
);
12479 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
12482 /* First try to get it from MAC address mailbox. */
12483 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_HIGH_MBOX
, &hi
);
12484 if ((hi
>> 16) == 0x484b) {
12485 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
12486 dev
->dev_addr
[1] = (hi
>> 0) & 0xff;
12488 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_LOW_MBOX
, &lo
);
12489 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
12490 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
12491 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
12492 dev
->dev_addr
[5] = (lo
>> 0) & 0xff;
12494 /* Some old bootcode may report a 0 MAC address in SRAM */
12495 addr_ok
= is_valid_ether_addr(&dev
->dev_addr
[0]);
12498 /* Next, try NVRAM. */
12499 if (!(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) &&
12500 !tg3_nvram_read_be32(tp
, mac_offset
+ 0, &hi
) &&
12501 !tg3_nvram_read_be32(tp
, mac_offset
+ 4, &lo
)) {
12502 memcpy(&dev
->dev_addr
[0], ((char *)&hi
) + 2, 2);
12503 memcpy(&dev
->dev_addr
[2], (char *)&lo
, sizeof(lo
));
12505 /* Finally just fetch it out of the MAC control regs. */
12507 hi
= tr32(MAC_ADDR_0_HIGH
);
12508 lo
= tr32(MAC_ADDR_0_LOW
);
12510 dev
->dev_addr
[5] = lo
& 0xff;
12511 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
12512 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
12513 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
12514 dev
->dev_addr
[1] = hi
& 0xff;
12515 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
12519 if (!is_valid_ether_addr(&dev
->dev_addr
[0])) {
12520 #ifdef CONFIG_SPARC
12521 if (!tg3_get_default_macaddr_sparc(tp
))
12526 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
12530 #define BOUNDARY_SINGLE_CACHELINE 1
12531 #define BOUNDARY_MULTI_CACHELINE 2
12533 static u32 __devinit
tg3_calc_dma_bndry(struct tg3
*tp
, u32 val
)
12535 int cacheline_size
;
12539 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
, &byte
);
12541 cacheline_size
= 1024;
12543 cacheline_size
= (int) byte
* 4;
12545 /* On 5703 and later chips, the boundary bits have no
12548 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
12549 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
&&
12550 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
12553 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12554 goal
= BOUNDARY_MULTI_CACHELINE
;
12556 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12557 goal
= BOUNDARY_SINGLE_CACHELINE
;
12566 /* PCI controllers on most RISC systems tend to disconnect
12567 * when a device tries to burst across a cache-line boundary.
12568 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12570 * Unfortunately, for PCI-E there are only limited
12571 * write-side controls for this, and thus for reads
12572 * we will still get the disconnects. We'll also waste
12573 * these PCI cycles for both read and write for chips
12574 * other than 5700 and 5701 which do not implement the
12577 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
12578 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
12579 switch (cacheline_size
) {
12584 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
12585 val
|= (DMA_RWCTRL_READ_BNDRY_128_PCIX
|
12586 DMA_RWCTRL_WRITE_BNDRY_128_PCIX
);
12588 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
12589 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
12594 val
|= (DMA_RWCTRL_READ_BNDRY_256_PCIX
|
12595 DMA_RWCTRL_WRITE_BNDRY_256_PCIX
);
12599 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
12600 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
12603 } else if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
12604 switch (cacheline_size
) {
12608 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
12609 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
12610 val
|= DMA_RWCTRL_WRITE_BNDRY_64_PCIE
;
12616 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
12617 val
|= DMA_RWCTRL_WRITE_BNDRY_128_PCIE
;
12621 switch (cacheline_size
) {
12623 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
12624 val
|= (DMA_RWCTRL_READ_BNDRY_16
|
12625 DMA_RWCTRL_WRITE_BNDRY_16
);
12630 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
12631 val
|= (DMA_RWCTRL_READ_BNDRY_32
|
12632 DMA_RWCTRL_WRITE_BNDRY_32
);
12637 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
12638 val
|= (DMA_RWCTRL_READ_BNDRY_64
|
12639 DMA_RWCTRL_WRITE_BNDRY_64
);
12644 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
12645 val
|= (DMA_RWCTRL_READ_BNDRY_128
|
12646 DMA_RWCTRL_WRITE_BNDRY_128
);
12651 val
|= (DMA_RWCTRL_READ_BNDRY_256
|
12652 DMA_RWCTRL_WRITE_BNDRY_256
);
12655 val
|= (DMA_RWCTRL_READ_BNDRY_512
|
12656 DMA_RWCTRL_WRITE_BNDRY_512
);
12660 val
|= (DMA_RWCTRL_READ_BNDRY_1024
|
12661 DMA_RWCTRL_WRITE_BNDRY_1024
);
12670 static int __devinit
tg3_do_test_dma(struct tg3
*tp
, u32
*buf
, dma_addr_t buf_dma
, int size
, int to_device
)
12672 struct tg3_internal_buffer_desc test_desc
;
12673 u32 sram_dma_descs
;
12676 sram_dma_descs
= NIC_SRAM_DMA_DESC_POOL_BASE
;
12678 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
, 0);
12679 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
, 0);
12680 tw32(RDMAC_STATUS
, 0);
12681 tw32(WDMAC_STATUS
, 0);
12683 tw32(BUFMGR_MODE
, 0);
12684 tw32(FTQ_RESET
, 0);
12686 test_desc
.addr_hi
= ((u64
) buf_dma
) >> 32;
12687 test_desc
.addr_lo
= buf_dma
& 0xffffffff;
12688 test_desc
.nic_mbuf
= 0x00002100;
12689 test_desc
.len
= size
;
12692 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12693 * the *second* time the tg3 driver was getting loaded after an
12696 * Broadcom tells me:
12697 * ...the DMA engine is connected to the GRC block and a DMA
12698 * reset may affect the GRC block in some unpredictable way...
12699 * The behavior of resets to individual blocks has not been tested.
12701 * Broadcom noted the GRC reset will also reset all sub-components.
12704 test_desc
.cqid_sqid
= (13 << 8) | 2;
12706 tw32_f(RDMAC_MODE
, RDMAC_MODE_ENABLE
);
12709 test_desc
.cqid_sqid
= (16 << 8) | 7;
12711 tw32_f(WDMAC_MODE
, WDMAC_MODE_ENABLE
);
12714 test_desc
.flags
= 0x00000005;
12716 for (i
= 0; i
< (sizeof(test_desc
) / sizeof(u32
)); i
++) {
12719 val
= *(((u32
*)&test_desc
) + i
);
12720 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
,
12721 sram_dma_descs
+ (i
* sizeof(u32
)));
12722 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
12724 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
12727 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ
, sram_dma_descs
);
12729 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ
, sram_dma_descs
);
12733 for (i
= 0; i
< 40; i
++) {
12737 val
= tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
);
12739 val
= tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
);
12740 if ((val
& 0xffff) == sram_dma_descs
) {
12751 #define TEST_BUFFER_SIZE 0x2000
12753 static int __devinit
tg3_test_dma(struct tg3
*tp
)
12755 dma_addr_t buf_dma
;
12756 u32
*buf
, saved_dma_rwctrl
;
12759 buf
= pci_alloc_consistent(tp
->pdev
, TEST_BUFFER_SIZE
, &buf_dma
);
12765 tp
->dma_rwctrl
= ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT
) |
12766 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT
));
12768 tp
->dma_rwctrl
= tg3_calc_dma_bndry(tp
, tp
->dma_rwctrl
);
12770 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
12771 /* DMA read watermark not used on PCIE */
12772 tp
->dma_rwctrl
|= 0x00180000;
12773 } else if (!(tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
12774 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
||
12775 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)
12776 tp
->dma_rwctrl
|= 0x003f0000;
12778 tp
->dma_rwctrl
|= 0x003f000f;
12780 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
12781 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
12782 u32 ccval
= (tr32(TG3PCI_CLOCK_CTRL
) & 0x1f);
12783 u32 read_water
= 0x7;
12785 /* If the 5704 is behind the EPB bridge, we can
12786 * do the less restrictive ONE_DMA workaround for
12787 * better performance.
12789 if ((tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
) &&
12790 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
12791 tp
->dma_rwctrl
|= 0x8000;
12792 else if (ccval
== 0x6 || ccval
== 0x7)
12793 tp
->dma_rwctrl
|= DMA_RWCTRL_ONE_DMA
;
12795 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
)
12797 /* Set bit 23 to enable PCIX hw bug fix */
12799 (read_water
<< DMA_RWCTRL_READ_WATER_SHIFT
) |
12800 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT
) |
12802 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
) {
12803 /* 5780 always in PCIX mode */
12804 tp
->dma_rwctrl
|= 0x00144000;
12805 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
12806 /* 5714 always in PCIX mode */
12807 tp
->dma_rwctrl
|= 0x00148000;
12809 tp
->dma_rwctrl
|= 0x001b000f;
12813 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
12814 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
12815 tp
->dma_rwctrl
&= 0xfffffff0;
12817 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
12818 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
12819 /* Remove this if it causes problems for some boards. */
12820 tp
->dma_rwctrl
|= DMA_RWCTRL_USE_MEM_READ_MULT
;
12822 /* On 5700/5701 chips, we need to set this bit.
12823 * Otherwise the chip will issue cacheline transactions
12824 * to streamable DMA memory with not all the byte
12825 * enables turned on. This is an error on several
12826 * RISC PCI controllers, in particular sparc64.
12828 * On 5703/5704 chips, this bit has been reassigned
12829 * a different meaning. In particular, it is used
12830 * on those chips to enable a PCI-X workaround.
12832 tp
->dma_rwctrl
|= DMA_RWCTRL_ASSERT_ALL_BE
;
12835 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
12838 /* Unneeded, already done by tg3_get_invariants. */
12839 tg3_switch_clocks(tp
);
12843 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
12844 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
12847 /* It is best to perform DMA test with maximum write burst size
12848 * to expose the 5700/5701 write DMA bug.
12850 saved_dma_rwctrl
= tp
->dma_rwctrl
;
12851 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
12852 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
12857 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++)
12860 /* Send the buffer to the chip. */
12861 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 1);
12863 printk(KERN_ERR
"tg3_test_dma() Write the buffer failed %d\n", ret
);
12868 /* validate data reached card RAM correctly. */
12869 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
12871 tg3_read_mem(tp
, 0x2100 + (i
*4), &val
);
12872 if (le32_to_cpu(val
) != p
[i
]) {
12873 printk(KERN_ERR
" tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val
, i
);
12874 /* ret = -ENODEV here? */
12879 /* Now read it back. */
12880 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 0);
12882 printk(KERN_ERR
"tg3_test_dma() Read the buffer failed %d\n", ret
);
12888 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
12892 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
12893 DMA_RWCTRL_WRITE_BNDRY_16
) {
12894 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
12895 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
12896 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
12899 printk(KERN_ERR
"tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p
[i
], i
);
12905 if (i
== (TEST_BUFFER_SIZE
/ sizeof(u32
))) {
12911 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
12912 DMA_RWCTRL_WRITE_BNDRY_16
) {
12913 static struct pci_device_id dma_wait_state_chipsets
[] = {
12914 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
,
12915 PCI_DEVICE_ID_APPLE_UNI_N_PCI15
) },
12919 /* DMA test passed without adjusting DMA boundary,
12920 * now look for chipsets that are known to expose the
12921 * DMA bug without failing the test.
12923 if (pci_dev_present(dma_wait_state_chipsets
)) {
12924 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
12925 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
12928 /* Safe to use the calculated DMA boundary. */
12929 tp
->dma_rwctrl
= saved_dma_rwctrl
;
12931 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
12935 pci_free_consistent(tp
->pdev
, TEST_BUFFER_SIZE
, buf
, buf_dma
);
12940 static void __devinit
tg3_init_link_config(struct tg3
*tp
)
12942 tp
->link_config
.advertising
=
12943 (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
12944 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
12945 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
|
12946 ADVERTISED_Autoneg
| ADVERTISED_MII
);
12947 tp
->link_config
.speed
= SPEED_INVALID
;
12948 tp
->link_config
.duplex
= DUPLEX_INVALID
;
12949 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
12950 tp
->link_config
.active_speed
= SPEED_INVALID
;
12951 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
12952 tp
->link_config
.phy_is_low_power
= 0;
12953 tp
->link_config
.orig_speed
= SPEED_INVALID
;
12954 tp
->link_config
.orig_duplex
= DUPLEX_INVALID
;
12955 tp
->link_config
.orig_autoneg
= AUTONEG_INVALID
;
12958 static void __devinit
tg3_init_bufmgr_config(struct tg3
*tp
)
12960 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
12961 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
12962 DEFAULT_MB_RDMA_LOW_WATER_5705
;
12963 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
12964 DEFAULT_MB_MACRX_LOW_WATER_5705
;
12965 tp
->bufmgr_config
.mbuf_high_water
=
12966 DEFAULT_MB_HIGH_WATER_5705
;
12967 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
12968 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
12969 DEFAULT_MB_MACRX_LOW_WATER_5906
;
12970 tp
->bufmgr_config
.mbuf_high_water
=
12971 DEFAULT_MB_HIGH_WATER_5906
;
12974 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
12975 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780
;
12976 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
12977 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780
;
12978 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
12979 DEFAULT_MB_HIGH_WATER_JUMBO_5780
;
12981 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
12982 DEFAULT_MB_RDMA_LOW_WATER
;
12983 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
12984 DEFAULT_MB_MACRX_LOW_WATER
;
12985 tp
->bufmgr_config
.mbuf_high_water
=
12986 DEFAULT_MB_HIGH_WATER
;
12988 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
12989 DEFAULT_MB_RDMA_LOW_WATER_JUMBO
;
12990 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
12991 DEFAULT_MB_MACRX_LOW_WATER_JUMBO
;
12992 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
12993 DEFAULT_MB_HIGH_WATER_JUMBO
;
12996 tp
->bufmgr_config
.dma_low_water
= DEFAULT_DMA_LOW_WATER
;
12997 tp
->bufmgr_config
.dma_high_water
= DEFAULT_DMA_HIGH_WATER
;
13000 static char * __devinit
tg3_phy_string(struct tg3
*tp
)
13002 switch (tp
->phy_id
& PHY_ID_MASK
) {
13003 case PHY_ID_BCM5400
: return "5400";
13004 case PHY_ID_BCM5401
: return "5401";
13005 case PHY_ID_BCM5411
: return "5411";
13006 case PHY_ID_BCM5701
: return "5701";
13007 case PHY_ID_BCM5703
: return "5703";
13008 case PHY_ID_BCM5704
: return "5704";
13009 case PHY_ID_BCM5705
: return "5705";
13010 case PHY_ID_BCM5750
: return "5750";
13011 case PHY_ID_BCM5752
: return "5752";
13012 case PHY_ID_BCM5714
: return "5714";
13013 case PHY_ID_BCM5780
: return "5780";
13014 case PHY_ID_BCM5755
: return "5755";
13015 case PHY_ID_BCM5787
: return "5787";
13016 case PHY_ID_BCM5784
: return "5784";
13017 case PHY_ID_BCM5756
: return "5722/5756";
13018 case PHY_ID_BCM5906
: return "5906";
13019 case PHY_ID_BCM5761
: return "5761";
13020 case PHY_ID_BCM8002
: return "8002/serdes";
13021 case 0: return "serdes";
13022 default: return "unknown";
13026 static char * __devinit
tg3_bus_string(struct tg3
*tp
, char *str
)
13028 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
13029 strcpy(str
, "PCI Express");
13031 } else if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
13032 u32 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
) & 0x1f;
13034 strcpy(str
, "PCIX:");
13036 if ((clock_ctrl
== 7) ||
13037 ((tr32(GRC_MISC_CFG
) & GRC_MISC_CFG_BOARD_ID_MASK
) ==
13038 GRC_MISC_CFG_BOARD_ID_5704CIOBE
))
13039 strcat(str
, "133MHz");
13040 else if (clock_ctrl
== 0)
13041 strcat(str
, "33MHz");
13042 else if (clock_ctrl
== 2)
13043 strcat(str
, "50MHz");
13044 else if (clock_ctrl
== 4)
13045 strcat(str
, "66MHz");
13046 else if (clock_ctrl
== 6)
13047 strcat(str
, "100MHz");
13049 strcpy(str
, "PCI:");
13050 if (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
)
13051 strcat(str
, "66MHz");
13053 strcat(str
, "33MHz");
13055 if (tp
->tg3_flags
& TG3_FLAG_PCI_32BIT
)
13056 strcat(str
, ":32-bit");
13058 strcat(str
, ":64-bit");
13062 static struct pci_dev
* __devinit
tg3_find_peer(struct tg3
*tp
)
13064 struct pci_dev
*peer
;
13065 unsigned int func
, devnr
= tp
->pdev
->devfn
& ~7;
13067 for (func
= 0; func
< 8; func
++) {
13068 peer
= pci_get_slot(tp
->pdev
->bus
, devnr
| func
);
13069 if (peer
&& peer
!= tp
->pdev
)
13073 /* 5704 can be configured in single-port mode, set peer to
13074 * tp->pdev in that case.
13082 * We don't need to keep the refcount elevated; there's no way
13083 * to remove one half of this device without removing the other
13090 static void __devinit
tg3_init_coal(struct tg3
*tp
)
13092 struct ethtool_coalesce
*ec
= &tp
->coal
;
13094 memset(ec
, 0, sizeof(*ec
));
13095 ec
->cmd
= ETHTOOL_GCOALESCE
;
13096 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS
;
13097 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS
;
13098 ec
->rx_max_coalesced_frames
= LOW_RXMAX_FRAMES
;
13099 ec
->tx_max_coalesced_frames
= LOW_TXMAX_FRAMES
;
13100 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT
;
13101 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT
;
13102 ec
->rx_max_coalesced_frames_irq
= DEFAULT_RXCOAL_MAXF_INT
;
13103 ec
->tx_max_coalesced_frames_irq
= DEFAULT_TXCOAL_MAXF_INT
;
13104 ec
->stats_block_coalesce_usecs
= DEFAULT_STAT_COAL_TICKS
;
13106 if (tp
->coalesce_mode
& (HOSTCC_MODE_CLRTICK_RXBD
|
13107 HOSTCC_MODE_CLRTICK_TXBD
)) {
13108 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS_CLRTCKS
;
13109 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT_CLRTCKS
;
13110 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS_CLRTCKS
;
13111 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT_CLRTCKS
;
13114 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
13115 ec
->rx_coalesce_usecs_irq
= 0;
13116 ec
->tx_coalesce_usecs_irq
= 0;
13117 ec
->stats_block_coalesce_usecs
= 0;
13121 static const struct net_device_ops tg3_netdev_ops
= {
13122 .ndo_open
= tg3_open
,
13123 .ndo_stop
= tg3_close
,
13124 .ndo_start_xmit
= tg3_start_xmit
,
13125 .ndo_get_stats
= tg3_get_stats
,
13126 .ndo_validate_addr
= eth_validate_addr
,
13127 .ndo_set_multicast_list
= tg3_set_rx_mode
,
13128 .ndo_set_mac_address
= tg3_set_mac_addr
,
13129 .ndo_do_ioctl
= tg3_ioctl
,
13130 .ndo_tx_timeout
= tg3_tx_timeout
,
13131 .ndo_change_mtu
= tg3_change_mtu
,
13132 #if TG3_VLAN_TAG_USED
13133 .ndo_vlan_rx_register
= tg3_vlan_rx_register
,
13135 #ifdef CONFIG_NET_POLL_CONTROLLER
13136 .ndo_poll_controller
= tg3_poll_controller
,
13140 static const struct net_device_ops tg3_netdev_ops_dma_bug
= {
13141 .ndo_open
= tg3_open
,
13142 .ndo_stop
= tg3_close
,
13143 .ndo_start_xmit
= tg3_start_xmit_dma_bug
,
13144 .ndo_get_stats
= tg3_get_stats
,
13145 .ndo_validate_addr
= eth_validate_addr
,
13146 .ndo_set_multicast_list
= tg3_set_rx_mode
,
13147 .ndo_set_mac_address
= tg3_set_mac_addr
,
13148 .ndo_do_ioctl
= tg3_ioctl
,
13149 .ndo_tx_timeout
= tg3_tx_timeout
,
13150 .ndo_change_mtu
= tg3_change_mtu
,
13151 #if TG3_VLAN_TAG_USED
13152 .ndo_vlan_rx_register
= tg3_vlan_rx_register
,
13154 #ifdef CONFIG_NET_POLL_CONTROLLER
13155 .ndo_poll_controller
= tg3_poll_controller
,
13159 static int __devinit
tg3_init_one(struct pci_dev
*pdev
,
13160 const struct pci_device_id
*ent
)
13162 static int tg3_version_printed
= 0;
13163 struct net_device
*dev
;
13167 u64 dma_mask
, persist_dma_mask
;
13169 if (tg3_version_printed
++ == 0)
13170 printk(KERN_INFO
"%s", version
);
13172 err
= pci_enable_device(pdev
);
13174 printk(KERN_ERR PFX
"Cannot enable PCI device, "
13179 err
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
13181 printk(KERN_ERR PFX
"Cannot obtain PCI resources, "
13183 goto err_out_disable_pdev
;
13186 pci_set_master(pdev
);
13188 /* Find power-management capability. */
13189 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
13191 printk(KERN_ERR PFX
"Cannot find PowerManagement capability, "
13194 goto err_out_free_res
;
13197 dev
= alloc_etherdev(sizeof(*tp
));
13199 printk(KERN_ERR PFX
"Etherdev alloc failed, aborting.\n");
13201 goto err_out_free_res
;
13204 SET_NETDEV_DEV(dev
, &pdev
->dev
);
13206 #if TG3_VLAN_TAG_USED
13207 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
13210 tp
= netdev_priv(dev
);
13213 tp
->pm_cap
= pm_cap
;
13214 tp
->rx_mode
= TG3_DEF_RX_MODE
;
13215 tp
->tx_mode
= TG3_DEF_TX_MODE
;
13218 tp
->msg_enable
= tg3_debug
;
13220 tp
->msg_enable
= TG3_DEF_MSG_ENABLE
;
13222 /* The word/byte swap controls here control register access byte
13223 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13226 tp
->misc_host_ctrl
=
13227 MISC_HOST_CTRL_MASK_PCI_INT
|
13228 MISC_HOST_CTRL_WORD_SWAP
|
13229 MISC_HOST_CTRL_INDIR_ACCESS
|
13230 MISC_HOST_CTRL_PCISTATE_RW
;
13232 /* The NONFRM (non-frame) byte/word swap controls take effect
13233 * on descriptor entries, anything which isn't packet data.
13235 * The StrongARM chips on the board (one for tx, one for rx)
13236 * are running in big-endian mode.
13238 tp
->grc_mode
= (GRC_MODE_WSWAP_DATA
| GRC_MODE_BSWAP_DATA
|
13239 GRC_MODE_WSWAP_NONFRM_DATA
);
13240 #ifdef __BIG_ENDIAN
13241 tp
->grc_mode
|= GRC_MODE_BSWAP_NONFRM_DATA
;
13243 spin_lock_init(&tp
->lock
);
13244 spin_lock_init(&tp
->indirect_lock
);
13245 INIT_WORK(&tp
->reset_task
, tg3_reset_task
);
13247 tp
->regs
= pci_ioremap_bar(pdev
, BAR_0
);
13249 printk(KERN_ERR PFX
"Cannot map device registers, "
13252 goto err_out_free_dev
;
13255 tg3_init_link_config(tp
);
13257 tp
->rx_pending
= TG3_DEF_RX_RING_PENDING
;
13258 tp
->rx_jumbo_pending
= TG3_DEF_RX_JUMBO_RING_PENDING
;
13259 tp
->tx_pending
= TG3_DEF_TX_RING_PENDING
;
13261 netif_napi_add(dev
, &tp
->napi
, tg3_poll
, 64);
13262 dev
->ethtool_ops
= &tg3_ethtool_ops
;
13263 dev
->watchdog_timeo
= TG3_TX_TIMEOUT
;
13264 dev
->irq
= pdev
->irq
;
13266 err
= tg3_get_invariants(tp
);
13268 printk(KERN_ERR PFX
"Problem fetching invariants of chip, "
13270 goto err_out_iounmap
;
13273 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
13274 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13275 dev
->netdev_ops
= &tg3_netdev_ops
;
13277 dev
->netdev_ops
= &tg3_netdev_ops_dma_bug
;
13280 /* The EPB bridge inside 5714, 5715, and 5780 and any
13281 * device behind the EPB cannot support DMA addresses > 40-bit.
13282 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13283 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13284 * do DMA address check in tg3_start_xmit().
13286 if (tp
->tg3_flags2
& TG3_FLG2_IS_5788
)
13287 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(32);
13288 else if (tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
) {
13289 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(40);
13290 #ifdef CONFIG_HIGHMEM
13291 dma_mask
= DMA_BIT_MASK(64);
13294 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(64);
13296 /* Configure DMA attributes. */
13297 if (dma_mask
> DMA_BIT_MASK(32)) {
13298 err
= pci_set_dma_mask(pdev
, dma_mask
);
13300 dev
->features
|= NETIF_F_HIGHDMA
;
13301 err
= pci_set_consistent_dma_mask(pdev
,
13304 printk(KERN_ERR PFX
"Unable to obtain 64 bit "
13305 "DMA for consistent allocations\n");
13306 goto err_out_iounmap
;
13310 if (err
|| dma_mask
== DMA_BIT_MASK(32)) {
13311 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
13313 printk(KERN_ERR PFX
"No usable DMA configuration, "
13315 goto err_out_iounmap
;
13319 tg3_init_bufmgr_config(tp
);
13321 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
)
13322 tp
->fw_needed
= FIRMWARE_TG3
;
13324 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
13325 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
13327 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
13328 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
||
13329 tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
||
13330 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
||
13331 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0) {
13332 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
13334 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
| TG3_FLG2_TSO_BUG
;
13335 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
)
13336 tp
->fw_needed
= FIRMWARE_TG3TSO5
;
13338 tp
->fw_needed
= FIRMWARE_TG3TSO
;
13341 /* TSO is on by default on chips that support hardware TSO.
13342 * Firmware TSO on older chips gives lower performance, so it
13343 * is off by default, but can be enabled using ethtool.
13345 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
13346 if (dev
->features
& NETIF_F_IP_CSUM
)
13347 dev
->features
|= NETIF_F_TSO
;
13348 if ((dev
->features
& NETIF_F_IPV6_CSUM
) &&
13349 (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
))
13350 dev
->features
|= NETIF_F_TSO6
;
13351 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
13352 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
13353 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) ||
13354 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
13355 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
13356 dev
->features
|= NETIF_F_TSO_ECN
;
13360 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
&&
13361 !(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) &&
13362 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
)) {
13363 tp
->tg3_flags2
|= TG3_FLG2_MAX_RXPEND_64
;
13364 tp
->rx_pending
= 63;
13367 err
= tg3_get_device_address(tp
);
13369 printk(KERN_ERR PFX
"Could not obtain valid ethernet address, "
13374 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
13375 tp
->aperegs
= pci_ioremap_bar(pdev
, BAR_2
);
13376 if (!tp
->aperegs
) {
13377 printk(KERN_ERR PFX
"Cannot map APE registers, "
13383 tg3_ape_lock_init(tp
);
13385 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)
13386 tg3_read_dash_ver(tp
);
13390 * Reset chip in case UNDI or EFI driver did not shutdown
13391 * DMA self test will enable WDMAC and we'll see (spurious)
13392 * pending DMA on the PCI bus at that point.
13394 if ((tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
) ||
13395 (tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
13396 tw32(MEMARB_MODE
, MEMARB_MODE_ENABLE
);
13397 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
13400 err
= tg3_test_dma(tp
);
13402 printk(KERN_ERR PFX
"DMA engine test failed, aborting.\n");
13403 goto err_out_apeunmap
;
13406 /* flow control autonegotiation is default behavior */
13407 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
13408 tp
->link_config
.flowctrl
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
13412 pci_set_drvdata(pdev
, dev
);
13414 err
= register_netdev(dev
);
13416 printk(KERN_ERR PFX
"Cannot register net device, "
13418 goto err_out_apeunmap
;
13421 printk(KERN_INFO
"%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
13423 tp
->board_part_number
,
13424 tp
->pci_chip_rev_id
,
13425 tg3_bus_string(tp
, str
),
13428 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
)
13430 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13432 tp
->mdio_bus
->phy_map
[PHY_ADDR
]->drv
->name
,
13433 dev_name(&tp
->mdio_bus
->phy_map
[PHY_ADDR
]->dev
));
13436 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13437 tp
->dev
->name
, tg3_phy_string(tp
),
13438 ((tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
) ? "10/100Base-TX" :
13439 ((tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
) ? "1000Base-SX" :
13440 "10/100/1000Base-T")),
13441 (tp
->tg3_flags2
& TG3_FLG2_NO_ETH_WIRE_SPEED
) == 0);
13443 printk(KERN_INFO
"%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
13445 (tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) != 0,
13446 (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) != 0,
13447 (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
) != 0,
13448 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0,
13449 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) != 0);
13450 printk(KERN_INFO
"%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13451 dev
->name
, tp
->dma_rwctrl
,
13452 (pdev
->dma_mask
== DMA_BIT_MASK(32)) ? 32 :
13453 (((u64
) pdev
->dma_mask
== DMA_BIT_MASK(40)) ? 40 : 64));
13459 iounmap(tp
->aperegs
);
13460 tp
->aperegs
= NULL
;
13465 release_firmware(tp
->fw
);
13477 pci_release_regions(pdev
);
13479 err_out_disable_pdev
:
13480 pci_disable_device(pdev
);
13481 pci_set_drvdata(pdev
, NULL
);
13485 static void __devexit
tg3_remove_one(struct pci_dev
*pdev
)
13487 struct net_device
*dev
= pci_get_drvdata(pdev
);
13490 struct tg3
*tp
= netdev_priv(dev
);
13493 release_firmware(tp
->fw
);
13495 flush_scheduled_work();
13497 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
13502 unregister_netdev(dev
);
13504 iounmap(tp
->aperegs
);
13505 tp
->aperegs
= NULL
;
13512 pci_release_regions(pdev
);
13513 pci_disable_device(pdev
);
13514 pci_set_drvdata(pdev
, NULL
);
13518 static int tg3_suspend(struct pci_dev
*pdev
, pm_message_t state
)
13520 struct net_device
*dev
= pci_get_drvdata(pdev
);
13521 struct tg3
*tp
= netdev_priv(dev
);
13522 pci_power_t target_state
;
13525 /* PCI register 4 needs to be saved whether netif_running() or not.
13526 * MSI address and data need to be saved if using MSI and
13529 pci_save_state(pdev
);
13531 if (!netif_running(dev
))
13534 flush_scheduled_work();
13536 tg3_netif_stop(tp
);
13538 del_timer_sync(&tp
->timer
);
13540 tg3_full_lock(tp
, 1);
13541 tg3_disable_ints(tp
);
13542 tg3_full_unlock(tp
);
13544 netif_device_detach(dev
);
13546 tg3_full_lock(tp
, 0);
13547 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
13548 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
13549 tg3_full_unlock(tp
);
13551 target_state
= pdev
->pm_cap
? pci_target_state(pdev
) : PCI_D3hot
;
13553 err
= tg3_set_power_state(tp
, target_state
);
13557 tg3_full_lock(tp
, 0);
13559 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
13560 err2
= tg3_restart_hw(tp
, 1);
13564 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
13565 add_timer(&tp
->timer
);
13567 netif_device_attach(dev
);
13568 tg3_netif_start(tp
);
13571 tg3_full_unlock(tp
);
13580 static int tg3_resume(struct pci_dev
*pdev
)
13582 struct net_device
*dev
= pci_get_drvdata(pdev
);
13583 struct tg3
*tp
= netdev_priv(dev
);
13586 pci_restore_state(tp
->pdev
);
13588 if (!netif_running(dev
))
13591 err
= tg3_set_power_state(tp
, PCI_D0
);
13595 netif_device_attach(dev
);
13597 tg3_full_lock(tp
, 0);
13599 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
13600 err
= tg3_restart_hw(tp
, 1);
13604 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
13605 add_timer(&tp
->timer
);
13607 tg3_netif_start(tp
);
13610 tg3_full_unlock(tp
);
13618 static struct pci_driver tg3_driver
= {
13619 .name
= DRV_MODULE_NAME
,
13620 .id_table
= tg3_pci_tbl
,
13621 .probe
= tg3_init_one
,
13622 .remove
= __devexit_p(tg3_remove_one
),
13623 .suspend
= tg3_suspend
,
13624 .resume
= tg3_resume
13627 static int __init
tg3_init(void)
13629 return pci_register_driver(&tg3_driver
);
13632 static void __exit
tg3_cleanup(void)
13634 pci_unregister_driver(&tg3_driver
);
13637 module_init(tg3_init
);
13638 module_exit(tg3_cleanup
);