arch/i386/power/cpu.c

   1 /*
   2  * Suspend support specific for i386.
   3  *
   4  * Distribute under GPLv2
   5  *
   6  * Copyright (c) 2002 Pavel Machek <pavel@suse.cz>
   7  * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
   8  */
   9
  10 #include <linux/config.h>
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/init.h>
  14 #include <linux/types.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/poll.h>
  17 #include <linux/delay.h>
  18 #include <linux/sysrq.h>
  19 #include <linux/proc_fs.h>
  20 #include <linux/irq.h>
  21 #include <linux/pm.h>
  22 #include <linux/device.h>
  23 #include <linux/suspend.h>
  24 #include <linux/acpi.h>
  25
  26 #include <asm/uaccess.h>
  27 #include <asm/acpi.h>
  28 #include <asm/tlbflush.h>
  29 #include <asm/processor.h>
  30
  31 static struct saved_context saved_context;
  32
  33 unsigned long saved_context_ebx;
  34 unsigned long saved_context_esp, saved_context_ebp;
  35 unsigned long saved_context_esi, saved_context_edi;
  36 unsigned long saved_context_eflags;
  37
  38 void __save_processor_state(struct saved_context *ctxt)
  39 {
  40         kernel_fpu_begin();
  41
  42         /*
  43          * descriptor tables
  44          */
  45         asm volatile ("sgdt %0" : "=m" (ctxt->gdt_limit));
  46         asm volatile ("sidt %0" : "=m" (ctxt->idt_limit));
  47         asm volatile ("str %0"  : "=m" (ctxt->tr));
  48
  49         /*
  50          * segment registers
  51          */
  52         asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
  53         asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
  54         asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
  55         asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
  56
  57         /*
  58          * control registers
  59          */
  60         asm volatile ("movl %%cr0, %0" : "=r" (ctxt->cr0));
  61         asm volatile ("movl %%cr2, %0" : "=r" (ctxt->cr2));
  62         asm volatile ("movl %%cr3, %0" : "=r" (ctxt->cr3));
  63         asm volatile ("movl %%cr4, %0" : "=r" (ctxt->cr4));
  64 }
  65
  66 void save_processor_state(void)
  67 {
  68         __save_processor_state(&saved_context);
  69 }
  70
  71 static void
  72 do_fpu_end(void)
  73 {
  74         /* restore FPU regs if necessary */
  75         /* Do it out of line so that gcc does not move cr0 load to some stupid place */
  76         kernel_fpu_end();
  77         mxcsr_feature_mask_init();
  78 }
  79
  80
  81 static void fix_processor_context(void)
  82 {
  83         int cpu = smp_processor_id();
  84         struct tss_struct * t = &per_cpu(init_tss, cpu);
  85
  86         set_tss_desc(cpu,t);    /* This just modifies memory; should not be necessary. But... This is necessary, because 386 hardware has concept of busy TSS or some similar stupidity. */
  87         per_cpu(cpu_gdt_table, cpu)[GDT_ENTRY_TSS].b &= 0xfffffdff;
  88
  89         load_TR_desc();                         /* This does ltr */
  90         load_LDT(&current->active_mm->context); /* This does lldt */
  91
  92         /*
  93          * Now maybe reload the debug registers
  94          */
  95         if (current->thread.debugreg[7]){
  96                 set_debugreg(current->thread.debugreg[0], 0);
  97                 set_debugreg(current->thread.debugreg[1], 1);
  98                 set_debugreg(current->thread.debugreg[2], 2);
  99                 set_debugreg(current->thread.debugreg[3], 3);
 100                 /* no 4 and 5 */
 101                 set_debugreg(current->thread.debugreg[6], 6);
 102                 set_debugreg(current->thread.debugreg[7], 7);
 103         }
 104
 105 }
 106
 107 void __restore_processor_state(struct saved_context *ctxt)
 108 {
 109         /*
 110          * control registers
 111          */
 112         asm volatile ("movl %0, %%cr4" :: "r" (ctxt->cr4));
 113         asm volatile ("movl %0, %%cr3" :: "r" (ctxt->cr3));
 114         asm volatile ("movl %0, %%cr2" :: "r" (ctxt->cr2));
 115         asm volatile ("movl %0, %%cr0" :: "r" (ctxt->cr0));
 116
 117         /*
 118          * now restore the descriptor tables to their proper values
 119          * ltr is done i fix_processor_context().
 120          */
 121         asm volatile ("lgdt %0" :: "m" (ctxt->gdt_limit));
 122         asm volatile ("lidt %0" :: "m" (ctxt->idt_limit));
 123
 124         /*
 125          * segment registers
 126          */
 127         asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
 128         asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
 129         asm volatile ("movw %0, %%gs" :: "r" (ctxt->gs));
 130         asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
 131
 132         /*
 133          * sysenter MSRs
 134          */
 135         if (boot_cpu_has(X86_FEATURE_SEP))
 136                 enable_sep_cpu();
 137
 138         fix_processor_context();
 139         do_fpu_end();
 140         mtrr_ap_init();
 141 }
 142
 143 void restore_processor_state(void)
 144 {
 145         __restore_processor_state(&saved_context);
 146 }
 147
 148 /* Needed by apm.c */
 149 EXPORT_SYMBOL(save_processor_state);
 150 EXPORT_SYMBOL(restore_processor_state);