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[PATCH] skge: fibre vs copper detection cleanup
[firewire-audio.git] / drivers / net / skge.c
blob3990829d3c4693e4ecc0b6505a015554d8fa7af3
1 /*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27 #include <linux/config.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/if_vlan.h>
36 #include <linux/ip.h>
37 #include <linux/delay.h>
38 #include <linux/crc32.h>
39 #include <linux/dma-mapping.h>
40 #include <asm/irq.h>
41
42 #include "skge.h"
43
44 #define DRV_NAME "skge"
45 #define DRV_VERSION "0.8"
46 #define PFX DRV_NAME " "
47
48 #define DEFAULT_TX_RING_SIZE 128
49 #define DEFAULT_RX_RING_SIZE 512
50 #define MAX_TX_RING_SIZE 1024
51 #define MAX_RX_RING_SIZE 4096
52 #define RX_COPY_THRESHOLD 128
53 #define RX_BUF_SIZE 1536
54 #define PHY_RETRIES 1000
55 #define ETH_JUMBO_MTU 9000
56 #define TX_WATCHDOG (5 * HZ)
57 #define NAPI_WEIGHT 64
58 #define BLINK_MS 250
59
60 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
61 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
62 MODULE_LICENSE("GPL");
63 MODULE_VERSION(DRV_VERSION);
64
65 static const u32 default_msg
66 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
67 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
68
69 static int debug = -1; /* defaults above */
70 module_param(debug, int, 0);
71 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
72
73 static const struct pci_device_id skge_id_table[] = {
74 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
75 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
76 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
77 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
78 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
79 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
80 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
81 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
82 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1032) },
83 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
84 { 0 }
85 };
86 MODULE_DEVICE_TABLE(pci, skge_id_table);
87
88 static int skge_up(struct net_device *dev);
89 static int skge_down(struct net_device *dev);
90 static void skge_tx_clean(struct skge_port *skge);
91 static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
92 static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
93 static void genesis_get_stats(struct skge_port *skge, u64 *data);
94 static void yukon_get_stats(struct skge_port *skge, u64 *data);
95 static void yukon_init(struct skge_hw *hw, int port);
96 static void yukon_reset(struct skge_hw *hw, int port);
97 static void genesis_mac_init(struct skge_hw *hw, int port);
98 static void genesis_reset(struct skge_hw *hw, int port);
99 static void genesis_link_up(struct skge_port *skge);
100
101 /* Avoid conditionals by using array */
102 static const int txqaddr[] = { Q_XA1, Q_XA2 };
103 static const int rxqaddr[] = { Q_R1, Q_R2 };
104 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
105 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
106 static const u32 portirqmask[] = { IS_PORT_1, IS_PORT_2 };
107
108 /* Don't need to look at whole 16K.
109 * last interesting register is descriptor poll timer.
110 */
111 #define SKGE_REGS_LEN (29*128)
112
113 static int skge_get_regs_len(struct net_device *dev)
114 {
115 return SKGE_REGS_LEN;
116 }
117
118 /*
119 * Returns copy of control register region
120 * I/O region is divided into banks and certain regions are unreadable
121 */
122 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
123 void *p)
124 {
125 const struct skge_port *skge = netdev_priv(dev);
126 unsigned long offs;
127 const void __iomem *io = skge->hw->regs;
128 static const unsigned long bankmap
129 = (1<<0) | (1<<2) | (1<<8) | (1<<9)
130 | (1<<12) | (1<<13) | (1<<14) | (1<<15) | (1<<16)
131 | (1<<17) | (1<<20) | (1<<21) | (1<<22) | (1<<23)
132 | (1<<24) | (1<<25) | (1<<26) | (1<<27) | (1<<28);
133
134 regs->version = 1;
135 for (offs = 0; offs < regs->len; offs += 128) {
136 u32 len = min_t(u32, 128, regs->len - offs);
137
138 if (bankmap & (1<<(offs/128)))
139 memcpy_fromio(p + offs, io + offs, len);
140 else
141 memset(p + offs, 0, len);
142 }
143 }
144
145 /* Wake on Lan only supported on Yukon chps with rev 1 or above */
146 static int wol_supported(const struct skge_hw *hw)
147 {
148 return !((hw->chip_id == CHIP_ID_GENESIS ||
149 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
150 }
151
152 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
153 {
154 struct skge_port *skge = netdev_priv(dev);
155
156 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
157 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
158 }
159
160 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
161 {
162 struct skge_port *skge = netdev_priv(dev);
163 struct skge_hw *hw = skge->hw;
164
165 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
166 return -EOPNOTSUPP;
167
168 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
169 return -EOPNOTSUPP;
170
171 skge->wol = wol->wolopts == WAKE_MAGIC;
172
173 if (skge->wol) {
174 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
175
176 skge_write16(hw, WOL_CTRL_STAT,
177 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
178 WOL_CTL_ENA_MAGIC_PKT_UNIT);
179 } else
180 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
181
182 return 0;
183 }
184
185 /* Determine supported/adverised modes based on hardware.
186 * Note: ethtoool ADVERTISED_xxx == SUPPORTED_xxx
187 */
188 static u32 skge_supported_modes(const struct skge_hw *hw)
189 {
190 u32 supported;
191
192 if (hw->copper) {
193 supported = SUPPORTED_10baseT_Half
194 | SUPPORTED_10baseT_Full
195 | SUPPORTED_100baseT_Half
196 | SUPPORTED_100baseT_Full
197 | SUPPORTED_1000baseT_Half
198 | SUPPORTED_1000baseT_Full
199 | SUPPORTED_Autoneg| SUPPORTED_TP;
200
201 if (hw->chip_id == CHIP_ID_GENESIS)
202 supported &= ~(SUPPORTED_10baseT_Half
203 | SUPPORTED_10baseT_Full
204 | SUPPORTED_100baseT_Half
205 | SUPPORTED_100baseT_Full);
206
207 else if (hw->chip_id == CHIP_ID_YUKON)
208 supported &= ~SUPPORTED_1000baseT_Half;
209 } else
210 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
211 | SUPPORTED_Autoneg;
212
213 return supported;
214 }
215
216 static int skge_get_settings(struct net_device *dev,
217 struct ethtool_cmd *ecmd)
218 {
219 struct skge_port *skge = netdev_priv(dev);
220 struct skge_hw *hw = skge->hw;
221
222 ecmd->transceiver = XCVR_INTERNAL;
223 ecmd->supported = skge_supported_modes(hw);
224
225 if (hw->copper) {
226 ecmd->port = PORT_TP;
227 ecmd->phy_address = hw->phy_addr;
228 } else
229 ecmd->port = PORT_FIBRE;
230
231 ecmd->advertising = skge->advertising;
232 ecmd->autoneg = skge->autoneg;
233 ecmd->speed = skge->speed;
234 ecmd->duplex = skge->duplex;
235 return 0;
236 }
237
238 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
239 {
240 struct skge_port *skge = netdev_priv(dev);
241 const struct skge_hw *hw = skge->hw;
242 u32 supported = skge_supported_modes(hw);
243
244 if (ecmd->autoneg == AUTONEG_ENABLE) {
245 ecmd->advertising = supported;
246 skge->duplex = -1;
247 skge->speed = -1;
248 } else {
249 u32 setting;
250
251 switch (ecmd->speed) {
252 case SPEED_1000:
253 if (ecmd->duplex == DUPLEX_FULL)
254 setting = SUPPORTED_1000baseT_Full;
255 else if (ecmd->duplex == DUPLEX_HALF)
256 setting = SUPPORTED_1000baseT_Half;
257 else
258 return -EINVAL;
259 break;
260 case SPEED_100:
261 if (ecmd->duplex == DUPLEX_FULL)
262 setting = SUPPORTED_100baseT_Full;
263 else if (ecmd->duplex == DUPLEX_HALF)
264 setting = SUPPORTED_100baseT_Half;
265 else
266 return -EINVAL;
267 break;
268
269 case SPEED_10:
270 if (ecmd->duplex == DUPLEX_FULL)
271 setting = SUPPORTED_10baseT_Full;
272 else if (ecmd->duplex == DUPLEX_HALF)
273 setting = SUPPORTED_10baseT_Half;
274 else
275 return -EINVAL;
276 break;
277 default:
278 return -EINVAL;
279 }
280
281 if ((setting & supported) == 0)
282 return -EINVAL;
283
284 skge->speed = ecmd->speed;
285 skge->duplex = ecmd->duplex;
286 }
287
288 skge->autoneg = ecmd->autoneg;
289 skge->advertising = ecmd->advertising;
290
291 if (netif_running(dev)) {
292 skge_down(dev);
293 skge_up(dev);
294 }
295 return (0);
296 }
297
298 static void skge_get_drvinfo(struct net_device *dev,
299 struct ethtool_drvinfo *info)
300 {
301 struct skge_port *skge = netdev_priv(dev);
302
303 strcpy(info->driver, DRV_NAME);
304 strcpy(info->version, DRV_VERSION);
305 strcpy(info->fw_version, "N/A");
306 strcpy(info->bus_info, pci_name(skge->hw->pdev));
307 }
308
309 static const struct skge_stat {
310 char name[ETH_GSTRING_LEN];
311 u16 xmac_offset;
312 u16 gma_offset;
313 } skge_stats[] = {
314 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
315 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
316
317 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
318 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
319 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
320 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
321 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
322 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
323 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
324 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
325
326 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
327 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
328 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
329 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
330 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
331 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
332
333 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
334 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
335 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
336 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
337 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
338 };
339
340 static int skge_get_stats_count(struct net_device *dev)
341 {
342 return ARRAY_SIZE(skge_stats);
343 }
344
345 static void skge_get_ethtool_stats(struct net_device *dev,
346 struct ethtool_stats *stats, u64 *data)
347 {
348 struct skge_port *skge = netdev_priv(dev);
349
350 if (skge->hw->chip_id == CHIP_ID_GENESIS)
351 genesis_get_stats(skge, data);
352 else
353 yukon_get_stats(skge, data);
354 }
355
356 /* Use hardware MIB variables for critical path statistics and
357 * transmit feedback not reported at interrupt.
358 * Other errors are accounted for in interrupt handler.
359 */
360 static struct net_device_stats *skge_get_stats(struct net_device *dev)
361 {
362 struct skge_port *skge = netdev_priv(dev);
363 u64 data[ARRAY_SIZE(skge_stats)];
364
365 if (skge->hw->chip_id == CHIP_ID_GENESIS)
366 genesis_get_stats(skge, data);
367 else
368 yukon_get_stats(skge, data);
369
370 skge->net_stats.tx_bytes = data[0];
371 skge->net_stats.rx_bytes = data[1];
372 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
373 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
374 skge->net_stats.multicast = data[5] + data[7];
375 skge->net_stats.collisions = data[10];
376 skge->net_stats.tx_aborted_errors = data[12];
377
378 return &skge->net_stats;
379 }
380
381 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
382 {
383 int i;
384
385 switch (stringset) {
386 case ETH_SS_STATS:
387 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
388 memcpy(data + i * ETH_GSTRING_LEN,
389 skge_stats[i].name, ETH_GSTRING_LEN);
390 break;
391 }
392 }
393
394 static void skge_get_ring_param(struct net_device *dev,
395 struct ethtool_ringparam *p)
396 {
397 struct skge_port *skge = netdev_priv(dev);
398
399 p->rx_max_pending = MAX_RX_RING_SIZE;
400 p->tx_max_pending = MAX_TX_RING_SIZE;
401 p->rx_mini_max_pending = 0;
402 p->rx_jumbo_max_pending = 0;
403
404 p->rx_pending = skge->rx_ring.count;
405 p->tx_pending = skge->tx_ring.count;
406 p->rx_mini_pending = 0;
407 p->rx_jumbo_pending = 0;
408 }
409
410 static int skge_set_ring_param(struct net_device *dev,
411 struct ethtool_ringparam *p)
412 {
413 struct skge_port *skge = netdev_priv(dev);
414
415 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
416 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
417 return -EINVAL;
418
419 skge->rx_ring.count = p->rx_pending;
420 skge->tx_ring.count = p->tx_pending;
421
422 if (netif_running(dev)) {
423 skge_down(dev);
424 skge_up(dev);
425 }
426
427 return 0;
428 }
429
430 static u32 skge_get_msglevel(struct net_device *netdev)
431 {
432 struct skge_port *skge = netdev_priv(netdev);
433 return skge->msg_enable;
434 }
435
436 static void skge_set_msglevel(struct net_device *netdev, u32 value)
437 {
438 struct skge_port *skge = netdev_priv(netdev);
439 skge->msg_enable = value;
440 }
441
442 static int skge_nway_reset(struct net_device *dev)
443 {
444 struct skge_port *skge = netdev_priv(dev);
445 struct skge_hw *hw = skge->hw;
446 int port = skge->port;
447
448 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
449 return -EINVAL;
450
451 spin_lock_bh(&hw->phy_lock);
452 if (hw->chip_id == CHIP_ID_GENESIS) {
453 genesis_reset(hw, port);
454 genesis_mac_init(hw, port);
455 } else {
456 yukon_reset(hw, port);
457 yukon_init(hw, port);
458 }
459 spin_unlock_bh(&hw->phy_lock);
460 return 0;
461 }
462
463 static int skge_set_sg(struct net_device *dev, u32 data)
464 {
465 struct skge_port *skge = netdev_priv(dev);
466 struct skge_hw *hw = skge->hw;
467
468 if (hw->chip_id == CHIP_ID_GENESIS && data)
469 return -EOPNOTSUPP;
470 return ethtool_op_set_sg(dev, data);
471 }
472
473 static int skge_set_tx_csum(struct net_device *dev, u32 data)
474 {
475 struct skge_port *skge = netdev_priv(dev);
476 struct skge_hw *hw = skge->hw;
477
478 if (hw->chip_id == CHIP_ID_GENESIS && data)
479 return -EOPNOTSUPP;
480
481 return ethtool_op_set_tx_csum(dev, data);
482 }
483
484 static u32 skge_get_rx_csum(struct net_device *dev)
485 {
486 struct skge_port *skge = netdev_priv(dev);
487
488 return skge->rx_csum;
489 }
490
491 /* Only Yukon supports checksum offload. */
492 static int skge_set_rx_csum(struct net_device *dev, u32 data)
493 {
494 struct skge_port *skge = netdev_priv(dev);
495
496 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
497 return -EOPNOTSUPP;
498
499 skge->rx_csum = data;
500 return 0;
501 }
502
503 static void skge_get_pauseparam(struct net_device *dev,
504 struct ethtool_pauseparam *ecmd)
505 {
506 struct skge_port *skge = netdev_priv(dev);
507
508 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
509 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
510 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
511 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
512
513 ecmd->autoneg = skge->autoneg;
514 }
515
516 static int skge_set_pauseparam(struct net_device *dev,
517 struct ethtool_pauseparam *ecmd)
518 {
519 struct skge_port *skge = netdev_priv(dev);
520
521 skge->autoneg = ecmd->autoneg;
522 if (ecmd->rx_pause && ecmd->tx_pause)
523 skge->flow_control = FLOW_MODE_SYMMETRIC;
524 else if (ecmd->rx_pause && !ecmd->tx_pause)
525 skge->flow_control = FLOW_MODE_REM_SEND;
526 else if (!ecmd->rx_pause && ecmd->tx_pause)
527 skge->flow_control = FLOW_MODE_LOC_SEND;
528 else
529 skge->flow_control = FLOW_MODE_NONE;
530
531 if (netif_running(dev)) {
532 skge_down(dev);
533 skge_up(dev);
534 }
535 return 0;
536 }
537
538 /* Chip internal frequency for clock calculations */
539 static inline u32 hwkhz(const struct skge_hw *hw)
540 {
541 if (hw->chip_id == CHIP_ID_GENESIS)
542 return 53215; /* or: 53.125 MHz */
543 else
544 return 78215; /* or: 78.125 MHz */
545 }
546
547 /* Chip hz to microseconds */
548 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
549 {
550 return (ticks * 1000) / hwkhz(hw);
551 }
552
553 /* Microseconds to chip hz */
554 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
555 {
556 return hwkhz(hw) * usec / 1000;
557 }
558
559 static int skge_get_coalesce(struct net_device *dev,
560 struct ethtool_coalesce *ecmd)
561 {
562 struct skge_port *skge = netdev_priv(dev);
563 struct skge_hw *hw = skge->hw;
564 int port = skge->port;
565
566 ecmd->rx_coalesce_usecs = 0;
567 ecmd->tx_coalesce_usecs = 0;
568
569 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
570 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
571 u32 msk = skge_read32(hw, B2_IRQM_MSK);
572
573 if (msk & rxirqmask[port])
574 ecmd->rx_coalesce_usecs = delay;
575 if (msk & txirqmask[port])
576 ecmd->tx_coalesce_usecs = delay;
577 }
578
579 return 0;
580 }
581
582 /* Note: interrupt timer is per board, but can turn on/off per port */
583 static int skge_set_coalesce(struct net_device *dev,
584 struct ethtool_coalesce *ecmd)
585 {
586 struct skge_port *skge = netdev_priv(dev);
587 struct skge_hw *hw = skge->hw;
588 int port = skge->port;
589 u32 msk = skge_read32(hw, B2_IRQM_MSK);
590 u32 delay = 25;
591
592 if (ecmd->rx_coalesce_usecs == 0)
593 msk &= ~rxirqmask[port];
594 else if (ecmd->rx_coalesce_usecs < 25 ||
595 ecmd->rx_coalesce_usecs > 33333)
596 return -EINVAL;
597 else {
598 msk |= rxirqmask[port];
599 delay = ecmd->rx_coalesce_usecs;
600 }
601
602 if (ecmd->tx_coalesce_usecs == 0)
603 msk &= ~txirqmask[port];
604 else if (ecmd->tx_coalesce_usecs < 25 ||
605 ecmd->tx_coalesce_usecs > 33333)
606 return -EINVAL;
607 else {
608 msk |= txirqmask[port];
609 delay = min(delay, ecmd->rx_coalesce_usecs);
610 }
611
612 skge_write32(hw, B2_IRQM_MSK, msk);
613 if (msk == 0)
614 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
615 else {
616 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
617 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
618 }
619 return 0;
620 }
621
622 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
623 static void skge_led(struct skge_port *skge, enum led_mode mode)
624 {
625 struct skge_hw *hw = skge->hw;
626 int port = skge->port;
627
628 spin_lock_bh(&hw->phy_lock);
629 if (hw->chip_id == CHIP_ID_GENESIS) {
630 switch (mode) {
631 case LED_MODE_OFF:
632 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
633 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
634 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
635 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
636 break;
637
638 case LED_MODE_ON:
639 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
640 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
641
642 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
643 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
644
645 break;
646
647 case LED_MODE_TST:
648 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
649 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
650 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
651
652 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
653 break;
654 }
655 } else {
656 switch (mode) {
657 case LED_MODE_OFF:
658 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
659 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
660 PHY_M_LED_MO_DUP(MO_LED_OFF) |
661 PHY_M_LED_MO_10(MO_LED_OFF) |
662 PHY_M_LED_MO_100(MO_LED_OFF) |
663 PHY_M_LED_MO_1000(MO_LED_OFF) |
664 PHY_M_LED_MO_RX(MO_LED_OFF));
665 break;
666 case LED_MODE_ON:
667 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
668 PHY_M_LED_PULS_DUR(PULS_170MS) |
669 PHY_M_LED_BLINK_RT(BLINK_84MS) |
670 PHY_M_LEDC_TX_CTRL |
671 PHY_M_LEDC_DP_CTRL);
672
673 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
674 PHY_M_LED_MO_RX(MO_LED_OFF) |
675 (skge->speed == SPEED_100 ?
676 PHY_M_LED_MO_100(MO_LED_ON) : 0));
677 break;
678 case LED_MODE_TST:
679 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
680 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
681 PHY_M_LED_MO_DUP(MO_LED_ON) |
682 PHY_M_LED_MO_10(MO_LED_ON) |
683 PHY_M_LED_MO_100(MO_LED_ON) |
684 PHY_M_LED_MO_1000(MO_LED_ON) |
685 PHY_M_LED_MO_RX(MO_LED_ON));
686 }
687 }
688 spin_unlock_bh(&hw->phy_lock);
689 }
690
691 /* blink LED's for finding board */
692 static int skge_phys_id(struct net_device *dev, u32 data)
693 {
694 struct skge_port *skge = netdev_priv(dev);
695 unsigned long ms;
696 enum led_mode mode = LED_MODE_TST;
697
698 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
699 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
700 else
701 ms = data * 1000;
702
703 while (ms > 0) {
704 skge_led(skge, mode);
705 mode ^= LED_MODE_TST;
706
707 if (msleep_interruptible(BLINK_MS))
708 break;
709 ms -= BLINK_MS;
710 }
711
712 /* back to regular LED state */
713 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
714
715 return 0;
716 }
717
718 static struct ethtool_ops skge_ethtool_ops = {
719 .get_settings = skge_get_settings,
720 .set_settings = skge_set_settings,
721 .get_drvinfo = skge_get_drvinfo,
722 .get_regs_len = skge_get_regs_len,
723 .get_regs = skge_get_regs,
724 .get_wol = skge_get_wol,
725 .set_wol = skge_set_wol,
726 .get_msglevel = skge_get_msglevel,
727 .set_msglevel = skge_set_msglevel,
728 .nway_reset = skge_nway_reset,
729 .get_link = ethtool_op_get_link,
730 .get_ringparam = skge_get_ring_param,
731 .set_ringparam = skge_set_ring_param,
732 .get_pauseparam = skge_get_pauseparam,
733 .set_pauseparam = skge_set_pauseparam,
734 .get_coalesce = skge_get_coalesce,
735 .set_coalesce = skge_set_coalesce,
736 .get_sg = ethtool_op_get_sg,
737 .set_sg = skge_set_sg,
738 .get_tx_csum = ethtool_op_get_tx_csum,
739 .set_tx_csum = skge_set_tx_csum,
740 .get_rx_csum = skge_get_rx_csum,
741 .set_rx_csum = skge_set_rx_csum,
742 .get_strings = skge_get_strings,
743 .phys_id = skge_phys_id,
744 .get_stats_count = skge_get_stats_count,
745 .get_ethtool_stats = skge_get_ethtool_stats,
746 };
747
748 /*
749 * Allocate ring elements and chain them together
750 * One-to-one association of board descriptors with ring elements
751 */
752 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
753 {
754 struct skge_tx_desc *d;
755 struct skge_element *e;
756 int i;
757
758 ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
759 if (!ring->start)
760 return -ENOMEM;
761
762 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
763 e->desc = d;
764 e->skb = NULL;
765 if (i == ring->count - 1) {
766 e->next = ring->start;
767 d->next_offset = base;
768 } else {
769 e->next = e + 1;
770 d->next_offset = base + (i+1) * sizeof(*d);
771 }
772 }
773 ring->to_use = ring->to_clean = ring->start;
774
775 return 0;
776 }
777
778 static struct sk_buff *skge_rx_alloc(struct net_device *dev, unsigned int size)
779 {
780 struct sk_buff *skb = dev_alloc_skb(size);
781
782 if (likely(skb)) {
783 skb->dev = dev;
784 skb_reserve(skb, NET_IP_ALIGN);
785 }
786 return skb;
787 }
788
789 /* Allocate and setup a new buffer for receiving */
790 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
791 struct sk_buff *skb, unsigned int bufsize)
792 {
793 struct skge_rx_desc *rd = e->desc;
794 u64 map;
795
796 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
797 PCI_DMA_FROMDEVICE);
798
799 rd->dma_lo = map;
800 rd->dma_hi = map >> 32;
801 e->skb = skb;
802 rd->csum1_start = ETH_HLEN;
803 rd->csum2_start = ETH_HLEN;
804 rd->csum1 = 0;
805 rd->csum2 = 0;
806
807 wmb();
808
809 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
810 pci_unmap_addr_set(e, mapaddr, map);
811 pci_unmap_len_set(e, maplen, bufsize);
812 }
813
814 /* Resume receiving using existing skb,
815 * Note: DMA address is not changed by chip.
816 * MTU not changed while receiver active.
817 */
818 static void skge_rx_reuse(struct skge_element *e, unsigned int size)
819 {
820 struct skge_rx_desc *rd = e->desc;
821
822 rd->csum2 = 0;
823 rd->csum2_start = ETH_HLEN;
824
825 wmb();
826
827 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
828 }
829
830
831 /* Free all buffers in receive ring, assumes receiver stopped */
832 static void skge_rx_clean(struct skge_port *skge)
833 {
834 struct skge_hw *hw = skge->hw;
835 struct skge_ring *ring = &skge->rx_ring;
836 struct skge_element *e;
837
838 e = ring->start;
839 do {
840 struct skge_rx_desc *rd = e->desc;
841 rd->control = 0;
842 if (e->skb) {
843 pci_unmap_single(hw->pdev,
844 pci_unmap_addr(e, mapaddr),
845 pci_unmap_len(e, maplen),
846 PCI_DMA_FROMDEVICE);
847 dev_kfree_skb(e->skb);
848 e->skb = NULL;
849 }
850 } while ((e = e->next) != ring->start);
851 }
852
853
854 /* Allocate buffers for receive ring
855 * For receive: to_clean is next received frame.
856 */
857 static int skge_rx_fill(struct skge_port *skge)
858 {
859 struct skge_ring *ring = &skge->rx_ring;
860 struct skge_element *e;
861 unsigned int bufsize = skge->rx_buf_size;
862
863 e = ring->start;
864 do {
865 struct sk_buff *skb = skge_rx_alloc(skge->netdev, bufsize);
866
867 if (!skb)
868 return -ENOMEM;
869
870 skge_rx_setup(skge, e, skb, bufsize);
871 } while ( (e = e->next) != ring->start);
872
873 ring->to_clean = ring->start;
874 return 0;
875 }
876
877 static void skge_link_up(struct skge_port *skge)
878 {
879 netif_carrier_on(skge->netdev);
880 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
881 netif_wake_queue(skge->netdev);
882
883 if (netif_msg_link(skge))
884 printk(KERN_INFO PFX
885 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
886 skge->netdev->name, skge->speed,
887 skge->duplex == DUPLEX_FULL ? "full" : "half",
888 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
889 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
890 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
891 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
892 "unknown");
893 }
894
895 static void skge_link_down(struct skge_port *skge)
896 {
897 netif_carrier_off(skge->netdev);
898 netif_stop_queue(skge->netdev);
899
900 if (netif_msg_link(skge))
901 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
902 }
903
904 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
905 {
906 int i;
907 u16 v;
908
909 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
910 v = xm_read16(hw, port, XM_PHY_DATA);
911
912 /* Need to wait for external PHY */
913 for (i = 0; i < PHY_RETRIES; i++) {
914 udelay(1);
915 if (xm_read16(hw, port, XM_MMU_CMD)
916 & XM_MMU_PHY_RDY)
917 goto ready;
918 }
919
920 printk(KERN_WARNING PFX "%s: phy read timed out\n",
921 hw->dev[port]->name);
922 return 0;
923 ready:
924 v = xm_read16(hw, port, XM_PHY_DATA);
925
926 return v;
927 }
928
929 static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
930 {
931 int i;
932
933 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
934 for (i = 0; i < PHY_RETRIES; i++) {
935 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
936 goto ready;
937 udelay(1);
938 }
939 printk(KERN_WARNING PFX "%s: phy write failed to come ready\n",
940 hw->dev[port]->name);
941
942
943 ready:
944 xm_write16(hw, port, XM_PHY_DATA, val);
945 for (i = 0; i < PHY_RETRIES; i++) {
946 udelay(1);
947 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
948 return;
949 }
950 printk(KERN_WARNING PFX "%s: phy write timed out\n",
951 hw->dev[port]->name);
952 }
953
954 static void genesis_init(struct skge_hw *hw)
955 {
956 /* set blink source counter */
957 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
958 skge_write8(hw, B2_BSC_CTRL, BSC_START);
959
960 /* configure mac arbiter */
961 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
962
963 /* configure mac arbiter timeout values */
964 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
965 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
966 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
967 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
968
969 skge_write8(hw, B3_MA_RCINI_RX1, 0);
970 skge_write8(hw, B3_MA_RCINI_RX2, 0);
971 skge_write8(hw, B3_MA_RCINI_TX1, 0);
972 skge_write8(hw, B3_MA_RCINI_TX2, 0);
973
974 /* configure packet arbiter timeout */
975 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
976 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
977 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
978 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
979 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
980 }
981
982 static void genesis_reset(struct skge_hw *hw, int port)
983 {
984 const u8 zero[8] = { 0 };
985
986 /* reset the statistics module */
987 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
988 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
989 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
990 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
991 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
992
993 /* disable Broadcom PHY IRQ */
994 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
995
996 xm_outhash(hw, port, XM_HSM, zero);
997 }
998
999
1000 /* Convert mode to MII values */
1001 static const u16 phy_pause_map[] = {
1002 [FLOW_MODE_NONE] = 0,
1003 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1004 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1005 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1006 };
1007
1008
1009 /* Check status of Broadcom phy link */
1010 static void bcom_check_link(struct skge_hw *hw, int port)
1011 {
1012 struct net_device *dev = hw->dev[port];
1013 struct skge_port *skge = netdev_priv(dev);
1014 u16 status;
1015
1016 /* read twice because of latch */
1017 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
1018 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1019
1020 pr_debug("bcom_check_link status=0x%x\n", status);
1021
1022 if ((status & PHY_ST_LSYNC) == 0) {
1023 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
1024 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1025 xm_write16(hw, port, XM_MMU_CMD, cmd);
1026 /* dummy read to ensure writing */
1027 (void) xm_read16(hw, port, XM_MMU_CMD);
1028
1029 if (netif_carrier_ok(dev))
1030 skge_link_down(skge);
1031 } else {
1032 if (skge->autoneg == AUTONEG_ENABLE &&
1033 (status & PHY_ST_AN_OVER)) {
1034 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1035 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1036
1037 if (lpa & PHY_B_AN_RF) {
1038 printk(KERN_NOTICE PFX "%s: remote fault\n",
1039 dev->name);
1040 return;
1041 }
1042
1043 /* Check Duplex mismatch */
1044 switch (aux & PHY_B_AS_AN_RES_MSK) {
1045 case PHY_B_RES_1000FD:
1046 skge->duplex = DUPLEX_FULL;
1047 break;
1048 case PHY_B_RES_1000HD:
1049 skge->duplex = DUPLEX_HALF;
1050 break;
1051 default:
1052 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1053 dev->name);
1054 return;
1055 }
1056
1057
1058 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1059 switch (aux & PHY_B_AS_PAUSE_MSK) {
1060 case PHY_B_AS_PAUSE_MSK:
1061 skge->flow_control = FLOW_MODE_SYMMETRIC;
1062 break;
1063 case PHY_B_AS_PRR:
1064 skge->flow_control = FLOW_MODE_REM_SEND;
1065 break;
1066 case PHY_B_AS_PRT:
1067 skge->flow_control = FLOW_MODE_LOC_SEND;
1068 break;
1069 default:
1070 skge->flow_control = FLOW_MODE_NONE;
1071 }
1072
1073 skge->speed = SPEED_1000;
1074 }
1075
1076 if (!netif_carrier_ok(dev))
1077 genesis_link_up(skge);
1078 }
1079 }
1080
1081 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1082 * Phy on for 100 or 10Mbit operation
1083 */
1084 static void bcom_phy_init(struct skge_port *skge, int jumbo)
1085 {
1086 struct skge_hw *hw = skge->hw;
1087 int port = skge->port;
1088 int i;
1089 u16 id1, r, ext, ctl;
1090
1091 /* magic workaround patterns for Broadcom */
1092 static const struct {
1093 u16 reg;
1094 u16 val;
1095 } A1hack[] = {
1096 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1097 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1098 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1099 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1100 }, C0hack[] = {
1101 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1102 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1103 };
1104
1105 pr_debug("bcom_phy_init\n");
1106
1107 /* read Id from external PHY (all have the same address) */
1108 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1109
1110 /* Optimize MDIO transfer by suppressing preamble. */
1111 r = xm_read16(hw, port, XM_MMU_CMD);
1112 r |= XM_MMU_NO_PRE;
1113 xm_write16(hw, port, XM_MMU_CMD,r);
1114
1115 switch (id1) {
1116 case PHY_BCOM_ID1_C0:
1117 /*
1118 * Workaround BCOM Errata for the C0 type.
1119 * Write magic patterns to reserved registers.
1120 */
1121 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1122 xm_phy_write(hw, port,
1123 C0hack[i].reg, C0hack[i].val);
1124
1125 break;
1126 case PHY_BCOM_ID1_A1:
1127 /*
1128 * Workaround BCOM Errata for the A1 type.
1129 * Write magic patterns to reserved registers.
1130 */
1131 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1132 xm_phy_write(hw, port,
1133 A1hack[i].reg, A1hack[i].val);
1134 break;
1135 }
1136
1137 /*
1138 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1139 * Disable Power Management after reset.
1140 */
1141 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1142 r |= PHY_B_AC_DIS_PM;
1143 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1144
1145 /* Dummy read */
1146 xm_read16(hw, port, XM_ISRC);
1147
1148 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1149 ctl = PHY_CT_SP1000; /* always 1000mbit */
1150
1151 if (skge->autoneg == AUTONEG_ENABLE) {
1152 /*
1153 * Workaround BCOM Errata #1 for the C5 type.
1154 * 1000Base-T Link Acquisition Failure in Slave Mode
1155 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1156 */
1157 u16 adv = PHY_B_1000C_RD;
1158 if (skge->advertising & ADVERTISED_1000baseT_Half)
1159 adv |= PHY_B_1000C_AHD;
1160 if (skge->advertising & ADVERTISED_1000baseT_Full)
1161 adv |= PHY_B_1000C_AFD;
1162 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1163
1164 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1165 } else {
1166 if (skge->duplex == DUPLEX_FULL)
1167 ctl |= PHY_CT_DUP_MD;
1168 /* Force to slave */
1169 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1170 }
1171
1172 /* Set autonegotiation pause parameters */
1173 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1174 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1175
1176 /* Handle Jumbo frames */
1177 if (jumbo) {
1178 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1179 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1180
1181 ext |= PHY_B_PEC_HIGH_LA;
1182
1183 }
1184
1185 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1186 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1187
1188 /* Use link status change interrrupt */
1189 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1190
1191 bcom_check_link(hw, port);
1192 }
1193
1194 static void genesis_mac_init(struct skge_hw *hw, int port)
1195 {
1196 struct net_device *dev = hw->dev[port];
1197 struct skge_port *skge = netdev_priv(dev);
1198 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1199 int i;
1200 u32 r;
1201 const u8 zero[6] = { 0 };
1202
1203 /* Clear MIB counters */
1204 xm_write16(hw, port, XM_STAT_CMD,
1205 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1206 /* Clear two times according to Errata #3 */
1207 xm_write16(hw, port, XM_STAT_CMD,
1208 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1209
1210 /* Unreset the XMAC. */
1211 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1212
1213 /*
1214 * Perform additional initialization for external PHYs,
1215 * namely for the 1000baseTX cards that use the XMAC's
1216 * GMII mode.
1217 */
1218 /* Take external Phy out of reset */
1219 r = skge_read32(hw, B2_GP_IO);
1220 if (port == 0)
1221 r |= GP_DIR_0|GP_IO_0;
1222 else
1223 r |= GP_DIR_2|GP_IO_2;
1224
1225 skge_write32(hw, B2_GP_IO, r);
1226 skge_read32(hw, B2_GP_IO);
1227
1228 /* Enable GMII interfac */
1229 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1230
1231 bcom_phy_init(skge, jumbo);
1232
1233 /* Set Station Address */
1234 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1235
1236 /* We don't use match addresses so clear */
1237 for (i = 1; i < 16; i++)
1238 xm_outaddr(hw, port, XM_EXM(i), zero);
1239
1240 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1241 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1242
1243 /* We don't need the FCS appended to the packet. */
1244 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1245 if (jumbo)
1246 r |= XM_RX_BIG_PK_OK;
1247
1248 if (skge->duplex == DUPLEX_HALF) {
1249 /*
1250 * If in manual half duplex mode the other side might be in
1251 * full duplex mode, so ignore if a carrier extension is not seen
1252 * on frames received
1253 */
1254 r |= XM_RX_DIS_CEXT;
1255 }
1256 xm_write16(hw, port, XM_RX_CMD, r);
1257
1258
1259 /* We want short frames padded to 60 bytes. */
1260 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1261
1262 /*
1263 * Bump up the transmit threshold. This helps hold off transmit
1264 * underruns when we're blasting traffic from both ports at once.
1265 */
1266 xm_write16(hw, port, XM_TX_THR, 512);
1267
1268 /*
1269 * Enable the reception of all error frames. This is is
1270 * a necessary evil due to the design of the XMAC. The
1271 * XMAC's receive FIFO is only 8K in size, however jumbo
1272 * frames can be up to 9000 bytes in length. When bad
1273 * frame filtering is enabled, the XMAC's RX FIFO operates
1274 * in 'store and forward' mode. For this to work, the
1275 * entire frame has to fit into the FIFO, but that means
1276 * that jumbo frames larger than 8192 bytes will be
1277 * truncated. Disabling all bad frame filtering causes
1278 * the RX FIFO to operate in streaming mode, in which
1279 * case the XMAC will start transfering frames out of the
1280 * RX FIFO as soon as the FIFO threshold is reached.
1281 */
1282 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1283
1284
1285 /*
1286 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1287 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1288 * and 'Octets Rx OK Hi Cnt Ov'.
1289 */
1290 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1291
1292 /*
1293 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1294 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1295 * and 'Octets Tx OK Hi Cnt Ov'.
1296 */
1297 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1298
1299 /* Configure MAC arbiter */
1300 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1301
1302 /* configure timeout values */
1303 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1304 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1305 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1306 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1307
1308 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1309 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1310 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1311 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1312
1313 /* Configure Rx MAC FIFO */
1314 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1315 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1316 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1317
1318 /* Configure Tx MAC FIFO */
1319 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1320 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1321 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1322
1323 if (jumbo) {
1324 /* Enable frame flushing if jumbo frames used */
1325 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1326 } else {
1327 /* enable timeout timers if normal frames */
1328 skge_write16(hw, B3_PA_CTRL,
1329 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1330 }
1331 }
1332
1333 static void genesis_stop(struct skge_port *skge)
1334 {
1335 struct skge_hw *hw = skge->hw;
1336 int port = skge->port;
1337 u32 reg;
1338
1339 /* Clear Tx packet arbiter timeout IRQ */
1340 skge_write16(hw, B3_PA_CTRL,
1341 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1342
1343 /*
1344 * If the transfer stucks at the MAC the STOP command will not
1345 * terminate if we don't flush the XMAC's transmit FIFO !
1346 */
1347 xm_write32(hw, port, XM_MODE,
1348 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1349
1350
1351 /* Reset the MAC */
1352 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1353
1354 /* For external PHYs there must be special handling */
1355 reg = skge_read32(hw, B2_GP_IO);
1356 if (port == 0) {
1357 reg |= GP_DIR_0;
1358 reg &= ~GP_IO_0;
1359 } else {
1360 reg |= GP_DIR_2;
1361 reg &= ~GP_IO_2;
1362 }
1363 skge_write32(hw, B2_GP_IO, reg);
1364 skge_read32(hw, B2_GP_IO);
1365
1366 xm_write16(hw, port, XM_MMU_CMD,
1367 xm_read16(hw, port, XM_MMU_CMD)
1368 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1369
1370 xm_read16(hw, port, XM_MMU_CMD);
1371 }
1372
1373
1374 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1375 {
1376 struct skge_hw *hw = skge->hw;
1377 int port = skge->port;
1378 int i;
1379 unsigned long timeout = jiffies + HZ;
1380
1381 xm_write16(hw, port,
1382 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1383
1384 /* wait for update to complete */
1385 while (xm_read16(hw, port, XM_STAT_CMD)
1386 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1387 if (time_after(jiffies, timeout))
1388 break;
1389 udelay(10);
1390 }
1391
1392 /* special case for 64 bit octet counter */
1393 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1394 | xm_read32(hw, port, XM_TXO_OK_LO);
1395 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1396 | xm_read32(hw, port, XM_RXO_OK_LO);
1397
1398 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1399 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1400 }
1401
1402 static void genesis_mac_intr(struct skge_hw *hw, int port)
1403 {
1404 struct skge_port *skge = netdev_priv(hw->dev[port]);
1405 u16 status = xm_read16(hw, port, XM_ISRC);
1406
1407 if (netif_msg_intr(skge))
1408 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1409 skge->netdev->name, status);
1410
1411 if (status & XM_IS_TXF_UR) {
1412 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1413 ++skge->net_stats.tx_fifo_errors;
1414 }
1415 if (status & XM_IS_RXF_OV) {
1416 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1417 ++skge->net_stats.rx_fifo_errors;
1418 }
1419 }
1420
1421 static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1422 {
1423 int i;
1424
1425 gma_write16(hw, port, GM_SMI_DATA, val);
1426 gma_write16(hw, port, GM_SMI_CTRL,
1427 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1428 for (i = 0; i < PHY_RETRIES; i++) {
1429 udelay(1);
1430
1431 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1432 break;
1433 }
1434 }
1435
1436 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1437 {
1438 int i;
1439
1440 gma_write16(hw, port, GM_SMI_CTRL,
1441 GM_SMI_CT_PHY_AD(hw->phy_addr)
1442 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1443
1444 for (i = 0; i < PHY_RETRIES; i++) {
1445 udelay(1);
1446 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1447 goto ready;
1448 }
1449
1450 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1451 hw->dev[port]->name);
1452 return 0;
1453 ready:
1454 return gma_read16(hw, port, GM_SMI_DATA);
1455 }
1456
1457 static void genesis_link_up(struct skge_port *skge)
1458 {
1459 struct skge_hw *hw = skge->hw;
1460 int port = skge->port;
1461 u16 cmd;
1462 u32 mode, msk;
1463
1464 pr_debug("genesis_link_up\n");
1465 cmd = xm_read16(hw, port, XM_MMU_CMD);
1466
1467 /*
1468 * enabling pause frame reception is required for 1000BT
1469 * because the XMAC is not reset if the link is going down
1470 */
1471 if (skge->flow_control == FLOW_MODE_NONE ||
1472 skge->flow_control == FLOW_MODE_LOC_SEND)
1473 /* Disable Pause Frame Reception */
1474 cmd |= XM_MMU_IGN_PF;
1475 else
1476 /* Enable Pause Frame Reception */
1477 cmd &= ~XM_MMU_IGN_PF;
1478
1479 xm_write16(hw, port, XM_MMU_CMD, cmd);
1480
1481 mode = xm_read32(hw, port, XM_MODE);
1482 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1483 skge->flow_control == FLOW_MODE_LOC_SEND) {
1484 /*
1485 * Configure Pause Frame Generation
1486 * Use internal and external Pause Frame Generation.
1487 * Sending pause frames is edge triggered.
1488 * Send a Pause frame with the maximum pause time if
1489 * internal oder external FIFO full condition occurs.
1490 * Send a zero pause time frame to re-start transmission.
1491 */
1492 /* XM_PAUSE_DA = '010000C28001' (default) */
1493 /* XM_MAC_PTIME = 0xffff (maximum) */
1494 /* remember this value is defined in big endian (!) */
1495 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1496
1497 mode |= XM_PAUSE_MODE;
1498 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1499 } else {
1500 /*
1501 * disable pause frame generation is required for 1000BT
1502 * because the XMAC is not reset if the link is going down
1503 */
1504 /* Disable Pause Mode in Mode Register */
1505 mode &= ~XM_PAUSE_MODE;
1506
1507 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1508 }
1509
1510 xm_write32(hw, port, XM_MODE, mode);
1511
1512 msk = XM_DEF_MSK;
1513 /* disable GP0 interrupt bit for external Phy */
1514 msk |= XM_IS_INP_ASS;
1515
1516 xm_write16(hw, port, XM_IMSK, msk);
1517 xm_read16(hw, port, XM_ISRC);
1518
1519 /* get MMU Command Reg. */
1520 cmd = xm_read16(hw, port, XM_MMU_CMD);
1521 if (skge->duplex == DUPLEX_FULL)
1522 cmd |= XM_MMU_GMII_FD;
1523
1524 /*
1525 * Workaround BCOM Errata (#10523) for all BCom Phys
1526 * Enable Power Management after link up
1527 */
1528 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1529 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1530 & ~PHY_B_AC_DIS_PM);
1531 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1532
1533 /* enable Rx/Tx */
1534 xm_write16(hw, port, XM_MMU_CMD,
1535 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1536 skge_link_up(skge);
1537 }
1538
1539
1540 static inline void bcom_phy_intr(struct skge_port *skge)
1541 {
1542 struct skge_hw *hw = skge->hw;
1543 int port = skge->port;
1544 u16 isrc;
1545
1546 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1547 if (netif_msg_intr(skge))
1548 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1549 skge->netdev->name, isrc);
1550
1551 if (isrc & PHY_B_IS_PSE)
1552 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1553 hw->dev[port]->name);
1554
1555 /* Workaround BCom Errata:
1556 * enable and disable loopback mode if "NO HCD" occurs.
1557 */
1558 if (isrc & PHY_B_IS_NO_HDCL) {
1559 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1560 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1561 ctrl | PHY_CT_LOOP);
1562 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1563 ctrl & ~PHY_CT_LOOP);
1564 }
1565
1566 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1567 bcom_check_link(hw, port);
1568
1569 }
1570
1571 /* Marvell Phy Initailization */
1572 static void yukon_init(struct skge_hw *hw, int port)
1573 {
1574 struct skge_port *skge = netdev_priv(hw->dev[port]);
1575 u16 ctrl, ct1000, adv;
1576
1577 pr_debug("yukon_init\n");
1578 if (skge->autoneg == AUTONEG_ENABLE) {
1579 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1580
1581 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1582 PHY_M_EC_MAC_S_MSK);
1583 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1584
1585 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1586
1587 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1588 }
1589
1590 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1591 if (skge->autoneg == AUTONEG_DISABLE)
1592 ctrl &= ~PHY_CT_ANE;
1593
1594 ctrl |= PHY_CT_RESET;
1595 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1596
1597 ctrl = 0;
1598 ct1000 = 0;
1599 adv = PHY_AN_CSMA;
1600
1601 if (skge->autoneg == AUTONEG_ENABLE) {
1602 if (hw->copper) {
1603 if (skge->advertising & ADVERTISED_1000baseT_Full)
1604 ct1000 |= PHY_M_1000C_AFD;
1605 if (skge->advertising & ADVERTISED_1000baseT_Half)
1606 ct1000 |= PHY_M_1000C_AHD;
1607 if (skge->advertising & ADVERTISED_100baseT_Full)
1608 adv |= PHY_M_AN_100_FD;
1609 if (skge->advertising & ADVERTISED_100baseT_Half)
1610 adv |= PHY_M_AN_100_HD;
1611 if (skge->advertising & ADVERTISED_10baseT_Full)
1612 adv |= PHY_M_AN_10_FD;
1613 if (skge->advertising & ADVERTISED_10baseT_Half)
1614 adv |= PHY_M_AN_10_HD;
1615 } else /* special defines for FIBER (88E1011S only) */
1616 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1617
1618 /* Set Flow-control capabilities */
1619 adv |= phy_pause_map[skge->flow_control];
1620
1621 /* Restart Auto-negotiation */
1622 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1623 } else {
1624 /* forced speed/duplex settings */
1625 ct1000 = PHY_M_1000C_MSE;
1626
1627 if (skge->duplex == DUPLEX_FULL)
1628 ctrl |= PHY_CT_DUP_MD;
1629
1630 switch (skge->speed) {
1631 case SPEED_1000:
1632 ctrl |= PHY_CT_SP1000;
1633 break;
1634 case SPEED_100:
1635 ctrl |= PHY_CT_SP100;
1636 break;
1637 }
1638
1639 ctrl |= PHY_CT_RESET;
1640 }
1641
1642 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1643
1644 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1645 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1646
1647 /* Enable phy interrupt on autonegotiation complete (or link up) */
1648 if (skge->autoneg == AUTONEG_ENABLE)
1649 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
1650 else
1651 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1652 }
1653
1654 static void yukon_reset(struct skge_hw *hw, int port)
1655 {
1656 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1657 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1658 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1659 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1660 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1661
1662 gma_write16(hw, port, GM_RX_CTRL,
1663 gma_read16(hw, port, GM_RX_CTRL)
1664 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1665 }
1666
1667 static void yukon_mac_init(struct skge_hw *hw, int port)
1668 {
1669 struct skge_port *skge = netdev_priv(hw->dev[port]);
1670 int i;
1671 u32 reg;
1672 const u8 *addr = hw->dev[port]->dev_addr;
1673
1674 /* WA code for COMA mode -- set PHY reset */
1675 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1676 hw->chip_rev >= CHIP_REV_YU_LITE_A3)
1677 skge_write32(hw, B2_GP_IO,
1678 (skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9));
1679
1680 /* hard reset */
1681 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1682 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1683
1684 /* WA code for COMA mode -- clear PHY reset */
1685 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1686 hw->chip_rev >= CHIP_REV_YU_LITE_A3)
1687 skge_write32(hw, B2_GP_IO,
1688 (skge_read32(hw, B2_GP_IO) | GP_DIR_9)
1689 & ~GP_IO_9);
1690
1691 /* Set hardware config mode */
1692 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1693 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1694 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1695
1696 /* Clear GMC reset */
1697 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1698 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1699 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
1700 if (skge->autoneg == AUTONEG_DISABLE) {
1701 reg = GM_GPCR_AU_ALL_DIS;
1702 gma_write16(hw, port, GM_GP_CTRL,
1703 gma_read16(hw, port, GM_GP_CTRL) | reg);
1704
1705 switch (skge->speed) {
1706 case SPEED_1000:
1707 reg |= GM_GPCR_SPEED_1000;
1708 /* fallthru */
1709 case SPEED_100:
1710 reg |= GM_GPCR_SPEED_100;
1711 }
1712
1713 if (skge->duplex == DUPLEX_FULL)
1714 reg |= GM_GPCR_DUP_FULL;
1715 } else
1716 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1717 switch (skge->flow_control) {
1718 case FLOW_MODE_NONE:
1719 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1720 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1721 break;
1722 case FLOW_MODE_LOC_SEND:
1723 /* disable Rx flow-control */
1724 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1725 }
1726
1727 gma_write16(hw, port, GM_GP_CTRL, reg);
1728 skge_read16(hw, GMAC_IRQ_SRC);
1729
1730 yukon_init(hw, port);
1731
1732 /* MIB clear */
1733 reg = gma_read16(hw, port, GM_PHY_ADDR);
1734 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
1735
1736 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
1737 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1738 gma_write16(hw, port, GM_PHY_ADDR, reg);
1739
1740 /* transmit control */
1741 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
1742
1743 /* receive control reg: unicast + multicast + no FCS */
1744 gma_write16(hw, port, GM_RX_CTRL,
1745 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1746
1747 /* transmit flow control */
1748 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
1749
1750 /* transmit parameter */
1751 gma_write16(hw, port, GM_TX_PARAM,
1752 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1753 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1754 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1755
1756 /* serial mode register */
1757 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1758 if (hw->dev[port]->mtu > 1500)
1759 reg |= GM_SMOD_JUMBO_ENA;
1760
1761 gma_write16(hw, port, GM_SERIAL_MODE, reg);
1762
1763 /* physical address: used for pause frames */
1764 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
1765 /* virtual address for data */
1766 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
1767
1768 /* enable interrupt mask for counter overflows */
1769 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1770 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1771 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
1772
1773 /* Initialize Mac Fifo */
1774
1775 /* Configure Rx MAC FIFO */
1776 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
1777 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1778 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1779 hw->chip_rev >= CHIP_REV_YU_LITE_A3)
1780 reg &= ~GMF_RX_F_FL_ON;
1781 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1782 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1783 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
1784
1785 /* Configure Tx MAC FIFO */
1786 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1787 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1788 }
1789
1790 static void yukon_stop(struct skge_port *skge)
1791 {
1792 struct skge_hw *hw = skge->hw;
1793 int port = skge->port;
1794
1795 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1796 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1797 skge_write32(hw, B2_GP_IO,
1798 skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9);
1799 }
1800
1801 gma_write16(hw, port, GM_GP_CTRL,
1802 gma_read16(hw, port, GM_GP_CTRL)
1803 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
1804 gma_read16(hw, port, GM_GP_CTRL);
1805
1806 /* set GPHY Control reset */
1807 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1808 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1809 }
1810
1811 static void yukon_get_stats(struct skge_port *skge, u64 *data)
1812 {
1813 struct skge_hw *hw = skge->hw;
1814 int port = skge->port;
1815 int i;
1816
1817 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1818 | gma_read32(hw, port, GM_TXO_OK_LO);
1819 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1820 | gma_read32(hw, port, GM_RXO_OK_LO);
1821
1822 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1823 data[i] = gma_read32(hw, port,
1824 skge_stats[i].gma_offset);
1825 }
1826
1827 static void yukon_mac_intr(struct skge_hw *hw, int port)
1828 {
1829 struct net_device *dev = hw->dev[port];
1830 struct skge_port *skge = netdev_priv(dev);
1831 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1832
1833 if (netif_msg_intr(skge))
1834 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1835 dev->name, status);
1836
1837 if (status & GM_IS_RX_FF_OR) {
1838 ++skge->net_stats.rx_fifo_errors;
1839 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1840 }
1841
1842 if (status & GM_IS_TX_FF_UR) {
1843 ++skge->net_stats.tx_fifo_errors;
1844 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1845 }
1846
1847 }
1848
1849 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1850 {
1851 switch (aux & PHY_M_PS_SPEED_MSK) {
1852 case PHY_M_PS_SPEED_1000:
1853 return SPEED_1000;
1854 case PHY_M_PS_SPEED_100:
1855 return SPEED_100;
1856 default:
1857 return SPEED_10;
1858 }
1859 }
1860
1861 static void yukon_link_up(struct skge_port *skge)
1862 {
1863 struct skge_hw *hw = skge->hw;
1864 int port = skge->port;
1865 u16 reg;
1866
1867 pr_debug("yukon_link_up\n");
1868
1869 /* Enable Transmit FIFO Underrun */
1870 skge_write8(hw, GMAC_IRQ_MSK, GMAC_DEF_MSK);
1871
1872 reg = gma_read16(hw, port, GM_GP_CTRL);
1873 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1874 reg |= GM_GPCR_DUP_FULL;
1875
1876 /* enable Rx/Tx */
1877 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1878 gma_write16(hw, port, GM_GP_CTRL, reg);
1879
1880 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1881 skge_link_up(skge);
1882 }
1883
1884 static void yukon_link_down(struct skge_port *skge)
1885 {
1886 struct skge_hw *hw = skge->hw;
1887 int port = skge->port;
1888 u16 ctrl;
1889
1890 pr_debug("yukon_link_down\n");
1891 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1892
1893 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1894 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1895 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1896
1897 if (skge->flow_control == FLOW_MODE_REM_SEND) {
1898 /* restore Asymmetric Pause bit */
1899 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1900 gm_phy_read(hw, port,
1901 PHY_MARV_AUNE_ADV)
1902 | PHY_M_AN_ASP);
1903
1904 }
1905
1906 yukon_reset(hw, port);
1907 skge_link_down(skge);
1908
1909 yukon_init(hw, port);
1910 }
1911
1912 static void yukon_phy_intr(struct skge_port *skge)
1913 {
1914 struct skge_hw *hw = skge->hw;
1915 int port = skge->port;
1916 const char *reason = NULL;
1917 u16 istatus, phystat;
1918
1919 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1920 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1921
1922 if (netif_msg_intr(skge))
1923 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1924 skge->netdev->name, istatus, phystat);
1925
1926 if (istatus & PHY_M_IS_AN_COMPL) {
1927 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
1928 & PHY_M_AN_RF) {
1929 reason = "remote fault";
1930 goto failed;
1931 }
1932
1933 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1934 reason = "master/slave fault";
1935 goto failed;
1936 }
1937
1938 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1939 reason = "speed/duplex";
1940 goto failed;
1941 }
1942
1943 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1944 ? DUPLEX_FULL : DUPLEX_HALF;
1945 skge->speed = yukon_speed(hw, phystat);
1946
1947 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1948 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1949 case PHY_M_PS_PAUSE_MSK:
1950 skge->flow_control = FLOW_MODE_SYMMETRIC;
1951 break;
1952 case PHY_M_PS_RX_P_EN:
1953 skge->flow_control = FLOW_MODE_REM_SEND;
1954 break;
1955 case PHY_M_PS_TX_P_EN:
1956 skge->flow_control = FLOW_MODE_LOC_SEND;
1957 break;
1958 default:
1959 skge->flow_control = FLOW_MODE_NONE;
1960 }
1961
1962 if (skge->flow_control == FLOW_MODE_NONE ||
1963 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
1964 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1965 else
1966 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1967 yukon_link_up(skge);
1968 return;
1969 }
1970
1971 if (istatus & PHY_M_IS_LSP_CHANGE)
1972 skge->speed = yukon_speed(hw, phystat);
1973
1974 if (istatus & PHY_M_IS_DUP_CHANGE)
1975 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1976 if (istatus & PHY_M_IS_LST_CHANGE) {
1977 if (phystat & PHY_M_PS_LINK_UP)
1978 yukon_link_up(skge);
1979 else
1980 yukon_link_down(skge);
1981 }
1982 return;
1983 failed:
1984 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
1985 skge->netdev->name, reason);
1986
1987 /* XXX restart autonegotiation? */
1988 }
1989
1990 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
1991 {
1992 u32 end;
1993
1994 start /= 8;
1995 len /= 8;
1996 end = start + len - 1;
1997
1998 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
1999 skge_write32(hw, RB_ADDR(q, RB_START), start);
2000 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2001 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2002 skge_write32(hw, RB_ADDR(q, RB_END), end);
2003
2004 if (q == Q_R1 || q == Q_R2) {
2005 /* Set thresholds on receive queue's */
2006 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2007 start + (2*len)/3);
2008 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2009 start + (len/3));
2010 } else {
2011 /* Enable store & forward on Tx queue's because
2012 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2013 */
2014 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2015 }
2016
2017 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2018 }
2019
2020 /* Setup Bus Memory Interface */
2021 static void skge_qset(struct skge_port *skge, u16 q,
2022 const struct skge_element *e)
2023 {
2024 struct skge_hw *hw = skge->hw;
2025 u32 watermark = 0x600;
2026 u64 base = skge->dma + (e->desc - skge->mem);
2027
2028 /* optimization to reduce window on 32bit/33mhz */
2029 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2030 watermark /= 2;
2031
2032 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2033 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2034 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2035 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2036 }
2037
2038 static int skge_up(struct net_device *dev)
2039 {
2040 struct skge_port *skge = netdev_priv(dev);
2041 struct skge_hw *hw = skge->hw;
2042 int port = skge->port;
2043 u32 chunk, ram_addr;
2044 size_t rx_size, tx_size;
2045 int err;
2046
2047 if (netif_msg_ifup(skge))
2048 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2049
2050 if (dev->mtu > RX_BUF_SIZE)
2051 skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;
2052 else
2053 skge->rx_buf_size = RX_BUF_SIZE;
2054
2055
2056 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2057 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2058 skge->mem_size = tx_size + rx_size;
2059 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2060 if (!skge->mem)
2061 return -ENOMEM;
2062
2063 memset(skge->mem, 0, skge->mem_size);
2064
2065 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2066 goto free_pci_mem;
2067
2068 err = skge_rx_fill(skge);
2069 if (err)
2070 goto free_rx_ring;
2071
2072 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2073 skge->dma + rx_size)))
2074 goto free_rx_ring;
2075
2076 skge->tx_avail = skge->tx_ring.count - 1;
2077
2078 /* Enable IRQ from port */
2079 hw->intr_mask |= portirqmask[port];
2080 skge_write32(hw, B0_IMSK, hw->intr_mask);
2081
2082 /* Initialze MAC */
2083 spin_lock_bh(&hw->phy_lock);
2084 if (hw->chip_id == CHIP_ID_GENESIS)
2085 genesis_mac_init(hw, port);
2086 else
2087 yukon_mac_init(hw, port);
2088 spin_unlock_bh(&hw->phy_lock);
2089
2090 /* Configure RAMbuffers */
2091 chunk = hw->ram_size / ((hw->ports + 1)*2);
2092 ram_addr = hw->ram_offset + 2 * chunk * port;
2093
2094 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2095 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2096
2097 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2098 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2099 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2100
2101 /* Start receiver BMU */
2102 wmb();
2103 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2104 skge_led(skge, LED_MODE_ON);
2105
2106 pr_debug("skge_up completed\n");
2107 return 0;
2108
2109 free_rx_ring:
2110 skge_rx_clean(skge);
2111 kfree(skge->rx_ring.start);
2112 free_pci_mem:
2113 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2114
2115 return err;
2116 }
2117
2118 static int skge_down(struct net_device *dev)
2119 {
2120 struct skge_port *skge = netdev_priv(dev);
2121 struct skge_hw *hw = skge->hw;
2122 int port = skge->port;
2123
2124 if (netif_msg_ifdown(skge))
2125 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2126
2127 netif_stop_queue(dev);
2128
2129 /* Stop transmitter */
2130 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2131 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2132 RB_RST_SET|RB_DIS_OP_MD);
2133
2134 if (hw->chip_id == CHIP_ID_GENESIS)
2135 genesis_stop(skge);
2136 else
2137 yukon_stop(skge);
2138
2139 /* Disable Force Sync bit and Enable Alloc bit */
2140 skge_write8(hw, SK_REG(port, TXA_CTRL),
2141 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2142
2143 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2144 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2145 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2146
2147 /* Reset PCI FIFO */
2148 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2149 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2150
2151 /* Reset the RAM Buffer async Tx queue */
2152 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2153 /* stop receiver */
2154 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2155 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2156 RB_RST_SET|RB_DIS_OP_MD);
2157 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2158
2159 if (hw->chip_id == CHIP_ID_GENESIS) {
2160 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2161 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2162 } else {
2163 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2164 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2165 }
2166
2167 skge_led(skge, LED_MODE_OFF);
2168
2169 skge_tx_clean(skge);
2170 skge_rx_clean(skge);
2171
2172 kfree(skge->rx_ring.start);
2173 kfree(skge->tx_ring.start);
2174 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2175 return 0;
2176 }
2177
2178 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2179 {
2180 struct skge_port *skge = netdev_priv(dev);
2181 struct skge_hw *hw = skge->hw;
2182 struct skge_ring *ring = &skge->tx_ring;
2183 struct skge_element *e;
2184 struct skge_tx_desc *td;
2185 int i;
2186 u32 control, len;
2187 u64 map;
2188 unsigned long flags;
2189
2190 skb = skb_padto(skb, ETH_ZLEN);
2191 if (!skb)
2192 return NETDEV_TX_OK;
2193
2194 local_irq_save(flags);
2195 if (!spin_trylock(&skge->tx_lock)) {
2196 /* Collision - tell upper layer to requeue */
2197 local_irq_restore(flags);
2198 return NETDEV_TX_LOCKED;
2199 }
2200
2201 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
2202 netif_stop_queue(dev);
2203 spin_unlock_irqrestore(&skge->tx_lock, flags);
2204
2205 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2206 dev->name);
2207 return NETDEV_TX_BUSY;
2208 }
2209
2210 e = ring->to_use;
2211 td = e->desc;
2212 e->skb = skb;
2213 len = skb_headlen(skb);
2214 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2215 pci_unmap_addr_set(e, mapaddr, map);
2216 pci_unmap_len_set(e, maplen, len);
2217
2218 td->dma_lo = map;
2219 td->dma_hi = map >> 32;
2220
2221 if (skb->ip_summed == CHECKSUM_HW) {
2222 const struct iphdr *ip
2223 = (const struct iphdr *) (skb->data + ETH_HLEN);
2224 int offset = skb->h.raw - skb->data;
2225
2226 /* This seems backwards, but it is what the sk98lin
2227 * does. Looks like hardware is wrong?
2228 */
2229 if (ip->protocol == IPPROTO_UDP
2230 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2231 control = BMU_TCP_CHECK;
2232 else
2233 control = BMU_UDP_CHECK;
2234
2235 td->csum_offs = 0;
2236 td->csum_start = offset;
2237 td->csum_write = offset + skb->csum;
2238 } else
2239 control = BMU_CHECK;
2240
2241 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2242 control |= BMU_EOF| BMU_IRQ_EOF;
2243 else {
2244 struct skge_tx_desc *tf = td;
2245
2246 control |= BMU_STFWD;
2247 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2248 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2249
2250 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2251 frag->size, PCI_DMA_TODEVICE);
2252
2253 e = e->next;
2254 e->skb = NULL;
2255 tf = e->desc;
2256 tf->dma_lo = map;
2257 tf->dma_hi = (u64) map >> 32;
2258 pci_unmap_addr_set(e, mapaddr, map);
2259 pci_unmap_len_set(e, maplen, frag->size);
2260
2261 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2262 }
2263 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2264 }
2265 /* Make sure all the descriptors written */
2266 wmb();
2267 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2268 wmb();
2269
2270 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2271
2272 if (netif_msg_tx_queued(skge))
2273 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2274 dev->name, e - ring->start, skb->len);
2275
2276 ring->to_use = e->next;
2277 skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2278 if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2279 pr_debug("%s: transmit queue full\n", dev->name);
2280 netif_stop_queue(dev);
2281 }
2282
2283 dev->trans_start = jiffies;
2284 spin_unlock_irqrestore(&skge->tx_lock, flags);
2285
2286 return NETDEV_TX_OK;
2287 }
2288
2289 static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2290 {
2291 /* This ring element can be skb or fragment */
2292 if (e->skb) {
2293 pci_unmap_single(hw->pdev,
2294 pci_unmap_addr(e, mapaddr),
2295 pci_unmap_len(e, maplen),
2296 PCI_DMA_TODEVICE);
2297 dev_kfree_skb_any(e->skb);
2298 e->skb = NULL;
2299 } else {
2300 pci_unmap_page(hw->pdev,
2301 pci_unmap_addr(e, mapaddr),
2302 pci_unmap_len(e, maplen),
2303 PCI_DMA_TODEVICE);
2304 }
2305 }
2306
2307 static void skge_tx_clean(struct skge_port *skge)
2308 {
2309 struct skge_ring *ring = &skge->tx_ring;
2310 struct skge_element *e;
2311 unsigned long flags;
2312
2313 spin_lock_irqsave(&skge->tx_lock, flags);
2314 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2315 ++skge->tx_avail;
2316 skge_tx_free(skge->hw, e);
2317 }
2318 ring->to_clean = e;
2319 spin_unlock_irqrestore(&skge->tx_lock, flags);
2320 }
2321
2322 static void skge_tx_timeout(struct net_device *dev)
2323 {
2324 struct skge_port *skge = netdev_priv(dev);
2325
2326 if (netif_msg_timer(skge))
2327 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2328
2329 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2330 skge_tx_clean(skge);
2331 }
2332
2333 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2334 {
2335 int err = 0;
2336 int running = netif_running(dev);
2337
2338 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2339 return -EINVAL;
2340
2341
2342 if (running)
2343 skge_down(dev);
2344 dev->mtu = new_mtu;
2345 if (running)
2346 skge_up(dev);
2347
2348 return err;
2349 }
2350
2351 static void genesis_set_multicast(struct net_device *dev)
2352 {
2353 struct skge_port *skge = netdev_priv(dev);
2354 struct skge_hw *hw = skge->hw;
2355 int port = skge->port;
2356 int i, count = dev->mc_count;
2357 struct dev_mc_list *list = dev->mc_list;
2358 u32 mode;
2359 u8 filter[8];
2360
2361 pr_debug("genesis_set_multicast flags=%x count=%d\n", dev->flags, dev->mc_count);
2362
2363 mode = xm_read32(hw, port, XM_MODE);
2364 mode |= XM_MD_ENA_HASH;
2365 if (dev->flags & IFF_PROMISC)
2366 mode |= XM_MD_ENA_PROM;
2367 else
2368 mode &= ~XM_MD_ENA_PROM;
2369
2370 if (dev->flags & IFF_ALLMULTI)
2371 memset(filter, 0xff, sizeof(filter));
2372 else {
2373 memset(filter, 0, sizeof(filter));
2374 for (i = 0; list && i < count; i++, list = list->next) {
2375 u32 crc, bit;
2376 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2377 bit = ~crc & 0x3f;
2378 filter[bit/8] |= 1 << (bit%8);
2379 }
2380 }
2381
2382 xm_write32(hw, port, XM_MODE, mode);
2383 xm_outhash(hw, port, XM_HSM, filter);
2384 }
2385
2386 static void yukon_set_multicast(struct net_device *dev)
2387 {
2388 struct skge_port *skge = netdev_priv(dev);
2389 struct skge_hw *hw = skge->hw;
2390 int port = skge->port;
2391 struct dev_mc_list *list = dev->mc_list;
2392 u16 reg;
2393 u8 filter[8];
2394
2395 memset(filter, 0, sizeof(filter));
2396
2397 reg = gma_read16(hw, port, GM_RX_CTRL);
2398 reg |= GM_RXCR_UCF_ENA;
2399
2400 if (dev->flags & IFF_PROMISC) /* promiscious */
2401 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2402 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2403 memset(filter, 0xff, sizeof(filter));
2404 else if (dev->mc_count == 0) /* no multicast */
2405 reg &= ~GM_RXCR_MCF_ENA;
2406 else {
2407 int i;
2408 reg |= GM_RXCR_MCF_ENA;
2409
2410 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2411 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2412 filter[bit/8] |= 1 << (bit%8);
2413 }
2414 }
2415
2416
2417 gma_write16(hw, port, GM_MC_ADDR_H1,
2418 (u16)filter[0] | ((u16)filter[1] << 8));
2419 gma_write16(hw, port, GM_MC_ADDR_H2,
2420 (u16)filter[2] | ((u16)filter[3] << 8));
2421 gma_write16(hw, port, GM_MC_ADDR_H3,
2422 (u16)filter[4] | ((u16)filter[5] << 8));
2423 gma_write16(hw, port, GM_MC_ADDR_H4,
2424 (u16)filter[6] | ((u16)filter[7] << 8));
2425
2426 gma_write16(hw, port, GM_RX_CTRL, reg);
2427 }
2428
2429 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2430 {
2431 if (hw->chip_id == CHIP_ID_GENESIS)
2432 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2433 else
2434 return (status & GMR_FS_ANY_ERR) ||
2435 (status & GMR_FS_RX_OK) == 0;
2436 }
2437
2438 static void skge_rx_error(struct skge_port *skge, int slot,
2439 u32 control, u32 status)
2440 {
2441 if (netif_msg_rx_err(skge))
2442 printk(KERN_DEBUG PFX "%s: rx err, slot %d control 0x%x status 0x%x\n",
2443 skge->netdev->name, slot, control, status);
2444
2445 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2446 skge->net_stats.rx_length_errors++;
2447 else if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2448 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2449 skge->net_stats.rx_length_errors++;
2450 if (status & XMR_FS_FRA_ERR)
2451 skge->net_stats.rx_frame_errors++;
2452 if (status & XMR_FS_FCS_ERR)
2453 skge->net_stats.rx_crc_errors++;
2454 } else {
2455 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2456 skge->net_stats.rx_length_errors++;
2457 if (status & GMR_FS_FRAGMENT)
2458 skge->net_stats.rx_frame_errors++;
2459 if (status & GMR_FS_CRC_ERR)
2460 skge->net_stats.rx_crc_errors++;
2461 }
2462 }
2463
2464 /* Get receive buffer from descriptor.
2465 * Handles copy of small buffers and reallocation failures
2466 */
2467 static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2468 struct skge_element *e,
2469 unsigned int len)
2470 {
2471 struct sk_buff *nskb, *skb;
2472
2473 if (len < RX_COPY_THRESHOLD) {
2474 nskb = skge_rx_alloc(skge->netdev, len + NET_IP_ALIGN);
2475 if (unlikely(!nskb))
2476 return NULL;
2477
2478 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2479 pci_unmap_addr(e, mapaddr),
2480 len, PCI_DMA_FROMDEVICE);
2481 memcpy(nskb->data, e->skb->data, len);
2482 pci_dma_sync_single_for_device(skge->hw->pdev,
2483 pci_unmap_addr(e, mapaddr),
2484 len, PCI_DMA_FROMDEVICE);
2485
2486 if (skge->rx_csum) {
2487 struct skge_rx_desc *rd = e->desc;
2488 nskb->csum = le16_to_cpu(rd->csum2);
2489 nskb->ip_summed = CHECKSUM_HW;
2490 }
2491 skge_rx_reuse(e, skge->rx_buf_size);
2492 return nskb;
2493 } else {
2494 nskb = skge_rx_alloc(skge->netdev, skge->rx_buf_size);
2495 if (unlikely(!nskb))
2496 return NULL;
2497
2498 pci_unmap_single(skge->hw->pdev,
2499 pci_unmap_addr(e, mapaddr),
2500 pci_unmap_len(e, maplen),
2501 PCI_DMA_FROMDEVICE);
2502 skb = e->skb;
2503 if (skge->rx_csum) {
2504 struct skge_rx_desc *rd = e->desc;
2505 skb->csum = le16_to_cpu(rd->csum2);
2506 skb->ip_summed = CHECKSUM_HW;
2507 }
2508
2509 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2510 return skb;
2511 }
2512 }
2513
2514
2515 static int skge_poll(struct net_device *dev, int *budget)
2516 {
2517 struct skge_port *skge = netdev_priv(dev);
2518 struct skge_hw *hw = skge->hw;
2519 struct skge_ring *ring = &skge->rx_ring;
2520 struct skge_element *e;
2521 unsigned int to_do = min(dev->quota, *budget);
2522 unsigned int work_done = 0;
2523
2524 pr_debug("skge_poll\n");
2525
2526 for (e = ring->to_clean; work_done < to_do; e = e->next) {
2527 struct skge_rx_desc *rd = e->desc;
2528 struct sk_buff *skb;
2529 u32 control, len, status;
2530
2531 rmb();
2532 control = rd->control;
2533 if (control & BMU_OWN)
2534 break;
2535
2536 len = control & BMU_BBC;
2537 status = rd->status;
2538
2539 if (unlikely((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)
2540 || bad_phy_status(hw, status))) {
2541 skge_rx_error(skge, e - ring->start, control, status);
2542 skge_rx_reuse(e, skge->rx_buf_size);
2543 continue;
2544 }
2545
2546 if (netif_msg_rx_status(skge))
2547 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2548 dev->name, e - ring->start, rd->status, len);
2549
2550 skb = skge_rx_get(skge, e, len);
2551 if (likely(skb)) {
2552 skb_put(skb, len);
2553 skb->protocol = eth_type_trans(skb, dev);
2554
2555 dev->last_rx = jiffies;
2556 netif_receive_skb(skb);
2557
2558 ++work_done;
2559 } else
2560 skge_rx_reuse(e, skge->rx_buf_size);
2561 }
2562 ring->to_clean = e;
2563
2564 /* restart receiver */
2565 wmb();
2566 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
2567 CSR_START | CSR_IRQ_CL_F);
2568
2569 *budget -= work_done;
2570 dev->quota -= work_done;
2571
2572 if (work_done >= to_do)
2573 return 1; /* not done */
2574
2575 local_irq_disable();
2576 __netif_rx_complete(dev);
2577 hw->intr_mask |= portirqmask[skge->port];
2578 skge_write32(hw, B0_IMSK, hw->intr_mask);
2579 local_irq_enable();
2580 return 0;
2581 }
2582
2583 static inline void skge_tx_intr(struct net_device *dev)
2584 {
2585 struct skge_port *skge = netdev_priv(dev);
2586 struct skge_hw *hw = skge->hw;
2587 struct skge_ring *ring = &skge->tx_ring;
2588 struct skge_element *e;
2589
2590 spin_lock(&skge->tx_lock);
2591 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2592 struct skge_tx_desc *td = e->desc;
2593 u32 control;
2594
2595 rmb();
2596 control = td->control;
2597 if (control & BMU_OWN)
2598 break;
2599
2600 if (unlikely(netif_msg_tx_done(skge)))
2601 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
2602 dev->name, e - ring->start, td->status);
2603
2604 skge_tx_free(hw, e);
2605 e->skb = NULL;
2606 ++skge->tx_avail;
2607 }
2608 ring->to_clean = e;
2609 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2610
2611 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2612 netif_wake_queue(dev);
2613
2614 spin_unlock(&skge->tx_lock);
2615 }
2616
2617 /* Parity errors seem to happen when Genesis is connected to a switch
2618 * with no other ports present. Heartbeat error??
2619 */
2620 static void skge_mac_parity(struct skge_hw *hw, int port)
2621 {
2622 struct net_device *dev = hw->dev[port];
2623
2624 if (dev) {
2625 struct skge_port *skge = netdev_priv(dev);
2626 ++skge->net_stats.tx_heartbeat_errors;
2627 }
2628
2629 if (hw->chip_id == CHIP_ID_GENESIS)
2630 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
2631 MFF_CLR_PERR);
2632 else
2633 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
2634 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
2635 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
2636 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2637 }
2638
2639 static void skge_pci_clear(struct skge_hw *hw)
2640 {
2641 u16 status;
2642
2643 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2644 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2645 pci_write_config_word(hw->pdev, PCI_STATUS,
2646 status | PCI_STATUS_ERROR_BITS);
2647 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2648 }
2649
2650 static void skge_mac_intr(struct skge_hw *hw, int port)
2651 {
2652 if (hw->chip_id == CHIP_ID_GENESIS)
2653 genesis_mac_intr(hw, port);
2654 else
2655 yukon_mac_intr(hw, port);
2656 }
2657
2658 /* Handle device specific framing and timeout interrupts */
2659 static void skge_error_irq(struct skge_hw *hw)
2660 {
2661 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2662
2663 if (hw->chip_id == CHIP_ID_GENESIS) {
2664 /* clear xmac errors */
2665 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
2666 skge_write16(hw, SK_REG(0, RX_MFF_CTRL1), MFF_CLR_INSTAT);
2667 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
2668 skge_write16(hw, SK_REG(0, RX_MFF_CTRL2), MFF_CLR_INSTAT);
2669 } else {
2670 /* Timestamp (unused) overflow */
2671 if (hwstatus & IS_IRQ_TIST_OV)
2672 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2673 }
2674
2675 if (hwstatus & IS_RAM_RD_PAR) {
2676 printk(KERN_ERR PFX "Ram read data parity error\n");
2677 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2678 }
2679
2680 if (hwstatus & IS_RAM_WR_PAR) {
2681 printk(KERN_ERR PFX "Ram write data parity error\n");
2682 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2683 }
2684
2685 if (hwstatus & IS_M1_PAR_ERR)
2686 skge_mac_parity(hw, 0);
2687
2688 if (hwstatus & IS_M2_PAR_ERR)
2689 skge_mac_parity(hw, 1);
2690
2691 if (hwstatus & IS_R1_PAR_ERR)
2692 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2693
2694 if (hwstatus & IS_R2_PAR_ERR)
2695 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2696
2697 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2698 printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2699 hwstatus);
2700
2701 skge_pci_clear(hw);
2702
2703 /* if error still set then just ignore it */
2704 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2705 if (hwstatus & IS_IRQ_STAT) {
2706 pr_debug("IRQ status %x: still set ignoring hardware errors\n",
2707 hwstatus);
2708 hw->intr_mask &= ~IS_HW_ERR;
2709 }
2710 }
2711 }
2712
2713 /*
2714 * Interrrupt from PHY are handled in tasklet (soft irq)
2715 * because accessing phy registers requires spin wait which might
2716 * cause excess interrupt latency.
2717 */
2718 static void skge_extirq(unsigned long data)
2719 {
2720 struct skge_hw *hw = (struct skge_hw *) data;
2721 int port;
2722
2723 spin_lock(&hw->phy_lock);
2724 for (port = 0; port < 2; port++) {
2725 struct net_device *dev = hw->dev[port];
2726
2727 if (dev && netif_running(dev)) {
2728 struct skge_port *skge = netdev_priv(dev);
2729
2730 if (hw->chip_id != CHIP_ID_GENESIS)
2731 yukon_phy_intr(skge);
2732 else
2733 bcom_phy_intr(skge);
2734 }
2735 }
2736 spin_unlock(&hw->phy_lock);
2737
2738 local_irq_disable();
2739 hw->intr_mask |= IS_EXT_REG;
2740 skge_write32(hw, B0_IMSK, hw->intr_mask);
2741 local_irq_enable();
2742 }
2743
2744 static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2745 {
2746 struct skge_hw *hw = dev_id;
2747 u32 status = skge_read32(hw, B0_SP_ISRC);
2748
2749 if (status == 0 || status == ~0) /* hotplug or shared irq */
2750 return IRQ_NONE;
2751
2752 status &= hw->intr_mask;
2753 if (status & IS_R1_F) {
2754 hw->intr_mask &= ~IS_R1_F;
2755 netif_rx_schedule(hw->dev[0]);
2756 }
2757
2758 if (status & IS_R2_F) {
2759 hw->intr_mask &= ~IS_R2_F;
2760 netif_rx_schedule(hw->dev[1]);
2761 }
2762
2763 if (status & IS_XA1_F)
2764 skge_tx_intr(hw->dev[0]);
2765
2766 if (status & IS_XA2_F)
2767 skge_tx_intr(hw->dev[1]);
2768
2769 if (status & IS_PA_TO_RX1) {
2770 struct skge_port *skge = netdev_priv(hw->dev[0]);
2771 ++skge->net_stats.rx_over_errors;
2772 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2773 }
2774
2775 if (status & IS_PA_TO_RX2) {
2776 struct skge_port *skge = netdev_priv(hw->dev[1]);
2777 ++skge->net_stats.rx_over_errors;
2778 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2779 }
2780
2781 if (status & IS_PA_TO_TX1)
2782 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2783
2784 if (status & IS_PA_TO_TX2)
2785 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2786
2787 if (status & IS_MAC1)
2788 skge_mac_intr(hw, 0);
2789
2790 if (status & IS_MAC2)
2791 skge_mac_intr(hw, 1);
2792
2793 if (status & IS_HW_ERR)
2794 skge_error_irq(hw);
2795
2796 if (status & IS_EXT_REG) {
2797 hw->intr_mask &= ~IS_EXT_REG;
2798 tasklet_schedule(&hw->ext_tasklet);
2799 }
2800
2801 skge_write32(hw, B0_IMSK, hw->intr_mask);
2802
2803 return IRQ_HANDLED;
2804 }
2805
2806 #ifdef CONFIG_NET_POLL_CONTROLLER
2807 static void skge_netpoll(struct net_device *dev)
2808 {
2809 struct skge_port *skge = netdev_priv(dev);
2810
2811 disable_irq(dev->irq);
2812 skge_intr(dev->irq, skge->hw, NULL);
2813 enable_irq(dev->irq);
2814 }
2815 #endif
2816
2817 static int skge_set_mac_address(struct net_device *dev, void *p)
2818 {
2819 struct skge_port *skge = netdev_priv(dev);
2820 struct sockaddr *addr = p;
2821 int err = 0;
2822
2823 if (!is_valid_ether_addr(addr->sa_data))
2824 return -EADDRNOTAVAIL;
2825
2826 skge_down(dev);
2827 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2828 memcpy_toio(skge->hw->regs + B2_MAC_1 + skge->port*8,
2829 dev->dev_addr, ETH_ALEN);
2830 memcpy_toio(skge->hw->regs + B2_MAC_2 + skge->port*8,
2831 dev->dev_addr, ETH_ALEN);
2832 if (dev->flags & IFF_UP)
2833 err = skge_up(dev);
2834 return err;
2835 }
2836
2837 static const struct {
2838 u8 id;
2839 const char *name;
2840 } skge_chips[] = {
2841 { CHIP_ID_GENESIS, "Genesis" },
2842 { CHIP_ID_YUKON, "Yukon" },
2843 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2844 { CHIP_ID_YUKON_LP, "Yukon-LP"},
2845 };
2846
2847 static const char *skge_board_name(const struct skge_hw *hw)
2848 {
2849 int i;
2850 static char buf[16];
2851
2852 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2853 if (skge_chips[i].id == hw->chip_id)
2854 return skge_chips[i].name;
2855
2856 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2857 return buf;
2858 }
2859
2860
2861 /*
2862 * Setup the board data structure, but don't bring up
2863 * the port(s)
2864 */
2865 static int skge_reset(struct skge_hw *hw)
2866 {
2867 u16 ctst;
2868 u8 t8, mac_cfg, pmd_type, phy_type;
2869 int i;
2870
2871 ctst = skge_read16(hw, B0_CTST);
2872
2873 /* do a SW reset */
2874 skge_write8(hw, B0_CTST, CS_RST_SET);
2875 skge_write8(hw, B0_CTST, CS_RST_CLR);
2876
2877 /* clear PCI errors, if any */
2878 skge_pci_clear(hw);
2879
2880 skge_write8(hw, B0_CTST, CS_MRST_CLR);
2881
2882 /* restore CLK_RUN bits (for Yukon-Lite) */
2883 skge_write16(hw, B0_CTST,
2884 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
2885
2886 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
2887 phy_type = skge_read8(hw, B2_E_1) & 0xf;
2888 pmd_type = skge_read8(hw, B2_PMD_TYP);
2889 hw->copper = (pmd_type == 'T' || pmd_type == '1');
2890
2891 switch (hw->chip_id) {
2892 case CHIP_ID_GENESIS:
2893 switch (phy_type) {
2894 case SK_PHY_BCOM:
2895 hw->phy_addr = PHY_ADDR_BCOM;
2896 break;
2897 default:
2898 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
2899 pci_name(hw->pdev), phy_type);
2900 return -EOPNOTSUPP;
2901 }
2902 break;
2903
2904 case CHIP_ID_YUKON:
2905 case CHIP_ID_YUKON_LITE:
2906 case CHIP_ID_YUKON_LP:
2907 if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
2908 hw->copper = 1;
2909
2910 hw->phy_addr = PHY_ADDR_MARV;
2911 break;
2912
2913 default:
2914 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2915 pci_name(hw->pdev), hw->chip_id);
2916 return -EOPNOTSUPP;
2917 }
2918
2919 mac_cfg = skge_read8(hw, B2_MAC_CFG);
2920 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
2921 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
2922
2923 /* read the adapters RAM size */
2924 t8 = skge_read8(hw, B2_E_0);
2925 if (hw->chip_id == CHIP_ID_GENESIS) {
2926 if (t8 == 3) {
2927 /* special case: 4 x 64k x 36, offset = 0x80000 */
2928 hw->ram_size = 0x100000;
2929 hw->ram_offset = 0x80000;
2930 } else
2931 hw->ram_size = t8 * 512;
2932 }
2933 else if (t8 == 0)
2934 hw->ram_size = 0x20000;
2935 else
2936 hw->ram_size = t8 * 4096;
2937
2938 hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
2939 if (hw->chip_id == CHIP_ID_GENESIS)
2940 genesis_init(hw);
2941 else {
2942 /* switch power to VCC (WA for VAUX problem) */
2943 skge_write8(hw, B0_POWER_CTRL,
2944 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
2945 /* avoid boards with stuck Hardware error bits */
2946 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
2947 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
2948 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
2949 hw->intr_mask &= ~IS_HW_ERR;
2950 }
2951
2952 for (i = 0; i < hw->ports; i++) {
2953 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2954 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2955 }
2956 }
2957
2958 /* turn off hardware timer (unused) */
2959 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
2960 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2961 skge_write8(hw, B0_LED, LED_STAT_ON);
2962
2963 /* enable the Tx Arbiters */
2964 for (i = 0; i < hw->ports; i++)
2965 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2966
2967 /* Initialize ram interface */
2968 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
2969
2970 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
2971 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
2972 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
2973 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
2974 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
2975 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
2976 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
2977 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
2978 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
2979 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
2980 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
2981 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
2982
2983 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
2984
2985 /* Set interrupt moderation for Transmit only
2986 * Receive interrupts avoided by NAPI
2987 */
2988 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
2989 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
2990 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
2991
2992 skge_write32(hw, B0_IMSK, hw->intr_mask);
2993
2994 if (hw->chip_id != CHIP_ID_GENESIS)
2995 skge_write8(hw, GMAC_IRQ_MSK, 0);
2996
2997 spin_lock_bh(&hw->phy_lock);
2998 for (i = 0; i < hw->ports; i++) {
2999 if (hw->chip_id == CHIP_ID_GENESIS)
3000 genesis_reset(hw, i);
3001 else
3002 yukon_reset(hw, i);
3003 }
3004 spin_unlock_bh(&hw->phy_lock);
3005
3006 return 0;
3007 }
3008
3009 /* Initialize network device */
3010 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3011 int highmem)
3012 {
3013 struct skge_port *skge;
3014 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3015
3016 if (!dev) {
3017 printk(KERN_ERR "skge etherdev alloc failed");
3018 return NULL;
3019 }
3020
3021 SET_MODULE_OWNER(dev);
3022 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3023 dev->open = skge_up;
3024 dev->stop = skge_down;
3025 dev->hard_start_xmit = skge_xmit_frame;
3026 dev->get_stats = skge_get_stats;
3027 if (hw->chip_id == CHIP_ID_GENESIS)
3028 dev->set_multicast_list = genesis_set_multicast;
3029 else
3030 dev->set_multicast_list = yukon_set_multicast;
3031
3032 dev->set_mac_address = skge_set_mac_address;
3033 dev->change_mtu = skge_change_mtu;
3034 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3035 dev->tx_timeout = skge_tx_timeout;
3036 dev->watchdog_timeo = TX_WATCHDOG;
3037 dev->poll = skge_poll;
3038 dev->weight = NAPI_WEIGHT;
3039 #ifdef CONFIG_NET_POLL_CONTROLLER
3040 dev->poll_controller = skge_netpoll;
3041 #endif
3042 dev->irq = hw->pdev->irq;
3043 dev->features = NETIF_F_LLTX;
3044 if (highmem)
3045 dev->features |= NETIF_F_HIGHDMA;
3046
3047 skge = netdev_priv(dev);
3048 skge->netdev = dev;
3049 skge->hw = hw;
3050 skge->msg_enable = netif_msg_init(debug, default_msg);
3051 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3052 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3053
3054 /* Auto speed and flow control */
3055 skge->autoneg = AUTONEG_ENABLE;
3056 skge->flow_control = FLOW_MODE_SYMMETRIC;
3057 skge->duplex = -1;
3058 skge->speed = -1;
3059 skge->advertising = skge_supported_modes(hw);
3060
3061 hw->dev[port] = dev;
3062
3063 skge->port = port;
3064
3065 spin_lock_init(&skge->tx_lock);
3066
3067 if (hw->chip_id != CHIP_ID_GENESIS) {
3068 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3069 skge->rx_csum = 1;
3070 }
3071
3072 /* read the mac address */
3073 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3074
3075 /* device is off until link detection */
3076 netif_carrier_off(dev);
3077 netif_stop_queue(dev);
3078
3079 return dev;
3080 }
3081
3082 static void __devinit skge_show_addr(struct net_device *dev)
3083 {
3084 const struct skge_port *skge = netdev_priv(dev);
3085
3086 if (netif_msg_probe(skge))
3087 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3088 dev->name,
3089 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3090 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3091 }
3092
3093 static int __devinit skge_probe(struct pci_dev *pdev,
3094 const struct pci_device_id *ent)
3095 {
3096 struct net_device *dev, *dev1;
3097 struct skge_hw *hw;
3098 int err, using_dac = 0;
3099
3100 if ((err = pci_enable_device(pdev))) {
3101 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3102 pci_name(pdev));
3103 goto err_out;
3104 }
3105
3106 if ((err = pci_request_regions(pdev, DRV_NAME))) {
3107 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3108 pci_name(pdev));
3109 goto err_out_disable_pdev;
3110 }
3111
3112 pci_set_master(pdev);
3113
3114 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)))
3115 using_dac = 1;
3116 else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3117 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3118 pci_name(pdev));
3119 goto err_out_free_regions;
3120 }
3121
3122 #ifdef __BIG_ENDIAN
3123 /* byte swap decriptors in hardware */
3124 {
3125 u32 reg;
3126
3127 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3128 reg |= PCI_REV_DESC;
3129 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3130 }
3131 #endif
3132
3133 err = -ENOMEM;
3134 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
3135 if (!hw) {
3136 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3137 pci_name(pdev));
3138 goto err_out_free_regions;
3139 }
3140
3141 memset(hw, 0, sizeof(*hw));
3142 hw->pdev = pdev;
3143 spin_lock_init(&hw->phy_lock);
3144 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3145
3146 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3147 if (!hw->regs) {
3148 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3149 pci_name(pdev));
3150 goto err_out_free_hw;
3151 }
3152
3153 if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3154 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3155 pci_name(pdev), pdev->irq);
3156 goto err_out_iounmap;
3157 }
3158 pci_set_drvdata(pdev, hw);
3159
3160 err = skge_reset(hw);
3161 if (err)
3162 goto err_out_free_irq;
3163
3164 printk(KERN_INFO PFX "addr 0x%lx irq %d chip %s rev %d\n",
3165 pci_resource_start(pdev, 0), pdev->irq,
3166 skge_board_name(hw), hw->chip_rev);
3167
3168 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
3169 goto err_out_led_off;
3170
3171 if ((err = register_netdev(dev))) {
3172 printk(KERN_ERR PFX "%s: cannot register net device\n",
3173 pci_name(pdev));
3174 goto err_out_free_netdev;
3175 }
3176
3177 skge_show_addr(dev);
3178
3179 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
3180 if (register_netdev(dev1) == 0)
3181 skge_show_addr(dev1);
3182 else {
3183 /* Failure to register second port need not be fatal */
3184 printk(KERN_WARNING PFX "register of second port failed\n");
3185 hw->dev[1] = NULL;
3186 free_netdev(dev1);
3187 }
3188 }
3189
3190 return 0;
3191
3192 err_out_free_netdev:
3193 free_netdev(dev);
3194 err_out_led_off:
3195 skge_write16(hw, B0_LED, LED_STAT_OFF);
3196 err_out_free_irq:
3197 free_irq(pdev->irq, hw);
3198 err_out_iounmap:
3199 iounmap(hw->regs);
3200 err_out_free_hw:
3201 kfree(hw);
3202 err_out_free_regions:
3203 pci_release_regions(pdev);
3204 err_out_disable_pdev:
3205 pci_disable_device(pdev);
3206 pci_set_drvdata(pdev, NULL);
3207 err_out:
3208 return err;
3209 }
3210
3211 static void __devexit skge_remove(struct pci_dev *pdev)
3212 {
3213 struct skge_hw *hw = pci_get_drvdata(pdev);
3214 struct net_device *dev0, *dev1;
3215
3216 if (!hw)
3217 return;
3218
3219 if ((dev1 = hw->dev[1]))
3220 unregister_netdev(dev1);
3221 dev0 = hw->dev[0];
3222 unregister_netdev(dev0);
3223
3224 tasklet_kill(&hw->ext_tasklet);
3225
3226 free_irq(pdev->irq, hw);
3227 pci_release_regions(pdev);
3228 pci_disable_device(pdev);
3229 if (dev1)
3230 free_netdev(dev1);
3231 free_netdev(dev0);
3232 skge_write16(hw, B0_LED, LED_STAT_OFF);
3233 iounmap(hw->regs);
3234 kfree(hw);
3235 pci_set_drvdata(pdev, NULL);
3236 }
3237
3238 #ifdef CONFIG_PM
3239 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3240 {
3241 struct skge_hw *hw = pci_get_drvdata(pdev);
3242 int i, wol = 0;
3243
3244 for (i = 0; i < 2; i++) {
3245 struct net_device *dev = hw->dev[i];
3246
3247 if (dev) {
3248 struct skge_port *skge = netdev_priv(dev);
3249 if (netif_running(dev)) {
3250 netif_carrier_off(dev);
3251 skge_down(dev);
3252 }
3253 netif_device_detach(dev);
3254 wol |= skge->wol;
3255 }
3256 }
3257
3258 pci_save_state(pdev);
3259 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3260 pci_disable_device(pdev);
3261 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3262
3263 return 0;
3264 }
3265
3266 static int skge_resume(struct pci_dev *pdev)
3267 {
3268 struct skge_hw *hw = pci_get_drvdata(pdev);
3269 int i;
3270
3271 pci_set_power_state(pdev, PCI_D0);
3272 pci_restore_state(pdev);
3273 pci_enable_wake(pdev, PCI_D0, 0);
3274
3275 skge_reset(hw);
3276
3277 for (i = 0; i < 2; i++) {
3278 struct net_device *dev = hw->dev[i];
3279 if (dev) {
3280 netif_device_attach(dev);
3281 if (netif_running(dev))
3282 skge_up(dev);
3283 }
3284 }
3285 return 0;
3286 }
3287 #endif
3288
3289 static struct pci_driver skge_driver = {
3290 .name = DRV_NAME,
3291 .id_table = skge_id_table,
3292 .probe = skge_probe,
3293 .remove = __devexit_p(skge_remove),
3294 #ifdef CONFIG_PM
3295 .suspend = skge_suspend,
3296 .resume = skge_resume,
3297 #endif
3298 };
3299
3300 static int __init skge_init_module(void)
3301 {
3302 return pci_module_init(&skge_driver);
3303 }
3304
3305 static void __exit skge_cleanup_module(void)
3306 {
3307 pci_unregister_driver(&skge_driver);
3308 }
3309
3310 module_init(skge_init_module);
3311 module_exit(skge_cleanup_module);
AMDTP streaming driver for the Linux FireWire stack (Juju)