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mwl8k: report rate and other information for received frames
[firewire-audio.git] / drivers / net / wireless / mwl8k.c
blob75c9261abad85fc2b3c1f5c9e743503bc1e49674
1 /*
2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
4 *
5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/sched.h>
16 #include <linux/spinlock.h>
17 #include <linux/list.h>
18 #include <linux/pci.h>
19 #include <linux/delay.h>
20 #include <linux/completion.h>
21 #include <linux/etherdevice.h>
22 #include <net/mac80211.h>
23 #include <linux/moduleparam.h>
24 #include <linux/firmware.h>
25 #include <linux/workqueue.h>
26
27 #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28 #define MWL8K_NAME KBUILD_MODNAME
29 #define MWL8K_VERSION "0.10"
30
31 static DEFINE_PCI_DEVICE_TABLE(mwl8k_table) = {
32 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = 8687, },
33 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = 8687, },
34 { }
35 };
36 MODULE_DEVICE_TABLE(pci, mwl8k_table);
37
38 /* Register definitions */
39 #define MWL8K_HIU_GEN_PTR 0x00000c10
40 #define MWL8K_MODE_STA 0x0000005a
41 #define MWL8K_MODE_AP 0x000000a5
42 #define MWL8K_HIU_INT_CODE 0x00000c14
43 #define MWL8K_FWSTA_READY 0xf0f1f2f4
44 #define MWL8K_FWAP_READY 0xf1f2f4a5
45 #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
46 #define MWL8K_HIU_SCRATCH 0x00000c40
47
48 /* Host->device communications */
49 #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
50 #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
51 #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
52 #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
53 #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
54 #define MWL8K_H2A_INT_DUMMY (1 << 20)
55 #define MWL8K_H2A_INT_RESET (1 << 15)
56 #define MWL8K_H2A_INT_DOORBELL (1 << 1)
57 #define MWL8K_H2A_INT_PPA_READY (1 << 0)
58
59 /* Device->host communications */
60 #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
61 #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
62 #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
63 #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
64 #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
65 #define MWL8K_A2H_INT_DUMMY (1 << 20)
66 #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
67 #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
68 #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
69 #define MWL8K_A2H_INT_RADIO_ON (1 << 6)
70 #define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
71 #define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
72 #define MWL8K_A2H_INT_OPC_DONE (1 << 2)
73 #define MWL8K_A2H_INT_RX_READY (1 << 1)
74 #define MWL8K_A2H_INT_TX_DONE (1 << 0)
75
76 #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
77 MWL8K_A2H_INT_CHNL_SWITCHED | \
78 MWL8K_A2H_INT_QUEUE_EMPTY | \
79 MWL8K_A2H_INT_RADAR_DETECT | \
80 MWL8K_A2H_INT_RADIO_ON | \
81 MWL8K_A2H_INT_RADIO_OFF | \
82 MWL8K_A2H_INT_MAC_EVENT | \
83 MWL8K_A2H_INT_OPC_DONE | \
84 MWL8K_A2H_INT_RX_READY | \
85 MWL8K_A2H_INT_TX_DONE)
86
87 #define MWL8K_RX_QUEUES 1
88 #define MWL8K_TX_QUEUES 4
89
90 struct mwl8k_rx_queue {
91 int rx_desc_count;
92
93 /* hw receives here */
94 int rx_head;
95
96 /* refill descs here */
97 int rx_tail;
98
99 struct mwl8k_rx_desc *rx_desc_area;
100 dma_addr_t rx_desc_dma;
101 struct sk_buff **rx_skb;
102 };
103
104 struct mwl8k_tx_queue {
105 /* hw transmits here */
106 int tx_head;
107
108 /* sw appends here */
109 int tx_tail;
110
111 struct ieee80211_tx_queue_stats tx_stats;
112 struct mwl8k_tx_desc *tx_desc_area;
113 dma_addr_t tx_desc_dma;
114 struct sk_buff **tx_skb;
115 };
116
117 /* Pointers to the firmware data and meta information about it. */
118 struct mwl8k_firmware {
119 /* Microcode */
120 struct firmware *ucode;
121
122 /* Boot helper code */
123 struct firmware *helper;
124 };
125
126 struct mwl8k_priv {
127 void __iomem *regs;
128 struct ieee80211_hw *hw;
129
130 struct pci_dev *pdev;
131
132 /* firmware files and meta data */
133 struct mwl8k_firmware fw;
134 u32 part_num;
135
136 /* firmware access */
137 struct mutex fw_mutex;
138 struct task_struct *fw_mutex_owner;
139 int fw_mutex_depth;
140 struct completion *hostcmd_wait;
141
142 /* lock held over TX and TX reap */
143 spinlock_t tx_lock;
144
145 /* TX quiesce completion, protected by fw_mutex and tx_lock */
146 struct completion *tx_wait;
147
148 struct ieee80211_vif *vif;
149
150 struct ieee80211_channel *current_channel;
151
152 /* power management status cookie from firmware */
153 u32 *cookie;
154 dma_addr_t cookie_dma;
155
156 u16 num_mcaddrs;
157 u8 hw_rev;
158 u32 fw_rev;
159
160 /*
161 * Running count of TX packets in flight, to avoid
162 * iterating over the transmit rings each time.
163 */
164 int pending_tx_pkts;
165
166 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
167 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
168
169 /* PHY parameters */
170 struct ieee80211_supported_band band;
171 struct ieee80211_channel channels[14];
172 struct ieee80211_rate rates[13];
173
174 bool radio_on;
175 bool radio_short_preamble;
176 bool wmm_enabled;
177
178 /* XXX need to convert this to handle multiple interfaces */
179 bool capture_beacon;
180 u8 capture_bssid[ETH_ALEN];
181 struct sk_buff *beacon_skb;
182
183 /*
184 * This FJ worker has to be global as it is scheduled from the
185 * RX handler. At this point we don't know which interface it
186 * belongs to until the list of bssids waiting to complete join
187 * is checked.
188 */
189 struct work_struct finalize_join_worker;
190
191 /* Tasklet to reclaim TX descriptors and buffers after tx */
192 struct tasklet_struct tx_reclaim_task;
193 };
194
195 /* Per interface specific private data */
196 struct mwl8k_vif {
197 /* backpointer to parent config block */
198 struct mwl8k_priv *priv;
199
200 /* BSS config of AP or IBSS from mac80211*/
201 struct ieee80211_bss_conf bss_info;
202
203 /* BSSID of AP or IBSS */
204 u8 bssid[ETH_ALEN];
205 u8 mac_addr[ETH_ALEN];
206
207 /*
208 * Subset of supported legacy rates.
209 * Intersection of AP and STA supported rates.
210 */
211 struct ieee80211_rate legacy_rates[13];
212
213 /* number of supported legacy rates */
214 u8 legacy_nrates;
215
216 /* Index into station database.Returned by update_sta_db call */
217 u8 peer_id;
218
219 /* Non AMPDU sequence number assigned by driver */
220 u16 seqno;
221 };
222
223 #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
224
225 static const struct ieee80211_channel mwl8k_channels[] = {
226 { .center_freq = 2412, .hw_value = 1, },
227 { .center_freq = 2417, .hw_value = 2, },
228 { .center_freq = 2422, .hw_value = 3, },
229 { .center_freq = 2427, .hw_value = 4, },
230 { .center_freq = 2432, .hw_value = 5, },
231 { .center_freq = 2437, .hw_value = 6, },
232 { .center_freq = 2442, .hw_value = 7, },
233 { .center_freq = 2447, .hw_value = 8, },
234 { .center_freq = 2452, .hw_value = 9, },
235 { .center_freq = 2457, .hw_value = 10, },
236 { .center_freq = 2462, .hw_value = 11, },
237 };
238
239 static const struct ieee80211_rate mwl8k_rates[] = {
240 { .bitrate = 10, .hw_value = 2, },
241 { .bitrate = 20, .hw_value = 4, },
242 { .bitrate = 55, .hw_value = 11, },
243 { .bitrate = 110, .hw_value = 22, },
244 { .bitrate = 220, .hw_value = 44, },
245 { .bitrate = 60, .hw_value = 12, },
246 { .bitrate = 90, .hw_value = 18, },
247 { .bitrate = 120, .hw_value = 24, },
248 { .bitrate = 180, .hw_value = 36, },
249 { .bitrate = 240, .hw_value = 48, },
250 { .bitrate = 360, .hw_value = 72, },
251 { .bitrate = 480, .hw_value = 96, },
252 { .bitrate = 540, .hw_value = 108, },
253 };
254
255 /* Set or get info from Firmware */
256 #define MWL8K_CMD_SET 0x0001
257 #define MWL8K_CMD_GET 0x0000
258
259 /* Firmware command codes */
260 #define MWL8K_CMD_CODE_DNLD 0x0001
261 #define MWL8K_CMD_GET_HW_SPEC 0x0003
262 #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
263 #define MWL8K_CMD_GET_STAT 0x0014
264 #define MWL8K_CMD_RADIO_CONTROL 0x001c
265 #define MWL8K_CMD_RF_TX_POWER 0x001e
266 #define MWL8K_CMD_SET_PRE_SCAN 0x0107
267 #define MWL8K_CMD_SET_POST_SCAN 0x0108
268 #define MWL8K_CMD_SET_RF_CHANNEL 0x010a
269 #define MWL8K_CMD_SET_AID 0x010d
270 #define MWL8K_CMD_SET_RATE 0x0110
271 #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
272 #define MWL8K_CMD_RTS_THRESHOLD 0x0113
273 #define MWL8K_CMD_SET_SLOT 0x0114
274 #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
275 #define MWL8K_CMD_SET_WMM_MODE 0x0123
276 #define MWL8K_CMD_MIMO_CONFIG 0x0125
277 #define MWL8K_CMD_USE_FIXED_RATE 0x0126
278 #define MWL8K_CMD_ENABLE_SNIFFER 0x0150
279 #define MWL8K_CMD_SET_MAC_ADDR 0x0202
280 #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
281 #define MWL8K_CMD_UPDATE_STADB 0x1123
282
283 static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
284 {
285 #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
286 snprintf(buf, bufsize, "%s", #x);\
287 return buf;\
288 } while (0)
289 switch (cmd & ~0x8000) {
290 MWL8K_CMDNAME(CODE_DNLD);
291 MWL8K_CMDNAME(GET_HW_SPEC);
292 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
293 MWL8K_CMDNAME(GET_STAT);
294 MWL8K_CMDNAME(RADIO_CONTROL);
295 MWL8K_CMDNAME(RF_TX_POWER);
296 MWL8K_CMDNAME(SET_PRE_SCAN);
297 MWL8K_CMDNAME(SET_POST_SCAN);
298 MWL8K_CMDNAME(SET_RF_CHANNEL);
299 MWL8K_CMDNAME(SET_AID);
300 MWL8K_CMDNAME(SET_RATE);
301 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
302 MWL8K_CMDNAME(RTS_THRESHOLD);
303 MWL8K_CMDNAME(SET_SLOT);
304 MWL8K_CMDNAME(SET_EDCA_PARAMS);
305 MWL8K_CMDNAME(SET_WMM_MODE);
306 MWL8K_CMDNAME(MIMO_CONFIG);
307 MWL8K_CMDNAME(USE_FIXED_RATE);
308 MWL8K_CMDNAME(ENABLE_SNIFFER);
309 MWL8K_CMDNAME(SET_MAC_ADDR);
310 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
311 MWL8K_CMDNAME(UPDATE_STADB);
312 default:
313 snprintf(buf, bufsize, "0x%x", cmd);
314 }
315 #undef MWL8K_CMDNAME
316
317 return buf;
318 }
319
320 /* Hardware and firmware reset */
321 static void mwl8k_hw_reset(struct mwl8k_priv *priv)
322 {
323 iowrite32(MWL8K_H2A_INT_RESET,
324 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
325 iowrite32(MWL8K_H2A_INT_RESET,
326 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
327 msleep(20);
328 }
329
330 /* Release fw image */
331 static void mwl8k_release_fw(struct firmware **fw)
332 {
333 if (*fw == NULL)
334 return;
335 release_firmware(*fw);
336 *fw = NULL;
337 }
338
339 static void mwl8k_release_firmware(struct mwl8k_priv *priv)
340 {
341 mwl8k_release_fw(&priv->fw.ucode);
342 mwl8k_release_fw(&priv->fw.helper);
343 }
344
345 /* Request fw image */
346 static int mwl8k_request_fw(struct mwl8k_priv *priv,
347 const char *fname, struct firmware **fw)
348 {
349 /* release current image */
350 if (*fw != NULL)
351 mwl8k_release_fw(fw);
352
353 return request_firmware((const struct firmware **)fw,
354 fname, &priv->pdev->dev);
355 }
356
357 static int mwl8k_request_firmware(struct mwl8k_priv *priv, u32 part_num)
358 {
359 u8 filename[64];
360 int rc;
361
362 priv->part_num = part_num;
363
364 snprintf(filename, sizeof(filename),
365 "mwl8k/helper_%u.fw", priv->part_num);
366
367 rc = mwl8k_request_fw(priv, filename, &priv->fw.helper);
368 if (rc) {
369 printk(KERN_ERR "%s: Error requesting helper firmware "
370 "file %s\n", pci_name(priv->pdev), filename);
371 return rc;
372 }
373
374 snprintf(filename, sizeof(filename),
375 "mwl8k/fmimage_%u.fw", priv->part_num);
376
377 rc = mwl8k_request_fw(priv, filename, &priv->fw.ucode);
378 if (rc) {
379 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
380 pci_name(priv->pdev), filename);
381 mwl8k_release_fw(&priv->fw.helper);
382 return rc;
383 }
384
385 return 0;
386 }
387
388 struct mwl8k_cmd_pkt {
389 __le16 code;
390 __le16 length;
391 __le16 seq_num;
392 __le16 result;
393 char payload[0];
394 } __attribute__((packed));
395
396 /*
397 * Firmware loading.
398 */
399 static int
400 mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
401 {
402 void __iomem *regs = priv->regs;
403 dma_addr_t dma_addr;
404 int loops;
405
406 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
407 if (pci_dma_mapping_error(priv->pdev, dma_addr))
408 return -ENOMEM;
409
410 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
411 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
412 iowrite32(MWL8K_H2A_INT_DOORBELL,
413 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
414 iowrite32(MWL8K_H2A_INT_DUMMY,
415 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
416
417 loops = 1000;
418 do {
419 u32 int_code;
420
421 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
422 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
423 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
424 break;
425 }
426
427 cond_resched();
428 udelay(1);
429 } while (--loops);
430
431 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
432
433 return loops ? 0 : -ETIMEDOUT;
434 }
435
436 static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
437 const u8 *data, size_t length)
438 {
439 struct mwl8k_cmd_pkt *cmd;
440 int done;
441 int rc = 0;
442
443 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
444 if (cmd == NULL)
445 return -ENOMEM;
446
447 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
448 cmd->seq_num = 0;
449 cmd->result = 0;
450
451 done = 0;
452 while (length) {
453 int block_size = length > 256 ? 256 : length;
454
455 memcpy(cmd->payload, data + done, block_size);
456 cmd->length = cpu_to_le16(block_size);
457
458 rc = mwl8k_send_fw_load_cmd(priv, cmd,
459 sizeof(*cmd) + block_size);
460 if (rc)
461 break;
462
463 done += block_size;
464 length -= block_size;
465 }
466
467 if (!rc) {
468 cmd->length = 0;
469 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
470 }
471
472 kfree(cmd);
473
474 return rc;
475 }
476
477 static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
478 const u8 *data, size_t length)
479 {
480 unsigned char *buffer;
481 int may_continue, rc = 0;
482 u32 done, prev_block_size;
483
484 buffer = kmalloc(1024, GFP_KERNEL);
485 if (buffer == NULL)
486 return -ENOMEM;
487
488 done = 0;
489 prev_block_size = 0;
490 may_continue = 1000;
491 while (may_continue > 0) {
492 u32 block_size;
493
494 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
495 if (block_size & 1) {
496 block_size &= ~1;
497 may_continue--;
498 } else {
499 done += prev_block_size;
500 length -= prev_block_size;
501 }
502
503 if (block_size > 1024 || block_size > length) {
504 rc = -EOVERFLOW;
505 break;
506 }
507
508 if (length == 0) {
509 rc = 0;
510 break;
511 }
512
513 if (block_size == 0) {
514 rc = -EPROTO;
515 may_continue--;
516 udelay(1);
517 continue;
518 }
519
520 prev_block_size = block_size;
521 memcpy(buffer, data + done, block_size);
522
523 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
524 if (rc)
525 break;
526 }
527
528 if (!rc && length != 0)
529 rc = -EREMOTEIO;
530
531 kfree(buffer);
532
533 return rc;
534 }
535
536 static int mwl8k_load_firmware(struct ieee80211_hw *hw)
537 {
538 struct mwl8k_priv *priv = hw->priv;
539 struct firmware *fw = priv->fw.ucode;
540 int rc;
541 int loops;
542
543 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
544 struct firmware *helper = priv->fw.helper;
545
546 if (helper == NULL) {
547 printk(KERN_ERR "%s: helper image needed but none "
548 "given\n", pci_name(priv->pdev));
549 return -EINVAL;
550 }
551
552 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
553 if (rc) {
554 printk(KERN_ERR "%s: unable to load firmware "
555 "helper image\n", pci_name(priv->pdev));
556 return rc;
557 }
558 msleep(1);
559
560 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
561 } else {
562 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
563 }
564
565 if (rc) {
566 printk(KERN_ERR "%s: unable to load firmware image\n",
567 pci_name(priv->pdev));
568 return rc;
569 }
570
571 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
572 msleep(1);
573
574 loops = 200000;
575 do {
576 if (ioread32(priv->regs + MWL8K_HIU_INT_CODE)
577 == MWL8K_FWSTA_READY)
578 break;
579 udelay(1);
580 } while (--loops);
581
582 return loops ? 0 : -ETIMEDOUT;
583 }
584
585
586 /*
587 * Defines shared between transmission and reception.
588 */
589 /* HT control fields for firmware */
590 struct ewc_ht_info {
591 __le16 control1;
592 __le16 control2;
593 __le16 control3;
594 } __attribute__((packed));
595
596 /* Firmware Station database operations */
597 #define MWL8K_STA_DB_ADD_ENTRY 0
598 #define MWL8K_STA_DB_MODIFY_ENTRY 1
599 #define MWL8K_STA_DB_DEL_ENTRY 2
600 #define MWL8K_STA_DB_FLUSH 3
601
602 /* Peer Entry flags - used to define the type of the peer node */
603 #define MWL8K_PEER_TYPE_ACCESSPOINT 2
604
605 #define MWL8K_IEEE_LEGACY_DATA_RATES 13
606 #define MWL8K_MCS_BITMAP_SIZE 16
607
608 struct peer_capability_info {
609 /* Peer type - AP vs. STA. */
610 __u8 peer_type;
611
612 /* Basic 802.11 capabilities from assoc resp. */
613 __le16 basic_caps;
614
615 /* Set if peer supports 802.11n high throughput (HT). */
616 __u8 ht_support;
617
618 /* Valid if HT is supported. */
619 __le16 ht_caps;
620 __u8 extended_ht_caps;
621 struct ewc_ht_info ewc_info;
622
623 /* Legacy rate table. Intersection of our rates and peer rates. */
624 __u8 legacy_rates[MWL8K_IEEE_LEGACY_DATA_RATES];
625
626 /* HT rate table. Intersection of our rates and peer rates. */
627 __u8 ht_rates[MWL8K_MCS_BITMAP_SIZE];
628 __u8 pad[16];
629
630 /* If set, interoperability mode, no proprietary extensions. */
631 __u8 interop;
632 __u8 pad2;
633 __u8 station_id;
634 __le16 amsdu_enabled;
635 } __attribute__((packed));
636
637 /* Inline functions to manipulate QoS field in data descriptor. */
638 static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
639 {
640 u16 val_mask = 1 << 4;
641
642 /* End of Service Period Bit 4 */
643 return qos | val_mask;
644 }
645
646 static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
647 {
648 u16 val_mask = 0x3;
649 u8 shift = 5;
650 u16 qos_mask = ~(val_mask << shift);
651
652 /* Ack Policy Bit 5-6 */
653 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
654 }
655
656 static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
657 {
658 u16 val_mask = 1 << 7;
659
660 /* AMSDU present Bit 7 */
661 return qos | val_mask;
662 }
663
664 static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
665 {
666 u16 val_mask = 0xff;
667 u8 shift = 8;
668 u16 qos_mask = ~(val_mask << shift);
669
670 /* Queue Length Bits 8-15 */
671 return (qos & qos_mask) | ((len & val_mask) << shift);
672 }
673
674 /* DMA header used by firmware and hardware. */
675 struct mwl8k_dma_data {
676 __le16 fwlen;
677 struct ieee80211_hdr wh;
678 } __attribute__((packed));
679
680 /* Routines to add/remove DMA header from skb. */
681 static inline void mwl8k_remove_dma_header(struct sk_buff *skb)
682 {
683 struct mwl8k_dma_data *tr = (struct mwl8k_dma_data *)skb->data;
684 void *dst, *src = &tr->wh;
685 int hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
686 u16 space = sizeof(struct mwl8k_dma_data) - hdrlen;
687
688 dst = (void *)tr + space;
689 if (dst != src) {
690 memmove(dst, src, hdrlen);
691 skb_pull(skb, space);
692 }
693 }
694
695 static inline void mwl8k_add_dma_header(struct sk_buff *skb)
696 {
697 struct ieee80211_hdr *wh;
698 u32 hdrlen, pktlen;
699 struct mwl8k_dma_data *tr;
700
701 wh = (struct ieee80211_hdr *)skb->data;
702 hdrlen = ieee80211_hdrlen(wh->frame_control);
703 pktlen = skb->len;
704
705 /*
706 * Copy up/down the 802.11 header; the firmware requires
707 * we present a 2-byte payload length followed by a
708 * 4-address header (w/o QoS), followed (optionally) by
709 * any WEP/ExtIV header (but only filled in for CCMP).
710 */
711 if (hdrlen != sizeof(struct mwl8k_dma_data))
712 skb_push(skb, sizeof(struct mwl8k_dma_data) - hdrlen);
713
714 tr = (struct mwl8k_dma_data *)skb->data;
715 if (wh != &tr->wh)
716 memmove(&tr->wh, wh, hdrlen);
717
718 /* Clear addr4 */
719 memset(tr->wh.addr4, 0, ETH_ALEN);
720
721 /*
722 * Firmware length is the length of the fully formed "802.11
723 * payload". That is, everything except for the 802.11 header.
724 * This includes all crypto material including the MIC.
725 */
726 tr->fwlen = cpu_to_le16(pktlen - hdrlen);
727 }
728
729
730 /*
731 * Packet reception.
732 */
733 #define MWL8K_RX_CTRL_OWNED_BY_HOST 0x02
734
735 struct mwl8k_rx_desc {
736 __le16 pkt_len;
737 __u8 link_quality;
738 __u8 noise_level;
739 __le32 pkt_phys_addr;
740 __le32 next_rx_desc_phys_addr;
741 __le16 qos_control;
742 __le16 rate_info;
743 __le32 pad0[4];
744 __u8 rssi;
745 __u8 channel;
746 __le16 pad1;
747 __u8 rx_ctrl;
748 __u8 rx_status;
749 __u8 pad2[2];
750 } __attribute__((packed));
751
752 #define MWL8K_RX_DESCS 256
753 #define MWL8K_RX_MAXSZ 3800
754
755 #define RATE_INFO_SHORTPRE 0x8000
756 #define RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
757 #define RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
758 #define RATE_INFO_40MHZ 0x0004
759 #define RATE_INFO_SHORTGI 0x0002
760 #define RATE_INFO_MCS_FORMAT 0x0001
761
762 static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
763 {
764 struct mwl8k_priv *priv = hw->priv;
765 struct mwl8k_rx_queue *rxq = priv->rxq + index;
766 int size;
767 int i;
768
769 rxq->rx_desc_count = 0;
770 rxq->rx_head = 0;
771 rxq->rx_tail = 0;
772
773 size = MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc);
774
775 rxq->rx_desc_area =
776 pci_alloc_consistent(priv->pdev, size, &rxq->rx_desc_dma);
777 if (rxq->rx_desc_area == NULL) {
778 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
779 wiphy_name(hw->wiphy));
780 return -ENOMEM;
781 }
782 memset(rxq->rx_desc_area, 0, size);
783
784 rxq->rx_skb = kmalloc(MWL8K_RX_DESCS *
785 sizeof(*rxq->rx_skb), GFP_KERNEL);
786 if (rxq->rx_skb == NULL) {
787 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
788 wiphy_name(hw->wiphy));
789 pci_free_consistent(priv->pdev, size,
790 rxq->rx_desc_area, rxq->rx_desc_dma);
791 return -ENOMEM;
792 }
793 memset(rxq->rx_skb, 0, MWL8K_RX_DESCS * sizeof(*rxq->rx_skb));
794
795 for (i = 0; i < MWL8K_RX_DESCS; i++) {
796 struct mwl8k_rx_desc *rx_desc;
797 int nexti;
798
799 rx_desc = rxq->rx_desc_area + i;
800 nexti = (i + 1) % MWL8K_RX_DESCS;
801
802 rx_desc->next_rx_desc_phys_addr =
803 cpu_to_le32(rxq->rx_desc_dma
804 + nexti * sizeof(*rx_desc));
805 rx_desc->rx_ctrl = MWL8K_RX_CTRL_OWNED_BY_HOST;
806 }
807
808 return 0;
809 }
810
811 static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
812 {
813 struct mwl8k_priv *priv = hw->priv;
814 struct mwl8k_rx_queue *rxq = priv->rxq + index;
815 int refilled;
816
817 refilled = 0;
818 while (rxq->rx_desc_count < MWL8K_RX_DESCS && limit--) {
819 struct sk_buff *skb;
820 int rx;
821
822 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
823 if (skb == NULL)
824 break;
825
826 rxq->rx_desc_count++;
827
828 rx = rxq->rx_tail;
829 rxq->rx_tail = (rx + 1) % MWL8K_RX_DESCS;
830
831 rxq->rx_desc_area[rx].pkt_phys_addr =
832 cpu_to_le32(pci_map_single(priv->pdev, skb->data,
833 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE));
834
835 rxq->rx_desc_area[rx].pkt_len = cpu_to_le16(MWL8K_RX_MAXSZ);
836 rxq->rx_skb[rx] = skb;
837 wmb();
838 rxq->rx_desc_area[rx].rx_ctrl = 0;
839
840 refilled++;
841 }
842
843 return refilled;
844 }
845
846 /* Must be called only when the card's reception is completely halted */
847 static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
848 {
849 struct mwl8k_priv *priv = hw->priv;
850 struct mwl8k_rx_queue *rxq = priv->rxq + index;
851 int i;
852
853 for (i = 0; i < MWL8K_RX_DESCS; i++) {
854 if (rxq->rx_skb[i] != NULL) {
855 unsigned long addr;
856
857 addr = le32_to_cpu(rxq->rx_desc_area[i].pkt_phys_addr);
858 pci_unmap_single(priv->pdev, addr, MWL8K_RX_MAXSZ,
859 PCI_DMA_FROMDEVICE);
860 kfree_skb(rxq->rx_skb[i]);
861 rxq->rx_skb[i] = NULL;
862 }
863 }
864
865 kfree(rxq->rx_skb);
866 rxq->rx_skb = NULL;
867
868 pci_free_consistent(priv->pdev,
869 MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc),
870 rxq->rx_desc_area, rxq->rx_desc_dma);
871 rxq->rx_desc_area = NULL;
872 }
873
874
875 /*
876 * Scan a list of BSSIDs to process for finalize join.
877 * Allows for extension to process multiple BSSIDs.
878 */
879 static inline int
880 mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
881 {
882 return priv->capture_beacon &&
883 ieee80211_is_beacon(wh->frame_control) &&
884 !compare_ether_addr(wh->addr3, priv->capture_bssid);
885 }
886
887 static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
888 struct sk_buff *skb)
889 {
890 struct mwl8k_priv *priv = hw->priv;
891
892 priv->capture_beacon = false;
893 memset(priv->capture_bssid, 0, ETH_ALEN);
894
895 /*
896 * Use GFP_ATOMIC as rxq_process is called from
897 * the primary interrupt handler, memory allocation call
898 * must not sleep.
899 */
900 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
901 if (priv->beacon_skb != NULL)
902 ieee80211_queue_work(hw, &priv->finalize_join_worker);
903 }
904
905 static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
906 {
907 struct mwl8k_priv *priv = hw->priv;
908 struct mwl8k_rx_queue *rxq = priv->rxq + index;
909 int processed;
910
911 processed = 0;
912 while (rxq->rx_desc_count && limit--) {
913 struct mwl8k_rx_desc *rx_desc;
914 struct sk_buff *skb;
915 struct ieee80211_rx_status status;
916 unsigned long addr;
917 struct ieee80211_hdr *wh;
918 u16 rate_info;
919
920 rx_desc = rxq->rx_desc_area + rxq->rx_head;
921 if (!(rx_desc->rx_ctrl & MWL8K_RX_CTRL_OWNED_BY_HOST))
922 break;
923 rmb();
924
925 skb = rxq->rx_skb[rxq->rx_head];
926 if (skb == NULL)
927 break;
928 rxq->rx_skb[rxq->rx_head] = NULL;
929
930 rxq->rx_head = (rxq->rx_head + 1) % MWL8K_RX_DESCS;
931 rxq->rx_desc_count--;
932
933 addr = le32_to_cpu(rx_desc->pkt_phys_addr);
934 pci_unmap_single(priv->pdev, addr,
935 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
936
937 skb_put(skb, le16_to_cpu(rx_desc->pkt_len));
938 mwl8k_remove_dma_header(skb);
939
940 wh = (struct ieee80211_hdr *)skb->data;
941
942 /*
943 * Check for a pending join operation. Save a
944 * copy of the beacon and schedule a tasklet to
945 * send a FINALIZE_JOIN command to the firmware.
946 */
947 if (mwl8k_capture_bssid(priv, wh))
948 mwl8k_save_beacon(hw, skb);
949
950 rate_info = le16_to_cpu(rx_desc->rate_info);
951
952 memset(&status, 0, sizeof(status));
953 status.mactime = 0;
954 status.signal = -rx_desc->rssi;
955 status.noise = -rx_desc->noise_level;
956 status.qual = rx_desc->link_quality;
957 status.antenna = RATE_INFO_ANTSELECT(rate_info);
958 status.rate_idx = RATE_INFO_RATEID(rate_info);
959 status.flag = 0;
960 if (rate_info & RATE_INFO_SHORTPRE)
961 status.flag |= RX_FLAG_SHORTPRE;
962 if (rate_info & RATE_INFO_40MHZ)
963 status.flag |= RX_FLAG_40MHZ;
964 if (rate_info & RATE_INFO_SHORTGI)
965 status.flag |= RX_FLAG_SHORT_GI;
966 if (rate_info & RATE_INFO_MCS_FORMAT)
967 status.flag |= RX_FLAG_HT;
968 status.band = IEEE80211_BAND_2GHZ;
969 status.freq = ieee80211_channel_to_frequency(rx_desc->channel);
970 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
971 ieee80211_rx_irqsafe(hw, skb);
972
973 processed++;
974 }
975
976 return processed;
977 }
978
979
980 /*
981 * Packet transmission.
982 */
983
984 /* Transmit packet ACK policy */
985 #define MWL8K_TXD_ACK_POLICY_NORMAL 0
986 #define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
987
988 #define MWL8K_TXD_STATUS_OK 0x00000001
989 #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
990 #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
991 #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
992 #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
993
994 struct mwl8k_tx_desc {
995 __le32 status;
996 __u8 data_rate;
997 __u8 tx_priority;
998 __le16 qos_control;
999 __le32 pkt_phys_addr;
1000 __le16 pkt_len;
1001 __u8 dest_MAC_addr[ETH_ALEN];
1002 __le32 next_tx_desc_phys_addr;
1003 __le32 reserved;
1004 __le16 rate_info;
1005 __u8 peer_id;
1006 __u8 tx_frag_cnt;
1007 } __attribute__((packed));
1008
1009 #define MWL8K_TX_DESCS 128
1010
1011 static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1012 {
1013 struct mwl8k_priv *priv = hw->priv;
1014 struct mwl8k_tx_queue *txq = priv->txq + index;
1015 int size;
1016 int i;
1017
1018 memset(&txq->tx_stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1019 txq->tx_stats.limit = MWL8K_TX_DESCS;
1020 txq->tx_head = 0;
1021 txq->tx_tail = 0;
1022
1023 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1024
1025 txq->tx_desc_area =
1026 pci_alloc_consistent(priv->pdev, size, &txq->tx_desc_dma);
1027 if (txq->tx_desc_area == NULL) {
1028 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
1029 wiphy_name(hw->wiphy));
1030 return -ENOMEM;
1031 }
1032 memset(txq->tx_desc_area, 0, size);
1033
1034 txq->tx_skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->tx_skb),
1035 GFP_KERNEL);
1036 if (txq->tx_skb == NULL) {
1037 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
1038 wiphy_name(hw->wiphy));
1039 pci_free_consistent(priv->pdev, size,
1040 txq->tx_desc_area, txq->tx_desc_dma);
1041 return -ENOMEM;
1042 }
1043 memset(txq->tx_skb, 0, MWL8K_TX_DESCS * sizeof(*txq->tx_skb));
1044
1045 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1046 struct mwl8k_tx_desc *tx_desc;
1047 int nexti;
1048
1049 tx_desc = txq->tx_desc_area + i;
1050 nexti = (i + 1) % MWL8K_TX_DESCS;
1051
1052 tx_desc->status = 0;
1053 tx_desc->next_tx_desc_phys_addr =
1054 cpu_to_le32(txq->tx_desc_dma +
1055 nexti * sizeof(*tx_desc));
1056 }
1057
1058 return 0;
1059 }
1060
1061 static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1062 {
1063 iowrite32(MWL8K_H2A_INT_PPA_READY,
1064 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1065 iowrite32(MWL8K_H2A_INT_DUMMY,
1066 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1067 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1068 }
1069
1070 struct mwl8k_txq_info {
1071 u32 fw_owned;
1072 u32 drv_owned;
1073 u32 unused;
1074 u32 len;
1075 u32 head;
1076 u32 tail;
1077 };
1078
1079 static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv,
1080 struct mwl8k_txq_info *txinfo)
1081 {
1082 int count, desc, status;
1083 struct mwl8k_tx_queue *txq;
1084 struct mwl8k_tx_desc *tx_desc;
1085 int ndescs = 0;
1086
1087 memset(txinfo, 0, MWL8K_TX_QUEUES * sizeof(struct mwl8k_txq_info));
1088
1089 for (count = 0; count < MWL8K_TX_QUEUES; count++) {
1090 txq = priv->txq + count;
1091 txinfo[count].len = txq->tx_stats.len;
1092 txinfo[count].head = txq->tx_head;
1093 txinfo[count].tail = txq->tx_tail;
1094 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
1095 tx_desc = txq->tx_desc_area + desc;
1096 status = le32_to_cpu(tx_desc->status);
1097
1098 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1099 txinfo[count].fw_owned++;
1100 else
1101 txinfo[count].drv_owned++;
1102
1103 if (tx_desc->pkt_len == 0)
1104 txinfo[count].unused++;
1105 }
1106 }
1107
1108 return ndescs;
1109 }
1110
1111 /*
1112 * Must be called with priv->fw_mutex held and tx queues stopped.
1113 */
1114 static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
1115 {
1116 struct mwl8k_priv *priv = hw->priv;
1117 DECLARE_COMPLETION_ONSTACK(tx_wait);
1118 u32 count;
1119 unsigned long timeout;
1120
1121 might_sleep();
1122
1123 spin_lock_bh(&priv->tx_lock);
1124 count = priv->pending_tx_pkts;
1125 if (count)
1126 priv->tx_wait = &tx_wait;
1127 spin_unlock_bh(&priv->tx_lock);
1128
1129 if (count) {
1130 struct mwl8k_txq_info txinfo[MWL8K_TX_QUEUES];
1131 int index;
1132 int newcount;
1133
1134 timeout = wait_for_completion_timeout(&tx_wait,
1135 msecs_to_jiffies(5000));
1136 if (timeout)
1137 return 0;
1138
1139 spin_lock_bh(&priv->tx_lock);
1140 priv->tx_wait = NULL;
1141 newcount = priv->pending_tx_pkts;
1142 mwl8k_scan_tx_ring(priv, txinfo);
1143 spin_unlock_bh(&priv->tx_lock);
1144
1145 printk(KERN_ERR "%s(%u) TIMEDOUT:5000ms Pend:%u-->%u\n",
1146 __func__, __LINE__, count, newcount);
1147
1148 for (index = 0; index < MWL8K_TX_QUEUES; index++)
1149 printk(KERN_ERR "TXQ:%u L:%u H:%u T:%u FW:%u "
1150 "DRV:%u U:%u\n",
1151 index,
1152 txinfo[index].len,
1153 txinfo[index].head,
1154 txinfo[index].tail,
1155 txinfo[index].fw_owned,
1156 txinfo[index].drv_owned,
1157 txinfo[index].unused);
1158
1159 return -ETIMEDOUT;
1160 }
1161
1162 return 0;
1163 }
1164
1165 #define MWL8K_TXD_SUCCESS(status) \
1166 ((status) & (MWL8K_TXD_STATUS_OK | \
1167 MWL8K_TXD_STATUS_OK_RETRY | \
1168 MWL8K_TXD_STATUS_OK_MORE_RETRY))
1169
1170 static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1171 {
1172 struct mwl8k_priv *priv = hw->priv;
1173 struct mwl8k_tx_queue *txq = priv->txq + index;
1174 int wake = 0;
1175
1176 while (txq->tx_stats.len > 0) {
1177 int tx;
1178 struct mwl8k_tx_desc *tx_desc;
1179 unsigned long addr;
1180 int size;
1181 struct sk_buff *skb;
1182 struct ieee80211_tx_info *info;
1183 u32 status;
1184
1185 tx = txq->tx_head;
1186 tx_desc = txq->tx_desc_area + tx;
1187
1188 status = le32_to_cpu(tx_desc->status);
1189
1190 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1191 if (!force)
1192 break;
1193 tx_desc->status &=
1194 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1195 }
1196
1197 txq->tx_head = (tx + 1) % MWL8K_TX_DESCS;
1198 BUG_ON(txq->tx_stats.len == 0);
1199 txq->tx_stats.len--;
1200 priv->pending_tx_pkts--;
1201
1202 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
1203 size = le16_to_cpu(tx_desc->pkt_len);
1204 skb = txq->tx_skb[tx];
1205 txq->tx_skb[tx] = NULL;
1206
1207 BUG_ON(skb == NULL);
1208 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1209
1210 mwl8k_remove_dma_header(skb);
1211
1212 /* Mark descriptor as unused */
1213 tx_desc->pkt_phys_addr = 0;
1214 tx_desc->pkt_len = 0;
1215
1216 info = IEEE80211_SKB_CB(skb);
1217 ieee80211_tx_info_clear_status(info);
1218 if (MWL8K_TXD_SUCCESS(status))
1219 info->flags |= IEEE80211_TX_STAT_ACK;
1220
1221 ieee80211_tx_status_irqsafe(hw, skb);
1222
1223 wake = 1;
1224 }
1225
1226 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
1227 ieee80211_wake_queue(hw, index);
1228 }
1229
1230 /* must be called only when the card's transmit is completely halted */
1231 static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1232 {
1233 struct mwl8k_priv *priv = hw->priv;
1234 struct mwl8k_tx_queue *txq = priv->txq + index;
1235
1236 mwl8k_txq_reclaim(hw, index, 1);
1237
1238 kfree(txq->tx_skb);
1239 txq->tx_skb = NULL;
1240
1241 pci_free_consistent(priv->pdev,
1242 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
1243 txq->tx_desc_area, txq->tx_desc_dma);
1244 txq->tx_desc_area = NULL;
1245 }
1246
1247 static int
1248 mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1249 {
1250 struct mwl8k_priv *priv = hw->priv;
1251 struct ieee80211_tx_info *tx_info;
1252 struct mwl8k_vif *mwl8k_vif;
1253 struct ieee80211_hdr *wh;
1254 struct mwl8k_tx_queue *txq;
1255 struct mwl8k_tx_desc *tx;
1256 dma_addr_t dma;
1257 u32 txstatus;
1258 u8 txdatarate;
1259 u16 qos;
1260
1261 wh = (struct ieee80211_hdr *)skb->data;
1262 if (ieee80211_is_data_qos(wh->frame_control))
1263 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1264 else
1265 qos = 0;
1266
1267 mwl8k_add_dma_header(skb);
1268 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
1269
1270 tx_info = IEEE80211_SKB_CB(skb);
1271 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
1272
1273 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1274 u16 seqno = mwl8k_vif->seqno;
1275
1276 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1277 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1278 mwl8k_vif->seqno = seqno++ % 4096;
1279 }
1280
1281 /* Setup firmware control bit fields for each frame type. */
1282 txstatus = 0;
1283 txdatarate = 0;
1284 if (ieee80211_is_mgmt(wh->frame_control) ||
1285 ieee80211_is_ctl(wh->frame_control)) {
1286 txdatarate = 0;
1287 qos = mwl8k_qos_setbit_eosp(qos);
1288 /* Set Queue size to unspecified */
1289 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1290 } else if (ieee80211_is_data(wh->frame_control)) {
1291 txdatarate = 1;
1292 if (is_multicast_ether_addr(wh->addr1))
1293 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1294
1295 /* Send pkt in an aggregate if AMPDU frame. */
1296 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1297 qos = mwl8k_qos_setbit_ack(qos,
1298 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1299 else
1300 qos = mwl8k_qos_setbit_ack(qos,
1301 MWL8K_TXD_ACK_POLICY_NORMAL);
1302
1303 if (qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
1304 qos = mwl8k_qos_setbit_amsdu(qos);
1305 }
1306
1307 dma = pci_map_single(priv->pdev, skb->data,
1308 skb->len, PCI_DMA_TODEVICE);
1309
1310 if (pci_dma_mapping_error(priv->pdev, dma)) {
1311 printk(KERN_DEBUG "%s: failed to dma map skb, "
1312 "dropping TX frame.\n", wiphy_name(hw->wiphy));
1313 dev_kfree_skb(skb);
1314 return NETDEV_TX_OK;
1315 }
1316
1317 spin_lock_bh(&priv->tx_lock);
1318
1319 txq = priv->txq + index;
1320
1321 BUG_ON(txq->tx_skb[txq->tx_tail] != NULL);
1322 txq->tx_skb[txq->tx_tail] = skb;
1323
1324 tx = txq->tx_desc_area + txq->tx_tail;
1325 tx->data_rate = txdatarate;
1326 tx->tx_priority = index;
1327 tx->qos_control = cpu_to_le16(qos);
1328 tx->pkt_phys_addr = cpu_to_le32(dma);
1329 tx->pkt_len = cpu_to_le16(skb->len);
1330 tx->rate_info = 0;
1331 tx->peer_id = mwl8k_vif->peer_id;
1332 wmb();
1333 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1334
1335 txq->tx_stats.count++;
1336 txq->tx_stats.len++;
1337 priv->pending_tx_pkts++;
1338
1339 txq->tx_tail++;
1340 if (txq->tx_tail == MWL8K_TX_DESCS)
1341 txq->tx_tail = 0;
1342
1343 if (txq->tx_head == txq->tx_tail)
1344 ieee80211_stop_queue(hw, index);
1345
1346 mwl8k_tx_start(priv);
1347
1348 spin_unlock_bh(&priv->tx_lock);
1349
1350 return NETDEV_TX_OK;
1351 }
1352
1353
1354 /*
1355 * Firmware access.
1356 *
1357 * We have the following requirements for issuing firmware commands:
1358 * - Some commands require that the packet transmit path is idle when
1359 * the command is issued. (For simplicity, we'll just quiesce the
1360 * transmit path for every command.)
1361 * - There are certain sequences of commands that need to be issued to
1362 * the hardware sequentially, with no other intervening commands.
1363 *
1364 * This leads to an implementation of a "firmware lock" as a mutex that
1365 * can be taken recursively, and which is taken by both the low-level
1366 * command submission function (mwl8k_post_cmd) as well as any users of
1367 * that function that require issuing of an atomic sequence of commands,
1368 * and quiesces the transmit path whenever it's taken.
1369 */
1370 static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1371 {
1372 struct mwl8k_priv *priv = hw->priv;
1373
1374 if (priv->fw_mutex_owner != current) {
1375 int rc;
1376
1377 mutex_lock(&priv->fw_mutex);
1378 ieee80211_stop_queues(hw);
1379
1380 rc = mwl8k_tx_wait_empty(hw);
1381 if (rc) {
1382 ieee80211_wake_queues(hw);
1383 mutex_unlock(&priv->fw_mutex);
1384
1385 return rc;
1386 }
1387
1388 priv->fw_mutex_owner = current;
1389 }
1390
1391 priv->fw_mutex_depth++;
1392
1393 return 0;
1394 }
1395
1396 static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1397 {
1398 struct mwl8k_priv *priv = hw->priv;
1399
1400 if (!--priv->fw_mutex_depth) {
1401 ieee80211_wake_queues(hw);
1402 priv->fw_mutex_owner = NULL;
1403 mutex_unlock(&priv->fw_mutex);
1404 }
1405 }
1406
1407
1408 /*
1409 * Command processing.
1410 */
1411
1412 /* Timeout firmware commands after 2000ms */
1413 #define MWL8K_CMD_TIMEOUT_MS 2000
1414
1415 static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1416 {
1417 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1418 struct mwl8k_priv *priv = hw->priv;
1419 void __iomem *regs = priv->regs;
1420 dma_addr_t dma_addr;
1421 unsigned int dma_size;
1422 int rc;
1423 unsigned long timeout = 0;
1424 u8 buf[32];
1425
1426 cmd->result = 0xffff;
1427 dma_size = le16_to_cpu(cmd->length);
1428 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1429 PCI_DMA_BIDIRECTIONAL);
1430 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1431 return -ENOMEM;
1432
1433 rc = mwl8k_fw_lock(hw);
1434 if (rc) {
1435 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1436 PCI_DMA_BIDIRECTIONAL);
1437 return rc;
1438 }
1439
1440 priv->hostcmd_wait = &cmd_wait;
1441 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1442 iowrite32(MWL8K_H2A_INT_DOORBELL,
1443 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1444 iowrite32(MWL8K_H2A_INT_DUMMY,
1445 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1446
1447 timeout = wait_for_completion_timeout(&cmd_wait,
1448 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1449
1450 priv->hostcmd_wait = NULL;
1451
1452 mwl8k_fw_unlock(hw);
1453
1454 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1455 PCI_DMA_BIDIRECTIONAL);
1456
1457 if (!timeout) {
1458 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
1459 wiphy_name(hw->wiphy),
1460 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1461 MWL8K_CMD_TIMEOUT_MS);
1462 rc = -ETIMEDOUT;
1463 } else {
1464 rc = cmd->result ? -EINVAL : 0;
1465 if (rc)
1466 printk(KERN_ERR "%s: Command %s error 0x%x\n",
1467 wiphy_name(hw->wiphy),
1468 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1469 le16_to_cpu(cmd->result));
1470 }
1471
1472 return rc;
1473 }
1474
1475 /*
1476 * GET_HW_SPEC.
1477 */
1478 struct mwl8k_cmd_get_hw_spec {
1479 struct mwl8k_cmd_pkt header;
1480 __u8 hw_rev;
1481 __u8 host_interface;
1482 __le16 num_mcaddrs;
1483 __u8 perm_addr[ETH_ALEN];
1484 __le16 region_code;
1485 __le32 fw_rev;
1486 __le32 ps_cookie;
1487 __le32 caps;
1488 __u8 mcs_bitmap[16];
1489 __le32 rx_queue_ptr;
1490 __le32 num_tx_queues;
1491 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1492 __le32 caps2;
1493 __le32 num_tx_desc_per_queue;
1494 __le32 total_rx_desc;
1495 } __attribute__((packed));
1496
1497 static int mwl8k_cmd_get_hw_spec(struct ieee80211_hw *hw)
1498 {
1499 struct mwl8k_priv *priv = hw->priv;
1500 struct mwl8k_cmd_get_hw_spec *cmd;
1501 int rc;
1502 int i;
1503
1504 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1505 if (cmd == NULL)
1506 return -ENOMEM;
1507
1508 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1509 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1510
1511 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1512 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1513 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rx_desc_dma);
1514 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1515 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1516 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].tx_desc_dma);
1517 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1518 cmd->total_rx_desc = cpu_to_le32(MWL8K_RX_DESCS);
1519
1520 rc = mwl8k_post_cmd(hw, &cmd->header);
1521
1522 if (!rc) {
1523 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1524 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1525 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1526 priv->hw_rev = cmd->hw_rev;
1527 }
1528
1529 kfree(cmd);
1530 return rc;
1531 }
1532
1533 /*
1534 * CMD_MAC_MULTICAST_ADR.
1535 */
1536 struct mwl8k_cmd_mac_multicast_adr {
1537 struct mwl8k_cmd_pkt header;
1538 __le16 action;
1539 __le16 numaddr;
1540 __u8 addr[0][ETH_ALEN];
1541 };
1542
1543 #define MWL8K_ENABLE_RX_DIRECTED 0x0001
1544 #define MWL8K_ENABLE_RX_MULTICAST 0x0002
1545 #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1546 #define MWL8K_ENABLE_RX_BROADCAST 0x0008
1547
1548 static struct mwl8k_cmd_pkt *
1549 __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
1550 int mc_count, struct dev_addr_list *mclist)
1551 {
1552 struct mwl8k_priv *priv = hw->priv;
1553 struct mwl8k_cmd_mac_multicast_adr *cmd;
1554 int size;
1555
1556 if (allmulti || mc_count > priv->num_mcaddrs) {
1557 allmulti = 1;
1558 mc_count = 0;
1559 }
1560
1561 size = sizeof(*cmd) + mc_count * ETH_ALEN;
1562
1563 cmd = kzalloc(size, GFP_ATOMIC);
1564 if (cmd == NULL)
1565 return NULL;
1566
1567 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1568 cmd->header.length = cpu_to_le16(size);
1569 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1570 MWL8K_ENABLE_RX_BROADCAST);
1571
1572 if (allmulti) {
1573 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1574 } else if (mc_count) {
1575 int i;
1576
1577 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1578 cmd->numaddr = cpu_to_le16(mc_count);
1579 for (i = 0; i < mc_count && mclist; i++) {
1580 if (mclist->da_addrlen != ETH_ALEN) {
1581 kfree(cmd);
1582 return NULL;
1583 }
1584 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1585 mclist = mclist->next;
1586 }
1587 }
1588
1589 return &cmd->header;
1590 }
1591
1592 /*
1593 * CMD_802_11_GET_STAT.
1594 */
1595 struct mwl8k_cmd_802_11_get_stat {
1596 struct mwl8k_cmd_pkt header;
1597 __le32 stats[64];
1598 } __attribute__((packed));
1599
1600 #define MWL8K_STAT_ACK_FAILURE 9
1601 #define MWL8K_STAT_RTS_FAILURE 12
1602 #define MWL8K_STAT_FCS_ERROR 24
1603 #define MWL8K_STAT_RTS_SUCCESS 11
1604
1605 static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1606 struct ieee80211_low_level_stats *stats)
1607 {
1608 struct mwl8k_cmd_802_11_get_stat *cmd;
1609 int rc;
1610
1611 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1612 if (cmd == NULL)
1613 return -ENOMEM;
1614
1615 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1616 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1617
1618 rc = mwl8k_post_cmd(hw, &cmd->header);
1619 if (!rc) {
1620 stats->dot11ACKFailureCount =
1621 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1622 stats->dot11RTSFailureCount =
1623 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1624 stats->dot11FCSErrorCount =
1625 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1626 stats->dot11RTSSuccessCount =
1627 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1628 }
1629 kfree(cmd);
1630
1631 return rc;
1632 }
1633
1634 /*
1635 * CMD_802_11_RADIO_CONTROL.
1636 */
1637 struct mwl8k_cmd_802_11_radio_control {
1638 struct mwl8k_cmd_pkt header;
1639 __le16 action;
1640 __le16 control;
1641 __le16 radio_on;
1642 } __attribute__((packed));
1643
1644 static int
1645 mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
1646 {
1647 struct mwl8k_priv *priv = hw->priv;
1648 struct mwl8k_cmd_802_11_radio_control *cmd;
1649 int rc;
1650
1651 if (enable == priv->radio_on && !force)
1652 return 0;
1653
1654 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1655 if (cmd == NULL)
1656 return -ENOMEM;
1657
1658 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1659 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1660 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1661 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
1662 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1663
1664 rc = mwl8k_post_cmd(hw, &cmd->header);
1665 kfree(cmd);
1666
1667 if (!rc)
1668 priv->radio_on = enable;
1669
1670 return rc;
1671 }
1672
1673 static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw)
1674 {
1675 return mwl8k_cmd_802_11_radio_control(hw, 0, 0);
1676 }
1677
1678 static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw)
1679 {
1680 return mwl8k_cmd_802_11_radio_control(hw, 1, 0);
1681 }
1682
1683 static int
1684 mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1685 {
1686 struct mwl8k_priv *priv;
1687
1688 if (hw == NULL || hw->priv == NULL)
1689 return -EINVAL;
1690 priv = hw->priv;
1691
1692 priv->radio_short_preamble = short_preamble;
1693
1694 return mwl8k_cmd_802_11_radio_control(hw, 1, 1);
1695 }
1696
1697 /*
1698 * CMD_802_11_RF_TX_POWER.
1699 */
1700 #define MWL8K_TX_POWER_LEVEL_TOTAL 8
1701
1702 struct mwl8k_cmd_802_11_rf_tx_power {
1703 struct mwl8k_cmd_pkt header;
1704 __le16 action;
1705 __le16 support_level;
1706 __le16 current_level;
1707 __le16 reserved;
1708 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1709 } __attribute__((packed));
1710
1711 static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
1712 {
1713 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
1714 int rc;
1715
1716 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1717 if (cmd == NULL)
1718 return -ENOMEM;
1719
1720 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1721 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1722 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1723 cmd->support_level = cpu_to_le16(dBm);
1724
1725 rc = mwl8k_post_cmd(hw, &cmd->header);
1726 kfree(cmd);
1727
1728 return rc;
1729 }
1730
1731 /*
1732 * CMD_SET_PRE_SCAN.
1733 */
1734 struct mwl8k_cmd_set_pre_scan {
1735 struct mwl8k_cmd_pkt header;
1736 } __attribute__((packed));
1737
1738 static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
1739 {
1740 struct mwl8k_cmd_set_pre_scan *cmd;
1741 int rc;
1742
1743 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1744 if (cmd == NULL)
1745 return -ENOMEM;
1746
1747 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
1748 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1749
1750 rc = mwl8k_post_cmd(hw, &cmd->header);
1751 kfree(cmd);
1752
1753 return rc;
1754 }
1755
1756 /*
1757 * CMD_SET_POST_SCAN.
1758 */
1759 struct mwl8k_cmd_set_post_scan {
1760 struct mwl8k_cmd_pkt header;
1761 __le32 isibss;
1762 __u8 bssid[ETH_ALEN];
1763 } __attribute__((packed));
1764
1765 static int
1766 mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
1767 {
1768 struct mwl8k_cmd_set_post_scan *cmd;
1769 int rc;
1770
1771 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1772 if (cmd == NULL)
1773 return -ENOMEM;
1774
1775 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
1776 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1777 cmd->isibss = 0;
1778 memcpy(cmd->bssid, mac, ETH_ALEN);
1779
1780 rc = mwl8k_post_cmd(hw, &cmd->header);
1781 kfree(cmd);
1782
1783 return rc;
1784 }
1785
1786 /*
1787 * CMD_SET_RF_CHANNEL.
1788 */
1789 struct mwl8k_cmd_set_rf_channel {
1790 struct mwl8k_cmd_pkt header;
1791 __le16 action;
1792 __u8 current_channel;
1793 __le32 channel_flags;
1794 } __attribute__((packed));
1795
1796 static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
1797 struct ieee80211_channel *channel)
1798 {
1799 struct mwl8k_cmd_set_rf_channel *cmd;
1800 int rc;
1801
1802 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1803 if (cmd == NULL)
1804 return -ENOMEM;
1805
1806 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
1807 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1808 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1809 cmd->current_channel = channel->hw_value;
1810 if (channel->band == IEEE80211_BAND_2GHZ)
1811 cmd->channel_flags = cpu_to_le32(0x00000081);
1812 else
1813 cmd->channel_flags = cpu_to_le32(0x00000000);
1814
1815 rc = mwl8k_post_cmd(hw, &cmd->header);
1816 kfree(cmd);
1817
1818 return rc;
1819 }
1820
1821 /*
1822 * CMD_SET_SLOT.
1823 */
1824 struct mwl8k_cmd_set_slot {
1825 struct mwl8k_cmd_pkt header;
1826 __le16 action;
1827 __u8 short_slot;
1828 } __attribute__((packed));
1829
1830 static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
1831 {
1832 struct mwl8k_cmd_set_slot *cmd;
1833 int rc;
1834
1835 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1836 if (cmd == NULL)
1837 return -ENOMEM;
1838
1839 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
1840 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1841 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1842 cmd->short_slot = short_slot_time;
1843
1844 rc = mwl8k_post_cmd(hw, &cmd->header);
1845 kfree(cmd);
1846
1847 return rc;
1848 }
1849
1850 /*
1851 * CMD_MIMO_CONFIG.
1852 */
1853 struct mwl8k_cmd_mimo_config {
1854 struct mwl8k_cmd_pkt header;
1855 __le32 action;
1856 __u8 rx_antenna_map;
1857 __u8 tx_antenna_map;
1858 } __attribute__((packed));
1859
1860 static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
1861 {
1862 struct mwl8k_cmd_mimo_config *cmd;
1863 int rc;
1864
1865 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1866 if (cmd == NULL)
1867 return -ENOMEM;
1868
1869 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
1870 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1871 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
1872 cmd->rx_antenna_map = rx;
1873 cmd->tx_antenna_map = tx;
1874
1875 rc = mwl8k_post_cmd(hw, &cmd->header);
1876 kfree(cmd);
1877
1878 return rc;
1879 }
1880
1881 /*
1882 * CMD_ENABLE_SNIFFER.
1883 */
1884 struct mwl8k_cmd_enable_sniffer {
1885 struct mwl8k_cmd_pkt header;
1886 __le32 action;
1887 } __attribute__((packed));
1888
1889 static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
1890 {
1891 struct mwl8k_cmd_enable_sniffer *cmd;
1892 int rc;
1893
1894 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1895 if (cmd == NULL)
1896 return -ENOMEM;
1897
1898 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
1899 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1900 cmd->action = cpu_to_le32(!!enable);
1901
1902 rc = mwl8k_post_cmd(hw, &cmd->header);
1903 kfree(cmd);
1904
1905 return rc;
1906 }
1907
1908 /*
1909 * CMD_SET_MAC_ADDR.
1910 */
1911 struct mwl8k_cmd_set_mac_addr {
1912 struct mwl8k_cmd_pkt header;
1913 __u8 mac_addr[ETH_ALEN];
1914 } __attribute__((packed));
1915
1916 static int mwl8k_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
1917 {
1918 struct mwl8k_cmd_set_mac_addr *cmd;
1919 int rc;
1920
1921 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1922 if (cmd == NULL)
1923 return -ENOMEM;
1924
1925 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
1926 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1927 memcpy(cmd->mac_addr, mac, ETH_ALEN);
1928
1929 rc = mwl8k_post_cmd(hw, &cmd->header);
1930 kfree(cmd);
1931
1932 return rc;
1933 }
1934
1935
1936 /*
1937 * CMD_SET_RATEADAPT_MODE.
1938 */
1939 struct mwl8k_cmd_set_rate_adapt_mode {
1940 struct mwl8k_cmd_pkt header;
1941 __le16 action;
1942 __le16 mode;
1943 } __attribute__((packed));
1944
1945 static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
1946 {
1947 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
1948 int rc;
1949
1950 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1951 if (cmd == NULL)
1952 return -ENOMEM;
1953
1954 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
1955 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1956 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1957 cmd->mode = cpu_to_le16(mode);
1958
1959 rc = mwl8k_post_cmd(hw, &cmd->header);
1960 kfree(cmd);
1961
1962 return rc;
1963 }
1964
1965 /*
1966 * CMD_SET_WMM_MODE.
1967 */
1968 struct mwl8k_cmd_set_wmm {
1969 struct mwl8k_cmd_pkt header;
1970 __le16 action;
1971 } __attribute__((packed));
1972
1973 static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
1974 {
1975 struct mwl8k_priv *priv = hw->priv;
1976 struct mwl8k_cmd_set_wmm *cmd;
1977 int rc;
1978
1979 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1980 if (cmd == NULL)
1981 return -ENOMEM;
1982
1983 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
1984 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1985 cmd->action = cpu_to_le16(!!enable);
1986
1987 rc = mwl8k_post_cmd(hw, &cmd->header);
1988 kfree(cmd);
1989
1990 if (!rc)
1991 priv->wmm_enabled = enable;
1992
1993 return rc;
1994 }
1995
1996 /*
1997 * CMD_SET_RTS_THRESHOLD.
1998 */
1999 struct mwl8k_cmd_rts_threshold {
2000 struct mwl8k_cmd_pkt header;
2001 __le16 action;
2002 __le16 threshold;
2003 } __attribute__((packed));
2004
2005 static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
2006 u16 action, u16 threshold)
2007 {
2008 struct mwl8k_cmd_rts_threshold *cmd;
2009 int rc;
2010
2011 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2012 if (cmd == NULL)
2013 return -ENOMEM;
2014
2015 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2016 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2017 cmd->action = cpu_to_le16(action);
2018 cmd->threshold = cpu_to_le16(threshold);
2019
2020 rc = mwl8k_post_cmd(hw, &cmd->header);
2021 kfree(cmd);
2022
2023 return rc;
2024 }
2025
2026 /*
2027 * CMD_SET_EDCA_PARAMS.
2028 */
2029 struct mwl8k_cmd_set_edca_params {
2030 struct mwl8k_cmd_pkt header;
2031
2032 /* See MWL8K_SET_EDCA_XXX below */
2033 __le16 action;
2034
2035 /* TX opportunity in units of 32 us */
2036 __le16 txop;
2037
2038 /* Log exponent of max contention period: 0...15*/
2039 __u8 log_cw_max;
2040
2041 /* Log exponent of min contention period: 0...15 */
2042 __u8 log_cw_min;
2043
2044 /* Adaptive interframe spacing in units of 32us */
2045 __u8 aifs;
2046
2047 /* TX queue to configure */
2048 __u8 txq;
2049 } __attribute__((packed));
2050
2051 #define MWL8K_SET_EDCA_CW 0x01
2052 #define MWL8K_SET_EDCA_TXOP 0x02
2053 #define MWL8K_SET_EDCA_AIFS 0x04
2054
2055 #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2056 MWL8K_SET_EDCA_TXOP | \
2057 MWL8K_SET_EDCA_AIFS)
2058
2059 static int
2060 mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2061 __u16 cw_min, __u16 cw_max,
2062 __u8 aifs, __u16 txop)
2063 {
2064 struct mwl8k_cmd_set_edca_params *cmd;
2065 int rc;
2066
2067 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2068 if (cmd == NULL)
2069 return -ENOMEM;
2070
2071 /*
2072 * Queues 0 (BE) and 1 (BK) are swapped in hardware for
2073 * this call.
2074 */
2075 qnum ^= !(qnum >> 1);
2076
2077 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2078 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2079 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2080 cmd->txop = cpu_to_le16(txop);
2081 cmd->log_cw_max = (u8)ilog2(cw_max + 1);
2082 cmd->log_cw_min = (u8)ilog2(cw_min + 1);
2083 cmd->aifs = aifs;
2084 cmd->txq = qnum;
2085
2086 rc = mwl8k_post_cmd(hw, &cmd->header);
2087 kfree(cmd);
2088
2089 return rc;
2090 }
2091
2092 /*
2093 * CMD_FINALIZE_JOIN.
2094 */
2095
2096 /* FJ beacon buffer size is compiled into the firmware. */
2097 #define MWL8K_FJ_BEACON_MAXLEN 128
2098
2099 struct mwl8k_cmd_finalize_join {
2100 struct mwl8k_cmd_pkt header;
2101 __le32 sleep_interval; /* Number of beacon periods to sleep */
2102 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2103 } __attribute__((packed));
2104
2105 static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2106 __u16 framelen, __u16 dtim)
2107 {
2108 struct mwl8k_cmd_finalize_join *cmd;
2109 struct ieee80211_mgmt *payload = frame;
2110 u16 hdrlen;
2111 u32 payload_len;
2112 int rc;
2113
2114 if (frame == NULL)
2115 return -EINVAL;
2116
2117 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2118 if (cmd == NULL)
2119 return -ENOMEM;
2120
2121 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2122 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2123 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2124
2125 hdrlen = ieee80211_hdrlen(payload->frame_control);
2126
2127 payload_len = framelen > hdrlen ? framelen - hdrlen : 0;
2128
2129 /* XXX TBD Might just have to abort and return an error */
2130 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2131 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
2132 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2133 payload_len, MWL8K_FJ_BEACON_MAXLEN);
2134
2135 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2136 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2137
2138 if (payload && payload_len)
2139 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2140
2141 rc = mwl8k_post_cmd(hw, &cmd->header);
2142 kfree(cmd);
2143 return rc;
2144 }
2145
2146 /*
2147 * CMD_UPDATE_STADB.
2148 */
2149 struct mwl8k_cmd_update_sta_db {
2150 struct mwl8k_cmd_pkt header;
2151
2152 /* See STADB_ACTION_TYPE */
2153 __le32 action;
2154
2155 /* Peer MAC address */
2156 __u8 peer_addr[ETH_ALEN];
2157
2158 __le32 reserved;
2159
2160 /* Peer info - valid during add/update. */
2161 struct peer_capability_info peer_info;
2162 } __attribute__((packed));
2163
2164 static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2165 struct ieee80211_vif *vif, __u32 action)
2166 {
2167 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2168 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2169 struct mwl8k_cmd_update_sta_db *cmd;
2170 struct peer_capability_info *peer_info;
2171 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2172 int rc;
2173 __u8 count, *rates;
2174
2175 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2176 if (cmd == NULL)
2177 return -ENOMEM;
2178
2179 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2180 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2181
2182 cmd->action = cpu_to_le32(action);
2183 peer_info = &cmd->peer_info;
2184 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
2185
2186 switch (action) {
2187 case MWL8K_STA_DB_ADD_ENTRY:
2188 case MWL8K_STA_DB_MODIFY_ENTRY:
2189 /* Build peer_info block */
2190 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2191 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
2192 peer_info->interop = 1;
2193 peer_info->amsdu_enabled = 0;
2194
2195 rates = peer_info->legacy_rates;
2196 for (count = 0; count < mv_vif->legacy_nrates; count++)
2197 rates[count] = bitrates[count].hw_value;
2198
2199 rc = mwl8k_post_cmd(hw, &cmd->header);
2200 if (rc == 0)
2201 mv_vif->peer_id = peer_info->station_id;
2202
2203 break;
2204
2205 case MWL8K_STA_DB_DEL_ENTRY:
2206 case MWL8K_STA_DB_FLUSH:
2207 default:
2208 rc = mwl8k_post_cmd(hw, &cmd->header);
2209 if (rc == 0)
2210 mv_vif->peer_id = 0;
2211 break;
2212 }
2213 kfree(cmd);
2214
2215 return rc;
2216 }
2217
2218 /*
2219 * CMD_SET_AID.
2220 */
2221 #define MWL8K_RATE_INDEX_MAX_ARRAY 14
2222
2223 #define MWL8K_FRAME_PROT_DISABLED 0x00
2224 #define MWL8K_FRAME_PROT_11G 0x07
2225 #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2226 #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
2227
2228 struct mwl8k_cmd_update_set_aid {
2229 struct mwl8k_cmd_pkt header;
2230 __le16 aid;
2231
2232 /* AP's MAC address (BSSID) */
2233 __u8 bssid[ETH_ALEN];
2234 __le16 protection_mode;
2235 __u8 supp_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2236 } __attribute__((packed));
2237
2238 static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2239 struct ieee80211_vif *vif)
2240 {
2241 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2242 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2243 struct mwl8k_cmd_update_set_aid *cmd;
2244 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2245 int count;
2246 u16 prot_mode;
2247 int rc;
2248
2249 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2250 if (cmd == NULL)
2251 return -ENOMEM;
2252
2253 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2254 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2255 cmd->aid = cpu_to_le16(info->aid);
2256
2257 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
2258
2259 if (info->use_cts_prot) {
2260 prot_mode = MWL8K_FRAME_PROT_11G;
2261 } else {
2262 switch (info->ht_operation_mode &
2263 IEEE80211_HT_OP_MODE_PROTECTION) {
2264 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2265 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2266 break;
2267 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2268 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2269 break;
2270 default:
2271 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2272 break;
2273 }
2274 }
2275 cmd->protection_mode = cpu_to_le16(prot_mode);
2276
2277 for (count = 0; count < mv_vif->legacy_nrates; count++)
2278 cmd->supp_rates[count] = bitrates[count].hw_value;
2279
2280 rc = mwl8k_post_cmd(hw, &cmd->header);
2281 kfree(cmd);
2282
2283 return rc;
2284 }
2285
2286 /*
2287 * CMD_SET_RATE.
2288 */
2289 struct mwl8k_cmd_update_rateset {
2290 struct mwl8k_cmd_pkt header;
2291 __u8 legacy_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2292
2293 /* Bitmap for supported MCS codes. */
2294 __u8 mcs_set[MWL8K_IEEE_LEGACY_DATA_RATES];
2295 __u8 reserved[MWL8K_IEEE_LEGACY_DATA_RATES];
2296 } __attribute__((packed));
2297
2298 static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2299 struct ieee80211_vif *vif)
2300 {
2301 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2302 struct mwl8k_cmd_update_rateset *cmd;
2303 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2304 int count;
2305 int rc;
2306
2307 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2308 if (cmd == NULL)
2309 return -ENOMEM;
2310
2311 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2312 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2313
2314 for (count = 0; count < mv_vif->legacy_nrates; count++)
2315 cmd->legacy_rates[count] = bitrates[count].hw_value;
2316
2317 rc = mwl8k_post_cmd(hw, &cmd->header);
2318 kfree(cmd);
2319
2320 return rc;
2321 }
2322
2323 /*
2324 * CMD_USE_FIXED_RATE.
2325 */
2326 #define MWL8K_RATE_TABLE_SIZE 8
2327 #define MWL8K_UCAST_RATE 0
2328 #define MWL8K_USE_AUTO_RATE 0x0002
2329
2330 struct mwl8k_rate_entry {
2331 /* Set to 1 if HT rate, 0 if legacy. */
2332 __le32 is_ht_rate;
2333
2334 /* Set to 1 to use retry_count field. */
2335 __le32 enable_retry;
2336
2337 /* Specified legacy rate or MCS. */
2338 __le32 rate;
2339
2340 /* Number of allowed retries. */
2341 __le32 retry_count;
2342 } __attribute__((packed));
2343
2344 struct mwl8k_rate_table {
2345 /* 1 to allow specified rate and below */
2346 __le32 allow_rate_drop;
2347 __le32 num_rates;
2348 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2349 } __attribute__((packed));
2350
2351 struct mwl8k_cmd_use_fixed_rate {
2352 struct mwl8k_cmd_pkt header;
2353 __le32 action;
2354 struct mwl8k_rate_table rate_table;
2355
2356 /* Unicast, Broadcast or Multicast */
2357 __le32 rate_type;
2358 __le32 reserved1;
2359 __le32 reserved2;
2360 } __attribute__((packed));
2361
2362 static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2363 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2364 {
2365 struct mwl8k_cmd_use_fixed_rate *cmd;
2366 int count;
2367 int rc;
2368
2369 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2370 if (cmd == NULL)
2371 return -ENOMEM;
2372
2373 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2374 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2375
2376 cmd->action = cpu_to_le32(action);
2377 cmd->rate_type = cpu_to_le32(rate_type);
2378
2379 if (rate_table != NULL) {
2380 /*
2381 * Copy over each field manually so that endian
2382 * conversion can be done.
2383 */
2384 cmd->rate_table.allow_rate_drop =
2385 cpu_to_le32(rate_table->allow_rate_drop);
2386 cmd->rate_table.num_rates =
2387 cpu_to_le32(rate_table->num_rates);
2388
2389 for (count = 0; count < rate_table->num_rates; count++) {
2390 struct mwl8k_rate_entry *dst =
2391 &cmd->rate_table.rate_entry[count];
2392 struct mwl8k_rate_entry *src =
2393 &rate_table->rate_entry[count];
2394
2395 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2396 dst->enable_retry = cpu_to_le32(src->enable_retry);
2397 dst->rate = cpu_to_le32(src->rate);
2398 dst->retry_count = cpu_to_le32(src->retry_count);
2399 }
2400 }
2401
2402 rc = mwl8k_post_cmd(hw, &cmd->header);
2403 kfree(cmd);
2404
2405 return rc;
2406 }
2407
2408
2409 /*
2410 * Interrupt handling.
2411 */
2412 static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2413 {
2414 struct ieee80211_hw *hw = dev_id;
2415 struct mwl8k_priv *priv = hw->priv;
2416 u32 status;
2417
2418 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2419 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2420
2421 if (!status)
2422 return IRQ_NONE;
2423
2424 if (status & MWL8K_A2H_INT_TX_DONE)
2425 tasklet_schedule(&priv->tx_reclaim_task);
2426
2427 if (status & MWL8K_A2H_INT_RX_READY) {
2428 while (rxq_process(hw, 0, 1))
2429 rxq_refill(hw, 0, 1);
2430 }
2431
2432 if (status & MWL8K_A2H_INT_OPC_DONE) {
2433 if (priv->hostcmd_wait != NULL)
2434 complete(priv->hostcmd_wait);
2435 }
2436
2437 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
2438 if (!mutex_is_locked(&priv->fw_mutex) &&
2439 priv->radio_on && priv->pending_tx_pkts)
2440 mwl8k_tx_start(priv);
2441 }
2442
2443 return IRQ_HANDLED;
2444 }
2445
2446
2447 /*
2448 * Core driver operations.
2449 */
2450 static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2451 {
2452 struct mwl8k_priv *priv = hw->priv;
2453 int index = skb_get_queue_mapping(skb);
2454 int rc;
2455
2456 if (priv->current_channel == NULL) {
2457 printk(KERN_DEBUG "%s: dropped TX frame since radio "
2458 "disabled\n", wiphy_name(hw->wiphy));
2459 dev_kfree_skb(skb);
2460 return NETDEV_TX_OK;
2461 }
2462
2463 rc = mwl8k_txq_xmit(hw, index, skb);
2464
2465 return rc;
2466 }
2467
2468 static int mwl8k_start(struct ieee80211_hw *hw)
2469 {
2470 struct mwl8k_priv *priv = hw->priv;
2471 int rc;
2472
2473 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
2474 IRQF_SHARED, MWL8K_NAME, hw);
2475 if (rc) {
2476 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2477 wiphy_name(hw->wiphy));
2478 return -EIO;
2479 }
2480
2481 /* Enable tx reclaim tasklet */
2482 tasklet_enable(&priv->tx_reclaim_task);
2483
2484 /* Enable interrupts */
2485 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2486
2487 rc = mwl8k_fw_lock(hw);
2488 if (!rc) {
2489 rc = mwl8k_cmd_802_11_radio_enable(hw);
2490
2491 if (!rc)
2492 rc = mwl8k_cmd_set_pre_scan(hw);
2493
2494 if (!rc)
2495 rc = mwl8k_cmd_set_post_scan(hw,
2496 "\x00\x00\x00\x00\x00\x00");
2497
2498 if (!rc)
2499 rc = mwl8k_cmd_setrateadaptmode(hw, 0);
2500
2501 if (!rc)
2502 rc = mwl8k_set_wmm(hw, 0);
2503
2504 if (!rc)
2505 rc = mwl8k_enable_sniffer(hw, 0);
2506
2507 mwl8k_fw_unlock(hw);
2508 }
2509
2510 if (rc) {
2511 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2512 free_irq(priv->pdev->irq, hw);
2513 tasklet_disable(&priv->tx_reclaim_task);
2514 }
2515
2516 return rc;
2517 }
2518
2519 static void mwl8k_stop(struct ieee80211_hw *hw)
2520 {
2521 struct mwl8k_priv *priv = hw->priv;
2522 int i;
2523
2524 mwl8k_cmd_802_11_radio_disable(hw);
2525
2526 ieee80211_stop_queues(hw);
2527
2528 /* Disable interrupts */
2529 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2530 free_irq(priv->pdev->irq, hw);
2531
2532 /* Stop finalize join worker */
2533 cancel_work_sync(&priv->finalize_join_worker);
2534 if (priv->beacon_skb != NULL)
2535 dev_kfree_skb(priv->beacon_skb);
2536
2537 /* Stop tx reclaim tasklet */
2538 tasklet_disable(&priv->tx_reclaim_task);
2539
2540 /* Return all skbs to mac80211 */
2541 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2542 mwl8k_txq_reclaim(hw, i, 1);
2543 }
2544
2545 static int mwl8k_add_interface(struct ieee80211_hw *hw,
2546 struct ieee80211_if_init_conf *conf)
2547 {
2548 struct mwl8k_priv *priv = hw->priv;
2549 struct mwl8k_vif *mwl8k_vif;
2550
2551 /*
2552 * We only support one active interface at a time.
2553 */
2554 if (priv->vif != NULL)
2555 return -EBUSY;
2556
2557 /*
2558 * We only support managed interfaces for now.
2559 */
2560 if (conf->type != NL80211_IFTYPE_STATION)
2561 return -EINVAL;
2562
2563 /* Clean out driver private area */
2564 mwl8k_vif = MWL8K_VIF(conf->vif);
2565 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2566
2567 /* Set and save the mac address */
2568 mwl8k_set_mac_addr(hw, conf->mac_addr);
2569 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
2570
2571 /* Back pointer to parent config block */
2572 mwl8k_vif->priv = priv;
2573
2574 /* Setup initial PHY parameters */
2575 memcpy(mwl8k_vif->legacy_rates,
2576 priv->rates, sizeof(mwl8k_vif->legacy_rates));
2577 mwl8k_vif->legacy_nrates = ARRAY_SIZE(priv->rates);
2578
2579 /* Set Initial sequence number to zero */
2580 mwl8k_vif->seqno = 0;
2581
2582 priv->vif = conf->vif;
2583 priv->current_channel = NULL;
2584
2585 return 0;
2586 }
2587
2588 static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2589 struct ieee80211_if_init_conf *conf)
2590 {
2591 struct mwl8k_priv *priv = hw->priv;
2592
2593 if (priv->vif == NULL)
2594 return;
2595
2596 mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
2597
2598 priv->vif = NULL;
2599 }
2600
2601 static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
2602 {
2603 struct ieee80211_conf *conf = &hw->conf;
2604 struct mwl8k_priv *priv = hw->priv;
2605 int rc;
2606
2607 if (conf->flags & IEEE80211_CONF_IDLE) {
2608 mwl8k_cmd_802_11_radio_disable(hw);
2609 priv->current_channel = NULL;
2610 return 0;
2611 }
2612
2613 rc = mwl8k_fw_lock(hw);
2614 if (rc)
2615 return rc;
2616
2617 rc = mwl8k_cmd_802_11_radio_enable(hw);
2618 if (rc)
2619 goto out;
2620
2621 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2622 if (rc)
2623 goto out;
2624
2625 priv->current_channel = conf->channel;
2626
2627 if (conf->power_level > 18)
2628 conf->power_level = 18;
2629 rc = mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level);
2630 if (rc)
2631 goto out;
2632
2633 if (mwl8k_cmd_mimo_config(hw, 0x7, 0x7))
2634 rc = -EINVAL;
2635
2636 out:
2637 mwl8k_fw_unlock(hw);
2638
2639 return rc;
2640 }
2641
2642 static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
2643 struct ieee80211_vif *vif,
2644 struct ieee80211_bss_conf *info,
2645 u32 changed)
2646 {
2647 struct mwl8k_priv *priv = hw->priv;
2648 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
2649 int rc;
2650
2651 if (changed & BSS_CHANGED_BSSID)
2652 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
2653
2654 if ((changed & BSS_CHANGED_ASSOC) == 0)
2655 return;
2656
2657 priv->capture_beacon = false;
2658
2659 rc = mwl8k_fw_lock(hw);
2660 if (rc)
2661 return;
2662
2663 if (info->assoc) {
2664 memcpy(&mwl8k_vif->bss_info, info,
2665 sizeof(struct ieee80211_bss_conf));
2666
2667 /* Install rates */
2668 rc = mwl8k_update_rateset(hw, vif);
2669 if (rc)
2670 goto out;
2671
2672 /* Turn on rate adaptation */
2673 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
2674 MWL8K_UCAST_RATE, NULL);
2675 if (rc)
2676 goto out;
2677
2678 /* Set radio preamble */
2679 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
2680 if (rc)
2681 goto out;
2682
2683 /* Set slot time */
2684 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
2685 if (rc)
2686 goto out;
2687
2688 /* Update peer rate info */
2689 rc = mwl8k_cmd_update_sta_db(hw, vif,
2690 MWL8K_STA_DB_MODIFY_ENTRY);
2691 if (rc)
2692 goto out;
2693
2694 /* Set AID */
2695 rc = mwl8k_cmd_set_aid(hw, vif);
2696 if (rc)
2697 goto out;
2698
2699 /*
2700 * Finalize the join. Tell rx handler to process
2701 * next beacon from our BSSID.
2702 */
2703 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
2704 priv->capture_beacon = true;
2705 } else {
2706 rc = mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
2707 memset(&mwl8k_vif->bss_info, 0,
2708 sizeof(struct ieee80211_bss_conf));
2709 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
2710 }
2711
2712 out:
2713 mwl8k_fw_unlock(hw);
2714 }
2715
2716 static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
2717 int mc_count, struct dev_addr_list *mclist)
2718 {
2719 struct mwl8k_cmd_pkt *cmd;
2720
2721 /*
2722 * Synthesize and return a command packet that programs the
2723 * hardware multicast address filter. At this point we don't
2724 * know whether FIF_ALLMULTI is being requested, but if it is,
2725 * we'll end up throwing this packet away and creating a new
2726 * one in mwl8k_configure_filter().
2727 */
2728 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
2729
2730 return (unsigned long)cmd;
2731 }
2732
2733 static void mwl8k_configure_filter(struct ieee80211_hw *hw,
2734 unsigned int changed_flags,
2735 unsigned int *total_flags,
2736 u64 multicast)
2737 {
2738 struct mwl8k_priv *priv = hw->priv;
2739 struct mwl8k_cmd_pkt *cmd;
2740
2741 /* Clear unsupported feature flags */
2742 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
2743
2744 if (mwl8k_fw_lock(hw))
2745 return;
2746
2747 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2748 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
2749 /*
2750 * Disable the BSS filter.
2751 */
2752 mwl8k_cmd_set_pre_scan(hw);
2753 } else {
2754 u8 *bssid;
2755
2756 /*
2757 * Enable the BSS filter.
2758 *
2759 * If there is an active STA interface, use that
2760 * interface's BSSID, otherwise use a dummy one
2761 * (where the OUI part needs to be nonzero for
2762 * the BSSID to be accepted by POST_SCAN).
2763 */
2764 bssid = "\x01\x00\x00\x00\x00\x00";
2765 if (priv->vif != NULL)
2766 bssid = MWL8K_VIF(priv->vif)->bssid;
2767
2768 mwl8k_cmd_set_post_scan(hw, bssid);
2769 }
2770 }
2771
2772 cmd = (void *)(unsigned long)multicast;
2773
2774 /*
2775 * If FIF_ALLMULTI is being requested, throw away the command
2776 * packet that ->prepare_multicast() built and replace it with
2777 * a command packet that enables reception of all multicast
2778 * packets.
2779 */
2780 if (*total_flags & FIF_ALLMULTI) {
2781 kfree(cmd);
2782 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
2783 }
2784
2785 if (cmd != NULL) {
2786 mwl8k_post_cmd(hw, cmd);
2787 kfree(cmd);
2788 }
2789
2790 mwl8k_fw_unlock(hw);
2791 }
2792
2793 static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2794 {
2795 return mwl8k_rts_threshold(hw, MWL8K_CMD_SET, value);
2796 }
2797
2798 static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2799 const struct ieee80211_tx_queue_params *params)
2800 {
2801 struct mwl8k_priv *priv = hw->priv;
2802 int rc;
2803
2804 rc = mwl8k_fw_lock(hw);
2805 if (!rc) {
2806 if (!priv->wmm_enabled)
2807 rc = mwl8k_set_wmm(hw, 1);
2808
2809 if (!rc)
2810 rc = mwl8k_set_edca_params(hw, queue,
2811 params->cw_min,
2812 params->cw_max,
2813 params->aifs,
2814 params->txop);
2815
2816 mwl8k_fw_unlock(hw);
2817 }
2818
2819 return rc;
2820 }
2821
2822 static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
2823 struct ieee80211_tx_queue_stats *stats)
2824 {
2825 struct mwl8k_priv *priv = hw->priv;
2826 struct mwl8k_tx_queue *txq;
2827 int index;
2828
2829 spin_lock_bh(&priv->tx_lock);
2830 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
2831 txq = priv->txq + index;
2832 memcpy(&stats[index], &txq->tx_stats,
2833 sizeof(struct ieee80211_tx_queue_stats));
2834 }
2835 spin_unlock_bh(&priv->tx_lock);
2836
2837 return 0;
2838 }
2839
2840 static int mwl8k_get_stats(struct ieee80211_hw *hw,
2841 struct ieee80211_low_level_stats *stats)
2842 {
2843 return mwl8k_cmd_802_11_get_stat(hw, stats);
2844 }
2845
2846 static const struct ieee80211_ops mwl8k_ops = {
2847 .tx = mwl8k_tx,
2848 .start = mwl8k_start,
2849 .stop = mwl8k_stop,
2850 .add_interface = mwl8k_add_interface,
2851 .remove_interface = mwl8k_remove_interface,
2852 .config = mwl8k_config,
2853 .bss_info_changed = mwl8k_bss_info_changed,
2854 .prepare_multicast = mwl8k_prepare_multicast,
2855 .configure_filter = mwl8k_configure_filter,
2856 .set_rts_threshold = mwl8k_set_rts_threshold,
2857 .conf_tx = mwl8k_conf_tx,
2858 .get_tx_stats = mwl8k_get_tx_stats,
2859 .get_stats = mwl8k_get_stats,
2860 };
2861
2862 static void mwl8k_tx_reclaim_handler(unsigned long data)
2863 {
2864 int i;
2865 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
2866 struct mwl8k_priv *priv = hw->priv;
2867
2868 spin_lock_bh(&priv->tx_lock);
2869 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2870 mwl8k_txq_reclaim(hw, i, 0);
2871
2872 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
2873 complete(priv->tx_wait);
2874 priv->tx_wait = NULL;
2875 }
2876 spin_unlock_bh(&priv->tx_lock);
2877 }
2878
2879 static void mwl8k_finalize_join_worker(struct work_struct *work)
2880 {
2881 struct mwl8k_priv *priv =
2882 container_of(work, struct mwl8k_priv, finalize_join_worker);
2883 struct sk_buff *skb = priv->beacon_skb;
2884 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
2885
2886 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
2887 dev_kfree_skb(skb);
2888
2889 priv->beacon_skb = NULL;
2890 }
2891
2892 static int __devinit mwl8k_probe(struct pci_dev *pdev,
2893 const struct pci_device_id *id)
2894 {
2895 static int printed_version = 0;
2896 struct ieee80211_hw *hw;
2897 struct mwl8k_priv *priv;
2898 int rc;
2899 int i;
2900
2901 if (!printed_version) {
2902 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
2903 printed_version = 1;
2904 }
2905
2906 rc = pci_enable_device(pdev);
2907 if (rc) {
2908 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
2909 MWL8K_NAME);
2910 return rc;
2911 }
2912
2913 rc = pci_request_regions(pdev, MWL8K_NAME);
2914 if (rc) {
2915 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
2916 MWL8K_NAME);
2917 return rc;
2918 }
2919
2920 pci_set_master(pdev);
2921
2922 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
2923 if (hw == NULL) {
2924 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
2925 rc = -ENOMEM;
2926 goto err_free_reg;
2927 }
2928
2929 priv = hw->priv;
2930 priv->hw = hw;
2931 priv->pdev = pdev;
2932 priv->wmm_enabled = false;
2933 priv->pending_tx_pkts = 0;
2934
2935 SET_IEEE80211_DEV(hw, &pdev->dev);
2936 pci_set_drvdata(pdev, hw);
2937
2938 priv->regs = pci_iomap(pdev, 1, 0x10000);
2939 if (priv->regs == NULL) {
2940 printk(KERN_ERR "%s: Cannot map device memory\n",
2941 wiphy_name(hw->wiphy));
2942 goto err_iounmap;
2943 }
2944
2945 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
2946 priv->band.band = IEEE80211_BAND_2GHZ;
2947 priv->band.channels = priv->channels;
2948 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
2949 priv->band.bitrates = priv->rates;
2950 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
2951 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
2952
2953 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
2954 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
2955
2956 /*
2957 * Extra headroom is the size of the required DMA header
2958 * minus the size of the smallest 802.11 frame (CTS frame).
2959 */
2960 hw->extra_tx_headroom =
2961 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
2962
2963 hw->channel_change_time = 10;
2964
2965 hw->queues = MWL8K_TX_QUEUES;
2966
2967 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
2968
2969 /* Set rssi and noise values to dBm */
2970 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
2971 hw->vif_data_size = sizeof(struct mwl8k_vif);
2972 priv->vif = NULL;
2973
2974 /* Set default radio state and preamble */
2975 priv->radio_on = 0;
2976 priv->radio_short_preamble = 0;
2977
2978 /* Finalize join worker */
2979 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
2980
2981 /* TX reclaim tasklet */
2982 tasklet_init(&priv->tx_reclaim_task,
2983 mwl8k_tx_reclaim_handler, (unsigned long)hw);
2984 tasklet_disable(&priv->tx_reclaim_task);
2985
2986 /* Power management cookie */
2987 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
2988 if (priv->cookie == NULL)
2989 goto err_iounmap;
2990
2991 rc = mwl8k_rxq_init(hw, 0);
2992 if (rc)
2993 goto err_iounmap;
2994 rxq_refill(hw, 0, INT_MAX);
2995
2996 mutex_init(&priv->fw_mutex);
2997 priv->fw_mutex_owner = NULL;
2998 priv->fw_mutex_depth = 0;
2999 priv->hostcmd_wait = NULL;
3000
3001 spin_lock_init(&priv->tx_lock);
3002
3003 priv->tx_wait = NULL;
3004
3005 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3006 rc = mwl8k_txq_init(hw, i);
3007 if (rc)
3008 goto err_free_queues;
3009 }
3010
3011 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3012 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3013 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3014 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3015
3016 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
3017 IRQF_SHARED, MWL8K_NAME, hw);
3018 if (rc) {
3019 printk(KERN_ERR "%s: failed to register IRQ handler\n",
3020 wiphy_name(hw->wiphy));
3021 goto err_free_queues;
3022 }
3023
3024 /* Reset firmware and hardware */
3025 mwl8k_hw_reset(priv);
3026
3027 /* Ask userland hotplug daemon for the device firmware */
3028 rc = mwl8k_request_firmware(priv, (u32)id->driver_data);
3029 if (rc) {
3030 printk(KERN_ERR "%s: Firmware files not found\n",
3031 wiphy_name(hw->wiphy));
3032 goto err_free_irq;
3033 }
3034
3035 /* Load firmware into hardware */
3036 rc = mwl8k_load_firmware(hw);
3037 if (rc) {
3038 printk(KERN_ERR "%s: Cannot start firmware\n",
3039 wiphy_name(hw->wiphy));
3040 goto err_stop_firmware;
3041 }
3042
3043 /* Reclaim memory once firmware is successfully loaded */
3044 mwl8k_release_firmware(priv);
3045
3046 /*
3047 * Temporarily enable interrupts. Initial firmware host
3048 * commands use interrupts and avoids polling. Disable
3049 * interrupts when done.
3050 */
3051 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3052
3053 /* Get config data, mac addrs etc */
3054 rc = mwl8k_cmd_get_hw_spec(hw);
3055 if (rc) {
3056 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3057 wiphy_name(hw->wiphy));
3058 goto err_stop_firmware;
3059 }
3060
3061 /* Turn radio off */
3062 rc = mwl8k_cmd_802_11_radio_disable(hw);
3063 if (rc) {
3064 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
3065 goto err_stop_firmware;
3066 }
3067
3068 /* Clear MAC address */
3069 rc = mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
3070 if (rc) {
3071 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3072 wiphy_name(hw->wiphy));
3073 goto err_stop_firmware;
3074 }
3075
3076 /* Disable interrupts */
3077 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3078 free_irq(priv->pdev->irq, hw);
3079
3080 rc = ieee80211_register_hw(hw);
3081 if (rc) {
3082 printk(KERN_ERR "%s: Cannot register device\n",
3083 wiphy_name(hw->wiphy));
3084 goto err_stop_firmware;
3085 }
3086
3087 printk(KERN_INFO "%s: 88w%u v%d, %pM, firmware version %u.%u.%u.%u\n",
3088 wiphy_name(hw->wiphy), priv->part_num, priv->hw_rev,
3089 hw->wiphy->perm_addr,
3090 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3091 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
3092
3093 return 0;
3094
3095 err_stop_firmware:
3096 mwl8k_hw_reset(priv);
3097 mwl8k_release_firmware(priv);
3098
3099 err_free_irq:
3100 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3101 free_irq(priv->pdev->irq, hw);
3102
3103 err_free_queues:
3104 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3105 mwl8k_txq_deinit(hw, i);
3106 mwl8k_rxq_deinit(hw, 0);
3107
3108 err_iounmap:
3109 if (priv->cookie != NULL)
3110 pci_free_consistent(priv->pdev, 4,
3111 priv->cookie, priv->cookie_dma);
3112
3113 if (priv->regs != NULL)
3114 pci_iounmap(pdev, priv->regs);
3115
3116 pci_set_drvdata(pdev, NULL);
3117 ieee80211_free_hw(hw);
3118
3119 err_free_reg:
3120 pci_release_regions(pdev);
3121 pci_disable_device(pdev);
3122
3123 return rc;
3124 }
3125
3126 static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
3127 {
3128 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3129 }
3130
3131 static void __devexit mwl8k_remove(struct pci_dev *pdev)
3132 {
3133 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3134 struct mwl8k_priv *priv;
3135 int i;
3136
3137 if (hw == NULL)
3138 return;
3139 priv = hw->priv;
3140
3141 ieee80211_stop_queues(hw);
3142
3143 ieee80211_unregister_hw(hw);
3144
3145 /* Remove tx reclaim tasklet */
3146 tasklet_kill(&priv->tx_reclaim_task);
3147
3148 /* Stop hardware */
3149 mwl8k_hw_reset(priv);
3150
3151 /* Return all skbs to mac80211 */
3152 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3153 mwl8k_txq_reclaim(hw, i, 1);
3154
3155 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3156 mwl8k_txq_deinit(hw, i);
3157
3158 mwl8k_rxq_deinit(hw, 0);
3159
3160 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
3161
3162 pci_iounmap(pdev, priv->regs);
3163 pci_set_drvdata(pdev, NULL);
3164 ieee80211_free_hw(hw);
3165 pci_release_regions(pdev);
3166 pci_disable_device(pdev);
3167 }
3168
3169 static struct pci_driver mwl8k_driver = {
3170 .name = MWL8K_NAME,
3171 .id_table = mwl8k_table,
3172 .probe = mwl8k_probe,
3173 .remove = __devexit_p(mwl8k_remove),
3174 .shutdown = __devexit_p(mwl8k_shutdown),
3175 };
3176
3177 static int __init mwl8k_init(void)
3178 {
3179 return pci_register_driver(&mwl8k_driver);
3180 }
3181
3182 static void __exit mwl8k_exit(void)
3183 {
3184 pci_unregister_driver(&mwl8k_driver);
3185 }
3186
3187 module_init(mwl8k_init);
3188 module_exit(mwl8k_exit);
3189
3190 MODULE_DESCRIPTION(MWL8K_DESC);
3191 MODULE_VERSION(MWL8K_VERSION);
3192 MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3193 MODULE_LICENSE("GPL");
AMDTP streaming driver for the Linux FireWire stack (Juju)