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IB/mthca: max_inline_data handling tweaks
[firewire-audio.git] / drivers / infiniband / hw / mthca / mthca_qp.c
blobfd60cf3a5ba374b32b3db6ca05f2e015b15ccba0
1 /*
2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Cisco Systems. All rights reserved.
4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 *
35 * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
36 */
37
38 #include <linux/init.h>
39 #include <linux/string.h>
40 #include <linux/slab.h>
41
42 #include <rdma/ib_verbs.h>
43 #include <rdma/ib_cache.h>
44 #include <rdma/ib_pack.h>
45
46 #include "mthca_dev.h"
47 #include "mthca_cmd.h"
48 #include "mthca_memfree.h"
49 #include "mthca_wqe.h"
50
51 enum {
52 MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
53 MTHCA_ACK_REQ_FREQ = 10,
54 MTHCA_FLIGHT_LIMIT = 9,
55 MTHCA_UD_HEADER_SIZE = 72, /* largest UD header possible */
56 MTHCA_INLINE_HEADER_SIZE = 4, /* data segment overhead for inline */
57 MTHCA_INLINE_CHUNK_SIZE = 16 /* inline data segment chunk */
58 };
59
60 enum {
61 MTHCA_QP_STATE_RST = 0,
62 MTHCA_QP_STATE_INIT = 1,
63 MTHCA_QP_STATE_RTR = 2,
64 MTHCA_QP_STATE_RTS = 3,
65 MTHCA_QP_STATE_SQE = 4,
66 MTHCA_QP_STATE_SQD = 5,
67 MTHCA_QP_STATE_ERR = 6,
68 MTHCA_QP_STATE_DRAINING = 7
69 };
70
71 enum {
72 MTHCA_QP_ST_RC = 0x0,
73 MTHCA_QP_ST_UC = 0x1,
74 MTHCA_QP_ST_RD = 0x2,
75 MTHCA_QP_ST_UD = 0x3,
76 MTHCA_QP_ST_MLX = 0x7
77 };
78
79 enum {
80 MTHCA_QP_PM_MIGRATED = 0x3,
81 MTHCA_QP_PM_ARMED = 0x0,
82 MTHCA_QP_PM_REARM = 0x1
83 };
84
85 enum {
86 /* qp_context flags */
87 MTHCA_QP_BIT_DE = 1 << 8,
88 /* params1 */
89 MTHCA_QP_BIT_SRE = 1 << 15,
90 MTHCA_QP_BIT_SWE = 1 << 14,
91 MTHCA_QP_BIT_SAE = 1 << 13,
92 MTHCA_QP_BIT_SIC = 1 << 4,
93 MTHCA_QP_BIT_SSC = 1 << 3,
94 /* params2 */
95 MTHCA_QP_BIT_RRE = 1 << 15,
96 MTHCA_QP_BIT_RWE = 1 << 14,
97 MTHCA_QP_BIT_RAE = 1 << 13,
98 MTHCA_QP_BIT_RIC = 1 << 4,
99 MTHCA_QP_BIT_RSC = 1 << 3
100 };
101
102 struct mthca_qp_path {
103 __be32 port_pkey;
104 u8 rnr_retry;
105 u8 g_mylmc;
106 __be16 rlid;
107 u8 ackto;
108 u8 mgid_index;
109 u8 static_rate;
110 u8 hop_limit;
111 __be32 sl_tclass_flowlabel;
112 u8 rgid[16];
113 } __attribute__((packed));
114
115 struct mthca_qp_context {
116 __be32 flags;
117 __be32 tavor_sched_queue; /* Reserved on Arbel */
118 u8 mtu_msgmax;
119 u8 rq_size_stride; /* Reserved on Tavor */
120 u8 sq_size_stride; /* Reserved on Tavor */
121 u8 rlkey_arbel_sched_queue; /* Reserved on Tavor */
122 __be32 usr_page;
123 __be32 local_qpn;
124 __be32 remote_qpn;
125 u32 reserved1[2];
126 struct mthca_qp_path pri_path;
127 struct mthca_qp_path alt_path;
128 __be32 rdd;
129 __be32 pd;
130 __be32 wqe_base;
131 __be32 wqe_lkey;
132 __be32 params1;
133 __be32 reserved2;
134 __be32 next_send_psn;
135 __be32 cqn_snd;
136 __be32 snd_wqe_base_l; /* Next send WQE on Tavor */
137 __be32 snd_db_index; /* (debugging only entries) */
138 __be32 last_acked_psn;
139 __be32 ssn;
140 __be32 params2;
141 __be32 rnr_nextrecvpsn;
142 __be32 ra_buff_indx;
143 __be32 cqn_rcv;
144 __be32 rcv_wqe_base_l; /* Next recv WQE on Tavor */
145 __be32 rcv_db_index; /* (debugging only entries) */
146 __be32 qkey;
147 __be32 srqn;
148 __be32 rmsn;
149 __be16 rq_wqe_counter; /* reserved on Tavor */
150 __be16 sq_wqe_counter; /* reserved on Tavor */
151 u32 reserved3[18];
152 } __attribute__((packed));
153
154 struct mthca_qp_param {
155 __be32 opt_param_mask;
156 u32 reserved1;
157 struct mthca_qp_context context;
158 u32 reserved2[62];
159 } __attribute__((packed));
160
161 enum {
162 MTHCA_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
163 MTHCA_QP_OPTPAR_RRE = 1 << 1,
164 MTHCA_QP_OPTPAR_RAE = 1 << 2,
165 MTHCA_QP_OPTPAR_RWE = 1 << 3,
166 MTHCA_QP_OPTPAR_PKEY_INDEX = 1 << 4,
167 MTHCA_QP_OPTPAR_Q_KEY = 1 << 5,
168 MTHCA_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
169 MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
170 MTHCA_QP_OPTPAR_SRA_MAX = 1 << 8,
171 MTHCA_QP_OPTPAR_RRA_MAX = 1 << 9,
172 MTHCA_QP_OPTPAR_PM_STATE = 1 << 10,
173 MTHCA_QP_OPTPAR_PORT_NUM = 1 << 11,
174 MTHCA_QP_OPTPAR_RETRY_COUNT = 1 << 12,
175 MTHCA_QP_OPTPAR_ALT_RNR_RETRY = 1 << 13,
176 MTHCA_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
177 MTHCA_QP_OPTPAR_RNR_RETRY = 1 << 15,
178 MTHCA_QP_OPTPAR_SCHED_QUEUE = 1 << 16
179 };
180
181 static const u8 mthca_opcode[] = {
182 [IB_WR_SEND] = MTHCA_OPCODE_SEND,
183 [IB_WR_SEND_WITH_IMM] = MTHCA_OPCODE_SEND_IMM,
184 [IB_WR_RDMA_WRITE] = MTHCA_OPCODE_RDMA_WRITE,
185 [IB_WR_RDMA_WRITE_WITH_IMM] = MTHCA_OPCODE_RDMA_WRITE_IMM,
186 [IB_WR_RDMA_READ] = MTHCA_OPCODE_RDMA_READ,
187 [IB_WR_ATOMIC_CMP_AND_SWP] = MTHCA_OPCODE_ATOMIC_CS,
188 [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
189 };
190
191 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
192 {
193 return qp->qpn >= dev->qp_table.sqp_start &&
194 qp->qpn <= dev->qp_table.sqp_start + 3;
195 }
196
197 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
198 {
199 return qp->qpn >= dev->qp_table.sqp_start &&
200 qp->qpn <= dev->qp_table.sqp_start + 1;
201 }
202
203 static void *get_recv_wqe(struct mthca_qp *qp, int n)
204 {
205 if (qp->is_direct)
206 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
207 else
208 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
209 ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
210 }
211
212 static void *get_send_wqe(struct mthca_qp *qp, int n)
213 {
214 if (qp->is_direct)
215 return qp->queue.direct.buf + qp->send_wqe_offset +
216 (n << qp->sq.wqe_shift);
217 else
218 return qp->queue.page_list[(qp->send_wqe_offset +
219 (n << qp->sq.wqe_shift)) >>
220 PAGE_SHIFT].buf +
221 ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
222 (PAGE_SIZE - 1));
223 }
224
225 static void mthca_wq_init(struct mthca_wq *wq)
226 {
227 spin_lock_init(&wq->lock);
228 wq->next_ind = 0;
229 wq->last_comp = wq->max - 1;
230 wq->head = 0;
231 wq->tail = 0;
232 }
233
234 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
235 enum ib_event_type event_type)
236 {
237 struct mthca_qp *qp;
238 struct ib_event event;
239
240 spin_lock(&dev->qp_table.lock);
241 qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
242 if (qp)
243 atomic_inc(&qp->refcount);
244 spin_unlock(&dev->qp_table.lock);
245
246 if (!qp) {
247 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
248 return;
249 }
250
251 event.device = &dev->ib_dev;
252 event.event = event_type;
253 event.element.qp = &qp->ibqp;
254 if (qp->ibqp.event_handler)
255 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
256
257 if (atomic_dec_and_test(&qp->refcount))
258 wake_up(&qp->wait);
259 }
260
261 static int to_mthca_state(enum ib_qp_state ib_state)
262 {
263 switch (ib_state) {
264 case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
265 case IB_QPS_INIT: return MTHCA_QP_STATE_INIT;
266 case IB_QPS_RTR: return MTHCA_QP_STATE_RTR;
267 case IB_QPS_RTS: return MTHCA_QP_STATE_RTS;
268 case IB_QPS_SQD: return MTHCA_QP_STATE_SQD;
269 case IB_QPS_SQE: return MTHCA_QP_STATE_SQE;
270 case IB_QPS_ERR: return MTHCA_QP_STATE_ERR;
271 default: return -1;
272 }
273 }
274
275 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
276
277 static int to_mthca_st(int transport)
278 {
279 switch (transport) {
280 case RC: return MTHCA_QP_ST_RC;
281 case UC: return MTHCA_QP_ST_UC;
282 case UD: return MTHCA_QP_ST_UD;
283 case RD: return MTHCA_QP_ST_RD;
284 case MLX: return MTHCA_QP_ST_MLX;
285 default: return -1;
286 }
287 }
288
289 static const struct {
290 int trans;
291 u32 req_param[NUM_TRANS];
292 u32 opt_param[NUM_TRANS];
293 } state_table[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = {
294 [IB_QPS_RESET] = {
295 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
296 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
297 [IB_QPS_INIT] = {
298 .trans = MTHCA_TRANS_RST2INIT,
299 .req_param = {
300 [UD] = (IB_QP_PKEY_INDEX |
301 IB_QP_PORT |
302 IB_QP_QKEY),
303 [UC] = (IB_QP_PKEY_INDEX |
304 IB_QP_PORT |
305 IB_QP_ACCESS_FLAGS),
306 [RC] = (IB_QP_PKEY_INDEX |
307 IB_QP_PORT |
308 IB_QP_ACCESS_FLAGS),
309 [MLX] = (IB_QP_PKEY_INDEX |
310 IB_QP_QKEY),
311 },
312 /* bug-for-bug compatibility with VAPI: */
313 .opt_param = {
314 [MLX] = IB_QP_PORT
315 }
316 },
317 },
318 [IB_QPS_INIT] = {
319 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
320 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
321 [IB_QPS_INIT] = {
322 .trans = MTHCA_TRANS_INIT2INIT,
323 .opt_param = {
324 [UD] = (IB_QP_PKEY_INDEX |
325 IB_QP_PORT |
326 IB_QP_QKEY),
327 [UC] = (IB_QP_PKEY_INDEX |
328 IB_QP_PORT |
329 IB_QP_ACCESS_FLAGS),
330 [RC] = (IB_QP_PKEY_INDEX |
331 IB_QP_PORT |
332 IB_QP_ACCESS_FLAGS),
333 [MLX] = (IB_QP_PKEY_INDEX |
334 IB_QP_QKEY),
335 }
336 },
337 [IB_QPS_RTR] = {
338 .trans = MTHCA_TRANS_INIT2RTR,
339 .req_param = {
340 [UC] = (IB_QP_AV |
341 IB_QP_PATH_MTU |
342 IB_QP_DEST_QPN |
343 IB_QP_RQ_PSN),
344 [RC] = (IB_QP_AV |
345 IB_QP_PATH_MTU |
346 IB_QP_DEST_QPN |
347 IB_QP_RQ_PSN |
348 IB_QP_MAX_DEST_RD_ATOMIC |
349 IB_QP_MIN_RNR_TIMER),
350 },
351 .opt_param = {
352 [UD] = (IB_QP_PKEY_INDEX |
353 IB_QP_QKEY),
354 [UC] = (IB_QP_ALT_PATH |
355 IB_QP_ACCESS_FLAGS |
356 IB_QP_PKEY_INDEX),
357 [RC] = (IB_QP_ALT_PATH |
358 IB_QP_ACCESS_FLAGS |
359 IB_QP_PKEY_INDEX),
360 [MLX] = (IB_QP_PKEY_INDEX |
361 IB_QP_QKEY),
362 }
363 }
364 },
365 [IB_QPS_RTR] = {
366 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
367 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
368 [IB_QPS_RTS] = {
369 .trans = MTHCA_TRANS_RTR2RTS,
370 .req_param = {
371 [UD] = IB_QP_SQ_PSN,
372 [UC] = IB_QP_SQ_PSN,
373 [RC] = (IB_QP_TIMEOUT |
374 IB_QP_RETRY_CNT |
375 IB_QP_RNR_RETRY |
376 IB_QP_SQ_PSN |
377 IB_QP_MAX_QP_RD_ATOMIC),
378 [MLX] = IB_QP_SQ_PSN,
379 },
380 .opt_param = {
381 [UD] = (IB_QP_CUR_STATE |
382 IB_QP_QKEY),
383 [UC] = (IB_QP_CUR_STATE |
384 IB_QP_ALT_PATH |
385 IB_QP_ACCESS_FLAGS |
386 IB_QP_PKEY_INDEX |
387 IB_QP_PATH_MIG_STATE),
388 [RC] = (IB_QP_CUR_STATE |
389 IB_QP_ALT_PATH |
390 IB_QP_ACCESS_FLAGS |
391 IB_QP_PKEY_INDEX |
392 IB_QP_MIN_RNR_TIMER |
393 IB_QP_PATH_MIG_STATE),
394 [MLX] = (IB_QP_CUR_STATE |
395 IB_QP_QKEY),
396 }
397 }
398 },
399 [IB_QPS_RTS] = {
400 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
401 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
402 [IB_QPS_RTS] = {
403 .trans = MTHCA_TRANS_RTS2RTS,
404 .opt_param = {
405 [UD] = (IB_QP_CUR_STATE |
406 IB_QP_QKEY),
407 [UC] = (IB_QP_ACCESS_FLAGS |
408 IB_QP_ALT_PATH |
409 IB_QP_PATH_MIG_STATE),
410 [RC] = (IB_QP_ACCESS_FLAGS |
411 IB_QP_ALT_PATH |
412 IB_QP_PATH_MIG_STATE |
413 IB_QP_MIN_RNR_TIMER),
414 [MLX] = (IB_QP_CUR_STATE |
415 IB_QP_QKEY),
416 }
417 },
418 [IB_QPS_SQD] = {
419 .trans = MTHCA_TRANS_RTS2SQD,
420 },
421 },
422 [IB_QPS_SQD] = {
423 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
424 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
425 [IB_QPS_RTS] = {
426 .trans = MTHCA_TRANS_SQD2RTS,
427 .opt_param = {
428 [UD] = (IB_QP_CUR_STATE |
429 IB_QP_QKEY),
430 [UC] = (IB_QP_CUR_STATE |
431 IB_QP_ALT_PATH |
432 IB_QP_ACCESS_FLAGS |
433 IB_QP_PATH_MIG_STATE),
434 [RC] = (IB_QP_CUR_STATE |
435 IB_QP_ALT_PATH |
436 IB_QP_ACCESS_FLAGS |
437 IB_QP_MIN_RNR_TIMER |
438 IB_QP_PATH_MIG_STATE),
439 [MLX] = (IB_QP_CUR_STATE |
440 IB_QP_QKEY),
441 }
442 },
443 [IB_QPS_SQD] = {
444 .trans = MTHCA_TRANS_SQD2SQD,
445 .opt_param = {
446 [UD] = (IB_QP_PKEY_INDEX |
447 IB_QP_QKEY),
448 [UC] = (IB_QP_AV |
449 IB_QP_CUR_STATE |
450 IB_QP_ALT_PATH |
451 IB_QP_ACCESS_FLAGS |
452 IB_QP_PKEY_INDEX |
453 IB_QP_PATH_MIG_STATE),
454 [RC] = (IB_QP_AV |
455 IB_QP_TIMEOUT |
456 IB_QP_RETRY_CNT |
457 IB_QP_RNR_RETRY |
458 IB_QP_MAX_QP_RD_ATOMIC |
459 IB_QP_MAX_DEST_RD_ATOMIC |
460 IB_QP_CUR_STATE |
461 IB_QP_ALT_PATH |
462 IB_QP_ACCESS_FLAGS |
463 IB_QP_PKEY_INDEX |
464 IB_QP_MIN_RNR_TIMER |
465 IB_QP_PATH_MIG_STATE),
466 [MLX] = (IB_QP_PKEY_INDEX |
467 IB_QP_QKEY),
468 }
469 }
470 },
471 [IB_QPS_SQE] = {
472 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
473 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
474 [IB_QPS_RTS] = {
475 .trans = MTHCA_TRANS_SQERR2RTS,
476 .opt_param = {
477 [UD] = (IB_QP_CUR_STATE |
478 IB_QP_QKEY),
479 [UC] = IB_QP_CUR_STATE,
480 [RC] = (IB_QP_CUR_STATE |
481 IB_QP_MIN_RNR_TIMER),
482 [MLX] = (IB_QP_CUR_STATE |
483 IB_QP_QKEY),
484 }
485 }
486 },
487 [IB_QPS_ERR] = {
488 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
489 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR }
490 }
491 };
492
493 static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
494 int attr_mask)
495 {
496 if (attr_mask & IB_QP_PKEY_INDEX)
497 sqp->pkey_index = attr->pkey_index;
498 if (attr_mask & IB_QP_QKEY)
499 sqp->qkey = attr->qkey;
500 if (attr_mask & IB_QP_SQ_PSN)
501 sqp->send_psn = attr->sq_psn;
502 }
503
504 static void init_port(struct mthca_dev *dev, int port)
505 {
506 int err;
507 u8 status;
508 struct mthca_init_ib_param param;
509
510 memset(&param, 0, sizeof param);
511
512 param.port_width = dev->limits.port_width_cap;
513 param.vl_cap = dev->limits.vl_cap;
514 param.mtu_cap = dev->limits.mtu_cap;
515 param.gid_cap = dev->limits.gid_table_len;
516 param.pkey_cap = dev->limits.pkey_table_len;
517
518 err = mthca_INIT_IB(dev, &param, port, &status);
519 if (err)
520 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
521 if (status)
522 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
523 }
524
525 static __be32 get_hw_access_flags(struct mthca_qp *qp, struct ib_qp_attr *attr,
526 int attr_mask)
527 {
528 u8 dest_rd_atomic;
529 u32 access_flags;
530 u32 hw_access_flags = 0;
531
532 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
533 dest_rd_atomic = attr->max_dest_rd_atomic;
534 else
535 dest_rd_atomic = qp->resp_depth;
536
537 if (attr_mask & IB_QP_ACCESS_FLAGS)
538 access_flags = attr->qp_access_flags;
539 else
540 access_flags = qp->atomic_rd_en;
541
542 if (!dest_rd_atomic)
543 access_flags &= IB_ACCESS_REMOTE_WRITE;
544
545 if (access_flags & IB_ACCESS_REMOTE_READ)
546 hw_access_flags |= MTHCA_QP_BIT_RRE;
547 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
548 hw_access_flags |= MTHCA_QP_BIT_RAE;
549 if (access_flags & IB_ACCESS_REMOTE_WRITE)
550 hw_access_flags |= MTHCA_QP_BIT_RWE;
551
552 return cpu_to_be32(hw_access_flags);
553 }
554
555 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
556 {
557 struct mthca_dev *dev = to_mdev(ibqp->device);
558 struct mthca_qp *qp = to_mqp(ibqp);
559 enum ib_qp_state cur_state, new_state;
560 struct mthca_mailbox *mailbox;
561 struct mthca_qp_param *qp_param;
562 struct mthca_qp_context *qp_context;
563 u32 req_param, opt_param;
564 u8 status;
565 int err;
566
567 if (attr_mask & IB_QP_CUR_STATE) {
568 if (attr->cur_qp_state != IB_QPS_RTR &&
569 attr->cur_qp_state != IB_QPS_RTS &&
570 attr->cur_qp_state != IB_QPS_SQD &&
571 attr->cur_qp_state != IB_QPS_SQE)
572 return -EINVAL;
573 else
574 cur_state = attr->cur_qp_state;
575 } else {
576 spin_lock_irq(&qp->sq.lock);
577 spin_lock(&qp->rq.lock);
578 cur_state = qp->state;
579 spin_unlock(&qp->rq.lock);
580 spin_unlock_irq(&qp->sq.lock);
581 }
582
583 if (attr_mask & IB_QP_STATE) {
584 if (attr->qp_state < 0 || attr->qp_state > IB_QPS_ERR)
585 return -EINVAL;
586 new_state = attr->qp_state;
587 } else
588 new_state = cur_state;
589
590 if (state_table[cur_state][new_state].trans == MTHCA_TRANS_INVALID) {
591 mthca_dbg(dev, "Illegal QP transition "
592 "%d->%d\n", cur_state, new_state);
593 return -EINVAL;
594 }
595
596 req_param = state_table[cur_state][new_state].req_param[qp->transport];
597 opt_param = state_table[cur_state][new_state].opt_param[qp->transport];
598
599 if ((req_param & attr_mask) != req_param) {
600 mthca_dbg(dev, "QP transition "
601 "%d->%d missing req attr 0x%08x\n",
602 cur_state, new_state,
603 req_param & ~attr_mask);
604 return -EINVAL;
605 }
606
607 if (attr_mask & ~(req_param | opt_param | IB_QP_STATE)) {
608 mthca_dbg(dev, "QP transition (transport %d) "
609 "%d->%d has extra attr 0x%08x\n",
610 qp->transport,
611 cur_state, new_state,
612 attr_mask & ~(req_param | opt_param |
613 IB_QP_STATE));
614 return -EINVAL;
615 }
616
617 if ((attr_mask & IB_QP_PKEY_INDEX) &&
618 attr->pkey_index >= dev->limits.pkey_table_len) {
619 mthca_dbg(dev, "PKey index (%u) too large. max is %d\n",
620 attr->pkey_index,dev->limits.pkey_table_len-1);
621 return -EINVAL;
622 }
623
624 if ((attr_mask & IB_QP_PORT) &&
625 (attr->port_num == 0 || attr->port_num > dev->limits.num_ports)) {
626 mthca_dbg(dev, "Port number (%u) is invalid\n", attr->port_num);
627 return -EINVAL;
628 }
629
630 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
631 attr->max_rd_atomic > dev->limits.max_qp_init_rdma) {
632 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n",
633 attr->max_rd_atomic, dev->limits.max_qp_init_rdma);
634 return -EINVAL;
635 }
636
637 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
638 attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) {
639 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n",
640 attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift);
641 return -EINVAL;
642 }
643
644 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
645 if (IS_ERR(mailbox))
646 return PTR_ERR(mailbox);
647 qp_param = mailbox->buf;
648 qp_context = &qp_param->context;
649 memset(qp_param, 0, sizeof *qp_param);
650
651 qp_context->flags = cpu_to_be32((to_mthca_state(new_state) << 28) |
652 (to_mthca_st(qp->transport) << 16));
653 qp_context->flags |= cpu_to_be32(MTHCA_QP_BIT_DE);
654 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
655 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
656 else {
657 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
658 switch (attr->path_mig_state) {
659 case IB_MIG_MIGRATED:
660 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
661 break;
662 case IB_MIG_REARM:
663 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
664 break;
665 case IB_MIG_ARMED:
666 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
667 break;
668 }
669 }
670
671 /* leave tavor_sched_queue as 0 */
672
673 if (qp->transport == MLX || qp->transport == UD)
674 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
675 else if (attr_mask & IB_QP_PATH_MTU)
676 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
677
678 if (mthca_is_memfree(dev)) {
679 if (qp->rq.max)
680 qp_context->rq_size_stride = long_log2(qp->rq.max) << 3;
681 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
682
683 if (qp->sq.max)
684 qp_context->sq_size_stride = long_log2(qp->sq.max) << 3;
685 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
686 }
687
688 /* leave arbel_sched_queue as 0 */
689
690 if (qp->ibqp.uobject)
691 qp_context->usr_page =
692 cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
693 else
694 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
695 qp_context->local_qpn = cpu_to_be32(qp->qpn);
696 if (attr_mask & IB_QP_DEST_QPN) {
697 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
698 }
699
700 if (qp->transport == MLX)
701 qp_context->pri_path.port_pkey |=
702 cpu_to_be32(to_msqp(qp)->port << 24);
703 else {
704 if (attr_mask & IB_QP_PORT) {
705 qp_context->pri_path.port_pkey |=
706 cpu_to_be32(attr->port_num << 24);
707 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
708 }
709 }
710
711 if (attr_mask & IB_QP_PKEY_INDEX) {
712 qp_context->pri_path.port_pkey |=
713 cpu_to_be32(attr->pkey_index);
714 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
715 }
716
717 if (attr_mask & IB_QP_RNR_RETRY) {
718 qp_context->pri_path.rnr_retry = attr->rnr_retry << 5;
719 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY);
720 }
721
722 if (attr_mask & IB_QP_AV) {
723 qp_context->pri_path.g_mylmc = attr->ah_attr.src_path_bits & 0x7f;
724 qp_context->pri_path.rlid = cpu_to_be16(attr->ah_attr.dlid);
725 qp_context->pri_path.static_rate = !!attr->ah_attr.static_rate;
726 if (attr->ah_attr.ah_flags & IB_AH_GRH) {
727 qp_context->pri_path.g_mylmc |= 1 << 7;
728 qp_context->pri_path.mgid_index = attr->ah_attr.grh.sgid_index;
729 qp_context->pri_path.hop_limit = attr->ah_attr.grh.hop_limit;
730 qp_context->pri_path.sl_tclass_flowlabel =
731 cpu_to_be32((attr->ah_attr.sl << 28) |
732 (attr->ah_attr.grh.traffic_class << 20) |
733 (attr->ah_attr.grh.flow_label));
734 memcpy(qp_context->pri_path.rgid,
735 attr->ah_attr.grh.dgid.raw, 16);
736 } else {
737 qp_context->pri_path.sl_tclass_flowlabel =
738 cpu_to_be32(attr->ah_attr.sl << 28);
739 }
740 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
741 }
742
743 if (attr_mask & IB_QP_TIMEOUT) {
744 qp_context->pri_path.ackto = attr->timeout << 3;
745 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
746 }
747
748 /* XXX alt_path */
749
750 /* leave rdd as 0 */
751 qp_context->pd = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
752 /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
753 qp_context->wqe_lkey = cpu_to_be32(qp->mr.ibmr.lkey);
754 qp_context->params1 = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
755 (MTHCA_FLIGHT_LIMIT << 24) |
756 MTHCA_QP_BIT_SWE);
757 if (qp->sq_policy == IB_SIGNAL_ALL_WR)
758 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
759 if (attr_mask & IB_QP_RETRY_CNT) {
760 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
761 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
762 }
763
764 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
765 if (attr->max_rd_atomic) {
766 qp_context->params1 |=
767 cpu_to_be32(MTHCA_QP_BIT_SRE |
768 MTHCA_QP_BIT_SAE);
769 qp_context->params1 |=
770 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
771 }
772 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
773 }
774
775 if (attr_mask & IB_QP_SQ_PSN)
776 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
777 qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
778
779 if (mthca_is_memfree(dev)) {
780 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
781 qp_context->snd_db_index = cpu_to_be32(qp->sq.db_index);
782 }
783
784 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
785 if (attr->max_dest_rd_atomic)
786 qp_context->params2 |=
787 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
788
789 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
790 }
791
792 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
793 qp_context->params2 |= get_hw_access_flags(qp, attr, attr_mask);
794 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
795 MTHCA_QP_OPTPAR_RRE |
796 MTHCA_QP_OPTPAR_RAE);
797 }
798
799 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
800
801 if (ibqp->srq)
802 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
803
804 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
805 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
806 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
807 }
808 if (attr_mask & IB_QP_RQ_PSN)
809 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
810
811 qp_context->ra_buff_indx =
812 cpu_to_be32(dev->qp_table.rdb_base +
813 ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
814 dev->qp_table.rdb_shift));
815
816 qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
817
818 if (mthca_is_memfree(dev))
819 qp_context->rcv_db_index = cpu_to_be32(qp->rq.db_index);
820
821 if (attr_mask & IB_QP_QKEY) {
822 qp_context->qkey = cpu_to_be32(attr->qkey);
823 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
824 }
825
826 if (ibqp->srq)
827 qp_context->srqn = cpu_to_be32(1 << 24 |
828 to_msrq(ibqp->srq)->srqn);
829
830 err = mthca_MODIFY_QP(dev, state_table[cur_state][new_state].trans,
831 qp->qpn, 0, mailbox, 0, &status);
832 if (status) {
833 mthca_warn(dev, "modify QP %d returned status %02x.\n",
834 state_table[cur_state][new_state].trans, status);
835 err = -EINVAL;
836 }
837
838 if (!err) {
839 qp->state = new_state;
840 if (attr_mask & IB_QP_ACCESS_FLAGS)
841 qp->atomic_rd_en = attr->qp_access_flags;
842 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
843 qp->resp_depth = attr->max_dest_rd_atomic;
844 }
845
846 mthca_free_mailbox(dev, mailbox);
847
848 if (is_sqp(dev, qp))
849 store_attrs(to_msqp(qp), attr, attr_mask);
850
851 /*
852 * If we moved QP0 to RTR, bring the IB link up; if we moved
853 * QP0 to RESET or ERROR, bring the link back down.
854 */
855 if (is_qp0(dev, qp)) {
856 if (cur_state != IB_QPS_RTR &&
857 new_state == IB_QPS_RTR)
858 init_port(dev, to_msqp(qp)->port);
859
860 if (cur_state != IB_QPS_RESET &&
861 cur_state != IB_QPS_ERR &&
862 (new_state == IB_QPS_RESET ||
863 new_state == IB_QPS_ERR))
864 mthca_CLOSE_IB(dev, to_msqp(qp)->port, &status);
865 }
866
867 /*
868 * If we moved a kernel QP to RESET, clean up all old CQ
869 * entries and reinitialize the QP.
870 */
871 if (!err && new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
872 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn,
873 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
874 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
875 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn,
876 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
877
878 mthca_wq_init(&qp->sq);
879 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
880
881 mthca_wq_init(&qp->rq);
882 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
883
884 if (mthca_is_memfree(dev)) {
885 *qp->sq.db = 0;
886 *qp->rq.db = 0;
887 }
888 }
889
890 return err;
891 }
892
893 static int mthca_max_data_size(struct mthca_dev *dev, struct mthca_qp *qp, int desc_sz)
894 {
895 /*
896 * Calculate the maximum size of WQE s/g segments, excluding
897 * the next segment and other non-data segments.
898 */
899 int max_data_size = desc_sz - sizeof (struct mthca_next_seg);
900
901 switch (qp->transport) {
902 case MLX:
903 max_data_size -= 2 * sizeof (struct mthca_data_seg);
904 break;
905
906 case UD:
907 if (mthca_is_memfree(dev))
908 max_data_size -= sizeof (struct mthca_arbel_ud_seg);
909 else
910 max_data_size -= sizeof (struct mthca_tavor_ud_seg);
911 break;
912
913 default:
914 max_data_size -= sizeof (struct mthca_raddr_seg);
915 break;
916 }
917
918 return max_data_size;
919 }
920
921 static inline int mthca_max_inline_data(struct mthca_pd *pd, int max_data_size)
922 {
923 /* We don't support inline data for kernel QPs (yet). */
924 return pd->ibpd.uobject ? max_data_size - MTHCA_INLINE_HEADER_SIZE : 0;
925 }
926
927 static void mthca_adjust_qp_caps(struct mthca_dev *dev,
928 struct mthca_pd *pd,
929 struct mthca_qp *qp)
930 {
931 int max_data_size = mthca_max_data_size(dev, qp,
932 min(dev->limits.max_desc_sz,
933 1 << qp->sq.wqe_shift));
934
935 qp->max_inline_data = mthca_max_inline_data(pd, max_data_size);
936
937 qp->sq.max_gs = min_t(int, dev->limits.max_sg,
938 max_data_size / sizeof (struct mthca_data_seg));
939 qp->rq.max_gs = min_t(int, dev->limits.max_sg,
940 (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
941 sizeof (struct mthca_next_seg)) /
942 sizeof (struct mthca_data_seg));
943 }
944
945 /*
946 * Allocate and register buffer for WQEs. qp->rq.max, sq.max,
947 * rq.max_gs and sq.max_gs must all be assigned.
948 * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
949 * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
950 * queue)
951 */
952 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
953 struct mthca_pd *pd,
954 struct mthca_qp *qp)
955 {
956 int size;
957 int err = -ENOMEM;
958
959 size = sizeof (struct mthca_next_seg) +
960 qp->rq.max_gs * sizeof (struct mthca_data_seg);
961
962 if (size > dev->limits.max_desc_sz)
963 return -EINVAL;
964
965 for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
966 qp->rq.wqe_shift++)
967 ; /* nothing */
968
969 size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
970 switch (qp->transport) {
971 case MLX:
972 size += 2 * sizeof (struct mthca_data_seg);
973 break;
974
975 case UD:
976 size += mthca_is_memfree(dev) ?
977 sizeof (struct mthca_arbel_ud_seg) :
978 sizeof (struct mthca_tavor_ud_seg);
979 break;
980
981 case UC:
982 size += sizeof (struct mthca_raddr_seg);
983 break;
984
985 case RC:
986 size += sizeof (struct mthca_raddr_seg);
987 /*
988 * An atomic op will require an atomic segment, a
989 * remote address segment and one scatter entry.
990 */
991 size = max_t(int, size,
992 sizeof (struct mthca_atomic_seg) +
993 sizeof (struct mthca_raddr_seg) +
994 sizeof (struct mthca_data_seg));
995 break;
996
997 default:
998 break;
999 }
1000
1001 /* Make sure that we have enough space for a bind request */
1002 size = max_t(int, size, sizeof (struct mthca_bind_seg));
1003
1004 size += sizeof (struct mthca_next_seg);
1005
1006 if (size > dev->limits.max_desc_sz)
1007 return -EINVAL;
1008
1009 for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
1010 qp->sq.wqe_shift++)
1011 ; /* nothing */
1012
1013 qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
1014 1 << qp->sq.wqe_shift);
1015
1016 /*
1017 * If this is a userspace QP, we don't actually have to
1018 * allocate anything. All we need is to calculate the WQE
1019 * sizes and the send_wqe_offset, so we're done now.
1020 */
1021 if (pd->ibpd.uobject)
1022 return 0;
1023
1024 size = PAGE_ALIGN(qp->send_wqe_offset +
1025 (qp->sq.max << qp->sq.wqe_shift));
1026
1027 qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
1028 GFP_KERNEL);
1029 if (!qp->wrid)
1030 goto err_out;
1031
1032 err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
1033 &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
1034 if (err)
1035 goto err_out;
1036
1037 return 0;
1038
1039 err_out:
1040 kfree(qp->wrid);
1041 return err;
1042 }
1043
1044 static void mthca_free_wqe_buf(struct mthca_dev *dev,
1045 struct mthca_qp *qp)
1046 {
1047 mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
1048 (qp->sq.max << qp->sq.wqe_shift)),
1049 &qp->queue, qp->is_direct, &qp->mr);
1050 kfree(qp->wrid);
1051 }
1052
1053 static int mthca_map_memfree(struct mthca_dev *dev,
1054 struct mthca_qp *qp)
1055 {
1056 int ret;
1057
1058 if (mthca_is_memfree(dev)) {
1059 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1060 if (ret)
1061 return ret;
1062
1063 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1064 if (ret)
1065 goto err_qpc;
1066
1067 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1068 qp->qpn << dev->qp_table.rdb_shift);
1069 if (ret)
1070 goto err_eqpc;
1071
1072 }
1073
1074 return 0;
1075
1076 err_eqpc:
1077 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1078
1079 err_qpc:
1080 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1081
1082 return ret;
1083 }
1084
1085 static void mthca_unmap_memfree(struct mthca_dev *dev,
1086 struct mthca_qp *qp)
1087 {
1088 mthca_table_put(dev, dev->qp_table.rdb_table,
1089 qp->qpn << dev->qp_table.rdb_shift);
1090 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1091 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1092 }
1093
1094 static int mthca_alloc_memfree(struct mthca_dev *dev,
1095 struct mthca_qp *qp)
1096 {
1097 int ret = 0;
1098
1099 if (mthca_is_memfree(dev)) {
1100 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1101 qp->qpn, &qp->rq.db);
1102 if (qp->rq.db_index < 0)
1103 return ret;
1104
1105 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1106 qp->qpn, &qp->sq.db);
1107 if (qp->sq.db_index < 0)
1108 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1109 }
1110
1111 return ret;
1112 }
1113
1114 static void mthca_free_memfree(struct mthca_dev *dev,
1115 struct mthca_qp *qp)
1116 {
1117 if (mthca_is_memfree(dev)) {
1118 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1119 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1120 }
1121 }
1122
1123 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1124 struct mthca_pd *pd,
1125 struct mthca_cq *send_cq,
1126 struct mthca_cq *recv_cq,
1127 enum ib_sig_type send_policy,
1128 struct mthca_qp *qp)
1129 {
1130 int ret;
1131 int i;
1132
1133 atomic_set(&qp->refcount, 1);
1134 init_waitqueue_head(&qp->wait);
1135 qp->state = IB_QPS_RESET;
1136 qp->atomic_rd_en = 0;
1137 qp->resp_depth = 0;
1138 qp->sq_policy = send_policy;
1139 mthca_wq_init(&qp->sq);
1140 mthca_wq_init(&qp->rq);
1141
1142 ret = mthca_map_memfree(dev, qp);
1143 if (ret)
1144 return ret;
1145
1146 ret = mthca_alloc_wqe_buf(dev, pd, qp);
1147 if (ret) {
1148 mthca_unmap_memfree(dev, qp);
1149 return ret;
1150 }
1151
1152 mthca_adjust_qp_caps(dev, pd, qp);
1153
1154 /*
1155 * If this is a userspace QP, we're done now. The doorbells
1156 * will be allocated and buffers will be initialized in
1157 * userspace.
1158 */
1159 if (pd->ibpd.uobject)
1160 return 0;
1161
1162 ret = mthca_alloc_memfree(dev, qp);
1163 if (ret) {
1164 mthca_free_wqe_buf(dev, qp);
1165 mthca_unmap_memfree(dev, qp);
1166 return ret;
1167 }
1168
1169 if (mthca_is_memfree(dev)) {
1170 struct mthca_next_seg *next;
1171 struct mthca_data_seg *scatter;
1172 int size = (sizeof (struct mthca_next_seg) +
1173 qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1174
1175 for (i = 0; i < qp->rq.max; ++i) {
1176 next = get_recv_wqe(qp, i);
1177 next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1178 qp->rq.wqe_shift);
1179 next->ee_nds = cpu_to_be32(size);
1180
1181 for (scatter = (void *) (next + 1);
1182 (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1183 ++scatter)
1184 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1185 }
1186
1187 for (i = 0; i < qp->sq.max; ++i) {
1188 next = get_send_wqe(qp, i);
1189 next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1190 qp->sq.wqe_shift) +
1191 qp->send_wqe_offset);
1192 }
1193 }
1194
1195 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1196 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1197
1198 return 0;
1199 }
1200
1201 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1202 struct mthca_pd *pd, struct mthca_qp *qp)
1203 {
1204 int max_data_size = mthca_max_data_size(dev, qp, dev->limits.max_desc_sz);
1205
1206 /* Sanity check QP size before proceeding */
1207 if (cap->max_send_wr > dev->limits.max_wqes ||
1208 cap->max_recv_wr > dev->limits.max_wqes ||
1209 cap->max_send_sge > dev->limits.max_sg ||
1210 cap->max_recv_sge > dev->limits.max_sg ||
1211 cap->max_inline_data > mthca_max_inline_data(pd, max_data_size))
1212 return -EINVAL;
1213
1214 /*
1215 * For MLX transport we need 2 extra S/G entries:
1216 * one for the header and one for the checksum at the end
1217 */
1218 if (qp->transport == MLX && cap->max_recv_sge + 2 > dev->limits.max_sg)
1219 return -EINVAL;
1220
1221 if (mthca_is_memfree(dev)) {
1222 qp->rq.max = cap->max_recv_wr ?
1223 roundup_pow_of_two(cap->max_recv_wr) : 0;
1224 qp->sq.max = cap->max_send_wr ?
1225 roundup_pow_of_two(cap->max_send_wr) : 0;
1226 } else {
1227 qp->rq.max = cap->max_recv_wr;
1228 qp->sq.max = cap->max_send_wr;
1229 }
1230
1231 qp->rq.max_gs = cap->max_recv_sge;
1232 qp->sq.max_gs = max_t(int, cap->max_send_sge,
1233 ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1234 MTHCA_INLINE_CHUNK_SIZE) /
1235 sizeof (struct mthca_data_seg));
1236
1237 return 0;
1238 }
1239
1240 int mthca_alloc_qp(struct mthca_dev *dev,
1241 struct mthca_pd *pd,
1242 struct mthca_cq *send_cq,
1243 struct mthca_cq *recv_cq,
1244 enum ib_qp_type type,
1245 enum ib_sig_type send_policy,
1246 struct ib_qp_cap *cap,
1247 struct mthca_qp *qp)
1248 {
1249 int err;
1250
1251 err = mthca_set_qp_size(dev, cap, pd, qp);
1252 if (err)
1253 return err;
1254
1255 switch (type) {
1256 case IB_QPT_RC: qp->transport = RC; break;
1257 case IB_QPT_UC: qp->transport = UC; break;
1258 case IB_QPT_UD: qp->transport = UD; break;
1259 default: return -EINVAL;
1260 }
1261
1262 qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1263 if (qp->qpn == -1)
1264 return -ENOMEM;
1265
1266 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1267 send_policy, qp);
1268 if (err) {
1269 mthca_free(&dev->qp_table.alloc, qp->qpn);
1270 return err;
1271 }
1272
1273 spin_lock_irq(&dev->qp_table.lock);
1274 mthca_array_set(&dev->qp_table.qp,
1275 qp->qpn & (dev->limits.num_qps - 1), qp);
1276 spin_unlock_irq(&dev->qp_table.lock);
1277
1278 return 0;
1279 }
1280
1281 int mthca_alloc_sqp(struct mthca_dev *dev,
1282 struct mthca_pd *pd,
1283 struct mthca_cq *send_cq,
1284 struct mthca_cq *recv_cq,
1285 enum ib_sig_type send_policy,
1286 struct ib_qp_cap *cap,
1287 int qpn,
1288 int port,
1289 struct mthca_sqp *sqp)
1290 {
1291 u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1292 int err;
1293
1294 err = mthca_set_qp_size(dev, cap, pd, &sqp->qp);
1295 if (err)
1296 return err;
1297
1298 sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1299 sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1300 &sqp->header_dma, GFP_KERNEL);
1301 if (!sqp->header_buf)
1302 return -ENOMEM;
1303
1304 spin_lock_irq(&dev->qp_table.lock);
1305 if (mthca_array_get(&dev->qp_table.qp, mqpn))
1306 err = -EBUSY;
1307 else
1308 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1309 spin_unlock_irq(&dev->qp_table.lock);
1310
1311 if (err)
1312 goto err_out;
1313
1314 sqp->port = port;
1315 sqp->qp.qpn = mqpn;
1316 sqp->qp.transport = MLX;
1317
1318 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1319 send_policy, &sqp->qp);
1320 if (err)
1321 goto err_out_free;
1322
1323 atomic_inc(&pd->sqp_count);
1324
1325 return 0;
1326
1327 err_out_free:
1328 /*
1329 * Lock CQs here, so that CQ polling code can do QP lookup
1330 * without taking a lock.
1331 */
1332 spin_lock_irq(&send_cq->lock);
1333 if (send_cq != recv_cq)
1334 spin_lock(&recv_cq->lock);
1335
1336 spin_lock(&dev->qp_table.lock);
1337 mthca_array_clear(&dev->qp_table.qp, mqpn);
1338 spin_unlock(&dev->qp_table.lock);
1339
1340 if (send_cq != recv_cq)
1341 spin_unlock(&recv_cq->lock);
1342 spin_unlock_irq(&send_cq->lock);
1343
1344 err_out:
1345 dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1346 sqp->header_buf, sqp->header_dma);
1347
1348 return err;
1349 }
1350
1351 void mthca_free_qp(struct mthca_dev *dev,
1352 struct mthca_qp *qp)
1353 {
1354 u8 status;
1355 struct mthca_cq *send_cq;
1356 struct mthca_cq *recv_cq;
1357
1358 send_cq = to_mcq(qp->ibqp.send_cq);
1359 recv_cq = to_mcq(qp->ibqp.recv_cq);
1360
1361 /*
1362 * Lock CQs here, so that CQ polling code can do QP lookup
1363 * without taking a lock.
1364 */
1365 spin_lock_irq(&send_cq->lock);
1366 if (send_cq != recv_cq)
1367 spin_lock(&recv_cq->lock);
1368
1369 spin_lock(&dev->qp_table.lock);
1370 mthca_array_clear(&dev->qp_table.qp,
1371 qp->qpn & (dev->limits.num_qps - 1));
1372 spin_unlock(&dev->qp_table.lock);
1373
1374 if (send_cq != recv_cq)
1375 spin_unlock(&recv_cq->lock);
1376 spin_unlock_irq(&send_cq->lock);
1377
1378 atomic_dec(&qp->refcount);
1379 wait_event(qp->wait, !atomic_read(&qp->refcount));
1380
1381 if (qp->state != IB_QPS_RESET)
1382 mthca_MODIFY_QP(dev, MTHCA_TRANS_ANY2RST, qp->qpn, 0, NULL, 0, &status);
1383
1384 /*
1385 * If this is a userspace QP, the buffers, MR, CQs and so on
1386 * will be cleaned up in userspace, so all we have to do is
1387 * unref the mem-free tables and free the QPN in our table.
1388 */
1389 if (!qp->ibqp.uobject) {
1390 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn,
1391 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1392 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
1393 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn,
1394 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1395
1396 mthca_free_memfree(dev, qp);
1397 mthca_free_wqe_buf(dev, qp);
1398 }
1399
1400 mthca_unmap_memfree(dev, qp);
1401
1402 if (is_sqp(dev, qp)) {
1403 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1404 dma_free_coherent(&dev->pdev->dev,
1405 to_msqp(qp)->header_buf_size,
1406 to_msqp(qp)->header_buf,
1407 to_msqp(qp)->header_dma);
1408 } else
1409 mthca_free(&dev->qp_table.alloc, qp->qpn);
1410 }
1411
1412 /* Create UD header for an MLX send and build a data segment for it */
1413 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1414 int ind, struct ib_send_wr *wr,
1415 struct mthca_mlx_seg *mlx,
1416 struct mthca_data_seg *data)
1417 {
1418 int header_size;
1419 int err;
1420 u16 pkey;
1421
1422 ib_ud_header_init(256, /* assume a MAD */
1423 sqp->ud_header.grh_present,
1424 &sqp->ud_header);
1425
1426 err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1427 if (err)
1428 return err;
1429 mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1430 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1431 (sqp->ud_header.lrh.destination_lid ==
1432 IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1433 (sqp->ud_header.lrh.service_level << 8));
1434 mlx->rlid = sqp->ud_header.lrh.destination_lid;
1435 mlx->vcrc = 0;
1436
1437 switch (wr->opcode) {
1438 case IB_WR_SEND:
1439 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1440 sqp->ud_header.immediate_present = 0;
1441 break;
1442 case IB_WR_SEND_WITH_IMM:
1443 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1444 sqp->ud_header.immediate_present = 1;
1445 sqp->ud_header.immediate_data = wr->imm_data;
1446 break;
1447 default:
1448 return -EINVAL;
1449 }
1450
1451 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
1452 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1453 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1454 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1455 if (!sqp->qp.ibqp.qp_num)
1456 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1457 sqp->pkey_index, &pkey);
1458 else
1459 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1460 wr->wr.ud.pkey_index, &pkey);
1461 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1462 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1463 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1464 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1465 sqp->qkey : wr->wr.ud.remote_qkey);
1466 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1467
1468 header_size = ib_ud_header_pack(&sqp->ud_header,
1469 sqp->header_buf +
1470 ind * MTHCA_UD_HEADER_SIZE);
1471
1472 data->byte_count = cpu_to_be32(header_size);
1473 data->lkey = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1474 data->addr = cpu_to_be64(sqp->header_dma +
1475 ind * MTHCA_UD_HEADER_SIZE);
1476
1477 return 0;
1478 }
1479
1480 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1481 struct ib_cq *ib_cq)
1482 {
1483 unsigned cur;
1484 struct mthca_cq *cq;
1485
1486 cur = wq->head - wq->tail;
1487 if (likely(cur + nreq < wq->max))
1488 return 0;
1489
1490 cq = to_mcq(ib_cq);
1491 spin_lock(&cq->lock);
1492 cur = wq->head - wq->tail;
1493 spin_unlock(&cq->lock);
1494
1495 return cur + nreq >= wq->max;
1496 }
1497
1498 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1499 struct ib_send_wr **bad_wr)
1500 {
1501 struct mthca_dev *dev = to_mdev(ibqp->device);
1502 struct mthca_qp *qp = to_mqp(ibqp);
1503 void *wqe;
1504 void *prev_wqe;
1505 unsigned long flags;
1506 int err = 0;
1507 int nreq;
1508 int i;
1509 int size;
1510 int size0 = 0;
1511 u32 f0 = 0;
1512 int ind;
1513 u8 op0 = 0;
1514
1515 spin_lock_irqsave(&qp->sq.lock, flags);
1516
1517 /* XXX check that state is OK to post send */
1518
1519 ind = qp->sq.next_ind;
1520
1521 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1522 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1523 mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1524 " %d max, %d nreq)\n", qp->qpn,
1525 qp->sq.head, qp->sq.tail,
1526 qp->sq.max, nreq);
1527 err = -ENOMEM;
1528 *bad_wr = wr;
1529 goto out;
1530 }
1531
1532 wqe = get_send_wqe(qp, ind);
1533 prev_wqe = qp->sq.last;
1534 qp->sq.last = wqe;
1535
1536 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1537 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1538 ((struct mthca_next_seg *) wqe)->flags =
1539 ((wr->send_flags & IB_SEND_SIGNALED) ?
1540 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1541 ((wr->send_flags & IB_SEND_SOLICITED) ?
1542 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) |
1543 cpu_to_be32(1);
1544 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1545 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1546 ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1547
1548 wqe += sizeof (struct mthca_next_seg);
1549 size = sizeof (struct mthca_next_seg) / 16;
1550
1551 switch (qp->transport) {
1552 case RC:
1553 switch (wr->opcode) {
1554 case IB_WR_ATOMIC_CMP_AND_SWP:
1555 case IB_WR_ATOMIC_FETCH_AND_ADD:
1556 ((struct mthca_raddr_seg *) wqe)->raddr =
1557 cpu_to_be64(wr->wr.atomic.remote_addr);
1558 ((struct mthca_raddr_seg *) wqe)->rkey =
1559 cpu_to_be32(wr->wr.atomic.rkey);
1560 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1561
1562 wqe += sizeof (struct mthca_raddr_seg);
1563
1564 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1565 ((struct mthca_atomic_seg *) wqe)->swap_add =
1566 cpu_to_be64(wr->wr.atomic.swap);
1567 ((struct mthca_atomic_seg *) wqe)->compare =
1568 cpu_to_be64(wr->wr.atomic.compare_add);
1569 } else {
1570 ((struct mthca_atomic_seg *) wqe)->swap_add =
1571 cpu_to_be64(wr->wr.atomic.compare_add);
1572 ((struct mthca_atomic_seg *) wqe)->compare = 0;
1573 }
1574
1575 wqe += sizeof (struct mthca_atomic_seg);
1576 size += (sizeof (struct mthca_raddr_seg) +
1577 sizeof (struct mthca_atomic_seg)) / 16;
1578 break;
1579
1580 case IB_WR_RDMA_WRITE:
1581 case IB_WR_RDMA_WRITE_WITH_IMM:
1582 case IB_WR_RDMA_READ:
1583 ((struct mthca_raddr_seg *) wqe)->raddr =
1584 cpu_to_be64(wr->wr.rdma.remote_addr);
1585 ((struct mthca_raddr_seg *) wqe)->rkey =
1586 cpu_to_be32(wr->wr.rdma.rkey);
1587 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1588 wqe += sizeof (struct mthca_raddr_seg);
1589 size += sizeof (struct mthca_raddr_seg) / 16;
1590 break;
1591
1592 default:
1593 /* No extra segments required for sends */
1594 break;
1595 }
1596
1597 break;
1598
1599 case UC:
1600 switch (wr->opcode) {
1601 case IB_WR_RDMA_WRITE:
1602 case IB_WR_RDMA_WRITE_WITH_IMM:
1603 ((struct mthca_raddr_seg *) wqe)->raddr =
1604 cpu_to_be64(wr->wr.rdma.remote_addr);
1605 ((struct mthca_raddr_seg *) wqe)->rkey =
1606 cpu_to_be32(wr->wr.rdma.rkey);
1607 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1608 wqe += sizeof (struct mthca_raddr_seg);
1609 size += sizeof (struct mthca_raddr_seg) / 16;
1610 break;
1611
1612 default:
1613 /* No extra segments required for sends */
1614 break;
1615 }
1616
1617 break;
1618
1619 case UD:
1620 ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1621 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1622 ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1623 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1624 ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1625 cpu_to_be32(wr->wr.ud.remote_qpn);
1626 ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1627 cpu_to_be32(wr->wr.ud.remote_qkey);
1628
1629 wqe += sizeof (struct mthca_tavor_ud_seg);
1630 size += sizeof (struct mthca_tavor_ud_seg) / 16;
1631 break;
1632
1633 case MLX:
1634 err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1635 wqe - sizeof (struct mthca_next_seg),
1636 wqe);
1637 if (err) {
1638 *bad_wr = wr;
1639 goto out;
1640 }
1641 wqe += sizeof (struct mthca_data_seg);
1642 size += sizeof (struct mthca_data_seg) / 16;
1643 break;
1644 }
1645
1646 if (wr->num_sge > qp->sq.max_gs) {
1647 mthca_err(dev, "too many gathers\n");
1648 err = -EINVAL;
1649 *bad_wr = wr;
1650 goto out;
1651 }
1652
1653 for (i = 0; i < wr->num_sge; ++i) {
1654 ((struct mthca_data_seg *) wqe)->byte_count =
1655 cpu_to_be32(wr->sg_list[i].length);
1656 ((struct mthca_data_seg *) wqe)->lkey =
1657 cpu_to_be32(wr->sg_list[i].lkey);
1658 ((struct mthca_data_seg *) wqe)->addr =
1659 cpu_to_be64(wr->sg_list[i].addr);
1660 wqe += sizeof (struct mthca_data_seg);
1661 size += sizeof (struct mthca_data_seg) / 16;
1662 }
1663
1664 /* Add one more inline data segment for ICRC */
1665 if (qp->transport == MLX) {
1666 ((struct mthca_data_seg *) wqe)->byte_count =
1667 cpu_to_be32((1 << 31) | 4);
1668 ((u32 *) wqe)[1] = 0;
1669 wqe += sizeof (struct mthca_data_seg);
1670 size += sizeof (struct mthca_data_seg) / 16;
1671 }
1672
1673 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1674
1675 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1676 mthca_err(dev, "opcode invalid\n");
1677 err = -EINVAL;
1678 *bad_wr = wr;
1679 goto out;
1680 }
1681
1682 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1683 cpu_to_be32(((ind << qp->sq.wqe_shift) +
1684 qp->send_wqe_offset) |
1685 mthca_opcode[wr->opcode]);
1686 wmb();
1687 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1688 cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size);
1689
1690 if (!size0) {
1691 size0 = size;
1692 op0 = mthca_opcode[wr->opcode];
1693 }
1694
1695 ++ind;
1696 if (unlikely(ind >= qp->sq.max))
1697 ind -= qp->sq.max;
1698 }
1699
1700 out:
1701 if (likely(nreq)) {
1702 __be32 doorbell[2];
1703
1704 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1705 qp->send_wqe_offset) | f0 | op0);
1706 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1707
1708 wmb();
1709
1710 mthca_write64(doorbell,
1711 dev->kar + MTHCA_SEND_DOORBELL,
1712 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1713 }
1714
1715 qp->sq.next_ind = ind;
1716 qp->sq.head += nreq;
1717
1718 spin_unlock_irqrestore(&qp->sq.lock, flags);
1719 return err;
1720 }
1721
1722 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1723 struct ib_recv_wr **bad_wr)
1724 {
1725 struct mthca_dev *dev = to_mdev(ibqp->device);
1726 struct mthca_qp *qp = to_mqp(ibqp);
1727 __be32 doorbell[2];
1728 unsigned long flags;
1729 int err = 0;
1730 int nreq;
1731 int i;
1732 int size;
1733 int size0 = 0;
1734 int ind;
1735 void *wqe;
1736 void *prev_wqe;
1737
1738 spin_lock_irqsave(&qp->rq.lock, flags);
1739
1740 /* XXX check that state is OK to post receive */
1741
1742 ind = qp->rq.next_ind;
1743
1744 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1745 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
1746 nreq = 0;
1747
1748 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1749 doorbell[1] = cpu_to_be32(qp->qpn << 8);
1750
1751 wmb();
1752
1753 mthca_write64(doorbell,
1754 dev->kar + MTHCA_RECEIVE_DOORBELL,
1755 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1756
1757 qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
1758 size0 = 0;
1759 }
1760
1761 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1762 mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1763 " %d max, %d nreq)\n", qp->qpn,
1764 qp->rq.head, qp->rq.tail,
1765 qp->rq.max, nreq);
1766 err = -ENOMEM;
1767 *bad_wr = wr;
1768 goto out;
1769 }
1770
1771 wqe = get_recv_wqe(qp, ind);
1772 prev_wqe = qp->rq.last;
1773 qp->rq.last = wqe;
1774
1775 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1776 ((struct mthca_next_seg *) wqe)->ee_nds =
1777 cpu_to_be32(MTHCA_NEXT_DBD);
1778 ((struct mthca_next_seg *) wqe)->flags = 0;
1779
1780 wqe += sizeof (struct mthca_next_seg);
1781 size = sizeof (struct mthca_next_seg) / 16;
1782
1783 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1784 err = -EINVAL;
1785 *bad_wr = wr;
1786 goto out;
1787 }
1788
1789 for (i = 0; i < wr->num_sge; ++i) {
1790 ((struct mthca_data_seg *) wqe)->byte_count =
1791 cpu_to_be32(wr->sg_list[i].length);
1792 ((struct mthca_data_seg *) wqe)->lkey =
1793 cpu_to_be32(wr->sg_list[i].lkey);
1794 ((struct mthca_data_seg *) wqe)->addr =
1795 cpu_to_be64(wr->sg_list[i].addr);
1796 wqe += sizeof (struct mthca_data_seg);
1797 size += sizeof (struct mthca_data_seg) / 16;
1798 }
1799
1800 qp->wrid[ind] = wr->wr_id;
1801
1802 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1803 cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1804 wmb();
1805 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1806 cpu_to_be32(MTHCA_NEXT_DBD | size);
1807
1808 if (!size0)
1809 size0 = size;
1810
1811 ++ind;
1812 if (unlikely(ind >= qp->rq.max))
1813 ind -= qp->rq.max;
1814 }
1815
1816 out:
1817 if (likely(nreq)) {
1818 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1819 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1820
1821 wmb();
1822
1823 mthca_write64(doorbell,
1824 dev->kar + MTHCA_RECEIVE_DOORBELL,
1825 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1826 }
1827
1828 qp->rq.next_ind = ind;
1829 qp->rq.head += nreq;
1830
1831 spin_unlock_irqrestore(&qp->rq.lock, flags);
1832 return err;
1833 }
1834
1835 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1836 struct ib_send_wr **bad_wr)
1837 {
1838 struct mthca_dev *dev = to_mdev(ibqp->device);
1839 struct mthca_qp *qp = to_mqp(ibqp);
1840 __be32 doorbell[2];
1841 void *wqe;
1842 void *prev_wqe;
1843 unsigned long flags;
1844 int err = 0;
1845 int nreq;
1846 int i;
1847 int size;
1848 int size0 = 0;
1849 u32 f0 = 0;
1850 int ind;
1851 u8 op0 = 0;
1852
1853 spin_lock_irqsave(&qp->sq.lock, flags);
1854
1855 /* XXX check that state is OK to post send */
1856
1857 ind = qp->sq.head & (qp->sq.max - 1);
1858
1859 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1860 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) {
1861 nreq = 0;
1862
1863 doorbell[0] = cpu_to_be32((MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) |
1864 ((qp->sq.head & 0xffff) << 8) |
1865 f0 | op0);
1866 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1867
1868 qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB;
1869 size0 = 0;
1870
1871 /*
1872 * Make sure that descriptors are written before
1873 * doorbell record.
1874 */
1875 wmb();
1876 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1877
1878 /*
1879 * Make sure doorbell record is written before we
1880 * write MMIO send doorbell.
1881 */
1882 wmb();
1883 mthca_write64(doorbell,
1884 dev->kar + MTHCA_SEND_DOORBELL,
1885 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1886 }
1887
1888 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1889 mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1890 " %d max, %d nreq)\n", qp->qpn,
1891 qp->sq.head, qp->sq.tail,
1892 qp->sq.max, nreq);
1893 err = -ENOMEM;
1894 *bad_wr = wr;
1895 goto out;
1896 }
1897
1898 wqe = get_send_wqe(qp, ind);
1899 prev_wqe = qp->sq.last;
1900 qp->sq.last = wqe;
1901
1902 ((struct mthca_next_seg *) wqe)->flags =
1903 ((wr->send_flags & IB_SEND_SIGNALED) ?
1904 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1905 ((wr->send_flags & IB_SEND_SOLICITED) ?
1906 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) |
1907 cpu_to_be32(1);
1908 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1909 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1910 ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1911
1912 wqe += sizeof (struct mthca_next_seg);
1913 size = sizeof (struct mthca_next_seg) / 16;
1914
1915 switch (qp->transport) {
1916 case RC:
1917 switch (wr->opcode) {
1918 case IB_WR_ATOMIC_CMP_AND_SWP:
1919 case IB_WR_ATOMIC_FETCH_AND_ADD:
1920 ((struct mthca_raddr_seg *) wqe)->raddr =
1921 cpu_to_be64(wr->wr.atomic.remote_addr);
1922 ((struct mthca_raddr_seg *) wqe)->rkey =
1923 cpu_to_be32(wr->wr.atomic.rkey);
1924 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1925
1926 wqe += sizeof (struct mthca_raddr_seg);
1927
1928 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1929 ((struct mthca_atomic_seg *) wqe)->swap_add =
1930 cpu_to_be64(wr->wr.atomic.swap);
1931 ((struct mthca_atomic_seg *) wqe)->compare =
1932 cpu_to_be64(wr->wr.atomic.compare_add);
1933 } else {
1934 ((struct mthca_atomic_seg *) wqe)->swap_add =
1935 cpu_to_be64(wr->wr.atomic.compare_add);
1936 ((struct mthca_atomic_seg *) wqe)->compare = 0;
1937 }
1938
1939 wqe += sizeof (struct mthca_atomic_seg);
1940 size += (sizeof (struct mthca_raddr_seg) +
1941 sizeof (struct mthca_atomic_seg)) / 16;
1942 break;
1943
1944 case IB_WR_RDMA_READ:
1945 case IB_WR_RDMA_WRITE:
1946 case IB_WR_RDMA_WRITE_WITH_IMM:
1947 ((struct mthca_raddr_seg *) wqe)->raddr =
1948 cpu_to_be64(wr->wr.rdma.remote_addr);
1949 ((struct mthca_raddr_seg *) wqe)->rkey =
1950 cpu_to_be32(wr->wr.rdma.rkey);
1951 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1952 wqe += sizeof (struct mthca_raddr_seg);
1953 size += sizeof (struct mthca_raddr_seg) / 16;
1954 break;
1955
1956 default:
1957 /* No extra segments required for sends */
1958 break;
1959 }
1960
1961 break;
1962
1963 case UC:
1964 switch (wr->opcode) {
1965 case IB_WR_RDMA_WRITE:
1966 case IB_WR_RDMA_WRITE_WITH_IMM:
1967 ((struct mthca_raddr_seg *) wqe)->raddr =
1968 cpu_to_be64(wr->wr.rdma.remote_addr);
1969 ((struct mthca_raddr_seg *) wqe)->rkey =
1970 cpu_to_be32(wr->wr.rdma.rkey);
1971 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1972 wqe += sizeof (struct mthca_raddr_seg);
1973 size += sizeof (struct mthca_raddr_seg) / 16;
1974 break;
1975
1976 default:
1977 /* No extra segments required for sends */
1978 break;
1979 }
1980
1981 break;
1982
1983 case UD:
1984 memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
1985 to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
1986 ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
1987 cpu_to_be32(wr->wr.ud.remote_qpn);
1988 ((struct mthca_arbel_ud_seg *) wqe)->qkey =
1989 cpu_to_be32(wr->wr.ud.remote_qkey);
1990
1991 wqe += sizeof (struct mthca_arbel_ud_seg);
1992 size += sizeof (struct mthca_arbel_ud_seg) / 16;
1993 break;
1994
1995 case MLX:
1996 err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1997 wqe - sizeof (struct mthca_next_seg),
1998 wqe);
1999 if (err) {
2000 *bad_wr = wr;
2001 goto out;
2002 }
2003 wqe += sizeof (struct mthca_data_seg);
2004 size += sizeof (struct mthca_data_seg) / 16;
2005 break;
2006 }
2007
2008 if (wr->num_sge > qp->sq.max_gs) {
2009 mthca_err(dev, "too many gathers\n");
2010 err = -EINVAL;
2011 *bad_wr = wr;
2012 goto out;
2013 }
2014
2015 for (i = 0; i < wr->num_sge; ++i) {
2016 ((struct mthca_data_seg *) wqe)->byte_count =
2017 cpu_to_be32(wr->sg_list[i].length);
2018 ((struct mthca_data_seg *) wqe)->lkey =
2019 cpu_to_be32(wr->sg_list[i].lkey);
2020 ((struct mthca_data_seg *) wqe)->addr =
2021 cpu_to_be64(wr->sg_list[i].addr);
2022 wqe += sizeof (struct mthca_data_seg);
2023 size += sizeof (struct mthca_data_seg) / 16;
2024 }
2025
2026 /* Add one more inline data segment for ICRC */
2027 if (qp->transport == MLX) {
2028 ((struct mthca_data_seg *) wqe)->byte_count =
2029 cpu_to_be32((1 << 31) | 4);
2030 ((u32 *) wqe)[1] = 0;
2031 wqe += sizeof (struct mthca_data_seg);
2032 size += sizeof (struct mthca_data_seg) / 16;
2033 }
2034
2035 qp->wrid[ind + qp->rq.max] = wr->wr_id;
2036
2037 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
2038 mthca_err(dev, "opcode invalid\n");
2039 err = -EINVAL;
2040 *bad_wr = wr;
2041 goto out;
2042 }
2043
2044 ((struct mthca_next_seg *) prev_wqe)->nda_op =
2045 cpu_to_be32(((ind << qp->sq.wqe_shift) +
2046 qp->send_wqe_offset) |
2047 mthca_opcode[wr->opcode]);
2048 wmb();
2049 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
2050 cpu_to_be32(MTHCA_NEXT_DBD | size);
2051
2052 if (!size0) {
2053 size0 = size;
2054 op0 = mthca_opcode[wr->opcode];
2055 }
2056
2057 ++ind;
2058 if (unlikely(ind >= qp->sq.max))
2059 ind -= qp->sq.max;
2060 }
2061
2062 out:
2063 if (likely(nreq)) {
2064 doorbell[0] = cpu_to_be32((nreq << 24) |
2065 ((qp->sq.head & 0xffff) << 8) |
2066 f0 | op0);
2067 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
2068
2069 qp->sq.head += nreq;
2070
2071 /*
2072 * Make sure that descriptors are written before
2073 * doorbell record.
2074 */
2075 wmb();
2076 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2077
2078 /*
2079 * Make sure doorbell record is written before we
2080 * write MMIO send doorbell.
2081 */
2082 wmb();
2083 mthca_write64(doorbell,
2084 dev->kar + MTHCA_SEND_DOORBELL,
2085 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2086 }
2087
2088 spin_unlock_irqrestore(&qp->sq.lock, flags);
2089 return err;
2090 }
2091
2092 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2093 struct ib_recv_wr **bad_wr)
2094 {
2095 struct mthca_dev *dev = to_mdev(ibqp->device);
2096 struct mthca_qp *qp = to_mqp(ibqp);
2097 unsigned long flags;
2098 int err = 0;
2099 int nreq;
2100 int ind;
2101 int i;
2102 void *wqe;
2103
2104 spin_lock_irqsave(&qp->rq.lock, flags);
2105
2106 /* XXX check that state is OK to post receive */
2107
2108 ind = qp->rq.head & (qp->rq.max - 1);
2109
2110 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2111 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2112 mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2113 " %d max, %d nreq)\n", qp->qpn,
2114 qp->rq.head, qp->rq.tail,
2115 qp->rq.max, nreq);
2116 err = -ENOMEM;
2117 *bad_wr = wr;
2118 goto out;
2119 }
2120
2121 wqe = get_recv_wqe(qp, ind);
2122
2123 ((struct mthca_next_seg *) wqe)->flags = 0;
2124
2125 wqe += sizeof (struct mthca_next_seg);
2126
2127 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2128 err = -EINVAL;
2129 *bad_wr = wr;
2130 goto out;
2131 }
2132
2133 for (i = 0; i < wr->num_sge; ++i) {
2134 ((struct mthca_data_seg *) wqe)->byte_count =
2135 cpu_to_be32(wr->sg_list[i].length);
2136 ((struct mthca_data_seg *) wqe)->lkey =
2137 cpu_to_be32(wr->sg_list[i].lkey);
2138 ((struct mthca_data_seg *) wqe)->addr =
2139 cpu_to_be64(wr->sg_list[i].addr);
2140 wqe += sizeof (struct mthca_data_seg);
2141 }
2142
2143 if (i < qp->rq.max_gs) {
2144 ((struct mthca_data_seg *) wqe)->byte_count = 0;
2145 ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
2146 ((struct mthca_data_seg *) wqe)->addr = 0;
2147 }
2148
2149 qp->wrid[ind] = wr->wr_id;
2150
2151 ++ind;
2152 if (unlikely(ind >= qp->rq.max))
2153 ind -= qp->rq.max;
2154 }
2155 out:
2156 if (likely(nreq)) {
2157 qp->rq.head += nreq;
2158
2159 /*
2160 * Make sure that descriptors are written before
2161 * doorbell record.
2162 */
2163 wmb();
2164 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2165 }
2166
2167 spin_unlock_irqrestore(&qp->rq.lock, flags);
2168 return err;
2169 }
2170
2171 int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2172 int index, int *dbd, __be32 *new_wqe)
2173 {
2174 struct mthca_next_seg *next;
2175
2176 /*
2177 * For SRQs, all WQEs generate a CQE, so we're always at the
2178 * end of the doorbell chain.
2179 */
2180 if (qp->ibqp.srq) {
2181 *new_wqe = 0;
2182 return 0;
2183 }
2184
2185 if (is_send)
2186 next = get_send_wqe(qp, index);
2187 else
2188 next = get_recv_wqe(qp, index);
2189
2190 *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2191 if (next->ee_nds & cpu_to_be32(0x3f))
2192 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2193 (next->ee_nds & cpu_to_be32(0x3f));
2194 else
2195 *new_wqe = 0;
2196
2197 return 0;
2198 }
2199
2200 int __devinit mthca_init_qp_table(struct mthca_dev *dev)
2201 {
2202 int err;
2203 u8 status;
2204 int i;
2205
2206 spin_lock_init(&dev->qp_table.lock);
2207
2208 /*
2209 * We reserve 2 extra QPs per port for the special QPs. The
2210 * special QP for port 1 has to be even, so round up.
2211 */
2212 dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2213 err = mthca_alloc_init(&dev->qp_table.alloc,
2214 dev->limits.num_qps,
2215 (1 << 24) - 1,
2216 dev->qp_table.sqp_start +
2217 MTHCA_MAX_PORTS * 2);
2218 if (err)
2219 return err;
2220
2221 err = mthca_array_init(&dev->qp_table.qp,
2222 dev->limits.num_qps);
2223 if (err) {
2224 mthca_alloc_cleanup(&dev->qp_table.alloc);
2225 return err;
2226 }
2227
2228 for (i = 0; i < 2; ++i) {
2229 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2230 dev->qp_table.sqp_start + i * 2,
2231 &status);
2232 if (err)
2233 goto err_out;
2234 if (status) {
2235 mthca_warn(dev, "CONF_SPECIAL_QP returned "
2236 "status %02x, aborting.\n",
2237 status);
2238 err = -EINVAL;
2239 goto err_out;
2240 }
2241 }
2242 return 0;
2243
2244 err_out:
2245 for (i = 0; i < 2; ++i)
2246 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2247
2248 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2249 mthca_alloc_cleanup(&dev->qp_table.alloc);
2250
2251 return err;
2252 }
2253
2254 void __devexit mthca_cleanup_qp_table(struct mthca_dev *dev)
2255 {
2256 int i;
2257 u8 status;
2258
2259 for (i = 0; i < 2; ++i)
2260 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2261
2262 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2263 mthca_alloc_cleanup(&dev->qp_table.alloc);
2264 }
AMDTP streaming driver for the Linux FireWire stack (Juju)