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b43: LP-PHY: Implement spec updates and remove resolved FIXMEs
[firewire-audio.git] / drivers / net / wireless / b43 / phy_lp.c
blob2d3a5d812c42a38f43a6caf8cde9f3534bf1c1b6
1 /*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11g LP-PHY driver
5
6 Copyright (c) 2008-2009 Michael Buesch <mb@bu3sch.de>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23 */
24
25 #include "b43.h"
26 #include "main.h"
27 #include "phy_lp.h"
28 #include "phy_common.h"
29 #include "tables_lpphy.h"
30
31
32 static inline u16 channel2freq_lp(u8 channel)
33 {
34 if (channel < 14)
35 return (2407 + 5 * channel);
36 else if (channel == 14)
37 return 2484;
38 else if (channel < 184)
39 return (5000 + 5 * channel);
40 else
41 return (4000 + 5 * channel);
42 }
43
44 static unsigned int b43_lpphy_op_get_default_chan(struct b43_wldev *dev)
45 {
46 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
47 return 1;
48 return 36;
49 }
50
51 static int b43_lpphy_op_allocate(struct b43_wldev *dev)
52 {
53 struct b43_phy_lp *lpphy;
54
55 lpphy = kzalloc(sizeof(*lpphy), GFP_KERNEL);
56 if (!lpphy)
57 return -ENOMEM;
58 dev->phy.lp = lpphy;
59
60 return 0;
61 }
62
63 static void b43_lpphy_op_prepare_structs(struct b43_wldev *dev)
64 {
65 struct b43_phy *phy = &dev->phy;
66 struct b43_phy_lp *lpphy = phy->lp;
67
68 memset(lpphy, 0, sizeof(*lpphy));
69
70 //TODO
71 }
72
73 static void b43_lpphy_op_free(struct b43_wldev *dev)
74 {
75 struct b43_phy_lp *lpphy = dev->phy.lp;
76
77 kfree(lpphy);
78 dev->phy.lp = NULL;
79 }
80
81 static void lpphy_read_band_sprom(struct b43_wldev *dev)
82 {
83 struct b43_phy_lp *lpphy = dev->phy.lp;
84 struct ssb_bus *bus = dev->dev->bus;
85 u16 cckpo, maxpwr;
86 u32 ofdmpo;
87 int i;
88
89 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
90 lpphy->tx_isolation_med_band = bus->sprom.tri2g;
91 lpphy->bx_arch = bus->sprom.bxa2g;
92 lpphy->rx_pwr_offset = bus->sprom.rxpo2g;
93 lpphy->rssi_vf = bus->sprom.rssismf2g;
94 lpphy->rssi_vc = bus->sprom.rssismc2g;
95 lpphy->rssi_gs = bus->sprom.rssisav2g;
96 lpphy->txpa[0] = bus->sprom.pa0b0;
97 lpphy->txpa[1] = bus->sprom.pa0b1;
98 lpphy->txpa[2] = bus->sprom.pa0b2;
99 maxpwr = bus->sprom.maxpwr_bg;
100 lpphy->max_tx_pwr_med_band = maxpwr;
101 cckpo = bus->sprom.cck2gpo;
102 ofdmpo = bus->sprom.ofdm2gpo;
103 if (cckpo) {
104 for (i = 0; i < 4; i++) {
105 lpphy->tx_max_rate[i] =
106 maxpwr - (ofdmpo & 0xF) * 2;
107 ofdmpo >>= 4;
108 }
109 ofdmpo = bus->sprom.ofdm2gpo;
110 for (i = 4; i < 15; i++) {
111 lpphy->tx_max_rate[i] =
112 maxpwr - (ofdmpo & 0xF) * 2;
113 ofdmpo >>= 4;
114 }
115 } else {
116 ofdmpo &= 0xFF;
117 for (i = 0; i < 4; i++)
118 lpphy->tx_max_rate[i] = maxpwr;
119 for (i = 4; i < 15; i++)
120 lpphy->tx_max_rate[i] = maxpwr - ofdmpo;
121 }
122 } else { /* 5GHz */
123 lpphy->tx_isolation_low_band = bus->sprom.tri5gl;
124 lpphy->tx_isolation_med_band = bus->sprom.tri5g;
125 lpphy->tx_isolation_hi_band = bus->sprom.tri5gh;
126 lpphy->bx_arch = bus->sprom.bxa5g;
127 lpphy->rx_pwr_offset = bus->sprom.rxpo5g;
128 lpphy->rssi_vf = bus->sprom.rssismf5g;
129 lpphy->rssi_vc = bus->sprom.rssismc5g;
130 lpphy->rssi_gs = bus->sprom.rssisav5g;
131 lpphy->txpa[0] = bus->sprom.pa1b0;
132 lpphy->txpa[1] = bus->sprom.pa1b1;
133 lpphy->txpa[2] = bus->sprom.pa1b2;
134 lpphy->txpal[0] = bus->sprom.pa1lob0;
135 lpphy->txpal[1] = bus->sprom.pa1lob1;
136 lpphy->txpal[2] = bus->sprom.pa1lob2;
137 lpphy->txpah[0] = bus->sprom.pa1hib0;
138 lpphy->txpah[1] = bus->sprom.pa1hib1;
139 lpphy->txpah[2] = bus->sprom.pa1hib2;
140 maxpwr = bus->sprom.maxpwr_al;
141 ofdmpo = bus->sprom.ofdm5glpo;
142 lpphy->max_tx_pwr_low_band = maxpwr;
143 for (i = 4; i < 12; i++) {
144 lpphy->tx_max_ratel[i] = maxpwr - (ofdmpo & 0xF) * 2;
145 ofdmpo >>= 4;
146 }
147 maxpwr = bus->sprom.maxpwr_a;
148 ofdmpo = bus->sprom.ofdm5gpo;
149 lpphy->max_tx_pwr_med_band = maxpwr;
150 for (i = 4; i < 12; i++) {
151 lpphy->tx_max_rate[i] = maxpwr - (ofdmpo & 0xF) * 2;
152 ofdmpo >>= 4;
153 }
154 maxpwr = bus->sprom.maxpwr_ah;
155 ofdmpo = bus->sprom.ofdm5ghpo;
156 lpphy->max_tx_pwr_hi_band = maxpwr;
157 for (i = 4; i < 12; i++) {
158 lpphy->tx_max_rateh[i] = maxpwr - (ofdmpo & 0xF) * 2;
159 ofdmpo >>= 4;
160 }
161 }
162 }
163
164 static void lpphy_adjust_gain_table(struct b43_wldev *dev, u32 freq)
165 {
166 struct b43_phy_lp *lpphy = dev->phy.lp;
167 u16 temp[3];
168 u16 isolation;
169
170 B43_WARN_ON(dev->phy.rev >= 2);
171
172 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
173 isolation = lpphy->tx_isolation_med_band;
174 else if (freq <= 5320)
175 isolation = lpphy->tx_isolation_low_band;
176 else if (freq <= 5700)
177 isolation = lpphy->tx_isolation_med_band;
178 else
179 isolation = lpphy->tx_isolation_hi_band;
180
181 temp[0] = ((isolation - 26) / 12) << 12;
182 temp[1] = temp[0] + 0x1000;
183 temp[2] = temp[0] + 0x2000;
184
185 b43_lptab_write_bulk(dev, B43_LPTAB16(12, 0), 3, temp);
186 b43_lptab_write_bulk(dev, B43_LPTAB16(13, 0), 3, temp);
187 }
188
189 static void lpphy_table_init(struct b43_wldev *dev)
190 {
191 u32 freq = channel2freq_lp(b43_lpphy_op_get_default_chan(dev));
192
193 if (dev->phy.rev < 2)
194 lpphy_rev0_1_table_init(dev);
195 else
196 lpphy_rev2plus_table_init(dev);
197
198 lpphy_init_tx_gain_table(dev);
199
200 if (dev->phy.rev < 2)
201 lpphy_adjust_gain_table(dev, freq);
202 }
203
204 static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
205 {
206 struct ssb_bus *bus = dev->dev->bus;
207 struct b43_phy_lp *lpphy = dev->phy.lp;
208 u16 tmp, tmp2;
209
210 b43_phy_mask(dev, B43_LPPHY_AFE_DAC_CTL, 0xF7FF);
211 b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0);
212 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
213 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
214 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
215 b43_phy_set(dev, B43_LPPHY_AFE_DAC_CTL, 0x0004);
216 b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0x0078);
217 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
218 b43_phy_write(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x0016);
219 b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_0, 0xFFF8, 0x0004);
220 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5400);
221 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2400);
222 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
223 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0x0006);
224 b43_phy_mask(dev, B43_LPPHY_RX_RADIO_CTL, 0xFFFE);
225 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x0005);
226 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC10, 0x0180);
227 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x3800);
228 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFFF0, 0x0005);
229 b43_phy_maskset(dev, B43_LPPHY_GAIN_MISMATCH_LIMIT, 0xFFC0, 0x001A);
230 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0x00B3);
231 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
232 b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB,
233 0xFF00, lpphy->rx_pwr_offset);
234 if ((bus->sprom.boardflags_lo & B43_BFL_FEM) &&
235 ((b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
236 (bus->sprom.boardflags_hi & B43_BFH_PAREF))) {
237 /* TODO:
238 * Set the LDO voltage to 0x0028 - FIXME: What is this?
239 * Call sb_pmu_set_ldo_voltage with 4 and the LDO voltage
240 * as arguments
241 * Call sb_pmu_paref_ldo_enable with argument TRUE
242 */
243 if (dev->phy.rev == 0) {
244 b43_phy_maskset(dev, B43_LPPHY_LP_RF_SIGNAL_LUT,
245 0xFFCF, 0x0010);
246 }
247 b43_lptab_write(dev, B43_LPTAB16(11, 7), 60);
248 } else {
249 //TODO: Call ssb_pmu_paref_ldo_enable with argument FALSE
250 b43_phy_maskset(dev, B43_LPPHY_LP_RF_SIGNAL_LUT,
251 0xFFCF, 0x0020);
252 b43_lptab_write(dev, B43_LPTAB16(11, 7), 100);
253 }
254 tmp = lpphy->rssi_vf | lpphy->rssi_vc << 4 | 0xA000;
255 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, tmp);
256 if (bus->sprom.boardflags_hi & B43_BFH_RSSIINV)
257 b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x0AAA);
258 else
259 b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x02AA);
260 b43_lptab_write(dev, B43_LPTAB16(11, 1), 24);
261 b43_phy_maskset(dev, B43_LPPHY_RX_RADIO_CTL,
262 0xFFF9, (lpphy->bx_arch << 1));
263 if (dev->phy.rev == 1 &&
264 (bus->sprom.boardflags_hi & B43_BFH_FEM_BT)) {
265 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
266 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0x3F00, 0x0900);
267 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
268 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
269 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x000A);
270 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0400);
271 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x000A);
272 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0B00);
273 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xFFC0, 0x000A);
274 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xC0FF, 0x0900);
275 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xFFC0, 0x000A);
276 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xC0FF, 0x0B00);
277 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xFFC0, 0x000A);
278 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xC0FF, 0x0900);
279 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A);
280 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00);
281 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ ||
282 (bus->boardinfo.type == 0x048A) || ((dev->phy.rev == 0) &&
283 (bus->sprom.boardflags_lo & B43_BFL_FEM))) {
284 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001);
285 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400);
286 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001);
287 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0500);
288 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
289 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0800);
290 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
291 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0A00);
292 } else if (dev->phy.rev == 1 ||
293 (bus->sprom.boardflags_lo & B43_BFL_FEM)) {
294 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0004);
295 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0800);
296 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0004);
297 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0C00);
298 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
299 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0100);
300 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
301 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0300);
302 } else {
303 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
304 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0900);
305 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
306 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
307 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0006);
308 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0500);
309 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0006);
310 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0700);
311 }
312 if (dev->phy.rev == 1 && (bus->sprom.boardflags_hi & B43_BFH_PAREF)) {
313 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_5, B43_LPPHY_TR_LOOKUP_1);
314 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_6, B43_LPPHY_TR_LOOKUP_2);
315 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_7, B43_LPPHY_TR_LOOKUP_3);
316 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_8, B43_LPPHY_TR_LOOKUP_4);
317 }
318 if ((bus->sprom.boardflags_hi & B43_BFH_FEM_BT) &&
319 (bus->chip_id == 0x5354) &&
320 (bus->chip_package == SSB_CHIPPACK_BCM4712S)) {
321 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0006);
322 b43_phy_write(dev, B43_LPPHY_GPIO_SELECT, 0x0005);
323 b43_phy_write(dev, B43_LPPHY_GPIO_OUTEN, 0xFFFF);
324 //FIXME the Broadcom driver caches & delays this HF write!
325 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_PR45960W);
326 }
327 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
328 b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x8000);
329 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0040);
330 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0xA400);
331 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0x0B00);
332 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x0007);
333 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFF8, 0x0003);
334 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFC7, 0x0020);
335 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
336 } else { /* 5GHz */
337 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0x7FFF);
338 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFBF);
339 }
340 if (dev->phy.rev == 1) {
341 tmp = b43_phy_read(dev, B43_LPPHY_CLIPCTRTHRESH);
342 tmp2 = (tmp & 0x03E0) >> 5;
343 tmp2 |= tmp << 5;
344 b43_phy_write(dev, B43_LPPHY_4C3, tmp2);
345 tmp = b43_phy_read(dev, B43_LPPHY_OFDMSYNCTHRESH0);
346 tmp2 = (tmp & 0x1F00) >> 8;
347 tmp2 |= tmp << 5;
348 b43_phy_write(dev, B43_LPPHY_4C4, tmp2);
349 tmp = b43_phy_read(dev, B43_LPPHY_VERYLOWGAINDB);
350 tmp2 = tmp & 0x00FF;
351 tmp2 |= tmp << 8;
352 b43_phy_write(dev, B43_LPPHY_4C5, tmp2);
353 }
354 }
355
356 static void lpphy_save_dig_flt_state(struct b43_wldev *dev)
357 {
358 static const u16 addr[] = {
359 B43_PHY_OFDM(0xC1),
360 B43_PHY_OFDM(0xC2),
361 B43_PHY_OFDM(0xC3),
362 B43_PHY_OFDM(0xC4),
363 B43_PHY_OFDM(0xC5),
364 B43_PHY_OFDM(0xC6),
365 B43_PHY_OFDM(0xC7),
366 B43_PHY_OFDM(0xC8),
367 B43_PHY_OFDM(0xCF),
368 };
369
370 static const u16 coefs[] = {
371 0xDE5E, 0xE832, 0xE331, 0x4D26,
372 0x0026, 0x1420, 0x0020, 0xFE08,
373 0x0008,
374 };
375
376 struct b43_phy_lp *lpphy = dev->phy.lp;
377 int i;
378
379 for (i = 0; i < ARRAY_SIZE(addr); i++) {
380 lpphy->dig_flt_state[i] = b43_phy_read(dev, addr[i]);
381 b43_phy_write(dev, addr[i], coefs[i]);
382 }
383 }
384
385 static void lpphy_restore_dig_flt_state(struct b43_wldev *dev)
386 {
387 static const u16 addr[] = {
388 B43_PHY_OFDM(0xC1),
389 B43_PHY_OFDM(0xC2),
390 B43_PHY_OFDM(0xC3),
391 B43_PHY_OFDM(0xC4),
392 B43_PHY_OFDM(0xC5),
393 B43_PHY_OFDM(0xC6),
394 B43_PHY_OFDM(0xC7),
395 B43_PHY_OFDM(0xC8),
396 B43_PHY_OFDM(0xCF),
397 };
398
399 struct b43_phy_lp *lpphy = dev->phy.lp;
400 int i;
401
402 for (i = 0; i < ARRAY_SIZE(addr); i++)
403 b43_phy_write(dev, addr[i], lpphy->dig_flt_state[i]);
404 }
405
406 static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
407 {
408 struct ssb_bus *bus = dev->dev->bus;
409 struct b43_phy_lp *lpphy = dev->phy.lp;
410
411 b43_phy_write(dev, B43_LPPHY_AFE_DAC_CTL, 0x50);
412 b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0x8800);
413 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
414 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0);
415 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
416 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
417 b43_phy_write(dev, B43_PHY_OFDM(0xF9), 0);
418 b43_phy_write(dev, B43_LPPHY_TR_LOOKUP_1, 0);
419 b43_phy_set(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x10);
420 b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0xB4);
421 b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xF8FF, 0x200);
422 b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xFF00, 0x7F);
423 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFF0F, 0x40);
424 b43_phy_maskset(dev, B43_LPPHY_PREAMBLECONFIRMTO, 0xFF00, 0x2);
425 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000);
426 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000);
427 b43_phy_set(dev, B43_PHY_OFDM(0x10A), 0x1);
428 if (bus->boardinfo.rev >= 0x18) {
429 b43_lptab_write(dev, B43_LPTAB32(17, 65), 0xEC);
430 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x14);
431 } else {
432 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x10);
433 }
434 b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0xFF00, 0xF4);
435 b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0x00FF, 0xF100);
436 b43_phy_write(dev, B43_LPPHY_CLIPTHRESH, 0x48);
437 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0xFF00, 0x46);
438 b43_phy_maskset(dev, B43_PHY_OFDM(0xE4), 0xFF00, 0x10);
439 b43_phy_maskset(dev, B43_LPPHY_PWR_THRESH1, 0xFFF0, 0x9);
440 b43_phy_mask(dev, B43_LPPHY_GAINDIRECTMISMATCH, ~0xF);
441 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5500);
442 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC1F, 0xA0);
443 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xE0FF, 0x300);
444 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2A00);
445 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
446 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
447 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xA);
448 } else {
449 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x1E00);
450 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xD);
451 }
452 b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFFE0, 0x1F);
453 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
454 b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0xFF00, 0x19);
455 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0x03FF, 0x3C00);
456 b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFC1F, 0x3E0);
457 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
458 b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0x00FF, 0x1900);
459 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
460 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x12);
461 b43_phy_maskset(dev, B43_LPPHY_GAINMISMATCH, 0x0FFF, 0x9000);
462
463 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
464 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x14), 0);
465 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x12), 0x40);
466 }
467
468 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
469 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x40);
470 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0xB00);
471 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x6);
472 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0x9D00);
473 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0xFF00, 0xA1);
474 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
475 } else /* 5GHz */
476 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x40);
477
478 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0xB3);
479 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
480 b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB, 0xFF00, lpphy->rx_pwr_offset);
481 b43_phy_set(dev, B43_LPPHY_RESET_CTL, 0x44);
482 b43_phy_write(dev, B43_LPPHY_RESET_CTL, 0x80);
483 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, 0xA954);
484 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_1,
485 0x2000 | ((u16)lpphy->rssi_gs << 10) |
486 ((u16)lpphy->rssi_vc << 4) | lpphy->rssi_vf);
487
488 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
489 b43_phy_set(dev, B43_LPPHY_AFE_ADC_CTL_0, 0x1C);
490 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL, 0x00FF, 0x8800);
491 b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_1, 0xFC3C, 0x0400);
492 }
493
494 lpphy_save_dig_flt_state(dev);
495 }
496
497 static void lpphy_baseband_init(struct b43_wldev *dev)
498 {
499 lpphy_table_init(dev);
500 if (dev->phy.rev >= 2)
501 lpphy_baseband_rev2plus_init(dev);
502 else
503 lpphy_baseband_rev0_1_init(dev);
504 }
505
506 struct b2062_freqdata {
507 u16 freq;
508 u8 data[6];
509 };
510
511 /* Initialize the 2062 radio. */
512 static void lpphy_2062_init(struct b43_wldev *dev)
513 {
514 struct b43_phy_lp *lpphy = dev->phy.lp;
515 struct ssb_bus *bus = dev->dev->bus;
516 u32 crystalfreq, tmp, ref;
517 unsigned int i;
518 const struct b2062_freqdata *fd = NULL;
519
520 static const struct b2062_freqdata freqdata_tab[] = {
521 { .freq = 12000, .data[0] = 6, .data[1] = 6, .data[2] = 6,
522 .data[3] = 6, .data[4] = 10, .data[5] = 6, },
523 { .freq = 13000, .data[0] = 4, .data[1] = 4, .data[2] = 4,
524 .data[3] = 4, .data[4] = 11, .data[5] = 7, },
525 { .freq = 14400, .data[0] = 3, .data[1] = 3, .data[2] = 3,
526 .data[3] = 3, .data[4] = 12, .data[5] = 7, },
527 { .freq = 16200, .data[0] = 3, .data[1] = 3, .data[2] = 3,
528 .data[3] = 3, .data[4] = 13, .data[5] = 8, },
529 { .freq = 18000, .data[0] = 2, .data[1] = 2, .data[2] = 2,
530 .data[3] = 2, .data[4] = 14, .data[5] = 8, },
531 { .freq = 19200, .data[0] = 1, .data[1] = 1, .data[2] = 1,
532 .data[3] = 1, .data[4] = 14, .data[5] = 9, },
533 };
534
535 b2062_upload_init_table(dev);
536
537 b43_radio_write(dev, B2062_N_TX_CTL3, 0);
538 b43_radio_write(dev, B2062_N_TX_CTL4, 0);
539 b43_radio_write(dev, B2062_N_TX_CTL5, 0);
540 b43_radio_write(dev, B2062_N_TX_CTL6, 0);
541 b43_radio_write(dev, B2062_N_PDN_CTL0, 0x40);
542 b43_radio_write(dev, B2062_N_PDN_CTL0, 0);
543 b43_radio_write(dev, B2062_N_CALIB_TS, 0x10);
544 b43_radio_write(dev, B2062_N_CALIB_TS, 0);
545 if (dev->phy.rev > 0) {
546 b43_radio_write(dev, B2062_S_BG_CTL1,
547 (b43_radio_read(dev, B2062_N_COMM2) >> 1) | 0x80);
548 }
549 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
550 b43_radio_set(dev, B2062_N_TSSI_CTL0, 0x1);
551 else
552 b43_radio_mask(dev, B2062_N_TSSI_CTL0, ~0x1);
553
554 /* Get the crystal freq, in Hz. */
555 crystalfreq = bus->chipco.pmu.crystalfreq * 1000;
556
557 B43_WARN_ON(!(bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU));
558 B43_WARN_ON(crystalfreq == 0);
559
560 if (crystalfreq <= 30000000) {
561 lpphy->pdiv = 1;
562 b43_radio_mask(dev, B2062_S_RFPLL_CTL1, 0xFFFB);
563 } else {
564 lpphy->pdiv = 2;
565 b43_radio_set(dev, B2062_S_RFPLL_CTL1, 0x4);
566 }
567
568 tmp = (((800000000 * lpphy->pdiv + crystalfreq) /
569 (2 * crystalfreq)) - 8) & 0xFF;
570 b43_radio_write(dev, B2062_S_RFPLL_CTL7, tmp);
571
572 tmp = (((100 * crystalfreq + 16000000 * lpphy->pdiv) /
573 (32000000 * lpphy->pdiv)) - 1) & 0xFF;
574 b43_radio_write(dev, B2062_S_RFPLL_CTL18, tmp);
575
576 tmp = (((2 * crystalfreq + 1000000 * lpphy->pdiv) /
577 (2000000 * lpphy->pdiv)) - 1) & 0xFF;
578 b43_radio_write(dev, B2062_S_RFPLL_CTL19, tmp);
579
580 ref = (1000 * lpphy->pdiv + 2 * crystalfreq) / (2000 * lpphy->pdiv);
581 ref &= 0xFFFF;
582 for (i = 0; i < ARRAY_SIZE(freqdata_tab); i++) {
583 if (ref < freqdata_tab[i].freq) {
584 fd = &freqdata_tab[i];
585 break;
586 }
587 }
588 if (!fd)
589 fd = &freqdata_tab[ARRAY_SIZE(freqdata_tab) - 1];
590 b43dbg(dev->wl, "b2062: Using crystal tab entry %u kHz.\n",
591 fd->freq); /* FIXME: Keep this printk until the code is fully debugged. */
592
593 b43_radio_write(dev, B2062_S_RFPLL_CTL8,
594 ((u16)(fd->data[1]) << 4) | fd->data[0]);
595 b43_radio_write(dev, B2062_S_RFPLL_CTL9,
596 ((u16)(fd->data[3]) << 4) | fd->data[2]);
597 b43_radio_write(dev, B2062_S_RFPLL_CTL10, fd->data[4]);
598 b43_radio_write(dev, B2062_S_RFPLL_CTL11, fd->data[5]);
599 }
600
601 /* Initialize the 2063 radio. */
602 static void lpphy_2063_init(struct b43_wldev *dev)
603 {
604 b2063_upload_init_table(dev);
605 b43_radio_write(dev, B2063_LOGEN_SP5, 0);
606 b43_radio_set(dev, B2063_COMM8, 0x38);
607 b43_radio_write(dev, B2063_REG_SP1, 0x56);
608 b43_radio_mask(dev, B2063_RX_BB_CTL2, ~0x2);
609 b43_radio_write(dev, B2063_PA_SP7, 0);
610 b43_radio_write(dev, B2063_TX_RF_SP6, 0x20);
611 b43_radio_write(dev, B2063_TX_RF_SP9, 0x40);
612 if (dev->phy.rev == 2) {
613 b43_radio_write(dev, B2063_PA_SP3, 0xa0);
614 b43_radio_write(dev, B2063_PA_SP4, 0xa0);
615 b43_radio_write(dev, B2063_PA_SP2, 0x18);
616 } else {
617 b43_radio_write(dev, B2063_PA_SP3, 0x20);
618 b43_radio_write(dev, B2063_PA_SP2, 0x20);
619 }
620 }
621
622 struct lpphy_stx_table_entry {
623 u16 phy_offset;
624 u16 phy_shift;
625 u16 rf_addr;
626 u16 rf_shift;
627 u16 mask;
628 };
629
630 static const struct lpphy_stx_table_entry lpphy_stx_table[] = {
631 { .phy_offset = 2, .phy_shift = 6, .rf_addr = 0x3d, .rf_shift = 3, .mask = 0x01, },
632 { .phy_offset = 1, .phy_shift = 12, .rf_addr = 0x4c, .rf_shift = 1, .mask = 0x01, },
633 { .phy_offset = 1, .phy_shift = 8, .rf_addr = 0x50, .rf_shift = 0, .mask = 0x7f, },
634 { .phy_offset = 0, .phy_shift = 8, .rf_addr = 0x44, .rf_shift = 0, .mask = 0xff, },
635 { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4a, .rf_shift = 0, .mask = 0xff, },
636 { .phy_offset = 0, .phy_shift = 4, .rf_addr = 0x4d, .rf_shift = 0, .mask = 0xff, },
637 { .phy_offset = 1, .phy_shift = 4, .rf_addr = 0x4e, .rf_shift = 0, .mask = 0xff, },
638 { .phy_offset = 0, .phy_shift = 12, .rf_addr = 0x4f, .rf_shift = 0, .mask = 0x0f, },
639 { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4f, .rf_shift = 4, .mask = 0x0f, },
640 { .phy_offset = 3, .phy_shift = 0, .rf_addr = 0x49, .rf_shift = 0, .mask = 0x0f, },
641 { .phy_offset = 4, .phy_shift = 3, .rf_addr = 0x46, .rf_shift = 4, .mask = 0x07, },
642 { .phy_offset = 3, .phy_shift = 15, .rf_addr = 0x46, .rf_shift = 0, .mask = 0x01, },
643 { .phy_offset = 4, .phy_shift = 0, .rf_addr = 0x46, .rf_shift = 1, .mask = 0x07, },
644 { .phy_offset = 3, .phy_shift = 8, .rf_addr = 0x48, .rf_shift = 4, .mask = 0x07, },
645 { .phy_offset = 3, .phy_shift = 11, .rf_addr = 0x48, .rf_shift = 0, .mask = 0x0f, },
646 { .phy_offset = 3, .phy_shift = 4, .rf_addr = 0x49, .rf_shift = 4, .mask = 0x0f, },
647 { .phy_offset = 2, .phy_shift = 15, .rf_addr = 0x45, .rf_shift = 0, .mask = 0x01, },
648 { .phy_offset = 5, .phy_shift = 13, .rf_addr = 0x52, .rf_shift = 4, .mask = 0x07, },
649 { .phy_offset = 6, .phy_shift = 0, .rf_addr = 0x52, .rf_shift = 7, .mask = 0x01, },
650 { .phy_offset = 5, .phy_shift = 3, .rf_addr = 0x41, .rf_shift = 5, .mask = 0x07, },
651 { .phy_offset = 5, .phy_shift = 6, .rf_addr = 0x41, .rf_shift = 0, .mask = 0x0f, },
652 { .phy_offset = 5, .phy_shift = 10, .rf_addr = 0x42, .rf_shift = 5, .mask = 0x07, },
653 { .phy_offset = 4, .phy_shift = 15, .rf_addr = 0x42, .rf_shift = 0, .mask = 0x01, },
654 { .phy_offset = 5, .phy_shift = 0, .rf_addr = 0x42, .rf_shift = 1, .mask = 0x07, },
655 { .phy_offset = 4, .phy_shift = 11, .rf_addr = 0x43, .rf_shift = 4, .mask = 0x0f, },
656 { .phy_offset = 4, .phy_shift = 7, .rf_addr = 0x43, .rf_shift = 0, .mask = 0x0f, },
657 { .phy_offset = 4, .phy_shift = 6, .rf_addr = 0x45, .rf_shift = 1, .mask = 0x01, },
658 { .phy_offset = 2, .phy_shift = 7, .rf_addr = 0x40, .rf_shift = 4, .mask = 0x0f, },
659 { .phy_offset = 2, .phy_shift = 11, .rf_addr = 0x40, .rf_shift = 0, .mask = 0x0f, },
660 };
661
662 static void lpphy_sync_stx(struct b43_wldev *dev)
663 {
664 const struct lpphy_stx_table_entry *e;
665 unsigned int i;
666 u16 tmp;
667
668 for (i = 0; i < ARRAY_SIZE(lpphy_stx_table); i++) {
669 e = &lpphy_stx_table[i];
670 tmp = b43_radio_read(dev, e->rf_addr);
671 tmp >>= e->rf_shift;
672 tmp <<= e->phy_shift;
673 b43_phy_maskset(dev, B43_PHY_OFDM(0xF2 + e->phy_offset),
674 ~(e->mask << e->phy_shift), tmp);
675 }
676 }
677
678 static void lpphy_radio_init(struct b43_wldev *dev)
679 {
680 /* The radio is attached through the 4wire bus. */
681 b43_phy_set(dev, B43_LPPHY_FOURWIRE_CTL, 0x2);
682 udelay(1);
683 b43_phy_mask(dev, B43_LPPHY_FOURWIRE_CTL, 0xFFFD);
684 udelay(1);
685
686 if (dev->phy.radio_ver == 0x2062) {
687 lpphy_2062_init(dev);
688 } else {
689 lpphy_2063_init(dev);
690 lpphy_sync_stx(dev);
691 b43_phy_write(dev, B43_PHY_OFDM(0xF0), 0x5F80);
692 b43_phy_write(dev, B43_PHY_OFDM(0xF1), 0);
693 if (dev->dev->bus->chip_id == 0x4325) {
694 // TODO SSB PMU recalibration
695 }
696 }
697 }
698
699 struct lpphy_iq_est { u32 iq_prod, i_pwr, q_pwr; };
700
701 static void lpphy_set_rc_cap(struct b43_wldev *dev)
702 {
703 struct b43_phy_lp *lpphy = dev->phy.lp;
704
705 u8 rc_cap = (lpphy->rc_cap & 0x1F) >> 1;
706
707 if (dev->phy.rev == 1) //FIXME check channel 14!
708 rc_cap = max_t(u8, rc_cap + 5, 15);
709
710 b43_radio_write(dev, B2062_N_RXBB_CALIB2,
711 max_t(u8, lpphy->rc_cap - 4, 0x80));
712 b43_radio_write(dev, B2062_N_TX_CTL_A, rc_cap | 0x80);
713 b43_radio_write(dev, B2062_S_RXG_CNT16,
714 ((lpphy->rc_cap & 0x1F) >> 2) | 0x80);
715 }
716
717 static u8 lpphy_get_bb_mult(struct b43_wldev *dev)
718 {
719 return (b43_lptab_read(dev, B43_LPTAB16(0, 87)) & 0xFF00) >> 8;
720 }
721
722 static void lpphy_set_bb_mult(struct b43_wldev *dev, u8 bb_mult)
723 {
724 b43_lptab_write(dev, B43_LPTAB16(0, 87), (u16)bb_mult << 8);
725 }
726
727 static void lpphy_set_deaf(struct b43_wldev *dev, bool user)
728 {
729 struct b43_phy_lp *lpphy = dev->phy.lp;
730
731 if (user)
732 lpphy->crs_usr_disable = 1;
733 else
734 lpphy->crs_sys_disable = 1;
735 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFF1F, 0x80);
736 }
737
738 static void lpphy_clear_deaf(struct b43_wldev *dev, bool user)
739 {
740 struct b43_phy_lp *lpphy = dev->phy.lp;
741
742 if (user)
743 lpphy->crs_usr_disable = 0;
744 else
745 lpphy->crs_sys_disable = 0;
746
747 if (!lpphy->crs_usr_disable && !lpphy->crs_sys_disable) {
748 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
749 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL,
750 0xFF1F, 0x60);
751 else
752 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL,
753 0xFF1F, 0x20);
754 }
755 }
756
757 static void lpphy_disable_crs(struct b43_wldev *dev, bool user)
758 {
759 lpphy_set_deaf(dev, user);
760 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x1);
761 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
762 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFB);
763 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x4);
764 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFF7);
765 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
766 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x10);
767 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
768 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFDF);
769 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x20);
770 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFBF);
771 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
772 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x7);
773 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x38);
774 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F);
775 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x100);
776 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFDFF);
777 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL0, 0);
778 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL1, 1);
779 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL2, 0x20);
780 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFBFF);
781 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xF7FF);
782 b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL, 0);
783 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, 0x45AF);
784 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0x3FF);
785 }
786
787 static void lpphy_restore_crs(struct b43_wldev *dev, bool user)
788 {
789 lpphy_clear_deaf(dev, user);
790 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFF80);
791 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFC00);
792 }
793
794 struct lpphy_tx_gains { u16 gm, pga, pad, dac; };
795
796 static struct lpphy_tx_gains lpphy_get_tx_gains(struct b43_wldev *dev)
797 {
798 struct lpphy_tx_gains gains;
799 u16 tmp;
800
801 gains.dac = (b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0x380) >> 7;
802 if (dev->phy.rev < 2) {
803 tmp = b43_phy_read(dev,
804 B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL) & 0x7FF;
805 gains.gm = tmp & 0x0007;
806 gains.pga = (tmp & 0x0078) >> 3;
807 gains.pad = (tmp & 0x780) >> 7;
808 } else {
809 tmp = b43_phy_read(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL);
810 gains.pad = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0xFF;
811 gains.gm = tmp & 0xFF;
812 gains.pga = (tmp >> 8) & 0xFF;
813 }
814
815 return gains;
816 }
817
818 static void lpphy_set_dac_gain(struct b43_wldev *dev, u16 dac)
819 {
820 u16 ctl = b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0xC7F;
821 ctl |= dac << 7;
822 b43_phy_maskset(dev, B43_LPPHY_AFE_DAC_CTL, 0xF000, ctl);
823 }
824
825 static void lpphy_set_tx_gains(struct b43_wldev *dev,
826 struct lpphy_tx_gains gains)
827 {
828 u16 rf_gain, pa_gain;
829
830 if (dev->phy.rev < 2) {
831 rf_gain = (gains.pad << 7) | (gains.pga << 3) | gains.gm;
832 b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
833 0xF800, rf_gain);
834 } else {
835 pa_gain = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0x1FC0;
836 pa_gain <<= 2;
837 b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
838 (gains.pga << 8) | gains.gm);
839 b43_phy_maskset(dev, B43_PHY_OFDM(0xFB),
840 0x8000, gains.pad | pa_gain);
841 b43_phy_write(dev, B43_PHY_OFDM(0xFC),
842 (gains.pga << 8) | gains.gm);
843 b43_phy_maskset(dev, B43_PHY_OFDM(0xFD),
844 0x8000, gains.pad | pa_gain);
845 }
846 lpphy_set_dac_gain(dev, gains.dac);
847 if (dev->phy.rev < 2) {
848 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF, 1 << 8);
849 } else {
850 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFF7F, 1 << 7);
851 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xBFFF, 1 << 14);
852 }
853 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFBF, 1 << 6);
854 }
855
856 static void lpphy_rev0_1_set_rx_gain(struct b43_wldev *dev, u32 gain)
857 {
858 u16 trsw = gain & 0x1;
859 u16 lna = (gain & 0xFFFC) | ((gain & 0xC) >> 2);
860 u16 ext_lna = (gain & 2) >> 1;
861
862 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw);
863 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
864 0xFBFF, ext_lna << 10);
865 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
866 0xF7FF, ext_lna << 11);
867 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, lna);
868 }
869
870 static void lpphy_rev2plus_set_rx_gain(struct b43_wldev *dev, u32 gain)
871 {
872 u16 low_gain = gain & 0xFFFF;
873 u16 high_gain = (gain >> 16) & 0xF;
874 u16 ext_lna = (gain >> 21) & 0x1;
875 u16 trsw = ~(gain >> 20) & 0x1;
876 u16 tmp;
877
878 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw);
879 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
880 0xFDFF, ext_lna << 9);
881 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
882 0xFBFF, ext_lna << 10);
883 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, low_gain);
884 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF0, high_gain);
885 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
886 tmp = (gain >> 2) & 0x3;
887 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
888 0xE7FF, tmp<<11);
889 b43_phy_maskset(dev, B43_PHY_OFDM(0xE6), 0xFFE7, tmp << 3);
890 }
891 }
892
893 static void lpphy_disable_rx_gain_override(struct b43_wldev *dev)
894 {
895 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFE);
896 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFEF);
897 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFBF);
898 if (dev->phy.rev >= 2) {
899 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF);
900 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
901 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFBFF);
902 b43_phy_mask(dev, B43_PHY_OFDM(0xE5), 0xFFF7);
903 }
904 } else {
905 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFDFF);
906 }
907 }
908
909 static void lpphy_enable_rx_gain_override(struct b43_wldev *dev)
910 {
911 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1);
912 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
913 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
914 if (dev->phy.rev >= 2) {
915 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100);
916 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
917 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x400);
918 b43_phy_set(dev, B43_PHY_OFDM(0xE5), 0x8);
919 }
920 } else {
921 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x200);
922 }
923 }
924
925 static void lpphy_set_rx_gain(struct b43_wldev *dev, u32 gain)
926 {
927 if (dev->phy.rev < 2)
928 lpphy_rev0_1_set_rx_gain(dev, gain);
929 else
930 lpphy_rev2plus_set_rx_gain(dev, gain);
931 lpphy_enable_rx_gain_override(dev);
932 }
933
934 static void lpphy_set_rx_gain_by_index(struct b43_wldev *dev, u16 idx)
935 {
936 u32 gain = b43_lptab_read(dev, B43_LPTAB16(12, idx));
937 lpphy_set_rx_gain(dev, gain);
938 }
939
940 static void lpphy_stop_ddfs(struct b43_wldev *dev)
941 {
942 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFD);
943 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xFFDF);
944 }
945
946 static void lpphy_run_ddfs(struct b43_wldev *dev, int i_on, int q_on,
947 int incr1, int incr2, int scale_idx)
948 {
949 lpphy_stop_ddfs(dev);
950 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0xFF80);
951 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0x80FF);
952 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0xFF80, incr1);
953 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0x80FF, incr2 << 8);
954 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF7, i_on << 3);
955 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFEF, q_on << 4);
956 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFF9F, scale_idx << 5);
957 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFB);
958 b43_phy_set(dev, B43_LPPHY_AFE_DDFS, 0x2);
959 b43_phy_set(dev, B43_LPPHY_AFE_DDFS, 0x20);
960 }
961
962 static bool lpphy_rx_iq_est(struct b43_wldev *dev, u16 samples, u8 time,
963 struct lpphy_iq_est *iq_est)
964 {
965 int i;
966
967 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFF7);
968 b43_phy_write(dev, B43_LPPHY_IQ_NUM_SMPLS_ADDR, samples);
969 b43_phy_maskset(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFF00, time);
970 b43_phy_mask(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFEFF);
971 b43_phy_set(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFDFF);
972
973 for (i = 0; i < 500; i++) {
974 if (!(b43_phy_read(dev,
975 B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200))
976 break;
977 msleep(1);
978 }
979
980 if ((b43_phy_read(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200)) {
981 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8);
982 return false;
983 }
984
985 iq_est->iq_prod = b43_phy_read(dev, B43_LPPHY_IQ_ACC_HI_ADDR);
986 iq_est->iq_prod <<= 16;
987 iq_est->iq_prod |= b43_phy_read(dev, B43_LPPHY_IQ_ACC_LO_ADDR);
988
989 iq_est->i_pwr = b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_HI_ADDR);
990 iq_est->i_pwr <<= 16;
991 iq_est->i_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_LO_ADDR);
992
993 iq_est->q_pwr = b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_HI_ADDR);
994 iq_est->q_pwr <<= 16;
995 iq_est->q_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_LO_ADDR);
996
997 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8);
998 return true;
999 }
1000
1001 static int lpphy_loopback(struct b43_wldev *dev)
1002 {
1003 struct lpphy_iq_est iq_est;
1004 int i, index = -1;
1005 u32 tmp;
1006
1007 memset(&iq_est, 0, sizeof(iq_est));
1008
1009 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x3);
1010 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
1011 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE);
1012 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x800);
1013 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x800);
1014 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
1015 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x8);
1016 b43_radio_write(dev, B2062_N_TX_CTL_A, 0x80);
1017 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x80);
1018 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x80);
1019 for (i = 0; i < 32; i++) {
1020 lpphy_set_rx_gain_by_index(dev, i);
1021 lpphy_run_ddfs(dev, 1, 1, 5, 5, 0);
1022 if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est)))
1023 continue;
1024 tmp = (iq_est.i_pwr + iq_est.q_pwr) / 1000;
1025 if ((tmp > 4000) && (tmp < 10000)) {
1026 index = i;
1027 break;
1028 }
1029 }
1030 lpphy_stop_ddfs(dev);
1031 return index;
1032 }
1033
1034 static u32 lpphy_qdiv_roundup(u32 dividend, u32 divisor, u8 precision)
1035 {
1036 u32 quotient, remainder, rbit, roundup, tmp;
1037
1038 if (divisor == 0)
1039 return 0;
1040
1041 quotient = dividend / divisor;
1042 remainder = dividend % divisor;
1043
1044 rbit = divisor & 0x1;
1045 roundup = (divisor >> 1) + rbit;
1046
1047 while (precision != 0) {
1048 tmp = remainder - roundup;
1049 quotient <<= 1;
1050 if (remainder >= roundup)
1051 remainder = (tmp << 1) + rbit;
1052 else
1053 remainder <<= 1;
1054 precision--;
1055 }
1056
1057 if (remainder >= roundup)
1058 quotient++;
1059
1060 return quotient;
1061 }
1062
1063 /* Read the TX power control mode from hardware. */
1064 static void lpphy_read_tx_pctl_mode_from_hardware(struct b43_wldev *dev)
1065 {
1066 struct b43_phy_lp *lpphy = dev->phy.lp;
1067 u16 ctl;
1068
1069 ctl = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_CMD);
1070 switch (ctl & B43_LPPHY_TX_PWR_CTL_CMD_MODE) {
1071 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF:
1072 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_OFF;
1073 break;
1074 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW:
1075 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_SW;
1076 break;
1077 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW:
1078 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_HW;
1079 break;
1080 default:
1081 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_UNKNOWN;
1082 B43_WARN_ON(1);
1083 break;
1084 }
1085 }
1086
1087 /* Set the TX power control mode in hardware. */
1088 static void lpphy_write_tx_pctl_mode_to_hardware(struct b43_wldev *dev)
1089 {
1090 struct b43_phy_lp *lpphy = dev->phy.lp;
1091 u16 ctl;
1092
1093 switch (lpphy->txpctl_mode) {
1094 case B43_LPPHY_TXPCTL_OFF:
1095 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF;
1096 break;
1097 case B43_LPPHY_TXPCTL_HW:
1098 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW;
1099 break;
1100 case B43_LPPHY_TXPCTL_SW:
1101 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW;
1102 break;
1103 default:
1104 ctl = 0;
1105 B43_WARN_ON(1);
1106 }
1107 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1108 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE, ctl);
1109 }
1110
1111 static void lpphy_set_tx_power_control(struct b43_wldev *dev,
1112 enum b43_lpphy_txpctl_mode mode)
1113 {
1114 struct b43_phy_lp *lpphy = dev->phy.lp;
1115 enum b43_lpphy_txpctl_mode oldmode;
1116
1117 lpphy_read_tx_pctl_mode_from_hardware(dev);
1118 oldmode = lpphy->txpctl_mode;
1119 if (oldmode == mode)
1120 return;
1121 lpphy->txpctl_mode = mode;
1122
1123 if (oldmode == B43_LPPHY_TXPCTL_HW) {
1124 //TODO Update TX Power NPT
1125 //TODO Clear all TX Power offsets
1126 } else {
1127 if (mode == B43_LPPHY_TXPCTL_HW) {
1128 //TODO Recalculate target TX power
1129 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1130 0xFF80, lpphy->tssi_idx);
1131 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM,
1132 0x8FFF, ((u16)lpphy->tssi_npt << 16));
1133 //TODO Set "TSSI Transmit Count" variable to total transmitted frame count
1134 //TODO Disable TX gain override
1135 lpphy->tx_pwr_idx_over = -1;
1136 }
1137 }
1138 if (dev->phy.rev >= 2) {
1139 if (mode == B43_LPPHY_TXPCTL_HW)
1140 b43_phy_maskset(dev, B43_PHY_OFDM(0xD0), 0xFD, 0x2);
1141 else
1142 b43_phy_maskset(dev, B43_PHY_OFDM(0xD0), 0xFD, 0);
1143 }
1144 lpphy_write_tx_pctl_mode_to_hardware(dev);
1145 }
1146
1147 static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
1148 unsigned int new_channel);
1149
1150 static void lpphy_rev0_1_rc_calib(struct b43_wldev *dev)
1151 {
1152 struct b43_phy_lp *lpphy = dev->phy.lp;
1153 struct lpphy_iq_est iq_est;
1154 struct lpphy_tx_gains tx_gains;
1155 static const u32 ideal_pwr_table[21] = {
1156 0x10000, 0x10557, 0x10e2d, 0x113e0, 0x10f22, 0x0ff64,
1157 0x0eda2, 0x0e5d4, 0x0efd1, 0x0fbe8, 0x0b7b8, 0x04b35,
1158 0x01a5e, 0x00a0b, 0x00444, 0x001fd, 0x000ff, 0x00088,
1159 0x0004c, 0x0002c, 0x0001a,
1160 };
1161 bool old_txg_ovr;
1162 u8 old_bbmult;
1163 u16 old_rf_ovr, old_rf_ovrval, old_afe_ovr, old_afe_ovrval,
1164 old_rf2_ovr, old_rf2_ovrval, old_phy_ctl;
1165 enum b43_lpphy_txpctl_mode old_txpctl;
1166 u32 normal_pwr, ideal_pwr, mean_sq_pwr, tmp = 0, mean_sq_pwr_min = 0;
1167 int loopback, i, j, inner_sum, err;
1168
1169 memset(&iq_est, 0, sizeof(iq_est));
1170
1171 err = b43_lpphy_op_switch_channel(dev, 7);
1172 if (err) {
1173 b43dbg(dev->wl,
1174 "RC calib: Failed to switch to channel 7, error = %d",
1175 err);
1176 }
1177 old_txg_ovr = !!(b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) & 0x40);
1178 old_bbmult = lpphy_get_bb_mult(dev);
1179 if (old_txg_ovr)
1180 tx_gains = lpphy_get_tx_gains(dev);
1181 old_rf_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_0);
1182 old_rf_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_VAL_0);
1183 old_afe_ovr = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR);
1184 old_afe_ovrval = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVRVAL);
1185 old_rf2_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2);
1186 old_rf2_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2_VAL);
1187 old_phy_ctl = b43_phy_read(dev, B43_LPPHY_LP_PHY_CTL);
1188 lpphy_read_tx_pctl_mode_from_hardware(dev);
1189 old_txpctl = lpphy->txpctl_mode;
1190
1191 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
1192 lpphy_disable_crs(dev, true);
1193 loopback = lpphy_loopback(dev);
1194 if (loopback == -1)
1195 goto finish;
1196 lpphy_set_rx_gain_by_index(dev, loopback);
1197 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFFBF, 0x40);
1198 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFF8, 0x1);
1199 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFC7, 0x8);
1200 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F, 0xC0);
1201 for (i = 128; i <= 159; i++) {
1202 b43_radio_write(dev, B2062_N_RXBB_CALIB2, i);
1203 inner_sum = 0;
1204 for (j = 5; j <= 25; j++) {
1205 lpphy_run_ddfs(dev, 1, 1, j, j, 0);
1206 if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est)))
1207 goto finish;
1208 mean_sq_pwr = iq_est.i_pwr + iq_est.q_pwr;
1209 if (j == 5)
1210 tmp = mean_sq_pwr;
1211 ideal_pwr = ((ideal_pwr_table[j-5] >> 3) + 1) >> 1;
1212 normal_pwr = lpphy_qdiv_roundup(mean_sq_pwr, tmp, 12);
1213 mean_sq_pwr = ideal_pwr - normal_pwr;
1214 mean_sq_pwr *= mean_sq_pwr;
1215 inner_sum += mean_sq_pwr;
1216 if ((i = 128) || (inner_sum < mean_sq_pwr_min)) {
1217 lpphy->rc_cap = i;
1218 mean_sq_pwr_min = inner_sum;
1219 }
1220 }
1221 }
1222 lpphy_stop_ddfs(dev);
1223
1224 finish:
1225 lpphy_restore_crs(dev, true);
1226 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, old_rf_ovrval);
1227 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, old_rf_ovr);
1228 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, old_afe_ovrval);
1229 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, old_afe_ovr);
1230 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, old_rf2_ovrval);
1231 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, old_rf2_ovr);
1232 b43_phy_write(dev, B43_LPPHY_LP_PHY_CTL, old_phy_ctl);
1233
1234 lpphy_set_bb_mult(dev, old_bbmult);
1235 if (old_txg_ovr) {
1236 /*
1237 * SPEC FIXME: The specs say "get_tx_gains" here, which is
1238 * illogical. According to lwfinger, vendor driver v4.150.10.5
1239 * has a Set here, while v4.174.64.19 has a Get - regression in
1240 * the vendor driver? This should be tested this once the code
1241 * is testable.
1242 */
1243 lpphy_set_tx_gains(dev, tx_gains);
1244 }
1245 lpphy_set_tx_power_control(dev, old_txpctl);
1246 if (lpphy->rc_cap)
1247 lpphy_set_rc_cap(dev);
1248 }
1249
1250 static void lpphy_rev2plus_rc_calib(struct b43_wldev *dev)
1251 {
1252 struct ssb_bus *bus = dev->dev->bus;
1253 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
1254 u8 tmp = b43_radio_read(dev, B2063_RX_BB_SP8) & 0xFF;
1255 int i;
1256
1257 b43_radio_write(dev, B2063_RX_BB_SP8, 0x0);
1258 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1259 b43_radio_mask(dev, B2063_PLL_SP1, 0xF7);
1260 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C);
1261 b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x15);
1262 b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x70);
1263 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x52);
1264 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1);
1265 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7D);
1266
1267 for (i = 0; i < 10000; i++) {
1268 if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)
1269 break;
1270 msleep(1);
1271 }
1272
1273 if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2))
1274 b43_radio_write(dev, B2063_RX_BB_SP8, tmp);
1275
1276 tmp = b43_radio_read(dev, B2063_TX_BB_SP3) & 0xFF;
1277
1278 b43_radio_write(dev, B2063_TX_BB_SP3, 0x0);
1279 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1280 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C);
1281 b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x55);
1282 b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x76);
1283
1284 if (crystal_freq == 24000000) {
1285 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0xFC);
1286 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x0);
1287 } else {
1288 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x13);
1289 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1);
1290 }
1291
1292 b43_radio_write(dev, B2063_PA_SP7, 0x7D);
1293
1294 for (i = 0; i < 10000; i++) {
1295 if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)
1296 break;
1297 msleep(1);
1298 }
1299
1300 if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2))
1301 b43_radio_write(dev, B2063_TX_BB_SP3, tmp);
1302
1303 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1304 }
1305
1306 static void lpphy_calibrate_rc(struct b43_wldev *dev)
1307 {
1308 struct b43_phy_lp *lpphy = dev->phy.lp;
1309
1310 if (dev->phy.rev >= 2) {
1311 lpphy_rev2plus_rc_calib(dev);
1312 } else if (!lpphy->rc_cap) {
1313 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1314 lpphy_rev0_1_rc_calib(dev);
1315 } else {
1316 lpphy_set_rc_cap(dev);
1317 }
1318 }
1319
1320 static void lpphy_set_tx_power_by_index(struct b43_wldev *dev, u8 index)
1321 {
1322 struct b43_phy_lp *lpphy = dev->phy.lp;
1323
1324 lpphy->tx_pwr_idx_over = index;
1325 if (lpphy->txpctl_mode != B43_LPPHY_TXPCTL_OFF)
1326 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_SW);
1327
1328 //TODO
1329 }
1330
1331 static void lpphy_btcoex_override(struct b43_wldev *dev)
1332 {
1333 b43_write16(dev, B43_MMIO_BTCOEX_CTL, 0x3);
1334 b43_write16(dev, B43_MMIO_BTCOEX_TXCTL, 0xFF);
1335 }
1336
1337 static void lpphy_pr41573_workaround(struct b43_wldev *dev)
1338 {
1339 struct b43_phy_lp *lpphy = dev->phy.lp;
1340 u32 *saved_tab;
1341 const unsigned int saved_tab_size = 256;
1342 enum b43_lpphy_txpctl_mode txpctl_mode;
1343 s8 tx_pwr_idx_over;
1344 u16 tssi_npt, tssi_idx;
1345
1346 saved_tab = kcalloc(saved_tab_size, sizeof(saved_tab[0]), GFP_KERNEL);
1347 if (!saved_tab) {
1348 b43err(dev->wl, "PR41573 failed. Out of memory!\n");
1349 return;
1350 }
1351
1352 lpphy_read_tx_pctl_mode_from_hardware(dev);
1353 txpctl_mode = lpphy->txpctl_mode;
1354 tx_pwr_idx_over = lpphy->tx_pwr_idx_over;
1355 tssi_npt = lpphy->tssi_npt;
1356 tssi_idx = lpphy->tssi_idx;
1357
1358 if (dev->phy.rev < 2) {
1359 b43_lptab_read_bulk(dev, B43_LPTAB32(10, 0x140),
1360 saved_tab_size, saved_tab);
1361 } else {
1362 b43_lptab_read_bulk(dev, B43_LPTAB32(7, 0x140),
1363 saved_tab_size, saved_tab);
1364 }
1365 //TODO
1366
1367 kfree(saved_tab);
1368 }
1369
1370 static void lpphy_calibration(struct b43_wldev *dev)
1371 {
1372 struct b43_phy_lp *lpphy = dev->phy.lp;
1373 enum b43_lpphy_txpctl_mode saved_pctl_mode;
1374
1375 b43_mac_suspend(dev);
1376
1377 lpphy_btcoex_override(dev);
1378 lpphy_read_tx_pctl_mode_from_hardware(dev);
1379 saved_pctl_mode = lpphy->txpctl_mode;
1380 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
1381 //TODO Perform transmit power table I/Q LO calibration
1382 if ((dev->phy.rev == 0) && (saved_pctl_mode != B43_LPPHY_TXPCTL_OFF))
1383 lpphy_pr41573_workaround(dev);
1384 //TODO If a full calibration has not been performed on this channel yet, perform PAPD TX-power calibration
1385 lpphy_set_tx_power_control(dev, saved_pctl_mode);
1386 //TODO Perform I/Q calibration with a single control value set
1387
1388 b43_mac_enable(dev);
1389 }
1390
1391 static void lpphy_set_tssi_mux(struct b43_wldev *dev, enum tssi_mux_mode mode)
1392 {
1393 if (mode != TSSI_MUX_EXT) {
1394 b43_radio_set(dev, B2063_PA_SP1, 0x2);
1395 b43_phy_set(dev, B43_PHY_OFDM(0xF3), 0x1000);
1396 b43_radio_write(dev, B2063_PA_CTL10, 0x51);
1397 if (mode == TSSI_MUX_POSTPA) {
1398 b43_radio_mask(dev, B2063_PA_SP1, 0xFFFE);
1399 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFC7);
1400 } else {
1401 b43_radio_maskset(dev, B2063_PA_SP1, 0xFFFE, 0x1);
1402 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL_OVRVAL,
1403 0xFFC7, 0x20);
1404 }
1405 } else {
1406 B43_WARN_ON(1);
1407 }
1408 }
1409
1410 static void lpphy_tx_pctl_init_hw(struct b43_wldev *dev)
1411 {
1412 u16 tmp;
1413 int i;
1414
1415 //SPEC TODO Call LP PHY Clear TX Power offsets
1416 for (i = 0; i < 64; i++) {
1417 if (dev->phy.rev >= 2)
1418 b43_lptab_write(dev, B43_LPTAB32(7, i + 1), i);
1419 else
1420 b43_lptab_write(dev, B43_LPTAB32(10, i + 1), i);
1421 }
1422
1423 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xFF00, 0xFF);
1424 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0x8FFF, 0x5000);
1425 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI, 0xFFC0, 0x1F);
1426 if (dev->phy.rev < 2) {
1427 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xEFFF);
1428 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xDFFF, 0x2000);
1429 } else {
1430 b43_phy_mask(dev, B43_PHY_OFDM(0x103), 0xFFFE);
1431 b43_phy_maskset(dev, B43_PHY_OFDM(0x103), 0xFFFB, 0x4);
1432 b43_phy_maskset(dev, B43_PHY_OFDM(0x103), 0xFFEF, 0x10);
1433 b43_radio_maskset(dev, B2063_IQ_CALIB_CTL2, 0xF3, 0x1);
1434 lpphy_set_tssi_mux(dev, TSSI_MUX_POSTPA);
1435 }
1436 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI, 0x7FFF, 0x8000);
1437 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xFF);
1438 b43_phy_write(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xA);
1439 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1440 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE,
1441 B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF);
1442 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xF8FF);
1443 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1444 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE,
1445 B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW);
1446
1447 if (dev->phy.rev < 2) {
1448 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF, 0x1000);
1449 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xEFFF);
1450 } else {
1451 lpphy_set_tx_power_by_index(dev, 0x7F);
1452 }
1453
1454 b43_dummy_transmission(dev, true, true);
1455
1456 tmp = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_STAT);
1457 if (tmp & 0x8000) {
1458 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI,
1459 0xFFC0, (tmp & 0xFF) - 32);
1460 }
1461
1462 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF);
1463
1464 // (SPEC?) TODO Set "Target TX frequency" variable to 0
1465 // SPEC FIXME "Set BB Multiplier to 0xE000" impossible - bb_mult is u8!
1466 }
1467
1468 static void lpphy_tx_pctl_init_sw(struct b43_wldev *dev)
1469 {
1470 struct lpphy_tx_gains gains;
1471
1472 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1473 gains.gm = 4;
1474 gains.pad = 12;
1475 gains.pga = 12;
1476 gains.dac = 0;
1477 } else {
1478 gains.gm = 7;
1479 gains.pad = 14;
1480 gains.pga = 15;
1481 gains.dac = 0;
1482 }
1483 lpphy_set_tx_gains(dev, gains);
1484 lpphy_set_bb_mult(dev, 150);
1485 }
1486
1487 /* Initialize TX power control */
1488 static void lpphy_tx_pctl_init(struct b43_wldev *dev)
1489 {
1490 if (0/*FIXME HWPCTL capable */) {
1491 lpphy_tx_pctl_init_hw(dev);
1492 } else { /* This device is only software TX power control capable. */
1493 lpphy_tx_pctl_init_sw(dev);
1494 }
1495 }
1496
1497 static u16 b43_lpphy_op_read(struct b43_wldev *dev, u16 reg)
1498 {
1499 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1500 return b43_read16(dev, B43_MMIO_PHY_DATA);
1501 }
1502
1503 static void b43_lpphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
1504 {
1505 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1506 b43_write16(dev, B43_MMIO_PHY_DATA, value);
1507 }
1508
1509 static u16 b43_lpphy_op_radio_read(struct b43_wldev *dev, u16 reg)
1510 {
1511 /* Register 1 is a 32-bit register. */
1512 B43_WARN_ON(reg == 1);
1513 /* LP-PHY needs a special bit set for read access */
1514 if (dev->phy.rev < 2) {
1515 if (reg != 0x4001)
1516 reg |= 0x100;
1517 } else
1518 reg |= 0x200;
1519
1520 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1521 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
1522 }
1523
1524 static void b43_lpphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
1525 {
1526 /* Register 1 is a 32-bit register. */
1527 B43_WARN_ON(reg == 1);
1528
1529 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1530 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
1531 }
1532
1533 static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev,
1534 bool blocked)
1535 {
1536 //TODO
1537 }
1538
1539 struct b206x_channel {
1540 u8 channel;
1541 u16 freq;
1542 u8 data[12];
1543 };
1544
1545 static const struct b206x_channel b2062_chantbl[] = {
1546 { .channel = 1, .freq = 2412, .data[0] = 0xFF, .data[1] = 0xFF,
1547 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1548 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1549 { .channel = 2, .freq = 2417, .data[0] = 0xFF, .data[1] = 0xFF,
1550 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1551 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1552 { .channel = 3, .freq = 2422, .data[0] = 0xFF, .data[1] = 0xFF,
1553 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1554 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1555 { .channel = 4, .freq = 2427, .data[0] = 0xFF, .data[1] = 0xFF,
1556 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1557 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1558 { .channel = 5, .freq = 2432, .data[0] = 0xFF, .data[1] = 0xFF,
1559 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1560 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1561 { .channel = 6, .freq = 2437, .data[0] = 0xFF, .data[1] = 0xFF,
1562 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1563 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1564 { .channel = 7, .freq = 2442, .data[0] = 0xFF, .data[1] = 0xFF,
1565 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1566 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1567 { .channel = 8, .freq = 2447, .data[0] = 0xFF, .data[1] = 0xFF,
1568 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1569 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1570 { .channel = 9, .freq = 2452, .data[0] = 0xFF, .data[1] = 0xFF,
1571 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1572 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1573 { .channel = 10, .freq = 2457, .data[0] = 0xFF, .data[1] = 0xFF,
1574 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1575 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1576 { .channel = 11, .freq = 2462, .data[0] = 0xFF, .data[1] = 0xFF,
1577 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1578 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1579 { .channel = 12, .freq = 2467, .data[0] = 0xFF, .data[1] = 0xFF,
1580 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1581 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1582 { .channel = 13, .freq = 2472, .data[0] = 0xFF, .data[1] = 0xFF,
1583 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1584 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1585 { .channel = 14, .freq = 2484, .data[0] = 0xFF, .data[1] = 0xFF,
1586 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1587 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1588 { .channel = 34, .freq = 5170, .data[0] = 0x00, .data[1] = 0x22,
1589 .data[2] = 0x20, .data[3] = 0x84, .data[4] = 0x3C, .data[5] = 0x77,
1590 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1591 { .channel = 38, .freq = 5190, .data[0] = 0x00, .data[1] = 0x11,
1592 .data[2] = 0x10, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1593 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1594 { .channel = 42, .freq = 5210, .data[0] = 0x00, .data[1] = 0x11,
1595 .data[2] = 0x10, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1596 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1597 { .channel = 46, .freq = 5230, .data[0] = 0x00, .data[1] = 0x00,
1598 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1599 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1600 { .channel = 36, .freq = 5180, .data[0] = 0x00, .data[1] = 0x11,
1601 .data[2] = 0x20, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1602 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1603 { .channel = 40, .freq = 5200, .data[0] = 0x00, .data[1] = 0x11,
1604 .data[2] = 0x10, .data[3] = 0x84, .data[4] = 0x3C, .data[5] = 0x77,
1605 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1606 { .channel = 44, .freq = 5220, .data[0] = 0x00, .data[1] = 0x11,
1607 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1608 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1609 { .channel = 48, .freq = 5240, .data[0] = 0x00, .data[1] = 0x00,
1610 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1611 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1612 { .channel = 52, .freq = 5260, .data[0] = 0x00, .data[1] = 0x00,
1613 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1614 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1615 { .channel = 56, .freq = 5280, .data[0] = 0x00, .data[1] = 0x00,
1616 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1617 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1618 { .channel = 60, .freq = 5300, .data[0] = 0x00, .data[1] = 0x00,
1619 .data[2] = 0x00, .data[3] = 0x63, .data[4] = 0x3C, .data[5] = 0x77,
1620 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1621 { .channel = 64, .freq = 5320, .data[0] = 0x00, .data[1] = 0x00,
1622 .data[2] = 0x00, .data[3] = 0x62, .data[4] = 0x3C, .data[5] = 0x77,
1623 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1624 { .channel = 100, .freq = 5500, .data[0] = 0x00, .data[1] = 0x00,
1625 .data[2] = 0x00, .data[3] = 0x30, .data[4] = 0x3C, .data[5] = 0x77,
1626 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1627 { .channel = 104, .freq = 5520, .data[0] = 0x00, .data[1] = 0x00,
1628 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
1629 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1630 { .channel = 108, .freq = 5540, .data[0] = 0x00, .data[1] = 0x00,
1631 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
1632 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1633 { .channel = 112, .freq = 5560, .data[0] = 0x00, .data[1] = 0x00,
1634 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
1635 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1636 { .channel = 116, .freq = 5580, .data[0] = 0x00, .data[1] = 0x00,
1637 .data[2] = 0x00, .data[3] = 0x10, .data[4] = 0x3C, .data[5] = 0x77,
1638 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1639 { .channel = 120, .freq = 5600, .data[0] = 0x00, .data[1] = 0x00,
1640 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1641 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1642 { .channel = 124, .freq = 5620, .data[0] = 0x00, .data[1] = 0x00,
1643 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1644 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1645 { .channel = 128, .freq = 5640, .data[0] = 0x00, .data[1] = 0x00,
1646 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1647 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1648 { .channel = 132, .freq = 5660, .data[0] = 0x00, .data[1] = 0x00,
1649 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1650 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1651 { .channel = 136, .freq = 5680, .data[0] = 0x00, .data[1] = 0x00,
1652 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1653 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1654 { .channel = 140, .freq = 5700, .data[0] = 0x00, .data[1] = 0x00,
1655 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1656 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1657 { .channel = 149, .freq = 5745, .data[0] = 0x00, .data[1] = 0x00,
1658 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1659 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1660 { .channel = 153, .freq = 5765, .data[0] = 0x00, .data[1] = 0x00,
1661 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1662 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1663 { .channel = 157, .freq = 5785, .data[0] = 0x00, .data[1] = 0x00,
1664 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1665 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1666 { .channel = 161, .freq = 5805, .data[0] = 0x00, .data[1] = 0x00,
1667 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1668 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1669 { .channel = 165, .freq = 5825, .data[0] = 0x00, .data[1] = 0x00,
1670 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1671 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1672 { .channel = 184, .freq = 4920, .data[0] = 0x55, .data[1] = 0x77,
1673 .data[2] = 0x90, .data[3] = 0xF7, .data[4] = 0x3C, .data[5] = 0x77,
1674 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1675 { .channel = 188, .freq = 4940, .data[0] = 0x44, .data[1] = 0x77,
1676 .data[2] = 0x80, .data[3] = 0xE7, .data[4] = 0x3C, .data[5] = 0x77,
1677 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1678 { .channel = 192, .freq = 4960, .data[0] = 0x44, .data[1] = 0x66,
1679 .data[2] = 0x80, .data[3] = 0xE7, .data[4] = 0x3C, .data[5] = 0x77,
1680 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1681 { .channel = 196, .freq = 4980, .data[0] = 0x33, .data[1] = 0x66,
1682 .data[2] = 0x70, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
1683 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1684 { .channel = 200, .freq = 5000, .data[0] = 0x22, .data[1] = 0x55,
1685 .data[2] = 0x60, .data[3] = 0xD7, .data[4] = 0x3C, .data[5] = 0x77,
1686 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1687 { .channel = 204, .freq = 5020, .data[0] = 0x22, .data[1] = 0x55,
1688 .data[2] = 0x60, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
1689 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1690 { .channel = 208, .freq = 5040, .data[0] = 0x22, .data[1] = 0x44,
1691 .data[2] = 0x50, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
1692 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1693 { .channel = 212, .freq = 5060, .data[0] = 0x11, .data[1] = 0x44,
1694 .data[2] = 0x50, .data[3] = 0xA5, .data[4] = 0x3C, .data[5] = 0x77,
1695 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1696 { .channel = 216, .freq = 5080, .data[0] = 0x00, .data[1] = 0x44,
1697 .data[2] = 0x40, .data[3] = 0xB6, .data[4] = 0x3C, .data[5] = 0x77,
1698 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1699 };
1700
1701 static const struct b206x_channel b2063_chantbl[] = {
1702 { .channel = 1, .freq = 2412, .data[0] = 0x6F, .data[1] = 0x3C,
1703 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1704 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1705 .data[10] = 0x80, .data[11] = 0x70, },
1706 { .channel = 2, .freq = 2417, .data[0] = 0x6F, .data[1] = 0x3C,
1707 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1708 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1709 .data[10] = 0x80, .data[11] = 0x70, },
1710 { .channel = 3, .freq = 2422, .data[0] = 0x6F, .data[1] = 0x3C,
1711 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1712 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1713 .data[10] = 0x80, .data[11] = 0x70, },
1714 { .channel = 4, .freq = 2427, .data[0] = 0x6F, .data[1] = 0x2C,
1715 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1716 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1717 .data[10] = 0x80, .data[11] = 0x70, },
1718 { .channel = 5, .freq = 2432, .data[0] = 0x6F, .data[1] = 0x2C,
1719 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1720 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1721 .data[10] = 0x80, .data[11] = 0x70, },
1722 { .channel = 6, .freq = 2437, .data[0] = 0x6F, .data[1] = 0x2C,
1723 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1724 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1725 .data[10] = 0x80, .data[11] = 0x70, },
1726 { .channel = 7, .freq = 2442, .data[0] = 0x6F, .data[1] = 0x2C,
1727 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1728 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1729 .data[10] = 0x80, .data[11] = 0x70, },
1730 { .channel = 8, .freq = 2447, .data[0] = 0x6F, .data[1] = 0x2C,
1731 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1732 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1733 .data[10] = 0x80, .data[11] = 0x70, },
1734 { .channel = 9, .freq = 2452, .data[0] = 0x6F, .data[1] = 0x1C,
1735 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1736 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1737 .data[10] = 0x80, .data[11] = 0x70, },
1738 { .channel = 10, .freq = 2457, .data[0] = 0x6F, .data[1] = 0x1C,
1739 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1740 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1741 .data[10] = 0x80, .data[11] = 0x70, },
1742 { .channel = 11, .freq = 2462, .data[0] = 0x6E, .data[1] = 0x1C,
1743 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1744 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1745 .data[10] = 0x80, .data[11] = 0x70, },
1746 { .channel = 12, .freq = 2467, .data[0] = 0x6E, .data[1] = 0x1C,
1747 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1748 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1749 .data[10] = 0x80, .data[11] = 0x70, },
1750 { .channel = 13, .freq = 2472, .data[0] = 0x6E, .data[1] = 0x1C,
1751 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1752 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1753 .data[10] = 0x80, .data[11] = 0x70, },
1754 { .channel = 14, .freq = 2484, .data[0] = 0x6E, .data[1] = 0x0C,
1755 .data[2] = 0x0C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1756 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1757 .data[10] = 0x80, .data[11] = 0x70, },
1758 { .channel = 34, .freq = 5170, .data[0] = 0x6A, .data[1] = 0x0C,
1759 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x02, .data[5] = 0x05,
1760 .data[6] = 0x0D, .data[7] = 0x0D, .data[8] = 0x77, .data[9] = 0x80,
1761 .data[10] = 0x20, .data[11] = 0x00, },
1762 { .channel = 36, .freq = 5180, .data[0] = 0x6A, .data[1] = 0x0C,
1763 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x05,
1764 .data[6] = 0x0D, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x80,
1765 .data[10] = 0x20, .data[11] = 0x00, },
1766 { .channel = 38, .freq = 5190, .data[0] = 0x6A, .data[1] = 0x0C,
1767 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
1768 .data[6] = 0x0C, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x80,
1769 .data[10] = 0x20, .data[11] = 0x00, },
1770 { .channel = 40, .freq = 5200, .data[0] = 0x69, .data[1] = 0x0C,
1771 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
1772 .data[6] = 0x0C, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x70,
1773 .data[10] = 0x20, .data[11] = 0x00, },
1774 { .channel = 42, .freq = 5210, .data[0] = 0x69, .data[1] = 0x0C,
1775 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
1776 .data[6] = 0x0B, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x70,
1777 .data[10] = 0x20, .data[11] = 0x00, },
1778 { .channel = 44, .freq = 5220, .data[0] = 0x69, .data[1] = 0x0C,
1779 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x04,
1780 .data[6] = 0x0B, .data[7] = 0x0B, .data[8] = 0x77, .data[9] = 0x60,
1781 .data[10] = 0x20, .data[11] = 0x00, },
1782 { .channel = 46, .freq = 5230, .data[0] = 0x69, .data[1] = 0x0C,
1783 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x03,
1784 .data[6] = 0x0A, .data[7] = 0x0B, .data[8] = 0x77, .data[9] = 0x60,
1785 .data[10] = 0x20, .data[11] = 0x00, },
1786 { .channel = 48, .freq = 5240, .data[0] = 0x69, .data[1] = 0x0C,
1787 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x03,
1788 .data[6] = 0x0A, .data[7] = 0x0A, .data[8] = 0x77, .data[9] = 0x60,
1789 .data[10] = 0x20, .data[11] = 0x00, },
1790 { .channel = 52, .freq = 5260, .data[0] = 0x68, .data[1] = 0x0C,
1791 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x02,
1792 .data[6] = 0x09, .data[7] = 0x09, .data[8] = 0x77, .data[9] = 0x60,
1793 .data[10] = 0x20, .data[11] = 0x00, },
1794 { .channel = 56, .freq = 5280, .data[0] = 0x68, .data[1] = 0x0C,
1795 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x01,
1796 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
1797 .data[10] = 0x10, .data[11] = 0x00, },
1798 { .channel = 60, .freq = 5300, .data[0] = 0x68, .data[1] = 0x0C,
1799 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x01,
1800 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
1801 .data[10] = 0x10, .data[11] = 0x00, },
1802 { .channel = 64, .freq = 5320, .data[0] = 0x67, .data[1] = 0x0C,
1803 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1804 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
1805 .data[10] = 0x10, .data[11] = 0x00, },
1806 { .channel = 100, .freq = 5500, .data[0] = 0x64, .data[1] = 0x0C,
1807 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1808 .data[6] = 0x02, .data[7] = 0x01, .data[8] = 0x77, .data[9] = 0x20,
1809 .data[10] = 0x00, .data[11] = 0x00, },
1810 { .channel = 104, .freq = 5520, .data[0] = 0x64, .data[1] = 0x0C,
1811 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1812 .data[6] = 0x01, .data[7] = 0x01, .data[8] = 0x77, .data[9] = 0x20,
1813 .data[10] = 0x00, .data[11] = 0x00, },
1814 { .channel = 108, .freq = 5540, .data[0] = 0x63, .data[1] = 0x0C,
1815 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1816 .data[6] = 0x01, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
1817 .data[10] = 0x00, .data[11] = 0x00, },
1818 { .channel = 112, .freq = 5560, .data[0] = 0x63, .data[1] = 0x0C,
1819 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1820 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
1821 .data[10] = 0x00, .data[11] = 0x00, },
1822 { .channel = 116, .freq = 5580, .data[0] = 0x62, .data[1] = 0x0C,
1823 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1824 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
1825 .data[10] = 0x00, .data[11] = 0x00, },
1826 { .channel = 120, .freq = 5600, .data[0] = 0x62, .data[1] = 0x0C,
1827 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1828 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1829 .data[10] = 0x00, .data[11] = 0x00, },
1830 { .channel = 124, .freq = 5620, .data[0] = 0x62, .data[1] = 0x0C,
1831 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1832 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1833 .data[10] = 0x00, .data[11] = 0x00, },
1834 { .channel = 128, .freq = 5640, .data[0] = 0x61, .data[1] = 0x0C,
1835 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1836 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1837 .data[10] = 0x00, .data[11] = 0x00, },
1838 { .channel = 132, .freq = 5660, .data[0] = 0x61, .data[1] = 0x0C,
1839 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1840 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1841 .data[10] = 0x00, .data[11] = 0x00, },
1842 { .channel = 136, .freq = 5680, .data[0] = 0x61, .data[1] = 0x0C,
1843 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1844 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1845 .data[10] = 0x00, .data[11] = 0x00, },
1846 { .channel = 140, .freq = 5700, .data[0] = 0x60, .data[1] = 0x0C,
1847 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1848 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1849 .data[10] = 0x00, .data[11] = 0x00, },
1850 { .channel = 149, .freq = 5745, .data[0] = 0x60, .data[1] = 0x0C,
1851 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1852 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1853 .data[10] = 0x00, .data[11] = 0x00, },
1854 { .channel = 153, .freq = 5765, .data[0] = 0x60, .data[1] = 0x0C,
1855 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1856 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1857 .data[10] = 0x00, .data[11] = 0x00, },
1858 { .channel = 157, .freq = 5785, .data[0] = 0x60, .data[1] = 0x0C,
1859 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1860 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1861 .data[10] = 0x00, .data[11] = 0x00, },
1862 { .channel = 161, .freq = 5805, .data[0] = 0x60, .data[1] = 0x0C,
1863 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1864 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1865 .data[10] = 0x00, .data[11] = 0x00, },
1866 { .channel = 165, .freq = 5825, .data[0] = 0x60, .data[1] = 0x0C,
1867 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1868 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1869 .data[10] = 0x00, .data[11] = 0x00, },
1870 { .channel = 184, .freq = 4920, .data[0] = 0x6E, .data[1] = 0x0C,
1871 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x09, .data[5] = 0x0E,
1872 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xC0,
1873 .data[10] = 0x50, .data[11] = 0x00, },
1874 { .channel = 188, .freq = 4940, .data[0] = 0x6E, .data[1] = 0x0C,
1875 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x09, .data[5] = 0x0D,
1876 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xB0,
1877 .data[10] = 0x50, .data[11] = 0x00, },
1878 { .channel = 192, .freq = 4960, .data[0] = 0x6E, .data[1] = 0x0C,
1879 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0C,
1880 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xB0,
1881 .data[10] = 0x50, .data[11] = 0x00, },
1882 { .channel = 196, .freq = 4980, .data[0] = 0x6D, .data[1] = 0x0C,
1883 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0C,
1884 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
1885 .data[10] = 0x40, .data[11] = 0x00, },
1886 { .channel = 200, .freq = 5000, .data[0] = 0x6D, .data[1] = 0x0C,
1887 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0B,
1888 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
1889 .data[10] = 0x40, .data[11] = 0x00, },
1890 { .channel = 204, .freq = 5020, .data[0] = 0x6D, .data[1] = 0x0C,
1891 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0A,
1892 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
1893 .data[10] = 0x40, .data[11] = 0x00, },
1894 { .channel = 208, .freq = 5040, .data[0] = 0x6C, .data[1] = 0x0C,
1895 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x07, .data[5] = 0x09,
1896 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
1897 .data[10] = 0x40, .data[11] = 0x00, },
1898 { .channel = 212, .freq = 5060, .data[0] = 0x6C, .data[1] = 0x0C,
1899 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x06, .data[5] = 0x08,
1900 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
1901 .data[10] = 0x40, .data[11] = 0x00, },
1902 { .channel = 216, .freq = 5080, .data[0] = 0x6C, .data[1] = 0x0C,
1903 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x05, .data[5] = 0x08,
1904 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
1905 .data[10] = 0x40, .data[11] = 0x00, },
1906 };
1907
1908 static void lpphy_b2062_reset_pll_bias(struct b43_wldev *dev)
1909 {
1910 struct ssb_bus *bus = dev->dev->bus;
1911
1912 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 0xFF);
1913 udelay(20);
1914 if (bus->chip_id == 0x5354) {
1915 b43_radio_write(dev, B2062_N_COMM1, 4);
1916 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 4);
1917 } else {
1918 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 0);
1919 }
1920 udelay(5);
1921 }
1922
1923 static void lpphy_b2062_vco_calib(struct b43_wldev *dev)
1924 {
1925 b43_phy_write(dev, B2062_S_RFPLL_CTL21, 0x42);
1926 b43_phy_write(dev, B2062_S_RFPLL_CTL21, 0x62);
1927 udelay(200);
1928 }
1929
1930 static int lpphy_b2062_tune(struct b43_wldev *dev,
1931 unsigned int channel)
1932 {
1933 struct b43_phy_lp *lpphy = dev->phy.lp;
1934 struct ssb_bus *bus = dev->dev->bus;
1935 const struct b206x_channel *chandata = NULL;
1936 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
1937 u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8, tmp9;
1938 int i, err = 0;
1939
1940 for (i = 0; i < ARRAY_SIZE(b2062_chantbl); i++) {
1941 if (b2062_chantbl[i].channel == channel) {
1942 chandata = &b2062_chantbl[i];
1943 break;
1944 }
1945 }
1946
1947 if (B43_WARN_ON(!chandata))
1948 return -EINVAL;
1949
1950 b43_radio_set(dev, B2062_S_RFPLL_CTL14, 0x04);
1951 b43_radio_write(dev, B2062_N_LGENA_TUNE0, chandata->data[0]);
1952 b43_radio_write(dev, B2062_N_LGENA_TUNE2, chandata->data[1]);
1953 b43_radio_write(dev, B2062_N_LGENA_TUNE3, chandata->data[2]);
1954 b43_radio_write(dev, B2062_N_TX_TUNE, chandata->data[3]);
1955 b43_radio_write(dev, B2062_S_LGENG_CTL1, chandata->data[4]);
1956 b43_radio_write(dev, B2062_N_LGENA_CTL5, chandata->data[5]);
1957 b43_radio_write(dev, B2062_N_LGENA_CTL6, chandata->data[6]);
1958 b43_radio_write(dev, B2062_N_TX_PGA, chandata->data[7]);
1959 b43_radio_write(dev, B2062_N_TX_PAD, chandata->data[8]);
1960
1961 tmp1 = crystal_freq / 1000;
1962 tmp2 = lpphy->pdiv * 1000;
1963 b43_radio_write(dev, B2062_S_RFPLL_CTL33, 0xCC);
1964 b43_radio_write(dev, B2062_S_RFPLL_CTL34, 0x07);
1965 lpphy_b2062_reset_pll_bias(dev);
1966 tmp3 = tmp2 * channel2freq_lp(channel);
1967 if (channel2freq_lp(channel) < 4000)
1968 tmp3 *= 2;
1969 tmp4 = 48 * tmp1;
1970 tmp6 = tmp3 / tmp4;
1971 tmp7 = tmp3 % tmp4;
1972 b43_radio_write(dev, B2062_S_RFPLL_CTL26, tmp6);
1973 tmp5 = tmp7 * 0x100;
1974 tmp6 = tmp5 / tmp4;
1975 tmp7 = tmp5 % tmp4;
1976 b43_radio_write(dev, B2062_S_RFPLL_CTL27, tmp6);
1977 tmp5 = tmp7 * 0x100;
1978 tmp6 = tmp5 / tmp4;
1979 tmp7 = tmp5 % tmp4;
1980 b43_radio_write(dev, B2062_S_RFPLL_CTL28, tmp6);
1981 tmp5 = tmp7 * 0x100;
1982 tmp6 = tmp5 / tmp4;
1983 tmp7 = tmp5 % tmp4;
1984 b43_radio_write(dev, B2062_S_RFPLL_CTL29, tmp6 + ((2 * tmp7) / tmp4));
1985 tmp8 = b43_phy_read(dev, B2062_S_RFPLL_CTL19);
1986 tmp9 = ((2 * tmp3 * (tmp8 + 1)) + (3 * tmp1)) / (6 * tmp1);
1987 b43_radio_write(dev, B2062_S_RFPLL_CTL23, (tmp9 >> 8) + 16);
1988 b43_radio_write(dev, B2062_S_RFPLL_CTL24, tmp9 & 0xFF);
1989
1990 lpphy_b2062_vco_calib(dev);
1991 if (b43_radio_read(dev, B2062_S_RFPLL_CTL3) & 0x10) {
1992 b43_radio_write(dev, B2062_S_RFPLL_CTL33, 0xFC);
1993 b43_radio_write(dev, B2062_S_RFPLL_CTL34, 0);
1994 lpphy_b2062_reset_pll_bias(dev);
1995 lpphy_b2062_vco_calib(dev);
1996 if (b43_radio_read(dev, B2062_S_RFPLL_CTL3) & 0x10)
1997 err = -EIO;
1998 }
1999
2000 b43_radio_mask(dev, B2062_S_RFPLL_CTL14, ~0x04);
2001 return err;
2002 }
2003
2004
2005 /* This was previously called lpphy_japan_filter */
2006 static void lpphy_set_analog_filter(struct b43_wldev *dev, int channel)
2007 {
2008 struct b43_phy_lp *lpphy = dev->phy.lp;
2009 u16 tmp = (channel == 14); //SPEC FIXME check japanwidefilter!
2010
2011 if (dev->phy.rev < 2) { //SPEC FIXME Isn't this rev0/1-specific?
2012 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFCFF, tmp << 9);
2013 if ((dev->phy.rev == 1) && (lpphy->rc_cap))
2014 lpphy_set_rc_cap(dev);
2015 } else {
2016 b43_radio_write(dev, B2063_TX_BB_SP3, 0x3F);
2017 }
2018 }
2019
2020 static void lpphy_b2063_vco_calib(struct b43_wldev *dev)
2021 {
2022 u16 tmp;
2023
2024 b43_phy_mask(dev, B2063_PLL_SP1, ~0x40);
2025 tmp = b43_phy_read(dev, B2063_PLL_JTAG_CALNRST) & 0xF8;
2026 b43_phy_write(dev, B2063_PLL_JTAG_CALNRST, tmp);
2027 udelay(1);
2028 b43_phy_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x4);
2029 udelay(1);
2030 b43_phy_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x6);
2031 udelay(1);
2032 b43_phy_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x7);
2033 udelay(300);
2034 b43_phy_set(dev, B2063_PLL_SP1, 0x40);
2035 }
2036
2037 static int lpphy_b2063_tune(struct b43_wldev *dev,
2038 unsigned int channel)
2039 {
2040 struct ssb_bus *bus = dev->dev->bus;
2041
2042 static const struct b206x_channel *chandata = NULL;
2043 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
2044 u32 freqref, vco_freq, val1, val2, val3, timeout, timeoutref, count;
2045 u16 old_comm15, scale;
2046 u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
2047 int i, div = (crystal_freq <= 26000000 ? 1 : 2);
2048
2049 for (i = 0; i < ARRAY_SIZE(b2063_chantbl); i++) {
2050 if (b2063_chantbl[i].channel == channel) {
2051 chandata = &b2063_chantbl[i];
2052 break;
2053 }
2054 }
2055
2056 if (B43_WARN_ON(!chandata))
2057 return -EINVAL;
2058
2059 b43_radio_write(dev, B2063_LOGEN_VCOBUF1, chandata->data[0]);
2060 b43_radio_write(dev, B2063_LOGEN_MIXER2, chandata->data[1]);
2061 b43_radio_write(dev, B2063_LOGEN_BUF2, chandata->data[2]);
2062 b43_radio_write(dev, B2063_LOGEN_RCCR1, chandata->data[3]);
2063 b43_radio_write(dev, B2063_A_RX_1ST3, chandata->data[4]);
2064 b43_radio_write(dev, B2063_A_RX_2ND1, chandata->data[5]);
2065 b43_radio_write(dev, B2063_A_RX_2ND4, chandata->data[6]);
2066 b43_radio_write(dev, B2063_A_RX_2ND7, chandata->data[7]);
2067 b43_radio_write(dev, B2063_A_RX_PS6, chandata->data[8]);
2068 b43_radio_write(dev, B2063_TX_RF_CTL2, chandata->data[9]);
2069 b43_radio_write(dev, B2063_TX_RF_CTL5, chandata->data[10]);
2070 b43_radio_write(dev, B2063_PA_CTL11, chandata->data[11]);
2071
2072 old_comm15 = b43_radio_read(dev, B2063_COMM15);
2073 b43_radio_set(dev, B2063_COMM15, 0x1E);
2074
2075 if (chandata->freq > 4000) /* spec says 2484, but 4000 is safer */
2076 vco_freq = chandata->freq << 1;
2077 else
2078 vco_freq = chandata->freq << 2;
2079
2080 freqref = crystal_freq * 3;
2081 val1 = lpphy_qdiv_roundup(crystal_freq, 1000000, 16);
2082 val2 = lpphy_qdiv_roundup(crystal_freq, 1000000 * div, 16);
2083 val3 = lpphy_qdiv_roundup(vco_freq, 3, 16);
2084 timeout = ((((8 * crystal_freq) / (div * 5000000)) + 1) >> 1) - 1;
2085 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB3, 0x2);
2086 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB6,
2087 0xFFF8, timeout >> 2);
2088 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB7,
2089 0xFF9F,timeout << 5);
2090
2091 timeoutref = ((((8 * crystal_freq) / (div * (timeout + 1))) +
2092 999999) / 1000000) + 1;
2093 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB5, timeoutref);
2094
2095 count = lpphy_qdiv_roundup(val3, val2 + 16, 16);
2096 count *= (timeout + 1) * (timeoutref + 1);
2097 count--;
2098 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB7,
2099 0xF0, count >> 8);
2100 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB8, count & 0xFF);
2101
2102 tmp1 = ((val3 * 62500) / freqref) << 4;
2103 tmp2 = ((val3 * 62500) % freqref) << 4;
2104 while (tmp2 >= freqref) {
2105 tmp1++;
2106 tmp2 -= freqref;
2107 }
2108 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG1, 0xFFE0, tmp1 >> 4);
2109 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG2, 0xFE0F, tmp1 << 4);
2110 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG2, 0xFFF0, tmp1 >> 16);
2111 b43_radio_write(dev, B2063_PLL_JTAG_PLL_SG3, (tmp2 >> 8) & 0xFF);
2112 b43_radio_write(dev, B2063_PLL_JTAG_PLL_SG4, tmp2 & 0xFF);
2113
2114 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF1, 0xB9);
2115 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF2, 0x88);
2116 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF3, 0x28);
2117 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF4, 0x63);
2118
2119 tmp3 = ((41 * (val3 - 3000)) /1200) + 27;
2120 tmp4 = lpphy_qdiv_roundup(132000 * tmp1, 8451, 16);
2121
2122 if ((tmp4 + tmp3 - 1) / tmp3 > 60) {
2123 scale = 1;
2124 tmp5 = ((tmp4 + tmp3) / (tmp3 << 1)) - 8;
2125 } else {
2126 scale = 0;
2127 tmp5 = ((tmp4 + (tmp3 >> 1)) / tmp3) - 8;
2128 }
2129 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFC0, tmp5);
2130 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFBF, scale << 6);
2131
2132 tmp6 = lpphy_qdiv_roundup(100 * val1, val3, 16);
2133 tmp6 *= (tmp5 * 8) * (scale + 1);
2134 if (tmp6 > 150)
2135 tmp6 = 0;
2136
2137 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFE0, tmp6);
2138 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFDF, scale << 5);
2139
2140 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFFFB, 0x4);
2141 if (crystal_freq > 26000000)
2142 b43_phy_set(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0x2);
2143 else
2144 b43_phy_mask(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFD);
2145
2146 if (val1 == 45)
2147 b43_phy_set(dev, B2063_PLL_JTAG_PLL_VCO1, 0x2);
2148 else
2149 b43_phy_mask(dev, B2063_PLL_JTAG_PLL_VCO1, 0xFD);
2150
2151 b43_phy_set(dev, B2063_PLL_SP2, 0x3);
2152 udelay(1);
2153 b43_phy_mask(dev, B2063_PLL_SP2, 0xFFFC);
2154 lpphy_b2063_vco_calib(dev);
2155 b43_radio_write(dev, B2063_COMM15, old_comm15);
2156
2157 return 0;
2158 }
2159
2160 static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
2161 unsigned int new_channel)
2162 {
2163 int err;
2164
2165 b43_write16(dev, B43_MMIO_CHANNEL, new_channel);
2166
2167 if (dev->phy.radio_ver == 0x2063) {
2168 err = lpphy_b2063_tune(dev, new_channel);
2169 if (err)
2170 return err;
2171 } else {
2172 err = lpphy_b2062_tune(dev, new_channel);
2173 if (err)
2174 return err;
2175 lpphy_set_analog_filter(dev, new_channel);
2176 lpphy_adjust_gain_table(dev, channel2freq_lp(new_channel));
2177 }
2178
2179 return 0;
2180 }
2181
2182 static int b43_lpphy_op_init(struct b43_wldev *dev)
2183 {
2184 int err;
2185
2186 lpphy_read_band_sprom(dev); //FIXME should this be in prepare_structs?
2187 lpphy_baseband_init(dev);
2188 lpphy_radio_init(dev);
2189 lpphy_calibrate_rc(dev);
2190 err = b43_lpphy_op_switch_channel(dev,
2191 b43_lpphy_op_get_default_chan(dev));
2192 if (err) {
2193 b43dbg(dev->wl, "Switch to init channel failed, error = %d.\n",
2194 err);
2195 }
2196 lpphy_tx_pctl_init(dev);
2197 lpphy_calibration(dev);
2198 //TODO ACI init
2199
2200 return 0;
2201 }
2202
2203 static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
2204 {
2205 //TODO
2206 }
2207
2208 static void b43_lpphy_op_adjust_txpower(struct b43_wldev *dev)
2209 {
2210 //TODO
2211 }
2212
2213 static enum b43_txpwr_result b43_lpphy_op_recalc_txpower(struct b43_wldev *dev,
2214 bool ignore_tssi)
2215 {
2216 //TODO
2217 return B43_TXPWR_RES_DONE;
2218 }
2219
2220 const struct b43_phy_operations b43_phyops_lp = {
2221 .allocate = b43_lpphy_op_allocate,
2222 .free = b43_lpphy_op_free,
2223 .prepare_structs = b43_lpphy_op_prepare_structs,
2224 .init = b43_lpphy_op_init,
2225 .phy_read = b43_lpphy_op_read,
2226 .phy_write = b43_lpphy_op_write,
2227 .radio_read = b43_lpphy_op_radio_read,
2228 .radio_write = b43_lpphy_op_radio_write,
2229 .software_rfkill = b43_lpphy_op_software_rfkill,
2230 .switch_analog = b43_phyop_switch_analog_generic,
2231 .switch_channel = b43_lpphy_op_switch_channel,
2232 .get_default_chan = b43_lpphy_op_get_default_chan,
2233 .set_rx_antenna = b43_lpphy_op_set_rx_antenna,
2234 .recalc_txpower = b43_lpphy_op_recalc_txpower,
2235 .adjust_txpower = b43_lpphy_op_adjust_txpower,
2236 };
AMDTP streaming driver for the Linux FireWire stack (Juju)