?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
rcu: documents rculist_nulls
[firewire-audio.git] / drivers / net / niu.c
blob2c3bb36cda17c12eb3041d886cd7089b3087ff66
1 /* niu.c: Neptune ethernet driver.
2 *
3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
4 */
5
6 #include <linux/module.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/netdevice.h>
11 #include <linux/ethtool.h>
12 #include <linux/etherdevice.h>
13 #include <linux/platform_device.h>
14 #include <linux/delay.h>
15 #include <linux/bitops.h>
16 #include <linux/mii.h>
17 #include <linux/if_ether.h>
18 #include <linux/if_vlan.h>
19 #include <linux/ip.h>
20 #include <linux/in.h>
21 #include <linux/ipv6.h>
22 #include <linux/log2.h>
23 #include <linux/jiffies.h>
24 #include <linux/crc32.h>
25
26 #include <linux/io.h>
27
28 #ifdef CONFIG_SPARC64
29 #include <linux/of_device.h>
30 #endif
31
32 #include "niu.h"
33
34 #define DRV_MODULE_NAME "niu"
35 #define PFX DRV_MODULE_NAME ": "
36 #define DRV_MODULE_VERSION "0.9"
37 #define DRV_MODULE_RELDATE "May 4, 2008"
38
39 static char version[] __devinitdata =
40 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
41
42 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
43 MODULE_DESCRIPTION("NIU ethernet driver");
44 MODULE_LICENSE("GPL");
45 MODULE_VERSION(DRV_MODULE_VERSION);
46
47 #ifndef DMA_44BIT_MASK
48 #define DMA_44BIT_MASK 0x00000fffffffffffULL
49 #endif
50
51 #ifndef readq
52 static u64 readq(void __iomem *reg)
53 {
54 return (((u64)readl(reg + 0x4UL) << 32) |
55 (u64)readl(reg));
56 }
57
58 static void writeq(u64 val, void __iomem *reg)
59 {
60 writel(val & 0xffffffff, reg);
61 writel(val >> 32, reg + 0x4UL);
62 }
63 #endif
64
65 static struct pci_device_id niu_pci_tbl[] = {
66 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
67 {}
68 };
69
70 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
71
72 #define NIU_TX_TIMEOUT (5 * HZ)
73
74 #define nr64(reg) readq(np->regs + (reg))
75 #define nw64(reg, val) writeq((val), np->regs + (reg))
76
77 #define nr64_mac(reg) readq(np->mac_regs + (reg))
78 #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
79
80 #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
81 #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
82
83 #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
84 #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
85
86 #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
87 #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
88
89 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
90
91 static int niu_debug;
92 static int debug = -1;
93 module_param(debug, int, 0);
94 MODULE_PARM_DESC(debug, "NIU debug level");
95
96 #define niudbg(TYPE, f, a...) \
97 do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
98 printk(KERN_DEBUG PFX f, ## a); \
99 } while (0)
100
101 #define niuinfo(TYPE, f, a...) \
102 do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
103 printk(KERN_INFO PFX f, ## a); \
104 } while (0)
105
106 #define niuwarn(TYPE, f, a...) \
107 do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
108 printk(KERN_WARNING PFX f, ## a); \
109 } while (0)
110
111 #define niu_lock_parent(np, flags) \
112 spin_lock_irqsave(&np->parent->lock, flags)
113 #define niu_unlock_parent(np, flags) \
114 spin_unlock_irqrestore(&np->parent->lock, flags)
115
116 static int serdes_init_10g_serdes(struct niu *np);
117
118 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
119 u64 bits, int limit, int delay)
120 {
121 while (--limit >= 0) {
122 u64 val = nr64_mac(reg);
123
124 if (!(val & bits))
125 break;
126 udelay(delay);
127 }
128 if (limit < 0)
129 return -ENODEV;
130 return 0;
131 }
132
133 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
134 u64 bits, int limit, int delay,
135 const char *reg_name)
136 {
137 int err;
138
139 nw64_mac(reg, bits);
140 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
141 if (err)
142 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
143 "would not clear, val[%llx]\n",
144 np->dev->name, (unsigned long long) bits, reg_name,
145 (unsigned long long) nr64_mac(reg));
146 return err;
147 }
148
149 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
150 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
151 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
152 })
153
154 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
155 u64 bits, int limit, int delay)
156 {
157 while (--limit >= 0) {
158 u64 val = nr64_ipp(reg);
159
160 if (!(val & bits))
161 break;
162 udelay(delay);
163 }
164 if (limit < 0)
165 return -ENODEV;
166 return 0;
167 }
168
169 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
170 u64 bits, int limit, int delay,
171 const char *reg_name)
172 {
173 int err;
174 u64 val;
175
176 val = nr64_ipp(reg);
177 val |= bits;
178 nw64_ipp(reg, val);
179
180 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
181 if (err)
182 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
183 "would not clear, val[%llx]\n",
184 np->dev->name, (unsigned long long) bits, reg_name,
185 (unsigned long long) nr64_ipp(reg));
186 return err;
187 }
188
189 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
190 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
191 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
192 })
193
194 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
195 u64 bits, int limit, int delay)
196 {
197 while (--limit >= 0) {
198 u64 val = nr64(reg);
199
200 if (!(val & bits))
201 break;
202 udelay(delay);
203 }
204 if (limit < 0)
205 return -ENODEV;
206 return 0;
207 }
208
209 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
210 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
211 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
212 })
213
214 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
215 u64 bits, int limit, int delay,
216 const char *reg_name)
217 {
218 int err;
219
220 nw64(reg, bits);
221 err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
222 if (err)
223 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
224 "would not clear, val[%llx]\n",
225 np->dev->name, (unsigned long long) bits, reg_name,
226 (unsigned long long) nr64(reg));
227 return err;
228 }
229
230 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
231 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
232 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
233 })
234
235 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
236 {
237 u64 val = (u64) lp->timer;
238
239 if (on)
240 val |= LDG_IMGMT_ARM;
241
242 nw64(LDG_IMGMT(lp->ldg_num), val);
243 }
244
245 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
246 {
247 unsigned long mask_reg, bits;
248 u64 val;
249
250 if (ldn < 0 || ldn > LDN_MAX)
251 return -EINVAL;
252
253 if (ldn < 64) {
254 mask_reg = LD_IM0(ldn);
255 bits = LD_IM0_MASK;
256 } else {
257 mask_reg = LD_IM1(ldn - 64);
258 bits = LD_IM1_MASK;
259 }
260
261 val = nr64(mask_reg);
262 if (on)
263 val &= ~bits;
264 else
265 val |= bits;
266 nw64(mask_reg, val);
267
268 return 0;
269 }
270
271 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
272 {
273 struct niu_parent *parent = np->parent;
274 int i;
275
276 for (i = 0; i <= LDN_MAX; i++) {
277 int err;
278
279 if (parent->ldg_map[i] != lp->ldg_num)
280 continue;
281
282 err = niu_ldn_irq_enable(np, i, on);
283 if (err)
284 return err;
285 }
286 return 0;
287 }
288
289 static int niu_enable_interrupts(struct niu *np, int on)
290 {
291 int i;
292
293 for (i = 0; i < np->num_ldg; i++) {
294 struct niu_ldg *lp = &np->ldg[i];
295 int err;
296
297 err = niu_enable_ldn_in_ldg(np, lp, on);
298 if (err)
299 return err;
300 }
301 for (i = 0; i < np->num_ldg; i++)
302 niu_ldg_rearm(np, &np->ldg[i], on);
303
304 return 0;
305 }
306
307 static u32 phy_encode(u32 type, int port)
308 {
309 return (type << (port * 2));
310 }
311
312 static u32 phy_decode(u32 val, int port)
313 {
314 return (val >> (port * 2)) & PORT_TYPE_MASK;
315 }
316
317 static int mdio_wait(struct niu *np)
318 {
319 int limit = 1000;
320 u64 val;
321
322 while (--limit > 0) {
323 val = nr64(MIF_FRAME_OUTPUT);
324 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
325 return val & MIF_FRAME_OUTPUT_DATA;
326
327 udelay(10);
328 }
329
330 return -ENODEV;
331 }
332
333 static int mdio_read(struct niu *np, int port, int dev, int reg)
334 {
335 int err;
336
337 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
338 err = mdio_wait(np);
339 if (err < 0)
340 return err;
341
342 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
343 return mdio_wait(np);
344 }
345
346 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
347 {
348 int err;
349
350 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
351 err = mdio_wait(np);
352 if (err < 0)
353 return err;
354
355 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
356 err = mdio_wait(np);
357 if (err < 0)
358 return err;
359
360 return 0;
361 }
362
363 static int mii_read(struct niu *np, int port, int reg)
364 {
365 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
366 return mdio_wait(np);
367 }
368
369 static int mii_write(struct niu *np, int port, int reg, int data)
370 {
371 int err;
372
373 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
374 err = mdio_wait(np);
375 if (err < 0)
376 return err;
377
378 return 0;
379 }
380
381 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
382 {
383 int err;
384
385 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
386 ESR2_TI_PLL_TX_CFG_L(channel),
387 val & 0xffff);
388 if (!err)
389 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
390 ESR2_TI_PLL_TX_CFG_H(channel),
391 val >> 16);
392 return err;
393 }
394
395 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
396 {
397 int err;
398
399 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
400 ESR2_TI_PLL_RX_CFG_L(channel),
401 val & 0xffff);
402 if (!err)
403 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
404 ESR2_TI_PLL_RX_CFG_H(channel),
405 val >> 16);
406 return err;
407 }
408
409 /* Mode is always 10G fiber. */
410 static int serdes_init_niu(struct niu *np)
411 {
412 struct niu_link_config *lp = &np->link_config;
413 u32 tx_cfg, rx_cfg;
414 unsigned long i;
415
416 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
417 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
418 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
419 PLL_RX_CFG_EQ_LP_ADAPTIVE);
420
421 if (lp->loopback_mode == LOOPBACK_PHY) {
422 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
423
424 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
425 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
426
427 tx_cfg |= PLL_TX_CFG_ENTEST;
428 rx_cfg |= PLL_RX_CFG_ENTEST;
429 }
430
431 /* Initialize all 4 lanes of the SERDES. */
432 for (i = 0; i < 4; i++) {
433 int err = esr2_set_tx_cfg(np, i, tx_cfg);
434 if (err)
435 return err;
436 }
437
438 for (i = 0; i < 4; i++) {
439 int err = esr2_set_rx_cfg(np, i, rx_cfg);
440 if (err)
441 return err;
442 }
443
444 return 0;
445 }
446
447 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
448 {
449 int err;
450
451 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
452 if (err >= 0) {
453 *val = (err & 0xffff);
454 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
455 ESR_RXTX_CTRL_H(chan));
456 if (err >= 0)
457 *val |= ((err & 0xffff) << 16);
458 err = 0;
459 }
460 return err;
461 }
462
463 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
464 {
465 int err;
466
467 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
468 ESR_GLUE_CTRL0_L(chan));
469 if (err >= 0) {
470 *val = (err & 0xffff);
471 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
472 ESR_GLUE_CTRL0_H(chan));
473 if (err >= 0) {
474 *val |= ((err & 0xffff) << 16);
475 err = 0;
476 }
477 }
478 return err;
479 }
480
481 static int esr_read_reset(struct niu *np, u32 *val)
482 {
483 int err;
484
485 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
486 ESR_RXTX_RESET_CTRL_L);
487 if (err >= 0) {
488 *val = (err & 0xffff);
489 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
490 ESR_RXTX_RESET_CTRL_H);
491 if (err >= 0) {
492 *val |= ((err & 0xffff) << 16);
493 err = 0;
494 }
495 }
496 return err;
497 }
498
499 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
500 {
501 int err;
502
503 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
504 ESR_RXTX_CTRL_L(chan), val & 0xffff);
505 if (!err)
506 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
507 ESR_RXTX_CTRL_H(chan), (val >> 16));
508 return err;
509 }
510
511 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
512 {
513 int err;
514
515 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
516 ESR_GLUE_CTRL0_L(chan), val & 0xffff);
517 if (!err)
518 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
519 ESR_GLUE_CTRL0_H(chan), (val >> 16));
520 return err;
521 }
522
523 static int esr_reset(struct niu *np)
524 {
525 u32 reset;
526 int err;
527
528 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
529 ESR_RXTX_RESET_CTRL_L, 0x0000);
530 if (err)
531 return err;
532 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
533 ESR_RXTX_RESET_CTRL_H, 0xffff);
534 if (err)
535 return err;
536 udelay(200);
537
538 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
539 ESR_RXTX_RESET_CTRL_L, 0xffff);
540 if (err)
541 return err;
542 udelay(200);
543
544 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
545 ESR_RXTX_RESET_CTRL_H, 0x0000);
546 if (err)
547 return err;
548 udelay(200);
549
550 err = esr_read_reset(np, &reset);
551 if (err)
552 return err;
553 if (reset != 0) {
554 dev_err(np->device, PFX "Port %u ESR_RESET "
555 "did not clear [%08x]\n",
556 np->port, reset);
557 return -ENODEV;
558 }
559
560 return 0;
561 }
562
563 static int serdes_init_10g(struct niu *np)
564 {
565 struct niu_link_config *lp = &np->link_config;
566 unsigned long ctrl_reg, test_cfg_reg, i;
567 u64 ctrl_val, test_cfg_val, sig, mask, val;
568 int err;
569
570 switch (np->port) {
571 case 0:
572 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
573 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
574 break;
575 case 1:
576 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
577 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
578 break;
579
580 default:
581 return -EINVAL;
582 }
583 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
584 ENET_SERDES_CTRL_SDET_1 |
585 ENET_SERDES_CTRL_SDET_2 |
586 ENET_SERDES_CTRL_SDET_3 |
587 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
588 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
589 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
590 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
591 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
592 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
593 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
594 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
595 test_cfg_val = 0;
596
597 if (lp->loopback_mode == LOOPBACK_PHY) {
598 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
599 ENET_SERDES_TEST_MD_0_SHIFT) |
600 (ENET_TEST_MD_PAD_LOOPBACK <<
601 ENET_SERDES_TEST_MD_1_SHIFT) |
602 (ENET_TEST_MD_PAD_LOOPBACK <<
603 ENET_SERDES_TEST_MD_2_SHIFT) |
604 (ENET_TEST_MD_PAD_LOOPBACK <<
605 ENET_SERDES_TEST_MD_3_SHIFT));
606 }
607
608 nw64(ctrl_reg, ctrl_val);
609 nw64(test_cfg_reg, test_cfg_val);
610
611 /* Initialize all 4 lanes of the SERDES. */
612 for (i = 0; i < 4; i++) {
613 u32 rxtx_ctrl, glue0;
614
615 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
616 if (err)
617 return err;
618 err = esr_read_glue0(np, i, &glue0);
619 if (err)
620 return err;
621
622 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
623 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
624 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
625
626 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
627 ESR_GLUE_CTRL0_THCNT |
628 ESR_GLUE_CTRL0_BLTIME);
629 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
630 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
631 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
632 (BLTIME_300_CYCLES <<
633 ESR_GLUE_CTRL0_BLTIME_SHIFT));
634
635 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
636 if (err)
637 return err;
638 err = esr_write_glue0(np, i, glue0);
639 if (err)
640 return err;
641 }
642
643 err = esr_reset(np);
644 if (err)
645 return err;
646
647 sig = nr64(ESR_INT_SIGNALS);
648 switch (np->port) {
649 case 0:
650 mask = ESR_INT_SIGNALS_P0_BITS;
651 val = (ESR_INT_SRDY0_P0 |
652 ESR_INT_DET0_P0 |
653 ESR_INT_XSRDY_P0 |
654 ESR_INT_XDP_P0_CH3 |
655 ESR_INT_XDP_P0_CH2 |
656 ESR_INT_XDP_P0_CH1 |
657 ESR_INT_XDP_P0_CH0);
658 break;
659
660 case 1:
661 mask = ESR_INT_SIGNALS_P1_BITS;
662 val = (ESR_INT_SRDY0_P1 |
663 ESR_INT_DET0_P1 |
664 ESR_INT_XSRDY_P1 |
665 ESR_INT_XDP_P1_CH3 |
666 ESR_INT_XDP_P1_CH2 |
667 ESR_INT_XDP_P1_CH1 |
668 ESR_INT_XDP_P1_CH0);
669 break;
670
671 default:
672 return -EINVAL;
673 }
674
675 if ((sig & mask) != val) {
676 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
677 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
678 return 0;
679 }
680 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
681 "[%08x]\n", np->port, (int) (sig & mask), (int) val);
682 return -ENODEV;
683 }
684 if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
685 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
686 return 0;
687 }
688
689 static int serdes_init_1g(struct niu *np)
690 {
691 u64 val;
692
693 val = nr64(ENET_SERDES_1_PLL_CFG);
694 val &= ~ENET_SERDES_PLL_FBDIV2;
695 switch (np->port) {
696 case 0:
697 val |= ENET_SERDES_PLL_HRATE0;
698 break;
699 case 1:
700 val |= ENET_SERDES_PLL_HRATE1;
701 break;
702 case 2:
703 val |= ENET_SERDES_PLL_HRATE2;
704 break;
705 case 3:
706 val |= ENET_SERDES_PLL_HRATE3;
707 break;
708 default:
709 return -EINVAL;
710 }
711 nw64(ENET_SERDES_1_PLL_CFG, val);
712
713 return 0;
714 }
715
716 static int serdes_init_1g_serdes(struct niu *np)
717 {
718 struct niu_link_config *lp = &np->link_config;
719 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
720 u64 ctrl_val, test_cfg_val, sig, mask, val;
721 int err;
722 u64 reset_val, val_rd;
723
724 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
725 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
726 ENET_SERDES_PLL_FBDIV0;
727 switch (np->port) {
728 case 0:
729 reset_val = ENET_SERDES_RESET_0;
730 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
731 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
732 pll_cfg = ENET_SERDES_0_PLL_CFG;
733 break;
734 case 1:
735 reset_val = ENET_SERDES_RESET_1;
736 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
737 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
738 pll_cfg = ENET_SERDES_1_PLL_CFG;
739 break;
740
741 default:
742 return -EINVAL;
743 }
744 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
745 ENET_SERDES_CTRL_SDET_1 |
746 ENET_SERDES_CTRL_SDET_2 |
747 ENET_SERDES_CTRL_SDET_3 |
748 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
749 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
750 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
751 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
752 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
753 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
754 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
755 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
756 test_cfg_val = 0;
757
758 if (lp->loopback_mode == LOOPBACK_PHY) {
759 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
760 ENET_SERDES_TEST_MD_0_SHIFT) |
761 (ENET_TEST_MD_PAD_LOOPBACK <<
762 ENET_SERDES_TEST_MD_1_SHIFT) |
763 (ENET_TEST_MD_PAD_LOOPBACK <<
764 ENET_SERDES_TEST_MD_2_SHIFT) |
765 (ENET_TEST_MD_PAD_LOOPBACK <<
766 ENET_SERDES_TEST_MD_3_SHIFT));
767 }
768
769 nw64(ENET_SERDES_RESET, reset_val);
770 mdelay(20);
771 val_rd = nr64(ENET_SERDES_RESET);
772 val_rd &= ~reset_val;
773 nw64(pll_cfg, val);
774 nw64(ctrl_reg, ctrl_val);
775 nw64(test_cfg_reg, test_cfg_val);
776 nw64(ENET_SERDES_RESET, val_rd);
777 mdelay(2000);
778
779 /* Initialize all 4 lanes of the SERDES. */
780 for (i = 0; i < 4; i++) {
781 u32 rxtx_ctrl, glue0;
782
783 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
784 if (err)
785 return err;
786 err = esr_read_glue0(np, i, &glue0);
787 if (err)
788 return err;
789
790 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
791 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
792 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
793
794 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
795 ESR_GLUE_CTRL0_THCNT |
796 ESR_GLUE_CTRL0_BLTIME);
797 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
798 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
799 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
800 (BLTIME_300_CYCLES <<
801 ESR_GLUE_CTRL0_BLTIME_SHIFT));
802
803 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
804 if (err)
805 return err;
806 err = esr_write_glue0(np, i, glue0);
807 if (err)
808 return err;
809 }
810
811
812 sig = nr64(ESR_INT_SIGNALS);
813 switch (np->port) {
814 case 0:
815 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
816 mask = val;
817 break;
818
819 case 1:
820 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
821 mask = val;
822 break;
823
824 default:
825 return -EINVAL;
826 }
827
828 if ((sig & mask) != val) {
829 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
830 "[%08x]\n", np->port, (int) (sig & mask), (int) val);
831 return -ENODEV;
832 }
833
834 return 0;
835 }
836
837 static int link_status_1g_serdes(struct niu *np, int *link_up_p)
838 {
839 struct niu_link_config *lp = &np->link_config;
840 int link_up;
841 u64 val;
842 u16 current_speed;
843 unsigned long flags;
844 u8 current_duplex;
845
846 link_up = 0;
847 current_speed = SPEED_INVALID;
848 current_duplex = DUPLEX_INVALID;
849
850 spin_lock_irqsave(&np->lock, flags);
851
852 val = nr64_pcs(PCS_MII_STAT);
853
854 if (val & PCS_MII_STAT_LINK_STATUS) {
855 link_up = 1;
856 current_speed = SPEED_1000;
857 current_duplex = DUPLEX_FULL;
858 }
859
860 lp->active_speed = current_speed;
861 lp->active_duplex = current_duplex;
862 spin_unlock_irqrestore(&np->lock, flags);
863
864 *link_up_p = link_up;
865 return 0;
866 }
867
868 static int link_status_10g_serdes(struct niu *np, int *link_up_p)
869 {
870 unsigned long flags;
871 struct niu_link_config *lp = &np->link_config;
872 int link_up = 0;
873 int link_ok = 1;
874 u64 val, val2;
875 u16 current_speed;
876 u8 current_duplex;
877
878 if (!(np->flags & NIU_FLAGS_10G))
879 return link_status_1g_serdes(np, link_up_p);
880
881 current_speed = SPEED_INVALID;
882 current_duplex = DUPLEX_INVALID;
883 spin_lock_irqsave(&np->lock, flags);
884
885 val = nr64_xpcs(XPCS_STATUS(0));
886 val2 = nr64_mac(XMAC_INTER2);
887 if (val2 & 0x01000000)
888 link_ok = 0;
889
890 if ((val & 0x1000ULL) && link_ok) {
891 link_up = 1;
892 current_speed = SPEED_10000;
893 current_duplex = DUPLEX_FULL;
894 }
895 lp->active_speed = current_speed;
896 lp->active_duplex = current_duplex;
897 spin_unlock_irqrestore(&np->lock, flags);
898 *link_up_p = link_up;
899 return 0;
900 }
901
902 static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
903 {
904 struct niu_link_config *lp = &np->link_config;
905 u16 current_speed, bmsr;
906 unsigned long flags;
907 u8 current_duplex;
908 int err, link_up;
909
910 link_up = 0;
911 current_speed = SPEED_INVALID;
912 current_duplex = DUPLEX_INVALID;
913
914 spin_lock_irqsave(&np->lock, flags);
915
916 err = -EINVAL;
917
918 err = mii_read(np, np->phy_addr, MII_BMSR);
919 if (err < 0)
920 goto out;
921
922 bmsr = err;
923 if (bmsr & BMSR_LSTATUS) {
924 u16 adv, lpa, common, estat;
925
926 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
927 if (err < 0)
928 goto out;
929 adv = err;
930
931 err = mii_read(np, np->phy_addr, MII_LPA);
932 if (err < 0)
933 goto out;
934 lpa = err;
935
936 common = adv & lpa;
937
938 err = mii_read(np, np->phy_addr, MII_ESTATUS);
939 if (err < 0)
940 goto out;
941 estat = err;
942 link_up = 1;
943 current_speed = SPEED_1000;
944 current_duplex = DUPLEX_FULL;
945
946 }
947 lp->active_speed = current_speed;
948 lp->active_duplex = current_duplex;
949 err = 0;
950
951 out:
952 spin_unlock_irqrestore(&np->lock, flags);
953
954 *link_up_p = link_up;
955 return err;
956 }
957
958 static int bcm8704_reset(struct niu *np)
959 {
960 int err, limit;
961
962 err = mdio_read(np, np->phy_addr,
963 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
964 if (err < 0)
965 return err;
966 err |= BMCR_RESET;
967 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
968 MII_BMCR, err);
969 if (err)
970 return err;
971
972 limit = 1000;
973 while (--limit >= 0) {
974 err = mdio_read(np, np->phy_addr,
975 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
976 if (err < 0)
977 return err;
978 if (!(err & BMCR_RESET))
979 break;
980 }
981 if (limit < 0) {
982 dev_err(np->device, PFX "Port %u PHY will not reset "
983 "(bmcr=%04x)\n", np->port, (err & 0xffff));
984 return -ENODEV;
985 }
986 return 0;
987 }
988
989 /* When written, certain PHY registers need to be read back twice
990 * in order for the bits to settle properly.
991 */
992 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
993 {
994 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
995 if (err < 0)
996 return err;
997 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
998 if (err < 0)
999 return err;
1000 return 0;
1001 }
1002
1003 static int bcm8706_init_user_dev3(struct niu *np)
1004 {
1005 int err;
1006
1007
1008 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1009 BCM8704_USER_OPT_DIGITAL_CTRL);
1010 if (err < 0)
1011 return err;
1012 err &= ~USER_ODIG_CTRL_GPIOS;
1013 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1014 err |= USER_ODIG_CTRL_RESV2;
1015 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1016 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1017 if (err)
1018 return err;
1019
1020 mdelay(1000);
1021
1022 return 0;
1023 }
1024
1025 static int bcm8704_init_user_dev3(struct niu *np)
1026 {
1027 int err;
1028
1029 err = mdio_write(np, np->phy_addr,
1030 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1031 (USER_CONTROL_OPTXRST_LVL |
1032 USER_CONTROL_OPBIASFLT_LVL |
1033 USER_CONTROL_OBTMPFLT_LVL |
1034 USER_CONTROL_OPPRFLT_LVL |
1035 USER_CONTROL_OPTXFLT_LVL |
1036 USER_CONTROL_OPRXLOS_LVL |
1037 USER_CONTROL_OPRXFLT_LVL |
1038 USER_CONTROL_OPTXON_LVL |
1039 (0x3f << USER_CONTROL_RES1_SHIFT)));
1040 if (err)
1041 return err;
1042
1043 err = mdio_write(np, np->phy_addr,
1044 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1045 (USER_PMD_TX_CTL_XFP_CLKEN |
1046 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1047 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1048 USER_PMD_TX_CTL_TSCK_LPWREN));
1049 if (err)
1050 return err;
1051
1052 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1053 if (err)
1054 return err;
1055 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1056 if (err)
1057 return err;
1058
1059 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1060 BCM8704_USER_OPT_DIGITAL_CTRL);
1061 if (err < 0)
1062 return err;
1063 err &= ~USER_ODIG_CTRL_GPIOS;
1064 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1065 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1066 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1067 if (err)
1068 return err;
1069
1070 mdelay(1000);
1071
1072 return 0;
1073 }
1074
1075 static int mrvl88x2011_act_led(struct niu *np, int val)
1076 {
1077 int err;
1078
1079 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1080 MRVL88X2011_LED_8_TO_11_CTL);
1081 if (err < 0)
1082 return err;
1083
1084 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1085 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1086
1087 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1088 MRVL88X2011_LED_8_TO_11_CTL, err);
1089 }
1090
1091 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1092 {
1093 int err;
1094
1095 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1096 MRVL88X2011_LED_BLINK_CTL);
1097 if (err >= 0) {
1098 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1099 err |= (rate << 4);
1100
1101 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1102 MRVL88X2011_LED_BLINK_CTL, err);
1103 }
1104
1105 return err;
1106 }
1107
1108 static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1109 {
1110 int err;
1111
1112 /* Set LED functions */
1113 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1114 if (err)
1115 return err;
1116
1117 /* led activity */
1118 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1119 if (err)
1120 return err;
1121
1122 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1123 MRVL88X2011_GENERAL_CTL);
1124 if (err < 0)
1125 return err;
1126
1127 err |= MRVL88X2011_ENA_XFPREFCLK;
1128
1129 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1130 MRVL88X2011_GENERAL_CTL, err);
1131 if (err < 0)
1132 return err;
1133
1134 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1135 MRVL88X2011_PMA_PMD_CTL_1);
1136 if (err < 0)
1137 return err;
1138
1139 if (np->link_config.loopback_mode == LOOPBACK_MAC)
1140 err |= MRVL88X2011_LOOPBACK;
1141 else
1142 err &= ~MRVL88X2011_LOOPBACK;
1143
1144 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1145 MRVL88X2011_PMA_PMD_CTL_1, err);
1146 if (err < 0)
1147 return err;
1148
1149 /* Enable PMD */
1150 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1151 MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1152 }
1153
1154
1155 static int xcvr_diag_bcm870x(struct niu *np)
1156 {
1157 u16 analog_stat0, tx_alarm_status;
1158 int err = 0;
1159
1160 #if 1
1161 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1162 MII_STAT1000);
1163 if (err < 0)
1164 return err;
1165 pr_info(PFX "Port %u PMA_PMD(MII_STAT1000) [%04x]\n",
1166 np->port, err);
1167
1168 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1169 if (err < 0)
1170 return err;
1171 pr_info(PFX "Port %u USER_DEV3(0x20) [%04x]\n",
1172 np->port, err);
1173
1174 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1175 MII_NWAYTEST);
1176 if (err < 0)
1177 return err;
1178 pr_info(PFX "Port %u PHYXS(MII_NWAYTEST) [%04x]\n",
1179 np->port, err);
1180 #endif
1181
1182 /* XXX dig this out it might not be so useful XXX */
1183 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1184 BCM8704_USER_ANALOG_STATUS0);
1185 if (err < 0)
1186 return err;
1187 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1188 BCM8704_USER_ANALOG_STATUS0);
1189 if (err < 0)
1190 return err;
1191 analog_stat0 = err;
1192
1193 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1194 BCM8704_USER_TX_ALARM_STATUS);
1195 if (err < 0)
1196 return err;
1197 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1198 BCM8704_USER_TX_ALARM_STATUS);
1199 if (err < 0)
1200 return err;
1201 tx_alarm_status = err;
1202
1203 if (analog_stat0 != 0x03fc) {
1204 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1205 pr_info(PFX "Port %u cable not connected "
1206 "or bad cable.\n", np->port);
1207 } else if (analog_stat0 == 0x639c) {
1208 pr_info(PFX "Port %u optical module is bad "
1209 "or missing.\n", np->port);
1210 }
1211 }
1212
1213 return 0;
1214 }
1215
1216 static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1217 {
1218 struct niu_link_config *lp = &np->link_config;
1219 int err;
1220
1221 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1222 MII_BMCR);
1223 if (err < 0)
1224 return err;
1225
1226 err &= ~BMCR_LOOPBACK;
1227
1228 if (lp->loopback_mode == LOOPBACK_MAC)
1229 err |= BMCR_LOOPBACK;
1230
1231 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1232 MII_BMCR, err);
1233 if (err)
1234 return err;
1235
1236 return 0;
1237 }
1238
1239 static int xcvr_init_10g_bcm8706(struct niu *np)
1240 {
1241 int err = 0;
1242 u64 val;
1243
1244 if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1245 (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1246 return err;
1247
1248 val = nr64_mac(XMAC_CONFIG);
1249 val &= ~XMAC_CONFIG_LED_POLARITY;
1250 val |= XMAC_CONFIG_FORCE_LED_ON;
1251 nw64_mac(XMAC_CONFIG, val);
1252
1253 val = nr64(MIF_CONFIG);
1254 val |= MIF_CONFIG_INDIRECT_MODE;
1255 nw64(MIF_CONFIG, val);
1256
1257 err = bcm8704_reset(np);
1258 if (err)
1259 return err;
1260
1261 err = xcvr_10g_set_lb_bcm870x(np);
1262 if (err)
1263 return err;
1264
1265 err = bcm8706_init_user_dev3(np);
1266 if (err)
1267 return err;
1268
1269 err = xcvr_diag_bcm870x(np);
1270 if (err)
1271 return err;
1272
1273 return 0;
1274 }
1275
1276 static int xcvr_init_10g_bcm8704(struct niu *np)
1277 {
1278 int err;
1279
1280 err = bcm8704_reset(np);
1281 if (err)
1282 return err;
1283
1284 err = bcm8704_init_user_dev3(np);
1285 if (err)
1286 return err;
1287
1288 err = xcvr_10g_set_lb_bcm870x(np);
1289 if (err)
1290 return err;
1291
1292 err = xcvr_diag_bcm870x(np);
1293 if (err)
1294 return err;
1295
1296 return 0;
1297 }
1298
1299 static int xcvr_init_10g(struct niu *np)
1300 {
1301 int phy_id, err;
1302 u64 val;
1303
1304 val = nr64_mac(XMAC_CONFIG);
1305 val &= ~XMAC_CONFIG_LED_POLARITY;
1306 val |= XMAC_CONFIG_FORCE_LED_ON;
1307 nw64_mac(XMAC_CONFIG, val);
1308
1309 /* XXX shared resource, lock parent XXX */
1310 val = nr64(MIF_CONFIG);
1311 val |= MIF_CONFIG_INDIRECT_MODE;
1312 nw64(MIF_CONFIG, val);
1313
1314 phy_id = phy_decode(np->parent->port_phy, np->port);
1315 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1316
1317 /* handle different phy types */
1318 switch (phy_id & NIU_PHY_ID_MASK) {
1319 case NIU_PHY_ID_MRVL88X2011:
1320 err = xcvr_init_10g_mrvl88x2011(np);
1321 break;
1322
1323 default: /* bcom 8704 */
1324 err = xcvr_init_10g_bcm8704(np);
1325 break;
1326 }
1327
1328 return 0;
1329 }
1330
1331 static int mii_reset(struct niu *np)
1332 {
1333 int limit, err;
1334
1335 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1336 if (err)
1337 return err;
1338
1339 limit = 1000;
1340 while (--limit >= 0) {
1341 udelay(500);
1342 err = mii_read(np, np->phy_addr, MII_BMCR);
1343 if (err < 0)
1344 return err;
1345 if (!(err & BMCR_RESET))
1346 break;
1347 }
1348 if (limit < 0) {
1349 dev_err(np->device, PFX "Port %u MII would not reset, "
1350 "bmcr[%04x]\n", np->port, err);
1351 return -ENODEV;
1352 }
1353
1354 return 0;
1355 }
1356
1357 static int xcvr_init_1g_rgmii(struct niu *np)
1358 {
1359 int err;
1360 u64 val;
1361 u16 bmcr, bmsr, estat;
1362
1363 val = nr64(MIF_CONFIG);
1364 val &= ~MIF_CONFIG_INDIRECT_MODE;
1365 nw64(MIF_CONFIG, val);
1366
1367 err = mii_reset(np);
1368 if (err)
1369 return err;
1370
1371 err = mii_read(np, np->phy_addr, MII_BMSR);
1372 if (err < 0)
1373 return err;
1374 bmsr = err;
1375
1376 estat = 0;
1377 if (bmsr & BMSR_ESTATEN) {
1378 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1379 if (err < 0)
1380 return err;
1381 estat = err;
1382 }
1383
1384 bmcr = 0;
1385 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1386 if (err)
1387 return err;
1388
1389 if (bmsr & BMSR_ESTATEN) {
1390 u16 ctrl1000 = 0;
1391
1392 if (estat & ESTATUS_1000_TFULL)
1393 ctrl1000 |= ADVERTISE_1000FULL;
1394 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1395 if (err)
1396 return err;
1397 }
1398
1399 bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1400
1401 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1402 if (err)
1403 return err;
1404
1405 err = mii_read(np, np->phy_addr, MII_BMCR);
1406 if (err < 0)
1407 return err;
1408 bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1409
1410 err = mii_read(np, np->phy_addr, MII_BMSR);
1411 if (err < 0)
1412 return err;
1413
1414 return 0;
1415 }
1416
1417 static int mii_init_common(struct niu *np)
1418 {
1419 struct niu_link_config *lp = &np->link_config;
1420 u16 bmcr, bmsr, adv, estat;
1421 int err;
1422
1423 err = mii_reset(np);
1424 if (err)
1425 return err;
1426
1427 err = mii_read(np, np->phy_addr, MII_BMSR);
1428 if (err < 0)
1429 return err;
1430 bmsr = err;
1431
1432 estat = 0;
1433 if (bmsr & BMSR_ESTATEN) {
1434 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1435 if (err < 0)
1436 return err;
1437 estat = err;
1438 }
1439
1440 bmcr = 0;
1441 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1442 if (err)
1443 return err;
1444
1445 if (lp->loopback_mode == LOOPBACK_MAC) {
1446 bmcr |= BMCR_LOOPBACK;
1447 if (lp->active_speed == SPEED_1000)
1448 bmcr |= BMCR_SPEED1000;
1449 if (lp->active_duplex == DUPLEX_FULL)
1450 bmcr |= BMCR_FULLDPLX;
1451 }
1452
1453 if (lp->loopback_mode == LOOPBACK_PHY) {
1454 u16 aux;
1455
1456 aux = (BCM5464R_AUX_CTL_EXT_LB |
1457 BCM5464R_AUX_CTL_WRITE_1);
1458 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1459 if (err)
1460 return err;
1461 }
1462
1463 /* XXX configurable XXX */
1464 /* XXX for now don't advertise half-duplex or asym pause... XXX */
1465 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1466 if (bmsr & BMSR_10FULL)
1467 adv |= ADVERTISE_10FULL;
1468 if (bmsr & BMSR_100FULL)
1469 adv |= ADVERTISE_100FULL;
1470 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1471 if (err)
1472 return err;
1473
1474 if (bmsr & BMSR_ESTATEN) {
1475 u16 ctrl1000 = 0;
1476
1477 if (estat & ESTATUS_1000_TFULL)
1478 ctrl1000 |= ADVERTISE_1000FULL;
1479 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1480 if (err)
1481 return err;
1482 }
1483 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1484
1485 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1486 if (err)
1487 return err;
1488
1489 err = mii_read(np, np->phy_addr, MII_BMCR);
1490 if (err < 0)
1491 return err;
1492 err = mii_read(np, np->phy_addr, MII_BMSR);
1493 if (err < 0)
1494 return err;
1495 #if 0
1496 pr_info(PFX "Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1497 np->port, bmcr, bmsr);
1498 #endif
1499
1500 return 0;
1501 }
1502
1503 static int xcvr_init_1g(struct niu *np)
1504 {
1505 u64 val;
1506
1507 /* XXX shared resource, lock parent XXX */
1508 val = nr64(MIF_CONFIG);
1509 val &= ~MIF_CONFIG_INDIRECT_MODE;
1510 nw64(MIF_CONFIG, val);
1511
1512 return mii_init_common(np);
1513 }
1514
1515 static int niu_xcvr_init(struct niu *np)
1516 {
1517 const struct niu_phy_ops *ops = np->phy_ops;
1518 int err;
1519
1520 err = 0;
1521 if (ops->xcvr_init)
1522 err = ops->xcvr_init(np);
1523
1524 return err;
1525 }
1526
1527 static int niu_serdes_init(struct niu *np)
1528 {
1529 const struct niu_phy_ops *ops = np->phy_ops;
1530 int err;
1531
1532 err = 0;
1533 if (ops->serdes_init)
1534 err = ops->serdes_init(np);
1535
1536 return err;
1537 }
1538
1539 static void niu_init_xif(struct niu *);
1540 static void niu_handle_led(struct niu *, int status);
1541
1542 static int niu_link_status_common(struct niu *np, int link_up)
1543 {
1544 struct niu_link_config *lp = &np->link_config;
1545 struct net_device *dev = np->dev;
1546 unsigned long flags;
1547
1548 if (!netif_carrier_ok(dev) && link_up) {
1549 niuinfo(LINK, "%s: Link is up at %s, %s duplex\n",
1550 dev->name,
1551 (lp->active_speed == SPEED_10000 ?
1552 "10Gb/sec" :
1553 (lp->active_speed == SPEED_1000 ?
1554 "1Gb/sec" :
1555 (lp->active_speed == SPEED_100 ?
1556 "100Mbit/sec" : "10Mbit/sec"))),
1557 (lp->active_duplex == DUPLEX_FULL ?
1558 "full" : "half"));
1559
1560 spin_lock_irqsave(&np->lock, flags);
1561 niu_init_xif(np);
1562 niu_handle_led(np, 1);
1563 spin_unlock_irqrestore(&np->lock, flags);
1564
1565 netif_carrier_on(dev);
1566 } else if (netif_carrier_ok(dev) && !link_up) {
1567 niuwarn(LINK, "%s: Link is down\n", dev->name);
1568 spin_lock_irqsave(&np->lock, flags);
1569 niu_handle_led(np, 0);
1570 spin_unlock_irqrestore(&np->lock, flags);
1571 netif_carrier_off(dev);
1572 }
1573
1574 return 0;
1575 }
1576
1577 static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
1578 {
1579 int err, link_up, pma_status, pcs_status;
1580
1581 link_up = 0;
1582
1583 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1584 MRVL88X2011_10G_PMD_STATUS_2);
1585 if (err < 0)
1586 goto out;
1587
1588 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1589 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1590 MRVL88X2011_PMA_PMD_STATUS_1);
1591 if (err < 0)
1592 goto out;
1593
1594 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1595
1596 /* Check PMC Register : 3.0001.2 == 1: read twice */
1597 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1598 MRVL88X2011_PMA_PMD_STATUS_1);
1599 if (err < 0)
1600 goto out;
1601
1602 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1603 MRVL88X2011_PMA_PMD_STATUS_1);
1604 if (err < 0)
1605 goto out;
1606
1607 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1608
1609 /* Check XGXS Register : 4.0018.[0-3,12] */
1610 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1611 MRVL88X2011_10G_XGXS_LANE_STAT);
1612 if (err < 0)
1613 goto out;
1614
1615 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1616 PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1617 PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1618 0x800))
1619 link_up = (pma_status && pcs_status) ? 1 : 0;
1620
1621 np->link_config.active_speed = SPEED_10000;
1622 np->link_config.active_duplex = DUPLEX_FULL;
1623 err = 0;
1624 out:
1625 mrvl88x2011_act_led(np, (link_up ?
1626 MRVL88X2011_LED_CTL_PCS_ACT :
1627 MRVL88X2011_LED_CTL_OFF));
1628
1629 *link_up_p = link_up;
1630 return err;
1631 }
1632
1633 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
1634 {
1635 int err, link_up;
1636 link_up = 0;
1637
1638 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1639 BCM8704_PMD_RCV_SIGDET);
1640 if (err < 0)
1641 goto out;
1642 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
1643 err = 0;
1644 goto out;
1645 }
1646
1647 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1648 BCM8704_PCS_10G_R_STATUS);
1649 if (err < 0)
1650 goto out;
1651
1652 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
1653 err = 0;
1654 goto out;
1655 }
1656
1657 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1658 BCM8704_PHYXS_XGXS_LANE_STAT);
1659 if (err < 0)
1660 goto out;
1661 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
1662 PHYXS_XGXS_LANE_STAT_MAGIC |
1663 PHYXS_XGXS_LANE_STAT_PATTEST |
1664 PHYXS_XGXS_LANE_STAT_LANE3 |
1665 PHYXS_XGXS_LANE_STAT_LANE2 |
1666 PHYXS_XGXS_LANE_STAT_LANE1 |
1667 PHYXS_XGXS_LANE_STAT_LANE0)) {
1668 err = 0;
1669 np->link_config.active_speed = SPEED_INVALID;
1670 np->link_config.active_duplex = DUPLEX_INVALID;
1671 goto out;
1672 }
1673
1674 link_up = 1;
1675 np->link_config.active_speed = SPEED_10000;
1676 np->link_config.active_duplex = DUPLEX_FULL;
1677 err = 0;
1678
1679 out:
1680 *link_up_p = link_up;
1681 if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
1682 err = 0;
1683 return err;
1684 }
1685
1686 static int link_status_10g_bcom(struct niu *np, int *link_up_p)
1687 {
1688 int err, link_up;
1689
1690 link_up = 0;
1691
1692 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1693 BCM8704_PMD_RCV_SIGDET);
1694 if (err < 0)
1695 goto out;
1696 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
1697 err = 0;
1698 goto out;
1699 }
1700
1701 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1702 BCM8704_PCS_10G_R_STATUS);
1703 if (err < 0)
1704 goto out;
1705 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
1706 err = 0;
1707 goto out;
1708 }
1709
1710 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1711 BCM8704_PHYXS_XGXS_LANE_STAT);
1712 if (err < 0)
1713 goto out;
1714
1715 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
1716 PHYXS_XGXS_LANE_STAT_MAGIC |
1717 PHYXS_XGXS_LANE_STAT_LANE3 |
1718 PHYXS_XGXS_LANE_STAT_LANE2 |
1719 PHYXS_XGXS_LANE_STAT_LANE1 |
1720 PHYXS_XGXS_LANE_STAT_LANE0)) {
1721 err = 0;
1722 goto out;
1723 }
1724
1725 link_up = 1;
1726 np->link_config.active_speed = SPEED_10000;
1727 np->link_config.active_duplex = DUPLEX_FULL;
1728 err = 0;
1729
1730 out:
1731 *link_up_p = link_up;
1732 return err;
1733 }
1734
1735 static int link_status_10g(struct niu *np, int *link_up_p)
1736 {
1737 unsigned long flags;
1738 int err = -EINVAL;
1739
1740 spin_lock_irqsave(&np->lock, flags);
1741
1742 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
1743 int phy_id;
1744
1745 phy_id = phy_decode(np->parent->port_phy, np->port);
1746 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1747
1748 /* handle different phy types */
1749 switch (phy_id & NIU_PHY_ID_MASK) {
1750 case NIU_PHY_ID_MRVL88X2011:
1751 err = link_status_10g_mrvl(np, link_up_p);
1752 break;
1753
1754 default: /* bcom 8704 */
1755 err = link_status_10g_bcom(np, link_up_p);
1756 break;
1757 }
1758 }
1759
1760 spin_unlock_irqrestore(&np->lock, flags);
1761
1762 return err;
1763 }
1764
1765 static int niu_10g_phy_present(struct niu *np)
1766 {
1767 u64 sig, mask, val;
1768
1769 sig = nr64(ESR_INT_SIGNALS);
1770 switch (np->port) {
1771 case 0:
1772 mask = ESR_INT_SIGNALS_P0_BITS;
1773 val = (ESR_INT_SRDY0_P0 |
1774 ESR_INT_DET0_P0 |
1775 ESR_INT_XSRDY_P0 |
1776 ESR_INT_XDP_P0_CH3 |
1777 ESR_INT_XDP_P0_CH2 |
1778 ESR_INT_XDP_P0_CH1 |
1779 ESR_INT_XDP_P0_CH0);
1780 break;
1781
1782 case 1:
1783 mask = ESR_INT_SIGNALS_P1_BITS;
1784 val = (ESR_INT_SRDY0_P1 |
1785 ESR_INT_DET0_P1 |
1786 ESR_INT_XSRDY_P1 |
1787 ESR_INT_XDP_P1_CH3 |
1788 ESR_INT_XDP_P1_CH2 |
1789 ESR_INT_XDP_P1_CH1 |
1790 ESR_INT_XDP_P1_CH0);
1791 break;
1792
1793 default:
1794 return 0;
1795 }
1796
1797 if ((sig & mask) != val)
1798 return 0;
1799 return 1;
1800 }
1801
1802 static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
1803 {
1804 unsigned long flags;
1805 int err = 0;
1806 int phy_present;
1807 int phy_present_prev;
1808
1809 spin_lock_irqsave(&np->lock, flags);
1810
1811 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
1812 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
1813 1 : 0;
1814 phy_present = niu_10g_phy_present(np);
1815 if (phy_present != phy_present_prev) {
1816 /* state change */
1817 if (phy_present) {
1818 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
1819 if (np->phy_ops->xcvr_init)
1820 err = np->phy_ops->xcvr_init(np);
1821 if (err) {
1822 /* debounce */
1823 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
1824 }
1825 } else {
1826 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
1827 *link_up_p = 0;
1828 niuwarn(LINK, "%s: Hotplug PHY Removed\n",
1829 np->dev->name);
1830 }
1831 }
1832 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT)
1833 err = link_status_10g_bcm8706(np, link_up_p);
1834 }
1835
1836 spin_unlock_irqrestore(&np->lock, flags);
1837
1838 return err;
1839 }
1840
1841 static int link_status_1g(struct niu *np, int *link_up_p)
1842 {
1843 struct niu_link_config *lp = &np->link_config;
1844 u16 current_speed, bmsr;
1845 unsigned long flags;
1846 u8 current_duplex;
1847 int err, link_up;
1848
1849 link_up = 0;
1850 current_speed = SPEED_INVALID;
1851 current_duplex = DUPLEX_INVALID;
1852
1853 spin_lock_irqsave(&np->lock, flags);
1854
1855 err = -EINVAL;
1856 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
1857 goto out;
1858
1859 err = mii_read(np, np->phy_addr, MII_BMSR);
1860 if (err < 0)
1861 goto out;
1862
1863 bmsr = err;
1864 if (bmsr & BMSR_LSTATUS) {
1865 u16 adv, lpa, common, estat;
1866
1867 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1868 if (err < 0)
1869 goto out;
1870 adv = err;
1871
1872 err = mii_read(np, np->phy_addr, MII_LPA);
1873 if (err < 0)
1874 goto out;
1875 lpa = err;
1876
1877 common = adv & lpa;
1878
1879 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1880 if (err < 0)
1881 goto out;
1882 estat = err;
1883
1884 link_up = 1;
1885 if (estat & (ESTATUS_1000_TFULL | ESTATUS_1000_THALF)) {
1886 current_speed = SPEED_1000;
1887 if (estat & ESTATUS_1000_TFULL)
1888 current_duplex = DUPLEX_FULL;
1889 else
1890 current_duplex = DUPLEX_HALF;
1891 } else {
1892 if (common & ADVERTISE_100BASE4) {
1893 current_speed = SPEED_100;
1894 current_duplex = DUPLEX_HALF;
1895 } else if (common & ADVERTISE_100FULL) {
1896 current_speed = SPEED_100;
1897 current_duplex = DUPLEX_FULL;
1898 } else if (common & ADVERTISE_100HALF) {
1899 current_speed = SPEED_100;
1900 current_duplex = DUPLEX_HALF;
1901 } else if (common & ADVERTISE_10FULL) {
1902 current_speed = SPEED_10;
1903 current_duplex = DUPLEX_FULL;
1904 } else if (common & ADVERTISE_10HALF) {
1905 current_speed = SPEED_10;
1906 current_duplex = DUPLEX_HALF;
1907 } else
1908 link_up = 0;
1909 }
1910 }
1911 lp->active_speed = current_speed;
1912 lp->active_duplex = current_duplex;
1913 err = 0;
1914
1915 out:
1916 spin_unlock_irqrestore(&np->lock, flags);
1917
1918 *link_up_p = link_up;
1919 return err;
1920 }
1921
1922 static int niu_link_status(struct niu *np, int *link_up_p)
1923 {
1924 const struct niu_phy_ops *ops = np->phy_ops;
1925 int err;
1926
1927 err = 0;
1928 if (ops->link_status)
1929 err = ops->link_status(np, link_up_p);
1930
1931 return err;
1932 }
1933
1934 static void niu_timer(unsigned long __opaque)
1935 {
1936 struct niu *np = (struct niu *) __opaque;
1937 unsigned long off;
1938 int err, link_up;
1939
1940 err = niu_link_status(np, &link_up);
1941 if (!err)
1942 niu_link_status_common(np, link_up);
1943
1944 if (netif_carrier_ok(np->dev))
1945 off = 5 * HZ;
1946 else
1947 off = 1 * HZ;
1948 np->timer.expires = jiffies + off;
1949
1950 add_timer(&np->timer);
1951 }
1952
1953 static const struct niu_phy_ops phy_ops_10g_serdes = {
1954 .serdes_init = serdes_init_10g_serdes,
1955 .link_status = link_status_10g_serdes,
1956 };
1957
1958 static const struct niu_phy_ops phy_ops_1g_rgmii = {
1959 .xcvr_init = xcvr_init_1g_rgmii,
1960 .link_status = link_status_1g_rgmii,
1961 };
1962
1963 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
1964 .serdes_init = serdes_init_niu,
1965 .xcvr_init = xcvr_init_10g,
1966 .link_status = link_status_10g,
1967 };
1968
1969 static const struct niu_phy_ops phy_ops_10g_fiber = {
1970 .serdes_init = serdes_init_10g,
1971 .xcvr_init = xcvr_init_10g,
1972 .link_status = link_status_10g,
1973 };
1974
1975 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
1976 .serdes_init = serdes_init_10g,
1977 .xcvr_init = xcvr_init_10g_bcm8706,
1978 .link_status = link_status_10g_hotplug,
1979 };
1980
1981 static const struct niu_phy_ops phy_ops_10g_copper = {
1982 .serdes_init = serdes_init_10g,
1983 .link_status = link_status_10g, /* XXX */
1984 };
1985
1986 static const struct niu_phy_ops phy_ops_1g_fiber = {
1987 .serdes_init = serdes_init_1g,
1988 .xcvr_init = xcvr_init_1g,
1989 .link_status = link_status_1g,
1990 };
1991
1992 static const struct niu_phy_ops phy_ops_1g_copper = {
1993 .xcvr_init = xcvr_init_1g,
1994 .link_status = link_status_1g,
1995 };
1996
1997 struct niu_phy_template {
1998 const struct niu_phy_ops *ops;
1999 u32 phy_addr_base;
2000 };
2001
2002 static const struct niu_phy_template phy_template_niu = {
2003 .ops = &phy_ops_10g_fiber_niu,
2004 .phy_addr_base = 16,
2005 };
2006
2007 static const struct niu_phy_template phy_template_10g_fiber = {
2008 .ops = &phy_ops_10g_fiber,
2009 .phy_addr_base = 8,
2010 };
2011
2012 static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2013 .ops = &phy_ops_10g_fiber_hotplug,
2014 .phy_addr_base = 8,
2015 };
2016
2017 static const struct niu_phy_template phy_template_10g_copper = {
2018 .ops = &phy_ops_10g_copper,
2019 .phy_addr_base = 10,
2020 };
2021
2022 static const struct niu_phy_template phy_template_1g_fiber = {
2023 .ops = &phy_ops_1g_fiber,
2024 .phy_addr_base = 0,
2025 };
2026
2027 static const struct niu_phy_template phy_template_1g_copper = {
2028 .ops = &phy_ops_1g_copper,
2029 .phy_addr_base = 0,
2030 };
2031
2032 static const struct niu_phy_template phy_template_1g_rgmii = {
2033 .ops = &phy_ops_1g_rgmii,
2034 .phy_addr_base = 0,
2035 };
2036
2037 static const struct niu_phy_template phy_template_10g_serdes = {
2038 .ops = &phy_ops_10g_serdes,
2039 .phy_addr_base = 0,
2040 };
2041
2042 static int niu_atca_port_num[4] = {
2043 0, 0, 11, 10
2044 };
2045
2046 static int serdes_init_10g_serdes(struct niu *np)
2047 {
2048 struct niu_link_config *lp = &np->link_config;
2049 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2050 u64 ctrl_val, test_cfg_val, sig, mask, val;
2051 int err;
2052 u64 reset_val;
2053
2054 switch (np->port) {
2055 case 0:
2056 reset_val = ENET_SERDES_RESET_0;
2057 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2058 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2059 pll_cfg = ENET_SERDES_0_PLL_CFG;
2060 break;
2061 case 1:
2062 reset_val = ENET_SERDES_RESET_1;
2063 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2064 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2065 pll_cfg = ENET_SERDES_1_PLL_CFG;
2066 break;
2067
2068 default:
2069 return -EINVAL;
2070 }
2071 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2072 ENET_SERDES_CTRL_SDET_1 |
2073 ENET_SERDES_CTRL_SDET_2 |
2074 ENET_SERDES_CTRL_SDET_3 |
2075 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2076 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2077 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2078 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2079 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2080 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2081 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2082 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2083 test_cfg_val = 0;
2084
2085 if (lp->loopback_mode == LOOPBACK_PHY) {
2086 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2087 ENET_SERDES_TEST_MD_0_SHIFT) |
2088 (ENET_TEST_MD_PAD_LOOPBACK <<
2089 ENET_SERDES_TEST_MD_1_SHIFT) |
2090 (ENET_TEST_MD_PAD_LOOPBACK <<
2091 ENET_SERDES_TEST_MD_2_SHIFT) |
2092 (ENET_TEST_MD_PAD_LOOPBACK <<
2093 ENET_SERDES_TEST_MD_3_SHIFT));
2094 }
2095
2096 esr_reset(np);
2097 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2098 nw64(ctrl_reg, ctrl_val);
2099 nw64(test_cfg_reg, test_cfg_val);
2100
2101 /* Initialize all 4 lanes of the SERDES. */
2102 for (i = 0; i < 4; i++) {
2103 u32 rxtx_ctrl, glue0;
2104
2105 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2106 if (err)
2107 return err;
2108 err = esr_read_glue0(np, i, &glue0);
2109 if (err)
2110 return err;
2111
2112 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2113 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2114 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2115
2116 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2117 ESR_GLUE_CTRL0_THCNT |
2118 ESR_GLUE_CTRL0_BLTIME);
2119 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2120 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2121 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2122 (BLTIME_300_CYCLES <<
2123 ESR_GLUE_CTRL0_BLTIME_SHIFT));
2124
2125 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2126 if (err)
2127 return err;
2128 err = esr_write_glue0(np, i, glue0);
2129 if (err)
2130 return err;
2131 }
2132
2133
2134 sig = nr64(ESR_INT_SIGNALS);
2135 switch (np->port) {
2136 case 0:
2137 mask = ESR_INT_SIGNALS_P0_BITS;
2138 val = (ESR_INT_SRDY0_P0 |
2139 ESR_INT_DET0_P0 |
2140 ESR_INT_XSRDY_P0 |
2141 ESR_INT_XDP_P0_CH3 |
2142 ESR_INT_XDP_P0_CH2 |
2143 ESR_INT_XDP_P0_CH1 |
2144 ESR_INT_XDP_P0_CH0);
2145 break;
2146
2147 case 1:
2148 mask = ESR_INT_SIGNALS_P1_BITS;
2149 val = (ESR_INT_SRDY0_P1 |
2150 ESR_INT_DET0_P1 |
2151 ESR_INT_XSRDY_P1 |
2152 ESR_INT_XDP_P1_CH3 |
2153 ESR_INT_XDP_P1_CH2 |
2154 ESR_INT_XDP_P1_CH1 |
2155 ESR_INT_XDP_P1_CH0);
2156 break;
2157
2158 default:
2159 return -EINVAL;
2160 }
2161
2162 if ((sig & mask) != val) {
2163 int err;
2164 err = serdes_init_1g_serdes(np);
2165 if (!err) {
2166 np->flags &= ~NIU_FLAGS_10G;
2167 np->mac_xcvr = MAC_XCVR_PCS;
2168 } else {
2169 dev_err(np->device, PFX "Port %u 10G/1G SERDES Link Failed \n",
2170 np->port);
2171 return -ENODEV;
2172 }
2173 }
2174
2175 return 0;
2176 }
2177
2178 static int niu_determine_phy_disposition(struct niu *np)
2179 {
2180 struct niu_parent *parent = np->parent;
2181 u8 plat_type = parent->plat_type;
2182 const struct niu_phy_template *tp;
2183 u32 phy_addr_off = 0;
2184
2185 if (plat_type == PLAT_TYPE_NIU) {
2186 tp = &phy_template_niu;
2187 phy_addr_off += np->port;
2188 } else {
2189 switch (np->flags &
2190 (NIU_FLAGS_10G |
2191 NIU_FLAGS_FIBER |
2192 NIU_FLAGS_XCVR_SERDES)) {
2193 case 0:
2194 /* 1G copper */
2195 tp = &phy_template_1g_copper;
2196 if (plat_type == PLAT_TYPE_VF_P0)
2197 phy_addr_off = 10;
2198 else if (plat_type == PLAT_TYPE_VF_P1)
2199 phy_addr_off = 26;
2200
2201 phy_addr_off += (np->port ^ 0x3);
2202 break;
2203
2204 case NIU_FLAGS_10G:
2205 /* 10G copper */
2206 tp = &phy_template_1g_copper;
2207 break;
2208
2209 case NIU_FLAGS_FIBER:
2210 /* 1G fiber */
2211 tp = &phy_template_1g_fiber;
2212 break;
2213
2214 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2215 /* 10G fiber */
2216 tp = &phy_template_10g_fiber;
2217 if (plat_type == PLAT_TYPE_VF_P0 ||
2218 plat_type == PLAT_TYPE_VF_P1)
2219 phy_addr_off = 8;
2220 phy_addr_off += np->port;
2221 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2222 tp = &phy_template_10g_fiber_hotplug;
2223 if (np->port == 0)
2224 phy_addr_off = 8;
2225 if (np->port == 1)
2226 phy_addr_off = 12;
2227 }
2228 break;
2229
2230 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2231 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2232 case NIU_FLAGS_XCVR_SERDES:
2233 switch(np->port) {
2234 case 0:
2235 case 1:
2236 tp = &phy_template_10g_serdes;
2237 break;
2238 case 2:
2239 case 3:
2240 tp = &phy_template_1g_rgmii;
2241 break;
2242 default:
2243 return -EINVAL;
2244 break;
2245 }
2246 phy_addr_off = niu_atca_port_num[np->port];
2247 break;
2248
2249 default:
2250 return -EINVAL;
2251 }
2252 }
2253
2254 np->phy_ops = tp->ops;
2255 np->phy_addr = tp->phy_addr_base + phy_addr_off;
2256
2257 return 0;
2258 }
2259
2260 static int niu_init_link(struct niu *np)
2261 {
2262 struct niu_parent *parent = np->parent;
2263 int err, ignore;
2264
2265 if (parent->plat_type == PLAT_TYPE_NIU) {
2266 err = niu_xcvr_init(np);
2267 if (err)
2268 return err;
2269 msleep(200);
2270 }
2271 err = niu_serdes_init(np);
2272 if (err)
2273 return err;
2274 msleep(200);
2275 err = niu_xcvr_init(np);
2276 if (!err)
2277 niu_link_status(np, &ignore);
2278 return 0;
2279 }
2280
2281 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2282 {
2283 u16 reg0 = addr[4] << 8 | addr[5];
2284 u16 reg1 = addr[2] << 8 | addr[3];
2285 u16 reg2 = addr[0] << 8 | addr[1];
2286
2287 if (np->flags & NIU_FLAGS_XMAC) {
2288 nw64_mac(XMAC_ADDR0, reg0);
2289 nw64_mac(XMAC_ADDR1, reg1);
2290 nw64_mac(XMAC_ADDR2, reg2);
2291 } else {
2292 nw64_mac(BMAC_ADDR0, reg0);
2293 nw64_mac(BMAC_ADDR1, reg1);
2294 nw64_mac(BMAC_ADDR2, reg2);
2295 }
2296 }
2297
2298 static int niu_num_alt_addr(struct niu *np)
2299 {
2300 if (np->flags & NIU_FLAGS_XMAC)
2301 return XMAC_NUM_ALT_ADDR;
2302 else
2303 return BMAC_NUM_ALT_ADDR;
2304 }
2305
2306 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2307 {
2308 u16 reg0 = addr[4] << 8 | addr[5];
2309 u16 reg1 = addr[2] << 8 | addr[3];
2310 u16 reg2 = addr[0] << 8 | addr[1];
2311
2312 if (index >= niu_num_alt_addr(np))
2313 return -EINVAL;
2314
2315 if (np->flags & NIU_FLAGS_XMAC) {
2316 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2317 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2318 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2319 } else {
2320 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2321 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2322 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2323 }
2324
2325 return 0;
2326 }
2327
2328 static int niu_enable_alt_mac(struct niu *np, int index, int on)
2329 {
2330 unsigned long reg;
2331 u64 val, mask;
2332
2333 if (index >= niu_num_alt_addr(np))
2334 return -EINVAL;
2335
2336 if (np->flags & NIU_FLAGS_XMAC) {
2337 reg = XMAC_ADDR_CMPEN;
2338 mask = 1 << index;
2339 } else {
2340 reg = BMAC_ADDR_CMPEN;
2341 mask = 1 << (index + 1);
2342 }
2343
2344 val = nr64_mac(reg);
2345 if (on)
2346 val |= mask;
2347 else
2348 val &= ~mask;
2349 nw64_mac(reg, val);
2350
2351 return 0;
2352 }
2353
2354 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2355 int num, int mac_pref)
2356 {
2357 u64 val = nr64_mac(reg);
2358 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2359 val |= num;
2360 if (mac_pref)
2361 val |= HOST_INFO_MPR;
2362 nw64_mac(reg, val);
2363 }
2364
2365 static int __set_rdc_table_num(struct niu *np,
2366 int xmac_index, int bmac_index,
2367 int rdc_table_num, int mac_pref)
2368 {
2369 unsigned long reg;
2370
2371 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2372 return -EINVAL;
2373 if (np->flags & NIU_FLAGS_XMAC)
2374 reg = XMAC_HOST_INFO(xmac_index);
2375 else
2376 reg = BMAC_HOST_INFO(bmac_index);
2377 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2378 return 0;
2379 }
2380
2381 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2382 int mac_pref)
2383 {
2384 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2385 }
2386
2387 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2388 int mac_pref)
2389 {
2390 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2391 }
2392
2393 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2394 int table_num, int mac_pref)
2395 {
2396 if (idx >= niu_num_alt_addr(np))
2397 return -EINVAL;
2398 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2399 }
2400
2401 static u64 vlan_entry_set_parity(u64 reg_val)
2402 {
2403 u64 port01_mask;
2404 u64 port23_mask;
2405
2406 port01_mask = 0x00ff;
2407 port23_mask = 0xff00;
2408
2409 if (hweight64(reg_val & port01_mask) & 1)
2410 reg_val |= ENET_VLAN_TBL_PARITY0;
2411 else
2412 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2413
2414 if (hweight64(reg_val & port23_mask) & 1)
2415 reg_val |= ENET_VLAN_TBL_PARITY1;
2416 else
2417 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2418
2419 return reg_val;
2420 }
2421
2422 static void vlan_tbl_write(struct niu *np, unsigned long index,
2423 int port, int vpr, int rdc_table)
2424 {
2425 u64 reg_val = nr64(ENET_VLAN_TBL(index));
2426
2427 reg_val &= ~((ENET_VLAN_TBL_VPR |
2428 ENET_VLAN_TBL_VLANRDCTBLN) <<
2429 ENET_VLAN_TBL_SHIFT(port));
2430 if (vpr)
2431 reg_val |= (ENET_VLAN_TBL_VPR <<
2432 ENET_VLAN_TBL_SHIFT(port));
2433 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2434
2435 reg_val = vlan_entry_set_parity(reg_val);
2436
2437 nw64(ENET_VLAN_TBL(index), reg_val);
2438 }
2439
2440 static void vlan_tbl_clear(struct niu *np)
2441 {
2442 int i;
2443
2444 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2445 nw64(ENET_VLAN_TBL(i), 0);
2446 }
2447
2448 static int tcam_wait_bit(struct niu *np, u64 bit)
2449 {
2450 int limit = 1000;
2451
2452 while (--limit > 0) {
2453 if (nr64(TCAM_CTL) & bit)
2454 break;
2455 udelay(1);
2456 }
2457 if (limit < 0)
2458 return -ENODEV;
2459
2460 return 0;
2461 }
2462
2463 static int tcam_flush(struct niu *np, int index)
2464 {
2465 nw64(TCAM_KEY_0, 0x00);
2466 nw64(TCAM_KEY_MASK_0, 0xff);
2467 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2468
2469 return tcam_wait_bit(np, TCAM_CTL_STAT);
2470 }
2471
2472 #if 0
2473 static int tcam_read(struct niu *np, int index,
2474 u64 *key, u64 *mask)
2475 {
2476 int err;
2477
2478 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2479 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2480 if (!err) {
2481 key[0] = nr64(TCAM_KEY_0);
2482 key[1] = nr64(TCAM_KEY_1);
2483 key[2] = nr64(TCAM_KEY_2);
2484 key[3] = nr64(TCAM_KEY_3);
2485 mask[0] = nr64(TCAM_KEY_MASK_0);
2486 mask[1] = nr64(TCAM_KEY_MASK_1);
2487 mask[2] = nr64(TCAM_KEY_MASK_2);
2488 mask[3] = nr64(TCAM_KEY_MASK_3);
2489 }
2490 return err;
2491 }
2492 #endif
2493
2494 static int tcam_write(struct niu *np, int index,
2495 u64 *key, u64 *mask)
2496 {
2497 nw64(TCAM_KEY_0, key[0]);
2498 nw64(TCAM_KEY_1, key[1]);
2499 nw64(TCAM_KEY_2, key[2]);
2500 nw64(TCAM_KEY_3, key[3]);
2501 nw64(TCAM_KEY_MASK_0, mask[0]);
2502 nw64(TCAM_KEY_MASK_1, mask[1]);
2503 nw64(TCAM_KEY_MASK_2, mask[2]);
2504 nw64(TCAM_KEY_MASK_3, mask[3]);
2505 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2506
2507 return tcam_wait_bit(np, TCAM_CTL_STAT);
2508 }
2509
2510 #if 0
2511 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2512 {
2513 int err;
2514
2515 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2516 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2517 if (!err)
2518 *data = nr64(TCAM_KEY_1);
2519
2520 return err;
2521 }
2522 #endif
2523
2524 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2525 {
2526 nw64(TCAM_KEY_1, assoc_data);
2527 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2528
2529 return tcam_wait_bit(np, TCAM_CTL_STAT);
2530 }
2531
2532 static void tcam_enable(struct niu *np, int on)
2533 {
2534 u64 val = nr64(FFLP_CFG_1);
2535
2536 if (on)
2537 val &= ~FFLP_CFG_1_TCAM_DIS;
2538 else
2539 val |= FFLP_CFG_1_TCAM_DIS;
2540 nw64(FFLP_CFG_1, val);
2541 }
2542
2543 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2544 {
2545 u64 val = nr64(FFLP_CFG_1);
2546
2547 val &= ~(FFLP_CFG_1_FFLPINITDONE |
2548 FFLP_CFG_1_CAMLAT |
2549 FFLP_CFG_1_CAMRATIO);
2550 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2551 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2552 nw64(FFLP_CFG_1, val);
2553
2554 val = nr64(FFLP_CFG_1);
2555 val |= FFLP_CFG_1_FFLPINITDONE;
2556 nw64(FFLP_CFG_1, val);
2557 }
2558
2559 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2560 int on)
2561 {
2562 unsigned long reg;
2563 u64 val;
2564
2565 if (class < CLASS_CODE_ETHERTYPE1 ||
2566 class > CLASS_CODE_ETHERTYPE2)
2567 return -EINVAL;
2568
2569 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2570 val = nr64(reg);
2571 if (on)
2572 val |= L2_CLS_VLD;
2573 else
2574 val &= ~L2_CLS_VLD;
2575 nw64(reg, val);
2576
2577 return 0;
2578 }
2579
2580 #if 0
2581 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2582 u64 ether_type)
2583 {
2584 unsigned long reg;
2585 u64 val;
2586
2587 if (class < CLASS_CODE_ETHERTYPE1 ||
2588 class > CLASS_CODE_ETHERTYPE2 ||
2589 (ether_type & ~(u64)0xffff) != 0)
2590 return -EINVAL;
2591
2592 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2593 val = nr64(reg);
2594 val &= ~L2_CLS_ETYPE;
2595 val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2596 nw64(reg, val);
2597
2598 return 0;
2599 }
2600 #endif
2601
2602 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2603 int on)
2604 {
2605 unsigned long reg;
2606 u64 val;
2607
2608 if (class < CLASS_CODE_USER_PROG1 ||
2609 class > CLASS_CODE_USER_PROG4)
2610 return -EINVAL;
2611
2612 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2613 val = nr64(reg);
2614 if (on)
2615 val |= L3_CLS_VALID;
2616 else
2617 val &= ~L3_CLS_VALID;
2618 nw64(reg, val);
2619
2620 return 0;
2621 }
2622
2623 #if 0
2624 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2625 int ipv6, u64 protocol_id,
2626 u64 tos_mask, u64 tos_val)
2627 {
2628 unsigned long reg;
2629 u64 val;
2630
2631 if (class < CLASS_CODE_USER_PROG1 ||
2632 class > CLASS_CODE_USER_PROG4 ||
2633 (protocol_id & ~(u64)0xff) != 0 ||
2634 (tos_mask & ~(u64)0xff) != 0 ||
2635 (tos_val & ~(u64)0xff) != 0)
2636 return -EINVAL;
2637
2638 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2639 val = nr64(reg);
2640 val &= ~(L3_CLS_IPVER | L3_CLS_PID |
2641 L3_CLS_TOSMASK | L3_CLS_TOS);
2642 if (ipv6)
2643 val |= L3_CLS_IPVER;
2644 val |= (protocol_id << L3_CLS_PID_SHIFT);
2645 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
2646 val |= (tos_val << L3_CLS_TOS_SHIFT);
2647 nw64(reg, val);
2648
2649 return 0;
2650 }
2651 #endif
2652
2653 static int tcam_early_init(struct niu *np)
2654 {
2655 unsigned long i;
2656 int err;
2657
2658 tcam_enable(np, 0);
2659 tcam_set_lat_and_ratio(np,
2660 DEFAULT_TCAM_LATENCY,
2661 DEFAULT_TCAM_ACCESS_RATIO);
2662 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
2663 err = tcam_user_eth_class_enable(np, i, 0);
2664 if (err)
2665 return err;
2666 }
2667 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
2668 err = tcam_user_ip_class_enable(np, i, 0);
2669 if (err)
2670 return err;
2671 }
2672
2673 return 0;
2674 }
2675
2676 static int tcam_flush_all(struct niu *np)
2677 {
2678 unsigned long i;
2679
2680 for (i = 0; i < np->parent->tcam_num_entries; i++) {
2681 int err = tcam_flush(np, i);
2682 if (err)
2683 return err;
2684 }
2685 return 0;
2686 }
2687
2688 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
2689 {
2690 return ((u64)index | (num_entries == 1 ?
2691 HASH_TBL_ADDR_AUTOINC : 0));
2692 }
2693
2694 #if 0
2695 static int hash_read(struct niu *np, unsigned long partition,
2696 unsigned long index, unsigned long num_entries,
2697 u64 *data)
2698 {
2699 u64 val = hash_addr_regval(index, num_entries);
2700 unsigned long i;
2701
2702 if (partition >= FCRAM_NUM_PARTITIONS ||
2703 index + num_entries > FCRAM_SIZE)
2704 return -EINVAL;
2705
2706 nw64(HASH_TBL_ADDR(partition), val);
2707 for (i = 0; i < num_entries; i++)
2708 data[i] = nr64(HASH_TBL_DATA(partition));
2709
2710 return 0;
2711 }
2712 #endif
2713
2714 static int hash_write(struct niu *np, unsigned long partition,
2715 unsigned long index, unsigned long num_entries,
2716 u64 *data)
2717 {
2718 u64 val = hash_addr_regval(index, num_entries);
2719 unsigned long i;
2720
2721 if (partition >= FCRAM_NUM_PARTITIONS ||
2722 index + (num_entries * 8) > FCRAM_SIZE)
2723 return -EINVAL;
2724
2725 nw64(HASH_TBL_ADDR(partition), val);
2726 for (i = 0; i < num_entries; i++)
2727 nw64(HASH_TBL_DATA(partition), data[i]);
2728
2729 return 0;
2730 }
2731
2732 static void fflp_reset(struct niu *np)
2733 {
2734 u64 val;
2735
2736 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
2737 udelay(10);
2738 nw64(FFLP_CFG_1, 0);
2739
2740 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
2741 nw64(FFLP_CFG_1, val);
2742 }
2743
2744 static void fflp_set_timings(struct niu *np)
2745 {
2746 u64 val = nr64(FFLP_CFG_1);
2747
2748 val &= ~FFLP_CFG_1_FFLPINITDONE;
2749 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
2750 nw64(FFLP_CFG_1, val);
2751
2752 val = nr64(FFLP_CFG_1);
2753 val |= FFLP_CFG_1_FFLPINITDONE;
2754 nw64(FFLP_CFG_1, val);
2755
2756 val = nr64(FCRAM_REF_TMR);
2757 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
2758 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
2759 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
2760 nw64(FCRAM_REF_TMR, val);
2761 }
2762
2763 static int fflp_set_partition(struct niu *np, u64 partition,
2764 u64 mask, u64 base, int enable)
2765 {
2766 unsigned long reg;
2767 u64 val;
2768
2769 if (partition >= FCRAM_NUM_PARTITIONS ||
2770 (mask & ~(u64)0x1f) != 0 ||
2771 (base & ~(u64)0x1f) != 0)
2772 return -EINVAL;
2773
2774 reg = FLW_PRT_SEL(partition);
2775
2776 val = nr64(reg);
2777 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
2778 val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
2779 val |= (base << FLW_PRT_SEL_BASE_SHIFT);
2780 if (enable)
2781 val |= FLW_PRT_SEL_EXT;
2782 nw64(reg, val);
2783
2784 return 0;
2785 }
2786
2787 static int fflp_disable_all_partitions(struct niu *np)
2788 {
2789 unsigned long i;
2790
2791 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
2792 int err = fflp_set_partition(np, 0, 0, 0, 0);
2793 if (err)
2794 return err;
2795 }
2796 return 0;
2797 }
2798
2799 static void fflp_llcsnap_enable(struct niu *np, int on)
2800 {
2801 u64 val = nr64(FFLP_CFG_1);
2802
2803 if (on)
2804 val |= FFLP_CFG_1_LLCSNAP;
2805 else
2806 val &= ~FFLP_CFG_1_LLCSNAP;
2807 nw64(FFLP_CFG_1, val);
2808 }
2809
2810 static void fflp_errors_enable(struct niu *np, int on)
2811 {
2812 u64 val = nr64(FFLP_CFG_1);
2813
2814 if (on)
2815 val &= ~FFLP_CFG_1_ERRORDIS;
2816 else
2817 val |= FFLP_CFG_1_ERRORDIS;
2818 nw64(FFLP_CFG_1, val);
2819 }
2820
2821 static int fflp_hash_clear(struct niu *np)
2822 {
2823 struct fcram_hash_ipv4 ent;
2824 unsigned long i;
2825
2826 /* IPV4 hash entry with valid bit clear, rest is don't care. */
2827 memset(&ent, 0, sizeof(ent));
2828 ent.header = HASH_HEADER_EXT;
2829
2830 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
2831 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
2832 if (err)
2833 return err;
2834 }
2835 return 0;
2836 }
2837
2838 static int fflp_early_init(struct niu *np)
2839 {
2840 struct niu_parent *parent;
2841 unsigned long flags;
2842 int err;
2843
2844 niu_lock_parent(np, flags);
2845
2846 parent = np->parent;
2847 err = 0;
2848 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
2849 niudbg(PROBE, "fflp_early_init: Initting hw on port %u\n",
2850 np->port);
2851 if (np->parent->plat_type != PLAT_TYPE_NIU) {
2852 fflp_reset(np);
2853 fflp_set_timings(np);
2854 err = fflp_disable_all_partitions(np);
2855 if (err) {
2856 niudbg(PROBE, "fflp_disable_all_partitions "
2857 "failed, err=%d\n", err);
2858 goto out;
2859 }
2860 }
2861
2862 err = tcam_early_init(np);
2863 if (err) {
2864 niudbg(PROBE, "tcam_early_init failed, err=%d\n",
2865 err);
2866 goto out;
2867 }
2868 fflp_llcsnap_enable(np, 1);
2869 fflp_errors_enable(np, 0);
2870 nw64(H1POLY, 0);
2871 nw64(H2POLY, 0);
2872
2873 err = tcam_flush_all(np);
2874 if (err) {
2875 niudbg(PROBE, "tcam_flush_all failed, err=%d\n",
2876 err);
2877 goto out;
2878 }
2879 if (np->parent->plat_type != PLAT_TYPE_NIU) {
2880 err = fflp_hash_clear(np);
2881 if (err) {
2882 niudbg(PROBE, "fflp_hash_clear failed, "
2883 "err=%d\n", err);
2884 goto out;
2885 }
2886 }
2887
2888 vlan_tbl_clear(np);
2889
2890 niudbg(PROBE, "fflp_early_init: Success\n");
2891 parent->flags |= PARENT_FLGS_CLS_HWINIT;
2892 }
2893 out:
2894 niu_unlock_parent(np, flags);
2895 return err;
2896 }
2897
2898 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
2899 {
2900 if (class_code < CLASS_CODE_USER_PROG1 ||
2901 class_code > CLASS_CODE_SCTP_IPV6)
2902 return -EINVAL;
2903
2904 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
2905 return 0;
2906 }
2907
2908 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
2909 {
2910 if (class_code < CLASS_CODE_USER_PROG1 ||
2911 class_code > CLASS_CODE_SCTP_IPV6)
2912 return -EINVAL;
2913
2914 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
2915 return 0;
2916 }
2917
2918 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
2919 u32 offset, u32 size)
2920 {
2921 int i = skb_shinfo(skb)->nr_frags;
2922 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2923
2924 frag->page = page;
2925 frag->page_offset = offset;
2926 frag->size = size;
2927
2928 skb->len += size;
2929 skb->data_len += size;
2930 skb->truesize += size;
2931
2932 skb_shinfo(skb)->nr_frags = i + 1;
2933 }
2934
2935 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
2936 {
2937 a >>= PAGE_SHIFT;
2938 a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
2939
2940 return (a & (MAX_RBR_RING_SIZE - 1));
2941 }
2942
2943 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
2944 struct page ***link)
2945 {
2946 unsigned int h = niu_hash_rxaddr(rp, addr);
2947 struct page *p, **pp;
2948
2949 addr &= PAGE_MASK;
2950 pp = &rp->rxhash[h];
2951 for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
2952 if (p->index == addr) {
2953 *link = pp;
2954 break;
2955 }
2956 }
2957
2958 return p;
2959 }
2960
2961 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
2962 {
2963 unsigned int h = niu_hash_rxaddr(rp, base);
2964
2965 page->index = base;
2966 page->mapping = (struct address_space *) rp->rxhash[h];
2967 rp->rxhash[h] = page;
2968 }
2969
2970 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
2971 gfp_t mask, int start_index)
2972 {
2973 struct page *page;
2974 u64 addr;
2975 int i;
2976
2977 page = alloc_page(mask);
2978 if (!page)
2979 return -ENOMEM;
2980
2981 addr = np->ops->map_page(np->device, page, 0,
2982 PAGE_SIZE, DMA_FROM_DEVICE);
2983
2984 niu_hash_page(rp, page, addr);
2985 if (rp->rbr_blocks_per_page > 1)
2986 atomic_add(rp->rbr_blocks_per_page - 1,
2987 &compound_head(page)->_count);
2988
2989 for (i = 0; i < rp->rbr_blocks_per_page; i++) {
2990 __le32 *rbr = &rp->rbr[start_index + i];
2991
2992 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
2993 addr += rp->rbr_block_size;
2994 }
2995
2996 return 0;
2997 }
2998
2999 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3000 {
3001 int index = rp->rbr_index;
3002
3003 rp->rbr_pending++;
3004 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3005 int err = niu_rbr_add_page(np, rp, mask, index);
3006
3007 if (unlikely(err)) {
3008 rp->rbr_pending--;
3009 return;
3010 }
3011
3012 rp->rbr_index += rp->rbr_blocks_per_page;
3013 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3014 if (rp->rbr_index == rp->rbr_table_size)
3015 rp->rbr_index = 0;
3016
3017 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3018 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3019 rp->rbr_pending = 0;
3020 }
3021 }
3022 }
3023
3024 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3025 {
3026 unsigned int index = rp->rcr_index;
3027 int num_rcr = 0;
3028
3029 rp->rx_dropped++;
3030 while (1) {
3031 struct page *page, **link;
3032 u64 addr, val;
3033 u32 rcr_size;
3034
3035 num_rcr++;
3036
3037 val = le64_to_cpup(&rp->rcr[index]);
3038 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3039 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3040 page = niu_find_rxpage(rp, addr, &link);
3041
3042 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3043 RCR_ENTRY_PKTBUFSZ_SHIFT];
3044 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3045 *link = (struct page *) page->mapping;
3046 np->ops->unmap_page(np->device, page->index,
3047 PAGE_SIZE, DMA_FROM_DEVICE);
3048 page->index = 0;
3049 page->mapping = NULL;
3050 __free_page(page);
3051 rp->rbr_refill_pending++;
3052 }
3053
3054 index = NEXT_RCR(rp, index);
3055 if (!(val & RCR_ENTRY_MULTI))
3056 break;
3057
3058 }
3059 rp->rcr_index = index;
3060
3061 return num_rcr;
3062 }
3063
3064 static int niu_process_rx_pkt(struct niu *np, struct rx_ring_info *rp)
3065 {
3066 unsigned int index = rp->rcr_index;
3067 struct sk_buff *skb;
3068 int len, num_rcr;
3069
3070 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3071 if (unlikely(!skb))
3072 return niu_rx_pkt_ignore(np, rp);
3073
3074 num_rcr = 0;
3075 while (1) {
3076 struct page *page, **link;
3077 u32 rcr_size, append_size;
3078 u64 addr, val, off;
3079
3080 num_rcr++;
3081
3082 val = le64_to_cpup(&rp->rcr[index]);
3083
3084 len = (val & RCR_ENTRY_L2_LEN) >>
3085 RCR_ENTRY_L2_LEN_SHIFT;
3086 len -= ETH_FCS_LEN;
3087
3088 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3089 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3090 page = niu_find_rxpage(rp, addr, &link);
3091
3092 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3093 RCR_ENTRY_PKTBUFSZ_SHIFT];
3094
3095 off = addr & ~PAGE_MASK;
3096 append_size = rcr_size;
3097 if (num_rcr == 1) {
3098 int ptype;
3099
3100 off += 2;
3101 append_size -= 2;
3102
3103 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3104 if ((ptype == RCR_PKT_TYPE_TCP ||
3105 ptype == RCR_PKT_TYPE_UDP) &&
3106 !(val & (RCR_ENTRY_NOPORT |
3107 RCR_ENTRY_ERROR)))
3108 skb->ip_summed = CHECKSUM_UNNECESSARY;
3109 else
3110 skb->ip_summed = CHECKSUM_NONE;
3111 }
3112 if (!(val & RCR_ENTRY_MULTI))
3113 append_size = len - skb->len;
3114
3115 niu_rx_skb_append(skb, page, off, append_size);
3116 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3117 *link = (struct page *) page->mapping;
3118 np->ops->unmap_page(np->device, page->index,
3119 PAGE_SIZE, DMA_FROM_DEVICE);
3120 page->index = 0;
3121 page->mapping = NULL;
3122 rp->rbr_refill_pending++;
3123 } else
3124 get_page(page);
3125
3126 index = NEXT_RCR(rp, index);
3127 if (!(val & RCR_ENTRY_MULTI))
3128 break;
3129
3130 }
3131 rp->rcr_index = index;
3132
3133 skb_reserve(skb, NET_IP_ALIGN);
3134 __pskb_pull_tail(skb, min(len, NIU_RXPULL_MAX));
3135
3136 rp->rx_packets++;
3137 rp->rx_bytes += skb->len;
3138
3139 skb->protocol = eth_type_trans(skb, np->dev);
3140 netif_receive_skb(skb);
3141
3142 return num_rcr;
3143 }
3144
3145 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3146 {
3147 int blocks_per_page = rp->rbr_blocks_per_page;
3148 int err, index = rp->rbr_index;
3149
3150 err = 0;
3151 while (index < (rp->rbr_table_size - blocks_per_page)) {
3152 err = niu_rbr_add_page(np, rp, mask, index);
3153 if (err)
3154 break;
3155
3156 index += blocks_per_page;
3157 }
3158
3159 rp->rbr_index = index;
3160 return err;
3161 }
3162
3163 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3164 {
3165 int i;
3166
3167 for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3168 struct page *page;
3169
3170 page = rp->rxhash[i];
3171 while (page) {
3172 struct page *next = (struct page *) page->mapping;
3173 u64 base = page->index;
3174
3175 np->ops->unmap_page(np->device, base, PAGE_SIZE,
3176 DMA_FROM_DEVICE);
3177 page->index = 0;
3178 page->mapping = NULL;
3179
3180 __free_page(page);
3181
3182 page = next;
3183 }
3184 }
3185
3186 for (i = 0; i < rp->rbr_table_size; i++)
3187 rp->rbr[i] = cpu_to_le32(0);
3188 rp->rbr_index = 0;
3189 }
3190
3191 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3192 {
3193 struct tx_buff_info *tb = &rp->tx_buffs[idx];
3194 struct sk_buff *skb = tb->skb;
3195 struct tx_pkt_hdr *tp;
3196 u64 tx_flags;
3197 int i, len;
3198
3199 tp = (struct tx_pkt_hdr *) skb->data;
3200 tx_flags = le64_to_cpup(&tp->flags);
3201
3202 rp->tx_packets++;
3203 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3204 ((tx_flags & TXHDR_PAD) / 2));
3205
3206 len = skb_headlen(skb);
3207 np->ops->unmap_single(np->device, tb->mapping,
3208 len, DMA_TO_DEVICE);
3209
3210 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3211 rp->mark_pending--;
3212
3213 tb->skb = NULL;
3214 do {
3215 idx = NEXT_TX(rp, idx);
3216 len -= MAX_TX_DESC_LEN;
3217 } while (len > 0);
3218
3219 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3220 tb = &rp->tx_buffs[idx];
3221 BUG_ON(tb->skb != NULL);
3222 np->ops->unmap_page(np->device, tb->mapping,
3223 skb_shinfo(skb)->frags[i].size,
3224 DMA_TO_DEVICE);
3225 idx = NEXT_TX(rp, idx);
3226 }
3227
3228 dev_kfree_skb(skb);
3229
3230 return idx;
3231 }
3232
3233 #define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3234
3235 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3236 {
3237 struct netdev_queue *txq;
3238 u16 pkt_cnt, tmp;
3239 int cons, index;
3240 u64 cs;
3241
3242 index = (rp - np->tx_rings);
3243 txq = netdev_get_tx_queue(np->dev, index);
3244
3245 cs = rp->tx_cs;
3246 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3247 goto out;
3248
3249 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3250 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3251 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3252
3253 rp->last_pkt_cnt = tmp;
3254
3255 cons = rp->cons;
3256
3257 niudbg(TX_DONE, "%s: niu_tx_work() pkt_cnt[%u] cons[%d]\n",
3258 np->dev->name, pkt_cnt, cons);
3259
3260 while (pkt_cnt--)
3261 cons = release_tx_packet(np, rp, cons);
3262
3263 rp->cons = cons;
3264 smp_mb();
3265
3266 out:
3267 if (unlikely(netif_tx_queue_stopped(txq) &&
3268 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
3269 __netif_tx_lock(txq, smp_processor_id());
3270 if (netif_tx_queue_stopped(txq) &&
3271 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
3272 netif_tx_wake_queue(txq);
3273 __netif_tx_unlock(txq);
3274 }
3275 }
3276
3277 static int niu_rx_work(struct niu *np, struct rx_ring_info *rp, int budget)
3278 {
3279 int qlen, rcr_done = 0, work_done = 0;
3280 struct rxdma_mailbox *mbox = rp->mbox;
3281 u64 stat;
3282
3283 #if 1
3284 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3285 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3286 #else
3287 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3288 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3289 #endif
3290 mbox->rx_dma_ctl_stat = 0;
3291 mbox->rcrstat_a = 0;
3292
3293 niudbg(RX_STATUS, "%s: niu_rx_work(chan[%d]), stat[%llx] qlen=%d\n",
3294 np->dev->name, rp->rx_channel, (unsigned long long) stat, qlen);
3295
3296 rcr_done = work_done = 0;
3297 qlen = min(qlen, budget);
3298 while (work_done < qlen) {
3299 rcr_done += niu_process_rx_pkt(np, rp);
3300 work_done++;
3301 }
3302
3303 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3304 unsigned int i;
3305
3306 for (i = 0; i < rp->rbr_refill_pending; i++)
3307 niu_rbr_refill(np, rp, GFP_ATOMIC);
3308 rp->rbr_refill_pending = 0;
3309 }
3310
3311 stat = (RX_DMA_CTL_STAT_MEX |
3312 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3313 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3314
3315 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3316
3317 return work_done;
3318 }
3319
3320 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3321 {
3322 u64 v0 = lp->v0;
3323 u32 tx_vec = (v0 >> 32);
3324 u32 rx_vec = (v0 & 0xffffffff);
3325 int i, work_done = 0;
3326
3327 niudbg(INTR, "%s: niu_poll_core() v0[%016llx]\n",
3328 np->dev->name, (unsigned long long) v0);
3329
3330 for (i = 0; i < np->num_tx_rings; i++) {
3331 struct tx_ring_info *rp = &np->tx_rings[i];
3332 if (tx_vec & (1 << rp->tx_channel))
3333 niu_tx_work(np, rp);
3334 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3335 }
3336
3337 for (i = 0; i < np->num_rx_rings; i++) {
3338 struct rx_ring_info *rp = &np->rx_rings[i];
3339
3340 if (rx_vec & (1 << rp->rx_channel)) {
3341 int this_work_done;
3342
3343 this_work_done = niu_rx_work(np, rp,
3344 budget);
3345
3346 budget -= this_work_done;
3347 work_done += this_work_done;
3348 }
3349 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3350 }
3351
3352 return work_done;
3353 }
3354
3355 static int niu_poll(struct napi_struct *napi, int budget)
3356 {
3357 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3358 struct niu *np = lp->np;
3359 int work_done;
3360
3361 work_done = niu_poll_core(np, lp, budget);
3362
3363 if (work_done < budget) {
3364 netif_rx_complete(np->dev, napi);
3365 niu_ldg_rearm(np, lp, 1);
3366 }
3367 return work_done;
3368 }
3369
3370 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3371 u64 stat)
3372 {
3373 dev_err(np->device, PFX "%s: RX channel %u errors ( ",
3374 np->dev->name, rp->rx_channel);
3375
3376 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3377 printk("RBR_TMOUT ");
3378 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3379 printk("RSP_CNT ");
3380 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3381 printk("BYTE_EN_BUS ");
3382 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3383 printk("RSP_DAT ");
3384 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3385 printk("RCR_ACK ");
3386 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3387 printk("RCR_SHA_PAR ");
3388 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3389 printk("RBR_PRE_PAR ");
3390 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3391 printk("CONFIG ");
3392 if (stat & RX_DMA_CTL_STAT_RCRINCON)
3393 printk("RCRINCON ");
3394 if (stat & RX_DMA_CTL_STAT_RCRFULL)
3395 printk("RCRFULL ");
3396 if (stat & RX_DMA_CTL_STAT_RBRFULL)
3397 printk("RBRFULL ");
3398 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3399 printk("RBRLOGPAGE ");
3400 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3401 printk("CFIGLOGPAGE ");
3402 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3403 printk("DC_FIDO ");
3404
3405 printk(")\n");
3406 }
3407
3408 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3409 {
3410 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3411 int err = 0;
3412
3413
3414 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3415 RX_DMA_CTL_STAT_PORT_FATAL))
3416 err = -EINVAL;
3417
3418 if (err) {
3419 dev_err(np->device, PFX "%s: RX channel %u error, stat[%llx]\n",
3420 np->dev->name, rp->rx_channel,
3421 (unsigned long long) stat);
3422
3423 niu_log_rxchan_errors(np, rp, stat);
3424 }
3425
3426 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3427 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3428
3429 return err;
3430 }
3431
3432 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3433 u64 cs)
3434 {
3435 dev_err(np->device, PFX "%s: TX channel %u errors ( ",
3436 np->dev->name, rp->tx_channel);
3437
3438 if (cs & TX_CS_MBOX_ERR)
3439 printk("MBOX ");
3440 if (cs & TX_CS_PKT_SIZE_ERR)
3441 printk("PKT_SIZE ");
3442 if (cs & TX_CS_TX_RING_OFLOW)
3443 printk("TX_RING_OFLOW ");
3444 if (cs & TX_CS_PREF_BUF_PAR_ERR)
3445 printk("PREF_BUF_PAR ");
3446 if (cs & TX_CS_NACK_PREF)
3447 printk("NACK_PREF ");
3448 if (cs & TX_CS_NACK_PKT_RD)
3449 printk("NACK_PKT_RD ");
3450 if (cs & TX_CS_CONF_PART_ERR)
3451 printk("CONF_PART ");
3452 if (cs & TX_CS_PKT_PRT_ERR)
3453 printk("PKT_PTR ");
3454
3455 printk(")\n");
3456 }
3457
3458 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3459 {
3460 u64 cs, logh, logl;
3461
3462 cs = nr64(TX_CS(rp->tx_channel));
3463 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3464 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3465
3466 dev_err(np->device, PFX "%s: TX channel %u error, "
3467 "cs[%llx] logh[%llx] logl[%llx]\n",
3468 np->dev->name, rp->tx_channel,
3469 (unsigned long long) cs,
3470 (unsigned long long) logh,
3471 (unsigned long long) logl);
3472
3473 niu_log_txchan_errors(np, rp, cs);
3474
3475 return -ENODEV;
3476 }
3477
3478 static int niu_mif_interrupt(struct niu *np)
3479 {
3480 u64 mif_status = nr64(MIF_STATUS);
3481 int phy_mdint = 0;
3482
3483 if (np->flags & NIU_FLAGS_XMAC) {
3484 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3485
3486 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3487 phy_mdint = 1;
3488 }
3489
3490 dev_err(np->device, PFX "%s: MIF interrupt, "
3491 "stat[%llx] phy_mdint(%d)\n",
3492 np->dev->name, (unsigned long long) mif_status, phy_mdint);
3493
3494 return -ENODEV;
3495 }
3496
3497 static void niu_xmac_interrupt(struct niu *np)
3498 {
3499 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3500 u64 val;
3501
3502 val = nr64_mac(XTXMAC_STATUS);
3503 if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3504 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3505 if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3506 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3507 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3508 mp->tx_fifo_errors++;
3509 if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3510 mp->tx_overflow_errors++;
3511 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3512 mp->tx_max_pkt_size_errors++;
3513 if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3514 mp->tx_underflow_errors++;
3515
3516 val = nr64_mac(XRXMAC_STATUS);
3517 if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3518 mp->rx_local_faults++;
3519 if (val & XRXMAC_STATUS_RFLT_DET)
3520 mp->rx_remote_faults++;
3521 if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3522 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3523 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3524 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3525 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3526 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3527 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3528 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3529 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3530 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3531 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3532 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3533 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3534 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3535 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3536 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3537 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3538 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3539 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3540 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3541 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3542 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3543 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3544 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3545 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3546 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
3547 if (val & XRXMAC_STAT_MSK_RXOCTET_CNT_EXP)
3548 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3549 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3550 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3551 if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3552 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3553 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3554 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3555 if (val & XRXMAC_STATUS_RXUFLOW)
3556 mp->rx_underflows++;
3557 if (val & XRXMAC_STATUS_RXOFLOW)
3558 mp->rx_overflows++;
3559
3560 val = nr64_mac(XMAC_FC_STAT);
3561 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
3562 mp->pause_off_state++;
3563 if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
3564 mp->pause_on_state++;
3565 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
3566 mp->pause_received++;
3567 }
3568
3569 static void niu_bmac_interrupt(struct niu *np)
3570 {
3571 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
3572 u64 val;
3573
3574 val = nr64_mac(BTXMAC_STATUS);
3575 if (val & BTXMAC_STATUS_UNDERRUN)
3576 mp->tx_underflow_errors++;
3577 if (val & BTXMAC_STATUS_MAX_PKT_ERR)
3578 mp->tx_max_pkt_size_errors++;
3579 if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
3580 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
3581 if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
3582 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
3583
3584 val = nr64_mac(BRXMAC_STATUS);
3585 if (val & BRXMAC_STATUS_OVERFLOW)
3586 mp->rx_overflows++;
3587 if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
3588 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
3589 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
3590 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
3591 if (val & BRXMAC_STATUS_CRC_ERR_EXP)
3592 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
3593 if (val & BRXMAC_STATUS_LEN_ERR_EXP)
3594 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
3595
3596 val = nr64_mac(BMAC_CTRL_STATUS);
3597 if (val & BMAC_CTRL_STATUS_NOPAUSE)
3598 mp->pause_off_state++;
3599 if (val & BMAC_CTRL_STATUS_PAUSE)
3600 mp->pause_on_state++;
3601 if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
3602 mp->pause_received++;
3603 }
3604
3605 static int niu_mac_interrupt(struct niu *np)
3606 {
3607 if (np->flags & NIU_FLAGS_XMAC)
3608 niu_xmac_interrupt(np);
3609 else
3610 niu_bmac_interrupt(np);
3611
3612 return 0;
3613 }
3614
3615 static void niu_log_device_error(struct niu *np, u64 stat)
3616 {
3617 dev_err(np->device, PFX "%s: Core device errors ( ",
3618 np->dev->name);
3619
3620 if (stat & SYS_ERR_MASK_META2)
3621 printk("META2 ");
3622 if (stat & SYS_ERR_MASK_META1)
3623 printk("META1 ");
3624 if (stat & SYS_ERR_MASK_PEU)
3625 printk("PEU ");
3626 if (stat & SYS_ERR_MASK_TXC)
3627 printk("TXC ");
3628 if (stat & SYS_ERR_MASK_RDMC)
3629 printk("RDMC ");
3630 if (stat & SYS_ERR_MASK_TDMC)
3631 printk("TDMC ");
3632 if (stat & SYS_ERR_MASK_ZCP)
3633 printk("ZCP ");
3634 if (stat & SYS_ERR_MASK_FFLP)
3635 printk("FFLP ");
3636 if (stat & SYS_ERR_MASK_IPP)
3637 printk("IPP ");
3638 if (stat & SYS_ERR_MASK_MAC)
3639 printk("MAC ");
3640 if (stat & SYS_ERR_MASK_SMX)
3641 printk("SMX ");
3642
3643 printk(")\n");
3644 }
3645
3646 static int niu_device_error(struct niu *np)
3647 {
3648 u64 stat = nr64(SYS_ERR_STAT);
3649
3650 dev_err(np->device, PFX "%s: Core device error, stat[%llx]\n",
3651 np->dev->name, (unsigned long long) stat);
3652
3653 niu_log_device_error(np, stat);
3654
3655 return -ENODEV;
3656 }
3657
3658 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
3659 u64 v0, u64 v1, u64 v2)
3660 {
3661
3662 int i, err = 0;
3663
3664 lp->v0 = v0;
3665 lp->v1 = v1;
3666 lp->v2 = v2;
3667
3668 if (v1 & 0x00000000ffffffffULL) {
3669 u32 rx_vec = (v1 & 0xffffffff);
3670
3671 for (i = 0; i < np->num_rx_rings; i++) {
3672 struct rx_ring_info *rp = &np->rx_rings[i];
3673
3674 if (rx_vec & (1 << rp->rx_channel)) {
3675 int r = niu_rx_error(np, rp);
3676 if (r) {
3677 err = r;
3678 } else {
3679 if (!v0)
3680 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3681 RX_DMA_CTL_STAT_MEX);
3682 }
3683 }
3684 }
3685 }
3686 if (v1 & 0x7fffffff00000000ULL) {
3687 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
3688
3689 for (i = 0; i < np->num_tx_rings; i++) {
3690 struct tx_ring_info *rp = &np->tx_rings[i];
3691
3692 if (tx_vec & (1 << rp->tx_channel)) {
3693 int r = niu_tx_error(np, rp);
3694 if (r)
3695 err = r;
3696 }
3697 }
3698 }
3699 if ((v0 | v1) & 0x8000000000000000ULL) {
3700 int r = niu_mif_interrupt(np);
3701 if (r)
3702 err = r;
3703 }
3704 if (v2) {
3705 if (v2 & 0x01ef) {
3706 int r = niu_mac_interrupt(np);
3707 if (r)
3708 err = r;
3709 }
3710 if (v2 & 0x0210) {
3711 int r = niu_device_error(np);
3712 if (r)
3713 err = r;
3714 }
3715 }
3716
3717 if (err)
3718 niu_enable_interrupts(np, 0);
3719
3720 return err;
3721 }
3722
3723 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
3724 int ldn)
3725 {
3726 struct rxdma_mailbox *mbox = rp->mbox;
3727 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3728
3729 stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
3730 RX_DMA_CTL_STAT_RCRTO);
3731 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
3732
3733 niudbg(INTR, "%s: rxchan_intr stat[%llx]\n",
3734 np->dev->name, (unsigned long long) stat);
3735 }
3736
3737 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
3738 int ldn)
3739 {
3740 rp->tx_cs = nr64(TX_CS(rp->tx_channel));
3741
3742 niudbg(INTR, "%s: txchan_intr cs[%llx]\n",
3743 np->dev->name, (unsigned long long) rp->tx_cs);
3744 }
3745
3746 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
3747 {
3748 struct niu_parent *parent = np->parent;
3749 u32 rx_vec, tx_vec;
3750 int i;
3751
3752 tx_vec = (v0 >> 32);
3753 rx_vec = (v0 & 0xffffffff);
3754
3755 for (i = 0; i < np->num_rx_rings; i++) {
3756 struct rx_ring_info *rp = &np->rx_rings[i];
3757 int ldn = LDN_RXDMA(rp->rx_channel);
3758
3759 if (parent->ldg_map[ldn] != ldg)
3760 continue;
3761
3762 nw64(LD_IM0(ldn), LD_IM0_MASK);
3763 if (rx_vec & (1 << rp->rx_channel))
3764 niu_rxchan_intr(np, rp, ldn);
3765 }
3766
3767 for (i = 0; i < np->num_tx_rings; i++) {
3768 struct tx_ring_info *rp = &np->tx_rings[i];
3769 int ldn = LDN_TXDMA(rp->tx_channel);
3770
3771 if (parent->ldg_map[ldn] != ldg)
3772 continue;
3773
3774 nw64(LD_IM0(ldn), LD_IM0_MASK);
3775 if (tx_vec & (1 << rp->tx_channel))
3776 niu_txchan_intr(np, rp, ldn);
3777 }
3778 }
3779
3780 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
3781 u64 v0, u64 v1, u64 v2)
3782 {
3783 if (likely(netif_rx_schedule_prep(np->dev, &lp->napi))) {
3784 lp->v0 = v0;
3785 lp->v1 = v1;
3786 lp->v2 = v2;
3787 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
3788 __netif_rx_schedule(np->dev, &lp->napi);
3789 }
3790 }
3791
3792 static irqreturn_t niu_interrupt(int irq, void *dev_id)
3793 {
3794 struct niu_ldg *lp = dev_id;
3795 struct niu *np = lp->np;
3796 int ldg = lp->ldg_num;
3797 unsigned long flags;
3798 u64 v0, v1, v2;
3799
3800 if (netif_msg_intr(np))
3801 printk(KERN_DEBUG PFX "niu_interrupt() ldg[%p](%d) ",
3802 lp, ldg);
3803
3804 spin_lock_irqsave(&np->lock, flags);
3805
3806 v0 = nr64(LDSV0(ldg));
3807 v1 = nr64(LDSV1(ldg));
3808 v2 = nr64(LDSV2(ldg));
3809
3810 if (netif_msg_intr(np))
3811 printk("v0[%llx] v1[%llx] v2[%llx]\n",
3812 (unsigned long long) v0,
3813 (unsigned long long) v1,
3814 (unsigned long long) v2);
3815
3816 if (unlikely(!v0 && !v1 && !v2)) {
3817 spin_unlock_irqrestore(&np->lock, flags);
3818 return IRQ_NONE;
3819 }
3820
3821 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
3822 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
3823 if (err)
3824 goto out;
3825 }
3826 if (likely(v0 & ~((u64)1 << LDN_MIF)))
3827 niu_schedule_napi(np, lp, v0, v1, v2);
3828 else
3829 niu_ldg_rearm(np, lp, 1);
3830 out:
3831 spin_unlock_irqrestore(&np->lock, flags);
3832
3833 return IRQ_HANDLED;
3834 }
3835
3836 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
3837 {
3838 if (rp->mbox) {
3839 np->ops->free_coherent(np->device,
3840 sizeof(struct rxdma_mailbox),
3841 rp->mbox, rp->mbox_dma);
3842 rp->mbox = NULL;
3843 }
3844 if (rp->rcr) {
3845 np->ops->free_coherent(np->device,
3846 MAX_RCR_RING_SIZE * sizeof(__le64),
3847 rp->rcr, rp->rcr_dma);
3848 rp->rcr = NULL;
3849 rp->rcr_table_size = 0;
3850 rp->rcr_index = 0;
3851 }
3852 if (rp->rbr) {
3853 niu_rbr_free(np, rp);
3854
3855 np->ops->free_coherent(np->device,
3856 MAX_RBR_RING_SIZE * sizeof(__le32),
3857 rp->rbr, rp->rbr_dma);
3858 rp->rbr = NULL;
3859 rp->rbr_table_size = 0;
3860 rp->rbr_index = 0;
3861 }
3862 kfree(rp->rxhash);
3863 rp->rxhash = NULL;
3864 }
3865
3866 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
3867 {
3868 if (rp->mbox) {
3869 np->ops->free_coherent(np->device,
3870 sizeof(struct txdma_mailbox),
3871 rp->mbox, rp->mbox_dma);
3872 rp->mbox = NULL;
3873 }
3874 if (rp->descr) {
3875 int i;
3876
3877 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
3878 if (rp->tx_buffs[i].skb)
3879 (void) release_tx_packet(np, rp, i);
3880 }
3881
3882 np->ops->free_coherent(np->device,
3883 MAX_TX_RING_SIZE * sizeof(__le64),
3884 rp->descr, rp->descr_dma);
3885 rp->descr = NULL;
3886 rp->pending = 0;
3887 rp->prod = 0;
3888 rp->cons = 0;
3889 rp->wrap_bit = 0;
3890 }
3891 }
3892
3893 static void niu_free_channels(struct niu *np)
3894 {
3895 int i;
3896
3897 if (np->rx_rings) {
3898 for (i = 0; i < np->num_rx_rings; i++) {
3899 struct rx_ring_info *rp = &np->rx_rings[i];
3900
3901 niu_free_rx_ring_info(np, rp);
3902 }
3903 kfree(np->rx_rings);
3904 np->rx_rings = NULL;
3905 np->num_rx_rings = 0;
3906 }
3907
3908 if (np->tx_rings) {
3909 for (i = 0; i < np->num_tx_rings; i++) {
3910 struct tx_ring_info *rp = &np->tx_rings[i];
3911
3912 niu_free_tx_ring_info(np, rp);
3913 }
3914 kfree(np->tx_rings);
3915 np->tx_rings = NULL;
3916 np->num_tx_rings = 0;
3917 }
3918 }
3919
3920 static int niu_alloc_rx_ring_info(struct niu *np,
3921 struct rx_ring_info *rp)
3922 {
3923 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
3924
3925 rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
3926 GFP_KERNEL);
3927 if (!rp->rxhash)
3928 return -ENOMEM;
3929
3930 rp->mbox = np->ops->alloc_coherent(np->device,
3931 sizeof(struct rxdma_mailbox),
3932 &rp->mbox_dma, GFP_KERNEL);
3933 if (!rp->mbox)
3934 return -ENOMEM;
3935 if ((unsigned long)rp->mbox & (64UL - 1)) {
3936 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3937 "RXDMA mailbox %p\n", np->dev->name, rp->mbox);
3938 return -EINVAL;
3939 }
3940
3941 rp->rcr = np->ops->alloc_coherent(np->device,
3942 MAX_RCR_RING_SIZE * sizeof(__le64),
3943 &rp->rcr_dma, GFP_KERNEL);
3944 if (!rp->rcr)
3945 return -ENOMEM;
3946 if ((unsigned long)rp->rcr & (64UL - 1)) {
3947 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3948 "RXDMA RCR table %p\n", np->dev->name, rp->rcr);
3949 return -EINVAL;
3950 }
3951 rp->rcr_table_size = MAX_RCR_RING_SIZE;
3952 rp->rcr_index = 0;
3953
3954 rp->rbr = np->ops->alloc_coherent(np->device,
3955 MAX_RBR_RING_SIZE * sizeof(__le32),
3956 &rp->rbr_dma, GFP_KERNEL);
3957 if (!rp->rbr)
3958 return -ENOMEM;
3959 if ((unsigned long)rp->rbr & (64UL - 1)) {
3960 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3961 "RXDMA RBR table %p\n", np->dev->name, rp->rbr);
3962 return -EINVAL;
3963 }
3964 rp->rbr_table_size = MAX_RBR_RING_SIZE;
3965 rp->rbr_index = 0;
3966 rp->rbr_pending = 0;
3967
3968 return 0;
3969 }
3970
3971 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
3972 {
3973 int mtu = np->dev->mtu;
3974
3975 /* These values are recommended by the HW designers for fair
3976 * utilization of DRR amongst the rings.
3977 */
3978 rp->max_burst = mtu + 32;
3979 if (rp->max_burst > 4096)
3980 rp->max_burst = 4096;
3981 }
3982
3983 static int niu_alloc_tx_ring_info(struct niu *np,
3984 struct tx_ring_info *rp)
3985 {
3986 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
3987
3988 rp->mbox = np->ops->alloc_coherent(np->device,
3989 sizeof(struct txdma_mailbox),
3990 &rp->mbox_dma, GFP_KERNEL);
3991 if (!rp->mbox)
3992 return -ENOMEM;
3993 if ((unsigned long)rp->mbox & (64UL - 1)) {
3994 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3995 "TXDMA mailbox %p\n", np->dev->name, rp->mbox);
3996 return -EINVAL;
3997 }
3998
3999 rp->descr = np->ops->alloc_coherent(np->device,
4000 MAX_TX_RING_SIZE * sizeof(__le64),
4001 &rp->descr_dma, GFP_KERNEL);
4002 if (!rp->descr)
4003 return -ENOMEM;
4004 if ((unsigned long)rp->descr & (64UL - 1)) {
4005 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4006 "TXDMA descr table %p\n", np->dev->name, rp->descr);
4007 return -EINVAL;
4008 }
4009
4010 rp->pending = MAX_TX_RING_SIZE;
4011 rp->prod = 0;
4012 rp->cons = 0;
4013 rp->wrap_bit = 0;
4014
4015 /* XXX make these configurable... XXX */
4016 rp->mark_freq = rp->pending / 4;
4017
4018 niu_set_max_burst(np, rp);
4019
4020 return 0;
4021 }
4022
4023 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4024 {
4025 u16 bss;
4026
4027 bss = min(PAGE_SHIFT, 15);
4028
4029 rp->rbr_block_size = 1 << bss;
4030 rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
4031
4032 rp->rbr_sizes[0] = 256;
4033 rp->rbr_sizes[1] = 1024;
4034 if (np->dev->mtu > ETH_DATA_LEN) {
4035 switch (PAGE_SIZE) {
4036 case 4 * 1024:
4037 rp->rbr_sizes[2] = 4096;
4038 break;
4039
4040 default:
4041 rp->rbr_sizes[2] = 8192;
4042 break;
4043 }
4044 } else {
4045 rp->rbr_sizes[2] = 2048;
4046 }
4047 rp->rbr_sizes[3] = rp->rbr_block_size;
4048 }
4049
4050 static int niu_alloc_channels(struct niu *np)
4051 {
4052 struct niu_parent *parent = np->parent;
4053 int first_rx_channel, first_tx_channel;
4054 int i, port, err;
4055
4056 port = np->port;
4057 first_rx_channel = first_tx_channel = 0;
4058 for (i = 0; i < port; i++) {
4059 first_rx_channel += parent->rxchan_per_port[i];
4060 first_tx_channel += parent->txchan_per_port[i];
4061 }
4062
4063 np->num_rx_rings = parent->rxchan_per_port[port];
4064 np->num_tx_rings = parent->txchan_per_port[port];
4065
4066 np->dev->real_num_tx_queues = np->num_tx_rings;
4067
4068 np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
4069 GFP_KERNEL);
4070 err = -ENOMEM;
4071 if (!np->rx_rings)
4072 goto out_err;
4073
4074 for (i = 0; i < np->num_rx_rings; i++) {
4075 struct rx_ring_info *rp = &np->rx_rings[i];
4076
4077 rp->np = np;
4078 rp->rx_channel = first_rx_channel + i;
4079
4080 err = niu_alloc_rx_ring_info(np, rp);
4081 if (err)
4082 goto out_err;
4083
4084 niu_size_rbr(np, rp);
4085
4086 /* XXX better defaults, configurable, etc... XXX */
4087 rp->nonsyn_window = 64;
4088 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4089 rp->syn_window = 64;
4090 rp->syn_threshold = rp->rcr_table_size - 64;
4091 rp->rcr_pkt_threshold = 16;
4092 rp->rcr_timeout = 8;
4093 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4094 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4095 rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4096
4097 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4098 if (err)
4099 return err;
4100 }
4101
4102 np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
4103 GFP_KERNEL);
4104 err = -ENOMEM;
4105 if (!np->tx_rings)
4106 goto out_err;
4107
4108 for (i = 0; i < np->num_tx_rings; i++) {
4109 struct tx_ring_info *rp = &np->tx_rings[i];
4110
4111 rp->np = np;
4112 rp->tx_channel = first_tx_channel + i;
4113
4114 err = niu_alloc_tx_ring_info(np, rp);
4115 if (err)
4116 goto out_err;
4117 }
4118
4119 return 0;
4120
4121 out_err:
4122 niu_free_channels(np);
4123 return err;
4124 }
4125
4126 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4127 {
4128 int limit = 1000;
4129
4130 while (--limit > 0) {
4131 u64 val = nr64(TX_CS(channel));
4132 if (val & TX_CS_SNG_STATE)
4133 return 0;
4134 }
4135 return -ENODEV;
4136 }
4137
4138 static int niu_tx_channel_stop(struct niu *np, int channel)
4139 {
4140 u64 val = nr64(TX_CS(channel));
4141
4142 val |= TX_CS_STOP_N_GO;
4143 nw64(TX_CS(channel), val);
4144
4145 return niu_tx_cs_sng_poll(np, channel);
4146 }
4147
4148 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4149 {
4150 int limit = 1000;
4151
4152 while (--limit > 0) {
4153 u64 val = nr64(TX_CS(channel));
4154 if (!(val & TX_CS_RST))
4155 return 0;
4156 }
4157 return -ENODEV;
4158 }
4159
4160 static int niu_tx_channel_reset(struct niu *np, int channel)
4161 {
4162 u64 val = nr64(TX_CS(channel));
4163 int err;
4164
4165 val |= TX_CS_RST;
4166 nw64(TX_CS(channel), val);
4167
4168 err = niu_tx_cs_reset_poll(np, channel);
4169 if (!err)
4170 nw64(TX_RING_KICK(channel), 0);
4171
4172 return err;
4173 }
4174
4175 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4176 {
4177 u64 val;
4178
4179 nw64(TX_LOG_MASK1(channel), 0);
4180 nw64(TX_LOG_VAL1(channel), 0);
4181 nw64(TX_LOG_MASK2(channel), 0);
4182 nw64(TX_LOG_VAL2(channel), 0);
4183 nw64(TX_LOG_PAGE_RELO1(channel), 0);
4184 nw64(TX_LOG_PAGE_RELO2(channel), 0);
4185 nw64(TX_LOG_PAGE_HDL(channel), 0);
4186
4187 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4188 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4189 nw64(TX_LOG_PAGE_VLD(channel), val);
4190
4191 /* XXX TXDMA 32bit mode? XXX */
4192
4193 return 0;
4194 }
4195
4196 static void niu_txc_enable_port(struct niu *np, int on)
4197 {
4198 unsigned long flags;
4199 u64 val, mask;
4200
4201 niu_lock_parent(np, flags);
4202 val = nr64(TXC_CONTROL);
4203 mask = (u64)1 << np->port;
4204 if (on) {
4205 val |= TXC_CONTROL_ENABLE | mask;
4206 } else {
4207 val &= ~mask;
4208 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4209 val &= ~TXC_CONTROL_ENABLE;
4210 }
4211 nw64(TXC_CONTROL, val);
4212 niu_unlock_parent(np, flags);
4213 }
4214
4215 static void niu_txc_set_imask(struct niu *np, u64 imask)
4216 {
4217 unsigned long flags;
4218 u64 val;
4219
4220 niu_lock_parent(np, flags);
4221 val = nr64(TXC_INT_MASK);
4222 val &= ~TXC_INT_MASK_VAL(np->port);
4223 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4224 niu_unlock_parent(np, flags);
4225 }
4226
4227 static void niu_txc_port_dma_enable(struct niu *np, int on)
4228 {
4229 u64 val = 0;
4230
4231 if (on) {
4232 int i;
4233
4234 for (i = 0; i < np->num_tx_rings; i++)
4235 val |= (1 << np->tx_rings[i].tx_channel);
4236 }
4237 nw64(TXC_PORT_DMA(np->port), val);
4238 }
4239
4240 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4241 {
4242 int err, channel = rp->tx_channel;
4243 u64 val, ring_len;
4244
4245 err = niu_tx_channel_stop(np, channel);
4246 if (err)
4247 return err;
4248
4249 err = niu_tx_channel_reset(np, channel);
4250 if (err)
4251 return err;
4252
4253 err = niu_tx_channel_lpage_init(np, channel);
4254 if (err)
4255 return err;
4256
4257 nw64(TXC_DMA_MAX(channel), rp->max_burst);
4258 nw64(TX_ENT_MSK(channel), 0);
4259
4260 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4261 TX_RNG_CFIG_STADDR)) {
4262 dev_err(np->device, PFX "%s: TX ring channel %d "
4263 "DMA addr (%llx) is not aligned.\n",
4264 np->dev->name, channel,
4265 (unsigned long long) rp->descr_dma);
4266 return -EINVAL;
4267 }
4268
4269 /* The length field in TX_RNG_CFIG is measured in 64-byte
4270 * blocks. rp->pending is the number of TX descriptors in
4271 * our ring, 8 bytes each, thus we divide by 8 bytes more
4272 * to get the proper value the chip wants.
4273 */
4274 ring_len = (rp->pending / 8);
4275
4276 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4277 rp->descr_dma);
4278 nw64(TX_RNG_CFIG(channel), val);
4279
4280 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4281 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4282 dev_err(np->device, PFX "%s: TX ring channel %d "
4283 "MBOX addr (%llx) is has illegal bits.\n",
4284 np->dev->name, channel,
4285 (unsigned long long) rp->mbox_dma);
4286 return -EINVAL;
4287 }
4288 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4289 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4290
4291 nw64(TX_CS(channel), 0);
4292
4293 rp->last_pkt_cnt = 0;
4294
4295 return 0;
4296 }
4297
4298 static void niu_init_rdc_groups(struct niu *np)
4299 {
4300 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4301 int i, first_table_num = tp->first_table_num;
4302
4303 for (i = 0; i < tp->num_tables; i++) {
4304 struct rdc_table *tbl = &tp->tables[i];
4305 int this_table = first_table_num + i;
4306 int slot;
4307
4308 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4309 nw64(RDC_TBL(this_table, slot),
4310 tbl->rxdma_channel[slot]);
4311 }
4312
4313 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4314 }
4315
4316 static void niu_init_drr_weight(struct niu *np)
4317 {
4318 int type = phy_decode(np->parent->port_phy, np->port);
4319 u64 val;
4320
4321 switch (type) {
4322 case PORT_TYPE_10G:
4323 val = PT_DRR_WEIGHT_DEFAULT_10G;
4324 break;
4325
4326 case PORT_TYPE_1G:
4327 default:
4328 val = PT_DRR_WEIGHT_DEFAULT_1G;
4329 break;
4330 }
4331 nw64(PT_DRR_WT(np->port), val);
4332 }
4333
4334 static int niu_init_hostinfo(struct niu *np)
4335 {
4336 struct niu_parent *parent = np->parent;
4337 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4338 int i, err, num_alt = niu_num_alt_addr(np);
4339 int first_rdc_table = tp->first_table_num;
4340
4341 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4342 if (err)
4343 return err;
4344
4345 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4346 if (err)
4347 return err;
4348
4349 for (i = 0; i < num_alt; i++) {
4350 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4351 if (err)
4352 return err;
4353 }
4354
4355 return 0;
4356 }
4357
4358 static int niu_rx_channel_reset(struct niu *np, int channel)
4359 {
4360 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4361 RXDMA_CFIG1_RST, 1000, 10,
4362 "RXDMA_CFIG1");
4363 }
4364
4365 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4366 {
4367 u64 val;
4368
4369 nw64(RX_LOG_MASK1(channel), 0);
4370 nw64(RX_LOG_VAL1(channel), 0);
4371 nw64(RX_LOG_MASK2(channel), 0);
4372 nw64(RX_LOG_VAL2(channel), 0);
4373 nw64(RX_LOG_PAGE_RELO1(channel), 0);
4374 nw64(RX_LOG_PAGE_RELO2(channel), 0);
4375 nw64(RX_LOG_PAGE_HDL(channel), 0);
4376
4377 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4378 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4379 nw64(RX_LOG_PAGE_VLD(channel), val);
4380
4381 return 0;
4382 }
4383
4384 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4385 {
4386 u64 val;
4387
4388 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4389 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4390 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4391 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4392 nw64(RDC_RED_PARA(rp->rx_channel), val);
4393 }
4394
4395 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4396 {
4397 u64 val = 0;
4398
4399 switch (rp->rbr_block_size) {
4400 case 4 * 1024:
4401 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4402 break;
4403 case 8 * 1024:
4404 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4405 break;
4406 case 16 * 1024:
4407 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4408 break;
4409 case 32 * 1024:
4410 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4411 break;
4412 default:
4413 return -EINVAL;
4414 }
4415 val |= RBR_CFIG_B_VLD2;
4416 switch (rp->rbr_sizes[2]) {
4417 case 2 * 1024:
4418 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4419 break;
4420 case 4 * 1024:
4421 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4422 break;
4423 case 8 * 1024:
4424 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4425 break;
4426 case 16 * 1024:
4427 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4428 break;
4429
4430 default:
4431 return -EINVAL;
4432 }
4433 val |= RBR_CFIG_B_VLD1;
4434 switch (rp->rbr_sizes[1]) {
4435 case 1 * 1024:
4436 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4437 break;
4438 case 2 * 1024:
4439 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4440 break;
4441 case 4 * 1024:
4442 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4443 break;
4444 case 8 * 1024:
4445 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4446 break;
4447
4448 default:
4449 return -EINVAL;
4450 }
4451 val |= RBR_CFIG_B_VLD0;
4452 switch (rp->rbr_sizes[0]) {
4453 case 256:
4454 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4455 break;
4456 case 512:
4457 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4458 break;
4459 case 1 * 1024:
4460 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4461 break;
4462 case 2 * 1024:
4463 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4464 break;
4465
4466 default:
4467 return -EINVAL;
4468 }
4469
4470 *ret = val;
4471 return 0;
4472 }
4473
4474 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4475 {
4476 u64 val = nr64(RXDMA_CFIG1(channel));
4477 int limit;
4478
4479 if (on)
4480 val |= RXDMA_CFIG1_EN;
4481 else
4482 val &= ~RXDMA_CFIG1_EN;
4483 nw64(RXDMA_CFIG1(channel), val);
4484
4485 limit = 1000;
4486 while (--limit > 0) {
4487 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4488 break;
4489 udelay(10);
4490 }
4491 if (limit <= 0)
4492 return -ENODEV;
4493 return 0;
4494 }
4495
4496 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4497 {
4498 int err, channel = rp->rx_channel;
4499 u64 val;
4500
4501 err = niu_rx_channel_reset(np, channel);
4502 if (err)
4503 return err;
4504
4505 err = niu_rx_channel_lpage_init(np, channel);
4506 if (err)
4507 return err;
4508
4509 niu_rx_channel_wred_init(np, rp);
4510
4511 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4512 nw64(RX_DMA_CTL_STAT(channel),
4513 (RX_DMA_CTL_STAT_MEX |
4514 RX_DMA_CTL_STAT_RCRTHRES |
4515 RX_DMA_CTL_STAT_RCRTO |
4516 RX_DMA_CTL_STAT_RBR_EMPTY));
4517 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4518 nw64(RXDMA_CFIG2(channel), (rp->mbox_dma & 0x00000000ffffffc0));
4519 nw64(RBR_CFIG_A(channel),
4520 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4521 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4522 err = niu_compute_rbr_cfig_b(rp, &val);
4523 if (err)
4524 return err;
4525 nw64(RBR_CFIG_B(channel), val);
4526 nw64(RCRCFIG_A(channel),
4527 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4528 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4529 nw64(RCRCFIG_B(channel),
4530 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4531 RCRCFIG_B_ENTOUT |
4532 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4533
4534 err = niu_enable_rx_channel(np, channel, 1);
4535 if (err)
4536 return err;
4537
4538 nw64(RBR_KICK(channel), rp->rbr_index);
4539
4540 val = nr64(RX_DMA_CTL_STAT(channel));
4541 val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4542 nw64(RX_DMA_CTL_STAT(channel), val);
4543
4544 return 0;
4545 }
4546
4547 static int niu_init_rx_channels(struct niu *np)
4548 {
4549 unsigned long flags;
4550 u64 seed = jiffies_64;
4551 int err, i;
4552
4553 niu_lock_parent(np, flags);
4554 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4555 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4556 niu_unlock_parent(np, flags);
4557
4558 /* XXX RXDMA 32bit mode? XXX */
4559
4560 niu_init_rdc_groups(np);
4561 niu_init_drr_weight(np);
4562
4563 err = niu_init_hostinfo(np);
4564 if (err)
4565 return err;
4566
4567 for (i = 0; i < np->num_rx_rings; i++) {
4568 struct rx_ring_info *rp = &np->rx_rings[i];
4569
4570 err = niu_init_one_rx_channel(np, rp);
4571 if (err)
4572 return err;
4573 }
4574
4575 return 0;
4576 }
4577
4578 static int niu_set_ip_frag_rule(struct niu *np)
4579 {
4580 struct niu_parent *parent = np->parent;
4581 struct niu_classifier *cp = &np->clas;
4582 struct niu_tcam_entry *tp;
4583 int index, err;
4584
4585 /* XXX fix this allocation scheme XXX */
4586 index = cp->tcam_index;
4587 tp = &parent->tcam[index];
4588
4589 /* Note that the noport bit is the same in both ipv4 and
4590 * ipv6 format TCAM entries.
4591 */
4592 memset(tp, 0, sizeof(*tp));
4593 tp->key[1] = TCAM_V4KEY1_NOPORT;
4594 tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
4595 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
4596 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
4597 err = tcam_write(np, index, tp->key, tp->key_mask);
4598 if (err)
4599 return err;
4600 err = tcam_assoc_write(np, index, tp->assoc_data);
4601 if (err)
4602 return err;
4603
4604 return 0;
4605 }
4606
4607 static int niu_init_classifier_hw(struct niu *np)
4608 {
4609 struct niu_parent *parent = np->parent;
4610 struct niu_classifier *cp = &np->clas;
4611 int i, err;
4612
4613 nw64(H1POLY, cp->h1_init);
4614 nw64(H2POLY, cp->h2_init);
4615
4616 err = niu_init_hostinfo(np);
4617 if (err)
4618 return err;
4619
4620 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
4621 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
4622
4623 vlan_tbl_write(np, i, np->port,
4624 vp->vlan_pref, vp->rdc_num);
4625 }
4626
4627 for (i = 0; i < cp->num_alt_mac_mappings; i++) {
4628 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
4629
4630 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
4631 ap->rdc_num, ap->mac_pref);
4632 if (err)
4633 return err;
4634 }
4635
4636 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
4637 int index = i - CLASS_CODE_USER_PROG1;
4638
4639 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
4640 if (err)
4641 return err;
4642 err = niu_set_flow_key(np, i, parent->flow_key[index]);
4643 if (err)
4644 return err;
4645 }
4646
4647 err = niu_set_ip_frag_rule(np);
4648 if (err)
4649 return err;
4650
4651 tcam_enable(np, 1);
4652
4653 return 0;
4654 }
4655
4656 static int niu_zcp_write(struct niu *np, int index, u64 *data)
4657 {
4658 nw64(ZCP_RAM_DATA0, data[0]);
4659 nw64(ZCP_RAM_DATA1, data[1]);
4660 nw64(ZCP_RAM_DATA2, data[2]);
4661 nw64(ZCP_RAM_DATA3, data[3]);
4662 nw64(ZCP_RAM_DATA4, data[4]);
4663 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
4664 nw64(ZCP_RAM_ACC,
4665 (ZCP_RAM_ACC_WRITE |
4666 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
4667 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
4668
4669 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
4670 1000, 100);
4671 }
4672
4673 static int niu_zcp_read(struct niu *np, int index, u64 *data)
4674 {
4675 int err;
4676
4677 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
4678 1000, 100);
4679 if (err) {
4680 dev_err(np->device, PFX "%s: ZCP read busy won't clear, "
4681 "ZCP_RAM_ACC[%llx]\n", np->dev->name,
4682 (unsigned long long) nr64(ZCP_RAM_ACC));
4683 return err;
4684 }
4685
4686 nw64(ZCP_RAM_ACC,
4687 (ZCP_RAM_ACC_READ |
4688 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
4689 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
4690
4691 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
4692 1000, 100);
4693 if (err) {
4694 dev_err(np->device, PFX "%s: ZCP read busy2 won't clear, "
4695 "ZCP_RAM_ACC[%llx]\n", np->dev->name,
4696 (unsigned long long) nr64(ZCP_RAM_ACC));
4697 return err;
4698 }
4699
4700 data[0] = nr64(ZCP_RAM_DATA0);
4701 data[1] = nr64(ZCP_RAM_DATA1);
4702 data[2] = nr64(ZCP_RAM_DATA2);
4703 data[3] = nr64(ZCP_RAM_DATA3);
4704 data[4] = nr64(ZCP_RAM_DATA4);
4705
4706 return 0;
4707 }
4708
4709 static void niu_zcp_cfifo_reset(struct niu *np)
4710 {
4711 u64 val = nr64(RESET_CFIFO);
4712
4713 val |= RESET_CFIFO_RST(np->port);
4714 nw64(RESET_CFIFO, val);
4715 udelay(10);
4716
4717 val &= ~RESET_CFIFO_RST(np->port);
4718 nw64(RESET_CFIFO, val);
4719 }
4720
4721 static int niu_init_zcp(struct niu *np)
4722 {
4723 u64 data[5], rbuf[5];
4724 int i, max, err;
4725
4726 if (np->parent->plat_type != PLAT_TYPE_NIU) {
4727 if (np->port == 0 || np->port == 1)
4728 max = ATLAS_P0_P1_CFIFO_ENTRIES;
4729 else
4730 max = ATLAS_P2_P3_CFIFO_ENTRIES;
4731 } else
4732 max = NIU_CFIFO_ENTRIES;
4733
4734 data[0] = 0;
4735 data[1] = 0;
4736 data[2] = 0;
4737 data[3] = 0;
4738 data[4] = 0;
4739
4740 for (i = 0; i < max; i++) {
4741 err = niu_zcp_write(np, i, data);
4742 if (err)
4743 return err;
4744 err = niu_zcp_read(np, i, rbuf);
4745 if (err)
4746 return err;
4747 }
4748
4749 niu_zcp_cfifo_reset(np);
4750 nw64(CFIFO_ECC(np->port), 0);
4751 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
4752 (void) nr64(ZCP_INT_STAT);
4753 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
4754
4755 return 0;
4756 }
4757
4758 static void niu_ipp_write(struct niu *np, int index, u64 *data)
4759 {
4760 u64 val = nr64_ipp(IPP_CFIG);
4761
4762 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
4763 nw64_ipp(IPP_DFIFO_WR_PTR, index);
4764 nw64_ipp(IPP_DFIFO_WR0, data[0]);
4765 nw64_ipp(IPP_DFIFO_WR1, data[1]);
4766 nw64_ipp(IPP_DFIFO_WR2, data[2]);
4767 nw64_ipp(IPP_DFIFO_WR3, data[3]);
4768 nw64_ipp(IPP_DFIFO_WR4, data[4]);
4769 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
4770 }
4771
4772 static void niu_ipp_read(struct niu *np, int index, u64 *data)
4773 {
4774 nw64_ipp(IPP_DFIFO_RD_PTR, index);
4775 data[0] = nr64_ipp(IPP_DFIFO_RD0);
4776 data[1] = nr64_ipp(IPP_DFIFO_RD1);
4777 data[2] = nr64_ipp(IPP_DFIFO_RD2);
4778 data[3] = nr64_ipp(IPP_DFIFO_RD3);
4779 data[4] = nr64_ipp(IPP_DFIFO_RD4);
4780 }
4781
4782 static int niu_ipp_reset(struct niu *np)
4783 {
4784 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
4785 1000, 100, "IPP_CFIG");
4786 }
4787
4788 static int niu_init_ipp(struct niu *np)
4789 {
4790 u64 data[5], rbuf[5], val;
4791 int i, max, err;
4792
4793 if (np->parent->plat_type != PLAT_TYPE_NIU) {
4794 if (np->port == 0 || np->port == 1)
4795 max = ATLAS_P0_P1_DFIFO_ENTRIES;
4796 else
4797 max = ATLAS_P2_P3_DFIFO_ENTRIES;
4798 } else
4799 max = NIU_DFIFO_ENTRIES;
4800
4801 data[0] = 0;
4802 data[1] = 0;
4803 data[2] = 0;
4804 data[3] = 0;
4805 data[4] = 0;
4806
4807 for (i = 0; i < max; i++) {
4808 niu_ipp_write(np, i, data);
4809 niu_ipp_read(np, i, rbuf);
4810 }
4811
4812 (void) nr64_ipp(IPP_INT_STAT);
4813 (void) nr64_ipp(IPP_INT_STAT);
4814
4815 err = niu_ipp_reset(np);
4816 if (err)
4817 return err;
4818
4819 (void) nr64_ipp(IPP_PKT_DIS);
4820 (void) nr64_ipp(IPP_BAD_CS_CNT);
4821 (void) nr64_ipp(IPP_ECC);
4822
4823 (void) nr64_ipp(IPP_INT_STAT);
4824
4825 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
4826
4827 val = nr64_ipp(IPP_CFIG);
4828 val &= ~IPP_CFIG_IP_MAX_PKT;
4829 val |= (IPP_CFIG_IPP_ENABLE |
4830 IPP_CFIG_DFIFO_ECC_EN |
4831 IPP_CFIG_DROP_BAD_CRC |
4832 IPP_CFIG_CKSUM_EN |
4833 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
4834 nw64_ipp(IPP_CFIG, val);
4835
4836 return 0;
4837 }
4838
4839 static void niu_handle_led(struct niu *np, int status)
4840 {
4841 u64 val;
4842 val = nr64_mac(XMAC_CONFIG);
4843
4844 if ((np->flags & NIU_FLAGS_10G) != 0 &&
4845 (np->flags & NIU_FLAGS_FIBER) != 0) {
4846 if (status) {
4847 val |= XMAC_CONFIG_LED_POLARITY;
4848 val &= ~XMAC_CONFIG_FORCE_LED_ON;
4849 } else {
4850 val |= XMAC_CONFIG_FORCE_LED_ON;
4851 val &= ~XMAC_CONFIG_LED_POLARITY;
4852 }
4853 }
4854
4855 nw64_mac(XMAC_CONFIG, val);
4856 }
4857
4858 static void niu_init_xif_xmac(struct niu *np)
4859 {
4860 struct niu_link_config *lp = &np->link_config;
4861 u64 val;
4862
4863 if (np->flags & NIU_FLAGS_XCVR_SERDES) {
4864 val = nr64(MIF_CONFIG);
4865 val |= MIF_CONFIG_ATCA_GE;
4866 nw64(MIF_CONFIG, val);
4867 }
4868
4869 val = nr64_mac(XMAC_CONFIG);
4870 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
4871
4872 val |= XMAC_CONFIG_TX_OUTPUT_EN;
4873
4874 if (lp->loopback_mode == LOOPBACK_MAC) {
4875 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
4876 val |= XMAC_CONFIG_LOOPBACK;
4877 } else {
4878 val &= ~XMAC_CONFIG_LOOPBACK;
4879 }
4880
4881 if (np->flags & NIU_FLAGS_10G) {
4882 val &= ~XMAC_CONFIG_LFS_DISABLE;
4883 } else {
4884 val |= XMAC_CONFIG_LFS_DISABLE;
4885 if (!(np->flags & NIU_FLAGS_FIBER) &&
4886 !(np->flags & NIU_FLAGS_XCVR_SERDES))
4887 val |= XMAC_CONFIG_1G_PCS_BYPASS;
4888 else
4889 val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
4890 }
4891
4892 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
4893
4894 if (lp->active_speed == SPEED_100)
4895 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
4896 else
4897 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
4898
4899 nw64_mac(XMAC_CONFIG, val);
4900
4901 val = nr64_mac(XMAC_CONFIG);
4902 val &= ~XMAC_CONFIG_MODE_MASK;
4903 if (np->flags & NIU_FLAGS_10G) {
4904 val |= XMAC_CONFIG_MODE_XGMII;
4905 } else {
4906 if (lp->active_speed == SPEED_100)
4907 val |= XMAC_CONFIG_MODE_MII;
4908 else
4909 val |= XMAC_CONFIG_MODE_GMII;
4910 }
4911
4912 nw64_mac(XMAC_CONFIG, val);
4913 }
4914
4915 static void niu_init_xif_bmac(struct niu *np)
4916 {
4917 struct niu_link_config *lp = &np->link_config;
4918 u64 val;
4919
4920 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
4921
4922 if (lp->loopback_mode == LOOPBACK_MAC)
4923 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
4924 else
4925 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
4926
4927 if (lp->active_speed == SPEED_1000)
4928 val |= BMAC_XIF_CONFIG_GMII_MODE;
4929 else
4930 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
4931
4932 val &= ~(BMAC_XIF_CONFIG_LINK_LED |
4933 BMAC_XIF_CONFIG_LED_POLARITY);
4934
4935 if (!(np->flags & NIU_FLAGS_10G) &&
4936 !(np->flags & NIU_FLAGS_FIBER) &&
4937 lp->active_speed == SPEED_100)
4938 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
4939 else
4940 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
4941
4942 nw64_mac(BMAC_XIF_CONFIG, val);
4943 }
4944
4945 static void niu_init_xif(struct niu *np)
4946 {
4947 if (np->flags & NIU_FLAGS_XMAC)
4948 niu_init_xif_xmac(np);
4949 else
4950 niu_init_xif_bmac(np);
4951 }
4952
4953 static void niu_pcs_mii_reset(struct niu *np)
4954 {
4955 int limit = 1000;
4956 u64 val = nr64_pcs(PCS_MII_CTL);
4957 val |= PCS_MII_CTL_RST;
4958 nw64_pcs(PCS_MII_CTL, val);
4959 while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
4960 udelay(100);
4961 val = nr64_pcs(PCS_MII_CTL);
4962 }
4963 }
4964
4965 static void niu_xpcs_reset(struct niu *np)
4966 {
4967 int limit = 1000;
4968 u64 val = nr64_xpcs(XPCS_CONTROL1);
4969 val |= XPCS_CONTROL1_RESET;
4970 nw64_xpcs(XPCS_CONTROL1, val);
4971 while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
4972 udelay(100);
4973 val = nr64_xpcs(XPCS_CONTROL1);
4974 }
4975 }
4976
4977 static int niu_init_pcs(struct niu *np)
4978 {
4979 struct niu_link_config *lp = &np->link_config;
4980 u64 val;
4981
4982 switch (np->flags & (NIU_FLAGS_10G |
4983 NIU_FLAGS_FIBER |
4984 NIU_FLAGS_XCVR_SERDES)) {
4985 case NIU_FLAGS_FIBER:
4986 /* 1G fiber */
4987 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
4988 nw64_pcs(PCS_DPATH_MODE, 0);
4989 niu_pcs_mii_reset(np);
4990 break;
4991
4992 case NIU_FLAGS_10G:
4993 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
4994 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
4995 /* 10G SERDES */
4996 if (!(np->flags & NIU_FLAGS_XMAC))
4997 return -EINVAL;
4998
4999 /* 10G copper or fiber */
5000 val = nr64_mac(XMAC_CONFIG);
5001 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5002 nw64_mac(XMAC_CONFIG, val);
5003
5004 niu_xpcs_reset(np);
5005
5006 val = nr64_xpcs(XPCS_CONTROL1);
5007 if (lp->loopback_mode == LOOPBACK_PHY)
5008 val |= XPCS_CONTROL1_LOOPBACK;
5009 else
5010 val &= ~XPCS_CONTROL1_LOOPBACK;
5011 nw64_xpcs(XPCS_CONTROL1, val);
5012
5013 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5014 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5015 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5016 break;
5017
5018
5019 case NIU_FLAGS_XCVR_SERDES:
5020 /* 1G SERDES */
5021 niu_pcs_mii_reset(np);
5022 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5023 nw64_pcs(PCS_DPATH_MODE, 0);
5024 break;
5025
5026 case 0:
5027 /* 1G copper */
5028 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5029 /* 1G RGMII FIBER */
5030 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5031 niu_pcs_mii_reset(np);
5032 break;
5033
5034 default:
5035 return -EINVAL;
5036 }
5037
5038 return 0;
5039 }
5040
5041 static int niu_reset_tx_xmac(struct niu *np)
5042 {
5043 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5044 (XTXMAC_SW_RST_REG_RS |
5045 XTXMAC_SW_RST_SOFT_RST),
5046 1000, 100, "XTXMAC_SW_RST");
5047 }
5048
5049 static int niu_reset_tx_bmac(struct niu *np)
5050 {
5051 int limit;
5052
5053 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5054 limit = 1000;
5055 while (--limit >= 0) {
5056 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5057 break;
5058 udelay(100);
5059 }
5060 if (limit < 0) {
5061 dev_err(np->device, PFX "Port %u TX BMAC would not reset, "
5062 "BTXMAC_SW_RST[%llx]\n",
5063 np->port,
5064 (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5065 return -ENODEV;
5066 }
5067
5068 return 0;
5069 }
5070
5071 static int niu_reset_tx_mac(struct niu *np)
5072 {
5073 if (np->flags & NIU_FLAGS_XMAC)
5074 return niu_reset_tx_xmac(np);
5075 else
5076 return niu_reset_tx_bmac(np);
5077 }
5078
5079 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5080 {
5081 u64 val;
5082
5083 val = nr64_mac(XMAC_MIN);
5084 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5085 XMAC_MIN_RX_MIN_PKT_SIZE);
5086 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5087 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5088 nw64_mac(XMAC_MIN, val);
5089
5090 nw64_mac(XMAC_MAX, max);
5091
5092 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5093
5094 val = nr64_mac(XMAC_IPG);
5095 if (np->flags & NIU_FLAGS_10G) {
5096 val &= ~XMAC_IPG_IPG_XGMII;
5097 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5098 } else {
5099 val &= ~XMAC_IPG_IPG_MII_GMII;
5100 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5101 }
5102 nw64_mac(XMAC_IPG, val);
5103
5104 val = nr64_mac(XMAC_CONFIG);
5105 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5106 XMAC_CONFIG_STRETCH_MODE |
5107 XMAC_CONFIG_VAR_MIN_IPG_EN |
5108 XMAC_CONFIG_TX_ENABLE);
5109 nw64_mac(XMAC_CONFIG, val);
5110
5111 nw64_mac(TXMAC_FRM_CNT, 0);
5112 nw64_mac(TXMAC_BYTE_CNT, 0);
5113 }
5114
5115 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5116 {
5117 u64 val;
5118
5119 nw64_mac(BMAC_MIN_FRAME, min);
5120 nw64_mac(BMAC_MAX_FRAME, max);
5121
5122 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5123 nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5124 nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5125
5126 val = nr64_mac(BTXMAC_CONFIG);
5127 val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5128 BTXMAC_CONFIG_ENABLE);
5129 nw64_mac(BTXMAC_CONFIG, val);
5130 }
5131
5132 static void niu_init_tx_mac(struct niu *np)
5133 {
5134 u64 min, max;
5135
5136 min = 64;
5137 if (np->dev->mtu > ETH_DATA_LEN)
5138 max = 9216;
5139 else
5140 max = 1522;
5141
5142 /* The XMAC_MIN register only accepts values for TX min which
5143 * have the low 3 bits cleared.
5144 */
5145 BUILD_BUG_ON(min & 0x7);
5146
5147 if (np->flags & NIU_FLAGS_XMAC)
5148 niu_init_tx_xmac(np, min, max);
5149 else
5150 niu_init_tx_bmac(np, min, max);
5151 }
5152
5153 static int niu_reset_rx_xmac(struct niu *np)
5154 {
5155 int limit;
5156
5157 nw64_mac(XRXMAC_SW_RST,
5158 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5159 limit = 1000;
5160 while (--limit >= 0) {
5161 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5162 XRXMAC_SW_RST_SOFT_RST)))
5163 break;
5164 udelay(100);
5165 }
5166 if (limit < 0) {
5167 dev_err(np->device, PFX "Port %u RX XMAC would not reset, "
5168 "XRXMAC_SW_RST[%llx]\n",
5169 np->port,
5170 (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5171 return -ENODEV;
5172 }
5173
5174 return 0;
5175 }
5176
5177 static int niu_reset_rx_bmac(struct niu *np)
5178 {
5179 int limit;
5180
5181 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5182 limit = 1000;
5183 while (--limit >= 0) {
5184 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5185 break;
5186 udelay(100);
5187 }
5188 if (limit < 0) {
5189 dev_err(np->device, PFX "Port %u RX BMAC would not reset, "
5190 "BRXMAC_SW_RST[%llx]\n",
5191 np->port,
5192 (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5193 return -ENODEV;
5194 }
5195
5196 return 0;
5197 }
5198
5199 static int niu_reset_rx_mac(struct niu *np)
5200 {
5201 if (np->flags & NIU_FLAGS_XMAC)
5202 return niu_reset_rx_xmac(np);
5203 else
5204 return niu_reset_rx_bmac(np);
5205 }
5206
5207 static void niu_init_rx_xmac(struct niu *np)
5208 {
5209 struct niu_parent *parent = np->parent;
5210 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5211 int first_rdc_table = tp->first_table_num;
5212 unsigned long i;
5213 u64 val;
5214
5215 nw64_mac(XMAC_ADD_FILT0, 0);
5216 nw64_mac(XMAC_ADD_FILT1, 0);
5217 nw64_mac(XMAC_ADD_FILT2, 0);
5218 nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5219 nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5220 for (i = 0; i < MAC_NUM_HASH; i++)
5221 nw64_mac(XMAC_HASH_TBL(i), 0);
5222 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5223 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5224 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5225
5226 val = nr64_mac(XMAC_CONFIG);
5227 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5228 XMAC_CONFIG_PROMISCUOUS |
5229 XMAC_CONFIG_PROMISC_GROUP |
5230 XMAC_CONFIG_ERR_CHK_DIS |
5231 XMAC_CONFIG_RX_CRC_CHK_DIS |
5232 XMAC_CONFIG_RESERVED_MULTICAST |
5233 XMAC_CONFIG_RX_CODEV_CHK_DIS |
5234 XMAC_CONFIG_ADDR_FILTER_EN |
5235 XMAC_CONFIG_RCV_PAUSE_ENABLE |
5236 XMAC_CONFIG_STRIP_CRC |
5237 XMAC_CONFIG_PASS_FLOW_CTRL |
5238 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5239 val |= (XMAC_CONFIG_HASH_FILTER_EN);
5240 nw64_mac(XMAC_CONFIG, val);
5241
5242 nw64_mac(RXMAC_BT_CNT, 0);
5243 nw64_mac(RXMAC_BC_FRM_CNT, 0);
5244 nw64_mac(RXMAC_MC_FRM_CNT, 0);
5245 nw64_mac(RXMAC_FRAG_CNT, 0);
5246 nw64_mac(RXMAC_HIST_CNT1, 0);
5247 nw64_mac(RXMAC_HIST_CNT2, 0);
5248 nw64_mac(RXMAC_HIST_CNT3, 0);
5249 nw64_mac(RXMAC_HIST_CNT4, 0);
5250 nw64_mac(RXMAC_HIST_CNT5, 0);
5251 nw64_mac(RXMAC_HIST_CNT6, 0);
5252 nw64_mac(RXMAC_HIST_CNT7, 0);
5253 nw64_mac(RXMAC_MPSZER_CNT, 0);
5254 nw64_mac(RXMAC_CRC_ER_CNT, 0);
5255 nw64_mac(RXMAC_CD_VIO_CNT, 0);
5256 nw64_mac(LINK_FAULT_CNT, 0);
5257 }
5258
5259 static void niu_init_rx_bmac(struct niu *np)
5260 {
5261 struct niu_parent *parent = np->parent;
5262 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5263 int first_rdc_table = tp->first_table_num;
5264 unsigned long i;
5265 u64 val;
5266
5267 nw64_mac(BMAC_ADD_FILT0, 0);
5268 nw64_mac(BMAC_ADD_FILT1, 0);
5269 nw64_mac(BMAC_ADD_FILT2, 0);
5270 nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5271 nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5272 for (i = 0; i < MAC_NUM_HASH; i++)
5273 nw64_mac(BMAC_HASH_TBL(i), 0);
5274 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5275 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5276 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5277
5278 val = nr64_mac(BRXMAC_CONFIG);
5279 val &= ~(BRXMAC_CONFIG_ENABLE |
5280 BRXMAC_CONFIG_STRIP_PAD |
5281 BRXMAC_CONFIG_STRIP_FCS |
5282 BRXMAC_CONFIG_PROMISC |
5283 BRXMAC_CONFIG_PROMISC_GRP |
5284 BRXMAC_CONFIG_ADDR_FILT_EN |
5285 BRXMAC_CONFIG_DISCARD_DIS);
5286 val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5287 nw64_mac(BRXMAC_CONFIG, val);
5288
5289 val = nr64_mac(BMAC_ADDR_CMPEN);
5290 val |= BMAC_ADDR_CMPEN_EN0;
5291 nw64_mac(BMAC_ADDR_CMPEN, val);
5292 }
5293
5294 static void niu_init_rx_mac(struct niu *np)
5295 {
5296 niu_set_primary_mac(np, np->dev->dev_addr);
5297
5298 if (np->flags & NIU_FLAGS_XMAC)
5299 niu_init_rx_xmac(np);
5300 else
5301 niu_init_rx_bmac(np);
5302 }
5303
5304 static void niu_enable_tx_xmac(struct niu *np, int on)
5305 {
5306 u64 val = nr64_mac(XMAC_CONFIG);
5307
5308 if (on)
5309 val |= XMAC_CONFIG_TX_ENABLE;
5310 else
5311 val &= ~XMAC_CONFIG_TX_ENABLE;
5312 nw64_mac(XMAC_CONFIG, val);
5313 }
5314
5315 static void niu_enable_tx_bmac(struct niu *np, int on)
5316 {
5317 u64 val = nr64_mac(BTXMAC_CONFIG);
5318
5319 if (on)
5320 val |= BTXMAC_CONFIG_ENABLE;
5321 else
5322 val &= ~BTXMAC_CONFIG_ENABLE;
5323 nw64_mac(BTXMAC_CONFIG, val);
5324 }
5325
5326 static void niu_enable_tx_mac(struct niu *np, int on)
5327 {
5328 if (np->flags & NIU_FLAGS_XMAC)
5329 niu_enable_tx_xmac(np, on);
5330 else
5331 niu_enable_tx_bmac(np, on);
5332 }
5333
5334 static void niu_enable_rx_xmac(struct niu *np, int on)
5335 {
5336 u64 val = nr64_mac(XMAC_CONFIG);
5337
5338 val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5339 XMAC_CONFIG_PROMISCUOUS);
5340
5341 if (np->flags & NIU_FLAGS_MCAST)
5342 val |= XMAC_CONFIG_HASH_FILTER_EN;
5343 if (np->flags & NIU_FLAGS_PROMISC)
5344 val |= XMAC_CONFIG_PROMISCUOUS;
5345
5346 if (on)
5347 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5348 else
5349 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5350 nw64_mac(XMAC_CONFIG, val);
5351 }
5352
5353 static void niu_enable_rx_bmac(struct niu *np, int on)
5354 {
5355 u64 val = nr64_mac(BRXMAC_CONFIG);
5356
5357 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5358 BRXMAC_CONFIG_PROMISC);
5359
5360 if (np->flags & NIU_FLAGS_MCAST)
5361 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5362 if (np->flags & NIU_FLAGS_PROMISC)
5363 val |= BRXMAC_CONFIG_PROMISC;
5364
5365 if (on)
5366 val |= BRXMAC_CONFIG_ENABLE;
5367 else
5368 val &= ~BRXMAC_CONFIG_ENABLE;
5369 nw64_mac(BRXMAC_CONFIG, val);
5370 }
5371
5372 static void niu_enable_rx_mac(struct niu *np, int on)
5373 {
5374 if (np->flags & NIU_FLAGS_XMAC)
5375 niu_enable_rx_xmac(np, on);
5376 else
5377 niu_enable_rx_bmac(np, on);
5378 }
5379
5380 static int niu_init_mac(struct niu *np)
5381 {
5382 int err;
5383
5384 niu_init_xif(np);
5385 err = niu_init_pcs(np);
5386 if (err)
5387 return err;
5388
5389 err = niu_reset_tx_mac(np);
5390 if (err)
5391 return err;
5392 niu_init_tx_mac(np);
5393 err = niu_reset_rx_mac(np);
5394 if (err)
5395 return err;
5396 niu_init_rx_mac(np);
5397
5398 /* This looks hookey but the RX MAC reset we just did will
5399 * undo some of the state we setup in niu_init_tx_mac() so we
5400 * have to call it again. In particular, the RX MAC reset will
5401 * set the XMAC_MAX register back to it's default value.
5402 */
5403 niu_init_tx_mac(np);
5404 niu_enable_tx_mac(np, 1);
5405
5406 niu_enable_rx_mac(np, 1);
5407
5408 return 0;
5409 }
5410
5411 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5412 {
5413 (void) niu_tx_channel_stop(np, rp->tx_channel);
5414 }
5415
5416 static void niu_stop_tx_channels(struct niu *np)
5417 {
5418 int i;
5419
5420 for (i = 0; i < np->num_tx_rings; i++) {
5421 struct tx_ring_info *rp = &np->tx_rings[i];
5422
5423 niu_stop_one_tx_channel(np, rp);
5424 }
5425 }
5426
5427 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5428 {
5429 (void) niu_tx_channel_reset(np, rp->tx_channel);
5430 }
5431
5432 static void niu_reset_tx_channels(struct niu *np)
5433 {
5434 int i;
5435
5436 for (i = 0; i < np->num_tx_rings; i++) {
5437 struct tx_ring_info *rp = &np->tx_rings[i];
5438
5439 niu_reset_one_tx_channel(np, rp);
5440 }
5441 }
5442
5443 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5444 {
5445 (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5446 }
5447
5448 static void niu_stop_rx_channels(struct niu *np)
5449 {
5450 int i;
5451
5452 for (i = 0; i < np->num_rx_rings; i++) {
5453 struct rx_ring_info *rp = &np->rx_rings[i];
5454
5455 niu_stop_one_rx_channel(np, rp);
5456 }
5457 }
5458
5459 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5460 {
5461 int channel = rp->rx_channel;
5462
5463 (void) niu_rx_channel_reset(np, channel);
5464 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5465 nw64(RX_DMA_CTL_STAT(channel), 0);
5466 (void) niu_enable_rx_channel(np, channel, 0);
5467 }
5468
5469 static void niu_reset_rx_channels(struct niu *np)
5470 {
5471 int i;
5472
5473 for (i = 0; i < np->num_rx_rings; i++) {
5474 struct rx_ring_info *rp = &np->rx_rings[i];
5475
5476 niu_reset_one_rx_channel(np, rp);
5477 }
5478 }
5479
5480 static void niu_disable_ipp(struct niu *np)
5481 {
5482 u64 rd, wr, val;
5483 int limit;
5484
5485 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5486 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5487 limit = 100;
5488 while (--limit >= 0 && (rd != wr)) {
5489 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5490 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5491 }
5492 if (limit < 0 &&
5493 (rd != 0 && wr != 1)) {
5494 dev_err(np->device, PFX "%s: IPP would not quiesce, "
5495 "rd_ptr[%llx] wr_ptr[%llx]\n",
5496 np->dev->name,
5497 (unsigned long long) nr64_ipp(IPP_DFIFO_RD_PTR),
5498 (unsigned long long) nr64_ipp(IPP_DFIFO_WR_PTR));
5499 }
5500
5501 val = nr64_ipp(IPP_CFIG);
5502 val &= ~(IPP_CFIG_IPP_ENABLE |
5503 IPP_CFIG_DFIFO_ECC_EN |
5504 IPP_CFIG_DROP_BAD_CRC |
5505 IPP_CFIG_CKSUM_EN);
5506 nw64_ipp(IPP_CFIG, val);
5507
5508 (void) niu_ipp_reset(np);
5509 }
5510
5511 static int niu_init_hw(struct niu *np)
5512 {
5513 int i, err;
5514
5515 niudbg(IFUP, "%s: Initialize TXC\n", np->dev->name);
5516 niu_txc_enable_port(np, 1);
5517 niu_txc_port_dma_enable(np, 1);
5518 niu_txc_set_imask(np, 0);
5519
5520 niudbg(IFUP, "%s: Initialize TX channels\n", np->dev->name);
5521 for (i = 0; i < np->num_tx_rings; i++) {
5522 struct tx_ring_info *rp = &np->tx_rings[i];
5523
5524 err = niu_init_one_tx_channel(np, rp);
5525 if (err)
5526 return err;
5527 }
5528
5529 niudbg(IFUP, "%s: Initialize RX channels\n", np->dev->name);
5530 err = niu_init_rx_channels(np);
5531 if (err)
5532 goto out_uninit_tx_channels;
5533
5534 niudbg(IFUP, "%s: Initialize classifier\n", np->dev->name);
5535 err = niu_init_classifier_hw(np);
5536 if (err)
5537 goto out_uninit_rx_channels;
5538
5539 niudbg(IFUP, "%s: Initialize ZCP\n", np->dev->name);
5540 err = niu_init_zcp(np);
5541 if (err)
5542 goto out_uninit_rx_channels;
5543
5544 niudbg(IFUP, "%s: Initialize IPP\n", np->dev->name);
5545 err = niu_init_ipp(np);
5546 if (err)
5547 goto out_uninit_rx_channels;
5548
5549 niudbg(IFUP, "%s: Initialize MAC\n", np->dev->name);
5550 err = niu_init_mac(np);
5551 if (err)
5552 goto out_uninit_ipp;
5553
5554 return 0;
5555
5556 out_uninit_ipp:
5557 niudbg(IFUP, "%s: Uninit IPP\n", np->dev->name);
5558 niu_disable_ipp(np);
5559
5560 out_uninit_rx_channels:
5561 niudbg(IFUP, "%s: Uninit RX channels\n", np->dev->name);
5562 niu_stop_rx_channels(np);
5563 niu_reset_rx_channels(np);
5564
5565 out_uninit_tx_channels:
5566 niudbg(IFUP, "%s: Uninit TX channels\n", np->dev->name);
5567 niu_stop_tx_channels(np);
5568 niu_reset_tx_channels(np);
5569
5570 return err;
5571 }
5572
5573 static void niu_stop_hw(struct niu *np)
5574 {
5575 niudbg(IFDOWN, "%s: Disable interrupts\n", np->dev->name);
5576 niu_enable_interrupts(np, 0);
5577
5578 niudbg(IFDOWN, "%s: Disable RX MAC\n", np->dev->name);
5579 niu_enable_rx_mac(np, 0);
5580
5581 niudbg(IFDOWN, "%s: Disable IPP\n", np->dev->name);
5582 niu_disable_ipp(np);
5583
5584 niudbg(IFDOWN, "%s: Stop TX channels\n", np->dev->name);
5585 niu_stop_tx_channels(np);
5586
5587 niudbg(IFDOWN, "%s: Stop RX channels\n", np->dev->name);
5588 niu_stop_rx_channels(np);
5589
5590 niudbg(IFDOWN, "%s: Reset TX channels\n", np->dev->name);
5591 niu_reset_tx_channels(np);
5592
5593 niudbg(IFDOWN, "%s: Reset RX channels\n", np->dev->name);
5594 niu_reset_rx_channels(np);
5595 }
5596
5597 static int niu_request_irq(struct niu *np)
5598 {
5599 int i, j, err;
5600
5601 err = 0;
5602 for (i = 0; i < np->num_ldg; i++) {
5603 struct niu_ldg *lp = &np->ldg[i];
5604
5605 err = request_irq(lp->irq, niu_interrupt,
5606 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
5607 np->dev->name, lp);
5608 if (err)
5609 goto out_free_irqs;
5610
5611 }
5612
5613 return 0;
5614
5615 out_free_irqs:
5616 for (j = 0; j < i; j++) {
5617 struct niu_ldg *lp = &np->ldg[j];
5618
5619 free_irq(lp->irq, lp);
5620 }
5621 return err;
5622 }
5623
5624 static void niu_free_irq(struct niu *np)
5625 {
5626 int i;
5627
5628 for (i = 0; i < np->num_ldg; i++) {
5629 struct niu_ldg *lp = &np->ldg[i];
5630
5631 free_irq(lp->irq, lp);
5632 }
5633 }
5634
5635 static void niu_enable_napi(struct niu *np)
5636 {
5637 int i;
5638
5639 for (i = 0; i < np->num_ldg; i++)
5640 napi_enable(&np->ldg[i].napi);
5641 }
5642
5643 static void niu_disable_napi(struct niu *np)
5644 {
5645 int i;
5646
5647 for (i = 0; i < np->num_ldg; i++)
5648 napi_disable(&np->ldg[i].napi);
5649 }
5650
5651 static int niu_open(struct net_device *dev)
5652 {
5653 struct niu *np = netdev_priv(dev);
5654 int err;
5655
5656 netif_carrier_off(dev);
5657
5658 err = niu_alloc_channels(np);
5659 if (err)
5660 goto out_err;
5661
5662 err = niu_enable_interrupts(np, 0);
5663 if (err)
5664 goto out_free_channels;
5665
5666 err = niu_request_irq(np);
5667 if (err)
5668 goto out_free_channels;
5669
5670 niu_enable_napi(np);
5671
5672 spin_lock_irq(&np->lock);
5673
5674 err = niu_init_hw(np);
5675 if (!err) {
5676 init_timer(&np->timer);
5677 np->timer.expires = jiffies + HZ;
5678 np->timer.data = (unsigned long) np;
5679 np->timer.function = niu_timer;
5680
5681 err = niu_enable_interrupts(np, 1);
5682 if (err)
5683 niu_stop_hw(np);
5684 }
5685
5686 spin_unlock_irq(&np->lock);
5687
5688 if (err) {
5689 niu_disable_napi(np);
5690 goto out_free_irq;
5691 }
5692
5693 netif_tx_start_all_queues(dev);
5694
5695 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
5696 netif_carrier_on(dev);
5697
5698 add_timer(&np->timer);
5699
5700 return 0;
5701
5702 out_free_irq:
5703 niu_free_irq(np);
5704
5705 out_free_channels:
5706 niu_free_channels(np);
5707
5708 out_err:
5709 return err;
5710 }
5711
5712 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
5713 {
5714 cancel_work_sync(&np->reset_task);
5715
5716 niu_disable_napi(np);
5717 netif_tx_stop_all_queues(dev);
5718
5719 del_timer_sync(&np->timer);
5720
5721 spin_lock_irq(&np->lock);
5722
5723 niu_stop_hw(np);
5724
5725 spin_unlock_irq(&np->lock);
5726 }
5727
5728 static int niu_close(struct net_device *dev)
5729 {
5730 struct niu *np = netdev_priv(dev);
5731
5732 niu_full_shutdown(np, dev);
5733
5734 niu_free_irq(np);
5735
5736 niu_free_channels(np);
5737
5738 niu_handle_led(np, 0);
5739
5740 return 0;
5741 }
5742
5743 static void niu_sync_xmac_stats(struct niu *np)
5744 {
5745 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
5746
5747 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
5748 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
5749
5750 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
5751 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
5752 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
5753 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
5754 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
5755 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
5756 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
5757 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
5758 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
5759 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
5760 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
5761 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
5762 mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
5763 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
5764 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
5765 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
5766 }
5767
5768 static void niu_sync_bmac_stats(struct niu *np)
5769 {
5770 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
5771
5772 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
5773 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
5774
5775 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
5776 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
5777 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
5778 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
5779 }
5780
5781 static void niu_sync_mac_stats(struct niu *np)
5782 {
5783 if (np->flags & NIU_FLAGS_XMAC)
5784 niu_sync_xmac_stats(np);
5785 else
5786 niu_sync_bmac_stats(np);
5787 }
5788
5789 static void niu_get_rx_stats(struct niu *np)
5790 {
5791 unsigned long pkts, dropped, errors, bytes;
5792 int i;
5793
5794 pkts = dropped = errors = bytes = 0;
5795 for (i = 0; i < np->num_rx_rings; i++) {
5796 struct rx_ring_info *rp = &np->rx_rings[i];
5797
5798 pkts += rp->rx_packets;
5799 bytes += rp->rx_bytes;
5800 dropped += rp->rx_dropped;
5801 errors += rp->rx_errors;
5802 }
5803 np->net_stats.rx_packets = pkts;
5804 np->net_stats.rx_bytes = bytes;
5805 np->net_stats.rx_dropped = dropped;
5806 np->net_stats.rx_errors = errors;
5807 }
5808
5809 static void niu_get_tx_stats(struct niu *np)
5810 {
5811 unsigned long pkts, errors, bytes;
5812 int i;
5813
5814 pkts = errors = bytes = 0;
5815 for (i = 0; i < np->num_tx_rings; i++) {
5816 struct tx_ring_info *rp = &np->tx_rings[i];
5817
5818 pkts += rp->tx_packets;
5819 bytes += rp->tx_bytes;
5820 errors += rp->tx_errors;
5821 }
5822 np->net_stats.tx_packets = pkts;
5823 np->net_stats.tx_bytes = bytes;
5824 np->net_stats.tx_errors = errors;
5825 }
5826
5827 static struct net_device_stats *niu_get_stats(struct net_device *dev)
5828 {
5829 struct niu *np = netdev_priv(dev);
5830
5831 niu_get_rx_stats(np);
5832 niu_get_tx_stats(np);
5833
5834 return &np->net_stats;
5835 }
5836
5837 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
5838 {
5839 int i;
5840
5841 for (i = 0; i < 16; i++)
5842 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
5843 }
5844
5845 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
5846 {
5847 int i;
5848
5849 for (i = 0; i < 16; i++)
5850 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
5851 }
5852
5853 static void niu_load_hash(struct niu *np, u16 *hash)
5854 {
5855 if (np->flags & NIU_FLAGS_XMAC)
5856 niu_load_hash_xmac(np, hash);
5857 else
5858 niu_load_hash_bmac(np, hash);
5859 }
5860
5861 static void niu_set_rx_mode(struct net_device *dev)
5862 {
5863 struct niu *np = netdev_priv(dev);
5864 int i, alt_cnt, err;
5865 struct dev_addr_list *addr;
5866 unsigned long flags;
5867 u16 hash[16] = { 0, };
5868
5869 spin_lock_irqsave(&np->lock, flags);
5870 niu_enable_rx_mac(np, 0);
5871
5872 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
5873 if (dev->flags & IFF_PROMISC)
5874 np->flags |= NIU_FLAGS_PROMISC;
5875 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 0))
5876 np->flags |= NIU_FLAGS_MCAST;
5877
5878 alt_cnt = dev->uc_count;
5879 if (alt_cnt > niu_num_alt_addr(np)) {
5880 alt_cnt = 0;
5881 np->flags |= NIU_FLAGS_PROMISC;
5882 }
5883
5884 if (alt_cnt) {
5885 int index = 0;
5886
5887 for (addr = dev->uc_list; addr; addr = addr->next) {
5888 err = niu_set_alt_mac(np, index,
5889 addr->da_addr);
5890 if (err)
5891 printk(KERN_WARNING PFX "%s: Error %d "
5892 "adding alt mac %d\n",
5893 dev->name, err, index);
5894 err = niu_enable_alt_mac(np, index, 1);
5895 if (err)
5896 printk(KERN_WARNING PFX "%s: Error %d "
5897 "enabling alt mac %d\n",
5898 dev->name, err, index);
5899
5900 index++;
5901 }
5902 } else {
5903 int alt_start;
5904 if (np->flags & NIU_FLAGS_XMAC)
5905 alt_start = 0;
5906 else
5907 alt_start = 1;
5908 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
5909 err = niu_enable_alt_mac(np, i, 0);
5910 if (err)
5911 printk(KERN_WARNING PFX "%s: Error %d "
5912 "disabling alt mac %d\n",
5913 dev->name, err, i);
5914 }
5915 }
5916 if (dev->flags & IFF_ALLMULTI) {
5917 for (i = 0; i < 16; i++)
5918 hash[i] = 0xffff;
5919 } else if (dev->mc_count > 0) {
5920 for (addr = dev->mc_list; addr; addr = addr->next) {
5921 u32 crc = ether_crc_le(ETH_ALEN, addr->da_addr);
5922
5923 crc >>= 24;
5924 hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
5925 }
5926 }
5927
5928 if (np->flags & NIU_FLAGS_MCAST)
5929 niu_load_hash(np, hash);
5930
5931 niu_enable_rx_mac(np, 1);
5932 spin_unlock_irqrestore(&np->lock, flags);
5933 }
5934
5935 static int niu_set_mac_addr(struct net_device *dev, void *p)
5936 {
5937 struct niu *np = netdev_priv(dev);
5938 struct sockaddr *addr = p;
5939 unsigned long flags;
5940
5941 if (!is_valid_ether_addr(addr->sa_data))
5942 return -EINVAL;
5943
5944 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
5945
5946 if (!netif_running(dev))
5947 return 0;
5948
5949 spin_lock_irqsave(&np->lock, flags);
5950 niu_enable_rx_mac(np, 0);
5951 niu_set_primary_mac(np, dev->dev_addr);
5952 niu_enable_rx_mac(np, 1);
5953 spin_unlock_irqrestore(&np->lock, flags);
5954
5955 return 0;
5956 }
5957
5958 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5959 {
5960 return -EOPNOTSUPP;
5961 }
5962
5963 static void niu_netif_stop(struct niu *np)
5964 {
5965 np->dev->trans_start = jiffies; /* prevent tx timeout */
5966
5967 niu_disable_napi(np);
5968
5969 netif_tx_disable(np->dev);
5970 }
5971
5972 static void niu_netif_start(struct niu *np)
5973 {
5974 /* NOTE: unconditional netif_wake_queue is only appropriate
5975 * so long as all callers are assured to have free tx slots
5976 * (such as after niu_init_hw).
5977 */
5978 netif_tx_wake_all_queues(np->dev);
5979
5980 niu_enable_napi(np);
5981
5982 niu_enable_interrupts(np, 1);
5983 }
5984
5985 static void niu_reset_buffers(struct niu *np)
5986 {
5987 int i, j, k, err;
5988
5989 if (np->rx_rings) {
5990 for (i = 0; i < np->num_rx_rings; i++) {
5991 struct rx_ring_info *rp = &np->rx_rings[i];
5992
5993 for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
5994 struct page *page;
5995
5996 page = rp->rxhash[j];
5997 while (page) {
5998 struct page *next =
5999 (struct page *) page->mapping;
6000 u64 base = page->index;
6001 base = base >> RBR_DESCR_ADDR_SHIFT;
6002 rp->rbr[k++] = cpu_to_le32(base);
6003 page = next;
6004 }
6005 }
6006 for (; k < MAX_RBR_RING_SIZE; k++) {
6007 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6008 if (unlikely(err))
6009 break;
6010 }
6011
6012 rp->rbr_index = rp->rbr_table_size - 1;
6013 rp->rcr_index = 0;
6014 rp->rbr_pending = 0;
6015 rp->rbr_refill_pending = 0;
6016 }
6017 }
6018 if (np->tx_rings) {
6019 for (i = 0; i < np->num_tx_rings; i++) {
6020 struct tx_ring_info *rp = &np->tx_rings[i];
6021
6022 for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6023 if (rp->tx_buffs[j].skb)
6024 (void) release_tx_packet(np, rp, j);
6025 }
6026
6027 rp->pending = MAX_TX_RING_SIZE;
6028 rp->prod = 0;
6029 rp->cons = 0;
6030 rp->wrap_bit = 0;
6031 }
6032 }
6033 }
6034
6035 static void niu_reset_task(struct work_struct *work)
6036 {
6037 struct niu *np = container_of(work, struct niu, reset_task);
6038 unsigned long flags;
6039 int err;
6040
6041 spin_lock_irqsave(&np->lock, flags);
6042 if (!netif_running(np->dev)) {
6043 spin_unlock_irqrestore(&np->lock, flags);
6044 return;
6045 }
6046
6047 spin_unlock_irqrestore(&np->lock, flags);
6048
6049 del_timer_sync(&np->timer);
6050
6051 niu_netif_stop(np);
6052
6053 spin_lock_irqsave(&np->lock, flags);
6054
6055 niu_stop_hw(np);
6056
6057 spin_unlock_irqrestore(&np->lock, flags);
6058
6059 niu_reset_buffers(np);
6060
6061 spin_lock_irqsave(&np->lock, flags);
6062
6063 err = niu_init_hw(np);
6064 if (!err) {
6065 np->timer.expires = jiffies + HZ;
6066 add_timer(&np->timer);
6067 niu_netif_start(np);
6068 }
6069
6070 spin_unlock_irqrestore(&np->lock, flags);
6071 }
6072
6073 static void niu_tx_timeout(struct net_device *dev)
6074 {
6075 struct niu *np = netdev_priv(dev);
6076
6077 dev_err(np->device, PFX "%s: Transmit timed out, resetting\n",
6078 dev->name);
6079
6080 schedule_work(&np->reset_task);
6081 }
6082
6083 static void niu_set_txd(struct tx_ring_info *rp, int index,
6084 u64 mapping, u64 len, u64 mark,
6085 u64 n_frags)
6086 {
6087 __le64 *desc = &rp->descr[index];
6088
6089 *desc = cpu_to_le64(mark |
6090 (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6091 (len << TX_DESC_TR_LEN_SHIFT) |
6092 (mapping & TX_DESC_SAD));
6093 }
6094
6095 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6096 u64 pad_bytes, u64 len)
6097 {
6098 u16 eth_proto, eth_proto_inner;
6099 u64 csum_bits, l3off, ihl, ret;
6100 u8 ip_proto;
6101 int ipv6;
6102
6103 eth_proto = be16_to_cpu(ehdr->h_proto);
6104 eth_proto_inner = eth_proto;
6105 if (eth_proto == ETH_P_8021Q) {
6106 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6107 __be16 val = vp->h_vlan_encapsulated_proto;
6108
6109 eth_proto_inner = be16_to_cpu(val);
6110 }
6111
6112 ipv6 = ihl = 0;
6113 switch (skb->protocol) {
6114 case __constant_htons(ETH_P_IP):
6115 ip_proto = ip_hdr(skb)->protocol;
6116 ihl = ip_hdr(skb)->ihl;
6117 break;
6118 case __constant_htons(ETH_P_IPV6):
6119 ip_proto = ipv6_hdr(skb)->nexthdr;
6120 ihl = (40 >> 2);
6121 ipv6 = 1;
6122 break;
6123 default:
6124 ip_proto = ihl = 0;
6125 break;
6126 }
6127
6128 csum_bits = TXHDR_CSUM_NONE;
6129 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6130 u64 start, stuff;
6131
6132 csum_bits = (ip_proto == IPPROTO_TCP ?
6133 TXHDR_CSUM_TCP :
6134 (ip_proto == IPPROTO_UDP ?
6135 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6136
6137 start = skb_transport_offset(skb) -
6138 (pad_bytes + sizeof(struct tx_pkt_hdr));
6139 stuff = start + skb->csum_offset;
6140
6141 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6142 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6143 }
6144
6145 l3off = skb_network_offset(skb) -
6146 (pad_bytes + sizeof(struct tx_pkt_hdr));
6147
6148 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6149 (len << TXHDR_LEN_SHIFT) |
6150 ((l3off / 2) << TXHDR_L3START_SHIFT) |
6151 (ihl << TXHDR_IHL_SHIFT) |
6152 ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
6153 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6154 (ipv6 ? TXHDR_IP_VER : 0) |
6155 csum_bits);
6156
6157 return ret;
6158 }
6159
6160 static int niu_start_xmit(struct sk_buff *skb, struct net_device *dev)
6161 {
6162 struct niu *np = netdev_priv(dev);
6163 unsigned long align, headroom;
6164 struct netdev_queue *txq;
6165 struct tx_ring_info *rp;
6166 struct tx_pkt_hdr *tp;
6167 unsigned int len, nfg;
6168 struct ethhdr *ehdr;
6169 int prod, i, tlen;
6170 u64 mapping, mrk;
6171
6172 i = skb_get_queue_mapping(skb);
6173 rp = &np->tx_rings[i];
6174 txq = netdev_get_tx_queue(dev, i);
6175
6176 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
6177 netif_tx_stop_queue(txq);
6178 dev_err(np->device, PFX "%s: BUG! Tx ring full when "
6179 "queue awake!\n", dev->name);
6180 rp->tx_errors++;
6181 return NETDEV_TX_BUSY;
6182 }
6183
6184 if (skb->len < ETH_ZLEN) {
6185 unsigned int pad_bytes = ETH_ZLEN - skb->len;
6186
6187 if (skb_pad(skb, pad_bytes))
6188 goto out;
6189 skb_put(skb, pad_bytes);
6190 }
6191
6192 len = sizeof(struct tx_pkt_hdr) + 15;
6193 if (skb_headroom(skb) < len) {
6194 struct sk_buff *skb_new;
6195
6196 skb_new = skb_realloc_headroom(skb, len);
6197 if (!skb_new) {
6198 rp->tx_errors++;
6199 goto out_drop;
6200 }
6201 kfree_skb(skb);
6202 skb = skb_new;
6203 } else
6204 skb_orphan(skb);
6205
6206 align = ((unsigned long) skb->data & (16 - 1));
6207 headroom = align + sizeof(struct tx_pkt_hdr);
6208
6209 ehdr = (struct ethhdr *) skb->data;
6210 tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
6211
6212 len = skb->len - sizeof(struct tx_pkt_hdr);
6213 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6214 tp->resv = 0;
6215
6216 len = skb_headlen(skb);
6217 mapping = np->ops->map_single(np->device, skb->data,
6218 len, DMA_TO_DEVICE);
6219
6220 prod = rp->prod;
6221
6222 rp->tx_buffs[prod].skb = skb;
6223 rp->tx_buffs[prod].mapping = mapping;
6224
6225 mrk = TX_DESC_SOP;
6226 if (++rp->mark_counter == rp->mark_freq) {
6227 rp->mark_counter = 0;
6228 mrk |= TX_DESC_MARK;
6229 rp->mark_pending++;
6230 }
6231
6232 tlen = len;
6233 nfg = skb_shinfo(skb)->nr_frags;
6234 while (tlen > 0) {
6235 tlen -= MAX_TX_DESC_LEN;
6236 nfg++;
6237 }
6238
6239 while (len > 0) {
6240 unsigned int this_len = len;
6241
6242 if (this_len > MAX_TX_DESC_LEN)
6243 this_len = MAX_TX_DESC_LEN;
6244
6245 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6246 mrk = nfg = 0;
6247
6248 prod = NEXT_TX(rp, prod);
6249 mapping += this_len;
6250 len -= this_len;
6251 }
6252
6253 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6254 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6255
6256 len = frag->size;
6257 mapping = np->ops->map_page(np->device, frag->page,
6258 frag->page_offset, len,
6259 DMA_TO_DEVICE);
6260
6261 rp->tx_buffs[prod].skb = NULL;
6262 rp->tx_buffs[prod].mapping = mapping;
6263
6264 niu_set_txd(rp, prod, mapping, len, 0, 0);
6265
6266 prod = NEXT_TX(rp, prod);
6267 }
6268
6269 if (prod < rp->prod)
6270 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6271 rp->prod = prod;
6272
6273 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6274
6275 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
6276 netif_tx_stop_queue(txq);
6277 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
6278 netif_tx_wake_queue(txq);
6279 }
6280
6281 dev->trans_start = jiffies;
6282
6283 out:
6284 return NETDEV_TX_OK;
6285
6286 out_drop:
6287 rp->tx_errors++;
6288 kfree_skb(skb);
6289 goto out;
6290 }
6291
6292 static int niu_change_mtu(struct net_device *dev, int new_mtu)
6293 {
6294 struct niu *np = netdev_priv(dev);
6295 int err, orig_jumbo, new_jumbo;
6296
6297 if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6298 return -EINVAL;
6299
6300 orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6301 new_jumbo = (new_mtu > ETH_DATA_LEN);
6302
6303 dev->mtu = new_mtu;
6304
6305 if (!netif_running(dev) ||
6306 (orig_jumbo == new_jumbo))
6307 return 0;
6308
6309 niu_full_shutdown(np, dev);
6310
6311 niu_free_channels(np);
6312
6313 niu_enable_napi(np);
6314
6315 err = niu_alloc_channels(np);
6316 if (err)
6317 return err;
6318
6319 spin_lock_irq(&np->lock);
6320
6321 err = niu_init_hw(np);
6322 if (!err) {
6323 init_timer(&np->timer);
6324 np->timer.expires = jiffies + HZ;
6325 np->timer.data = (unsigned long) np;
6326 np->timer.function = niu_timer;
6327
6328 err = niu_enable_interrupts(np, 1);
6329 if (err)
6330 niu_stop_hw(np);
6331 }
6332
6333 spin_unlock_irq(&np->lock);
6334
6335 if (!err) {
6336 netif_tx_start_all_queues(dev);
6337 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6338 netif_carrier_on(dev);
6339
6340 add_timer(&np->timer);
6341 }
6342
6343 return err;
6344 }
6345
6346 static void niu_get_drvinfo(struct net_device *dev,
6347 struct ethtool_drvinfo *info)
6348 {
6349 struct niu *np = netdev_priv(dev);
6350 struct niu_vpd *vpd = &np->vpd;
6351
6352 strcpy(info->driver, DRV_MODULE_NAME);
6353 strcpy(info->version, DRV_MODULE_VERSION);
6354 sprintf(info->fw_version, "%d.%d",
6355 vpd->fcode_major, vpd->fcode_minor);
6356 if (np->parent->plat_type != PLAT_TYPE_NIU)
6357 strcpy(info->bus_info, pci_name(np->pdev));
6358 }
6359
6360 static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6361 {
6362 struct niu *np = netdev_priv(dev);
6363 struct niu_link_config *lp;
6364
6365 lp = &np->link_config;
6366
6367 memset(cmd, 0, sizeof(*cmd));
6368 cmd->phy_address = np->phy_addr;
6369 cmd->supported = lp->supported;
6370 cmd->advertising = lp->advertising;
6371 cmd->autoneg = lp->autoneg;
6372 cmd->speed = lp->active_speed;
6373 cmd->duplex = lp->active_duplex;
6374
6375 return 0;
6376 }
6377
6378 static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6379 {
6380 return -EINVAL;
6381 }
6382
6383 static u32 niu_get_msglevel(struct net_device *dev)
6384 {
6385 struct niu *np = netdev_priv(dev);
6386 return np->msg_enable;
6387 }
6388
6389 static void niu_set_msglevel(struct net_device *dev, u32 value)
6390 {
6391 struct niu *np = netdev_priv(dev);
6392 np->msg_enable = value;
6393 }
6394
6395 static int niu_get_eeprom_len(struct net_device *dev)
6396 {
6397 struct niu *np = netdev_priv(dev);
6398
6399 return np->eeprom_len;
6400 }
6401
6402 static int niu_get_eeprom(struct net_device *dev,
6403 struct ethtool_eeprom *eeprom, u8 *data)
6404 {
6405 struct niu *np = netdev_priv(dev);
6406 u32 offset, len, val;
6407
6408 offset = eeprom->offset;
6409 len = eeprom->len;
6410
6411 if (offset + len < offset)
6412 return -EINVAL;
6413 if (offset >= np->eeprom_len)
6414 return -EINVAL;
6415 if (offset + len > np->eeprom_len)
6416 len = eeprom->len = np->eeprom_len - offset;
6417
6418 if (offset & 3) {
6419 u32 b_offset, b_count;
6420
6421 b_offset = offset & 3;
6422 b_count = 4 - b_offset;
6423 if (b_count > len)
6424 b_count = len;
6425
6426 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6427 memcpy(data, ((char *)&val) + b_offset, b_count);
6428 data += b_count;
6429 len -= b_count;
6430 offset += b_count;
6431 }
6432 while (len >= 4) {
6433 val = nr64(ESPC_NCR(offset / 4));
6434 memcpy(data, &val, 4);
6435 data += 4;
6436 len -= 4;
6437 offset += 4;
6438 }
6439 if (len) {
6440 val = nr64(ESPC_NCR(offset / 4));
6441 memcpy(data, &val, len);
6442 }
6443 return 0;
6444 }
6445
6446 static int niu_ethflow_to_class(int flow_type, u64 *class)
6447 {
6448 switch (flow_type) {
6449 case TCP_V4_FLOW:
6450 *class = CLASS_CODE_TCP_IPV4;
6451 break;
6452 case UDP_V4_FLOW:
6453 *class = CLASS_CODE_UDP_IPV4;
6454 break;
6455 case AH_ESP_V4_FLOW:
6456 *class = CLASS_CODE_AH_ESP_IPV4;
6457 break;
6458 case SCTP_V4_FLOW:
6459 *class = CLASS_CODE_SCTP_IPV4;
6460 break;
6461 case TCP_V6_FLOW:
6462 *class = CLASS_CODE_TCP_IPV6;
6463 break;
6464 case UDP_V6_FLOW:
6465 *class = CLASS_CODE_UDP_IPV6;
6466 break;
6467 case AH_ESP_V6_FLOW:
6468 *class = CLASS_CODE_AH_ESP_IPV6;
6469 break;
6470 case SCTP_V6_FLOW:
6471 *class = CLASS_CODE_SCTP_IPV6;
6472 break;
6473 default:
6474 return 0;
6475 }
6476
6477 return 1;
6478 }
6479
6480 static u64 niu_flowkey_to_ethflow(u64 flow_key)
6481 {
6482 u64 ethflow = 0;
6483
6484 if (flow_key & FLOW_KEY_PORT)
6485 ethflow |= RXH_DEV_PORT;
6486 if (flow_key & FLOW_KEY_L2DA)
6487 ethflow |= RXH_L2DA;
6488 if (flow_key & FLOW_KEY_VLAN)
6489 ethflow |= RXH_VLAN;
6490 if (flow_key & FLOW_KEY_IPSA)
6491 ethflow |= RXH_IP_SRC;
6492 if (flow_key & FLOW_KEY_IPDA)
6493 ethflow |= RXH_IP_DST;
6494 if (flow_key & FLOW_KEY_PROTO)
6495 ethflow |= RXH_L3_PROTO;
6496 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
6497 ethflow |= RXH_L4_B_0_1;
6498 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
6499 ethflow |= RXH_L4_B_2_3;
6500
6501 return ethflow;
6502
6503 }
6504
6505 static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
6506 {
6507 u64 key = 0;
6508
6509 if (ethflow & RXH_DEV_PORT)
6510 key |= FLOW_KEY_PORT;
6511 if (ethflow & RXH_L2DA)
6512 key |= FLOW_KEY_L2DA;
6513 if (ethflow & RXH_VLAN)
6514 key |= FLOW_KEY_VLAN;
6515 if (ethflow & RXH_IP_SRC)
6516 key |= FLOW_KEY_IPSA;
6517 if (ethflow & RXH_IP_DST)
6518 key |= FLOW_KEY_IPDA;
6519 if (ethflow & RXH_L3_PROTO)
6520 key |= FLOW_KEY_PROTO;
6521 if (ethflow & RXH_L4_B_0_1)
6522 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
6523 if (ethflow & RXH_L4_B_2_3)
6524 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
6525
6526 *flow_key = key;
6527
6528 return 1;
6529
6530 }
6531
6532 static int niu_get_hash_opts(struct net_device *dev, struct ethtool_rxnfc *cmd)
6533 {
6534 struct niu *np = netdev_priv(dev);
6535 u64 class;
6536
6537 cmd->data = 0;
6538
6539 if (!niu_ethflow_to_class(cmd->flow_type, &class))
6540 return -EINVAL;
6541
6542 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
6543 TCAM_KEY_DISC)
6544 cmd->data = RXH_DISCARD;
6545 else
6546
6547 cmd->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
6548 CLASS_CODE_USER_PROG1]);
6549 return 0;
6550 }
6551
6552 static int niu_set_hash_opts(struct net_device *dev, struct ethtool_rxnfc *cmd)
6553 {
6554 struct niu *np = netdev_priv(dev);
6555 u64 class;
6556 u64 flow_key = 0;
6557 unsigned long flags;
6558
6559 if (!niu_ethflow_to_class(cmd->flow_type, &class))
6560 return -EINVAL;
6561
6562 if (class < CLASS_CODE_USER_PROG1 ||
6563 class > CLASS_CODE_SCTP_IPV6)
6564 return -EINVAL;
6565
6566 if (cmd->data & RXH_DISCARD) {
6567 niu_lock_parent(np, flags);
6568 flow_key = np->parent->tcam_key[class -
6569 CLASS_CODE_USER_PROG1];
6570 flow_key |= TCAM_KEY_DISC;
6571 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
6572 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
6573 niu_unlock_parent(np, flags);
6574 return 0;
6575 } else {
6576 /* Discard was set before, but is not set now */
6577 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
6578 TCAM_KEY_DISC) {
6579 niu_lock_parent(np, flags);
6580 flow_key = np->parent->tcam_key[class -
6581 CLASS_CODE_USER_PROG1];
6582 flow_key &= ~TCAM_KEY_DISC;
6583 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
6584 flow_key);
6585 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
6586 flow_key;
6587 niu_unlock_parent(np, flags);
6588 }
6589 }
6590
6591 if (!niu_ethflow_to_flowkey(cmd->data, &flow_key))
6592 return -EINVAL;
6593
6594 niu_lock_parent(np, flags);
6595 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
6596 np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
6597 niu_unlock_parent(np, flags);
6598
6599 return 0;
6600 }
6601
6602 static const struct {
6603 const char string[ETH_GSTRING_LEN];
6604 } niu_xmac_stat_keys[] = {
6605 { "tx_frames" },
6606 { "tx_bytes" },
6607 { "tx_fifo_errors" },
6608 { "tx_overflow_errors" },
6609 { "tx_max_pkt_size_errors" },
6610 { "tx_underflow_errors" },
6611 { "rx_local_faults" },
6612 { "rx_remote_faults" },
6613 { "rx_link_faults" },
6614 { "rx_align_errors" },
6615 { "rx_frags" },
6616 { "rx_mcasts" },
6617 { "rx_bcasts" },
6618 { "rx_hist_cnt1" },
6619 { "rx_hist_cnt2" },
6620 { "rx_hist_cnt3" },
6621 { "rx_hist_cnt4" },
6622 { "rx_hist_cnt5" },
6623 { "rx_hist_cnt6" },
6624 { "rx_hist_cnt7" },
6625 { "rx_octets" },
6626 { "rx_code_violations" },
6627 { "rx_len_errors" },
6628 { "rx_crc_errors" },
6629 { "rx_underflows" },
6630 { "rx_overflows" },
6631 { "pause_off_state" },
6632 { "pause_on_state" },
6633 { "pause_received" },
6634 };
6635
6636 #define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
6637
6638 static const struct {
6639 const char string[ETH_GSTRING_LEN];
6640 } niu_bmac_stat_keys[] = {
6641 { "tx_underflow_errors" },
6642 { "tx_max_pkt_size_errors" },
6643 { "tx_bytes" },
6644 { "tx_frames" },
6645 { "rx_overflows" },
6646 { "rx_frames" },
6647 { "rx_align_errors" },
6648 { "rx_crc_errors" },
6649 { "rx_len_errors" },
6650 { "pause_off_state" },
6651 { "pause_on_state" },
6652 { "pause_received" },
6653 };
6654
6655 #define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
6656
6657 static const struct {
6658 const char string[ETH_GSTRING_LEN];
6659 } niu_rxchan_stat_keys[] = {
6660 { "rx_channel" },
6661 { "rx_packets" },
6662 { "rx_bytes" },
6663 { "rx_dropped" },
6664 { "rx_errors" },
6665 };
6666
6667 #define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
6668
6669 static const struct {
6670 const char string[ETH_GSTRING_LEN];
6671 } niu_txchan_stat_keys[] = {
6672 { "tx_channel" },
6673 { "tx_packets" },
6674 { "tx_bytes" },
6675 { "tx_errors" },
6676 };
6677
6678 #define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
6679
6680 static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
6681 {
6682 struct niu *np = netdev_priv(dev);
6683 int i;
6684
6685 if (stringset != ETH_SS_STATS)
6686 return;
6687
6688 if (np->flags & NIU_FLAGS_XMAC) {
6689 memcpy(data, niu_xmac_stat_keys,
6690 sizeof(niu_xmac_stat_keys));
6691 data += sizeof(niu_xmac_stat_keys);
6692 } else {
6693 memcpy(data, niu_bmac_stat_keys,
6694 sizeof(niu_bmac_stat_keys));
6695 data += sizeof(niu_bmac_stat_keys);
6696 }
6697 for (i = 0; i < np->num_rx_rings; i++) {
6698 memcpy(data, niu_rxchan_stat_keys,
6699 sizeof(niu_rxchan_stat_keys));
6700 data += sizeof(niu_rxchan_stat_keys);
6701 }
6702 for (i = 0; i < np->num_tx_rings; i++) {
6703 memcpy(data, niu_txchan_stat_keys,
6704 sizeof(niu_txchan_stat_keys));
6705 data += sizeof(niu_txchan_stat_keys);
6706 }
6707 }
6708
6709 static int niu_get_stats_count(struct net_device *dev)
6710 {
6711 struct niu *np = netdev_priv(dev);
6712
6713 return ((np->flags & NIU_FLAGS_XMAC ?
6714 NUM_XMAC_STAT_KEYS :
6715 NUM_BMAC_STAT_KEYS) +
6716 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
6717 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS));
6718 }
6719
6720 static void niu_get_ethtool_stats(struct net_device *dev,
6721 struct ethtool_stats *stats, u64 *data)
6722 {
6723 struct niu *np = netdev_priv(dev);
6724 int i;
6725
6726 niu_sync_mac_stats(np);
6727 if (np->flags & NIU_FLAGS_XMAC) {
6728 memcpy(data, &np->mac_stats.xmac,
6729 sizeof(struct niu_xmac_stats));
6730 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
6731 } else {
6732 memcpy(data, &np->mac_stats.bmac,
6733 sizeof(struct niu_bmac_stats));
6734 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
6735 }
6736 for (i = 0; i < np->num_rx_rings; i++) {
6737 struct rx_ring_info *rp = &np->rx_rings[i];
6738
6739 data[0] = rp->rx_channel;
6740 data[1] = rp->rx_packets;
6741 data[2] = rp->rx_bytes;
6742 data[3] = rp->rx_dropped;
6743 data[4] = rp->rx_errors;
6744 data += 5;
6745 }
6746 for (i = 0; i < np->num_tx_rings; i++) {
6747 struct tx_ring_info *rp = &np->tx_rings[i];
6748
6749 data[0] = rp->tx_channel;
6750 data[1] = rp->tx_packets;
6751 data[2] = rp->tx_bytes;
6752 data[3] = rp->tx_errors;
6753 data += 4;
6754 }
6755 }
6756
6757 static u64 niu_led_state_save(struct niu *np)
6758 {
6759 if (np->flags & NIU_FLAGS_XMAC)
6760 return nr64_mac(XMAC_CONFIG);
6761 else
6762 return nr64_mac(BMAC_XIF_CONFIG);
6763 }
6764
6765 static void niu_led_state_restore(struct niu *np, u64 val)
6766 {
6767 if (np->flags & NIU_FLAGS_XMAC)
6768 nw64_mac(XMAC_CONFIG, val);
6769 else
6770 nw64_mac(BMAC_XIF_CONFIG, val);
6771 }
6772
6773 static void niu_force_led(struct niu *np, int on)
6774 {
6775 u64 val, reg, bit;
6776
6777 if (np->flags & NIU_FLAGS_XMAC) {
6778 reg = XMAC_CONFIG;
6779 bit = XMAC_CONFIG_FORCE_LED_ON;
6780 } else {
6781 reg = BMAC_XIF_CONFIG;
6782 bit = BMAC_XIF_CONFIG_LINK_LED;
6783 }
6784
6785 val = nr64_mac(reg);
6786 if (on)
6787 val |= bit;
6788 else
6789 val &= ~bit;
6790 nw64_mac(reg, val);
6791 }
6792
6793 static int niu_phys_id(struct net_device *dev, u32 data)
6794 {
6795 struct niu *np = netdev_priv(dev);
6796 u64 orig_led_state;
6797 int i;
6798
6799 if (!netif_running(dev))
6800 return -EAGAIN;
6801
6802 if (data == 0)
6803 data = 2;
6804
6805 orig_led_state = niu_led_state_save(np);
6806 for (i = 0; i < (data * 2); i++) {
6807 int on = ((i % 2) == 0);
6808
6809 niu_force_led(np, on);
6810
6811 if (msleep_interruptible(500))
6812 break;
6813 }
6814 niu_led_state_restore(np, orig_led_state);
6815
6816 return 0;
6817 }
6818
6819 static const struct ethtool_ops niu_ethtool_ops = {
6820 .get_drvinfo = niu_get_drvinfo,
6821 .get_link = ethtool_op_get_link,
6822 .get_msglevel = niu_get_msglevel,
6823 .set_msglevel = niu_set_msglevel,
6824 .get_eeprom_len = niu_get_eeprom_len,
6825 .get_eeprom = niu_get_eeprom,
6826 .get_settings = niu_get_settings,
6827 .set_settings = niu_set_settings,
6828 .get_strings = niu_get_strings,
6829 .get_stats_count = niu_get_stats_count,
6830 .get_ethtool_stats = niu_get_ethtool_stats,
6831 .phys_id = niu_phys_id,
6832 .get_rxhash = niu_get_hash_opts,
6833 .set_rxhash = niu_set_hash_opts,
6834 };
6835
6836 static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
6837 int ldg, int ldn)
6838 {
6839 if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
6840 return -EINVAL;
6841 if (ldn < 0 || ldn > LDN_MAX)
6842 return -EINVAL;
6843
6844 parent->ldg_map[ldn] = ldg;
6845
6846 if (np->parent->plat_type == PLAT_TYPE_NIU) {
6847 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
6848 * the firmware, and we're not supposed to change them.
6849 * Validate the mapping, because if it's wrong we probably
6850 * won't get any interrupts and that's painful to debug.
6851 */
6852 if (nr64(LDG_NUM(ldn)) != ldg) {
6853 dev_err(np->device, PFX "Port %u, mis-matched "
6854 "LDG assignment "
6855 "for ldn %d, should be %d is %llu\n",
6856 np->port, ldn, ldg,
6857 (unsigned long long) nr64(LDG_NUM(ldn)));
6858 return -EINVAL;
6859 }
6860 } else
6861 nw64(LDG_NUM(ldn), ldg);
6862
6863 return 0;
6864 }
6865
6866 static int niu_set_ldg_timer_res(struct niu *np, int res)
6867 {
6868 if (res < 0 || res > LDG_TIMER_RES_VAL)
6869 return -EINVAL;
6870
6871
6872 nw64(LDG_TIMER_RES, res);
6873
6874 return 0;
6875 }
6876
6877 static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
6878 {
6879 if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
6880 (func < 0 || func > 3) ||
6881 (vector < 0 || vector > 0x1f))
6882 return -EINVAL;
6883
6884 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
6885
6886 return 0;
6887 }
6888
6889 static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
6890 {
6891 u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
6892 (addr << ESPC_PIO_STAT_ADDR_SHIFT));
6893 int limit;
6894
6895 if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
6896 return -EINVAL;
6897
6898 frame = frame_base;
6899 nw64(ESPC_PIO_STAT, frame);
6900 limit = 64;
6901 do {
6902 udelay(5);
6903 frame = nr64(ESPC_PIO_STAT);
6904 if (frame & ESPC_PIO_STAT_READ_END)
6905 break;
6906 } while (limit--);
6907 if (!(frame & ESPC_PIO_STAT_READ_END)) {
6908 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
6909 (unsigned long long) frame);
6910 return -ENODEV;
6911 }
6912
6913 frame = frame_base;
6914 nw64(ESPC_PIO_STAT, frame);
6915 limit = 64;
6916 do {
6917 udelay(5);
6918 frame = nr64(ESPC_PIO_STAT);
6919 if (frame & ESPC_PIO_STAT_READ_END)
6920 break;
6921 } while (limit--);
6922 if (!(frame & ESPC_PIO_STAT_READ_END)) {
6923 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
6924 (unsigned long long) frame);
6925 return -ENODEV;
6926 }
6927
6928 frame = nr64(ESPC_PIO_STAT);
6929 return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
6930 }
6931
6932 static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
6933 {
6934 int err = niu_pci_eeprom_read(np, off);
6935 u16 val;
6936
6937 if (err < 0)
6938 return err;
6939 val = (err << 8);
6940 err = niu_pci_eeprom_read(np, off + 1);
6941 if (err < 0)
6942 return err;
6943 val |= (err & 0xff);
6944
6945 return val;
6946 }
6947
6948 static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
6949 {
6950 int err = niu_pci_eeprom_read(np, off);
6951 u16 val;
6952
6953 if (err < 0)
6954 return err;
6955
6956 val = (err & 0xff);
6957 err = niu_pci_eeprom_read(np, off + 1);
6958 if (err < 0)
6959 return err;
6960
6961 val |= (err & 0xff) << 8;
6962
6963 return val;
6964 }
6965
6966 static int __devinit niu_pci_vpd_get_propname(struct niu *np,
6967 u32 off,
6968 char *namebuf,
6969 int namebuf_len)
6970 {
6971 int i;
6972
6973 for (i = 0; i < namebuf_len; i++) {
6974 int err = niu_pci_eeprom_read(np, off + i);
6975 if (err < 0)
6976 return err;
6977 *namebuf++ = err;
6978 if (!err)
6979 break;
6980 }
6981 if (i >= namebuf_len)
6982 return -EINVAL;
6983
6984 return i + 1;
6985 }
6986
6987 static void __devinit niu_vpd_parse_version(struct niu *np)
6988 {
6989 struct niu_vpd *vpd = &np->vpd;
6990 int len = strlen(vpd->version) + 1;
6991 const char *s = vpd->version;
6992 int i;
6993
6994 for (i = 0; i < len - 5; i++) {
6995 if (!strncmp(s + i, "FCode ", 5))
6996 break;
6997 }
6998 if (i >= len - 5)
6999 return;
7000
7001 s += i + 5;
7002 sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
7003
7004 niudbg(PROBE, "VPD_SCAN: FCODE major(%d) minor(%d)\n",
7005 vpd->fcode_major, vpd->fcode_minor);
7006 if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
7007 (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
7008 vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
7009 np->flags |= NIU_FLAGS_VPD_VALID;
7010 }
7011
7012 /* ESPC_PIO_EN_ENABLE must be set */
7013 static int __devinit niu_pci_vpd_scan_props(struct niu *np,
7014 u32 start, u32 end)
7015 {
7016 unsigned int found_mask = 0;
7017 #define FOUND_MASK_MODEL 0x00000001
7018 #define FOUND_MASK_BMODEL 0x00000002
7019 #define FOUND_MASK_VERS 0x00000004
7020 #define FOUND_MASK_MAC 0x00000008
7021 #define FOUND_MASK_NMAC 0x00000010
7022 #define FOUND_MASK_PHY 0x00000020
7023 #define FOUND_MASK_ALL 0x0000003f
7024
7025 niudbg(PROBE, "VPD_SCAN: start[%x] end[%x]\n",
7026 start, end);
7027 while (start < end) {
7028 int len, err, instance, type, prop_len;
7029 char namebuf[64];
7030 u8 *prop_buf;
7031 int max_len;
7032
7033 if (found_mask == FOUND_MASK_ALL) {
7034 niu_vpd_parse_version(np);
7035 return 1;
7036 }
7037
7038 err = niu_pci_eeprom_read(np, start + 2);
7039 if (err < 0)
7040 return err;
7041 len = err;
7042 start += 3;
7043
7044 instance = niu_pci_eeprom_read(np, start);
7045 type = niu_pci_eeprom_read(np, start + 3);
7046 prop_len = niu_pci_eeprom_read(np, start + 4);
7047 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
7048 if (err < 0)
7049 return err;
7050
7051 prop_buf = NULL;
7052 max_len = 0;
7053 if (!strcmp(namebuf, "model")) {
7054 prop_buf = np->vpd.model;
7055 max_len = NIU_VPD_MODEL_MAX;
7056 found_mask |= FOUND_MASK_MODEL;
7057 } else if (!strcmp(namebuf, "board-model")) {
7058 prop_buf = np->vpd.board_model;
7059 max_len = NIU_VPD_BD_MODEL_MAX;
7060 found_mask |= FOUND_MASK_BMODEL;
7061 } else if (!strcmp(namebuf, "version")) {
7062 prop_buf = np->vpd.version;
7063 max_len = NIU_VPD_VERSION_MAX;
7064 found_mask |= FOUND_MASK_VERS;
7065 } else if (!strcmp(namebuf, "local-mac-address")) {
7066 prop_buf = np->vpd.local_mac;
7067 max_len = ETH_ALEN;
7068 found_mask |= FOUND_MASK_MAC;
7069 } else if (!strcmp(namebuf, "num-mac-addresses")) {
7070 prop_buf = &np->vpd.mac_num;
7071 max_len = 1;
7072 found_mask |= FOUND_MASK_NMAC;
7073 } else if (!strcmp(namebuf, "phy-type")) {
7074 prop_buf = np->vpd.phy_type;
7075 max_len = NIU_VPD_PHY_TYPE_MAX;
7076 found_mask |= FOUND_MASK_PHY;
7077 }
7078
7079 if (max_len && prop_len > max_len) {
7080 dev_err(np->device, PFX "Property '%s' length (%d) is "
7081 "too long.\n", namebuf, prop_len);
7082 return -EINVAL;
7083 }
7084
7085 if (prop_buf) {
7086 u32 off = start + 5 + err;
7087 int i;
7088
7089 niudbg(PROBE, "VPD_SCAN: Reading in property [%s] "
7090 "len[%d]\n", namebuf, prop_len);
7091 for (i = 0; i < prop_len; i++)
7092 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
7093 }
7094
7095 start += len;
7096 }
7097
7098 return 0;
7099 }
7100
7101 /* ESPC_PIO_EN_ENABLE must be set */
7102 static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
7103 {
7104 u32 offset;
7105 int err;
7106
7107 err = niu_pci_eeprom_read16_swp(np, start + 1);
7108 if (err < 0)
7109 return;
7110
7111 offset = err + 3;
7112
7113 while (start + offset < ESPC_EEPROM_SIZE) {
7114 u32 here = start + offset;
7115 u32 end;
7116
7117 err = niu_pci_eeprom_read(np, here);
7118 if (err != 0x90)
7119 return;
7120
7121 err = niu_pci_eeprom_read16_swp(np, here + 1);
7122 if (err < 0)
7123 return;
7124
7125 here = start + offset + 3;
7126 end = start + offset + err;
7127
7128 offset += err;
7129
7130 err = niu_pci_vpd_scan_props(np, here, end);
7131 if (err < 0 || err == 1)
7132 return;
7133 }
7134 }
7135
7136 /* ESPC_PIO_EN_ENABLE must be set */
7137 static u32 __devinit niu_pci_vpd_offset(struct niu *np)
7138 {
7139 u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
7140 int err;
7141
7142 while (start < end) {
7143 ret = start;
7144
7145 /* ROM header signature? */
7146 err = niu_pci_eeprom_read16(np, start + 0);
7147 if (err != 0x55aa)
7148 return 0;
7149
7150 /* Apply offset to PCI data structure. */
7151 err = niu_pci_eeprom_read16(np, start + 23);
7152 if (err < 0)
7153 return 0;
7154 start += err;
7155
7156 /* Check for "PCIR" signature. */
7157 err = niu_pci_eeprom_read16(np, start + 0);
7158 if (err != 0x5043)
7159 return 0;
7160 err = niu_pci_eeprom_read16(np, start + 2);
7161 if (err != 0x4952)
7162 return 0;
7163
7164 /* Check for OBP image type. */
7165 err = niu_pci_eeprom_read(np, start + 20);
7166 if (err < 0)
7167 return 0;
7168 if (err != 0x01) {
7169 err = niu_pci_eeprom_read(np, ret + 2);
7170 if (err < 0)
7171 return 0;
7172
7173 start = ret + (err * 512);
7174 continue;
7175 }
7176
7177 err = niu_pci_eeprom_read16_swp(np, start + 8);
7178 if (err < 0)
7179 return err;
7180 ret += err;
7181
7182 err = niu_pci_eeprom_read(np, ret + 0);
7183 if (err != 0x82)
7184 return 0;
7185
7186 return ret;
7187 }
7188
7189 return 0;
7190 }
7191
7192 static int __devinit niu_phy_type_prop_decode(struct niu *np,
7193 const char *phy_prop)
7194 {
7195 if (!strcmp(phy_prop, "mif")) {
7196 /* 1G copper, MII */
7197 np->flags &= ~(NIU_FLAGS_FIBER |
7198 NIU_FLAGS_10G);
7199 np->mac_xcvr = MAC_XCVR_MII;
7200 } else if (!strcmp(phy_prop, "xgf")) {
7201 /* 10G fiber, XPCS */
7202 np->flags |= (NIU_FLAGS_10G |
7203 NIU_FLAGS_FIBER);
7204 np->mac_xcvr = MAC_XCVR_XPCS;
7205 } else if (!strcmp(phy_prop, "pcs")) {
7206 /* 1G fiber, PCS */
7207 np->flags &= ~NIU_FLAGS_10G;
7208 np->flags |= NIU_FLAGS_FIBER;
7209 np->mac_xcvr = MAC_XCVR_PCS;
7210 } else if (!strcmp(phy_prop, "xgc")) {
7211 /* 10G copper, XPCS */
7212 np->flags |= NIU_FLAGS_10G;
7213 np->flags &= ~NIU_FLAGS_FIBER;
7214 np->mac_xcvr = MAC_XCVR_XPCS;
7215 } else {
7216 return -EINVAL;
7217 }
7218 return 0;
7219 }
7220
7221 static int niu_pci_vpd_get_nports(struct niu *np)
7222 {
7223 int ports = 0;
7224
7225 if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
7226 (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
7227 (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
7228 (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
7229 (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
7230 ports = 4;
7231 } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
7232 (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
7233 (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
7234 (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
7235 ports = 2;
7236 }
7237
7238 return ports;
7239 }
7240
7241 static void __devinit niu_pci_vpd_validate(struct niu *np)
7242 {
7243 struct net_device *dev = np->dev;
7244 struct niu_vpd *vpd = &np->vpd;
7245 u8 val8;
7246
7247 if (!is_valid_ether_addr(&vpd->local_mac[0])) {
7248 dev_err(np->device, PFX "VPD MAC invalid, "
7249 "falling back to SPROM.\n");
7250
7251 np->flags &= ~NIU_FLAGS_VPD_VALID;
7252 return;
7253 }
7254
7255 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
7256 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
7257 np->flags |= NIU_FLAGS_10G;
7258 np->flags &= ~NIU_FLAGS_FIBER;
7259 np->flags |= NIU_FLAGS_XCVR_SERDES;
7260 np->mac_xcvr = MAC_XCVR_PCS;
7261 if (np->port > 1) {
7262 np->flags |= NIU_FLAGS_FIBER;
7263 np->flags &= ~NIU_FLAGS_10G;
7264 }
7265 if (np->flags & NIU_FLAGS_10G)
7266 np->mac_xcvr = MAC_XCVR_XPCS;
7267 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
7268 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
7269 NIU_FLAGS_HOTPLUG_PHY);
7270 } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
7271 dev_err(np->device, PFX "Illegal phy string [%s].\n",
7272 np->vpd.phy_type);
7273 dev_err(np->device, PFX "Falling back to SPROM.\n");
7274 np->flags &= ~NIU_FLAGS_VPD_VALID;
7275 return;
7276 }
7277
7278 memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
7279
7280 val8 = dev->perm_addr[5];
7281 dev->perm_addr[5] += np->port;
7282 if (dev->perm_addr[5] < val8)
7283 dev->perm_addr[4]++;
7284
7285 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
7286 }
7287
7288 static int __devinit niu_pci_probe_sprom(struct niu *np)
7289 {
7290 struct net_device *dev = np->dev;
7291 int len, i;
7292 u64 val, sum;
7293 u8 val8;
7294
7295 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
7296 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
7297 len = val / 4;
7298
7299 np->eeprom_len = len;
7300
7301 niudbg(PROBE, "SPROM: Image size %llu\n", (unsigned long long) val);
7302
7303 sum = 0;
7304 for (i = 0; i < len; i++) {
7305 val = nr64(ESPC_NCR(i));
7306 sum += (val >> 0) & 0xff;
7307 sum += (val >> 8) & 0xff;
7308 sum += (val >> 16) & 0xff;
7309 sum += (val >> 24) & 0xff;
7310 }
7311 niudbg(PROBE, "SPROM: Checksum %x\n", (int)(sum & 0xff));
7312 if ((sum & 0xff) != 0xab) {
7313 dev_err(np->device, PFX "Bad SPROM checksum "
7314 "(%x, should be 0xab)\n", (int) (sum & 0xff));
7315 return -EINVAL;
7316 }
7317
7318 val = nr64(ESPC_PHY_TYPE);
7319 switch (np->port) {
7320 case 0:
7321 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
7322 ESPC_PHY_TYPE_PORT0_SHIFT;
7323 break;
7324 case 1:
7325 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
7326 ESPC_PHY_TYPE_PORT1_SHIFT;
7327 break;
7328 case 2:
7329 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
7330 ESPC_PHY_TYPE_PORT2_SHIFT;
7331 break;
7332 case 3:
7333 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
7334 ESPC_PHY_TYPE_PORT3_SHIFT;
7335 break;
7336 default:
7337 dev_err(np->device, PFX "Bogus port number %u\n",
7338 np->port);
7339 return -EINVAL;
7340 }
7341 niudbg(PROBE, "SPROM: PHY type %x\n", val8);
7342
7343 switch (val8) {
7344 case ESPC_PHY_TYPE_1G_COPPER:
7345 /* 1G copper, MII */
7346 np->flags &= ~(NIU_FLAGS_FIBER |
7347 NIU_FLAGS_10G);
7348 np->mac_xcvr = MAC_XCVR_MII;
7349 break;
7350
7351 case ESPC_PHY_TYPE_1G_FIBER:
7352 /* 1G fiber, PCS */
7353 np->flags &= ~NIU_FLAGS_10G;
7354 np->flags |= NIU_FLAGS_FIBER;
7355 np->mac_xcvr = MAC_XCVR_PCS;
7356 break;
7357
7358 case ESPC_PHY_TYPE_10G_COPPER:
7359 /* 10G copper, XPCS */
7360 np->flags |= NIU_FLAGS_10G;
7361 np->flags &= ~NIU_FLAGS_FIBER;
7362 np->mac_xcvr = MAC_XCVR_XPCS;
7363 break;
7364
7365 case ESPC_PHY_TYPE_10G_FIBER:
7366 /* 10G fiber, XPCS */
7367 np->flags |= (NIU_FLAGS_10G |
7368 NIU_FLAGS_FIBER);
7369 np->mac_xcvr = MAC_XCVR_XPCS;
7370 break;
7371
7372 default:
7373 dev_err(np->device, PFX "Bogus SPROM phy type %u\n", val8);
7374 return -EINVAL;
7375 }
7376
7377 val = nr64(ESPC_MAC_ADDR0);
7378 niudbg(PROBE, "SPROM: MAC_ADDR0[%08llx]\n",
7379 (unsigned long long) val);
7380 dev->perm_addr[0] = (val >> 0) & 0xff;
7381 dev->perm_addr[1] = (val >> 8) & 0xff;
7382 dev->perm_addr[2] = (val >> 16) & 0xff;
7383 dev->perm_addr[3] = (val >> 24) & 0xff;
7384
7385 val = nr64(ESPC_MAC_ADDR1);
7386 niudbg(PROBE, "SPROM: MAC_ADDR1[%08llx]\n",
7387 (unsigned long long) val);
7388 dev->perm_addr[4] = (val >> 0) & 0xff;
7389 dev->perm_addr[5] = (val >> 8) & 0xff;
7390
7391 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
7392 dev_err(np->device, PFX "SPROM MAC address invalid\n");
7393 dev_err(np->device, PFX "[ \n");
7394 for (i = 0; i < 6; i++)
7395 printk("%02x ", dev->perm_addr[i]);
7396 printk("]\n");
7397 return -EINVAL;
7398 }
7399
7400 val8 = dev->perm_addr[5];
7401 dev->perm_addr[5] += np->port;
7402 if (dev->perm_addr[5] < val8)
7403 dev->perm_addr[4]++;
7404
7405 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
7406
7407 val = nr64(ESPC_MOD_STR_LEN);
7408 niudbg(PROBE, "SPROM: MOD_STR_LEN[%llu]\n",
7409 (unsigned long long) val);
7410 if (val >= 8 * 4)
7411 return -EINVAL;
7412
7413 for (i = 0; i < val; i += 4) {
7414 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
7415
7416 np->vpd.model[i + 3] = (tmp >> 0) & 0xff;
7417 np->vpd.model[i + 2] = (tmp >> 8) & 0xff;
7418 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
7419 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
7420 }
7421 np->vpd.model[val] = '\0';
7422
7423 val = nr64(ESPC_BD_MOD_STR_LEN);
7424 niudbg(PROBE, "SPROM: BD_MOD_STR_LEN[%llu]\n",
7425 (unsigned long long) val);
7426 if (val >= 4 * 4)
7427 return -EINVAL;
7428
7429 for (i = 0; i < val; i += 4) {
7430 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
7431
7432 np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff;
7433 np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff;
7434 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
7435 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
7436 }
7437 np->vpd.board_model[val] = '\0';
7438
7439 np->vpd.mac_num =
7440 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
7441 niudbg(PROBE, "SPROM: NUM_PORTS_MACS[%d]\n",
7442 np->vpd.mac_num);
7443
7444 return 0;
7445 }
7446
7447 static int __devinit niu_get_and_validate_port(struct niu *np)
7448 {
7449 struct niu_parent *parent = np->parent;
7450
7451 if (np->port <= 1)
7452 np->flags |= NIU_FLAGS_XMAC;
7453
7454 if (!parent->num_ports) {
7455 if (parent->plat_type == PLAT_TYPE_NIU) {
7456 parent->num_ports = 2;
7457 } else {
7458 parent->num_ports = niu_pci_vpd_get_nports(np);
7459 if (!parent->num_ports) {
7460 /* Fall back to SPROM as last resort.
7461 * This will fail on most cards.
7462 */
7463 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
7464 ESPC_NUM_PORTS_MACS_VAL;
7465
7466 /* All of the current probing methods fail on
7467 * Maramba on-board parts.
7468 */
7469 if (!parent->num_ports)
7470 parent->num_ports = 4;
7471 }
7472 }
7473 }
7474
7475 niudbg(PROBE, "niu_get_and_validate_port: port[%d] num_ports[%d]\n",
7476 np->port, parent->num_ports);
7477 if (np->port >= parent->num_ports)
7478 return -ENODEV;
7479
7480 return 0;
7481 }
7482
7483 static int __devinit phy_record(struct niu_parent *parent,
7484 struct phy_probe_info *p,
7485 int dev_id_1, int dev_id_2, u8 phy_port,
7486 int type)
7487 {
7488 u32 id = (dev_id_1 << 16) | dev_id_2;
7489 u8 idx;
7490
7491 if (dev_id_1 < 0 || dev_id_2 < 0)
7492 return 0;
7493 if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
7494 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
7495 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011) &&
7496 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8706))
7497 return 0;
7498 } else {
7499 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
7500 return 0;
7501 }
7502
7503 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
7504 parent->index, id,
7505 (type == PHY_TYPE_PMA_PMD ?
7506 "PMA/PMD" :
7507 (type == PHY_TYPE_PCS ?
7508 "PCS" : "MII")),
7509 phy_port);
7510
7511 if (p->cur[type] >= NIU_MAX_PORTS) {
7512 printk(KERN_ERR PFX "Too many PHY ports.\n");
7513 return -EINVAL;
7514 }
7515 idx = p->cur[type];
7516 p->phy_id[type][idx] = id;
7517 p->phy_port[type][idx] = phy_port;
7518 p->cur[type] = idx + 1;
7519 return 0;
7520 }
7521
7522 static int __devinit port_has_10g(struct phy_probe_info *p, int port)
7523 {
7524 int i;
7525
7526 for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
7527 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
7528 return 1;
7529 }
7530 for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
7531 if (p->phy_port[PHY_TYPE_PCS][i] == port)
7532 return 1;
7533 }
7534
7535 return 0;
7536 }
7537
7538 static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
7539 {
7540 int port, cnt;
7541
7542 cnt = 0;
7543 *lowest = 32;
7544 for (port = 8; port < 32; port++) {
7545 if (port_has_10g(p, port)) {
7546 if (!cnt)
7547 *lowest = port;
7548 cnt++;
7549 }
7550 }
7551
7552 return cnt;
7553 }
7554
7555 static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
7556 {
7557 *lowest = 32;
7558 if (p->cur[PHY_TYPE_MII])
7559 *lowest = p->phy_port[PHY_TYPE_MII][0];
7560
7561 return p->cur[PHY_TYPE_MII];
7562 }
7563
7564 static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
7565 {
7566 int num_ports = parent->num_ports;
7567 int i;
7568
7569 for (i = 0; i < num_ports; i++) {
7570 parent->rxchan_per_port[i] = (16 / num_ports);
7571 parent->txchan_per_port[i] = (16 / num_ports);
7572
7573 pr_info(PFX "niu%d: Port %u [%u RX chans] "
7574 "[%u TX chans]\n",
7575 parent->index, i,
7576 parent->rxchan_per_port[i],
7577 parent->txchan_per_port[i]);
7578 }
7579 }
7580
7581 static void __devinit niu_divide_channels(struct niu_parent *parent,
7582 int num_10g, int num_1g)
7583 {
7584 int num_ports = parent->num_ports;
7585 int rx_chans_per_10g, rx_chans_per_1g;
7586 int tx_chans_per_10g, tx_chans_per_1g;
7587 int i, tot_rx, tot_tx;
7588
7589 if (!num_10g || !num_1g) {
7590 rx_chans_per_10g = rx_chans_per_1g =
7591 (NIU_NUM_RXCHAN / num_ports);
7592 tx_chans_per_10g = tx_chans_per_1g =
7593 (NIU_NUM_TXCHAN / num_ports);
7594 } else {
7595 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
7596 rx_chans_per_10g = (NIU_NUM_RXCHAN -
7597 (rx_chans_per_1g * num_1g)) /
7598 num_10g;
7599
7600 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
7601 tx_chans_per_10g = (NIU_NUM_TXCHAN -
7602 (tx_chans_per_1g * num_1g)) /
7603 num_10g;
7604 }
7605
7606 tot_rx = tot_tx = 0;
7607 for (i = 0; i < num_ports; i++) {
7608 int type = phy_decode(parent->port_phy, i);
7609
7610 if (type == PORT_TYPE_10G) {
7611 parent->rxchan_per_port[i] = rx_chans_per_10g;
7612 parent->txchan_per_port[i] = tx_chans_per_10g;
7613 } else {
7614 parent->rxchan_per_port[i] = rx_chans_per_1g;
7615 parent->txchan_per_port[i] = tx_chans_per_1g;
7616 }
7617 pr_info(PFX "niu%d: Port %u [%u RX chans] "
7618 "[%u TX chans]\n",
7619 parent->index, i,
7620 parent->rxchan_per_port[i],
7621 parent->txchan_per_port[i]);
7622 tot_rx += parent->rxchan_per_port[i];
7623 tot_tx += parent->txchan_per_port[i];
7624 }
7625
7626 if (tot_rx > NIU_NUM_RXCHAN) {
7627 printk(KERN_ERR PFX "niu%d: Too many RX channels (%d), "
7628 "resetting to one per port.\n",
7629 parent->index, tot_rx);
7630 for (i = 0; i < num_ports; i++)
7631 parent->rxchan_per_port[i] = 1;
7632 }
7633 if (tot_tx > NIU_NUM_TXCHAN) {
7634 printk(KERN_ERR PFX "niu%d: Too many TX channels (%d), "
7635 "resetting to one per port.\n",
7636 parent->index, tot_tx);
7637 for (i = 0; i < num_ports; i++)
7638 parent->txchan_per_port[i] = 1;
7639 }
7640 if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
7641 printk(KERN_WARNING PFX "niu%d: Driver bug, wasted channels, "
7642 "RX[%d] TX[%d]\n",
7643 parent->index, tot_rx, tot_tx);
7644 }
7645 }
7646
7647 static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
7648 int num_10g, int num_1g)
7649 {
7650 int i, num_ports = parent->num_ports;
7651 int rdc_group, rdc_groups_per_port;
7652 int rdc_channel_base;
7653
7654 rdc_group = 0;
7655 rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
7656
7657 rdc_channel_base = 0;
7658
7659 for (i = 0; i < num_ports; i++) {
7660 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
7661 int grp, num_channels = parent->rxchan_per_port[i];
7662 int this_channel_offset;
7663
7664 tp->first_table_num = rdc_group;
7665 tp->num_tables = rdc_groups_per_port;
7666 this_channel_offset = 0;
7667 for (grp = 0; grp < tp->num_tables; grp++) {
7668 struct rdc_table *rt = &tp->tables[grp];
7669 int slot;
7670
7671 pr_info(PFX "niu%d: Port %d RDC tbl(%d) [ ",
7672 parent->index, i, tp->first_table_num + grp);
7673 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
7674 rt->rxdma_channel[slot] =
7675 rdc_channel_base + this_channel_offset;
7676
7677 printk("%d ", rt->rxdma_channel[slot]);
7678
7679 if (++this_channel_offset == num_channels)
7680 this_channel_offset = 0;
7681 }
7682 printk("]\n");
7683 }
7684
7685 parent->rdc_default[i] = rdc_channel_base;
7686
7687 rdc_channel_base += num_channels;
7688 rdc_group += rdc_groups_per_port;
7689 }
7690 }
7691
7692 static int __devinit fill_phy_probe_info(struct niu *np,
7693 struct niu_parent *parent,
7694 struct phy_probe_info *info)
7695 {
7696 unsigned long flags;
7697 int port, err;
7698
7699 memset(info, 0, sizeof(*info));
7700
7701 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
7702 niu_lock_parent(np, flags);
7703 err = 0;
7704 for (port = 8; port < 32; port++) {
7705 int dev_id_1, dev_id_2;
7706
7707 dev_id_1 = mdio_read(np, port,
7708 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
7709 dev_id_2 = mdio_read(np, port,
7710 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
7711 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
7712 PHY_TYPE_PMA_PMD);
7713 if (err)
7714 break;
7715 dev_id_1 = mdio_read(np, port,
7716 NIU_PCS_DEV_ADDR, MII_PHYSID1);
7717 dev_id_2 = mdio_read(np, port,
7718 NIU_PCS_DEV_ADDR, MII_PHYSID2);
7719 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
7720 PHY_TYPE_PCS);
7721 if (err)
7722 break;
7723 dev_id_1 = mii_read(np, port, MII_PHYSID1);
7724 dev_id_2 = mii_read(np, port, MII_PHYSID2);
7725 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
7726 PHY_TYPE_MII);
7727 if (err)
7728 break;
7729 }
7730 niu_unlock_parent(np, flags);
7731
7732 return err;
7733 }
7734
7735 static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
7736 {
7737 struct phy_probe_info *info = &parent->phy_probe_info;
7738 int lowest_10g, lowest_1g;
7739 int num_10g, num_1g;
7740 u32 val;
7741 int err;
7742
7743 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
7744 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
7745 num_10g = 0;
7746 num_1g = 2;
7747 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
7748 parent->num_ports = 4;
7749 val = (phy_encode(PORT_TYPE_1G, 0) |
7750 phy_encode(PORT_TYPE_1G, 1) |
7751 phy_encode(PORT_TYPE_1G, 2) |
7752 phy_encode(PORT_TYPE_1G, 3));
7753 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
7754 num_10g = 2;
7755 num_1g = 0;
7756 parent->num_ports = 2;
7757 val = (phy_encode(PORT_TYPE_10G, 0) |
7758 phy_encode(PORT_TYPE_10G, 1));
7759 } else {
7760 err = fill_phy_probe_info(np, parent, info);
7761 if (err)
7762 return err;
7763
7764 num_10g = count_10g_ports(info, &lowest_10g);
7765 num_1g = count_1g_ports(info, &lowest_1g);
7766
7767 switch ((num_10g << 4) | num_1g) {
7768 case 0x24:
7769 if (lowest_1g == 10)
7770 parent->plat_type = PLAT_TYPE_VF_P0;
7771 else if (lowest_1g == 26)
7772 parent->plat_type = PLAT_TYPE_VF_P1;
7773 else
7774 goto unknown_vg_1g_port;
7775
7776 /* fallthru */
7777 case 0x22:
7778 val = (phy_encode(PORT_TYPE_10G, 0) |
7779 phy_encode(PORT_TYPE_10G, 1) |
7780 phy_encode(PORT_TYPE_1G, 2) |
7781 phy_encode(PORT_TYPE_1G, 3));
7782 break;
7783
7784 case 0x20:
7785 val = (phy_encode(PORT_TYPE_10G, 0) |
7786 phy_encode(PORT_TYPE_10G, 1));
7787 break;
7788
7789 case 0x10:
7790 val = phy_encode(PORT_TYPE_10G, np->port);
7791 break;
7792
7793 case 0x14:
7794 if (lowest_1g == 10)
7795 parent->plat_type = PLAT_TYPE_VF_P0;
7796 else if (lowest_1g == 26)
7797 parent->plat_type = PLAT_TYPE_VF_P1;
7798 else
7799 goto unknown_vg_1g_port;
7800
7801 /* fallthru */
7802 case 0x13:
7803 if ((lowest_10g & 0x7) == 0)
7804 val = (phy_encode(PORT_TYPE_10G, 0) |
7805 phy_encode(PORT_TYPE_1G, 1) |
7806 phy_encode(PORT_TYPE_1G, 2) |
7807 phy_encode(PORT_TYPE_1G, 3));
7808 else
7809 val = (phy_encode(PORT_TYPE_1G, 0) |
7810 phy_encode(PORT_TYPE_10G, 1) |
7811 phy_encode(PORT_TYPE_1G, 2) |
7812 phy_encode(PORT_TYPE_1G, 3));
7813 break;
7814
7815 case 0x04:
7816 if (lowest_1g == 10)
7817 parent->plat_type = PLAT_TYPE_VF_P0;
7818 else if (lowest_1g == 26)
7819 parent->plat_type = PLAT_TYPE_VF_P1;
7820 else
7821 goto unknown_vg_1g_port;
7822
7823 val = (phy_encode(PORT_TYPE_1G, 0) |
7824 phy_encode(PORT_TYPE_1G, 1) |
7825 phy_encode(PORT_TYPE_1G, 2) |
7826 phy_encode(PORT_TYPE_1G, 3));
7827 break;
7828
7829 default:
7830 printk(KERN_ERR PFX "Unsupported port config "
7831 "10G[%d] 1G[%d]\n",
7832 num_10g, num_1g);
7833 return -EINVAL;
7834 }
7835 }
7836
7837 parent->port_phy = val;
7838
7839 if (parent->plat_type == PLAT_TYPE_NIU)
7840 niu_n2_divide_channels(parent);
7841 else
7842 niu_divide_channels(parent, num_10g, num_1g);
7843
7844 niu_divide_rdc_groups(parent, num_10g, num_1g);
7845
7846 return 0;
7847
7848 unknown_vg_1g_port:
7849 printk(KERN_ERR PFX "Cannot identify platform type, 1gport=%d\n",
7850 lowest_1g);
7851 return -EINVAL;
7852 }
7853
7854 static int __devinit niu_probe_ports(struct niu *np)
7855 {
7856 struct niu_parent *parent = np->parent;
7857 int err, i;
7858
7859 niudbg(PROBE, "niu_probe_ports(): port_phy[%08x]\n",
7860 parent->port_phy);
7861
7862 if (parent->port_phy == PORT_PHY_UNKNOWN) {
7863 err = walk_phys(np, parent);
7864 if (err)
7865 return err;
7866
7867 niu_set_ldg_timer_res(np, 2);
7868 for (i = 0; i <= LDN_MAX; i++)
7869 niu_ldn_irq_enable(np, i, 0);
7870 }
7871
7872 if (parent->port_phy == PORT_PHY_INVALID)
7873 return -EINVAL;
7874
7875 return 0;
7876 }
7877
7878 static int __devinit niu_classifier_swstate_init(struct niu *np)
7879 {
7880 struct niu_classifier *cp = &np->clas;
7881
7882 niudbg(PROBE, "niu_classifier_swstate_init: num_tcam(%d)\n",
7883 np->parent->tcam_num_entries);
7884
7885 cp->tcam_index = (u16) np->port;
7886 cp->h1_init = 0xffffffff;
7887 cp->h2_init = 0xffff;
7888
7889 return fflp_early_init(np);
7890 }
7891
7892 static void __devinit niu_link_config_init(struct niu *np)
7893 {
7894 struct niu_link_config *lp = &np->link_config;
7895
7896 lp->advertising = (ADVERTISED_10baseT_Half |
7897 ADVERTISED_10baseT_Full |
7898 ADVERTISED_100baseT_Half |
7899 ADVERTISED_100baseT_Full |
7900 ADVERTISED_1000baseT_Half |
7901 ADVERTISED_1000baseT_Full |
7902 ADVERTISED_10000baseT_Full |
7903 ADVERTISED_Autoneg);
7904 lp->speed = lp->active_speed = SPEED_INVALID;
7905 lp->duplex = lp->active_duplex = DUPLEX_INVALID;
7906 #if 0
7907 lp->loopback_mode = LOOPBACK_MAC;
7908 lp->active_speed = SPEED_10000;
7909 lp->active_duplex = DUPLEX_FULL;
7910 #else
7911 lp->loopback_mode = LOOPBACK_DISABLED;
7912 #endif
7913 }
7914
7915 static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
7916 {
7917 switch (np->port) {
7918 case 0:
7919 np->mac_regs = np->regs + XMAC_PORT0_OFF;
7920 np->ipp_off = 0x00000;
7921 np->pcs_off = 0x04000;
7922 np->xpcs_off = 0x02000;
7923 break;
7924
7925 case 1:
7926 np->mac_regs = np->regs + XMAC_PORT1_OFF;
7927 np->ipp_off = 0x08000;
7928 np->pcs_off = 0x0a000;
7929 np->xpcs_off = 0x08000;
7930 break;
7931
7932 case 2:
7933 np->mac_regs = np->regs + BMAC_PORT2_OFF;
7934 np->ipp_off = 0x04000;
7935 np->pcs_off = 0x0e000;
7936 np->xpcs_off = ~0UL;
7937 break;
7938
7939 case 3:
7940 np->mac_regs = np->regs + BMAC_PORT3_OFF;
7941 np->ipp_off = 0x0c000;
7942 np->pcs_off = 0x12000;
7943 np->xpcs_off = ~0UL;
7944 break;
7945
7946 default:
7947 dev_err(np->device, PFX "Port %u is invalid, cannot "
7948 "compute MAC block offset.\n", np->port);
7949 return -EINVAL;
7950 }
7951
7952 return 0;
7953 }
7954
7955 static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
7956 {
7957 struct msix_entry msi_vec[NIU_NUM_LDG];
7958 struct niu_parent *parent = np->parent;
7959 struct pci_dev *pdev = np->pdev;
7960 int i, num_irqs, err;
7961 u8 first_ldg;
7962
7963 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
7964 for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
7965 ldg_num_map[i] = first_ldg + i;
7966
7967 num_irqs = (parent->rxchan_per_port[np->port] +
7968 parent->txchan_per_port[np->port] +
7969 (np->port == 0 ? 3 : 1));
7970 BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
7971
7972 retry:
7973 for (i = 0; i < num_irqs; i++) {
7974 msi_vec[i].vector = 0;
7975 msi_vec[i].entry = i;
7976 }
7977
7978 err = pci_enable_msix(pdev, msi_vec, num_irqs);
7979 if (err < 0) {
7980 np->flags &= ~NIU_FLAGS_MSIX;
7981 return;
7982 }
7983 if (err > 0) {
7984 num_irqs = err;
7985 goto retry;
7986 }
7987
7988 np->flags |= NIU_FLAGS_MSIX;
7989 for (i = 0; i < num_irqs; i++)
7990 np->ldg[i].irq = msi_vec[i].vector;
7991 np->num_ldg = num_irqs;
7992 }
7993
7994 static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
7995 {
7996 #ifdef CONFIG_SPARC64
7997 struct of_device *op = np->op;
7998 const u32 *int_prop;
7999 int i;
8000
8001 int_prop = of_get_property(op->node, "interrupts", NULL);
8002 if (!int_prop)
8003 return -ENODEV;
8004
8005 for (i = 0; i < op->num_irqs; i++) {
8006 ldg_num_map[i] = int_prop[i];
8007 np->ldg[i].irq = op->irqs[i];
8008 }
8009
8010 np->num_ldg = op->num_irqs;
8011
8012 return 0;
8013 #else
8014 return -EINVAL;
8015 #endif
8016 }
8017
8018 static int __devinit niu_ldg_init(struct niu *np)
8019 {
8020 struct niu_parent *parent = np->parent;
8021 u8 ldg_num_map[NIU_NUM_LDG];
8022 int first_chan, num_chan;
8023 int i, err, ldg_rotor;
8024 u8 port;
8025
8026 np->num_ldg = 1;
8027 np->ldg[0].irq = np->dev->irq;
8028 if (parent->plat_type == PLAT_TYPE_NIU) {
8029 err = niu_n2_irq_init(np, ldg_num_map);
8030 if (err)
8031 return err;
8032 } else
8033 niu_try_msix(np, ldg_num_map);
8034
8035 port = np->port;
8036 for (i = 0; i < np->num_ldg; i++) {
8037 struct niu_ldg *lp = &np->ldg[i];
8038
8039 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
8040
8041 lp->np = np;
8042 lp->ldg_num = ldg_num_map[i];
8043 lp->timer = 2; /* XXX */
8044
8045 /* On N2 NIU the firmware has setup the SID mappings so they go
8046 * to the correct values that will route the LDG to the proper
8047 * interrupt in the NCU interrupt table.
8048 */
8049 if (np->parent->plat_type != PLAT_TYPE_NIU) {
8050 err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
8051 if (err)
8052 return err;
8053 }
8054 }
8055
8056 /* We adopt the LDG assignment ordering used by the N2 NIU
8057 * 'interrupt' properties because that simplifies a lot of
8058 * things. This ordering is:
8059 *
8060 * MAC
8061 * MIF (if port zero)
8062 * SYSERR (if port zero)
8063 * RX channels
8064 * TX channels
8065 */
8066
8067 ldg_rotor = 0;
8068
8069 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
8070 LDN_MAC(port));
8071 if (err)
8072 return err;
8073
8074 ldg_rotor++;
8075 if (ldg_rotor == np->num_ldg)
8076 ldg_rotor = 0;
8077
8078 if (port == 0) {
8079 err = niu_ldg_assign_ldn(np, parent,
8080 ldg_num_map[ldg_rotor],
8081 LDN_MIF);
8082 if (err)
8083 return err;
8084
8085 ldg_rotor++;
8086 if (ldg_rotor == np->num_ldg)
8087 ldg_rotor = 0;
8088
8089 err = niu_ldg_assign_ldn(np, parent,
8090 ldg_num_map[ldg_rotor],
8091 LDN_DEVICE_ERROR);
8092 if (err)
8093 return err;
8094
8095 ldg_rotor++;
8096 if (ldg_rotor == np->num_ldg)
8097 ldg_rotor = 0;
8098
8099 }
8100
8101 first_chan = 0;
8102 for (i = 0; i < port; i++)
8103 first_chan += parent->rxchan_per_port[port];
8104 num_chan = parent->rxchan_per_port[port];
8105
8106 for (i = first_chan; i < (first_chan + num_chan); i++) {
8107 err = niu_ldg_assign_ldn(np, parent,
8108 ldg_num_map[ldg_rotor],
8109 LDN_RXDMA(i));
8110 if (err)
8111 return err;
8112 ldg_rotor++;
8113 if (ldg_rotor == np->num_ldg)
8114 ldg_rotor = 0;
8115 }
8116
8117 first_chan = 0;
8118 for (i = 0; i < port; i++)
8119 first_chan += parent->txchan_per_port[port];
8120 num_chan = parent->txchan_per_port[port];
8121 for (i = first_chan; i < (first_chan + num_chan); i++) {
8122 err = niu_ldg_assign_ldn(np, parent,
8123 ldg_num_map[ldg_rotor],
8124 LDN_TXDMA(i));
8125 if (err)
8126 return err;
8127 ldg_rotor++;
8128 if (ldg_rotor == np->num_ldg)
8129 ldg_rotor = 0;
8130 }
8131
8132 return 0;
8133 }
8134
8135 static void __devexit niu_ldg_free(struct niu *np)
8136 {
8137 if (np->flags & NIU_FLAGS_MSIX)
8138 pci_disable_msix(np->pdev);
8139 }
8140
8141 static int __devinit niu_get_of_props(struct niu *np)
8142 {
8143 #ifdef CONFIG_SPARC64
8144 struct net_device *dev = np->dev;
8145 struct device_node *dp;
8146 const char *phy_type;
8147 const u8 *mac_addr;
8148 const char *model;
8149 int prop_len;
8150
8151 if (np->parent->plat_type == PLAT_TYPE_NIU)
8152 dp = np->op->node;
8153 else
8154 dp = pci_device_to_OF_node(np->pdev);
8155
8156 phy_type = of_get_property(dp, "phy-type", &prop_len);
8157 if (!phy_type) {
8158 dev_err(np->device, PFX "%s: OF node lacks "
8159 "phy-type property\n",
8160 dp->full_name);
8161 return -EINVAL;
8162 }
8163
8164 if (!strcmp(phy_type, "none"))
8165 return -ENODEV;
8166
8167 strcpy(np->vpd.phy_type, phy_type);
8168
8169 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
8170 dev_err(np->device, PFX "%s: Illegal phy string [%s].\n",
8171 dp->full_name, np->vpd.phy_type);
8172 return -EINVAL;
8173 }
8174
8175 mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
8176 if (!mac_addr) {
8177 dev_err(np->device, PFX "%s: OF node lacks "
8178 "local-mac-address property\n",
8179 dp->full_name);
8180 return -EINVAL;
8181 }
8182 if (prop_len != dev->addr_len) {
8183 dev_err(np->device, PFX "%s: OF MAC address prop len (%d) "
8184 "is wrong.\n",
8185 dp->full_name, prop_len);
8186 }
8187 memcpy(dev->perm_addr, mac_addr, dev->addr_len);
8188 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
8189 int i;
8190
8191 dev_err(np->device, PFX "%s: OF MAC address is invalid\n",
8192 dp->full_name);
8193 dev_err(np->device, PFX "%s: [ \n",
8194 dp->full_name);
8195 for (i = 0; i < 6; i++)
8196 printk("%02x ", dev->perm_addr[i]);
8197 printk("]\n");
8198 return -EINVAL;
8199 }
8200
8201 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8202
8203 model = of_get_property(dp, "model", &prop_len);
8204
8205 if (model)
8206 strcpy(np->vpd.model, model);
8207
8208 return 0;
8209 #else
8210 return -EINVAL;
8211 #endif
8212 }
8213
8214 static int __devinit niu_get_invariants(struct niu *np)
8215 {
8216 int err, have_props;
8217 u32 offset;
8218
8219 err = niu_get_of_props(np);
8220 if (err == -ENODEV)
8221 return err;
8222
8223 have_props = !err;
8224
8225 err = niu_init_mac_ipp_pcs_base(np);
8226 if (err)
8227 return err;
8228
8229 if (have_props) {
8230 err = niu_get_and_validate_port(np);
8231 if (err)
8232 return err;
8233
8234 } else {
8235 if (np->parent->plat_type == PLAT_TYPE_NIU)
8236 return -EINVAL;
8237
8238 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
8239 offset = niu_pci_vpd_offset(np);
8240 niudbg(PROBE, "niu_get_invariants: VPD offset [%08x]\n",
8241 offset);
8242 if (offset)
8243 niu_pci_vpd_fetch(np, offset);
8244 nw64(ESPC_PIO_EN, 0);
8245
8246 if (np->flags & NIU_FLAGS_VPD_VALID) {
8247 niu_pci_vpd_validate(np);
8248 err = niu_get_and_validate_port(np);
8249 if (err)
8250 return err;
8251 }
8252
8253 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
8254 err = niu_get_and_validate_port(np);
8255 if (err)
8256 return err;
8257 err = niu_pci_probe_sprom(np);
8258 if (err)
8259 return err;
8260 }
8261 }
8262
8263 err = niu_probe_ports(np);
8264 if (err)
8265 return err;
8266
8267 niu_ldg_init(np);
8268
8269 niu_classifier_swstate_init(np);
8270 niu_link_config_init(np);
8271
8272 err = niu_determine_phy_disposition(np);
8273 if (!err)
8274 err = niu_init_link(np);
8275
8276 return err;
8277 }
8278
8279 static LIST_HEAD(niu_parent_list);
8280 static DEFINE_MUTEX(niu_parent_lock);
8281 static int niu_parent_index;
8282
8283 static ssize_t show_port_phy(struct device *dev,
8284 struct device_attribute *attr, char *buf)
8285 {
8286 struct platform_device *plat_dev = to_platform_device(dev);
8287 struct niu_parent *p = plat_dev->dev.platform_data;
8288 u32 port_phy = p->port_phy;
8289 char *orig_buf = buf;
8290 int i;
8291
8292 if (port_phy == PORT_PHY_UNKNOWN ||
8293 port_phy == PORT_PHY_INVALID)
8294 return 0;
8295
8296 for (i = 0; i < p->num_ports; i++) {
8297 const char *type_str;
8298 int type;
8299
8300 type = phy_decode(port_phy, i);
8301 if (type == PORT_TYPE_10G)
8302 type_str = "10G";
8303 else
8304 type_str = "1G";
8305 buf += sprintf(buf,
8306 (i == 0) ? "%s" : " %s",
8307 type_str);
8308 }
8309 buf += sprintf(buf, "\n");
8310 return buf - orig_buf;
8311 }
8312
8313 static ssize_t show_plat_type(struct device *dev,
8314 struct device_attribute *attr, char *buf)
8315 {
8316 struct platform_device *plat_dev = to_platform_device(dev);
8317 struct niu_parent *p = plat_dev->dev.platform_data;
8318 const char *type_str;
8319
8320 switch (p->plat_type) {
8321 case PLAT_TYPE_ATLAS:
8322 type_str = "atlas";
8323 break;
8324 case PLAT_TYPE_NIU:
8325 type_str = "niu";
8326 break;
8327 case PLAT_TYPE_VF_P0:
8328 type_str = "vf_p0";
8329 break;
8330 case PLAT_TYPE_VF_P1:
8331 type_str = "vf_p1";
8332 break;
8333 default:
8334 type_str = "unknown";
8335 break;
8336 }
8337
8338 return sprintf(buf, "%s\n", type_str);
8339 }
8340
8341 static ssize_t __show_chan_per_port(struct device *dev,
8342 struct device_attribute *attr, char *buf,
8343 int rx)
8344 {
8345 struct platform_device *plat_dev = to_platform_device(dev);
8346 struct niu_parent *p = plat_dev->dev.platform_data;
8347 char *orig_buf = buf;
8348 u8 *arr;
8349 int i;
8350
8351 arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
8352
8353 for (i = 0; i < p->num_ports; i++) {
8354 buf += sprintf(buf,
8355 (i == 0) ? "%d" : " %d",
8356 arr[i]);
8357 }
8358 buf += sprintf(buf, "\n");
8359
8360 return buf - orig_buf;
8361 }
8362
8363 static ssize_t show_rxchan_per_port(struct device *dev,
8364 struct device_attribute *attr, char *buf)
8365 {
8366 return __show_chan_per_port(dev, attr, buf, 1);
8367 }
8368
8369 static ssize_t show_txchan_per_port(struct device *dev,
8370 struct device_attribute *attr, char *buf)
8371 {
8372 return __show_chan_per_port(dev, attr, buf, 1);
8373 }
8374
8375 static ssize_t show_num_ports(struct device *dev,
8376 struct device_attribute *attr, char *buf)
8377 {
8378 struct platform_device *plat_dev = to_platform_device(dev);
8379 struct niu_parent *p = plat_dev->dev.platform_data;
8380
8381 return sprintf(buf, "%d\n", p->num_ports);
8382 }
8383
8384 static struct device_attribute niu_parent_attributes[] = {
8385 __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
8386 __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
8387 __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
8388 __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
8389 __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
8390 {}
8391 };
8392
8393 static struct niu_parent * __devinit niu_new_parent(struct niu *np,
8394 union niu_parent_id *id,
8395 u8 ptype)
8396 {
8397 struct platform_device *plat_dev;
8398 struct niu_parent *p;
8399 int i;
8400
8401 niudbg(PROBE, "niu_new_parent: Creating new parent.\n");
8402
8403 plat_dev = platform_device_register_simple("niu", niu_parent_index,
8404 NULL, 0);
8405 if (!plat_dev)
8406 return NULL;
8407
8408 for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
8409 int err = device_create_file(&plat_dev->dev,
8410 &niu_parent_attributes[i]);
8411 if (err)
8412 goto fail_unregister;
8413 }
8414
8415 p = kzalloc(sizeof(*p), GFP_KERNEL);
8416 if (!p)
8417 goto fail_unregister;
8418
8419 p->index = niu_parent_index++;
8420
8421 plat_dev->dev.platform_data = p;
8422 p->plat_dev = plat_dev;
8423
8424 memcpy(&p->id, id, sizeof(*id));
8425 p->plat_type = ptype;
8426 INIT_LIST_HEAD(&p->list);
8427 atomic_set(&p->refcnt, 0);
8428 list_add(&p->list, &niu_parent_list);
8429 spin_lock_init(&p->lock);
8430
8431 p->rxdma_clock_divider = 7500;
8432
8433 p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
8434 if (p->plat_type == PLAT_TYPE_NIU)
8435 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
8436
8437 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
8438 int index = i - CLASS_CODE_USER_PROG1;
8439
8440 p->tcam_key[index] = TCAM_KEY_TSEL;
8441 p->flow_key[index] = (FLOW_KEY_IPSA |
8442 FLOW_KEY_IPDA |
8443 FLOW_KEY_PROTO |
8444 (FLOW_KEY_L4_BYTE12 <<
8445 FLOW_KEY_L4_0_SHIFT) |
8446 (FLOW_KEY_L4_BYTE12 <<
8447 FLOW_KEY_L4_1_SHIFT));
8448 }
8449
8450 for (i = 0; i < LDN_MAX + 1; i++)
8451 p->ldg_map[i] = LDG_INVALID;
8452
8453 return p;
8454
8455 fail_unregister:
8456 platform_device_unregister(plat_dev);
8457 return NULL;
8458 }
8459
8460 static struct niu_parent * __devinit niu_get_parent(struct niu *np,
8461 union niu_parent_id *id,
8462 u8 ptype)
8463 {
8464 struct niu_parent *p, *tmp;
8465 int port = np->port;
8466
8467 niudbg(PROBE, "niu_get_parent: platform_type[%u] port[%u]\n",
8468 ptype, port);
8469
8470 mutex_lock(&niu_parent_lock);
8471 p = NULL;
8472 list_for_each_entry(tmp, &niu_parent_list, list) {
8473 if (!memcmp(id, &tmp->id, sizeof(*id))) {
8474 p = tmp;
8475 break;
8476 }
8477 }
8478 if (!p)
8479 p = niu_new_parent(np, id, ptype);
8480
8481 if (p) {
8482 char port_name[6];
8483 int err;
8484
8485 sprintf(port_name, "port%d", port);
8486 err = sysfs_create_link(&p->plat_dev->dev.kobj,
8487 &np->device->kobj,
8488 port_name);
8489 if (!err) {
8490 p->ports[port] = np;
8491 atomic_inc(&p->refcnt);
8492 }
8493 }
8494 mutex_unlock(&niu_parent_lock);
8495
8496 return p;
8497 }
8498
8499 static void niu_put_parent(struct niu *np)
8500 {
8501 struct niu_parent *p = np->parent;
8502 u8 port = np->port;
8503 char port_name[6];
8504
8505 BUG_ON(!p || p->ports[port] != np);
8506
8507 niudbg(PROBE, "niu_put_parent: port[%u]\n", port);
8508
8509 sprintf(port_name, "port%d", port);
8510
8511 mutex_lock(&niu_parent_lock);
8512
8513 sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
8514
8515 p->ports[port] = NULL;
8516 np->parent = NULL;
8517
8518 if (atomic_dec_and_test(&p->refcnt)) {
8519 list_del(&p->list);
8520 platform_device_unregister(p->plat_dev);
8521 }
8522
8523 mutex_unlock(&niu_parent_lock);
8524 }
8525
8526 static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
8527 u64 *handle, gfp_t flag)
8528 {
8529 dma_addr_t dh;
8530 void *ret;
8531
8532 ret = dma_alloc_coherent(dev, size, &dh, flag);
8533 if (ret)
8534 *handle = dh;
8535 return ret;
8536 }
8537
8538 static void niu_pci_free_coherent(struct device *dev, size_t size,
8539 void *cpu_addr, u64 handle)
8540 {
8541 dma_free_coherent(dev, size, cpu_addr, handle);
8542 }
8543
8544 static u64 niu_pci_map_page(struct device *dev, struct page *page,
8545 unsigned long offset, size_t size,
8546 enum dma_data_direction direction)
8547 {
8548 return dma_map_page(dev, page, offset, size, direction);
8549 }
8550
8551 static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
8552 size_t size, enum dma_data_direction direction)
8553 {
8554 return dma_unmap_page(dev, dma_address, size, direction);
8555 }
8556
8557 static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
8558 size_t size,
8559 enum dma_data_direction direction)
8560 {
8561 return dma_map_single(dev, cpu_addr, size, direction);
8562 }
8563
8564 static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
8565 size_t size,
8566 enum dma_data_direction direction)
8567 {
8568 dma_unmap_single(dev, dma_address, size, direction);
8569 }
8570
8571 static const struct niu_ops niu_pci_ops = {
8572 .alloc_coherent = niu_pci_alloc_coherent,
8573 .free_coherent = niu_pci_free_coherent,
8574 .map_page = niu_pci_map_page,
8575 .unmap_page = niu_pci_unmap_page,
8576 .map_single = niu_pci_map_single,
8577 .unmap_single = niu_pci_unmap_single,
8578 };
8579
8580 static void __devinit niu_driver_version(void)
8581 {
8582 static int niu_version_printed;
8583
8584 if (niu_version_printed++ == 0)
8585 pr_info("%s", version);
8586 }
8587
8588 static struct net_device * __devinit niu_alloc_and_init(
8589 struct device *gen_dev, struct pci_dev *pdev,
8590 struct of_device *op, const struct niu_ops *ops,
8591 u8 port)
8592 {
8593 struct net_device *dev;
8594 struct niu *np;
8595
8596 dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
8597 if (!dev) {
8598 dev_err(gen_dev, PFX "Etherdev alloc failed, aborting.\n");
8599 return NULL;
8600 }
8601
8602 SET_NETDEV_DEV(dev, gen_dev);
8603
8604 np = netdev_priv(dev);
8605 np->dev = dev;
8606 np->pdev = pdev;
8607 np->op = op;
8608 np->device = gen_dev;
8609 np->ops = ops;
8610
8611 np->msg_enable = niu_debug;
8612
8613 spin_lock_init(&np->lock);
8614 INIT_WORK(&np->reset_task, niu_reset_task);
8615
8616 np->port = port;
8617
8618 return dev;
8619 }
8620
8621 static void __devinit niu_assign_netdev_ops(struct net_device *dev)
8622 {
8623 dev->open = niu_open;
8624 dev->stop = niu_close;
8625 dev->get_stats = niu_get_stats;
8626 dev->set_multicast_list = niu_set_rx_mode;
8627 dev->set_mac_address = niu_set_mac_addr;
8628 dev->do_ioctl = niu_ioctl;
8629 dev->tx_timeout = niu_tx_timeout;
8630 dev->hard_start_xmit = niu_start_xmit;
8631 dev->ethtool_ops = &niu_ethtool_ops;
8632 dev->watchdog_timeo = NIU_TX_TIMEOUT;
8633 dev->change_mtu = niu_change_mtu;
8634 }
8635
8636 static void __devinit niu_device_announce(struct niu *np)
8637 {
8638 struct net_device *dev = np->dev;
8639
8640 pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
8641
8642 if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
8643 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
8644 dev->name,
8645 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
8646 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
8647 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
8648 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
8649 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
8650 np->vpd.phy_type);
8651 } else {
8652 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
8653 dev->name,
8654 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
8655 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
8656 (np->flags & NIU_FLAGS_FIBER ? "FIBER" : "COPPER"),
8657 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
8658 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
8659 np->vpd.phy_type);
8660 }
8661 }
8662
8663 static int __devinit niu_pci_init_one(struct pci_dev *pdev,
8664 const struct pci_device_id *ent)
8665 {
8666 union niu_parent_id parent_id;
8667 struct net_device *dev;
8668 struct niu *np;
8669 int err, pos;
8670 u64 dma_mask;
8671 u16 val16;
8672
8673 niu_driver_version();
8674
8675 err = pci_enable_device(pdev);
8676 if (err) {
8677 dev_err(&pdev->dev, PFX "Cannot enable PCI device, "
8678 "aborting.\n");
8679 return err;
8680 }
8681
8682 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
8683 !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
8684 dev_err(&pdev->dev, PFX "Cannot find proper PCI device "
8685 "base addresses, aborting.\n");
8686 err = -ENODEV;
8687 goto err_out_disable_pdev;
8688 }
8689
8690 err = pci_request_regions(pdev, DRV_MODULE_NAME);
8691 if (err) {
8692 dev_err(&pdev->dev, PFX "Cannot obtain PCI resources, "
8693 "aborting.\n");
8694 goto err_out_disable_pdev;
8695 }
8696
8697 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
8698 if (pos <= 0) {
8699 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
8700 "aborting.\n");
8701 goto err_out_free_res;
8702 }
8703
8704 dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
8705 &niu_pci_ops, PCI_FUNC(pdev->devfn));
8706 if (!dev) {
8707 err = -ENOMEM;
8708 goto err_out_free_res;
8709 }
8710 np = netdev_priv(dev);
8711
8712 memset(&parent_id, 0, sizeof(parent_id));
8713 parent_id.pci.domain = pci_domain_nr(pdev->bus);
8714 parent_id.pci.bus = pdev->bus->number;
8715 parent_id.pci.device = PCI_SLOT(pdev->devfn);
8716
8717 np->parent = niu_get_parent(np, &parent_id,
8718 PLAT_TYPE_ATLAS);
8719 if (!np->parent) {
8720 err = -ENOMEM;
8721 goto err_out_free_dev;
8722 }
8723
8724 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
8725 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
8726 val16 |= (PCI_EXP_DEVCTL_CERE |
8727 PCI_EXP_DEVCTL_NFERE |
8728 PCI_EXP_DEVCTL_FERE |
8729 PCI_EXP_DEVCTL_URRE |
8730 PCI_EXP_DEVCTL_RELAX_EN);
8731 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
8732
8733 dma_mask = DMA_44BIT_MASK;
8734 err = pci_set_dma_mask(pdev, dma_mask);
8735 if (!err) {
8736 dev->features |= NETIF_F_HIGHDMA;
8737 err = pci_set_consistent_dma_mask(pdev, dma_mask);
8738 if (err) {
8739 dev_err(&pdev->dev, PFX "Unable to obtain 44 bit "
8740 "DMA for consistent allocations, "
8741 "aborting.\n");
8742 goto err_out_release_parent;
8743 }
8744 }
8745 if (err || dma_mask == DMA_32BIT_MASK) {
8746 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
8747 if (err) {
8748 dev_err(&pdev->dev, PFX "No usable DMA configuration, "
8749 "aborting.\n");
8750 goto err_out_release_parent;
8751 }
8752 }
8753
8754 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
8755
8756 np->regs = pci_ioremap_bar(pdev, 0);
8757 if (!np->regs) {
8758 dev_err(&pdev->dev, PFX "Cannot map device registers, "
8759 "aborting.\n");
8760 err = -ENOMEM;
8761 goto err_out_release_parent;
8762 }
8763
8764 pci_set_master(pdev);
8765 pci_save_state(pdev);
8766
8767 dev->irq = pdev->irq;
8768
8769 niu_assign_netdev_ops(dev);
8770
8771 err = niu_get_invariants(np);
8772 if (err) {
8773 if (err != -ENODEV)
8774 dev_err(&pdev->dev, PFX "Problem fetching invariants "
8775 "of chip, aborting.\n");
8776 goto err_out_iounmap;
8777 }
8778
8779 err = register_netdev(dev);
8780 if (err) {
8781 dev_err(&pdev->dev, PFX "Cannot register net device, "
8782 "aborting.\n");
8783 goto err_out_iounmap;
8784 }
8785
8786 pci_set_drvdata(pdev, dev);
8787
8788 niu_device_announce(np);
8789
8790 return 0;
8791
8792 err_out_iounmap:
8793 if (np->regs) {
8794 iounmap(np->regs);
8795 np->regs = NULL;
8796 }
8797
8798 err_out_release_parent:
8799 niu_put_parent(np);
8800
8801 err_out_free_dev:
8802 free_netdev(dev);
8803
8804 err_out_free_res:
8805 pci_release_regions(pdev);
8806
8807 err_out_disable_pdev:
8808 pci_disable_device(pdev);
8809 pci_set_drvdata(pdev, NULL);
8810
8811 return err;
8812 }
8813
8814 static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
8815 {
8816 struct net_device *dev = pci_get_drvdata(pdev);
8817
8818 if (dev) {
8819 struct niu *np = netdev_priv(dev);
8820
8821 unregister_netdev(dev);
8822 if (np->regs) {
8823 iounmap(np->regs);
8824 np->regs = NULL;
8825 }
8826
8827 niu_ldg_free(np);
8828
8829 niu_put_parent(np);
8830
8831 free_netdev(dev);
8832 pci_release_regions(pdev);
8833 pci_disable_device(pdev);
8834 pci_set_drvdata(pdev, NULL);
8835 }
8836 }
8837
8838 static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
8839 {
8840 struct net_device *dev = pci_get_drvdata(pdev);
8841 struct niu *np = netdev_priv(dev);
8842 unsigned long flags;
8843
8844 if (!netif_running(dev))
8845 return 0;
8846
8847 flush_scheduled_work();
8848 niu_netif_stop(np);
8849
8850 del_timer_sync(&np->timer);
8851
8852 spin_lock_irqsave(&np->lock, flags);
8853 niu_enable_interrupts(np, 0);
8854 spin_unlock_irqrestore(&np->lock, flags);
8855
8856 netif_device_detach(dev);
8857
8858 spin_lock_irqsave(&np->lock, flags);
8859 niu_stop_hw(np);
8860 spin_unlock_irqrestore(&np->lock, flags);
8861
8862 pci_save_state(pdev);
8863
8864 return 0;
8865 }
8866
8867 static int niu_resume(struct pci_dev *pdev)
8868 {
8869 struct net_device *dev = pci_get_drvdata(pdev);
8870 struct niu *np = netdev_priv(dev);
8871 unsigned long flags;
8872 int err;
8873
8874 if (!netif_running(dev))
8875 return 0;
8876
8877 pci_restore_state(pdev);
8878
8879 netif_device_attach(dev);
8880
8881 spin_lock_irqsave(&np->lock, flags);
8882
8883 err = niu_init_hw(np);
8884 if (!err) {
8885 np->timer.expires = jiffies + HZ;
8886 add_timer(&np->timer);
8887 niu_netif_start(np);
8888 }
8889
8890 spin_unlock_irqrestore(&np->lock, flags);
8891
8892 return err;
8893 }
8894
8895 static struct pci_driver niu_pci_driver = {
8896 .name = DRV_MODULE_NAME,
8897 .id_table = niu_pci_tbl,
8898 .probe = niu_pci_init_one,
8899 .remove = __devexit_p(niu_pci_remove_one),
8900 .suspend = niu_suspend,
8901 .resume = niu_resume,
8902 };
8903
8904 #ifdef CONFIG_SPARC64
8905 static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
8906 u64 *dma_addr, gfp_t flag)
8907 {
8908 unsigned long order = get_order(size);
8909 unsigned long page = __get_free_pages(flag, order);
8910
8911 if (page == 0UL)
8912 return NULL;
8913 memset((char *)page, 0, PAGE_SIZE << order);
8914 *dma_addr = __pa(page);
8915
8916 return (void *) page;
8917 }
8918
8919 static void niu_phys_free_coherent(struct device *dev, size_t size,
8920 void *cpu_addr, u64 handle)
8921 {
8922 unsigned long order = get_order(size);
8923
8924 free_pages((unsigned long) cpu_addr, order);
8925 }
8926
8927 static u64 niu_phys_map_page(struct device *dev, struct page *page,
8928 unsigned long offset, size_t size,
8929 enum dma_data_direction direction)
8930 {
8931 return page_to_phys(page) + offset;
8932 }
8933
8934 static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
8935 size_t size, enum dma_data_direction direction)
8936 {
8937 /* Nothing to do. */
8938 }
8939
8940 static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
8941 size_t size,
8942 enum dma_data_direction direction)
8943 {
8944 return __pa(cpu_addr);
8945 }
8946
8947 static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
8948 size_t size,
8949 enum dma_data_direction direction)
8950 {
8951 /* Nothing to do. */
8952 }
8953
8954 static const struct niu_ops niu_phys_ops = {
8955 .alloc_coherent = niu_phys_alloc_coherent,
8956 .free_coherent = niu_phys_free_coherent,
8957 .map_page = niu_phys_map_page,
8958 .unmap_page = niu_phys_unmap_page,
8959 .map_single = niu_phys_map_single,
8960 .unmap_single = niu_phys_unmap_single,
8961 };
8962
8963 static unsigned long res_size(struct resource *r)
8964 {
8965 return r->end - r->start + 1UL;
8966 }
8967
8968 static int __devinit niu_of_probe(struct of_device *op,
8969 const struct of_device_id *match)
8970 {
8971 union niu_parent_id parent_id;
8972 struct net_device *dev;
8973 struct niu *np;
8974 const u32 *reg;
8975 int err;
8976
8977 niu_driver_version();
8978
8979 reg = of_get_property(op->node, "reg", NULL);
8980 if (!reg) {
8981 dev_err(&op->dev, PFX "%s: No 'reg' property, aborting.\n",
8982 op->node->full_name);
8983 return -ENODEV;
8984 }
8985
8986 dev = niu_alloc_and_init(&op->dev, NULL, op,
8987 &niu_phys_ops, reg[0] & 0x1);
8988 if (!dev) {
8989 err = -ENOMEM;
8990 goto err_out;
8991 }
8992 np = netdev_priv(dev);
8993
8994 memset(&parent_id, 0, sizeof(parent_id));
8995 parent_id.of = of_get_parent(op->node);
8996
8997 np->parent = niu_get_parent(np, &parent_id,
8998 PLAT_TYPE_NIU);
8999 if (!np->parent) {
9000 err = -ENOMEM;
9001 goto err_out_free_dev;
9002 }
9003
9004 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
9005
9006 np->regs = of_ioremap(&op->resource[1], 0,
9007 res_size(&op->resource[1]),
9008 "niu regs");
9009 if (!np->regs) {
9010 dev_err(&op->dev, PFX "Cannot map device registers, "
9011 "aborting.\n");
9012 err = -ENOMEM;
9013 goto err_out_release_parent;
9014 }
9015
9016 np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
9017 res_size(&op->resource[2]),
9018 "niu vregs-1");
9019 if (!np->vir_regs_1) {
9020 dev_err(&op->dev, PFX "Cannot map device vir registers 1, "
9021 "aborting.\n");
9022 err = -ENOMEM;
9023 goto err_out_iounmap;
9024 }
9025
9026 np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
9027 res_size(&op->resource[3]),
9028 "niu vregs-2");
9029 if (!np->vir_regs_2) {
9030 dev_err(&op->dev, PFX "Cannot map device vir registers 2, "
9031 "aborting.\n");
9032 err = -ENOMEM;
9033 goto err_out_iounmap;
9034 }
9035
9036 niu_assign_netdev_ops(dev);
9037
9038 err = niu_get_invariants(np);
9039 if (err) {
9040 if (err != -ENODEV)
9041 dev_err(&op->dev, PFX "Problem fetching invariants "
9042 "of chip, aborting.\n");
9043 goto err_out_iounmap;
9044 }
9045
9046 err = register_netdev(dev);
9047 if (err) {
9048 dev_err(&op->dev, PFX "Cannot register net device, "
9049 "aborting.\n");
9050 goto err_out_iounmap;
9051 }
9052
9053 dev_set_drvdata(&op->dev, dev);
9054
9055 niu_device_announce(np);
9056
9057 return 0;
9058
9059 err_out_iounmap:
9060 if (np->vir_regs_1) {
9061 of_iounmap(&op->resource[2], np->vir_regs_1,
9062 res_size(&op->resource[2]));
9063 np->vir_regs_1 = NULL;
9064 }
9065
9066 if (np->vir_regs_2) {
9067 of_iounmap(&op->resource[3], np->vir_regs_2,
9068 res_size(&op->resource[3]));
9069 np->vir_regs_2 = NULL;
9070 }
9071
9072 if (np->regs) {
9073 of_iounmap(&op->resource[1], np->regs,
9074 res_size(&op->resource[1]));
9075 np->regs = NULL;
9076 }
9077
9078 err_out_release_parent:
9079 niu_put_parent(np);
9080
9081 err_out_free_dev:
9082 free_netdev(dev);
9083
9084 err_out:
9085 return err;
9086 }
9087
9088 static int __devexit niu_of_remove(struct of_device *op)
9089 {
9090 struct net_device *dev = dev_get_drvdata(&op->dev);
9091
9092 if (dev) {
9093 struct niu *np = netdev_priv(dev);
9094
9095 unregister_netdev(dev);
9096
9097 if (np->vir_regs_1) {
9098 of_iounmap(&op->resource[2], np->vir_regs_1,
9099 res_size(&op->resource[2]));
9100 np->vir_regs_1 = NULL;
9101 }
9102
9103 if (np->vir_regs_2) {
9104 of_iounmap(&op->resource[3], np->vir_regs_2,
9105 res_size(&op->resource[3]));
9106 np->vir_regs_2 = NULL;
9107 }
9108
9109 if (np->regs) {
9110 of_iounmap(&op->resource[1], np->regs,
9111 res_size(&op->resource[1]));
9112 np->regs = NULL;
9113 }
9114
9115 niu_ldg_free(np);
9116
9117 niu_put_parent(np);
9118
9119 free_netdev(dev);
9120 dev_set_drvdata(&op->dev, NULL);
9121 }
9122 return 0;
9123 }
9124
9125 static const struct of_device_id niu_match[] = {
9126 {
9127 .name = "network",
9128 .compatible = "SUNW,niusl",
9129 },
9130 {},
9131 };
9132 MODULE_DEVICE_TABLE(of, niu_match);
9133
9134 static struct of_platform_driver niu_of_driver = {
9135 .name = "niu",
9136 .match_table = niu_match,
9137 .probe = niu_of_probe,
9138 .remove = __devexit_p(niu_of_remove),
9139 };
9140
9141 #endif /* CONFIG_SPARC64 */
9142
9143 static int __init niu_init(void)
9144 {
9145 int err = 0;
9146
9147 BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
9148
9149 niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
9150
9151 #ifdef CONFIG_SPARC64
9152 err = of_register_driver(&niu_of_driver, &of_bus_type);
9153 #endif
9154
9155 if (!err) {
9156 err = pci_register_driver(&niu_pci_driver);
9157 #ifdef CONFIG_SPARC64
9158 if (err)
9159 of_unregister_driver(&niu_of_driver);
9160 #endif
9161 }
9162
9163 return err;
9164 }
9165
9166 static void __exit niu_exit(void)
9167 {
9168 pci_unregister_driver(&niu_pci_driver);
9169 #ifdef CONFIG_SPARC64
9170 of_unregister_driver(&niu_of_driver);
9171 #endif
9172 }
9173
9174 module_init(niu_init);
9175 module_exit(niu_exit);
AMDTP streaming driver for the Linux FireWire stack (Juju)