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ixgbe: Harden the 82599 multispeed fiber autotry mechanism
[firewire-audio.git] / drivers / net / ixgbe / ixgbe_82599.c
blob84b83f7b473feec2292c54e1c0ab9d73522851a7
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe.h"
33 #include "ixgbe_phy.h"
34
35 #define IXGBE_82599_MAX_TX_QUEUES 128
36 #define IXGBE_82599_MAX_RX_QUEUES 128
37 #define IXGBE_82599_RAR_ENTRIES 128
38 #define IXGBE_82599_MC_TBL_SIZE 128
39 #define IXGBE_82599_VFT_TBL_SIZE 128
40
41 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
42 ixgbe_link_speed *speed,
43 bool *autoneg);
44 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw);
45 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw);
46 s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
47 ixgbe_link_speed speed, bool autoneg,
48 bool autoneg_wait_to_complete);
49 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw);
50 s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
51 ixgbe_link_speed *speed,
52 bool *link_up, bool link_up_wait_to_complete);
53 s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
54 ixgbe_link_speed speed,
55 bool autoneg,
56 bool autoneg_wait_to_complete);
57 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
58 ixgbe_link_speed *speed,
59 bool *autoneg);
60 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw);
61 static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
62 ixgbe_link_speed speed,
63 bool autoneg,
64 bool autoneg_wait_to_complete);
65 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw);
66 s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
67 s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
68 s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan,
69 u32 vind, bool vlan_on);
70 s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw);
71 s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw);
72 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);
73 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);
74 s32 ixgbe_start_hw_rev_0_82599(struct ixgbe_hw *hw);
75 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw);
76 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw);
77 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
78
79 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
80 {
81 struct ixgbe_mac_info *mac = &hw->mac;
82 if (hw->phy.multispeed_fiber) {
83 /* Set up dual speed SFP+ support */
84 mac->ops.setup_link =
85 &ixgbe_setup_mac_link_multispeed_fiber;
86 mac->ops.setup_link_speed =
87 &ixgbe_setup_mac_link_speed_multispeed_fiber;
88 } else {
89 mac->ops.setup_link =
90 &ixgbe_setup_mac_link_82599;
91 mac->ops.setup_link_speed =
92 &ixgbe_setup_mac_link_speed_82599;
93 }
94 }
95
96 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
97 {
98 s32 ret_val = 0;
99 u16 list_offset, data_offset, data_value;
100
101 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
102 ixgbe_init_mac_link_ops_82599(hw);
103
104 hw->phy.ops.reset = NULL;
105
106 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
107 &data_offset);
108
109 if (ret_val != 0)
110 goto setup_sfp_out;
111
112 /* PHY config will finish before releasing the semaphore */
113 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
114 if (ret_val != 0) {
115 ret_val = IXGBE_ERR_SWFW_SYNC;
116 goto setup_sfp_out;
117 }
118
119 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
120 while (data_value != 0xffff) {
121 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
122 IXGBE_WRITE_FLUSH(hw);
123 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
124 }
125 /* Now restart DSP by setting Restart_AN */
126 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
127 (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART));
128
129 /* Release the semaphore */
130 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
131 /* Delay obtaining semaphore again to allow FW access */
132 msleep(hw->eeprom.semaphore_delay);
133 }
134
135 setup_sfp_out:
136 return ret_val;
137 }
138
139 /**
140 * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
141 * @hw: pointer to hardware structure
142 *
143 * Read PCIe configuration space, and get the MSI-X vector count from
144 * the capabilities table.
145 **/
146 u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
147 {
148 struct ixgbe_adapter *adapter = hw->back;
149 u16 msix_count;
150 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
151 &msix_count);
152 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
153
154 /* MSI-X count is zero-based in HW, so increment to give proper value */
155 msix_count++;
156
157 return msix_count;
158 }
159
160 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
161 {
162 struct ixgbe_mac_info *mac = &hw->mac;
163
164 ixgbe_init_mac_link_ops_82599(hw);
165
166 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
167 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
168 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
169 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
170 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
171 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
172
173 return 0;
174 }
175
176 /**
177 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
178 * @hw: pointer to hardware structure
179 *
180 * Initialize any function pointers that were not able to be
181 * set during get_invariants because the PHY/SFP type was
182 * not known. Perform the SFP init if necessary.
183 *
184 **/
185 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
186 {
187 struct ixgbe_mac_info *mac = &hw->mac;
188 struct ixgbe_phy_info *phy = &hw->phy;
189 s32 ret_val = 0;
190
191 /* Identify the PHY or SFP module */
192 ret_val = phy->ops.identify(hw);
193
194 /* Setup function pointers based on detected SFP module and speeds */
195 ixgbe_init_mac_link_ops_82599(hw);
196
197 /* If copper media, overwrite with copper function pointers */
198 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
199 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
200 mac->ops.setup_link_speed =
201 &ixgbe_setup_copper_link_speed_82599;
202 mac->ops.get_link_capabilities =
203 &ixgbe_get_copper_link_capabilities_82599;
204 }
205
206 /* Set necessary function pointers based on phy type */
207 switch (hw->phy.type) {
208 case ixgbe_phy_tn:
209 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
210 phy->ops.get_firmware_version =
211 &ixgbe_get_phy_firmware_version_tnx;
212 break;
213 default:
214 break;
215 }
216
217 return ret_val;
218 }
219
220 /**
221 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
222 * @hw: pointer to hardware structure
223 * @speed: pointer to link speed
224 * @negotiation: true when autoneg or autotry is enabled
225 *
226 * Determines the link capabilities by reading the AUTOC register.
227 **/
228 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
229 ixgbe_link_speed *speed,
230 bool *negotiation)
231 {
232 s32 status = 0;
233 u32 autoc = 0;
234
235 /*
236 * Determine link capabilities based on the stored value of AUTOC,
237 * which represents EEPROM defaults. If AUTOC value has not been
238 * stored, use the current register value.
239 */
240 if (hw->mac.orig_link_settings_stored)
241 autoc = hw->mac.orig_autoc;
242 else
243 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
244
245 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
246 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
247 *speed = IXGBE_LINK_SPEED_1GB_FULL;
248 *negotiation = false;
249 break;
250
251 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
252 *speed = IXGBE_LINK_SPEED_10GB_FULL;
253 *negotiation = false;
254 break;
255
256 case IXGBE_AUTOC_LMS_1G_AN:
257 *speed = IXGBE_LINK_SPEED_1GB_FULL;
258 *negotiation = true;
259 break;
260
261 case IXGBE_AUTOC_LMS_10G_SERIAL:
262 *speed = IXGBE_LINK_SPEED_10GB_FULL;
263 *negotiation = false;
264 break;
265
266 case IXGBE_AUTOC_LMS_KX4_KX_KR:
267 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
268 *speed = IXGBE_LINK_SPEED_UNKNOWN;
269 if (autoc & IXGBE_AUTOC_KR_SUPP)
270 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
271 if (autoc & IXGBE_AUTOC_KX4_SUPP)
272 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
273 if (autoc & IXGBE_AUTOC_KX_SUPP)
274 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
275 *negotiation = true;
276 break;
277
278 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
279 *speed = IXGBE_LINK_SPEED_100_FULL;
280 if (autoc & IXGBE_AUTOC_KR_SUPP)
281 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
282 if (autoc & IXGBE_AUTOC_KX4_SUPP)
283 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
284 if (autoc & IXGBE_AUTOC_KX_SUPP)
285 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
286 *negotiation = true;
287 break;
288
289 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
290 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
291 *negotiation = false;
292 break;
293
294 default:
295 status = IXGBE_ERR_LINK_SETUP;
296 goto out;
297 break;
298 }
299
300 if (hw->phy.multispeed_fiber) {
301 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
302 IXGBE_LINK_SPEED_1GB_FULL;
303 *negotiation = true;
304 }
305
306 out:
307 return status;
308 }
309
310 /**
311 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
312 * @hw: pointer to hardware structure
313 * @speed: pointer to link speed
314 * @autoneg: boolean auto-negotiation value
315 *
316 * Determines the link capabilities by reading the AUTOC register.
317 **/
318 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
319 ixgbe_link_speed *speed,
320 bool *autoneg)
321 {
322 s32 status = IXGBE_ERR_LINK_SETUP;
323 u16 speed_ability;
324
325 *speed = 0;
326 *autoneg = true;
327
328 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
329 &speed_ability);
330
331 if (status == 0) {
332 if (speed_ability & MDIO_SPEED_10G)
333 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
334 if (speed_ability & MDIO_PMA_SPEED_1000)
335 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
336 }
337
338 return status;
339 }
340
341 /**
342 * ixgbe_get_media_type_82599 - Get media type
343 * @hw: pointer to hardware structure
344 *
345 * Returns the media type (fiber, copper, backplane)
346 **/
347 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
348 {
349 enum ixgbe_media_type media_type;
350
351 /* Detect if there is a copper PHY attached. */
352 if (hw->phy.type == ixgbe_phy_cu_unknown ||
353 hw->phy.type == ixgbe_phy_tn) {
354 media_type = ixgbe_media_type_copper;
355 goto out;
356 }
357
358 switch (hw->device_id) {
359 case IXGBE_DEV_ID_82599_KX4:
360 case IXGBE_DEV_ID_82599_XAUI_LOM:
361 /* Default device ID is mezzanine card KX/KX4 */
362 media_type = ixgbe_media_type_backplane;
363 break;
364 case IXGBE_DEV_ID_82599_SFP:
365 media_type = ixgbe_media_type_fiber;
366 break;
367 default:
368 media_type = ixgbe_media_type_unknown;
369 break;
370 }
371 out:
372 return media_type;
373 }
374
375 /**
376 * ixgbe_setup_mac_link_82599 - Setup MAC link settings
377 * @hw: pointer to hardware structure
378 *
379 * Configures link settings based on values in the ixgbe_hw struct.
380 * Restarts the link. Performs autonegotiation if needed.
381 **/
382 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw)
383 {
384 u32 autoc_reg;
385 u32 links_reg;
386 u32 i;
387 s32 status = 0;
388
389 /* Restart link */
390 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
391 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
392 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
393
394 /* Only poll for autoneg to complete if specified to do so */
395 if (hw->phy.autoneg_wait_to_complete) {
396 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
397 IXGBE_AUTOC_LMS_KX4_KX_KR ||
398 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
399 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
400 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
401 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
402 links_reg = 0; /* Just in case Autoneg time = 0 */
403 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
404 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
405 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
406 break;
407 msleep(100);
408 }
409 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
410 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
411 hw_dbg(hw, "Autoneg did not complete.\n");
412 }
413 }
414 }
415
416 /* Set up flow control */
417 status = ixgbe_setup_fc_generic(hw, 0);
418
419 /* Add delay to filter out noises during initial link setup */
420 msleep(50);
421
422 return status;
423 }
424
425 /**
426 * ixgbe_setup_mac_link_multispeed_fiber - Setup MAC link settings
427 * @hw: pointer to hardware structure
428 *
429 * Configures link settings based on values in the ixgbe_hw struct.
430 * Restarts the link for multi-speed fiber at 1G speed, if link
431 * fails at 10G.
432 * Performs autonegotiation if needed.
433 **/
434 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw)
435 {
436 s32 status = 0;
437 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_82599_AUTONEG;
438 status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw, link_speed,
439 true, true);
440 return status;
441 }
442
443 /**
444 * ixgbe_setup_mac_link_speed_multispeed_fiber - Set MAC link speed
445 * @hw: pointer to hardware structure
446 * @speed: new link speed
447 * @autoneg: true if autonegotiation enabled
448 * @autoneg_wait_to_complete: true when waiting for completion is needed
449 *
450 * Set the link speed in the AUTOC register and restarts link.
451 **/
452 s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
453 ixgbe_link_speed speed,
454 bool autoneg,
455 bool autoneg_wait_to_complete)
456 {
457 s32 status = 0;
458 ixgbe_link_speed phy_link_speed;
459 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
460 u32 speedcnt = 0;
461 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
462 bool link_up = false;
463 bool negotiation;
464 int i;
465
466 /* Mask off requested but non-supported speeds */
467 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
468 speed &= phy_link_speed;
469
470 /*
471 * When the driver changes the link speeds that it can support,
472 * it sets autotry_restart to true to indicate that we need to
473 * initiate a new autotry session with the link partner. To do
474 * so, we set the speed then disable and re-enable the tx laser, to
475 * alert the link partner that it also needs to restart autotry on its
476 * end. This is consistent with true clause 37 autoneg, which also
477 * involves a loss of signal.
478 */
479
480 /*
481 * Try each speed one by one, highest priority first. We do this in
482 * software because 10gb fiber doesn't support speed autonegotiation.
483 */
484 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
485 speedcnt++;
486 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
487
488 /* If we already have link at this speed, just jump out */
489 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
490
491 if ((phy_link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
492 goto out;
493
494 /* Set the module link speed */
495 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
496 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
497
498 /* Allow module to change analog characteristics (1G->10G) */
499 msleep(40);
500
501 status = ixgbe_setup_mac_link_speed_82599(hw,
502 IXGBE_LINK_SPEED_10GB_FULL,
503 autoneg,
504 autoneg_wait_to_complete);
505 if (status != 0)
506 goto out;
507
508 /* Flap the tx laser if it has not already been done */
509 if (hw->mac.autotry_restart) {
510 /* Disable tx laser; allow 100us to go dark per spec */
511 esdp_reg |= IXGBE_ESDP_SDP3;
512 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
513 udelay(100);
514
515 /* Enable tx laser; allow 2ms to light up per spec */
516 esdp_reg &= ~IXGBE_ESDP_SDP3;
517 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
518 msleep(2);
519
520 hw->mac.autotry_restart = false;
521 }
522
523 /* The controller may take up to 500ms at 10g to acquire link */
524 for (i = 0; i < 5; i++) {
525 /* Wait for the link partner to also set speed */
526 msleep(100);
527
528 /* If we have link, just jump out */
529 hw->mac.ops.check_link(hw, &phy_link_speed,
530 &link_up, false);
531 if (link_up)
532 goto out;
533 }
534 }
535
536 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
537 speedcnt++;
538 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
539 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
540
541 /* If we already have link at this speed, just jump out */
542 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
543
544 if ((phy_link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
545 goto out;
546
547 /* Set the module link speed */
548 esdp_reg &= ~IXGBE_ESDP_SDP5;
549 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
550 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
551
552 /* Allow module to change analog characteristics (10G->1G) */
553 msleep(40);
554
555 status = ixgbe_setup_mac_link_speed_82599(hw,
556 IXGBE_LINK_SPEED_1GB_FULL,
557 autoneg,
558 autoneg_wait_to_complete);
559 if (status != 0)
560 goto out;
561
562 /* Flap the tx laser if it has not already been done */
563 if (hw->mac.autotry_restart) {
564 /* Disable tx laser; allow 100us to go dark per spec */
565 esdp_reg |= IXGBE_ESDP_SDP3;
566 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
567 udelay(100);
568
569 /* Enable tx laser; allow 2ms to light up per spec */
570 esdp_reg &= ~IXGBE_ESDP_SDP3;
571 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
572 msleep(2);
573
574 hw->mac.autotry_restart = false;
575 }
576
577 /* Wait for the link partner to also set speed */
578 msleep(100);
579
580 /* If we have link, just jump out */
581 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
582 if (link_up)
583 goto out;
584 }
585
586 /*
587 * We didn't get link. Configure back to the highest speed we tried,
588 * (if there was more than one). We call ourselves back with just the
589 * single highest speed that the user requested.
590 */
591 if (speedcnt > 1)
592 status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw,
593 highest_link_speed,
594 autoneg,
595 autoneg_wait_to_complete);
596
597 out:
598 return status;
599 }
600
601 /**
602 * ixgbe_check_mac_link_82599 - Determine link and speed status
603 * @hw: pointer to hardware structure
604 * @speed: pointer to link speed
605 * @link_up: true when link is up
606 * @link_up_wait_to_complete: bool used to wait for link up or not
607 *
608 * Reads the links register to determine if link is up and the current speed
609 **/
610 s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
611 bool *link_up, bool link_up_wait_to_complete)
612 {
613 u32 links_reg;
614 u32 i;
615
616 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
617 if (link_up_wait_to_complete) {
618 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
619 if (links_reg & IXGBE_LINKS_UP) {
620 *link_up = true;
621 break;
622 } else {
623 *link_up = false;
624 }
625 msleep(100);
626 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
627 }
628 } else {
629 if (links_reg & IXGBE_LINKS_UP)
630 *link_up = true;
631 else
632 *link_up = false;
633 }
634
635 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
636 IXGBE_LINKS_SPEED_10G_82599)
637 *speed = IXGBE_LINK_SPEED_10GB_FULL;
638 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
639 IXGBE_LINKS_SPEED_1G_82599)
640 *speed = IXGBE_LINK_SPEED_1GB_FULL;
641 else
642 *speed = IXGBE_LINK_SPEED_100_FULL;
643
644
645 return 0;
646 }
647
648 /**
649 * ixgbe_setup_mac_link_speed_82599 - Set MAC link speed
650 * @hw: pointer to hardware structure
651 * @speed: new link speed
652 * @autoneg: true if autonegotiation enabled
653 * @autoneg_wait_to_complete: true when waiting for completion is needed
654 *
655 * Set the link speed in the AUTOC register and restarts link.
656 **/
657 s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
658 ixgbe_link_speed speed, bool autoneg,
659 bool autoneg_wait_to_complete)
660 {
661 s32 status = 0;
662 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
663 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
664 u32 start_autoc = autoc;
665 u32 orig_autoc = 0;
666 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
667 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
668 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
669 u32 links_reg;
670 u32 i;
671 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
672
673 /* Check to see if speed passed in is supported. */
674 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
675 speed &= link_capabilities;
676
677 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
678 status = IXGBE_ERR_LINK_SETUP;
679 goto out;
680 }
681
682 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
683 if (hw->mac.orig_link_settings_stored)
684 orig_autoc = hw->mac.orig_autoc;
685 else
686 orig_autoc = autoc;
687
688
689 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
690 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
691 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
692 /* Set KX4/KX/KR support according to speed requested */
693 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
694 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
695 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
696 autoc |= IXGBE_AUTOC_KX4_SUPP;
697 if (orig_autoc & IXGBE_AUTOC_KR_SUPP)
698 autoc |= IXGBE_AUTOC_KR_SUPP;
699 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
700 autoc |= IXGBE_AUTOC_KX_SUPP;
701 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
702 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
703 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
704 /* Switch from 1G SFI to 10G SFI if requested */
705 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
706 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
707 autoc &= ~IXGBE_AUTOC_LMS_MASK;
708 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
709 }
710 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
711 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
712 /* Switch from 10G SFI to 1G SFI if requested */
713 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
714 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
715 autoc &= ~IXGBE_AUTOC_LMS_MASK;
716 if (autoneg)
717 autoc |= IXGBE_AUTOC_LMS_1G_AN;
718 else
719 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
720 }
721 }
722
723 if (autoc != start_autoc) {
724 /* Restart link */
725 autoc |= IXGBE_AUTOC_AN_RESTART;
726 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
727
728 /* Only poll for autoneg to complete if specified to do so */
729 if (autoneg_wait_to_complete) {
730 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
731 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
732 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
733 links_reg = 0; /*Just in case Autoneg time=0*/
734 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
735 links_reg =
736 IXGBE_READ_REG(hw, IXGBE_LINKS);
737 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
738 break;
739 msleep(100);
740 }
741 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
742 status =
743 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
744 hw_dbg(hw, "Autoneg did not "
745 "complete.\n");
746 }
747 }
748 }
749
750 /* Set up flow control */
751 status = ixgbe_setup_fc_generic(hw, 0);
752
753 /* Add delay to filter out noises during initial link setup */
754 msleep(50);
755 }
756
757 out:
758 return status;
759 }
760
761 /**
762 * ixgbe_setup_copper_link_82599 - Setup copper link settings
763 * @hw: pointer to hardware structure
764 *
765 * Restarts the link on PHY and then MAC. Performs autonegotiation if needed.
766 **/
767 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw)
768 {
769 s32 status;
770
771 /* Restart autonegotiation on PHY */
772 status = hw->phy.ops.setup_link(hw);
773
774 /* Set up MAC */
775 ixgbe_setup_mac_link_82599(hw);
776
777 return status;
778 }
779
780 /**
781 * ixgbe_setup_copper_link_speed_82599 - Set the PHY autoneg advertised field
782 * @hw: pointer to hardware structure
783 * @speed: new link speed
784 * @autoneg: true if autonegotiation enabled
785 * @autoneg_wait_to_complete: true if waiting is needed to complete
786 *
787 * Restarts link on PHY and MAC based on settings passed in.
788 **/
789 static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
790 ixgbe_link_speed speed,
791 bool autoneg,
792 bool autoneg_wait_to_complete)
793 {
794 s32 status;
795
796 /* Setup the PHY according to input speed */
797 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
798 autoneg_wait_to_complete);
799 /* Set up MAC */
800 ixgbe_setup_mac_link_82599(hw);
801
802 return status;
803 }
804
805 /**
806 * ixgbe_reset_hw_82599 - Perform hardware reset
807 * @hw: pointer to hardware structure
808 *
809 * Resets the hardware by resetting the transmit and receive units, masks
810 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
811 * reset.
812 **/
813 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
814 {
815 s32 status = 0;
816 u32 ctrl, ctrl_ext;
817 u32 i;
818 u32 autoc;
819 u32 autoc2;
820
821 /* Call adapter stop to disable tx/rx and clear interrupts */
822 hw->mac.ops.stop_adapter(hw);
823
824 /* PHY ops must be identified and initialized prior to reset */
825
826 /* Init PHY and function pointers, perform SFP setup */
827 status = hw->phy.ops.init(hw);
828
829 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
830 goto reset_hw_out;
831
832 /* Setup SFP module if there is one present. */
833 if (hw->phy.sfp_setup_needed) {
834 status = hw->mac.ops.setup_sfp(hw);
835 hw->phy.sfp_setup_needed = false;
836 }
837
838 /* Reset PHY */
839 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
840 hw->phy.ops.reset(hw);
841
842 /*
843 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
844 * access and verify no pending requests before reset
845 */
846 status = ixgbe_disable_pcie_master(hw);
847 if (status != 0) {
848 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
849 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
850 }
851
852 /*
853 * Issue global reset to the MAC. This needs to be a SW reset.
854 * If link reset is used, it might reset the MAC when mng is using it
855 */
856 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
857 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
858 IXGBE_WRITE_FLUSH(hw);
859
860 /* Poll for reset bit to self-clear indicating reset is complete */
861 for (i = 0; i < 10; i++) {
862 udelay(1);
863 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
864 if (!(ctrl & IXGBE_CTRL_RST))
865 break;
866 }
867 if (ctrl & IXGBE_CTRL_RST) {
868 status = IXGBE_ERR_RESET_FAILED;
869 hw_dbg(hw, "Reset polling failed to complete.\n");
870 }
871 /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
872 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
873 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
874 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
875
876 msleep(50);
877
878
879
880 /*
881 * Store the original AUTOC/AUTOC2 values if they have not been
882 * stored off yet. Otherwise restore the stored original
883 * values since the reset operation sets back to defaults.
884 */
885 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
886 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
887 if (hw->mac.orig_link_settings_stored == false) {
888 hw->mac.orig_autoc = autoc;
889 hw->mac.orig_autoc2 = autoc2;
890 hw->mac.orig_link_settings_stored = true;
891 } else {
892 if (autoc != hw->mac.orig_autoc)
893 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
894 IXGBE_AUTOC_AN_RESTART));
895
896 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
897 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
898 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
899 autoc2 |= (hw->mac.orig_autoc2 &
900 IXGBE_AUTOC2_UPPER_MASK);
901 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
902 }
903 }
904
905 /*
906 * Store MAC address from RAR0, clear receive address registers, and
907 * clear the multicast table. Also reset num_rar_entries to 128,
908 * since we modify this value when programming the SAN MAC address.
909 */
910 hw->mac.num_rar_entries = 128;
911 hw->mac.ops.init_rx_addrs(hw);
912
913 /* Store the permanent mac address */
914 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
915
916 /* Store the permanent SAN mac address */
917 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
918
919 /* Add the SAN MAC address to the RAR only if it's a valid address */
920 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
921 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
922 hw->mac.san_addr, 0, IXGBE_RAH_AV);
923
924 /* Reserve the last RAR for the SAN MAC address */
925 hw->mac.num_rar_entries--;
926 }
927
928 reset_hw_out:
929 return status;
930 }
931
932 /**
933 * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
934 * @hw: pointer to hardware struct
935 * @rar: receive address register index to disassociate
936 * @vmdq: VMDq pool index to remove from the rar
937 **/
938 s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
939 {
940 u32 mpsar_lo, mpsar_hi;
941 u32 rar_entries = hw->mac.num_rar_entries;
942
943 if (rar < rar_entries) {
944 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
945 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
946
947 if (!mpsar_lo && !mpsar_hi)
948 goto done;
949
950 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
951 if (mpsar_lo) {
952 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
953 mpsar_lo = 0;
954 }
955 if (mpsar_hi) {
956 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
957 mpsar_hi = 0;
958 }
959 } else if (vmdq < 32) {
960 mpsar_lo &= ~(1 << vmdq);
961 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
962 } else {
963 mpsar_hi &= ~(1 << (vmdq - 32));
964 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
965 }
966
967 /* was that the last pool using this rar? */
968 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
969 hw->mac.ops.clear_rar(hw, rar);
970 } else {
971 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
972 }
973
974 done:
975 return 0;
976 }
977
978 /**
979 * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
980 * @hw: pointer to hardware struct
981 * @rar: receive address register index to associate with a VMDq index
982 * @vmdq: VMDq pool index
983 **/
984 s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
985 {
986 u32 mpsar;
987 u32 rar_entries = hw->mac.num_rar_entries;
988
989 if (rar < rar_entries) {
990 if (vmdq < 32) {
991 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
992 mpsar |= 1 << vmdq;
993 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
994 } else {
995 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
996 mpsar |= 1 << (vmdq - 32);
997 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
998 }
999 } else {
1000 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
1001 }
1002 return 0;
1003 }
1004
1005 /**
1006 * ixgbe_set_vfta_82599 - Set VLAN filter table
1007 * @hw: pointer to hardware structure
1008 * @vlan: VLAN id to write to VLAN filter
1009 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
1010 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
1011 *
1012 * Turn on/off specified VLAN in the VLAN filter table.
1013 **/
1014 s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
1015 bool vlan_on)
1016 {
1017 u32 regindex;
1018 u32 bitindex;
1019 u32 bits;
1020 u32 first_empty_slot;
1021
1022 if (vlan > 4095)
1023 return IXGBE_ERR_PARAM;
1024
1025 /*
1026 * this is a 2 part operation - first the VFTA, then the
1027 * VLVF and VLVFB if vind is set
1028 */
1029
1030 /* Part 1
1031 * The VFTA is a bitstring made up of 128 32-bit registers
1032 * that enable the particular VLAN id, much like the MTA:
1033 * bits[11-5]: which register
1034 * bits[4-0]: which bit in the register
1035 */
1036 regindex = (vlan >> 5) & 0x7F;
1037 bitindex = vlan & 0x1F;
1038 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
1039 if (vlan_on)
1040 bits |= (1 << bitindex);
1041 else
1042 bits &= ~(1 << bitindex);
1043 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
1044
1045
1046 /* Part 2
1047 * If the vind is set
1048 * Either vlan_on
1049 * make sure the vlan is in VLVF
1050 * set the vind bit in the matching VLVFB
1051 * Or !vlan_on
1052 * clear the pool bit and possibly the vind
1053 */
1054 if (vind) {
1055 /* find the vlanid or the first empty slot */
1056 first_empty_slot = 0;
1057
1058 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
1059 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
1060 if (!bits && !first_empty_slot)
1061 first_empty_slot = regindex;
1062 else if ((bits & 0x0FFF) == vlan)
1063 break;
1064 }
1065
1066 if (regindex >= IXGBE_VLVF_ENTRIES) {
1067 if (first_empty_slot)
1068 regindex = first_empty_slot;
1069 else {
1070 hw_dbg(hw, "No space in VLVF.\n");
1071 goto out;
1072 }
1073 }
1074
1075 if (vlan_on) {
1076 /* set the pool bit */
1077 if (vind < 32) {
1078 bits = IXGBE_READ_REG(hw,
1079 IXGBE_VLVFB(regindex * 2));
1080 bits |= (1 << vind);
1081 IXGBE_WRITE_REG(hw,
1082 IXGBE_VLVFB(regindex * 2), bits);
1083 } else {
1084 bits = IXGBE_READ_REG(hw,
1085 IXGBE_VLVFB((regindex * 2) + 1));
1086 bits |= (1 << vind);
1087 IXGBE_WRITE_REG(hw,
1088 IXGBE_VLVFB((regindex * 2) + 1), bits);
1089 }
1090 } else {
1091 /* clear the pool bit */
1092 if (vind < 32) {
1093 bits = IXGBE_READ_REG(hw,
1094 IXGBE_VLVFB(regindex * 2));
1095 bits &= ~(1 << vind);
1096 IXGBE_WRITE_REG(hw,
1097 IXGBE_VLVFB(regindex * 2), bits);
1098 bits |= IXGBE_READ_REG(hw,
1099 IXGBE_VLVFB((regindex * 2) + 1));
1100 } else {
1101 bits = IXGBE_READ_REG(hw,
1102 IXGBE_VLVFB((regindex * 2) + 1));
1103 bits &= ~(1 << vind);
1104 IXGBE_WRITE_REG(hw,
1105 IXGBE_VLVFB((regindex * 2) + 1), bits);
1106 bits |= IXGBE_READ_REG(hw,
1107 IXGBE_VLVFB(regindex * 2));
1108 }
1109 }
1110
1111 if (bits)
1112 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex),
1113 (IXGBE_VLVF_VIEN | vlan));
1114 else
1115 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0);
1116 }
1117
1118 out:
1119 return 0;
1120 }
1121
1122 /**
1123 * ixgbe_clear_vfta_82599 - Clear VLAN filter table
1124 * @hw: pointer to hardware structure
1125 *
1126 * Clears the VLAN filer table, and the VMDq index associated with the filter
1127 **/
1128 s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
1129 {
1130 u32 offset;
1131
1132 for (offset = 0; offset < hw->mac.vft_size; offset++)
1133 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1134
1135 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
1136 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
1137 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
1138 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
1139 }
1140
1141 return 0;
1142 }
1143
1144 /**
1145 * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1146 * @hw: pointer to hardware structure
1147 **/
1148 s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
1149 {
1150 int i;
1151 hw_dbg(hw, " Clearing UTA\n");
1152
1153 for (i = 0; i < 128; i++)
1154 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1155
1156 return 0;
1157 }
1158
1159 /**
1160 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1161 * @hw: pointer to hardware structure
1162 * @reg: analog register to read
1163 * @val: read value
1164 *
1165 * Performs read operation to Omer analog register specified.
1166 **/
1167 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1168 {
1169 u32 core_ctl;
1170
1171 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1172 (reg << 8));
1173 IXGBE_WRITE_FLUSH(hw);
1174 udelay(10);
1175 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1176 *val = (u8)core_ctl;
1177
1178 return 0;
1179 }
1180
1181 /**
1182 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1183 * @hw: pointer to hardware structure
1184 * @reg: atlas register to write
1185 * @val: value to write
1186 *
1187 * Performs write operation to Omer analog register specified.
1188 **/
1189 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1190 {
1191 u32 core_ctl;
1192
1193 core_ctl = (reg << 8) | val;
1194 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1195 IXGBE_WRITE_FLUSH(hw);
1196 udelay(10);
1197
1198 return 0;
1199 }
1200
1201 /**
1202 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1203 * @hw: pointer to hardware structure
1204 *
1205 * Starts the hardware using the generic start_hw function.
1206 * Then performs device-specific:
1207 * Clears the rate limiter registers.
1208 **/
1209 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1210 {
1211 u32 q_num;
1212
1213 ixgbe_start_hw_generic(hw);
1214
1215 /* Clear the rate limiters */
1216 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
1217 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
1218 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
1219 }
1220 IXGBE_WRITE_FLUSH(hw);
1221
1222 /* We need to run link autotry after the driver loads */
1223 hw->mac.autotry_restart = true;
1224
1225 return 0;
1226 }
1227
1228 /**
1229 * ixgbe_identify_phy_82599 - Get physical layer module
1230 * @hw: pointer to hardware structure
1231 *
1232 * Determines the physical layer module found on the current adapter.
1233 **/
1234 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1235 {
1236 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1237 status = ixgbe_identify_phy_generic(hw);
1238 if (status != 0)
1239 status = ixgbe_identify_sfp_module_generic(hw);
1240 return status;
1241 }
1242
1243 /**
1244 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1245 * @hw: pointer to hardware structure
1246 *
1247 * Determines physical layer capabilities of the current configuration.
1248 **/
1249 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1250 {
1251 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1252 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1253 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1254 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1255 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1256 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1257 u16 ext_ability = 0;
1258 u8 comp_codes_10g = 0;
1259
1260 hw->phy.ops.identify(hw);
1261
1262 if (hw->phy.type == ixgbe_phy_tn ||
1263 hw->phy.type == ixgbe_phy_cu_unknown) {
1264 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1265 &ext_ability);
1266 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
1267 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1268 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
1269 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1270 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
1271 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1272 goto out;
1273 }
1274
1275 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1276 case IXGBE_AUTOC_LMS_1G_AN:
1277 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1278 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1279 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1280 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1281 goto out;
1282 } else
1283 /* SFI mode so read SFP module */
1284 goto sfp_check;
1285 break;
1286 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1287 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1288 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1289 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1290 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1291 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
1292 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
1293 goto out;
1294 break;
1295 case IXGBE_AUTOC_LMS_10G_SERIAL:
1296 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1297 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1298 goto out;
1299 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1300 goto sfp_check;
1301 break;
1302 case IXGBE_AUTOC_LMS_KX4_KX_KR:
1303 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1304 if (autoc & IXGBE_AUTOC_KX_SUPP)
1305 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1306 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1307 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1308 if (autoc & IXGBE_AUTOC_KR_SUPP)
1309 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1310 goto out;
1311 break;
1312 default:
1313 goto out;
1314 break;
1315 }
1316
1317 sfp_check:
1318 /* SFP check must be done last since DA modules are sometimes used to
1319 * test KR mode - we need to id KR mode correctly before SFP module.
1320 * Call identify_sfp because the pluggable module may have changed */
1321 hw->phy.ops.identify_sfp(hw);
1322 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1323 goto out;
1324
1325 switch (hw->phy.type) {
1326 case ixgbe_phy_tw_tyco:
1327 case ixgbe_phy_tw_unknown:
1328 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1329 break;
1330 case ixgbe_phy_sfp_avago:
1331 case ixgbe_phy_sfp_ftl:
1332 case ixgbe_phy_sfp_intel:
1333 case ixgbe_phy_sfp_unknown:
1334 hw->phy.ops.read_i2c_eeprom(hw,
1335 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1336 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1337 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1338 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1339 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1340 break;
1341 default:
1342 break;
1343 }
1344
1345 out:
1346 return physical_layer;
1347 }
1348
1349 /**
1350 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1351 * @hw: pointer to hardware structure
1352 * @regval: register value to write to RXCTRL
1353 *
1354 * Enables the Rx DMA unit for 82599
1355 **/
1356 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
1357 {
1358 #define IXGBE_MAX_SECRX_POLL 30
1359 int i;
1360 int secrxreg;
1361
1362 /*
1363 * Workaround for 82599 silicon errata when enabling the Rx datapath.
1364 * If traffic is incoming before we enable the Rx unit, it could hang
1365 * the Rx DMA unit. Therefore, make sure the security engine is
1366 * completely disabled prior to enabling the Rx unit.
1367 */
1368 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1369 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
1370 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1371 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
1372 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
1373 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
1374 break;
1375 else
1376 udelay(10);
1377 }
1378
1379 /* For informational purposes only */
1380 if (i >= IXGBE_MAX_SECRX_POLL)
1381 hw_dbg(hw, "Rx unit being enabled before security "
1382 "path fully disabled. Continuing with init.\n");
1383
1384 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
1385 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1386 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
1387 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1388 IXGBE_WRITE_FLUSH(hw);
1389
1390 return 0;
1391 }
1392
1393 /**
1394 * ixgbe_get_device_caps_82599 - Get additional device capabilities
1395 * @hw: pointer to hardware structure
1396 * @device_caps: the EEPROM word with the extra device capabilities
1397 *
1398 * This function will read the EEPROM location for the device capabilities,
1399 * and return the word through device_caps.
1400 **/
1401 s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
1402 {
1403 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
1404
1405 return 0;
1406 }
1407
1408 /**
1409 * ixgbe_get_san_mac_addr_offset_82599 - SAN MAC address offset for 82599
1410 * @hw: pointer to hardware structure
1411 * @san_mac_offset: SAN MAC address offset
1412 *
1413 * This function will read the EEPROM location for the SAN MAC address
1414 * pointer, and returns the value at that location. This is used in both
1415 * get and set mac_addr routines.
1416 **/
1417 s32 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw,
1418 u16 *san_mac_offset)
1419 {
1420 /*
1421 * First read the EEPROM pointer to see if the MAC addresses are
1422 * available.
1423 */
1424 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
1425
1426 return 0;
1427 }
1428
1429 /**
1430 * ixgbe_get_san_mac_addr_82599 - SAN MAC address retrieval for 82599
1431 * @hw: pointer to hardware structure
1432 * @san_mac_addr: SAN MAC address
1433 *
1434 * Reads the SAN MAC address from the EEPROM, if it's available. This is
1435 * per-port, so set_lan_id() must be called before reading the addresses.
1436 * set_lan_id() is called by identify_sfp(), but this cannot be relied
1437 * upon for non-SFP connections, so we must call it here.
1438 **/
1439 s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr)
1440 {
1441 u16 san_mac_data, san_mac_offset;
1442 u8 i;
1443
1444 /*
1445 * First read the EEPROM pointer to see if the MAC addresses are
1446 * available. If they're not, no point in calling set_lan_id() here.
1447 */
1448 ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset);
1449
1450 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
1451 /*
1452 * No addresses available in this EEPROM. It's not an
1453 * error though, so just wipe the local address and return.
1454 */
1455 for (i = 0; i < 6; i++)
1456 san_mac_addr[i] = 0xFF;
1457
1458 goto san_mac_addr_out;
1459 }
1460
1461 /* make sure we know which port we need to program */
1462 hw->mac.ops.set_lan_id(hw);
1463 /* apply the port offset to the address offset */
1464 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
1465 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
1466 for (i = 0; i < 3; i++) {
1467 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
1468 san_mac_addr[i * 2] = (u8)(san_mac_data);
1469 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
1470 san_mac_offset++;
1471 }
1472
1473 san_mac_addr_out:
1474 return 0;
1475 }
1476
1477 static struct ixgbe_mac_operations mac_ops_82599 = {
1478 .init_hw = &ixgbe_init_hw_generic,
1479 .reset_hw = &ixgbe_reset_hw_82599,
1480 .start_hw = &ixgbe_start_hw_82599,
1481 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
1482 .get_media_type = &ixgbe_get_media_type_82599,
1483 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
1484 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
1485 .get_mac_addr = &ixgbe_get_mac_addr_generic,
1486 .get_san_mac_addr = &ixgbe_get_san_mac_addr_82599,
1487 .get_device_caps = &ixgbe_get_device_caps_82599,
1488 .stop_adapter = &ixgbe_stop_adapter_generic,
1489 .get_bus_info = &ixgbe_get_bus_info_generic,
1490 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
1491 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
1492 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
1493 .setup_link = &ixgbe_setup_mac_link_82599,
1494 .setup_link_speed = &ixgbe_setup_mac_link_speed_82599,
1495 .check_link = &ixgbe_check_mac_link_82599,
1496 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
1497 .led_on = &ixgbe_led_on_generic,
1498 .led_off = &ixgbe_led_off_generic,
1499 .blink_led_start = &ixgbe_blink_led_start_generic,
1500 .blink_led_stop = &ixgbe_blink_led_stop_generic,
1501 .set_rar = &ixgbe_set_rar_generic,
1502 .clear_rar = &ixgbe_clear_rar_generic,
1503 .set_vmdq = &ixgbe_set_vmdq_82599,
1504 .clear_vmdq = &ixgbe_clear_vmdq_82599,
1505 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
1506 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
1507 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
1508 .enable_mc = &ixgbe_enable_mc_generic,
1509 .disable_mc = &ixgbe_disable_mc_generic,
1510 .clear_vfta = &ixgbe_clear_vfta_82599,
1511 .set_vfta = &ixgbe_set_vfta_82599,
1512 .setup_fc = &ixgbe_setup_fc_generic,
1513 .init_uta_tables = &ixgbe_init_uta_tables_82599,
1514 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
1515 };
1516
1517 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
1518 .init_params = &ixgbe_init_eeprom_params_generic,
1519 .read = &ixgbe_read_eeprom_generic,
1520 .write = &ixgbe_write_eeprom_generic,
1521 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
1522 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
1523 };
1524
1525 static struct ixgbe_phy_operations phy_ops_82599 = {
1526 .identify = &ixgbe_identify_phy_82599,
1527 .identify_sfp = &ixgbe_identify_sfp_module_generic,
1528 .init = &ixgbe_init_phy_ops_82599,
1529 .reset = &ixgbe_reset_phy_generic,
1530 .read_reg = &ixgbe_read_phy_reg_generic,
1531 .write_reg = &ixgbe_write_phy_reg_generic,
1532 .setup_link = &ixgbe_setup_phy_link_generic,
1533 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
1534 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
1535 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
1536 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
1537 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
1538 };
1539
1540 struct ixgbe_info ixgbe_82599_info = {
1541 .mac = ixgbe_mac_82599EB,
1542 .get_invariants = &ixgbe_get_invariants_82599,
1543 .mac_ops = &mac_ops_82599,
1544 .eeprom_ops = &eeprom_ops_82599,
1545 .phy_ops = &phy_ops_82599,
1546 };
AMDTP streaming driver for the Linux FireWire stack (Juju)