2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
33 #define ATHEROS_VENDOR_ID 0x168c
34 #define AR5416_DEVID_PCI 0x0023
35 #define AR5416_DEVID_PCIE 0x0024
36 #define AR9160_DEVID_PCI 0x0027
37 #define AR9280_DEVID_PCI 0x0029
38 #define AR9280_DEVID_PCIE 0x002a
39 #define AR9285_DEVID_PCIE 0x002b
40 #define AR5416_AR9100_DEVID 0x000b
41 #define AR_SUBVENDOR_ID_NOG 0x0e11
42 #define AR_SUBVENDOR_ID_NEW_A 0x7065
43 #define AR5416_MAGIC 0x19641014
45 /* Register read/write primitives */
46 #define REG_WRITE(_ah, _reg, _val) ath9k_iowrite32((_ah), (_reg), (_val))
47 #define REG_READ(_ah, _reg) ath9k_ioread32((_ah), (_reg))
49 #define SM(_v, _f) (((_v) << _f##_S) & _f)
50 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
51 #define REG_RMW(_a, _r, _set, _clr) \
52 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
53 #define REG_RMW_FIELD(_a, _r, _f, _v) \
55 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
56 #define REG_SET_BIT(_a, _r, _f) \
57 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
58 #define REG_CLR_BIT(_a, _r, _f) \
59 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
61 #define DO_DELAY(x) do { \
62 if ((++(x) % 64) == 0) \
66 #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
68 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
69 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
70 INI_RA((iniarray), r, (column))); \
75 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
76 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
77 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
78 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
79 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
80 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
82 #define AR_GPIOD_MASK 0x00001FFF
83 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
85 #define BASE_ACTIVATE_DELAY 100
86 #define RTC_PLL_SETTLE_DELAY 1000
87 #define COEF_SCALE_S 24
88 #define HT40_CHANNEL_CENTER_SHIFT 10
90 #define ATH9K_ANTENNA0_CHAINMASK 0x1
91 #define ATH9K_ANTENNA1_CHAINMASK 0x2
93 #define ATH9K_NUM_DMA_DEBUG_REGS 8
94 #define ATH9K_NUM_QUEUES 10
96 #define MAX_RATE_POWER 63
97 #define AH_WAIT_TIMEOUT 100000 /* (us) */
98 #define AH_TIME_QUANTUM 10
99 #define AR_KEYTABLE_SIZE 128
100 #define POWER_UP_TIME 200000
101 #define SPUR_RSSI_THRESH 40
103 #define CAB_TIMEOUT_VAL 10
104 #define BEACON_TIMEOUT_VAL 10
105 #define MIN_BEACON_TIMEOUT_VAL 1
108 #define INIT_CONFIG_STATUS 0x00000000
109 #define INIT_RSSI_THR 0x00000700
110 #define INIT_BCON_CNTRL_REG 0x00000000
112 #define TU_TO_USEC(_tu) ((_tu) << 10)
118 ATH9K_MODE_11NA_HT20
= 6,
119 ATH9K_MODE_11NG_HT20
= 7,
120 ATH9K_MODE_11NA_HT40PLUS
= 8,
121 ATH9K_MODE_11NA_HT40MINUS
= 9,
122 ATH9K_MODE_11NG_HT40PLUS
= 10,
123 ATH9K_MODE_11NG_HT40MINUS
= 11,
128 ATH9K_HW_CAP_MIC_AESCCM
= BIT(0),
129 ATH9K_HW_CAP_MIC_CKIP
= BIT(1),
130 ATH9K_HW_CAP_MIC_TKIP
= BIT(2),
131 ATH9K_HW_CAP_CIPHER_AESCCM
= BIT(3),
132 ATH9K_HW_CAP_CIPHER_CKIP
= BIT(4),
133 ATH9K_HW_CAP_CIPHER_TKIP
= BIT(5),
134 ATH9K_HW_CAP_VEOL
= BIT(6),
135 ATH9K_HW_CAP_BSSIDMASK
= BIT(7),
136 ATH9K_HW_CAP_MCAST_KEYSEARCH
= BIT(8),
137 ATH9K_HW_CAP_HT
= BIT(9),
138 ATH9K_HW_CAP_GTT
= BIT(10),
139 ATH9K_HW_CAP_FASTCC
= BIT(11),
140 ATH9K_HW_CAP_RFSILENT
= BIT(12),
141 ATH9K_HW_CAP_CST
= BIT(13),
142 ATH9K_HW_CAP_ENHANCEDPM
= BIT(14),
143 ATH9K_HW_CAP_AUTOSLEEP
= BIT(15),
144 ATH9K_HW_CAP_4KB_SPLITTRANS
= BIT(16),
145 ATH9K_HW_CAP_BT_COEX
= BIT(17)
148 enum ath9k_capability_type
{
149 ATH9K_CAP_CIPHER
= 0,
151 ATH9K_CAP_TKIP_SPLIT
,
154 ATH9K_CAP_MCAST_KEYSRCH
,
158 struct ath9k_hw_capabilities
{
159 u32 hw_caps
; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
160 DECLARE_BITMAP(wireless_modes
, ATH9K_MODE_MAX
); /* ATH9K_MODE_* */
163 u16 low_5ghz_chan
, high_5ghz_chan
;
164 u16 low_2ghz_chan
, high_2ghz_chan
;
168 u16 tx_triglevel_max
;
175 struct ath9k_ops_config
{
176 int dma_beacon_response_time
;
177 int sw_beacon_response_time
;
178 int additional_swba_backoff
;
180 int cwm_ignore_extcca
;
181 u8 pcie_powersave_enable
;
191 u16 diversity_control
;
192 u16 antenna_switch_swap
;
193 int serialize_regmode
;
194 bool intr_mitigation
;
195 #define SPUR_DISABLE 0
196 #define SPUR_ENABLE_IOCTL 1
197 #define SPUR_ENABLE_EEPROM 2
198 #define AR_EEPROM_MODAL_SPURS 5
199 #define AR_SPUR_5413_1 1640
200 #define AR_SPUR_5413_2 1200
201 #define AR_NO_SPUR 0x8000
202 #define AR_BASE_FREQ_2GHZ 2300
203 #define AR_BASE_FREQ_5GHZ 4900
204 #define AR_SPUR_FEEQ_BOUND_HT40 19
205 #define AR_SPUR_FEEQ_BOUND_HT20 10
207 u16 spurchans
[AR_EEPROM_MODAL_SPURS
][2];
211 ATH9K_INT_RX
= 0x00000001,
212 ATH9K_INT_RXDESC
= 0x00000002,
213 ATH9K_INT_RXNOFRM
= 0x00000008,
214 ATH9K_INT_RXEOL
= 0x00000010,
215 ATH9K_INT_RXORN
= 0x00000020,
216 ATH9K_INT_TX
= 0x00000040,
217 ATH9K_INT_TXDESC
= 0x00000080,
218 ATH9K_INT_TIM_TIMER
= 0x00000100,
219 ATH9K_INT_TXURN
= 0x00000800,
220 ATH9K_INT_MIB
= 0x00001000,
221 ATH9K_INT_RXPHY
= 0x00004000,
222 ATH9K_INT_RXKCM
= 0x00008000,
223 ATH9K_INT_SWBA
= 0x00010000,
224 ATH9K_INT_BMISS
= 0x00040000,
225 ATH9K_INT_BNR
= 0x00100000,
226 ATH9K_INT_TIM
= 0x00200000,
227 ATH9K_INT_DTIM
= 0x00400000,
228 ATH9K_INT_DTIMSYNC
= 0x00800000,
229 ATH9K_INT_GPIO
= 0x01000000,
230 ATH9K_INT_CABEND
= 0x02000000,
231 ATH9K_INT_TSFOOR
= 0x04000000,
232 ATH9K_INT_CST
= 0x10000000,
233 ATH9K_INT_GTT
= 0x20000000,
234 ATH9K_INT_FATAL
= 0x40000000,
235 ATH9K_INT_GLOBAL
= 0x80000000,
236 ATH9K_INT_BMISC
= ATH9K_INT_TIM
|
241 ATH9K_INT_COMMON
= ATH9K_INT_RXNOFRM
|
253 ATH9K_INT_NOCARD
= 0xffffffff
256 #define CHANNEL_CW_INT 0x00002
257 #define CHANNEL_CCK 0x00020
258 #define CHANNEL_OFDM 0x00040
259 #define CHANNEL_2GHZ 0x00080
260 #define CHANNEL_5GHZ 0x00100
261 #define CHANNEL_PASSIVE 0x00200
262 #define CHANNEL_DYN 0x00400
263 #define CHANNEL_HALF 0x04000
264 #define CHANNEL_QUARTER 0x08000
265 #define CHANNEL_HT20 0x10000
266 #define CHANNEL_HT40PLUS 0x20000
267 #define CHANNEL_HT40MINUS 0x40000
269 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
270 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
271 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
272 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
273 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
274 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
275 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
276 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
277 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
278 #define CHANNEL_ALL \
287 struct ath9k_channel
{
288 struct ieee80211_channel
*chan
;
293 bool oneTimeCalsDone
;
296 int16_t rawNoiseFloor
;
299 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
300 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
301 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
302 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
303 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
304 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
305 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
306 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
307 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
308 #define IS_CHAN_A_5MHZ_SPACED(_c) \
309 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
310 (((_c)->channel % 20) != 0) && \
311 (((_c)->channel % 10) != 0))
313 /* These macros check chanmode and not channelFlags */
314 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
315 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
316 ((_c)->chanmode == CHANNEL_G_HT20))
317 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
318 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
319 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
320 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
321 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
323 enum ath9k_power_mode
{
326 ATH9K_PM_NETWORK_SLEEP
,
330 enum ath9k_ant_setting
{
331 ATH9K_ANT_VARIABLE
= 0,
336 enum ath9k_tp_scale
{
337 ATH9K_TP_SCALE_MAX
= 0,
345 SER_REG_MODE_OFF
= 0,
347 SER_REG_MODE_AUTO
= 2,
350 struct ath9k_beacon_state
{
354 #define ATH9K_BEACON_PERIOD 0x0000ffff
355 #define ATH9K_BEACON_ENA 0x00800000
356 #define ATH9K_BEACON_RESET_TSF 0x01000000
357 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
360 u16 bs_cfpmaxduration
;
363 u16 bs_bmissthreshold
;
364 u32 bs_sleepduration
;
365 u32 bs_tsfoor_threshold
;
368 struct chan_centers
{
375 ATH9K_RESET_POWER_ON
,
380 struct ath9k_hw_version
{
392 struct ath_softc
*ah_sc
;
393 struct ath9k_hw_version hw_version
;
394 struct ath9k_ops_config config
;
395 struct ath9k_hw_capabilities caps
;
396 struct ath_regulatory regulatory
;
397 struct ath9k_channel channels
[38];
398 struct ath9k_channel
*curchan
;
401 struct ar5416_eeprom_def def
;
402 struct ar5416_eeprom_4k map4k
;
404 const struct eeprom_ops
*eep_ops
;
405 enum ath9k_eep_map eep_map
;
409 u8 macaddr
[ETH_ALEN
];
418 enum nl80211_iftype opmode
;
419 enum ath9k_power_mode power_mode
;
420 enum ath9k_power_mode restore_mode
;
422 struct ath9k_nfcal_hist nfCalHist
[NUM_NF_READINGS
];
423 struct ar5416Stats stats
;
424 struct ath9k_tx_queue_info txq
[ATH9K_NUM_TX_QUEUES
];
426 int16_t curchan_rad_index
;
428 u32 txok_interrupt_mask
;
429 u32 txerr_interrupt_mask
;
430 u32 txdesc_interrupt_mask
;
431 u32 txeol_interrupt_mask
;
432 u32 txurn_interrupt_mask
;
435 u16 antenna_switch_swap
;
436 enum ath9k_ant_setting diversity_control
;
439 enum ath9k_cal_types supp_cals
;
440 struct ath9k_cal_list iq_caldata
;
441 struct ath9k_cal_list adcgain_caldata
;
442 struct ath9k_cal_list adcdc_calinitdata
;
443 struct ath9k_cal_list adcdc_caldata
;
444 struct ath9k_cal_list
*cal_list
;
445 struct ath9k_cal_list
*cal_list_last
;
446 struct ath9k_cal_list
*cal_list_curr
;
447 #define totalPowerMeasI meas0.unsign
448 #define totalPowerMeasQ meas1.unsign
449 #define totalIqCorrMeas meas2.sign
450 #define totalAdcIOddPhase meas0.unsign
451 #define totalAdcIEvenPhase meas1.unsign
452 #define totalAdcQOddPhase meas2.unsign
453 #define totalAdcQEvenPhase meas3.unsign
454 #define totalAdcDcOffsetIOddPhase meas0.sign
455 #define totalAdcDcOffsetIEvenPhase meas1.sign
456 #define totalAdcDcOffsetQOddPhase meas2.sign
457 #define totalAdcDcOffsetQEvenPhase meas3.sign
459 u32 unsign
[AR5416_MAX_CHAINS
];
460 int32_t sign
[AR5416_MAX_CHAINS
];
463 u32 unsign
[AR5416_MAX_CHAINS
];
464 int32_t sign
[AR5416_MAX_CHAINS
];
467 u32 unsign
[AR5416_MAX_CHAINS
];
468 int32_t sign
[AR5416_MAX_CHAINS
];
471 u32 unsign
[AR5416_MAX_CHAINS
];
472 int32_t sign
[AR5416_MAX_CHAINS
];
476 u32 sta_id1_defaults
;
482 } enable_32kHz_clock
;
485 u32
*analogBank0Data
;
486 u32
*analogBank1Data
;
487 u32
*analogBank2Data
;
488 u32
*analogBank3Data
;
489 u32
*analogBank6Data
;
490 u32
*analogBank6TPCData
;
491 u32
*analogBank7Data
;
495 int16_t txpower_indexoffset
;
505 bool has_hw_phycounters
;
507 struct ar5416AniState
*curani
;
508 struct ar5416AniState ani
[255];
509 int totalSizeDesired
[5];
513 enum ath9k_ani_cmd ani_function
;
516 enum ath9k_ht_extprotspacing extprotspacing
;
520 u32 originalGain
[22];
524 struct ar5416IniArray iniModes
;
525 struct ar5416IniArray iniCommon
;
526 struct ar5416IniArray iniBank0
;
527 struct ar5416IniArray iniBB_RfGain
;
528 struct ar5416IniArray iniBank1
;
529 struct ar5416IniArray iniBank2
;
530 struct ar5416IniArray iniBank3
;
531 struct ar5416IniArray iniBank6
;
532 struct ar5416IniArray iniBank6TPC
;
533 struct ar5416IniArray iniBank7
;
534 struct ar5416IniArray iniAddac
;
535 struct ar5416IniArray iniPcieSerdes
;
536 struct ar5416IniArray iniModesAdditional
;
537 struct ar5416IniArray iniModesRxGain
;
538 struct ar5416IniArray iniModesTxGain
;
541 /* Attach, Detach, Reset */
542 const char *ath9k_hw_probe(u16 vendorid
, u16 devid
);
543 void ath9k_hw_detach(struct ath_hw
*ah
);
544 struct ath_hw
*ath9k_hw_attach(u16 devid
, struct ath_softc
*sc
, int *error
);
545 void ath9k_hw_rfdetach(struct ath_hw
*ah
);
546 int ath9k_hw_reset(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
547 bool bChannelChange
);
548 void ath9k_hw_fill_cap_info(struct ath_hw
*ah
);
549 bool ath9k_hw_getcapability(struct ath_hw
*ah
, enum ath9k_capability_type type
,
550 u32 capability
, u32
*result
);
551 bool ath9k_hw_setcapability(struct ath_hw
*ah
, enum ath9k_capability_type type
,
552 u32 capability
, u32 setting
, int *status
);
554 /* Key Cache Management */
555 bool ath9k_hw_keyreset(struct ath_hw
*ah
, u16 entry
);
556 bool ath9k_hw_keysetmac(struct ath_hw
*ah
, u16 entry
, const u8
*mac
);
557 bool ath9k_hw_set_keycache_entry(struct ath_hw
*ah
, u16 entry
,
558 const struct ath9k_keyval
*k
,
560 bool ath9k_hw_keyisvalid(struct ath_hw
*ah
, u16 entry
);
562 /* GPIO / RFKILL / Antennae */
563 void ath9k_hw_cfg_gpio_input(struct ath_hw
*ah
, u32 gpio
);
564 u32
ath9k_hw_gpio_get(struct ath_hw
*ah
, u32 gpio
);
565 void ath9k_hw_cfg_output(struct ath_hw
*ah
, u32 gpio
,
567 void ath9k_hw_set_gpio(struct ath_hw
*ah
, u32 gpio
, u32 val
);
568 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
569 void ath9k_enable_rfkill(struct ath_hw
*ah
);
571 u32
ath9k_hw_getdefantenna(struct ath_hw
*ah
);
572 void ath9k_hw_setantenna(struct ath_hw
*ah
, u32 antenna
);
573 bool ath9k_hw_setantennaswitch(struct ath_hw
*ah
,
574 enum ath9k_ant_setting settings
,
575 struct ath9k_channel
*chan
,
576 u8
*tx_chainmask
, u8
*rx_chainmask
,
579 /* General Operation */
580 bool ath9k_hw_wait(struct ath_hw
*ah
, u32 reg
, u32 mask
, u32 val
, u32 timeout
);
581 u32
ath9k_hw_reverse_bits(u32 val
, u32 n
);
582 bool ath9k_get_channel_edges(struct ath_hw
*ah
, u16 flags
, u16
*low
, u16
*high
);
583 u16
ath9k_hw_computetxtime(struct ath_hw
*ah
,
584 const struct ath_rate_table
*rates
,
585 u32 frameLen
, u16 rateix
, bool shortPreamble
);
586 void ath9k_hw_get_channel_centers(struct ath_hw
*ah
,
587 struct ath9k_channel
*chan
,
588 struct chan_centers
*centers
);
589 u32
ath9k_hw_getrxfilter(struct ath_hw
*ah
);
590 void ath9k_hw_setrxfilter(struct ath_hw
*ah
, u32 bits
);
591 bool ath9k_hw_phy_disable(struct ath_hw
*ah
);
592 bool ath9k_hw_disable(struct ath_hw
*ah
);
593 bool ath9k_hw_set_txpowerlimit(struct ath_hw
*ah
, u32 limit
);
594 void ath9k_hw_setmac(struct ath_hw
*ah
, const u8
*mac
);
595 void ath9k_hw_setopmode(struct ath_hw
*ah
);
596 void ath9k_hw_setmcastfilter(struct ath_hw
*ah
, u32 filter0
, u32 filter1
);
597 void ath9k_hw_setbssidmask(struct ath_softc
*sc
);
598 void ath9k_hw_write_associd(struct ath_softc
*sc
);
599 u64
ath9k_hw_gettsf64(struct ath_hw
*ah
);
600 void ath9k_hw_settsf64(struct ath_hw
*ah
, u64 tsf64
);
601 void ath9k_hw_reset_tsf(struct ath_hw
*ah
);
602 bool ath9k_hw_set_tsfadjust(struct ath_hw
*ah
, u32 setting
);
603 bool ath9k_hw_setslottime(struct ath_hw
*ah
, u32 us
);
604 void ath9k_hw_set11nmac2040(struct ath_hw
*ah
, enum ath9k_ht_macmode mode
);
605 void ath9k_hw_beaconinit(struct ath_hw
*ah
, u32 next_beacon
, u32 beacon_period
);
606 void ath9k_hw_set_sta_beacon_timers(struct ath_hw
*ah
,
607 const struct ath9k_beacon_state
*bs
);
608 bool ath9k_hw_setpower(struct ath_hw
*ah
,
609 enum ath9k_power_mode mode
);
610 void ath9k_hw_configpcipowersave(struct ath_hw
*ah
, int restore
);
612 /* Interrupt Handling */
613 bool ath9k_hw_intrpend(struct ath_hw
*ah
);
614 bool ath9k_hw_getisr(struct ath_hw
*ah
, enum ath9k_int
*masked
);
615 enum ath9k_int
ath9k_hw_intrget(struct ath_hw
*ah
);
616 enum ath9k_int
ath9k_hw_set_interrupts(struct ath_hw
*ah
, enum ath9k_int ints
);
618 void ath9k_hw_btcoex_enable(struct ath_hw
*ah
);