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ath9k: make private driver rate tables const
[firewire-audio.git] / drivers / net / wireless / ath / ath9k / hw.c
blob041c0f518ac7ff2f551e0692b77c8a5c1f582081
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "ath9k.h"
21 #include "initvals.h"
22
23 static int btcoex_enable;
24 module_param(btcoex_enable, bool, 0);
25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
26
27 #define ATH9K_CLOCK_RATE_CCK 22
28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
30
31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
33 enum ath9k_ht_macmode macmode);
34 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
35 struct ar5416_eeprom_def *pEepData,
36 u32 reg, u32 value);
37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
38 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
39
40 /********************/
41 /* Helper Functions */
42 /********************/
43
44 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
45 {
46 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
47
48 if (!ah->curchan) /* should really check for CCK instead */
49 return clks / ATH9K_CLOCK_RATE_CCK;
50 if (conf->channel->band == IEEE80211_BAND_2GHZ)
51 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
52
53 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
54 }
55
56 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
57 {
58 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
59
60 if (conf_is_ht40(conf))
61 return ath9k_hw_mac_usec(ah, clks) / 2;
62 else
63 return ath9k_hw_mac_usec(ah, clks);
64 }
65
66 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
67 {
68 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
69
70 if (!ah->curchan) /* should really check for CCK instead */
71 return usecs *ATH9K_CLOCK_RATE_CCK;
72 if (conf->channel->band == IEEE80211_BAND_2GHZ)
73 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
74 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
75 }
76
77 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
78 {
79 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
80
81 if (conf_is_ht40(conf))
82 return ath9k_hw_mac_clks(ah, usecs) * 2;
83 else
84 return ath9k_hw_mac_clks(ah, usecs);
85 }
86
87 /*
88 * Read and write, they both share the same lock. We do this to serialize
89 * reads and writes on Atheros 802.11n PCI devices only. This is required
90 * as the FIFO on these devices can only accept sanely 2 requests. After
91 * that the device goes bananas. Serializing the reads/writes prevents this
92 * from happening.
93 */
94
95 void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
96 {
97 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
98 unsigned long flags;
99 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
100 iowrite32(val, ah->ah_sc->mem + reg_offset);
101 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
102 } else
103 iowrite32(val, ah->ah_sc->mem + reg_offset);
104 }
105
106 unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
107 {
108 u32 val;
109 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
110 unsigned long flags;
111 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
112 val = ioread32(ah->ah_sc->mem + reg_offset);
113 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
114 } else
115 val = ioread32(ah->ah_sc->mem + reg_offset);
116 return val;
117 }
118
119 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
120 {
121 int i;
122
123 BUG_ON(timeout < AH_TIME_QUANTUM);
124
125 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
126 if ((REG_READ(ah, reg) & mask) == val)
127 return true;
128
129 udelay(AH_TIME_QUANTUM);
130 }
131
132 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
133 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
134 timeout, reg, REG_READ(ah, reg), mask, val);
135
136 return false;
137 }
138
139 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
140 {
141 u32 retval;
142 int i;
143
144 for (i = 0, retval = 0; i < n; i++) {
145 retval = (retval << 1) | (val & 1);
146 val >>= 1;
147 }
148 return retval;
149 }
150
151 bool ath9k_get_channel_edges(struct ath_hw *ah,
152 u16 flags, u16 *low,
153 u16 *high)
154 {
155 struct ath9k_hw_capabilities *pCap = &ah->caps;
156
157 if (flags & CHANNEL_5GHZ) {
158 *low = pCap->low_5ghz_chan;
159 *high = pCap->high_5ghz_chan;
160 return true;
161 }
162 if ((flags & CHANNEL_2GHZ)) {
163 *low = pCap->low_2ghz_chan;
164 *high = pCap->high_2ghz_chan;
165 return true;
166 }
167 return false;
168 }
169
170 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
171 const struct ath_rate_table *rates,
172 u32 frameLen, u16 rateix,
173 bool shortPreamble)
174 {
175 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
176 u32 kbps;
177
178 kbps = rates->info[rateix].ratekbps;
179
180 if (kbps == 0)
181 return 0;
182
183 switch (rates->info[rateix].phy) {
184 case WLAN_RC_PHY_CCK:
185 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
186 if (shortPreamble && rates->info[rateix].short_preamble)
187 phyTime >>= 1;
188 numBits = frameLen << 3;
189 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
190 break;
191 case WLAN_RC_PHY_OFDM:
192 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
193 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
194 numBits = OFDM_PLCP_BITS + (frameLen << 3);
195 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
196 txTime = OFDM_SIFS_TIME_QUARTER
197 + OFDM_PREAMBLE_TIME_QUARTER
198 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
199 } else if (ah->curchan &&
200 IS_CHAN_HALF_RATE(ah->curchan)) {
201 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
202 numBits = OFDM_PLCP_BITS + (frameLen << 3);
203 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
204 txTime = OFDM_SIFS_TIME_HALF +
205 OFDM_PREAMBLE_TIME_HALF
206 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
207 } else {
208 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
209 numBits = OFDM_PLCP_BITS + (frameLen << 3);
210 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
211 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
212 + (numSymbols * OFDM_SYMBOL_TIME);
213 }
214 break;
215 default:
216 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
217 "Unknown phy %u (rate ix %u)\n",
218 rates->info[rateix].phy, rateix);
219 txTime = 0;
220 break;
221 }
222
223 return txTime;
224 }
225
226 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
227 struct ath9k_channel *chan,
228 struct chan_centers *centers)
229 {
230 int8_t extoff;
231
232 if (!IS_CHAN_HT40(chan)) {
233 centers->ctl_center = centers->ext_center =
234 centers->synth_center = chan->channel;
235 return;
236 }
237
238 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
239 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
240 centers->synth_center =
241 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
242 extoff = 1;
243 } else {
244 centers->synth_center =
245 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
246 extoff = -1;
247 }
248
249 centers->ctl_center =
250 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
251 centers->ext_center =
252 centers->synth_center + (extoff *
253 ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
254 HT40_CHANNEL_CENTER_SHIFT : 15));
255 }
256
257 /******************/
258 /* Chip Revisions */
259 /******************/
260
261 static void ath9k_hw_read_revisions(struct ath_hw *ah)
262 {
263 u32 val;
264
265 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
266
267 if (val == 0xFF) {
268 val = REG_READ(ah, AR_SREV);
269 ah->hw_version.macVersion =
270 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
271 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
272 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
273 } else {
274 if (!AR_SREV_9100(ah))
275 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
276
277 ah->hw_version.macRev = val & AR_SREV_REVISION;
278
279 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
280 ah->is_pciexpress = true;
281 }
282 }
283
284 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
285 {
286 u32 val;
287 int i;
288
289 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
290
291 for (i = 0; i < 8; i++)
292 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
293 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
294 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
295
296 return ath9k_hw_reverse_bits(val, 8);
297 }
298
299 /************************************/
300 /* HW Attach, Detach, Init Routines */
301 /************************************/
302
303 static void ath9k_hw_disablepcie(struct ath_hw *ah)
304 {
305 if (AR_SREV_9100(ah))
306 return;
307
308 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
309 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
310 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
311 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
312 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
313 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
314 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
315 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
316 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
317
318 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
319 }
320
321 static bool ath9k_hw_chip_test(struct ath_hw *ah)
322 {
323 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
324 u32 regHold[2];
325 u32 patternData[4] = { 0x55555555,
326 0xaaaaaaaa,
327 0x66666666,
328 0x99999999 };
329 int i, j;
330
331 for (i = 0; i < 2; i++) {
332 u32 addr = regAddr[i];
333 u32 wrData, rdData;
334
335 regHold[i] = REG_READ(ah, addr);
336 for (j = 0; j < 0x100; j++) {
337 wrData = (j << 16) | j;
338 REG_WRITE(ah, addr, wrData);
339 rdData = REG_READ(ah, addr);
340 if (rdData != wrData) {
341 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
342 "address test failed "
343 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
344 addr, wrData, rdData);
345 return false;
346 }
347 }
348 for (j = 0; j < 4; j++) {
349 wrData = patternData[j];
350 REG_WRITE(ah, addr, wrData);
351 rdData = REG_READ(ah, addr);
352 if (wrData != rdData) {
353 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
354 "address test failed "
355 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
356 addr, wrData, rdData);
357 return false;
358 }
359 }
360 REG_WRITE(ah, regAddr[i], regHold[i]);
361 }
362 udelay(100);
363
364 return true;
365 }
366
367 static const char *ath9k_hw_devname(u16 devid)
368 {
369 switch (devid) {
370 case AR5416_DEVID_PCI:
371 return "Atheros 5416";
372 case AR5416_DEVID_PCIE:
373 return "Atheros 5418";
374 case AR9160_DEVID_PCI:
375 return "Atheros 9160";
376 case AR5416_AR9100_DEVID:
377 return "Atheros 9100";
378 case AR9280_DEVID_PCI:
379 case AR9280_DEVID_PCIE:
380 return "Atheros 9280";
381 case AR9285_DEVID_PCIE:
382 return "Atheros 9285";
383 }
384
385 return NULL;
386 }
387
388 static void ath9k_hw_set_defaults(struct ath_hw *ah)
389 {
390 int i;
391
392 ah->config.dma_beacon_response_time = 2;
393 ah->config.sw_beacon_response_time = 10;
394 ah->config.additional_swba_backoff = 0;
395 ah->config.ack_6mb = 0x0;
396 ah->config.cwm_ignore_extcca = 0;
397 ah->config.pcie_powersave_enable = 0;
398 ah->config.pcie_clock_req = 0;
399 ah->config.pcie_waen = 0;
400 ah->config.analog_shiftreg = 1;
401 ah->config.ht_enable = 1;
402 ah->config.ofdm_trig_low = 200;
403 ah->config.ofdm_trig_high = 500;
404 ah->config.cck_trig_high = 200;
405 ah->config.cck_trig_low = 100;
406 ah->config.enable_ani = 1;
407 ah->config.diversity_control = 0;
408 ah->config.antenna_switch_swap = 0;
409
410 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
411 ah->config.spurchans[i][0] = AR_NO_SPUR;
412 ah->config.spurchans[i][1] = AR_NO_SPUR;
413 }
414
415 ah->config.intr_mitigation = true;
416
417 /*
418 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
419 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
420 * This means we use it for all AR5416 devices, and the few
421 * minor PCI AR9280 devices out there.
422 *
423 * Serialization is required because these devices do not handle
424 * well the case of two concurrent reads/writes due to the latency
425 * involved. During one read/write another read/write can be issued
426 * on another CPU while the previous read/write may still be working
427 * on our hardware, if we hit this case the hardware poops in a loop.
428 * We prevent this by serializing reads and writes.
429 *
430 * This issue is not present on PCI-Express devices or pre-AR5416
431 * devices (legacy, 802.11abg).
432 */
433 if (num_possible_cpus() > 1)
434 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
435 }
436
437 static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc,
438 int *status)
439 {
440 struct ath_hw *ah;
441
442 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
443 if (ah == NULL) {
444 DPRINTF(sc, ATH_DBG_FATAL,
445 "Cannot allocate memory for state block\n");
446 *status = -ENOMEM;
447 return NULL;
448 }
449
450 ah->ah_sc = sc;
451 ah->hw_version.magic = AR5416_MAGIC;
452 ah->regulatory.country_code = CTRY_DEFAULT;
453 ah->hw_version.devid = devid;
454 ah->hw_version.subvendorid = 0;
455
456 ah->ah_flags = 0;
457 if ((devid == AR5416_AR9100_DEVID))
458 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
459 if (!AR_SREV_9100(ah))
460 ah->ah_flags = AH_USE_EEPROM;
461
462 ah->regulatory.power_limit = MAX_RATE_POWER;
463 ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
464 ah->atim_window = 0;
465 ah->diversity_control = ah->config.diversity_control;
466 ah->antenna_switch_swap =
467 ah->config.antenna_switch_swap;
468 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
469 ah->beacon_interval = 100;
470 ah->enable_32kHz_clock = DONT_USE_32KHZ;
471 ah->slottime = (u32) -1;
472 ah->acktimeout = (u32) -1;
473 ah->ctstimeout = (u32) -1;
474 ah->globaltxtimeout = (u32) -1;
475
476 ah->gbeacon_rate = 0;
477
478 return ah;
479 }
480
481 static int ath9k_hw_rfattach(struct ath_hw *ah)
482 {
483 bool rfStatus = false;
484 int ecode = 0;
485
486 rfStatus = ath9k_hw_init_rf(ah, &ecode);
487 if (!rfStatus) {
488 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
489 "RF setup failed, status: %u\n", ecode);
490 return ecode;
491 }
492
493 return 0;
494 }
495
496 static int ath9k_hw_rf_claim(struct ath_hw *ah)
497 {
498 u32 val;
499
500 REG_WRITE(ah, AR_PHY(0), 0x00000007);
501
502 val = ath9k_hw_get_radiorev(ah);
503 switch (val & AR_RADIO_SREV_MAJOR) {
504 case 0:
505 val = AR_RAD5133_SREV_MAJOR;
506 break;
507 case AR_RAD5133_SREV_MAJOR:
508 case AR_RAD5122_SREV_MAJOR:
509 case AR_RAD2133_SREV_MAJOR:
510 case AR_RAD2122_SREV_MAJOR:
511 break;
512 default:
513 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
514 "Radio Chip Rev 0x%02X not supported\n",
515 val & AR_RADIO_SREV_MAJOR);
516 return -EOPNOTSUPP;
517 }
518
519 ah->hw_version.analog5GhzRev = val;
520
521 return 0;
522 }
523
524 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
525 {
526 u32 sum;
527 int i;
528 u16 eeval;
529
530 sum = 0;
531 for (i = 0; i < 3; i++) {
532 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
533 sum += eeval;
534 ah->macaddr[2 * i] = eeval >> 8;
535 ah->macaddr[2 * i + 1] = eeval & 0xff;
536 }
537 if (sum == 0 || sum == 0xffff * 3)
538 return -EADDRNOTAVAIL;
539
540 return 0;
541 }
542
543 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
544 {
545 u32 rxgain_type;
546
547 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
548 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
549
550 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
551 INIT_INI_ARRAY(&ah->iniModesRxGain,
552 ar9280Modes_backoff_13db_rxgain_9280_2,
553 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
554 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
555 INIT_INI_ARRAY(&ah->iniModesRxGain,
556 ar9280Modes_backoff_23db_rxgain_9280_2,
557 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
558 else
559 INIT_INI_ARRAY(&ah->iniModesRxGain,
560 ar9280Modes_original_rxgain_9280_2,
561 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
562 } else {
563 INIT_INI_ARRAY(&ah->iniModesRxGain,
564 ar9280Modes_original_rxgain_9280_2,
565 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
566 }
567 }
568
569 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
570 {
571 u32 txgain_type;
572
573 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
574 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
575
576 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
577 INIT_INI_ARRAY(&ah->iniModesTxGain,
578 ar9280Modes_high_power_tx_gain_9280_2,
579 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
580 else
581 INIT_INI_ARRAY(&ah->iniModesTxGain,
582 ar9280Modes_original_tx_gain_9280_2,
583 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
584 } else {
585 INIT_INI_ARRAY(&ah->iniModesTxGain,
586 ar9280Modes_original_tx_gain_9280_2,
587 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
588 }
589 }
590
591 static int ath9k_hw_post_attach(struct ath_hw *ah)
592 {
593 int ecode;
594
595 if (!ath9k_hw_chip_test(ah))
596 return -ENODEV;
597
598 ecode = ath9k_hw_rf_claim(ah);
599 if (ecode != 0)
600 return ecode;
601
602 ecode = ath9k_hw_eeprom_attach(ah);
603 if (ecode != 0)
604 return ecode;
605
606 DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
607 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
608
609 ecode = ath9k_hw_rfattach(ah);
610 if (ecode != 0)
611 return ecode;
612
613 if (!AR_SREV_9100(ah)) {
614 ath9k_hw_ani_setup(ah);
615 ath9k_hw_ani_attach(ah);
616 }
617
618 return 0;
619 }
620
621 static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
622 int *status)
623 {
624 struct ath_hw *ah;
625 int ecode;
626 u32 i, j;
627
628 ah = ath9k_hw_newstate(devid, sc, status);
629 if (ah == NULL)
630 return NULL;
631
632 ath9k_hw_set_defaults(ah);
633
634 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
635 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't reset chip\n");
636 ecode = -EIO;
637 goto bad;
638 }
639
640 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
641 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
642 ecode = -EIO;
643 goto bad;
644 }
645
646 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
647 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
648 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
649 ah->config.serialize_regmode =
650 SER_REG_MODE_ON;
651 } else {
652 ah->config.serialize_regmode =
653 SER_REG_MODE_OFF;
654 }
655 }
656
657 DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
658 ah->config.serialize_regmode);
659
660 if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) &&
661 (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&
662 (ah->hw_version.macVersion != AR_SREV_VERSION_9160) &&
663 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
664 DPRINTF(sc, ATH_DBG_FATAL,
665 "Mac Chip Rev 0x%02x.%x is not supported by "
666 "this driver\n", ah->hw_version.macVersion,
667 ah->hw_version.macRev);
668 ecode = -EOPNOTSUPP;
669 goto bad;
670 }
671
672 if (AR_SREV_9100(ah)) {
673 ah->iq_caldata.calData = &iq_cal_multi_sample;
674 ah->supp_cals = IQ_MISMATCH_CAL;
675 ah->is_pciexpress = false;
676 }
677 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
678
679 if (AR_SREV_9160_10_OR_LATER(ah)) {
680 if (AR_SREV_9280_10_OR_LATER(ah)) {
681 ah->iq_caldata.calData = &iq_cal_single_sample;
682 ah->adcgain_caldata.calData =
683 &adc_gain_cal_single_sample;
684 ah->adcdc_caldata.calData =
685 &adc_dc_cal_single_sample;
686 ah->adcdc_calinitdata.calData =
687 &adc_init_dc_cal;
688 } else {
689 ah->iq_caldata.calData = &iq_cal_multi_sample;
690 ah->adcgain_caldata.calData =
691 &adc_gain_cal_multi_sample;
692 ah->adcdc_caldata.calData =
693 &adc_dc_cal_multi_sample;
694 ah->adcdc_calinitdata.calData =
695 &adc_init_dc_cal;
696 }
697 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
698 }
699
700 ah->ani_function = ATH9K_ANI_ALL;
701 if (AR_SREV_9280_10_OR_LATER(ah))
702 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
703
704 if (AR_SREV_9285_12_OR_LATER(ah)) {
705
706 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
707 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
708 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
709 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
710
711 if (ah->config.pcie_clock_req) {
712 INIT_INI_ARRAY(&ah->iniPcieSerdes,
713 ar9285PciePhy_clkreq_off_L1_9285_1_2,
714 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
715 } else {
716 INIT_INI_ARRAY(&ah->iniPcieSerdes,
717 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
718 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
719 2);
720 }
721 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
722 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
723 ARRAY_SIZE(ar9285Modes_9285), 6);
724 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
725 ARRAY_SIZE(ar9285Common_9285), 2);
726
727 if (ah->config.pcie_clock_req) {
728 INIT_INI_ARRAY(&ah->iniPcieSerdes,
729 ar9285PciePhy_clkreq_off_L1_9285,
730 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
731 } else {
732 INIT_INI_ARRAY(&ah->iniPcieSerdes,
733 ar9285PciePhy_clkreq_always_on_L1_9285,
734 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
735 }
736 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
737 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
738 ARRAY_SIZE(ar9280Modes_9280_2), 6);
739 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
740 ARRAY_SIZE(ar9280Common_9280_2), 2);
741
742 if (ah->config.pcie_clock_req) {
743 INIT_INI_ARRAY(&ah->iniPcieSerdes,
744 ar9280PciePhy_clkreq_off_L1_9280,
745 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
746 } else {
747 INIT_INI_ARRAY(&ah->iniPcieSerdes,
748 ar9280PciePhy_clkreq_always_on_L1_9280,
749 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
750 }
751 INIT_INI_ARRAY(&ah->iniModesAdditional,
752 ar9280Modes_fast_clock_9280_2,
753 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
754 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
755 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
756 ARRAY_SIZE(ar9280Modes_9280), 6);
757 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
758 ARRAY_SIZE(ar9280Common_9280), 2);
759 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
760 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
761 ARRAY_SIZE(ar5416Modes_9160), 6);
762 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
763 ARRAY_SIZE(ar5416Common_9160), 2);
764 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
765 ARRAY_SIZE(ar5416Bank0_9160), 2);
766 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
767 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
768 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
769 ARRAY_SIZE(ar5416Bank1_9160), 2);
770 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
771 ARRAY_SIZE(ar5416Bank2_9160), 2);
772 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
773 ARRAY_SIZE(ar5416Bank3_9160), 3);
774 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
775 ARRAY_SIZE(ar5416Bank6_9160), 3);
776 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
777 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
778 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
779 ARRAY_SIZE(ar5416Bank7_9160), 2);
780 if (AR_SREV_9160_11(ah)) {
781 INIT_INI_ARRAY(&ah->iniAddac,
782 ar5416Addac_91601_1,
783 ARRAY_SIZE(ar5416Addac_91601_1), 2);
784 } else {
785 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
786 ARRAY_SIZE(ar5416Addac_9160), 2);
787 }
788 } else if (AR_SREV_9100_OR_LATER(ah)) {
789 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
790 ARRAY_SIZE(ar5416Modes_9100), 6);
791 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
792 ARRAY_SIZE(ar5416Common_9100), 2);
793 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
794 ARRAY_SIZE(ar5416Bank0_9100), 2);
795 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
796 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
797 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
798 ARRAY_SIZE(ar5416Bank1_9100), 2);
799 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
800 ARRAY_SIZE(ar5416Bank2_9100), 2);
801 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
802 ARRAY_SIZE(ar5416Bank3_9100), 3);
803 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
804 ARRAY_SIZE(ar5416Bank6_9100), 3);
805 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
806 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
807 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
808 ARRAY_SIZE(ar5416Bank7_9100), 2);
809 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
810 ARRAY_SIZE(ar5416Addac_9100), 2);
811 } else {
812 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
813 ARRAY_SIZE(ar5416Modes), 6);
814 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
815 ARRAY_SIZE(ar5416Common), 2);
816 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
817 ARRAY_SIZE(ar5416Bank0), 2);
818 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
819 ARRAY_SIZE(ar5416BB_RfGain), 3);
820 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
821 ARRAY_SIZE(ar5416Bank1), 2);
822 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
823 ARRAY_SIZE(ar5416Bank2), 2);
824 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
825 ARRAY_SIZE(ar5416Bank3), 3);
826 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
827 ARRAY_SIZE(ar5416Bank6), 3);
828 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
829 ARRAY_SIZE(ar5416Bank6TPC), 3);
830 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
831 ARRAY_SIZE(ar5416Bank7), 2);
832 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
833 ARRAY_SIZE(ar5416Addac), 2);
834 }
835
836 if (ah->is_pciexpress)
837 ath9k_hw_configpcipowersave(ah, 0);
838 else
839 ath9k_hw_disablepcie(ah);
840
841 ecode = ath9k_hw_post_attach(ah);
842 if (ecode != 0)
843 goto bad;
844
845 if (AR_SREV_9285_12_OR_LATER(ah)) {
846 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
847
848 /* txgain table */
849 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
850 INIT_INI_ARRAY(&ah->iniModesTxGain,
851 ar9285Modes_high_power_tx_gain_9285_1_2,
852 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
853 } else {
854 INIT_INI_ARRAY(&ah->iniModesTxGain,
855 ar9285Modes_original_tx_gain_9285_1_2,
856 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
857 }
858
859 }
860
861 /* rxgain table */
862 if (AR_SREV_9280_20(ah))
863 ath9k_hw_init_rxgain_ini(ah);
864
865 /* txgain table */
866 if (AR_SREV_9280_20(ah))
867 ath9k_hw_init_txgain_ini(ah);
868
869 ath9k_hw_fill_cap_info(ah);
870
871 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
872 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
873
874 /* EEPROM Fixup */
875 for (i = 0; i < ah->iniModes.ia_rows; i++) {
876 u32 reg = INI_RA(&ah->iniModes, i, 0);
877
878 for (j = 1; j < ah->iniModes.ia_columns; j++) {
879 u32 val = INI_RA(&ah->iniModes, i, j);
880
881 INI_RA(&ah->iniModes, i, j) =
882 ath9k_hw_ini_fixup(ah,
883 &ah->eeprom.def,
884 reg, val);
885 }
886 }
887 }
888
889 ecode = ath9k_hw_init_macaddr(ah);
890 if (ecode != 0) {
891 DPRINTF(sc, ATH_DBG_FATAL,
892 "Failed to initialize MAC address\n");
893 goto bad;
894 }
895
896 if (AR_SREV_9285(ah))
897 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
898 else
899 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
900
901 ath9k_init_nfcal_hist_buffer(ah);
902
903 return ah;
904 bad:
905 if (ah)
906 ath9k_hw_detach(ah);
907 if (status)
908 *status = ecode;
909
910 return NULL;
911 }
912
913 static void ath9k_hw_init_bb(struct ath_hw *ah,
914 struct ath9k_channel *chan)
915 {
916 u32 synthDelay;
917
918 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
919 if (IS_CHAN_B(chan))
920 synthDelay = (4 * synthDelay) / 22;
921 else
922 synthDelay /= 10;
923
924 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
925
926 udelay(synthDelay + BASE_ACTIVATE_DELAY);
927 }
928
929 static void ath9k_hw_init_qos(struct ath_hw *ah)
930 {
931 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
932 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
933
934 REG_WRITE(ah, AR_QOS_NO_ACK,
935 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
936 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
937 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
938
939 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
940 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
941 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
942 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
943 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
944 }
945
946 static void ath9k_hw_init_pll(struct ath_hw *ah,
947 struct ath9k_channel *chan)
948 {
949 u32 pll;
950
951 if (AR_SREV_9100(ah)) {
952 if (chan && IS_CHAN_5GHZ(chan))
953 pll = 0x1450;
954 else
955 pll = 0x1458;
956 } else {
957 if (AR_SREV_9280_10_OR_LATER(ah)) {
958 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
959
960 if (chan && IS_CHAN_HALF_RATE(chan))
961 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
962 else if (chan && IS_CHAN_QUARTER_RATE(chan))
963 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
964
965 if (chan && IS_CHAN_5GHZ(chan)) {
966 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
967
968
969 if (AR_SREV_9280_20(ah)) {
970 if (((chan->channel % 20) == 0)
971 || ((chan->channel % 10) == 0))
972 pll = 0x2850;
973 else
974 pll = 0x142c;
975 }
976 } else {
977 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
978 }
979
980 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
981
982 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
983
984 if (chan && IS_CHAN_HALF_RATE(chan))
985 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
986 else if (chan && IS_CHAN_QUARTER_RATE(chan))
987 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
988
989 if (chan && IS_CHAN_5GHZ(chan))
990 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
991 else
992 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
993 } else {
994 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
995
996 if (chan && IS_CHAN_HALF_RATE(chan))
997 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
998 else if (chan && IS_CHAN_QUARTER_RATE(chan))
999 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1000
1001 if (chan && IS_CHAN_5GHZ(chan))
1002 pll |= SM(0xa, AR_RTC_PLL_DIV);
1003 else
1004 pll |= SM(0xb, AR_RTC_PLL_DIV);
1005 }
1006 }
1007 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1008
1009 udelay(RTC_PLL_SETTLE_DELAY);
1010
1011 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1012 }
1013
1014 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1015 {
1016 int rx_chainmask, tx_chainmask;
1017
1018 rx_chainmask = ah->rxchainmask;
1019 tx_chainmask = ah->txchainmask;
1020
1021 switch (rx_chainmask) {
1022 case 0x5:
1023 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1024 AR_PHY_SWAP_ALT_CHAIN);
1025 case 0x3:
1026 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1027 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1028 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1029 break;
1030 }
1031 case 0x1:
1032 case 0x2:
1033 case 0x7:
1034 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1035 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1036 break;
1037 default:
1038 break;
1039 }
1040
1041 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1042 if (tx_chainmask == 0x5) {
1043 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1044 AR_PHY_SWAP_ALT_CHAIN);
1045 }
1046 if (AR_SREV_9100(ah))
1047 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1048 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1049 }
1050
1051 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1052 enum nl80211_iftype opmode)
1053 {
1054 ah->mask_reg = AR_IMR_TXERR |
1055 AR_IMR_TXURN |
1056 AR_IMR_RXERR |
1057 AR_IMR_RXORN |
1058 AR_IMR_BCNMISC;
1059
1060 if (ah->config.intr_mitigation)
1061 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1062 else
1063 ah->mask_reg |= AR_IMR_RXOK;
1064
1065 ah->mask_reg |= AR_IMR_TXOK;
1066
1067 if (opmode == NL80211_IFTYPE_AP)
1068 ah->mask_reg |= AR_IMR_MIB;
1069
1070 REG_WRITE(ah, AR_IMR, ah->mask_reg);
1071 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1072
1073 if (!AR_SREV_9100(ah)) {
1074 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1075 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1076 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1077 }
1078 }
1079
1080 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1081 {
1082 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1083 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1084 ah->acktimeout = (u32) -1;
1085 return false;
1086 } else {
1087 REG_RMW_FIELD(ah, AR_TIME_OUT,
1088 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1089 ah->acktimeout = us;
1090 return true;
1091 }
1092 }
1093
1094 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1095 {
1096 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1097 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1098 ah->ctstimeout = (u32) -1;
1099 return false;
1100 } else {
1101 REG_RMW_FIELD(ah, AR_TIME_OUT,
1102 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1103 ah->ctstimeout = us;
1104 return true;
1105 }
1106 }
1107
1108 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1109 {
1110 if (tu > 0xFFFF) {
1111 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1112 "bad global tx timeout %u\n", tu);
1113 ah->globaltxtimeout = (u32) -1;
1114 return false;
1115 } else {
1116 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1117 ah->globaltxtimeout = tu;
1118 return true;
1119 }
1120 }
1121
1122 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1123 {
1124 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1125 ah->misc_mode);
1126
1127 if (ah->misc_mode != 0)
1128 REG_WRITE(ah, AR_PCU_MISC,
1129 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1130 if (ah->slottime != (u32) -1)
1131 ath9k_hw_setslottime(ah, ah->slottime);
1132 if (ah->acktimeout != (u32) -1)
1133 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1134 if (ah->ctstimeout != (u32) -1)
1135 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1136 if (ah->globaltxtimeout != (u32) -1)
1137 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1138 }
1139
1140 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1141 {
1142 return vendorid == ATHEROS_VENDOR_ID ?
1143 ath9k_hw_devname(devid) : NULL;
1144 }
1145
1146 void ath9k_hw_detach(struct ath_hw *ah)
1147 {
1148 if (!AR_SREV_9100(ah))
1149 ath9k_hw_ani_detach(ah);
1150
1151 ath9k_hw_rfdetach(ah);
1152 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1153 kfree(ah);
1154 }
1155
1156 struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error)
1157 {
1158 struct ath_hw *ah = NULL;
1159
1160 switch (devid) {
1161 case AR5416_DEVID_PCI:
1162 case AR5416_DEVID_PCIE:
1163 case AR5416_AR9100_DEVID:
1164 case AR9160_DEVID_PCI:
1165 case AR9280_DEVID_PCI:
1166 case AR9280_DEVID_PCIE:
1167 case AR9285_DEVID_PCIE:
1168 ah = ath9k_hw_do_attach(devid, sc, error);
1169 break;
1170 default:
1171 *error = -ENXIO;
1172 break;
1173 }
1174
1175 return ah;
1176 }
1177
1178 /*******/
1179 /* INI */
1180 /*******/
1181
1182 static void ath9k_hw_override_ini(struct ath_hw *ah,
1183 struct ath9k_channel *chan)
1184 {
1185 /*
1186 * Set the RX_ABORT and RX_DIS and clear if off only after
1187 * RXE is set for MAC. This prevents frames with corrupted
1188 * descriptor status.
1189 */
1190 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1191
1192
1193 if (!AR_SREV_5416_20_OR_LATER(ah) ||
1194 AR_SREV_9280_10_OR_LATER(ah))
1195 return;
1196
1197 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1198 }
1199
1200 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1201 struct ar5416_eeprom_def *pEepData,
1202 u32 reg, u32 value)
1203 {
1204 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1205
1206 switch (ah->hw_version.devid) {
1207 case AR9280_DEVID_PCI:
1208 if (reg == 0x7894) {
1209 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1210 "ini VAL: %x EEPROM: %x\n", value,
1211 (pBase->version & 0xff));
1212
1213 if ((pBase->version & 0xff) > 0x0a) {
1214 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1215 "PWDCLKIND: %d\n",
1216 pBase->pwdclkind);
1217 value &= ~AR_AN_TOP2_PWDCLKIND;
1218 value |= AR_AN_TOP2_PWDCLKIND &
1219 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1220 } else {
1221 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1222 "PWDCLKIND Earlier Rev\n");
1223 }
1224
1225 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1226 "final ini VAL: %x\n", value);
1227 }
1228 break;
1229 }
1230
1231 return value;
1232 }
1233
1234 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1235 struct ar5416_eeprom_def *pEepData,
1236 u32 reg, u32 value)
1237 {
1238 if (ah->eep_map == EEP_MAP_4KBITS)
1239 return value;
1240 else
1241 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1242 }
1243
1244 static void ath9k_olc_init(struct ath_hw *ah)
1245 {
1246 u32 i;
1247
1248 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1249 ah->originalGain[i] =
1250 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1251 AR_PHY_TX_GAIN);
1252 ah->PDADCdelta = 0;
1253 }
1254
1255 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1256 struct ath9k_channel *chan)
1257 {
1258 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1259
1260 if (IS_CHAN_B(chan))
1261 ctl |= CTL_11B;
1262 else if (IS_CHAN_G(chan))
1263 ctl |= CTL_11G;
1264 else
1265 ctl |= CTL_11A;
1266
1267 return ctl;
1268 }
1269
1270 static int ath9k_hw_process_ini(struct ath_hw *ah,
1271 struct ath9k_channel *chan,
1272 enum ath9k_ht_macmode macmode)
1273 {
1274 int i, regWrites = 0;
1275 struct ieee80211_channel *channel = chan->chan;
1276 u32 modesIndex, freqIndex;
1277 int status;
1278
1279 switch (chan->chanmode) {
1280 case CHANNEL_A:
1281 case CHANNEL_A_HT20:
1282 modesIndex = 1;
1283 freqIndex = 1;
1284 break;
1285 case CHANNEL_A_HT40PLUS:
1286 case CHANNEL_A_HT40MINUS:
1287 modesIndex = 2;
1288 freqIndex = 1;
1289 break;
1290 case CHANNEL_G:
1291 case CHANNEL_G_HT20:
1292 case CHANNEL_B:
1293 modesIndex = 4;
1294 freqIndex = 2;
1295 break;
1296 case CHANNEL_G_HT40PLUS:
1297 case CHANNEL_G_HT40MINUS:
1298 modesIndex = 3;
1299 freqIndex = 2;
1300 break;
1301
1302 default:
1303 return -EINVAL;
1304 }
1305
1306 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1307 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1308 ah->eep_ops->set_addac(ah, chan);
1309
1310 if (AR_SREV_5416_22_OR_LATER(ah)) {
1311 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1312 } else {
1313 struct ar5416IniArray temp;
1314 u32 addacSize =
1315 sizeof(u32) * ah->iniAddac.ia_rows *
1316 ah->iniAddac.ia_columns;
1317
1318 memcpy(ah->addac5416_21,
1319 ah->iniAddac.ia_array, addacSize);
1320
1321 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1322
1323 temp.ia_array = ah->addac5416_21;
1324 temp.ia_columns = ah->iniAddac.ia_columns;
1325 temp.ia_rows = ah->iniAddac.ia_rows;
1326 REG_WRITE_ARRAY(&temp, 1, regWrites);
1327 }
1328
1329 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1330
1331 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1332 u32 reg = INI_RA(&ah->iniModes, i, 0);
1333 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1334
1335 REG_WRITE(ah, reg, val);
1336
1337 if (reg >= 0x7800 && reg < 0x78a0
1338 && ah->config.analog_shiftreg) {
1339 udelay(100);
1340 }
1341
1342 DO_DELAY(regWrites);
1343 }
1344
1345 if (AR_SREV_9280(ah))
1346 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1347
1348 if (AR_SREV_9280(ah) || (AR_SREV_9285(ah) &&
1349 AR_SREV_9285_12_OR_LATER(ah)))
1350 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1351
1352 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1353 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1354 u32 val = INI_RA(&ah->iniCommon, i, 1);
1355
1356 REG_WRITE(ah, reg, val);
1357
1358 if (reg >= 0x7800 && reg < 0x78a0
1359 && ah->config.analog_shiftreg) {
1360 udelay(100);
1361 }
1362
1363 DO_DELAY(regWrites);
1364 }
1365
1366 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1367
1368 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1369 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1370 regWrites);
1371 }
1372
1373 ath9k_hw_override_ini(ah, chan);
1374 ath9k_hw_set_regs(ah, chan, macmode);
1375 ath9k_hw_init_chain_masks(ah);
1376
1377 if (OLC_FOR_AR9280_20_LATER)
1378 ath9k_olc_init(ah);
1379
1380 status = ah->eep_ops->set_txpower(ah, chan,
1381 ath9k_regd_get_ctl(&ah->regulatory, chan),
1382 channel->max_antenna_gain * 2,
1383 channel->max_power * 2,
1384 min((u32) MAX_RATE_POWER,
1385 (u32) ah->regulatory.power_limit));
1386 if (status != 0) {
1387 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1388 "Error initializing transmit power\n");
1389 return -EIO;
1390 }
1391
1392 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1393 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1394 "ar5416SetRfRegs failed\n");
1395 return -EIO;
1396 }
1397
1398 return 0;
1399 }
1400
1401 /****************************************/
1402 /* Reset and Channel Switching Routines */
1403 /****************************************/
1404
1405 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1406 {
1407 u32 rfMode = 0;
1408
1409 if (chan == NULL)
1410 return;
1411
1412 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1413 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1414
1415 if (!AR_SREV_9280_10_OR_LATER(ah))
1416 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1417 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1418
1419 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1420 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1421
1422 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1423 }
1424
1425 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1426 {
1427 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1428 }
1429
1430 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1431 {
1432 u32 regval;
1433
1434 regval = REG_READ(ah, AR_AHB_MODE);
1435 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1436
1437 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1438 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1439
1440 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1441
1442 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1443 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1444
1445 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1446
1447 if (AR_SREV_9285(ah)) {
1448 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1449 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1450 } else {
1451 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1452 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1453 }
1454 }
1455
1456 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1457 {
1458 u32 val;
1459
1460 val = REG_READ(ah, AR_STA_ID1);
1461 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1462 switch (opmode) {
1463 case NL80211_IFTYPE_AP:
1464 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1465 | AR_STA_ID1_KSRCH_MODE);
1466 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1467 break;
1468 case NL80211_IFTYPE_ADHOC:
1469 case NL80211_IFTYPE_MESH_POINT:
1470 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1471 | AR_STA_ID1_KSRCH_MODE);
1472 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1473 break;
1474 case NL80211_IFTYPE_STATION:
1475 case NL80211_IFTYPE_MONITOR:
1476 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1477 break;
1478 }
1479 }
1480
1481 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1482 u32 coef_scaled,
1483 u32 *coef_mantissa,
1484 u32 *coef_exponent)
1485 {
1486 u32 coef_exp, coef_man;
1487
1488 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1489 if ((coef_scaled >> coef_exp) & 0x1)
1490 break;
1491
1492 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1493
1494 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1495
1496 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1497 *coef_exponent = coef_exp - 16;
1498 }
1499
1500 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1501 struct ath9k_channel *chan)
1502 {
1503 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1504 u32 clockMhzScaled = 0x64000000;
1505 struct chan_centers centers;
1506
1507 if (IS_CHAN_HALF_RATE(chan))
1508 clockMhzScaled = clockMhzScaled >> 1;
1509 else if (IS_CHAN_QUARTER_RATE(chan))
1510 clockMhzScaled = clockMhzScaled >> 2;
1511
1512 ath9k_hw_get_channel_centers(ah, chan, &centers);
1513 coef_scaled = clockMhzScaled / centers.synth_center;
1514
1515 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1516 &ds_coef_exp);
1517
1518 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1519 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1520 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1521 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1522
1523 coef_scaled = (9 * coef_scaled) / 10;
1524
1525 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1526 &ds_coef_exp);
1527
1528 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1529 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1530 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1531 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1532 }
1533
1534 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1535 {
1536 u32 rst_flags;
1537 u32 tmpReg;
1538
1539 if (AR_SREV_9100(ah)) {
1540 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1541 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1542 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1543 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1544 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1545 }
1546
1547 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1548 AR_RTC_FORCE_WAKE_ON_INT);
1549
1550 if (AR_SREV_9100(ah)) {
1551 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1552 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1553 } else {
1554 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1555 if (tmpReg &
1556 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1557 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1558 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1559 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1560 } else {
1561 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1562 }
1563
1564 rst_flags = AR_RTC_RC_MAC_WARM;
1565 if (type == ATH9K_RESET_COLD)
1566 rst_flags |= AR_RTC_RC_MAC_COLD;
1567 }
1568
1569 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1570 udelay(50);
1571
1572 REG_WRITE(ah, AR_RTC_RC, 0);
1573 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1574 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1575 "RTC stuck in MAC reset\n");
1576 return false;
1577 }
1578
1579 if (!AR_SREV_9100(ah))
1580 REG_WRITE(ah, AR_RC, 0);
1581
1582 ath9k_hw_init_pll(ah, NULL);
1583
1584 if (AR_SREV_9100(ah))
1585 udelay(50);
1586
1587 return true;
1588 }
1589
1590 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1591 {
1592 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1593 AR_RTC_FORCE_WAKE_ON_INT);
1594
1595 REG_WRITE(ah, AR_RTC_RESET, 0);
1596 udelay(2);
1597 REG_WRITE(ah, AR_RTC_RESET, 1);
1598
1599 if (!ath9k_hw_wait(ah,
1600 AR_RTC_STATUS,
1601 AR_RTC_STATUS_M,
1602 AR_RTC_STATUS_ON,
1603 AH_WAIT_TIMEOUT)) {
1604 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1605 return false;
1606 }
1607
1608 ath9k_hw_read_revisions(ah);
1609
1610 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1611 }
1612
1613 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1614 {
1615 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1616 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1617
1618 switch (type) {
1619 case ATH9K_RESET_POWER_ON:
1620 return ath9k_hw_set_reset_power_on(ah);
1621 break;
1622 case ATH9K_RESET_WARM:
1623 case ATH9K_RESET_COLD:
1624 return ath9k_hw_set_reset(ah, type);
1625 break;
1626 default:
1627 return false;
1628 }
1629 }
1630
1631 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1632 enum ath9k_ht_macmode macmode)
1633 {
1634 u32 phymode;
1635 u32 enableDacFifo = 0;
1636
1637 if (AR_SREV_9285_10_OR_LATER(ah))
1638 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1639 AR_PHY_FC_ENABLE_DAC_FIFO);
1640
1641 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1642 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1643
1644 if (IS_CHAN_HT40(chan)) {
1645 phymode |= AR_PHY_FC_DYN2040_EN;
1646
1647 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1648 (chan->chanmode == CHANNEL_G_HT40PLUS))
1649 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1650
1651 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1652 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1653 }
1654 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1655
1656 ath9k_hw_set11nmac2040(ah, macmode);
1657
1658 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1659 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1660 }
1661
1662 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1663 struct ath9k_channel *chan)
1664 {
1665 if (OLC_FOR_AR9280_20_LATER) {
1666 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1667 return false;
1668 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1669 return false;
1670
1671 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1672 return false;
1673
1674 ah->chip_fullsleep = false;
1675 ath9k_hw_init_pll(ah, chan);
1676 ath9k_hw_set_rfmode(ah, chan);
1677
1678 return true;
1679 }
1680
1681 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1682 struct ath9k_channel *chan,
1683 enum ath9k_ht_macmode macmode)
1684 {
1685 struct ieee80211_channel *channel = chan->chan;
1686 u32 synthDelay, qnum;
1687
1688 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1689 if (ath9k_hw_numtxpending(ah, qnum)) {
1690 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1691 "Transmit frames pending on queue %d\n", qnum);
1692 return false;
1693 }
1694 }
1695
1696 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1697 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1698 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1699 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1700 "Could not kill baseband RX\n");
1701 return false;
1702 }
1703
1704 ath9k_hw_set_regs(ah, chan, macmode);
1705
1706 if (AR_SREV_9280_10_OR_LATER(ah)) {
1707 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1708 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1709 "Failed to set channel\n");
1710 return false;
1711 }
1712 } else {
1713 if (!(ath9k_hw_set_channel(ah, chan))) {
1714 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1715 "Failed to set channel\n");
1716 return false;
1717 }
1718 }
1719
1720 if (ah->eep_ops->set_txpower(ah, chan,
1721 ath9k_regd_get_ctl(&ah->regulatory, chan),
1722 channel->max_antenna_gain * 2,
1723 channel->max_power * 2,
1724 min((u32) MAX_RATE_POWER,
1725 (u32) ah->regulatory.power_limit)) != 0) {
1726 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1727 "Error initializing transmit power\n");
1728 return false;
1729 }
1730
1731 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1732 if (IS_CHAN_B(chan))
1733 synthDelay = (4 * synthDelay) / 22;
1734 else
1735 synthDelay /= 10;
1736
1737 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1738
1739 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1740
1741 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1742 ath9k_hw_set_delta_slope(ah, chan);
1743
1744 if (AR_SREV_9280_10_OR_LATER(ah))
1745 ath9k_hw_9280_spur_mitigate(ah, chan);
1746 else
1747 ath9k_hw_spur_mitigate(ah, chan);
1748
1749 if (!chan->oneTimeCalsDone)
1750 chan->oneTimeCalsDone = true;
1751
1752 return true;
1753 }
1754
1755 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1756 {
1757 int bb_spur = AR_NO_SPUR;
1758 int freq;
1759 int bin, cur_bin;
1760 int bb_spur_off, spur_subchannel_sd;
1761 int spur_freq_sd;
1762 int spur_delta_phase;
1763 int denominator;
1764 int upper, lower, cur_vit_mask;
1765 int tmp, newVal;
1766 int i;
1767 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1768 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1769 };
1770 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1771 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1772 };
1773 int inc[4] = { 0, 100, 0, 0 };
1774 struct chan_centers centers;
1775
1776 int8_t mask_m[123];
1777 int8_t mask_p[123];
1778 int8_t mask_amt;
1779 int tmp_mask;
1780 int cur_bb_spur;
1781 bool is2GHz = IS_CHAN_2GHZ(chan);
1782
1783 memset(&mask_m, 0, sizeof(int8_t) * 123);
1784 memset(&mask_p, 0, sizeof(int8_t) * 123);
1785
1786 ath9k_hw_get_channel_centers(ah, chan, &centers);
1787 freq = centers.synth_center;
1788
1789 ah->config.spurmode = SPUR_ENABLE_EEPROM;
1790 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1791 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1792
1793 if (is2GHz)
1794 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1795 else
1796 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1797
1798 if (AR_NO_SPUR == cur_bb_spur)
1799 break;
1800 cur_bb_spur = cur_bb_spur - freq;
1801
1802 if (IS_CHAN_HT40(chan)) {
1803 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1804 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1805 bb_spur = cur_bb_spur;
1806 break;
1807 }
1808 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1809 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1810 bb_spur = cur_bb_spur;
1811 break;
1812 }
1813 }
1814
1815 if (AR_NO_SPUR == bb_spur) {
1816 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1817 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1818 return;
1819 } else {
1820 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1821 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1822 }
1823
1824 bin = bb_spur * 320;
1825
1826 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1827
1828 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1829 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1830 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1831 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1832 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1833
1834 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1835 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1836 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1837 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1838 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1839 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1840
1841 if (IS_CHAN_HT40(chan)) {
1842 if (bb_spur < 0) {
1843 spur_subchannel_sd = 1;
1844 bb_spur_off = bb_spur + 10;
1845 } else {
1846 spur_subchannel_sd = 0;
1847 bb_spur_off = bb_spur - 10;
1848 }
1849 } else {
1850 spur_subchannel_sd = 0;
1851 bb_spur_off = bb_spur;
1852 }
1853
1854 if (IS_CHAN_HT40(chan))
1855 spur_delta_phase =
1856 ((bb_spur * 262144) /
1857 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1858 else
1859 spur_delta_phase =
1860 ((bb_spur * 524288) /
1861 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1862
1863 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1864 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1865
1866 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1867 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1868 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1869 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1870
1871 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1872 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1873
1874 cur_bin = -6000;
1875 upper = bin + 100;
1876 lower = bin - 100;
1877
1878 for (i = 0; i < 4; i++) {
1879 int pilot_mask = 0;
1880 int chan_mask = 0;
1881 int bp = 0;
1882 for (bp = 0; bp < 30; bp++) {
1883 if ((cur_bin > lower) && (cur_bin < upper)) {
1884 pilot_mask = pilot_mask | 0x1 << bp;
1885 chan_mask = chan_mask | 0x1 << bp;
1886 }
1887 cur_bin += 100;
1888 }
1889 cur_bin += inc[i];
1890 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1891 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1892 }
1893
1894 cur_vit_mask = 6100;
1895 upper = bin + 120;
1896 lower = bin - 120;
1897
1898 for (i = 0; i < 123; i++) {
1899 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1900
1901 /* workaround for gcc bug #37014 */
1902 volatile int tmp_v = abs(cur_vit_mask - bin);
1903
1904 if (tmp_v < 75)
1905 mask_amt = 1;
1906 else
1907 mask_amt = 0;
1908 if (cur_vit_mask < 0)
1909 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1910 else
1911 mask_p[cur_vit_mask / 100] = mask_amt;
1912 }
1913 cur_vit_mask -= 100;
1914 }
1915
1916 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1917 | (mask_m[48] << 26) | (mask_m[49] << 24)
1918 | (mask_m[50] << 22) | (mask_m[51] << 20)
1919 | (mask_m[52] << 18) | (mask_m[53] << 16)
1920 | (mask_m[54] << 14) | (mask_m[55] << 12)
1921 | (mask_m[56] << 10) | (mask_m[57] << 8)
1922 | (mask_m[58] << 6) | (mask_m[59] << 4)
1923 | (mask_m[60] << 2) | (mask_m[61] << 0);
1924 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1925 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1926
1927 tmp_mask = (mask_m[31] << 28)
1928 | (mask_m[32] << 26) | (mask_m[33] << 24)
1929 | (mask_m[34] << 22) | (mask_m[35] << 20)
1930 | (mask_m[36] << 18) | (mask_m[37] << 16)
1931 | (mask_m[48] << 14) | (mask_m[39] << 12)
1932 | (mask_m[40] << 10) | (mask_m[41] << 8)
1933 | (mask_m[42] << 6) | (mask_m[43] << 4)
1934 | (mask_m[44] << 2) | (mask_m[45] << 0);
1935 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1936 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1937
1938 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1939 | (mask_m[18] << 26) | (mask_m[18] << 24)
1940 | (mask_m[20] << 22) | (mask_m[20] << 20)
1941 | (mask_m[22] << 18) | (mask_m[22] << 16)
1942 | (mask_m[24] << 14) | (mask_m[24] << 12)
1943 | (mask_m[25] << 10) | (mask_m[26] << 8)
1944 | (mask_m[27] << 6) | (mask_m[28] << 4)
1945 | (mask_m[29] << 2) | (mask_m[30] << 0);
1946 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1947 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1948
1949 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1950 | (mask_m[2] << 26) | (mask_m[3] << 24)
1951 | (mask_m[4] << 22) | (mask_m[5] << 20)
1952 | (mask_m[6] << 18) | (mask_m[7] << 16)
1953 | (mask_m[8] << 14) | (mask_m[9] << 12)
1954 | (mask_m[10] << 10) | (mask_m[11] << 8)
1955 | (mask_m[12] << 6) | (mask_m[13] << 4)
1956 | (mask_m[14] << 2) | (mask_m[15] << 0);
1957 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1958 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1959
1960 tmp_mask = (mask_p[15] << 28)
1961 | (mask_p[14] << 26) | (mask_p[13] << 24)
1962 | (mask_p[12] << 22) | (mask_p[11] << 20)
1963 | (mask_p[10] << 18) | (mask_p[9] << 16)
1964 | (mask_p[8] << 14) | (mask_p[7] << 12)
1965 | (mask_p[6] << 10) | (mask_p[5] << 8)
1966 | (mask_p[4] << 6) | (mask_p[3] << 4)
1967 | (mask_p[2] << 2) | (mask_p[1] << 0);
1968 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1969 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1970
1971 tmp_mask = (mask_p[30] << 28)
1972 | (mask_p[29] << 26) | (mask_p[28] << 24)
1973 | (mask_p[27] << 22) | (mask_p[26] << 20)
1974 | (mask_p[25] << 18) | (mask_p[24] << 16)
1975 | (mask_p[23] << 14) | (mask_p[22] << 12)
1976 | (mask_p[21] << 10) | (mask_p[20] << 8)
1977 | (mask_p[19] << 6) | (mask_p[18] << 4)
1978 | (mask_p[17] << 2) | (mask_p[16] << 0);
1979 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1980 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1981
1982 tmp_mask = (mask_p[45] << 28)
1983 | (mask_p[44] << 26) | (mask_p[43] << 24)
1984 | (mask_p[42] << 22) | (mask_p[41] << 20)
1985 | (mask_p[40] << 18) | (mask_p[39] << 16)
1986 | (mask_p[38] << 14) | (mask_p[37] << 12)
1987 | (mask_p[36] << 10) | (mask_p[35] << 8)
1988 | (mask_p[34] << 6) | (mask_p[33] << 4)
1989 | (mask_p[32] << 2) | (mask_p[31] << 0);
1990 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1991 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1992
1993 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1994 | (mask_p[59] << 26) | (mask_p[58] << 24)
1995 | (mask_p[57] << 22) | (mask_p[56] << 20)
1996 | (mask_p[55] << 18) | (mask_p[54] << 16)
1997 | (mask_p[53] << 14) | (mask_p[52] << 12)
1998 | (mask_p[51] << 10) | (mask_p[50] << 8)
1999 | (mask_p[49] << 6) | (mask_p[48] << 4)
2000 | (mask_p[47] << 2) | (mask_p[46] << 0);
2001 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2002 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2003 }
2004
2005 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
2006 {
2007 int bb_spur = AR_NO_SPUR;
2008 int bin, cur_bin;
2009 int spur_freq_sd;
2010 int spur_delta_phase;
2011 int denominator;
2012 int upper, lower, cur_vit_mask;
2013 int tmp, new;
2014 int i;
2015 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2016 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2017 };
2018 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2019 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2020 };
2021 int inc[4] = { 0, 100, 0, 0 };
2022
2023 int8_t mask_m[123];
2024 int8_t mask_p[123];
2025 int8_t mask_amt;
2026 int tmp_mask;
2027 int cur_bb_spur;
2028 bool is2GHz = IS_CHAN_2GHZ(chan);
2029
2030 memset(&mask_m, 0, sizeof(int8_t) * 123);
2031 memset(&mask_p, 0, sizeof(int8_t) * 123);
2032
2033 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2034 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2035 if (AR_NO_SPUR == cur_bb_spur)
2036 break;
2037 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2038 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2039 bb_spur = cur_bb_spur;
2040 break;
2041 }
2042 }
2043
2044 if (AR_NO_SPUR == bb_spur)
2045 return;
2046
2047 bin = bb_spur * 32;
2048
2049 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2050 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2051 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2052 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2053 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2054
2055 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2056
2057 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2058 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2059 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2060 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2061 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2062 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2063
2064 spur_delta_phase = ((bb_spur * 524288) / 100) &
2065 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2066
2067 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2068 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2069
2070 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2071 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2072 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2073 REG_WRITE(ah, AR_PHY_TIMING11, new);
2074
2075 cur_bin = -6000;
2076 upper = bin + 100;
2077 lower = bin - 100;
2078
2079 for (i = 0; i < 4; i++) {
2080 int pilot_mask = 0;
2081 int chan_mask = 0;
2082 int bp = 0;
2083 for (bp = 0; bp < 30; bp++) {
2084 if ((cur_bin > lower) && (cur_bin < upper)) {
2085 pilot_mask = pilot_mask | 0x1 << bp;
2086 chan_mask = chan_mask | 0x1 << bp;
2087 }
2088 cur_bin += 100;
2089 }
2090 cur_bin += inc[i];
2091 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2092 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2093 }
2094
2095 cur_vit_mask = 6100;
2096 upper = bin + 120;
2097 lower = bin - 120;
2098
2099 for (i = 0; i < 123; i++) {
2100 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2101
2102 /* workaround for gcc bug #37014 */
2103 volatile int tmp_v = abs(cur_vit_mask - bin);
2104
2105 if (tmp_v < 75)
2106 mask_amt = 1;
2107 else
2108 mask_amt = 0;
2109 if (cur_vit_mask < 0)
2110 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2111 else
2112 mask_p[cur_vit_mask / 100] = mask_amt;
2113 }
2114 cur_vit_mask -= 100;
2115 }
2116
2117 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2118 | (mask_m[48] << 26) | (mask_m[49] << 24)
2119 | (mask_m[50] << 22) | (mask_m[51] << 20)
2120 | (mask_m[52] << 18) | (mask_m[53] << 16)
2121 | (mask_m[54] << 14) | (mask_m[55] << 12)
2122 | (mask_m[56] << 10) | (mask_m[57] << 8)
2123 | (mask_m[58] << 6) | (mask_m[59] << 4)
2124 | (mask_m[60] << 2) | (mask_m[61] << 0);
2125 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2126 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2127
2128 tmp_mask = (mask_m[31] << 28)
2129 | (mask_m[32] << 26) | (mask_m[33] << 24)
2130 | (mask_m[34] << 22) | (mask_m[35] << 20)
2131 | (mask_m[36] << 18) | (mask_m[37] << 16)
2132 | (mask_m[48] << 14) | (mask_m[39] << 12)
2133 | (mask_m[40] << 10) | (mask_m[41] << 8)
2134 | (mask_m[42] << 6) | (mask_m[43] << 4)
2135 | (mask_m[44] << 2) | (mask_m[45] << 0);
2136 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2137 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2138
2139 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2140 | (mask_m[18] << 26) | (mask_m[18] << 24)
2141 | (mask_m[20] << 22) | (mask_m[20] << 20)
2142 | (mask_m[22] << 18) | (mask_m[22] << 16)
2143 | (mask_m[24] << 14) | (mask_m[24] << 12)
2144 | (mask_m[25] << 10) | (mask_m[26] << 8)
2145 | (mask_m[27] << 6) | (mask_m[28] << 4)
2146 | (mask_m[29] << 2) | (mask_m[30] << 0);
2147 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2148 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2149
2150 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2151 | (mask_m[2] << 26) | (mask_m[3] << 24)
2152 | (mask_m[4] << 22) | (mask_m[5] << 20)
2153 | (mask_m[6] << 18) | (mask_m[7] << 16)
2154 | (mask_m[8] << 14) | (mask_m[9] << 12)
2155 | (mask_m[10] << 10) | (mask_m[11] << 8)
2156 | (mask_m[12] << 6) | (mask_m[13] << 4)
2157 | (mask_m[14] << 2) | (mask_m[15] << 0);
2158 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2159 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2160
2161 tmp_mask = (mask_p[15] << 28)
2162 | (mask_p[14] << 26) | (mask_p[13] << 24)
2163 | (mask_p[12] << 22) | (mask_p[11] << 20)
2164 | (mask_p[10] << 18) | (mask_p[9] << 16)
2165 | (mask_p[8] << 14) | (mask_p[7] << 12)
2166 | (mask_p[6] << 10) | (mask_p[5] << 8)
2167 | (mask_p[4] << 6) | (mask_p[3] << 4)
2168 | (mask_p[2] << 2) | (mask_p[1] << 0);
2169 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2170 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2171
2172 tmp_mask = (mask_p[30] << 28)
2173 | (mask_p[29] << 26) | (mask_p[28] << 24)
2174 | (mask_p[27] << 22) | (mask_p[26] << 20)
2175 | (mask_p[25] << 18) | (mask_p[24] << 16)
2176 | (mask_p[23] << 14) | (mask_p[22] << 12)
2177 | (mask_p[21] << 10) | (mask_p[20] << 8)
2178 | (mask_p[19] << 6) | (mask_p[18] << 4)
2179 | (mask_p[17] << 2) | (mask_p[16] << 0);
2180 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2181 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2182
2183 tmp_mask = (mask_p[45] << 28)
2184 | (mask_p[44] << 26) | (mask_p[43] << 24)
2185 | (mask_p[42] << 22) | (mask_p[41] << 20)
2186 | (mask_p[40] << 18) | (mask_p[39] << 16)
2187 | (mask_p[38] << 14) | (mask_p[37] << 12)
2188 | (mask_p[36] << 10) | (mask_p[35] << 8)
2189 | (mask_p[34] << 6) | (mask_p[33] << 4)
2190 | (mask_p[32] << 2) | (mask_p[31] << 0);
2191 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2192 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2193
2194 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2195 | (mask_p[59] << 26) | (mask_p[58] << 24)
2196 | (mask_p[57] << 22) | (mask_p[56] << 20)
2197 | (mask_p[55] << 18) | (mask_p[54] << 16)
2198 | (mask_p[53] << 14) | (mask_p[52] << 12)
2199 | (mask_p[51] << 10) | (mask_p[50] << 8)
2200 | (mask_p[49] << 6) | (mask_p[48] << 4)
2201 | (mask_p[47] << 2) | (mask_p[46] << 0);
2202 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2203 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2204 }
2205
2206 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2207 bool bChannelChange)
2208 {
2209 u32 saveLedState;
2210 struct ath_softc *sc = ah->ah_sc;
2211 struct ath9k_channel *curchan = ah->curchan;
2212 u32 saveDefAntenna;
2213 u32 macStaId1;
2214 int i, rx_chainmask, r;
2215
2216 ah->extprotspacing = sc->ht_extprotspacing;
2217 ah->txchainmask = sc->tx_chainmask;
2218 ah->rxchainmask = sc->rx_chainmask;
2219
2220 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2221 return -EIO;
2222
2223 if (curchan)
2224 ath9k_hw_getnf(ah, curchan);
2225
2226 if (bChannelChange &&
2227 (ah->chip_fullsleep != true) &&
2228 (ah->curchan != NULL) &&
2229 (chan->channel != ah->curchan->channel) &&
2230 ((chan->channelFlags & CHANNEL_ALL) ==
2231 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2232 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2233 !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2234
2235 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2236 ath9k_hw_loadnf(ah, ah->curchan);
2237 ath9k_hw_start_nfcal(ah);
2238 return 0;
2239 }
2240 }
2241
2242 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2243 if (saveDefAntenna == 0)
2244 saveDefAntenna = 1;
2245
2246 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2247
2248 saveLedState = REG_READ(ah, AR_CFG_LED) &
2249 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2250 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2251
2252 ath9k_hw_mark_phy_inactive(ah);
2253
2254 if (!ath9k_hw_chip_reset(ah, chan)) {
2255 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n");
2256 return -EINVAL;
2257 }
2258
2259 if (AR_SREV_9280_10_OR_LATER(ah))
2260 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2261
2262 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2263 if (r)
2264 return r;
2265
2266 /* Setup MFP options for CCMP */
2267 if (AR_SREV_9280_20_OR_LATER(ah)) {
2268 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2269 * frames when constructing CCMP AAD. */
2270 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2271 0xc7ff);
2272 ah->sw_mgmt_crypto = false;
2273 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2274 /* Disable hardware crypto for management frames */
2275 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2276 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2277 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2278 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2279 ah->sw_mgmt_crypto = true;
2280 } else
2281 ah->sw_mgmt_crypto = true;
2282
2283 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2284 ath9k_hw_set_delta_slope(ah, chan);
2285
2286 if (AR_SREV_9280_10_OR_LATER(ah))
2287 ath9k_hw_9280_spur_mitigate(ah, chan);
2288 else
2289 ath9k_hw_spur_mitigate(ah, chan);
2290
2291 ah->eep_ops->set_board_values(ah, chan);
2292
2293 ath9k_hw_decrease_chain_power(ah, chan);
2294
2295 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2296 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2297 | macStaId1
2298 | AR_STA_ID1_RTS_USE_DEF
2299 | (ah->config.
2300 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2301 | ah->sta_id1_defaults);
2302 ath9k_hw_set_operating_mode(ah, ah->opmode);
2303
2304 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2305 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2306
2307 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2308
2309 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2310 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2311 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2312
2313 REG_WRITE(ah, AR_ISR, ~0);
2314
2315 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2316
2317 if (AR_SREV_9280_10_OR_LATER(ah)) {
2318 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
2319 return -EIO;
2320 } else {
2321 if (!(ath9k_hw_set_channel(ah, chan)))
2322 return -EIO;
2323 }
2324
2325 for (i = 0; i < AR_NUM_DCU; i++)
2326 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2327
2328 ah->intr_txqs = 0;
2329 for (i = 0; i < ah->caps.total_queues; i++)
2330 ath9k_hw_resettxqueue(ah, i);
2331
2332 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2333 ath9k_hw_init_qos(ah);
2334
2335 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2336 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2337 ath9k_enable_rfkill(ah);
2338 #endif
2339 ath9k_hw_init_user_settings(ah);
2340
2341 REG_WRITE(ah, AR_STA_ID1,
2342 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2343
2344 ath9k_hw_set_dma(ah);
2345
2346 REG_WRITE(ah, AR_OBS, 8);
2347
2348 if (ah->config.intr_mitigation) {
2349 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2350 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2351 }
2352
2353 ath9k_hw_init_bb(ah, chan);
2354
2355 if (!ath9k_hw_init_cal(ah, chan))
2356 return -EIO;;
2357
2358 rx_chainmask = ah->rxchainmask;
2359 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2360 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2361 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2362 }
2363
2364 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2365
2366 if (AR_SREV_9100(ah)) {
2367 u32 mask;
2368 mask = REG_READ(ah, AR_CFG);
2369 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2370 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2371 "CFG Byte Swap Set 0x%x\n", mask);
2372 } else {
2373 mask =
2374 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2375 REG_WRITE(ah, AR_CFG, mask);
2376 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2377 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2378 }
2379 } else {
2380 #ifdef __BIG_ENDIAN
2381 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2382 #endif
2383 }
2384
2385 return 0;
2386 }
2387
2388 /************************/
2389 /* Key Cache Management */
2390 /************************/
2391
2392 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2393 {
2394 u32 keyType;
2395
2396 if (entry >= ah->caps.keycache_size) {
2397 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2398 "keychache entry %u out of range\n", entry);
2399 return false;
2400 }
2401
2402 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2403
2404 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2405 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2406 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2407 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2408 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2409 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2410 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2411 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2412
2413 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2414 u16 micentry = entry + 64;
2415
2416 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2417 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2418 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2419 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2420
2421 }
2422
2423 if (ah->curchan == NULL)
2424 return true;
2425
2426 return true;
2427 }
2428
2429 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2430 {
2431 u32 macHi, macLo;
2432
2433 if (entry >= ah->caps.keycache_size) {
2434 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2435 "keychache entry %u out of range\n", entry);
2436 return false;
2437 }
2438
2439 if (mac != NULL) {
2440 macHi = (mac[5] << 8) | mac[4];
2441 macLo = (mac[3] << 24) |
2442 (mac[2] << 16) |
2443 (mac[1] << 8) |
2444 mac[0];
2445 macLo >>= 1;
2446 macLo |= (macHi & 1) << 31;
2447 macHi >>= 1;
2448 } else {
2449 macLo = macHi = 0;
2450 }
2451 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2452 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2453
2454 return true;
2455 }
2456
2457 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2458 const struct ath9k_keyval *k,
2459 const u8 *mac)
2460 {
2461 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2462 u32 key0, key1, key2, key3, key4;
2463 u32 keyType;
2464
2465 if (entry >= pCap->keycache_size) {
2466 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2467 "keycache entry %u out of range\n", entry);
2468 return false;
2469 }
2470
2471 switch (k->kv_type) {
2472 case ATH9K_CIPHER_AES_OCB:
2473 keyType = AR_KEYTABLE_TYPE_AES;
2474 break;
2475 case ATH9K_CIPHER_AES_CCM:
2476 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2477 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2478 "AES-CCM not supported by mac rev 0x%x\n",
2479 ah->hw_version.macRev);
2480 return false;
2481 }
2482 keyType = AR_KEYTABLE_TYPE_CCM;
2483 break;
2484 case ATH9K_CIPHER_TKIP:
2485 keyType = AR_KEYTABLE_TYPE_TKIP;
2486 if (ATH9K_IS_MIC_ENABLED(ah)
2487 && entry + 64 >= pCap->keycache_size) {
2488 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2489 "entry %u inappropriate for TKIP\n", entry);
2490 return false;
2491 }
2492 break;
2493 case ATH9K_CIPHER_WEP:
2494 if (k->kv_len < LEN_WEP40) {
2495 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2496 "WEP key length %u too small\n", k->kv_len);
2497 return false;
2498 }
2499 if (k->kv_len <= LEN_WEP40)
2500 keyType = AR_KEYTABLE_TYPE_40;
2501 else if (k->kv_len <= LEN_WEP104)
2502 keyType = AR_KEYTABLE_TYPE_104;
2503 else
2504 keyType = AR_KEYTABLE_TYPE_128;
2505 break;
2506 case ATH9K_CIPHER_CLR:
2507 keyType = AR_KEYTABLE_TYPE_CLR;
2508 break;
2509 default:
2510 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2511 "cipher %u not supported\n", k->kv_type);
2512 return false;
2513 }
2514
2515 key0 = get_unaligned_le32(k->kv_val + 0);
2516 key1 = get_unaligned_le16(k->kv_val + 4);
2517 key2 = get_unaligned_le32(k->kv_val + 6);
2518 key3 = get_unaligned_le16(k->kv_val + 10);
2519 key4 = get_unaligned_le32(k->kv_val + 12);
2520 if (k->kv_len <= LEN_WEP104)
2521 key4 &= 0xff;
2522
2523 /*
2524 * Note: Key cache registers access special memory area that requires
2525 * two 32-bit writes to actually update the values in the internal
2526 * memory. Consequently, the exact order and pairs used here must be
2527 * maintained.
2528 */
2529
2530 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2531 u16 micentry = entry + 64;
2532
2533 /*
2534 * Write inverted key[47:0] first to avoid Michael MIC errors
2535 * on frames that could be sent or received at the same time.
2536 * The correct key will be written in the end once everything
2537 * else is ready.
2538 */
2539 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2540 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2541
2542 /* Write key[95:48] */
2543 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2544 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2545
2546 /* Write key[127:96] and key type */
2547 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2548 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2549
2550 /* Write MAC address for the entry */
2551 (void) ath9k_hw_keysetmac(ah, entry, mac);
2552
2553 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2554 /*
2555 * TKIP uses two key cache entries:
2556 * Michael MIC TX/RX keys in the same key cache entry
2557 * (idx = main index + 64):
2558 * key0 [31:0] = RX key [31:0]
2559 * key1 [15:0] = TX key [31:16]
2560 * key1 [31:16] = reserved
2561 * key2 [31:0] = RX key [63:32]
2562 * key3 [15:0] = TX key [15:0]
2563 * key3 [31:16] = reserved
2564 * key4 [31:0] = TX key [63:32]
2565 */
2566 u32 mic0, mic1, mic2, mic3, mic4;
2567
2568 mic0 = get_unaligned_le32(k->kv_mic + 0);
2569 mic2 = get_unaligned_le32(k->kv_mic + 4);
2570 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2571 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2572 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2573
2574 /* Write RX[31:0] and TX[31:16] */
2575 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2576 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2577
2578 /* Write RX[63:32] and TX[15:0] */
2579 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2580 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2581
2582 /* Write TX[63:32] and keyType(reserved) */
2583 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2584 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2585 AR_KEYTABLE_TYPE_CLR);
2586
2587 } else {
2588 /*
2589 * TKIP uses four key cache entries (two for group
2590 * keys):
2591 * Michael MIC TX/RX keys are in different key cache
2592 * entries (idx = main index + 64 for TX and
2593 * main index + 32 + 96 for RX):
2594 * key0 [31:0] = TX/RX MIC key [31:0]
2595 * key1 [31:0] = reserved
2596 * key2 [31:0] = TX/RX MIC key [63:32]
2597 * key3 [31:0] = reserved
2598 * key4 [31:0] = reserved
2599 *
2600 * Upper layer code will call this function separately
2601 * for TX and RX keys when these registers offsets are
2602 * used.
2603 */
2604 u32 mic0, mic2;
2605
2606 mic0 = get_unaligned_le32(k->kv_mic + 0);
2607 mic2 = get_unaligned_le32(k->kv_mic + 4);
2608
2609 /* Write MIC key[31:0] */
2610 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2611 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2612
2613 /* Write MIC key[63:32] */
2614 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2615 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2616
2617 /* Write TX[63:32] and keyType(reserved) */
2618 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2619 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2620 AR_KEYTABLE_TYPE_CLR);
2621 }
2622
2623 /* MAC address registers are reserved for the MIC entry */
2624 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2625 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2626
2627 /*
2628 * Write the correct (un-inverted) key[47:0] last to enable
2629 * TKIP now that all other registers are set with correct
2630 * values.
2631 */
2632 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2633 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2634 } else {
2635 /* Write key[47:0] */
2636 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2637 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2638
2639 /* Write key[95:48] */
2640 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2641 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2642
2643 /* Write key[127:96] and key type */
2644 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2645 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2646
2647 /* Write MAC address for the entry */
2648 (void) ath9k_hw_keysetmac(ah, entry, mac);
2649 }
2650
2651 return true;
2652 }
2653
2654 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2655 {
2656 if (entry < ah->caps.keycache_size) {
2657 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2658 if (val & AR_KEYTABLE_VALID)
2659 return true;
2660 }
2661 return false;
2662 }
2663
2664 /******************************/
2665 /* Power Management (Chipset) */
2666 /******************************/
2667
2668 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2669 {
2670 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2671 if (setChip) {
2672 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2673 AR_RTC_FORCE_WAKE_EN);
2674 if (!AR_SREV_9100(ah))
2675 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2676
2677 REG_CLR_BIT(ah, (AR_RTC_RESET),
2678 AR_RTC_RESET_EN);
2679 }
2680 }
2681
2682 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2683 {
2684 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2685 if (setChip) {
2686 struct ath9k_hw_capabilities *pCap = &ah->caps;
2687
2688 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2689 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2690 AR_RTC_FORCE_WAKE_ON_INT);
2691 } else {
2692 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2693 AR_RTC_FORCE_WAKE_EN);
2694 }
2695 }
2696 }
2697
2698 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2699 {
2700 u32 val;
2701 int i;
2702
2703 if (setChip) {
2704 if ((REG_READ(ah, AR_RTC_STATUS) &
2705 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2706 if (ath9k_hw_set_reset_reg(ah,
2707 ATH9K_RESET_POWER_ON) != true) {
2708 return false;
2709 }
2710 }
2711 if (AR_SREV_9100(ah))
2712 REG_SET_BIT(ah, AR_RTC_RESET,
2713 AR_RTC_RESET_EN);
2714
2715 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2716 AR_RTC_FORCE_WAKE_EN);
2717 udelay(50);
2718
2719 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2720 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2721 if (val == AR_RTC_STATUS_ON)
2722 break;
2723 udelay(50);
2724 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2725 AR_RTC_FORCE_WAKE_EN);
2726 }
2727 if (i == 0) {
2728 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2729 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2730 return false;
2731 }
2732 }
2733
2734 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2735
2736 return true;
2737 }
2738
2739 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2740 {
2741 int status = true, setChip = true;
2742 static const char *modes[] = {
2743 "AWAKE",
2744 "FULL-SLEEP",
2745 "NETWORK SLEEP",
2746 "UNDEFINED"
2747 };
2748
2749 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n",
2750 modes[ah->power_mode], modes[mode]);
2751
2752 switch (mode) {
2753 case ATH9K_PM_AWAKE:
2754 status = ath9k_hw_set_power_awake(ah, setChip);
2755 break;
2756 case ATH9K_PM_FULL_SLEEP:
2757 ath9k_set_power_sleep(ah, setChip);
2758 ah->chip_fullsleep = true;
2759 break;
2760 case ATH9K_PM_NETWORK_SLEEP:
2761 ath9k_set_power_network_sleep(ah, setChip);
2762 break;
2763 default:
2764 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2765 "Unknown power mode %u\n", mode);
2766 return false;
2767 }
2768 ah->power_mode = mode;
2769
2770 return status;
2771 }
2772
2773 /*
2774 * Helper for ASPM support.
2775 *
2776 * Disable PLL when in L0s as well as receiver clock when in L1.
2777 * This power saving option must be enabled through the SerDes.
2778 *
2779 * Programming the SerDes must go through the same 288 bit serial shift
2780 * register as the other analog registers. Hence the 9 writes.
2781 */
2782 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2783 {
2784 u8 i;
2785
2786 if (ah->is_pciexpress != true)
2787 return;
2788
2789 /* Do not touch SerDes registers */
2790 if (ah->config.pcie_powersave_enable == 2)
2791 return;
2792
2793 /* Nothing to do on restore for 11N */
2794 if (restore)
2795 return;
2796
2797 if (AR_SREV_9280_20_OR_LATER(ah)) {
2798 /*
2799 * AR9280 2.0 or later chips use SerDes values from the
2800 * initvals.h initialized depending on chipset during
2801 * ath9k_hw_do_attach()
2802 */
2803 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2804 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2805 INI_RA(&ah->iniPcieSerdes, i, 1));
2806 }
2807 } else if (AR_SREV_9280(ah) &&
2808 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2809 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2810 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2811
2812 /* RX shut off when elecidle is asserted */
2813 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2814 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2815 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2816
2817 /* Shut off CLKREQ active in L1 */
2818 if (ah->config.pcie_clock_req)
2819 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2820 else
2821 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2822
2823 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2824 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2825 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2826
2827 /* Load the new settings */
2828 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2829
2830 } else {
2831 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2832 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2833
2834 /* RX shut off when elecidle is asserted */
2835 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2836 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2837 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2838
2839 /*
2840 * Ignore ah->ah_config.pcie_clock_req setting for
2841 * pre-AR9280 11n
2842 */
2843 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2844
2845 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2846 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2847 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2848
2849 /* Load the new settings */
2850 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2851 }
2852
2853 udelay(1000);
2854
2855 /* set bit 19 to allow forcing of pcie core into L1 state */
2856 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2857
2858 /* Several PCIe massages to ensure proper behaviour */
2859 if (ah->config.pcie_waen) {
2860 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2861 } else {
2862 if (AR_SREV_9285(ah))
2863 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2864 /*
2865 * On AR9280 chips bit 22 of 0x4004 needs to be set to
2866 * otherwise card may disappear.
2867 */
2868 else if (AR_SREV_9280(ah))
2869 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2870 else
2871 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2872 }
2873 }
2874
2875 /**********************/
2876 /* Interrupt Handling */
2877 /**********************/
2878
2879 bool ath9k_hw_intrpend(struct ath_hw *ah)
2880 {
2881 u32 host_isr;
2882
2883 if (AR_SREV_9100(ah))
2884 return true;
2885
2886 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2887 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2888 return true;
2889
2890 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2891 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2892 && (host_isr != AR_INTR_SPURIOUS))
2893 return true;
2894
2895 return false;
2896 }
2897
2898 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2899 {
2900 u32 isr = 0;
2901 u32 mask2 = 0;
2902 struct ath9k_hw_capabilities *pCap = &ah->caps;
2903 u32 sync_cause = 0;
2904 bool fatal_int = false;
2905
2906 if (!AR_SREV_9100(ah)) {
2907 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2908 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2909 == AR_RTC_STATUS_ON) {
2910 isr = REG_READ(ah, AR_ISR);
2911 }
2912 }
2913
2914 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2915 AR_INTR_SYNC_DEFAULT;
2916
2917 *masked = 0;
2918
2919 if (!isr && !sync_cause)
2920 return false;
2921 } else {
2922 *masked = 0;
2923 isr = REG_READ(ah, AR_ISR);
2924 }
2925
2926 if (isr) {
2927 if (isr & AR_ISR_BCNMISC) {
2928 u32 isr2;
2929 isr2 = REG_READ(ah, AR_ISR_S2);
2930 if (isr2 & AR_ISR_S2_TIM)
2931 mask2 |= ATH9K_INT_TIM;
2932 if (isr2 & AR_ISR_S2_DTIM)
2933 mask2 |= ATH9K_INT_DTIM;
2934 if (isr2 & AR_ISR_S2_DTIMSYNC)
2935 mask2 |= ATH9K_INT_DTIMSYNC;
2936 if (isr2 & (AR_ISR_S2_CABEND))
2937 mask2 |= ATH9K_INT_CABEND;
2938 if (isr2 & AR_ISR_S2_GTT)
2939 mask2 |= ATH9K_INT_GTT;
2940 if (isr2 & AR_ISR_S2_CST)
2941 mask2 |= ATH9K_INT_CST;
2942 if (isr2 & AR_ISR_S2_TSFOOR)
2943 mask2 |= ATH9K_INT_TSFOOR;
2944 }
2945
2946 isr = REG_READ(ah, AR_ISR_RAC);
2947 if (isr == 0xffffffff) {
2948 *masked = 0;
2949 return false;
2950 }
2951
2952 *masked = isr & ATH9K_INT_COMMON;
2953
2954 if (ah->config.intr_mitigation) {
2955 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2956 *masked |= ATH9K_INT_RX;
2957 }
2958
2959 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2960 *masked |= ATH9K_INT_RX;
2961 if (isr &
2962 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2963 AR_ISR_TXEOL)) {
2964 u32 s0_s, s1_s;
2965
2966 *masked |= ATH9K_INT_TX;
2967
2968 s0_s = REG_READ(ah, AR_ISR_S0_S);
2969 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2970 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2971
2972 s1_s = REG_READ(ah, AR_ISR_S1_S);
2973 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2974 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2975 }
2976
2977 if (isr & AR_ISR_RXORN) {
2978 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2979 "receive FIFO overrun interrupt\n");
2980 }
2981
2982 if (!AR_SREV_9100(ah)) {
2983 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2984 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2985 if (isr5 & AR_ISR_S5_TIM_TIMER)
2986 *masked |= ATH9K_INT_TIM_TIMER;
2987 }
2988 }
2989
2990 *masked |= mask2;
2991 }
2992
2993 if (AR_SREV_9100(ah))
2994 return true;
2995
2996 if (sync_cause) {
2997 fatal_int =
2998 (sync_cause &
2999 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
3000 ? true : false;
3001
3002 if (fatal_int) {
3003 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3004 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3005 "received PCI FATAL interrupt\n");
3006 }
3007 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3008 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3009 "received PCI PERR interrupt\n");
3010 }
3011 *masked |= ATH9K_INT_FATAL;
3012 }
3013 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3014 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3015 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3016 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3017 REG_WRITE(ah, AR_RC, 0);
3018 *masked |= ATH9K_INT_FATAL;
3019 }
3020 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3021 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3022 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3023 }
3024
3025 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3026 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3027 }
3028
3029 return true;
3030 }
3031
3032 enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah)
3033 {
3034 return ah->mask_reg;
3035 }
3036
3037 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3038 {
3039 u32 omask = ah->mask_reg;
3040 u32 mask, mask2;
3041 struct ath9k_hw_capabilities *pCap = &ah->caps;
3042
3043 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3044
3045 if (omask & ATH9K_INT_GLOBAL) {
3046 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
3047 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3048 (void) REG_READ(ah, AR_IER);
3049 if (!AR_SREV_9100(ah)) {
3050 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3051 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3052
3053 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3054 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3055 }
3056 }
3057
3058 mask = ints & ATH9K_INT_COMMON;
3059 mask2 = 0;
3060
3061 if (ints & ATH9K_INT_TX) {
3062 if (ah->txok_interrupt_mask)
3063 mask |= AR_IMR_TXOK;
3064 if (ah->txdesc_interrupt_mask)
3065 mask |= AR_IMR_TXDESC;
3066 if (ah->txerr_interrupt_mask)
3067 mask |= AR_IMR_TXERR;
3068 if (ah->txeol_interrupt_mask)
3069 mask |= AR_IMR_TXEOL;
3070 }
3071 if (ints & ATH9K_INT_RX) {
3072 mask |= AR_IMR_RXERR;
3073 if (ah->config.intr_mitigation)
3074 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3075 else
3076 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3077 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3078 mask |= AR_IMR_GENTMR;
3079 }
3080
3081 if (ints & (ATH9K_INT_BMISC)) {
3082 mask |= AR_IMR_BCNMISC;
3083 if (ints & ATH9K_INT_TIM)
3084 mask2 |= AR_IMR_S2_TIM;
3085 if (ints & ATH9K_INT_DTIM)
3086 mask2 |= AR_IMR_S2_DTIM;
3087 if (ints & ATH9K_INT_DTIMSYNC)
3088 mask2 |= AR_IMR_S2_DTIMSYNC;
3089 if (ints & ATH9K_INT_CABEND)
3090 mask2 |= AR_IMR_S2_CABEND;
3091 if (ints & ATH9K_INT_TSFOOR)
3092 mask2 |= AR_IMR_S2_TSFOOR;
3093 }
3094
3095 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3096 mask |= AR_IMR_BCNMISC;
3097 if (ints & ATH9K_INT_GTT)
3098 mask2 |= AR_IMR_S2_GTT;
3099 if (ints & ATH9K_INT_CST)
3100 mask2 |= AR_IMR_S2_CST;
3101 }
3102
3103 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3104 REG_WRITE(ah, AR_IMR, mask);
3105 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3106 AR_IMR_S2_DTIM |
3107 AR_IMR_S2_DTIMSYNC |
3108 AR_IMR_S2_CABEND |
3109 AR_IMR_S2_CABTO |
3110 AR_IMR_S2_TSFOOR |
3111 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3112 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3113 ah->mask_reg = ints;
3114
3115 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3116 if (ints & ATH9K_INT_TIM_TIMER)
3117 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3118 else
3119 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3120 }
3121
3122 if (ints & ATH9K_INT_GLOBAL) {
3123 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3124 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3125 if (!AR_SREV_9100(ah)) {
3126 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3127 AR_INTR_MAC_IRQ);
3128 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3129
3130
3131 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3132 AR_INTR_SYNC_DEFAULT);
3133 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3134 AR_INTR_SYNC_DEFAULT);
3135 }
3136 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3137 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3138 }
3139
3140 return omask;
3141 }
3142
3143 /*******************/
3144 /* Beacon Handling */
3145 /*******************/
3146
3147 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3148 {
3149 int flags = 0;
3150
3151 ah->beacon_interval = beacon_period;
3152
3153 switch (ah->opmode) {
3154 case NL80211_IFTYPE_STATION:
3155 case NL80211_IFTYPE_MONITOR:
3156 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3157 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3158 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3159 flags |= AR_TBTT_TIMER_EN;
3160 break;
3161 case NL80211_IFTYPE_ADHOC:
3162 case NL80211_IFTYPE_MESH_POINT:
3163 REG_SET_BIT(ah, AR_TXCFG,
3164 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3165 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3166 TU_TO_USEC(next_beacon +
3167 (ah->atim_window ? ah->
3168 atim_window : 1)));
3169 flags |= AR_NDP_TIMER_EN;
3170 case NL80211_IFTYPE_AP:
3171 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3172 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3173 TU_TO_USEC(next_beacon -
3174 ah->config.
3175 dma_beacon_response_time));
3176 REG_WRITE(ah, AR_NEXT_SWBA,
3177 TU_TO_USEC(next_beacon -
3178 ah->config.
3179 sw_beacon_response_time));
3180 flags |=
3181 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3182 break;
3183 default:
3184 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3185 "%s: unsupported opmode: %d\n",
3186 __func__, ah->opmode);
3187 return;
3188 break;
3189 }
3190
3191 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3192 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3193 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3194 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3195
3196 beacon_period &= ~ATH9K_BEACON_ENA;
3197 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3198 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3199 ath9k_hw_reset_tsf(ah);
3200 }
3201
3202 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3203 }
3204
3205 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3206 const struct ath9k_beacon_state *bs)
3207 {
3208 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3209 struct ath9k_hw_capabilities *pCap = &ah->caps;
3210
3211 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3212
3213 REG_WRITE(ah, AR_BEACON_PERIOD,
3214 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3215 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3216 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3217
3218 REG_RMW_FIELD(ah, AR_RSSI_THR,
3219 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3220
3221 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3222
3223 if (bs->bs_sleepduration > beaconintval)
3224 beaconintval = bs->bs_sleepduration;
3225
3226 dtimperiod = bs->bs_dtimperiod;
3227 if (bs->bs_sleepduration > dtimperiod)
3228 dtimperiod = bs->bs_sleepduration;
3229
3230 if (beaconintval == dtimperiod)
3231 nextTbtt = bs->bs_nextdtim;
3232 else
3233 nextTbtt = bs->bs_nexttbtt;
3234
3235 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3236 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3237 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3238 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3239
3240 REG_WRITE(ah, AR_NEXT_DTIM,
3241 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3242 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3243
3244 REG_WRITE(ah, AR_SLEEP1,
3245 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3246 | AR_SLEEP1_ASSUME_DTIM);
3247
3248 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3249 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3250 else
3251 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3252
3253 REG_WRITE(ah, AR_SLEEP2,
3254 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3255
3256 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3257 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3258
3259 REG_SET_BIT(ah, AR_TIMER_MODE,
3260 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3261 AR_DTIM_TIMER_EN);
3262
3263 /* TSF Out of Range Threshold */
3264 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3265 }
3266
3267 /*******************/
3268 /* HW Capabilities */
3269 /*******************/
3270
3271 void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3272 {
3273 struct ath9k_hw_capabilities *pCap = &ah->caps;
3274 u16 capField = 0, eeval;
3275
3276 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3277 ah->regulatory.current_rd = eeval;
3278
3279 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3280 if (AR_SREV_9285_10_OR_LATER(ah))
3281 eeval |= AR9285_RDEXT_DEFAULT;
3282 ah->regulatory.current_rd_ext = eeval;
3283
3284 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3285
3286 if (ah->opmode != NL80211_IFTYPE_AP &&
3287 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3288 if (ah->regulatory.current_rd == 0x64 ||
3289 ah->regulatory.current_rd == 0x65)
3290 ah->regulatory.current_rd += 5;
3291 else if (ah->regulatory.current_rd == 0x41)
3292 ah->regulatory.current_rd = 0x43;
3293 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3294 "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3295 }
3296
3297 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3298 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3299
3300 if (eeval & AR5416_OPFLAGS_11A) {
3301 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3302 if (ah->config.ht_enable) {
3303 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3304 set_bit(ATH9K_MODE_11NA_HT20,
3305 pCap->wireless_modes);
3306 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3307 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3308 pCap->wireless_modes);
3309 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3310 pCap->wireless_modes);
3311 }
3312 }
3313 }
3314
3315 if (eeval & AR5416_OPFLAGS_11G) {
3316 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3317 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3318 if (ah->config.ht_enable) {
3319 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3320 set_bit(ATH9K_MODE_11NG_HT20,
3321 pCap->wireless_modes);
3322 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3323 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3324 pCap->wireless_modes);
3325 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3326 pCap->wireless_modes);
3327 }
3328 }
3329 }
3330
3331 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3332 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3333 !(eeval & AR5416_OPFLAGS_11A))
3334 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3335 else
3336 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3337
3338 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3339 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3340
3341 pCap->low_2ghz_chan = 2312;
3342 pCap->high_2ghz_chan = 2732;
3343
3344 pCap->low_5ghz_chan = 4920;
3345 pCap->high_5ghz_chan = 6100;
3346
3347 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3348 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3349 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3350
3351 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3352 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3353 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3354
3355 if (ah->config.ht_enable)
3356 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3357 else
3358 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3359
3360 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3361 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3362 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3363 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3364
3365 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3366 pCap->total_queues =
3367 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3368 else
3369 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3370
3371 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3372 pCap->keycache_size =
3373 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3374 else
3375 pCap->keycache_size = AR_KEYTABLE_SIZE;
3376
3377 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3378 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3379
3380 if (AR_SREV_9285_10_OR_LATER(ah))
3381 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3382 else if (AR_SREV_9280_10_OR_LATER(ah))
3383 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3384 else
3385 pCap->num_gpio_pins = AR_NUM_GPIO;
3386
3387 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3388 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3389 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3390 } else {
3391 pCap->rts_aggr_limit = (8 * 1024);
3392 }
3393
3394 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3395
3396 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3397 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3398 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3399 ah->rfkill_gpio =
3400 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3401 ah->rfkill_polarity =
3402 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3403
3404 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3405 }
3406 #endif
3407
3408 if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3409 (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3410 (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3411 (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3412 (ah->hw_version.macVersion == AR_SREV_VERSION_9280) ||
3413 (ah->hw_version.macVersion == AR_SREV_VERSION_9285))
3414 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3415 else
3416 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3417
3418 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3419 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3420 else
3421 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3422
3423 if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3424 pCap->reg_cap =
3425 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3426 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3427 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3428 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3429 } else {
3430 pCap->reg_cap =
3431 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3432 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3433 }
3434
3435 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3436
3437 pCap->num_antcfg_5ghz =
3438 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3439 pCap->num_antcfg_2ghz =
3440 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3441
3442 if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3443 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3444 ah->btactive_gpio = 6;
3445 ah->wlanactive_gpio = 5;
3446 }
3447 }
3448
3449 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3450 u32 capability, u32 *result)
3451 {
3452 switch (type) {
3453 case ATH9K_CAP_CIPHER:
3454 switch (capability) {
3455 case ATH9K_CIPHER_AES_CCM:
3456 case ATH9K_CIPHER_AES_OCB:
3457 case ATH9K_CIPHER_TKIP:
3458 case ATH9K_CIPHER_WEP:
3459 case ATH9K_CIPHER_MIC:
3460 case ATH9K_CIPHER_CLR:
3461 return true;
3462 default:
3463 return false;
3464 }
3465 case ATH9K_CAP_TKIP_MIC:
3466 switch (capability) {
3467 case 0:
3468 return true;
3469 case 1:
3470 return (ah->sta_id1_defaults &
3471 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3472 false;
3473 }
3474 case ATH9K_CAP_TKIP_SPLIT:
3475 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3476 false : true;
3477 case ATH9K_CAP_DIVERSITY:
3478 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3479 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3480 true : false;
3481 case ATH9K_CAP_MCAST_KEYSRCH:
3482 switch (capability) {
3483 case 0:
3484 return true;
3485 case 1:
3486 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3487 return false;
3488 } else {
3489 return (ah->sta_id1_defaults &
3490 AR_STA_ID1_MCAST_KSRCH) ? true :
3491 false;
3492 }
3493 }
3494 return false;
3495 case ATH9K_CAP_TXPOW:
3496 switch (capability) {
3497 case 0:
3498 return 0;
3499 case 1:
3500 *result = ah->regulatory.power_limit;
3501 return 0;
3502 case 2:
3503 *result = ah->regulatory.max_power_level;
3504 return 0;
3505 case 3:
3506 *result = ah->regulatory.tp_scale;
3507 return 0;
3508 }
3509 return false;
3510 case ATH9K_CAP_DS:
3511 return (AR_SREV_9280_20_OR_LATER(ah) &&
3512 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3513 ? false : true;
3514 default:
3515 return false;
3516 }
3517 }
3518
3519 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3520 u32 capability, u32 setting, int *status)
3521 {
3522 u32 v;
3523
3524 switch (type) {
3525 case ATH9K_CAP_TKIP_MIC:
3526 if (setting)
3527 ah->sta_id1_defaults |=
3528 AR_STA_ID1_CRPT_MIC_ENABLE;
3529 else
3530 ah->sta_id1_defaults &=
3531 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3532 return true;
3533 case ATH9K_CAP_DIVERSITY:
3534 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3535 if (setting)
3536 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3537 else
3538 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3539 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3540 return true;
3541 case ATH9K_CAP_MCAST_KEYSRCH:
3542 if (setting)
3543 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3544 else
3545 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3546 return true;
3547 default:
3548 return false;
3549 }
3550 }
3551
3552 /****************************/
3553 /* GPIO / RFKILL / Antennae */
3554 /****************************/
3555
3556 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3557 u32 gpio, u32 type)
3558 {
3559 int addr;
3560 u32 gpio_shift, tmp;
3561
3562 if (gpio > 11)
3563 addr = AR_GPIO_OUTPUT_MUX3;
3564 else if (gpio > 5)
3565 addr = AR_GPIO_OUTPUT_MUX2;
3566 else
3567 addr = AR_GPIO_OUTPUT_MUX1;
3568
3569 gpio_shift = (gpio % 6) * 5;
3570
3571 if (AR_SREV_9280_20_OR_LATER(ah)
3572 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3573 REG_RMW(ah, addr, (type << gpio_shift),
3574 (0x1f << gpio_shift));
3575 } else {
3576 tmp = REG_READ(ah, addr);
3577 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3578 tmp &= ~(0x1f << gpio_shift);
3579 tmp |= (type << gpio_shift);
3580 REG_WRITE(ah, addr, tmp);
3581 }
3582 }
3583
3584 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3585 {
3586 u32 gpio_shift;
3587
3588 ASSERT(gpio < ah->caps.num_gpio_pins);
3589
3590 gpio_shift = gpio << 1;
3591
3592 REG_RMW(ah,
3593 AR_GPIO_OE_OUT,
3594 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3595 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3596 }
3597
3598 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3599 {
3600 #define MS_REG_READ(x, y) \
3601 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3602
3603 if (gpio >= ah->caps.num_gpio_pins)
3604 return 0xffffffff;
3605
3606 if (AR_SREV_9285_10_OR_LATER(ah))
3607 return MS_REG_READ(AR9285, gpio) != 0;
3608 else if (AR_SREV_9280_10_OR_LATER(ah))
3609 return MS_REG_READ(AR928X, gpio) != 0;
3610 else
3611 return MS_REG_READ(AR, gpio) != 0;
3612 }
3613
3614 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3615 u32 ah_signal_type)
3616 {
3617 u32 gpio_shift;
3618
3619 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3620
3621 gpio_shift = 2 * gpio;
3622
3623 REG_RMW(ah,
3624 AR_GPIO_OE_OUT,
3625 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3626 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3627 }
3628
3629 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3630 {
3631 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3632 AR_GPIO_BIT(gpio));
3633 }
3634
3635 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3636 void ath9k_enable_rfkill(struct ath_hw *ah)
3637 {
3638 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3639 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3640
3641 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3642 AR_GPIO_INPUT_MUX2_RFSILENT);
3643
3644 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3645 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3646 }
3647 #endif
3648
3649 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3650 {
3651 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3652 }
3653
3654 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3655 {
3656 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3657 }
3658
3659 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3660 enum ath9k_ant_setting settings,
3661 struct ath9k_channel *chan,
3662 u8 *tx_chainmask,
3663 u8 *rx_chainmask,
3664 u8 *antenna_cfgd)
3665 {
3666 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3667
3668 if (AR_SREV_9280(ah)) {
3669 if (!tx_chainmask_cfg) {
3670
3671 tx_chainmask_cfg = *tx_chainmask;
3672 rx_chainmask_cfg = *rx_chainmask;
3673 }
3674
3675 switch (settings) {
3676 case ATH9K_ANT_FIXED_A:
3677 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3678 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3679 *antenna_cfgd = true;
3680 break;
3681 case ATH9K_ANT_FIXED_B:
3682 if (ah->caps.tx_chainmask >
3683 ATH9K_ANTENNA1_CHAINMASK) {
3684 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3685 }
3686 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3687 *antenna_cfgd = true;
3688 break;
3689 case ATH9K_ANT_VARIABLE:
3690 *tx_chainmask = tx_chainmask_cfg;
3691 *rx_chainmask = rx_chainmask_cfg;
3692 *antenna_cfgd = true;
3693 break;
3694 default:
3695 break;
3696 }
3697 } else {
3698 ah->diversity_control = settings;
3699 }
3700
3701 return true;
3702 }
3703
3704 /*********************/
3705 /* General Operation */
3706 /*********************/
3707
3708 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3709 {
3710 u32 bits = REG_READ(ah, AR_RX_FILTER);
3711 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3712
3713 if (phybits & AR_PHY_ERR_RADAR)
3714 bits |= ATH9K_RX_FILTER_PHYRADAR;
3715 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3716 bits |= ATH9K_RX_FILTER_PHYERR;
3717
3718 return bits;
3719 }
3720
3721 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3722 {
3723 u32 phybits;
3724
3725 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3726 phybits = 0;
3727 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3728 phybits |= AR_PHY_ERR_RADAR;
3729 if (bits & ATH9K_RX_FILTER_PHYERR)
3730 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3731 REG_WRITE(ah, AR_PHY_ERR, phybits);
3732
3733 if (phybits)
3734 REG_WRITE(ah, AR_RXCFG,
3735 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3736 else
3737 REG_WRITE(ah, AR_RXCFG,
3738 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3739 }
3740
3741 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3742 {
3743 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3744 }
3745
3746 bool ath9k_hw_disable(struct ath_hw *ah)
3747 {
3748 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3749 return false;
3750
3751 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3752 }
3753
3754 bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3755 {
3756 struct ath9k_channel *chan = ah->curchan;
3757 struct ieee80211_channel *channel = chan->chan;
3758
3759 ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3760
3761 if (ah->eep_ops->set_txpower(ah, chan,
3762 ath9k_regd_get_ctl(&ah->regulatory, chan),
3763 channel->max_antenna_gain * 2,
3764 channel->max_power * 2,
3765 min((u32) MAX_RATE_POWER,
3766 (u32) ah->regulatory.power_limit)) != 0)
3767 return false;
3768
3769 return true;
3770 }
3771
3772 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3773 {
3774 memcpy(ah->macaddr, mac, ETH_ALEN);
3775 }
3776
3777 void ath9k_hw_setopmode(struct ath_hw *ah)
3778 {
3779 ath9k_hw_set_operating_mode(ah, ah->opmode);
3780 }
3781
3782 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3783 {
3784 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3785 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3786 }
3787
3788 void ath9k_hw_setbssidmask(struct ath_softc *sc)
3789 {
3790 REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3791 REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3792 }
3793
3794 void ath9k_hw_write_associd(struct ath_softc *sc)
3795 {
3796 REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3797 REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3798 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3799 }
3800
3801 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3802 {
3803 u64 tsf;
3804
3805 tsf = REG_READ(ah, AR_TSF_U32);
3806 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3807
3808 return tsf;
3809 }
3810
3811 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3812 {
3813 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3814 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3815 }
3816
3817 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3818 {
3819 int count;
3820
3821 count = 0;
3822 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3823 count++;
3824 if (count > 10) {
3825 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3826 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3827 break;
3828 }
3829 udelay(10);
3830 }
3831 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3832 }
3833
3834 bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3835 {
3836 if (setting)
3837 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3838 else
3839 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3840
3841 return true;
3842 }
3843
3844 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3845 {
3846 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3847 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3848 ah->slottime = (u32) -1;
3849 return false;
3850 } else {
3851 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3852 ah->slottime = us;
3853 return true;
3854 }
3855 }
3856
3857 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3858 {
3859 u32 macmode;
3860
3861 if (mode == ATH9K_HT_MACMODE_2040 &&
3862 !ah->config.cwm_ignore_extcca)
3863 macmode = AR_2040_JOINED_RX_CLEAR;
3864 else
3865 macmode = 0;
3866
3867 REG_WRITE(ah, AR_2040_MODE, macmode);
3868 }
3869
3870 /***************************/
3871 /* Bluetooth Coexistence */
3872 /***************************/
3873
3874 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3875 {
3876 /* connect bt_active to baseband */
3877 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3878 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3879 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3880
3881 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3882 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3883
3884 /* Set input mux for bt_active to gpio pin */
3885 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3886 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3887 ah->btactive_gpio);
3888
3889 /* Configure the desired gpio port for input */
3890 ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
3891
3892 /* Configure the desired GPIO port for TX_FRAME output */
3893 ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
3894 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3895 }
AMDTP streaming driver for the Linux FireWire stack (Juju)