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[MIPS] Deforest the function pointer jungle in the time code.
[firewire-audio.git] / arch / mips / tx4938 / toshiba_rbtx4938 / setup.c
blob304b406fcb9dd305a640ce3b9f926c5c36e682c7
1 /*
2 * linux/arch/mips/tx4938/toshiba_rbtx4938/setup.c
3 *
4 * Setup pointers to hardware-dependent routines.
5 * Copyright (C) 2000-2001 Toshiba Corporation
6 *
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13 */
14 #include <linux/init.h>
15 #include <linux/types.h>
16 #include <linux/ioport.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/console.h>
20 #include <linux/pci.h>
21 #include <linux/pm.h>
22 #include <linux/platform_device.h>
23 #include <linux/clk.h>
24
25 #include <asm/wbflush.h>
26 #include <asm/reboot.h>
27 #include <asm/irq.h>
28 #include <asm/time.h>
29 #include <asm/uaccess.h>
30 #include <asm/io.h>
31 #include <asm/bootinfo.h>
32 #include <asm/tx4938/rbtx4938.h>
33 #ifdef CONFIG_SERIAL_TXX9
34 #include <linux/tty.h>
35 #include <linux/serial.h>
36 #include <linux/serial_core.h>
37 #endif
38 #include <linux/spi/spi.h>
39 #include <asm/tx4938/spi.h>
40 #include <asm/gpio.h>
41
42 extern char * __init prom_getcmdline(void);
43 static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr);
44
45 /* These functions are used for rebooting or halting the machine*/
46 extern void rbtx4938_machine_restart(char *command);
47 extern void rbtx4938_machine_halt(void);
48 extern void rbtx4938_machine_power_off(void);
49
50 /* clocks */
51 unsigned int txx9_master_clock;
52 unsigned int txx9_cpu_clock;
53 unsigned int txx9_gbus_clock;
54
55 unsigned long rbtx4938_ce_base[8];
56 unsigned long rbtx4938_ce_size[8];
57 int txboard_pci66_mode;
58 static int tx4938_pcic_trdyto; /* default: disabled */
59 static int tx4938_pcic_retryto; /* default: disabled */
60 static int tx4938_ccfg_toeon = 1;
61
62 struct tx4938_pcic_reg *pcicptrs[4] = {
63 tx4938_pcicptr /* default setting for TX4938 */
64 };
65
66 static struct {
67 unsigned long base;
68 unsigned long size;
69 } phys_regions[16] __initdata;
70 static int num_phys_regions __initdata;
71
72 #define PHYS_REGION_MINSIZE 0x10000
73
74 void rbtx4938_machine_halt(void)
75 {
76 printk(KERN_NOTICE "System Halted\n");
77 local_irq_disable();
78
79 while (1)
80 __asm__(".set\tmips3\n\t"
81 "wait\n\t"
82 ".set\tmips0");
83 }
84
85 void rbtx4938_machine_power_off(void)
86 {
87 rbtx4938_machine_halt();
88 /* no return */
89 }
90
91 void rbtx4938_machine_restart(char *command)
92 {
93 local_irq_disable();
94
95 printk("Rebooting...");
96 *rbtx4938_softresetlock_ptr = 1;
97 *rbtx4938_sfvol_ptr = 1;
98 *rbtx4938_softreset_ptr = 1;
99 wbflush();
100
101 while(1);
102 }
103
104 void __init
105 txboard_add_phys_region(unsigned long base, unsigned long size)
106 {
107 if (num_phys_regions >= ARRAY_SIZE(phys_regions)) {
108 printk("phys_region overflow\n");
109 return;
110 }
111 phys_regions[num_phys_regions].base = base;
112 phys_regions[num_phys_regions].size = size;
113 num_phys_regions++;
114 }
115 unsigned long __init
116 txboard_find_free_phys_region(unsigned long begin, unsigned long end,
117 unsigned long size)
118 {
119 unsigned long base;
120 int i;
121
122 for (base = begin / size * size; base < end; base += size) {
123 for (i = 0; i < num_phys_regions; i++) {
124 if (phys_regions[i].size &&
125 base <= phys_regions[i].base + (phys_regions[i].size - 1) &&
126 base + (size - 1) >= phys_regions[i].base)
127 break;
128 }
129 if (i == num_phys_regions)
130 return base;
131 }
132 return 0;
133 }
134 unsigned long __init
135 txboard_find_free_phys_region_shrink(unsigned long begin, unsigned long end,
136 unsigned long *size)
137 {
138 unsigned long sz, base;
139 for (sz = *size; sz >= PHYS_REGION_MINSIZE; sz /= 2) {
140 base = txboard_find_free_phys_region(begin, end, sz);
141 if (base) {
142 *size = sz;
143 return base;
144 }
145 }
146 return 0;
147 }
148 unsigned long __init
149 txboard_request_phys_region_range(unsigned long begin, unsigned long end,
150 unsigned long size)
151 {
152 unsigned long base;
153 base = txboard_find_free_phys_region(begin, end, size);
154 if (base)
155 txboard_add_phys_region(base, size);
156 return base;
157 }
158 unsigned long __init
159 txboard_request_phys_region(unsigned long size)
160 {
161 unsigned long base;
162 unsigned long begin = 0, end = 0x20000000; /* search low 512MB */
163 base = txboard_find_free_phys_region(begin, end, size);
164 if (base)
165 txboard_add_phys_region(base, size);
166 return base;
167 }
168 unsigned long __init
169 txboard_request_phys_region_shrink(unsigned long *size)
170 {
171 unsigned long base;
172 unsigned long begin = 0, end = 0x20000000; /* search low 512MB */
173 base = txboard_find_free_phys_region_shrink(begin, end, size);
174 if (base)
175 txboard_add_phys_region(base, *size);
176 return base;
177 }
178
179 #ifdef CONFIG_PCI
180 void __init
181 tx4938_pcic_setup(struct tx4938_pcic_reg *pcicptr,
182 struct pci_controller *channel,
183 unsigned long pci_io_base,
184 int extarb)
185 {
186 int i;
187
188 /* Disable All Initiator Space */
189 pcicptr->pciccfg &= ~(TX4938_PCIC_PCICCFG_G2PMEN(0)|
190 TX4938_PCIC_PCICCFG_G2PMEN(1)|
191 TX4938_PCIC_PCICCFG_G2PMEN(2)|
192 TX4938_PCIC_PCICCFG_G2PIOEN);
193
194 /* GB->PCI mappings */
195 pcicptr->g2piomask = (channel->io_resource->end - channel->io_resource->start) >> 4;
196 pcicptr->g2piogbase = pci_io_base |
197 #ifdef __BIG_ENDIAN
198 TX4938_PCIC_G2PIOGBASE_ECHG
199 #else
200 TX4938_PCIC_G2PIOGBASE_BSDIS
201 #endif
202 ;
203 pcicptr->g2piopbase = 0;
204 for (i = 0; i < 3; i++) {
205 pcicptr->g2pmmask[i] = 0;
206 pcicptr->g2pmgbase[i] = 0;
207 pcicptr->g2pmpbase[i] = 0;
208 }
209 if (channel->mem_resource->end) {
210 pcicptr->g2pmmask[0] = (channel->mem_resource->end - channel->mem_resource->start) >> 4;
211 pcicptr->g2pmgbase[0] = channel->mem_resource->start |
212 #ifdef __BIG_ENDIAN
213 TX4938_PCIC_G2PMnGBASE_ECHG
214 #else
215 TX4938_PCIC_G2PMnGBASE_BSDIS
216 #endif
217 ;
218 pcicptr->g2pmpbase[0] = channel->mem_resource->start;
219 }
220 /* PCI->GB mappings (I/O 256B) */
221 pcicptr->p2giopbase = 0; /* 256B */
222 pcicptr->p2giogbase = 0;
223 /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */
224 pcicptr->p2gm0plbase = 0;
225 pcicptr->p2gm0pubase = 0;
226 pcicptr->p2gmgbase[0] = 0 |
227 TX4938_PCIC_P2GMnGBASE_TMEMEN |
228 #ifdef __BIG_ENDIAN
229 TX4938_PCIC_P2GMnGBASE_TECHG
230 #else
231 TX4938_PCIC_P2GMnGBASE_TBSDIS
232 #endif
233 ;
234 /* PCI->GB mappings (MEM 16MB) */
235 pcicptr->p2gm1plbase = 0xffffffff;
236 pcicptr->p2gm1pubase = 0xffffffff;
237 pcicptr->p2gmgbase[1] = 0;
238 /* PCI->GB mappings (MEM 1MB) */
239 pcicptr->p2gm2pbase = 0xffffffff; /* 1MB */
240 pcicptr->p2gmgbase[2] = 0;
241
242 pcicptr->pciccfg &= TX4938_PCIC_PCICCFG_GBWC_MASK;
243 /* Enable Initiator Memory Space */
244 if (channel->mem_resource->end)
245 pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PMEN(0);
246 /* Enable Initiator I/O Space */
247 if (channel->io_resource->end)
248 pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PIOEN;
249 /* Enable Initiator Config */
250 pcicptr->pciccfg |=
251 TX4938_PCIC_PCICCFG_ICAEN |
252 TX4938_PCIC_PCICCFG_TCAR;
253
254 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
255 pcicptr->pcicfg1 = 0;
256
257 pcicptr->g2ptocnt &= ~0xffff;
258
259 if (tx4938_pcic_trdyto >= 0) {
260 pcicptr->g2ptocnt &= ~0xff;
261 pcicptr->g2ptocnt |= (tx4938_pcic_trdyto & 0xff);
262 }
263
264 if (tx4938_pcic_retryto >= 0) {
265 pcicptr->g2ptocnt &= ~0xff00;
266 pcicptr->g2ptocnt |= ((tx4938_pcic_retryto<<8) & 0xff00);
267 }
268
269 /* Clear All Local Bus Status */
270 pcicptr->pcicstatus = TX4938_PCIC_PCICSTATUS_ALL;
271 /* Enable All Local Bus Interrupts */
272 pcicptr->pcicmask = TX4938_PCIC_PCICSTATUS_ALL;
273 /* Clear All Initiator Status */
274 pcicptr->g2pstatus = TX4938_PCIC_G2PSTATUS_ALL;
275 /* Enable All Initiator Interrupts */
276 pcicptr->g2pmask = TX4938_PCIC_G2PSTATUS_ALL;
277 /* Clear All PCI Status Error */
278 pcicptr->pcistatus =
279 (pcicptr->pcistatus & 0x0000ffff) |
280 (TX4938_PCIC_PCISTATUS_ALL << 16);
281 /* Enable All PCI Status Error Interrupts */
282 pcicptr->pcimask = TX4938_PCIC_PCISTATUS_ALL;
283
284 if (!extarb) {
285 /* Reset Bus Arbiter */
286 pcicptr->pbacfg = TX4938_PCIC_PBACFG_RPBA;
287 pcicptr->pbabm = 0;
288 /* Enable Bus Arbiter */
289 pcicptr->pbacfg = TX4938_PCIC_PBACFG_PBAEN;
290 }
291
292 /* PCIC Int => IRC IRQ16 */
293 pcicptr->pcicfg2 =
294 (pcicptr->pcicfg2 & 0xffffff00) | TX4938_IR_PCIC;
295
296 pcicptr->pcistatus = PCI_COMMAND_MASTER |
297 PCI_COMMAND_MEMORY |
298 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
299 }
300
301 int __init
302 tx4938_report_pciclk(void)
303 {
304 unsigned long pcode = TX4938_REV_PCODE();
305 int pciclk = 0;
306 printk("TX%lx PCIC --%s PCICLK:",
307 pcode,
308 (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) ? " PCI66" : "");
309 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) {
310
311 switch ((unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK) {
312 case TX4938_CCFG_PCIDIVMODE_4:
313 pciclk = txx9_cpu_clock / 4; break;
314 case TX4938_CCFG_PCIDIVMODE_4_5:
315 pciclk = txx9_cpu_clock * 2 / 9; break;
316 case TX4938_CCFG_PCIDIVMODE_5:
317 pciclk = txx9_cpu_clock / 5; break;
318 case TX4938_CCFG_PCIDIVMODE_5_5:
319 pciclk = txx9_cpu_clock * 2 / 11; break;
320 case TX4938_CCFG_PCIDIVMODE_8:
321 pciclk = txx9_cpu_clock / 8; break;
322 case TX4938_CCFG_PCIDIVMODE_9:
323 pciclk = txx9_cpu_clock / 9; break;
324 case TX4938_CCFG_PCIDIVMODE_10:
325 pciclk = txx9_cpu_clock / 10; break;
326 case TX4938_CCFG_PCIDIVMODE_11:
327 pciclk = txx9_cpu_clock / 11; break;
328 }
329 printk("Internal(%dMHz)", pciclk / 1000000);
330 } else {
331 printk("External");
332 pciclk = -1;
333 }
334 printk("\n");
335 return pciclk;
336 }
337
338 void __init set_tx4938_pcicptr(int ch, struct tx4938_pcic_reg *pcicptr)
339 {
340 pcicptrs[ch] = pcicptr;
341 }
342
343 struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch)
344 {
345 return pcicptrs[ch];
346 }
347
348 static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
349 int top_bus, int busnr, int devfn)
350 {
351 static struct pci_dev dev;
352 static struct pci_bus bus;
353
354 dev.sysdata = bus.sysdata = hose;
355 dev.devfn = devfn;
356 bus.number = busnr;
357 bus.ops = hose->pci_ops;
358 bus.parent = NULL;
359 dev.bus = &bus;
360
361 return &dev;
362 }
363
364 #define EARLY_PCI_OP(rw, size, type) \
365 static int early_##rw##_config_##size(struct pci_controller *hose, \
366 int top_bus, int bus, int devfn, int offset, type value) \
367 { \
368 return pci_##rw##_config_##size( \
369 fake_pci_dev(hose, top_bus, bus, devfn), \
370 offset, value); \
371 }
372
373 EARLY_PCI_OP(read, word, u16 *)
374
375 int txboard_pci66_check(struct pci_controller *hose, int top_bus, int current_bus)
376 {
377 u32 pci_devfn;
378 unsigned short vid;
379 int devfn_start = 0;
380 int devfn_stop = 0xff;
381 int cap66 = -1;
382 u16 stat;
383
384 printk("PCI: Checking 66MHz capabilities...\n");
385
386 for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
387 if (early_read_config_word(hose, top_bus, current_bus,
388 pci_devfn, PCI_VENDOR_ID,
389 &vid) != PCIBIOS_SUCCESSFUL)
390 continue;
391
392 if (vid == 0xffff) continue;
393
394 /* check 66MHz capability */
395 if (cap66 < 0)
396 cap66 = 1;
397 if (cap66) {
398 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
399 PCI_STATUS, &stat);
400 if (!(stat & PCI_STATUS_66MHZ)) {
401 printk(KERN_DEBUG "PCI: %02x:%02x not 66MHz capable.\n",
402 current_bus, pci_devfn);
403 cap66 = 0;
404 break;
405 }
406 }
407 }
408 return cap66 > 0;
409 }
410
411 int __init
412 tx4938_pciclk66_setup(void)
413 {
414 int pciclk;
415
416 /* Assert M66EN */
417 tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI66;
418 /* Double PCICLK (if possible) */
419 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) {
420 unsigned int pcidivmode =
421 tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK;
422 switch (pcidivmode) {
423 case TX4938_CCFG_PCIDIVMODE_8:
424 case TX4938_CCFG_PCIDIVMODE_4:
425 pcidivmode = TX4938_CCFG_PCIDIVMODE_4;
426 pciclk = txx9_cpu_clock / 4;
427 break;
428 case TX4938_CCFG_PCIDIVMODE_9:
429 case TX4938_CCFG_PCIDIVMODE_4_5:
430 pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5;
431 pciclk = txx9_cpu_clock * 2 / 9;
432 break;
433 case TX4938_CCFG_PCIDIVMODE_10:
434 case TX4938_CCFG_PCIDIVMODE_5:
435 pcidivmode = TX4938_CCFG_PCIDIVMODE_5;
436 pciclk = txx9_cpu_clock / 5;
437 break;
438 case TX4938_CCFG_PCIDIVMODE_11:
439 case TX4938_CCFG_PCIDIVMODE_5_5:
440 default:
441 pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5;
442 pciclk = txx9_cpu_clock * 2 / 11;
443 break;
444 }
445 tx4938_ccfgptr->ccfg =
446 (tx4938_ccfgptr->ccfg & ~TX4938_CCFG_PCIDIVMODE_MASK)
447 | pcidivmode;
448 printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n",
449 (unsigned long)tx4938_ccfgptr->ccfg);
450 } else {
451 pciclk = -1;
452 }
453 return pciclk;
454 }
455
456 extern struct pci_controller tx4938_pci_controller[];
457 static int __init tx4938_pcibios_init(void)
458 {
459 unsigned long mem_base[2];
460 unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0,TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */
461 unsigned long io_base[2];
462 unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0,TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */
463 /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */
464 int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB);
465
466 PCIBIOS_MIN_IO = 0x00001000UL;
467
468 mem_base[0] = txboard_request_phys_region_shrink(&mem_size[0]);
469 io_base[0] = txboard_request_phys_region_shrink(&io_size[0]);
470
471 printk("TX4938 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
472 (unsigned short)(tx4938_pcicptr->pciid >> 16),
473 (unsigned short)(tx4938_pcicptr->pciid & 0xffff),
474 (unsigned short)(tx4938_pcicptr->pciccrev & 0xff),
475 extarb ? "External" : "Internal");
476
477 /* setup PCI area */
478 tx4938_pci_controller[0].io_resource->start = io_base[0];
479 tx4938_pci_controller[0].io_resource->end = (io_base[0] + io_size[0]) - 1;
480 tx4938_pci_controller[0].mem_resource->start = mem_base[0];
481 tx4938_pci_controller[0].mem_resource->end = mem_base[0] + mem_size[0] - 1;
482
483 set_tx4938_pcicptr(0, tx4938_pcicptr);
484
485 register_pci_controller(&tx4938_pci_controller[0]);
486
487 if (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) {
488 printk("TX4938_CCFG_PCI66 already configured\n");
489 txboard_pci66_mode = -1; /* already configured */
490 }
491
492 /* Reset PCI Bus */
493 *rbtx4938_pcireset_ptr = 0;
494 /* Reset PCIC */
495 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST;
496 if (txboard_pci66_mode > 0)
497 tx4938_pciclk66_setup();
498 mdelay(10);
499 /* clear PCIC reset */
500 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
501 *rbtx4938_pcireset_ptr = 1;
502 wbflush();
503 tx4938_report_pcic_status1(tx4938_pcicptr);
504
505 tx4938_report_pciclk();
506 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb);
507 if (txboard_pci66_mode == 0 &&
508 txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) {
509 /* Reset PCI Bus */
510 *rbtx4938_pcireset_ptr = 0;
511 /* Reset PCIC */
512 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST;
513 tx4938_pciclk66_setup();
514 mdelay(10);
515 /* clear PCIC reset */
516 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
517 *rbtx4938_pcireset_ptr = 1;
518 wbflush();
519 /* Reinitialize PCIC */
520 tx4938_report_pciclk();
521 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb);
522 }
523
524 mem_base[1] = txboard_request_phys_region_shrink(&mem_size[1]);
525 io_base[1] = txboard_request_phys_region_shrink(&io_size[1]);
526 /* Reset PCIC1 */
527 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIC1RST;
528 /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */
529 if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD))
530 tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI1_66;
531 else
532 tx4938_ccfgptr->ccfg &= ~TX4938_CCFG_PCI1_66;
533 mdelay(10);
534 /* clear PCIC1 reset */
535 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST;
536 tx4938_report_pcic_status1(tx4938_pcic1ptr);
537
538 printk("TX4938 PCIC1 -- DID:%04x VID:%04x RID:%02x",
539 (unsigned short)(tx4938_pcic1ptr->pciid >> 16),
540 (unsigned short)(tx4938_pcic1ptr->pciid & 0xffff),
541 (unsigned short)(tx4938_pcic1ptr->pciccrev & 0xff));
542 printk("%s PCICLK:%dMHz\n",
543 (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1_66) ? " PCI66" : "",
544 txx9_gbus_clock /
545 ((tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2) /
546 1000000);
547
548 /* assumption: CPHYSADDR(mips_io_port_base) == io_base[0] */
549 tx4938_pci_controller[1].io_resource->start =
550 io_base[1] - io_base[0];
551 tx4938_pci_controller[1].io_resource->end =
552 io_base[1] - io_base[0] + io_size[1] - 1;
553 tx4938_pci_controller[1].mem_resource->start = mem_base[1];
554 tx4938_pci_controller[1].mem_resource->end =
555 mem_base[1] + mem_size[1] - 1;
556 set_tx4938_pcicptr(1, tx4938_pcic1ptr);
557
558 register_pci_controller(&tx4938_pci_controller[1]);
559
560 tx4938_pcic_setup(tx4938_pcic1ptr, &tx4938_pci_controller[1], io_base[1], extarb);
561
562 /* map ioport 0 to PCI I/O space address 0 */
563 set_io_port_base(KSEG1 + io_base[0]);
564
565 return 0;
566 }
567
568 arch_initcall(tx4938_pcibios_init);
569
570 #endif /* CONFIG_PCI */
571
572 /* SPI support */
573
574 /* chip select for SPI devices */
575 #define SEEPROM1_CS 7 /* PIO7 */
576 #define SEEPROM2_CS 0 /* IOC */
577 #define SEEPROM3_CS 1 /* IOC */
578 #define SRTC_CS 2 /* IOC */
579
580 #ifdef CONFIG_PCI
581 static int __init rbtx4938_ethaddr_init(void)
582 {
583 unsigned char dat[17];
584 unsigned char sum;
585 int i;
586
587 /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
588 if (spi_eeprom_read(SEEPROM1_CS, 0, dat, sizeof(dat))) {
589 printk(KERN_ERR "seeprom: read error.\n");
590 return -ENODEV;
591 } else {
592 if (strcmp(dat, "MAC") != 0)
593 printk(KERN_WARNING "seeprom: bad signature.\n");
594 for (i = 0, sum = 0; i < sizeof(dat); i++)
595 sum += dat[i];
596 if (sum)
597 printk(KERN_WARNING "seeprom: bad checksum.\n");
598 }
599 for (i = 0; i < 2; i++) {
600 unsigned int slot = TX4938_PCIC_IDSEL_AD_TO_SLOT(31 - i);
601 unsigned int id = (1 << 8) | PCI_DEVFN(slot, 0); /* bus 1 */
602 struct platform_device *pdev;
603 if (!(tx4938_ccfgptr->pcfg &
604 (i ? TX4938_PCFG_ETH1_SEL : TX4938_PCFG_ETH0_SEL)))
605 continue;
606 pdev = platform_device_alloc("tc35815-mac", id);
607 if (!pdev ||
608 platform_device_add_data(pdev, &dat[4 + 6 * i], 6) ||
609 platform_device_add(pdev))
610 platform_device_put(pdev);
611 }
612 return 0;
613 }
614 device_initcall(rbtx4938_ethaddr_init);
615 #endif /* CONFIG_PCI */
616
617 static void __init rbtx4938_spi_setup(void)
618 {
619 /* set SPI_SEL */
620 tx4938_ccfgptr->pcfg |= TX4938_PCFG_SPI_SEL;
621 /* chip selects for SPI devices */
622 tx4938_pioptr->dout |= (1 << SEEPROM1_CS);
623 tx4938_pioptr->dir |= (1 << SEEPROM1_CS);
624 }
625
626 static struct resource rbtx4938_fpga_resource;
627
628 static char pcode_str[8];
629 static struct resource tx4938_reg_resource = {
630 .start = TX4938_REG_BASE,
631 .end = TX4938_REG_BASE + TX4938_REG_SIZE,
632 .name = pcode_str,
633 .flags = IORESOURCE_MEM
634 };
635
636 void __init tx4938_board_setup(void)
637 {
638 int i;
639 unsigned long divmode;
640 int cpuclk = 0;
641 unsigned long pcode = TX4938_REV_PCODE();
642
643 ioport_resource.start = 0x1000;
644 ioport_resource.end = 0xffffffff;
645 iomem_resource.start = 0x1000;
646 iomem_resource.end = 0xffffffff; /* expand to 4GB */
647
648 sprintf(pcode_str, "TX%lx", pcode);
649 /* SDRAMC,EBUSC are configured by PROM */
650 for (i = 0; i < 8; i++) {
651 if (!(tx4938_ebuscptr->cr[i] & 0x8))
652 continue; /* disabled */
653 rbtx4938_ce_base[i] = (unsigned long)TX4938_EBUSC_BA(i);
654 txboard_add_phys_region(rbtx4938_ce_base[i], TX4938_EBUSC_SIZE(i));
655 }
656
657 /* clocks */
658 if (txx9_master_clock) {
659 /* calculate gbus_clock and cpu_clock_freq from master_clock */
660 divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK;
661 switch (divmode) {
662 case TX4938_CCFG_DIVMODE_8:
663 case TX4938_CCFG_DIVMODE_10:
664 case TX4938_CCFG_DIVMODE_12:
665 case TX4938_CCFG_DIVMODE_16:
666 case TX4938_CCFG_DIVMODE_18:
667 txx9_gbus_clock = txx9_master_clock * 4; break;
668 default:
669 txx9_gbus_clock = txx9_master_clock;
670 }
671 switch (divmode) {
672 case TX4938_CCFG_DIVMODE_2:
673 case TX4938_CCFG_DIVMODE_8:
674 cpuclk = txx9_gbus_clock * 2; break;
675 case TX4938_CCFG_DIVMODE_2_5:
676 case TX4938_CCFG_DIVMODE_10:
677 cpuclk = txx9_gbus_clock * 5 / 2; break;
678 case TX4938_CCFG_DIVMODE_3:
679 case TX4938_CCFG_DIVMODE_12:
680 cpuclk = txx9_gbus_clock * 3; break;
681 case TX4938_CCFG_DIVMODE_4:
682 case TX4938_CCFG_DIVMODE_16:
683 cpuclk = txx9_gbus_clock * 4; break;
684 case TX4938_CCFG_DIVMODE_4_5:
685 case TX4938_CCFG_DIVMODE_18:
686 cpuclk = txx9_gbus_clock * 9 / 2; break;
687 }
688 txx9_cpu_clock = cpuclk;
689 } else {
690 if (txx9_cpu_clock == 0) {
691 txx9_cpu_clock = 300000000; /* 300MHz */
692 }
693 /* calculate gbus_clock and master_clock from cpu_clock_freq */
694 cpuclk = txx9_cpu_clock;
695 divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK;
696 switch (divmode) {
697 case TX4938_CCFG_DIVMODE_2:
698 case TX4938_CCFG_DIVMODE_8:
699 txx9_gbus_clock = cpuclk / 2; break;
700 case TX4938_CCFG_DIVMODE_2_5:
701 case TX4938_CCFG_DIVMODE_10:
702 txx9_gbus_clock = cpuclk * 2 / 5; break;
703 case TX4938_CCFG_DIVMODE_3:
704 case TX4938_CCFG_DIVMODE_12:
705 txx9_gbus_clock = cpuclk / 3; break;
706 case TX4938_CCFG_DIVMODE_4:
707 case TX4938_CCFG_DIVMODE_16:
708 txx9_gbus_clock = cpuclk / 4; break;
709 case TX4938_CCFG_DIVMODE_4_5:
710 case TX4938_CCFG_DIVMODE_18:
711 txx9_gbus_clock = cpuclk * 2 / 9; break;
712 }
713 switch (divmode) {
714 case TX4938_CCFG_DIVMODE_8:
715 case TX4938_CCFG_DIVMODE_10:
716 case TX4938_CCFG_DIVMODE_12:
717 case TX4938_CCFG_DIVMODE_16:
718 case TX4938_CCFG_DIVMODE_18:
719 txx9_master_clock = txx9_gbus_clock / 4; break;
720 default:
721 txx9_master_clock = txx9_gbus_clock;
722 }
723 }
724 /* change default value to udelay/mdelay take reasonable time */
725 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
726
727 /* CCFG */
728 /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */
729 tx4938_ccfgptr->ccfg |= TX4938_CCFG_WDRST | TX4938_CCFG_BEOW;
730 /* clear PCIC1 reset */
731 if (tx4938_ccfgptr->clkctr & TX4938_CLKCTR_PCIC1RST)
732 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST;
733
734 /* enable Timeout BusError */
735 if (tx4938_ccfg_toeon)
736 tx4938_ccfgptr->ccfg |= TX4938_CCFG_TOE;
737
738 /* DMA selection */
739 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_DMASEL_ALL;
740
741 /* Use external clock for external arbiter */
742 if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB))
743 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_PCICLKEN_ALL;
744
745 printk("%s -- %dMHz(M%dMHz) CRIR:%08lx CCFG:%Lx PCFG:%Lx\n",
746 pcode_str,
747 cpuclk / 1000000, txx9_master_clock / 1000000,
748 (unsigned long)tx4938_ccfgptr->crir,
749 tx4938_ccfgptr->ccfg,
750 tx4938_ccfgptr->pcfg);
751
752 printk("%s SDRAMC --", pcode_str);
753 for (i = 0; i < 4; i++) {
754 unsigned long long cr = tx4938_sdramcptr->cr[i];
755 unsigned long ram_base, ram_size;
756 if (!((unsigned long)cr & 0x00000400))
757 continue; /* disabled */
758 ram_base = (unsigned long)(cr >> 49) << 21;
759 ram_size = ((unsigned long)(cr >> 33) + 1) << 21;
760 if (ram_base >= 0x20000000)
761 continue; /* high memory (ignore) */
762 printk(" CR%d:%016Lx", i, cr);
763 txboard_add_phys_region(ram_base, ram_size);
764 }
765 printk(" TR:%09Lx\n", tx4938_sdramcptr->tr);
766
767 /* SRAM */
768 if (pcode == 0x4938 && tx4938_sramcptr->cr & 1) {
769 unsigned int size = 0x800;
770 unsigned long base =
771 (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1);
772 txboard_add_phys_region(base, size);
773 }
774
775 /* TMR */
776 /* disable all timers */
777 for (i = 0; i < TX4938_NR_TMR; i++) {
778 tx4938_tmrptr(i)->tcr = 0x00000020;
779 tx4938_tmrptr(i)->tisr = 0;
780 tx4938_tmrptr(i)->cpra = 0xffffffff;
781 tx4938_tmrptr(i)->itmr = 0;
782 tx4938_tmrptr(i)->ccdr = 0;
783 tx4938_tmrptr(i)->pgmr = 0;
784 }
785
786 /* enable DMA */
787 TX4938_WR64(0xff1fb150, TX4938_DMA_MCR_MSTEN);
788 TX4938_WR64(0xff1fb950, TX4938_DMA_MCR_MSTEN);
789
790 /* PIO */
791 tx4938_pioptr->maskcpu = 0;
792 tx4938_pioptr->maskext = 0;
793
794 /* TX4938 internal registers */
795 if (request_resource(&iomem_resource, &tx4938_reg_resource))
796 printk("request resource for internal registers failed\n");
797 }
798
799 #ifdef CONFIG_PCI
800 static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr)
801 {
802 unsigned short pcistatus = (unsigned short)(pcicptr->pcistatus >> 16);
803 unsigned long g2pstatus = pcicptr->g2pstatus;
804 unsigned long pcicstatus = pcicptr->pcicstatus;
805 static struct {
806 unsigned long flag;
807 const char *str;
808 } pcistat_tbl[] = {
809 { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" },
810 { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" },
811 { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" },
812 { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" },
813 { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" },
814 { PCI_STATUS_PARITY, "MasterParityError" },
815 }, g2pstat_tbl[] = {
816 { TX4938_PCIC_G2PSTATUS_TTOE, "TIOE" },
817 { TX4938_PCIC_G2PSTATUS_RTOE, "RTOE" },
818 }, pcicstat_tbl[] = {
819 { TX4938_PCIC_PCICSTATUS_PME, "PME" },
820 { TX4938_PCIC_PCICSTATUS_TLB, "TLB" },
821 { TX4938_PCIC_PCICSTATUS_NIB, "NIB" },
822 { TX4938_PCIC_PCICSTATUS_ZIB, "ZIB" },
823 { TX4938_PCIC_PCICSTATUS_PERR, "PERR" },
824 { TX4938_PCIC_PCICSTATUS_SERR, "SERR" },
825 { TX4938_PCIC_PCICSTATUS_GBE, "GBE" },
826 { TX4938_PCIC_PCICSTATUS_IWB, "IWB" },
827 };
828 int i;
829
830 printk("pcistat:%04x(", pcistatus);
831 for (i = 0; i < ARRAY_SIZE(pcistat_tbl); i++)
832 if (pcistatus & pcistat_tbl[i].flag)
833 printk("%s ", pcistat_tbl[i].str);
834 printk("), g2pstatus:%08lx(", g2pstatus);
835 for (i = 0; i < ARRAY_SIZE(g2pstat_tbl); i++)
836 if (g2pstatus & g2pstat_tbl[i].flag)
837 printk("%s ", g2pstat_tbl[i].str);
838 printk("), pcicstatus:%08lx(", pcicstatus);
839 for (i = 0; i < ARRAY_SIZE(pcicstat_tbl); i++)
840 if (pcicstatus & pcicstat_tbl[i].flag)
841 printk("%s ", pcicstat_tbl[i].str);
842 printk(")\n");
843 }
844
845 void tx4938_report_pcic_status(void)
846 {
847 int i;
848 struct tx4938_pcic_reg *pcicptr;
849 for (i = 0; (pcicptr = get_tx4938_pcicptr(i)) != NULL; i++)
850 tx4938_report_pcic_status1(pcicptr);
851 }
852
853 #endif /* CONFIG_PCI */
854
855 /* We use onchip r4k counter or TMR timer as our system wide timer
856 * interrupt running at 100HZ. */
857
858 void __init plat_time_init(void)
859 {
860 mips_hpt_frequency = txx9_cpu_clock / 2;
861 }
862
863 void __init toshiba_rbtx4938_setup(void)
864 {
865 unsigned long long pcfg;
866 char *argptr;
867
868 iomem_resource.end = 0xffffffff; /* 4GB */
869
870 if (txx9_master_clock == 0)
871 txx9_master_clock = 25000000; /* 25MHz */
872 tx4938_board_setup();
873 /* setup serial stuff */
874 TX4938_WR(0xff1ff314, 0x00000000); /* h/w flow control off */
875 TX4938_WR(0xff1ff414, 0x00000000); /* h/w flow control off */
876
877 #ifndef CONFIG_PCI
878 set_io_port_base(RBTX4938_ETHER_BASE);
879 #endif
880
881 #ifdef CONFIG_SERIAL_TXX9
882 {
883 extern int early_serial_txx9_setup(struct uart_port *port);
884 int i;
885 struct uart_port req;
886 for(i = 0; i < 2; i++) {
887 memset(&req, 0, sizeof(req));
888 req.line = i;
889 req.iotype = UPIO_MEM;
890 req.membase = (char *)(0xff1ff300 + i * 0x100);
891 req.mapbase = 0xff1ff300 + i * 0x100;
892 req.irq = RBTX4938_IRQ_IRC_SIO(i);
893 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
894 req.uartclk = 50000000;
895 early_serial_txx9_setup(&req);
896 }
897 }
898 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
899 argptr = prom_getcmdline();
900 if (strstr(argptr, "console=") == NULL) {
901 strcat(argptr, " console=ttyS0,38400");
902 }
903 #endif
904 #endif
905
906 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
907 printk("PIOSEL: disabling both ata and nand selection\n");
908 local_irq_disable();
909 tx4938_ccfgptr->pcfg &= ~(TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
910 #endif
911
912 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
913 printk("PIOSEL: enabling nand selection\n");
914 tx4938_ccfgptr->pcfg |= TX4938_PCFG_NDF_SEL;
915 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_ATA_SEL;
916 #endif
917
918 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
919 printk("PIOSEL: enabling ata selection\n");
920 tx4938_ccfgptr->pcfg |= TX4938_PCFG_ATA_SEL;
921 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_NDF_SEL;
922 #endif
923
924 #ifdef CONFIG_IP_PNP
925 argptr = prom_getcmdline();
926 if (strstr(argptr, "ip=") == NULL) {
927 strcat(argptr, " ip=any");
928 }
929 #endif
930
931
932 #ifdef CONFIG_FB
933 {
934 conswitchp = &dummy_con;
935 }
936 #endif
937
938 rbtx4938_spi_setup();
939 pcfg = tx4938_ccfgptr->pcfg; /* updated */
940 /* fixup piosel */
941 if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
942 TX4938_PCFG_ATA_SEL) {
943 *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x04;
944 }
945 else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
946 TX4938_PCFG_NDF_SEL) {
947 *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x08;
948 }
949 else {
950 *rbtx4938_piosel_ptr &= ~(0x08 | 0x04);
951 }
952
953 rbtx4938_fpga_resource.name = "FPGA Registers";
954 rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
955 rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
956 rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
957 if (request_resource(&iomem_resource, &rbtx4938_fpga_resource))
958 printk("request resource for fpga failed\n");
959
960 /* disable all OnBoard I/O interrupts */
961 *rbtx4938_imask_ptr = 0;
962
963 _machine_restart = rbtx4938_machine_restart;
964 _machine_halt = rbtx4938_machine_halt;
965 pm_power_off = rbtx4938_machine_power_off;
966
967 *rbtx4938_led_ptr = 0xff;
968 printk("RBTX4938 --- FPGA(Rev %02x)", *rbtx4938_fpga_rev_ptr);
969 printk(" DIPSW:%02x,%02x\n",
970 *rbtx4938_dipsw_ptr, *rbtx4938_bdipsw_ptr);
971 }
972
973 static int __init rbtx4938_ne_init(void)
974 {
975 struct resource res[] = {
976 {
977 .start = RBTX4938_RTL_8019_BASE,
978 .end = RBTX4938_RTL_8019_BASE + 0x20 - 1,
979 .flags = IORESOURCE_IO,
980 }, {
981 .start = RBTX4938_RTL_8019_IRQ,
982 .flags = IORESOURCE_IRQ,
983 }
984 };
985 struct platform_device *dev =
986 platform_device_register_simple("ne", -1,
987 res, ARRAY_SIZE(res));
988 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
989 }
990 device_initcall(rbtx4938_ne_init);
991
992 /* GPIO support */
993
994 static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock);
995
996 static void rbtx4938_spi_gpio_set(unsigned gpio, int value)
997 {
998 u8 val;
999 unsigned long flags;
1000 gpio -= 16;
1001 spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags);
1002 val = *rbtx4938_spics_ptr;
1003 if (value)
1004 val |= 1 << gpio;
1005 else
1006 val &= ~(1 << gpio);
1007 *rbtx4938_spics_ptr = val;
1008 mmiowb();
1009 spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags);
1010 }
1011
1012 static int rbtx4938_spi_gpio_dir_out(unsigned gpio, int value)
1013 {
1014 rbtx4938_spi_gpio_set(gpio, value);
1015 return 0;
1016 }
1017
1018 static DEFINE_SPINLOCK(tx4938_gpio_lock);
1019
1020 static int tx4938_gpio_get(unsigned gpio)
1021 {
1022 return tx4938_pioptr->din & (1 << gpio);
1023 }
1024
1025 static void tx4938_gpio_set_raw(unsigned gpio, int value)
1026 {
1027 u32 val;
1028 val = tx4938_pioptr->dout;
1029 if (value)
1030 val |= 1 << gpio;
1031 else
1032 val &= ~(1 << gpio);
1033 tx4938_pioptr->dout = val;
1034 }
1035
1036 static void tx4938_gpio_set(unsigned gpio, int value)
1037 {
1038 unsigned long flags;
1039 spin_lock_irqsave(&tx4938_gpio_lock, flags);
1040 tx4938_gpio_set_raw(gpio, value);
1041 mmiowb();
1042 spin_unlock_irqrestore(&tx4938_gpio_lock, flags);
1043 }
1044
1045 static int tx4938_gpio_dir_in(unsigned gpio)
1046 {
1047 spin_lock_irq(&tx4938_gpio_lock);
1048 tx4938_pioptr->dir &= ~(1 << gpio);
1049 mmiowb();
1050 spin_unlock_irq(&tx4938_gpio_lock);
1051 return 0;
1052 }
1053
1054 static int tx4938_gpio_dir_out(unsigned int gpio, int value)
1055 {
1056 spin_lock_irq(&tx4938_gpio_lock);
1057 tx4938_gpio_set_raw(gpio, value);
1058 tx4938_pioptr->dir |= 1 << gpio;
1059 mmiowb();
1060 spin_unlock_irq(&tx4938_gpio_lock);
1061 return 0;
1062 }
1063
1064 int gpio_direction_input(unsigned gpio)
1065 {
1066 if (gpio < 16)
1067 return tx4938_gpio_dir_in(gpio);
1068 return -EINVAL;
1069 }
1070
1071 int gpio_direction_output(unsigned gpio, int value)
1072 {
1073 if (gpio < 16)
1074 return tx4938_gpio_dir_out(gpio, value);
1075 if (gpio < 16 + 3)
1076 return rbtx4938_spi_gpio_dir_out(gpio, value);
1077 return -EINVAL;
1078 }
1079
1080 int gpio_get_value(unsigned gpio)
1081 {
1082 if (gpio < 16)
1083 return tx4938_gpio_get(gpio);
1084 return 0;
1085 }
1086
1087 void gpio_set_value(unsigned gpio, int value)
1088 {
1089 if (gpio < 16)
1090 tx4938_gpio_set(gpio, value);
1091 else
1092 rbtx4938_spi_gpio_set(gpio, value);
1093 }
1094
1095 /* SPI support */
1096
1097 static void __init txx9_spi_init(unsigned long base, int irq)
1098 {
1099 struct resource res[] = {
1100 {
1101 .start = base,
1102 .end = base + 0x20 - 1,
1103 .flags = IORESOURCE_MEM,
1104 .parent = &tx4938_reg_resource,
1105 }, {
1106 .start = irq,
1107 .flags = IORESOURCE_IRQ,
1108 },
1109 };
1110 platform_device_register_simple("spi_txx9", 0,
1111 res, ARRAY_SIZE(res));
1112 }
1113
1114 static int __init rbtx4938_spi_init(void)
1115 {
1116 struct spi_board_info srtc_info = {
1117 .modalias = "rtc-rs5c348",
1118 .max_speed_hz = 1000000, /* 1.0Mbps @ Vdd 2.0V */
1119 .bus_num = 0,
1120 .chip_select = 16 + SRTC_CS,
1121 /* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS */
1122 .mode = SPI_MODE_1 | SPI_CS_HIGH,
1123 };
1124 spi_register_board_info(&srtc_info, 1);
1125 spi_eeprom_register(SEEPROM1_CS);
1126 spi_eeprom_register(16 + SEEPROM2_CS);
1127 spi_eeprom_register(16 + SEEPROM3_CS);
1128 txx9_spi_init(TX4938_SPI_REG & 0xfffffffffULL, RBTX4938_IRQ_IRC_SPI);
1129 return 0;
1130 }
1131 arch_initcall(rbtx4938_spi_init);
1132
1133 /* Minimum CLK support */
1134
1135 struct clk *clk_get(struct device *dev, const char *id)
1136 {
1137 if (!strcmp(id, "spi-baseclk"))
1138 return (struct clk *)(txx9_gbus_clock / 2 / 4);
1139 return ERR_PTR(-ENOENT);
1140 }
1141 EXPORT_SYMBOL(clk_get);
1142
1143 int clk_enable(struct clk *clk)
1144 {
1145 return 0;
1146 }
1147 EXPORT_SYMBOL(clk_enable);
1148
1149 void clk_disable(struct clk *clk)
1150 {
1151 }
1152 EXPORT_SYMBOL(clk_disable);
1153
1154 unsigned long clk_get_rate(struct clk *clk)
1155 {
1156 return (unsigned long)clk;
1157 }
1158 EXPORT_SYMBOL(clk_get_rate);
1159
1160 void clk_put(struct clk *clk)
1161 {
1162 }
1163 EXPORT_SYMBOL(clk_put);
AMDTP streaming driver for the Linux FireWire stack (Juju)