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iwlwifi: add channel switch support to 5000 series and up
[firewire-audio.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
blob09a7bd2c0be446527a4b94ea881f34facfc42295
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/skbuff.h>
34 #include <linux/netdevice.h>
35 #include <linux/wireless.h>
36 #include <linux/firmware.h>
37 #include <linux/etherdevice.h>
38 #include <asm/unaligned.h>
39 #include <net/mac80211.h>
40
41 #include "iwl-fh.h"
42 #include "iwl-3945-fh.h"
43 #include "iwl-commands.h"
44 #include "iwl-sta.h"
45 #include "iwl-3945.h"
46 #include "iwl-eeprom.h"
47 #include "iwl-helpers.h"
48 #include "iwl-core.h"
49 #include "iwl-led.h"
50 #include "iwl-3945-led.h"
51
52 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
53 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
54 IWL_RATE_##r##M_IEEE, \
55 IWL_RATE_##ip##M_INDEX, \
56 IWL_RATE_##in##M_INDEX, \
57 IWL_RATE_##rp##M_INDEX, \
58 IWL_RATE_##rn##M_INDEX, \
59 IWL_RATE_##pp##M_INDEX, \
60 IWL_RATE_##np##M_INDEX, \
61 IWL_RATE_##r##M_INDEX_TABLE, \
62 IWL_RATE_##ip##M_INDEX_TABLE }
63
64 /*
65 * Parameter order:
66 * rate, prev rate, next rate, prev tgg rate, next tgg rate
67 *
68 * If there isn't a valid next or previous rate then INV is used which
69 * maps to IWL_RATE_INVALID
70 *
71 */
72 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
73 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
74 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
75 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
76 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
77 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
78 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
79 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
80 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
81 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
82 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
83 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
84 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
85 };
86
87 /* 1 = enable the iwl3945_disable_events() function */
88 #define IWL_EVT_DISABLE (0)
89 #define IWL_EVT_DISABLE_SIZE (1532/32)
90
91 /**
92 * iwl3945_disable_events - Disable selected events in uCode event log
93 *
94 * Disable an event by writing "1"s into "disable"
95 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
96 * Default values of 0 enable uCode events to be logged.
97 * Use for only special debugging. This function is just a placeholder as-is,
98 * you'll need to provide the special bits! ...
99 * ... and set IWL_EVT_DISABLE to 1. */
100 void iwl3945_disable_events(struct iwl_priv *priv)
101 {
102 int i;
103 u32 base; /* SRAM address of event log header */
104 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
105 u32 array_size; /* # of u32 entries in array */
106 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
107 0x00000000, /* 31 - 0 Event id numbers */
108 0x00000000, /* 63 - 32 */
109 0x00000000, /* 95 - 64 */
110 0x00000000, /* 127 - 96 */
111 0x00000000, /* 159 - 128 */
112 0x00000000, /* 191 - 160 */
113 0x00000000, /* 223 - 192 */
114 0x00000000, /* 255 - 224 */
115 0x00000000, /* 287 - 256 */
116 0x00000000, /* 319 - 288 */
117 0x00000000, /* 351 - 320 */
118 0x00000000, /* 383 - 352 */
119 0x00000000, /* 415 - 384 */
120 0x00000000, /* 447 - 416 */
121 0x00000000, /* 479 - 448 */
122 0x00000000, /* 511 - 480 */
123 0x00000000, /* 543 - 512 */
124 0x00000000, /* 575 - 544 */
125 0x00000000, /* 607 - 576 */
126 0x00000000, /* 639 - 608 */
127 0x00000000, /* 671 - 640 */
128 0x00000000, /* 703 - 672 */
129 0x00000000, /* 735 - 704 */
130 0x00000000, /* 767 - 736 */
131 0x00000000, /* 799 - 768 */
132 0x00000000, /* 831 - 800 */
133 0x00000000, /* 863 - 832 */
134 0x00000000, /* 895 - 864 */
135 0x00000000, /* 927 - 896 */
136 0x00000000, /* 959 - 928 */
137 0x00000000, /* 991 - 960 */
138 0x00000000, /* 1023 - 992 */
139 0x00000000, /* 1055 - 1024 */
140 0x00000000, /* 1087 - 1056 */
141 0x00000000, /* 1119 - 1088 */
142 0x00000000, /* 1151 - 1120 */
143 0x00000000, /* 1183 - 1152 */
144 0x00000000, /* 1215 - 1184 */
145 0x00000000, /* 1247 - 1216 */
146 0x00000000, /* 1279 - 1248 */
147 0x00000000, /* 1311 - 1280 */
148 0x00000000, /* 1343 - 1312 */
149 0x00000000, /* 1375 - 1344 */
150 0x00000000, /* 1407 - 1376 */
151 0x00000000, /* 1439 - 1408 */
152 0x00000000, /* 1471 - 1440 */
153 0x00000000, /* 1503 - 1472 */
154 };
155
156 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
157 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
158 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
159 return;
160 }
161
162 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
163 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
164
165 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
166 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
167 disable_ptr);
168 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
169 iwl_write_targ_mem(priv,
170 disable_ptr + (i * sizeof(u32)),
171 evt_disable[i]);
172
173 } else {
174 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
175 IWL_DEBUG_INFO(priv, " by writing \"1\"s into disable bitmap\n");
176 IWL_DEBUG_INFO(priv, " in SRAM at 0x%x, size %d u32s\n",
177 disable_ptr, array_size);
178 }
179
180 }
181
182 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
183 {
184 int idx;
185
186 for (idx = 0; idx < IWL_RATE_COUNT; idx++)
187 if (iwl3945_rates[idx].plcp == plcp)
188 return idx;
189 return -1;
190 }
191
192 #ifdef CONFIG_IWLWIFI_DEBUG
193 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
194
195 static const char *iwl3945_get_tx_fail_reason(u32 status)
196 {
197 switch (status & TX_STATUS_MSK) {
198 case TX_STATUS_SUCCESS:
199 return "SUCCESS";
200 TX_STATUS_ENTRY(SHORT_LIMIT);
201 TX_STATUS_ENTRY(LONG_LIMIT);
202 TX_STATUS_ENTRY(FIFO_UNDERRUN);
203 TX_STATUS_ENTRY(MGMNT_ABORT);
204 TX_STATUS_ENTRY(NEXT_FRAG);
205 TX_STATUS_ENTRY(LIFE_EXPIRE);
206 TX_STATUS_ENTRY(DEST_PS);
207 TX_STATUS_ENTRY(ABORTED);
208 TX_STATUS_ENTRY(BT_RETRY);
209 TX_STATUS_ENTRY(STA_INVALID);
210 TX_STATUS_ENTRY(FRAG_DROPPED);
211 TX_STATUS_ENTRY(TID_DISABLE);
212 TX_STATUS_ENTRY(FRAME_FLUSHED);
213 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
214 TX_STATUS_ENTRY(TX_LOCKED);
215 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
216 }
217
218 return "UNKNOWN";
219 }
220 #else
221 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
222 {
223 return "";
224 }
225 #endif
226
227 /*
228 * get ieee prev rate from rate scale table.
229 * for A and B mode we need to overright prev
230 * value
231 */
232 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
233 {
234 int next_rate = iwl3945_get_prev_ieee_rate(rate);
235
236 switch (priv->band) {
237 case IEEE80211_BAND_5GHZ:
238 if (rate == IWL_RATE_12M_INDEX)
239 next_rate = IWL_RATE_9M_INDEX;
240 else if (rate == IWL_RATE_6M_INDEX)
241 next_rate = IWL_RATE_6M_INDEX;
242 break;
243 case IEEE80211_BAND_2GHZ:
244 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
245 iwl_is_associated(priv)) {
246 if (rate == IWL_RATE_11M_INDEX)
247 next_rate = IWL_RATE_5M_INDEX;
248 }
249 break;
250
251 default:
252 break;
253 }
254
255 return next_rate;
256 }
257
258
259 /**
260 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
261 *
262 * When FW advances 'R' index, all entries between old and new 'R' index
263 * need to be reclaimed. As result, some free space forms. If there is
264 * enough free space (> low mark), wake the stack that feeds us.
265 */
266 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
267 int txq_id, int index)
268 {
269 struct iwl_tx_queue *txq = &priv->txq[txq_id];
270 struct iwl_queue *q = &txq->q;
271 struct iwl_tx_info *tx_info;
272
273 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
274
275 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
276 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
277
278 tx_info = &txq->txb[txq->q.read_ptr];
279 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
280 tx_info->skb[0] = NULL;
281 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
282 }
283
284 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
285 (txq_id != IWL_CMD_QUEUE_NUM) &&
286 priv->mac80211_registered)
287 iwl_wake_queue(priv, txq_id);
288 }
289
290 /**
291 * iwl3945_rx_reply_tx - Handle Tx response
292 */
293 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
294 struct iwl_rx_mem_buffer *rxb)
295 {
296 struct iwl_rx_packet *pkt = rxb_addr(rxb);
297 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
298 int txq_id = SEQ_TO_QUEUE(sequence);
299 int index = SEQ_TO_INDEX(sequence);
300 struct iwl_tx_queue *txq = &priv->txq[txq_id];
301 struct ieee80211_tx_info *info;
302 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
303 u32 status = le32_to_cpu(tx_resp->status);
304 int rate_idx;
305 int fail;
306
307 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
308 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
309 "is out of range [0-%d] %d %d\n", txq_id,
310 index, txq->q.n_bd, txq->q.write_ptr,
311 txq->q.read_ptr);
312 return;
313 }
314
315 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
316 ieee80211_tx_info_clear_status(info);
317
318 /* Fill the MRR chain with some info about on-chip retransmissions */
319 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
320 if (info->band == IEEE80211_BAND_5GHZ)
321 rate_idx -= IWL_FIRST_OFDM_RATE;
322
323 fail = tx_resp->failure_frame;
324
325 info->status.rates[0].idx = rate_idx;
326 info->status.rates[0].count = fail + 1; /* add final attempt */
327
328 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
329 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
330 IEEE80211_TX_STAT_ACK : 0;
331
332 IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
333 txq_id, iwl3945_get_tx_fail_reason(status), status,
334 tx_resp->rate, tx_resp->failure_frame);
335
336 IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
337 iwl3945_tx_queue_reclaim(priv, txq_id, index);
338
339 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
340 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
341 }
342
343
344
345 /*****************************************************************************
346 *
347 * Intel PRO/Wireless 3945ABG/BG Network Connection
348 *
349 * RX handler implementations
350 *
351 *****************************************************************************/
352
353 void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
354 struct iwl_rx_mem_buffer *rxb)
355 {
356 struct iwl_rx_packet *pkt = rxb_addr(rxb);
357 IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
358 (int)sizeof(struct iwl3945_notif_statistics),
359 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
360
361 memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
362 }
363
364 /******************************************************************************
365 *
366 * Misc. internal state and helper functions
367 *
368 ******************************************************************************/
369 #ifdef CONFIG_IWLWIFI_DEBUG
370
371 /**
372 * iwl3945_report_frame - dump frame to syslog during debug sessions
373 *
374 * You may hack this function to show different aspects of received frames,
375 * including selective frame dumps.
376 * group100 parameter selects whether to show 1 out of 100 good frames.
377 */
378 static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
379 struct iwl_rx_packet *pkt,
380 struct ieee80211_hdr *header, int group100)
381 {
382 u32 to_us;
383 u32 print_summary = 0;
384 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
385 u32 hundred = 0;
386 u32 dataframe = 0;
387 __le16 fc;
388 u16 seq_ctl;
389 u16 channel;
390 u16 phy_flags;
391 u16 length;
392 u16 status;
393 u16 bcn_tmr;
394 u32 tsf_low;
395 u64 tsf;
396 u8 rssi;
397 u8 agc;
398 u16 sig_avg;
399 u16 noise_diff;
400 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
401 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
402 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
403 u8 *data = IWL_RX_DATA(pkt);
404
405 /* MAC header */
406 fc = header->frame_control;
407 seq_ctl = le16_to_cpu(header->seq_ctrl);
408
409 /* metadata */
410 channel = le16_to_cpu(rx_hdr->channel);
411 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
412 length = le16_to_cpu(rx_hdr->len);
413
414 /* end-of-frame status and timestamp */
415 status = le32_to_cpu(rx_end->status);
416 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
417 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
418 tsf = le64_to_cpu(rx_end->timestamp);
419
420 /* signal statistics */
421 rssi = rx_stats->rssi;
422 agc = rx_stats->agc;
423 sig_avg = le16_to_cpu(rx_stats->sig_avg);
424 noise_diff = le16_to_cpu(rx_stats->noise_diff);
425
426 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
427
428 /* if data frame is to us and all is good,
429 * (optionally) print summary for only 1 out of every 100 */
430 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
431 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
432 dataframe = 1;
433 if (!group100)
434 print_summary = 1; /* print each frame */
435 else if (priv->framecnt_to_us < 100) {
436 priv->framecnt_to_us++;
437 print_summary = 0;
438 } else {
439 priv->framecnt_to_us = 0;
440 print_summary = 1;
441 hundred = 1;
442 }
443 } else {
444 /* print summary for all other frames */
445 print_summary = 1;
446 }
447
448 if (print_summary) {
449 char *title;
450 int rate;
451
452 if (hundred)
453 title = "100Frames";
454 else if (ieee80211_has_retry(fc))
455 title = "Retry";
456 else if (ieee80211_is_assoc_resp(fc))
457 title = "AscRsp";
458 else if (ieee80211_is_reassoc_resp(fc))
459 title = "RasRsp";
460 else if (ieee80211_is_probe_resp(fc)) {
461 title = "PrbRsp";
462 print_dump = 1; /* dump frame contents */
463 } else if (ieee80211_is_beacon(fc)) {
464 title = "Beacon";
465 print_dump = 1; /* dump frame contents */
466 } else if (ieee80211_is_atim(fc))
467 title = "ATIM";
468 else if (ieee80211_is_auth(fc))
469 title = "Auth";
470 else if (ieee80211_is_deauth(fc))
471 title = "DeAuth";
472 else if (ieee80211_is_disassoc(fc))
473 title = "DisAssoc";
474 else
475 title = "Frame";
476
477 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
478 if (rate == -1)
479 rate = 0;
480 else
481 rate = iwl3945_rates[rate].ieee / 2;
482
483 /* print frame summary.
484 * MAC addresses show just the last byte (for brevity),
485 * but you can hack it to show more, if you'd like to. */
486 if (dataframe)
487 IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
488 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
489 title, le16_to_cpu(fc), header->addr1[5],
490 length, rssi, channel, rate);
491 else {
492 /* src/dst addresses assume managed mode */
493 IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, "
494 "src=0x%02x, rssi=%u, tim=%lu usec, "
495 "phy=0x%02x, chnl=%d\n",
496 title, le16_to_cpu(fc), header->addr1[5],
497 header->addr3[5], rssi,
498 tsf_low - priv->scan_start_tsf,
499 phy_flags, channel);
500 }
501 }
502 if (print_dump)
503 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
504 }
505
506 static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
507 struct iwl_rx_packet *pkt,
508 struct ieee80211_hdr *header, int group100)
509 {
510 if (iwl_get_debug_level(priv) & IWL_DL_RX)
511 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
512 }
513
514 #else
515 static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
516 struct iwl_rx_packet *pkt,
517 struct ieee80211_hdr *header, int group100)
518 {
519 }
520 #endif
521
522 /* This is necessary only for a number of statistics, see the caller. */
523 static int iwl3945_is_network_packet(struct iwl_priv *priv,
524 struct ieee80211_hdr *header)
525 {
526 /* Filter incoming packets to determine if they are targeted toward
527 * this network, discarding packets coming from ourselves */
528 switch (priv->iw_mode) {
529 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
530 /* packets to our IBSS update information */
531 return !compare_ether_addr(header->addr3, priv->bssid);
532 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
533 /* packets to our IBSS update information */
534 return !compare_ether_addr(header->addr2, priv->bssid);
535 default:
536 return 1;
537 }
538 }
539
540 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
541 struct iwl_rx_mem_buffer *rxb,
542 struct ieee80211_rx_status *stats)
543 {
544 struct iwl_rx_packet *pkt = rxb_addr(rxb);
545 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
546 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
547 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
548 u16 len = le16_to_cpu(rx_hdr->len);
549 struct sk_buff *skb;
550 int ret;
551 __le16 fc = hdr->frame_control;
552
553 /* We received data from the HW, so stop the watchdog */
554 if (unlikely(len + IWL39_RX_FRAME_SIZE >
555 PAGE_SIZE << priv->hw_params.rx_page_order)) {
556 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
557 return;
558 }
559
560 /* We only process data packets if the interface is open */
561 if (unlikely(!priv->is_open)) {
562 IWL_DEBUG_DROP_LIMIT(priv,
563 "Dropping packet while interface is not open.\n");
564 return;
565 }
566
567 skb = alloc_skb(IWL_LINK_HDR_MAX, GFP_ATOMIC);
568 if (!skb) {
569 IWL_ERR(priv, "alloc_skb failed\n");
570 return;
571 }
572
573 if (!iwl3945_mod_params.sw_crypto)
574 iwl_set_decrypted_flag(priv,
575 (struct ieee80211_hdr *)rxb_addr(rxb),
576 le32_to_cpu(rx_end->status), stats);
577
578 skb_add_rx_frag(skb, 0, rxb->page,
579 (void *)rx_hdr->payload - (void *)pkt, len);
580
581 /* mac80211 currently doesn't support paged SKB. Convert it to
582 * linear SKB for management frame and data frame requires
583 * software decryption or software defragementation. */
584 if (ieee80211_is_mgmt(fc) ||
585 ieee80211_has_protected(fc) ||
586 ieee80211_has_morefrags(fc) ||
587 le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG)
588 ret = skb_linearize(skb);
589 else
590 ret = __pskb_pull_tail(skb, min_t(u16, IWL_LINK_HDR_MAX, len)) ?
591 0 : -ENOMEM;
592
593 if (ret) {
594 kfree_skb(skb);
595 goto out;
596 }
597
598 /*
599 * XXX: We cannot touch the page and its virtual memory (pkt) after
600 * here. It might have already been freed by the above skb change.
601 */
602
603 iwl_update_stats(priv, false, fc, len);
604 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
605
606 ieee80211_rx(priv->hw, skb);
607 out:
608 priv->alloc_rxb_page--;
609 rxb->page = NULL;
610 }
611
612 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
613
614 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
615 struct iwl_rx_mem_buffer *rxb)
616 {
617 struct ieee80211_hdr *header;
618 struct ieee80211_rx_status rx_status;
619 struct iwl_rx_packet *pkt = rxb_addr(rxb);
620 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
621 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
622 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
623 int snr;
624 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
625 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
626 u8 network_packet;
627
628 rx_status.flag = 0;
629 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
630 rx_status.freq =
631 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
632 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
633 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
634
635 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
636 if (rx_status.band == IEEE80211_BAND_5GHZ)
637 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
638
639 rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
640 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
641
642 /* set the preamble flag if appropriate */
643 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
644 rx_status.flag |= RX_FLAG_SHORTPRE;
645
646 if ((unlikely(rx_stats->phy_count > 20))) {
647 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
648 rx_stats->phy_count);
649 return;
650 }
651
652 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
653 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
654 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
655 return;
656 }
657
658
659
660 /* Convert 3945's rssi indicator to dBm */
661 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
662
663 /* Set default noise value to -127 */
664 if (priv->last_rx_noise == 0)
665 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
666
667 /* 3945 provides noise info for OFDM frames only.
668 * sig_avg and noise_diff are measured by the 3945's digital signal
669 * processor (DSP), and indicate linear levels of signal level and
670 * distortion/noise within the packet preamble after
671 * automatic gain control (AGC). sig_avg should stay fairly
672 * constant if the radio's AGC is working well.
673 * Since these values are linear (not dB or dBm), linear
674 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
675 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
676 * to obtain noise level in dBm.
677 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
678 if (rx_stats_noise_diff) {
679 snr = rx_stats_sig_avg / rx_stats_noise_diff;
680 rx_status.noise = rx_status.signal -
681 iwl3945_calc_db_from_ratio(snr);
682 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
683 rx_status.noise);
684
685 /* If noise info not available, calculate signal quality indicator (%)
686 * using just the dBm signal level. */
687 } else {
688 rx_status.noise = priv->last_rx_noise;
689 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
690 }
691
692
693 IWL_DEBUG_STATS(priv, "Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
694 rx_status.signal, rx_status.noise, rx_status.qual,
695 rx_stats_sig_avg, rx_stats_noise_diff);
696
697 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
698
699 network_packet = iwl3945_is_network_packet(priv, header);
700
701 IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
702 network_packet ? '*' : ' ',
703 le16_to_cpu(rx_hdr->channel),
704 rx_status.signal, rx_status.signal,
705 rx_status.noise, rx_status.rate_idx);
706
707 /* Set "1" to report good data frames in groups of 100 */
708 iwl3945_dbg_report_frame(priv, pkt, header, 1);
709 iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
710
711 if (network_packet) {
712 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
713 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
714 priv->last_rx_rssi = rx_status.signal;
715 priv->last_rx_noise = rx_status.noise;
716 }
717
718 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
719 }
720
721 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
722 struct iwl_tx_queue *txq,
723 dma_addr_t addr, u16 len, u8 reset, u8 pad)
724 {
725 int count;
726 struct iwl_queue *q;
727 struct iwl3945_tfd *tfd, *tfd_tmp;
728
729 q = &txq->q;
730 tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
731 tfd = &tfd_tmp[q->write_ptr];
732
733 if (reset)
734 memset(tfd, 0, sizeof(*tfd));
735
736 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
737
738 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
739 IWL_ERR(priv, "Error can not send more than %d chunks\n",
740 NUM_TFD_CHUNKS);
741 return -EINVAL;
742 }
743
744 tfd->tbs[count].addr = cpu_to_le32(addr);
745 tfd->tbs[count].len = cpu_to_le32(len);
746
747 count++;
748
749 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
750 TFD_CTL_PAD_SET(pad));
751
752 return 0;
753 }
754
755 /**
756 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
757 *
758 * Does NOT advance any indexes
759 */
760 void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
761 {
762 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
763 int index = txq->q.read_ptr;
764 struct iwl3945_tfd *tfd = &tfd_tmp[index];
765 struct pci_dev *dev = priv->pci_dev;
766 int i;
767 int counter;
768
769 /* sanity check */
770 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
771 if (counter > NUM_TFD_CHUNKS) {
772 IWL_ERR(priv, "Too many chunks: %i\n", counter);
773 /* @todo issue fatal error, it is quite serious situation */
774 return;
775 }
776
777 /* Unmap tx_cmd */
778 if (counter)
779 pci_unmap_single(dev,
780 pci_unmap_addr(&txq->meta[index], mapping),
781 pci_unmap_len(&txq->meta[index], len),
782 PCI_DMA_TODEVICE);
783
784 /* unmap chunks if any */
785
786 for (i = 1; i < counter; i++) {
787 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
788 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
789 if (txq->txb[txq->q.read_ptr].skb[0]) {
790 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
791 if (txq->txb[txq->q.read_ptr].skb[0]) {
792 /* Can be called from interrupt context */
793 dev_kfree_skb_any(skb);
794 txq->txb[txq->q.read_ptr].skb[0] = NULL;
795 }
796 }
797 }
798 return ;
799 }
800
801 /**
802 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
803 *
804 */
805 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
806 struct iwl_device_cmd *cmd,
807 struct ieee80211_tx_info *info,
808 struct ieee80211_hdr *hdr,
809 int sta_id, int tx_id)
810 {
811 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
812 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
813 u16 rate_mask;
814 int rate;
815 u8 rts_retry_limit;
816 u8 data_retry_limit;
817 __le32 tx_flags;
818 __le16 fc = hdr->frame_control;
819 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
820
821 rate = iwl3945_rates[rate_index].plcp;
822 tx_flags = tx_cmd->tx_flags;
823
824 /* We need to figure out how to get the sta->supp_rates while
825 * in this running context */
826 rate_mask = IWL_RATES_MASK;
827
828
829 /* Set retry limit on DATA packets and Probe Responses*/
830 if (ieee80211_is_probe_resp(fc))
831 data_retry_limit = 3;
832 else
833 data_retry_limit = IWL_DEFAULT_TX_RETRY;
834 tx_cmd->data_retry_limit = data_retry_limit;
835
836 if (tx_id >= IWL_CMD_QUEUE_NUM)
837 rts_retry_limit = 3;
838 else
839 rts_retry_limit = 7;
840
841 if (data_retry_limit < rts_retry_limit)
842 rts_retry_limit = data_retry_limit;
843 tx_cmd->rts_retry_limit = rts_retry_limit;
844
845 if (ieee80211_is_mgmt(fc)) {
846 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
847 case cpu_to_le16(IEEE80211_STYPE_AUTH):
848 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
849 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
850 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
851 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
852 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
853 tx_flags |= TX_CMD_FLG_CTS_MSK;
854 }
855 break;
856 default:
857 break;
858 }
859 }
860
861 tx_cmd->rate = rate;
862 tx_cmd->tx_flags = tx_flags;
863
864 /* OFDM */
865 tx_cmd->supp_rates[0] =
866 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
867
868 /* CCK */
869 tx_cmd->supp_rates[1] = (rate_mask & 0xF);
870
871 IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
872 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
873 tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags),
874 tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]);
875 }
876
877 u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
878 {
879 unsigned long flags_spin;
880 struct iwl_station_entry *station;
881
882 if (sta_id == IWL_INVALID_STATION)
883 return IWL_INVALID_STATION;
884
885 spin_lock_irqsave(&priv->sta_lock, flags_spin);
886 station = &priv->stations[sta_id];
887
888 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
889 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
890 station->sta.mode = STA_CONTROL_MODIFY_MSK;
891
892 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
893
894 iwl_send_add_sta(priv, &station->sta, flags);
895 IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
896 sta_id, tx_rate);
897 return sta_id;
898 }
899
900 static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
901 {
902 if (src == IWL_PWR_SRC_VAUX) {
903 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
904 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
905 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
906 ~APMG_PS_CTRL_MSK_PWR_SRC);
907
908 iwl_poll_bit(priv, CSR_GPIO_IN,
909 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
910 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
911 }
912 } else {
913 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
914 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
915 ~APMG_PS_CTRL_MSK_PWR_SRC);
916
917 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
918 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
919 }
920
921 return 0;
922 }
923
924 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
925 {
926 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
927 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
928 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
929 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
930 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
931 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
932 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
933 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
934 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
935 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
936 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
937 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
938
939 /* fake read to flush all prev I/O */
940 iwl_read_direct32(priv, FH39_RSSR_CTRL);
941
942 return 0;
943 }
944
945 static int iwl3945_tx_reset(struct iwl_priv *priv)
946 {
947
948 /* bypass mode */
949 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
950
951 /* RA 0 is active */
952 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
953
954 /* all 6 fifo are active */
955 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
956
957 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
958 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
959 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
960 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
961
962 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
963 priv->shared_phys);
964
965 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
966 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
967 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
968 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
969 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
970 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
971 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
972 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
973
974
975 return 0;
976 }
977
978 /**
979 * iwl3945_txq_ctx_reset - Reset TX queue context
980 *
981 * Destroys all DMA structures and initialize them again
982 */
983 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
984 {
985 int rc;
986 int txq_id, slots_num;
987
988 iwl3945_hw_txq_ctx_free(priv);
989
990 /* allocate tx queue structure */
991 rc = iwl_alloc_txq_mem(priv);
992 if (rc)
993 return rc;
994
995 /* Tx CMD queue */
996 rc = iwl3945_tx_reset(priv);
997 if (rc)
998 goto error;
999
1000 /* Tx queue(s) */
1001 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1002 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1003 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
1004 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1005 txq_id);
1006 if (rc) {
1007 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
1008 goto error;
1009 }
1010 }
1011
1012 return rc;
1013
1014 error:
1015 iwl3945_hw_txq_ctx_free(priv);
1016 return rc;
1017 }
1018
1019
1020 /*
1021 * Start up 3945's basic functionality after it has been reset
1022 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
1023 * NOTE: This does not load uCode nor start the embedded processor
1024 */
1025 static int iwl3945_apm_init(struct iwl_priv *priv)
1026 {
1027 int ret = iwl_apm_init(priv);
1028
1029 /* Clear APMG (NIC's internal power management) interrupts */
1030 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1031 iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
1032
1033 /* Reset radio chip */
1034 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1035 udelay(5);
1036 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1037
1038 return ret;
1039 }
1040
1041 static void iwl3945_nic_config(struct iwl_priv *priv)
1042 {
1043 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1044 unsigned long flags;
1045 u8 rev_id = 0;
1046
1047 spin_lock_irqsave(&priv->lock, flags);
1048
1049 /* Determine HW type */
1050 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1051
1052 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
1053
1054 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1055 IWL_DEBUG_INFO(priv, "RTP type \n");
1056 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1057 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
1058 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1059 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
1060 } else {
1061 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
1062 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1063 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
1064 }
1065
1066 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
1067 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
1068 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1069 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1070 } else
1071 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
1072
1073 if ((eeprom->board_revision & 0xF0) == 0xD0) {
1074 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1075 eeprom->board_revision);
1076 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1077 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1078 } else {
1079 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1080 eeprom->board_revision);
1081 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1082 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1083 }
1084
1085 if (eeprom->almgor_m_version <= 1) {
1086 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1087 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1088 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
1089 eeprom->almgor_m_version);
1090 } else {
1091 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
1092 eeprom->almgor_m_version);
1093 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1094 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1095 }
1096 spin_unlock_irqrestore(&priv->lock, flags);
1097
1098 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1099 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
1100
1101 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1102 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
1103 }
1104
1105 int iwl3945_hw_nic_init(struct iwl_priv *priv)
1106 {
1107 int rc;
1108 unsigned long flags;
1109 struct iwl_rx_queue *rxq = &priv->rxq;
1110
1111 spin_lock_irqsave(&priv->lock, flags);
1112 priv->cfg->ops->lib->apm_ops.init(priv);
1113 spin_unlock_irqrestore(&priv->lock, flags);
1114
1115 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1116 if (rc)
1117 return rc;
1118
1119 priv->cfg->ops->lib->apm_ops.config(priv);
1120
1121 /* Allocate the RX queue, or reset if it is already allocated */
1122 if (!rxq->bd) {
1123 rc = iwl_rx_queue_alloc(priv);
1124 if (rc) {
1125 IWL_ERR(priv, "Unable to initialize Rx queue\n");
1126 return -ENOMEM;
1127 }
1128 } else
1129 iwl3945_rx_queue_reset(priv, rxq);
1130
1131 iwl3945_rx_replenish(priv);
1132
1133 iwl3945_rx_init(priv, rxq);
1134
1135
1136 /* Look at using this instead:
1137 rxq->need_update = 1;
1138 iwl_rx_queue_update_write_ptr(priv, rxq);
1139 */
1140
1141 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1142
1143 rc = iwl3945_txq_ctx_reset(priv);
1144 if (rc)
1145 return rc;
1146
1147 set_bit(STATUS_INIT, &priv->status);
1148
1149 return 0;
1150 }
1151
1152 /**
1153 * iwl3945_hw_txq_ctx_free - Free TXQ Context
1154 *
1155 * Destroy all TX DMA queues and structures
1156 */
1157 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1158 {
1159 int txq_id;
1160
1161 /* Tx queues */
1162 if (priv->txq)
1163 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1164 txq_id++)
1165 if (txq_id == IWL_CMD_QUEUE_NUM)
1166 iwl_cmd_queue_free(priv);
1167 else
1168 iwl_tx_queue_free(priv, txq_id);
1169
1170 /* free tx queue structure */
1171 iwl_free_txq_mem(priv);
1172 }
1173
1174 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1175 {
1176 int txq_id;
1177
1178 /* stop SCD */
1179 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1180 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0);
1181
1182 /* reset TFD queues */
1183 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1184 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1185 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1186 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1187 1000);
1188 }
1189
1190 iwl3945_hw_txq_ctx_free(priv);
1191 }
1192
1193 /**
1194 * iwl3945_hw_reg_adjust_power_by_temp
1195 * return index delta into power gain settings table
1196 */
1197 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1198 {
1199 return (new_reading - old_reading) * (-11) / 100;
1200 }
1201
1202 /**
1203 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1204 */
1205 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1206 {
1207 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1208 }
1209
1210 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1211 {
1212 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1213 }
1214
1215 /**
1216 * iwl3945_hw_reg_txpower_get_temperature
1217 * get the current temperature by reading from NIC
1218 */
1219 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1220 {
1221 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1222 int temperature;
1223
1224 temperature = iwl3945_hw_get_temperature(priv);
1225
1226 /* driver's okay range is -260 to +25.
1227 * human readable okay range is 0 to +285 */
1228 IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1229
1230 /* handle insane temp reading */
1231 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1232 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
1233
1234 /* if really really hot(?),
1235 * substitute the 3rd band/group's temp measured at factory */
1236 if (priv->last_temperature > 100)
1237 temperature = eeprom->groups[2].temperature;
1238 else /* else use most recent "sane" value from driver */
1239 temperature = priv->last_temperature;
1240 }
1241
1242 return temperature; /* raw, not "human readable" */
1243 }
1244
1245 /* Adjust Txpower only if temperature variance is greater than threshold.
1246 *
1247 * Both are lower than older versions' 9 degrees */
1248 #define IWL_TEMPERATURE_LIMIT_TIMER 6
1249
1250 /**
1251 * is_temp_calib_needed - determines if new calibration is needed
1252 *
1253 * records new temperature in tx_mgr->temperature.
1254 * replaces tx_mgr->last_temperature *only* if calib needed
1255 * (assumes caller will actually do the calibration!). */
1256 static int is_temp_calib_needed(struct iwl_priv *priv)
1257 {
1258 int temp_diff;
1259
1260 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1261 temp_diff = priv->temperature - priv->last_temperature;
1262
1263 /* get absolute value */
1264 if (temp_diff < 0) {
1265 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
1266 temp_diff = -temp_diff;
1267 } else if (temp_diff == 0)
1268 IWL_DEBUG_POWER(priv, "Same temp,\n");
1269 else
1270 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
1271
1272 /* if we don't need calibration, *don't* update last_temperature */
1273 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1274 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
1275 return 0;
1276 }
1277
1278 IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
1279
1280 /* assume that caller will actually do calib ...
1281 * update the "last temperature" value */
1282 priv->last_temperature = priv->temperature;
1283 return 1;
1284 }
1285
1286 #define IWL_MAX_GAIN_ENTRIES 78
1287 #define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1288 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1289
1290 /* radio and DSP power table, each step is 1/2 dB.
1291 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1292 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1293 {
1294 {251, 127}, /* 2.4 GHz, highest power */
1295 {251, 127},
1296 {251, 127},
1297 {251, 127},
1298 {251, 125},
1299 {251, 110},
1300 {251, 105},
1301 {251, 98},
1302 {187, 125},
1303 {187, 115},
1304 {187, 108},
1305 {187, 99},
1306 {243, 119},
1307 {243, 111},
1308 {243, 105},
1309 {243, 97},
1310 {243, 92},
1311 {211, 106},
1312 {211, 100},
1313 {179, 120},
1314 {179, 113},
1315 {179, 107},
1316 {147, 125},
1317 {147, 119},
1318 {147, 112},
1319 {147, 106},
1320 {147, 101},
1321 {147, 97},
1322 {147, 91},
1323 {115, 107},
1324 {235, 121},
1325 {235, 115},
1326 {235, 109},
1327 {203, 127},
1328 {203, 121},
1329 {203, 115},
1330 {203, 108},
1331 {203, 102},
1332 {203, 96},
1333 {203, 92},
1334 {171, 110},
1335 {171, 104},
1336 {171, 98},
1337 {139, 116},
1338 {227, 125},
1339 {227, 119},
1340 {227, 113},
1341 {227, 107},
1342 {227, 101},
1343 {227, 96},
1344 {195, 113},
1345 {195, 106},
1346 {195, 102},
1347 {195, 95},
1348 {163, 113},
1349 {163, 106},
1350 {163, 102},
1351 {163, 95},
1352 {131, 113},
1353 {131, 106},
1354 {131, 102},
1355 {131, 95},
1356 {99, 113},
1357 {99, 106},
1358 {99, 102},
1359 {99, 95},
1360 {67, 113},
1361 {67, 106},
1362 {67, 102},
1363 {67, 95},
1364 {35, 113},
1365 {35, 106},
1366 {35, 102},
1367 {35, 95},
1368 {3, 113},
1369 {3, 106},
1370 {3, 102},
1371 {3, 95} }, /* 2.4 GHz, lowest power */
1372 {
1373 {251, 127}, /* 5.x GHz, highest power */
1374 {251, 120},
1375 {251, 114},
1376 {219, 119},
1377 {219, 101},
1378 {187, 113},
1379 {187, 102},
1380 {155, 114},
1381 {155, 103},
1382 {123, 117},
1383 {123, 107},
1384 {123, 99},
1385 {123, 92},
1386 {91, 108},
1387 {59, 125},
1388 {59, 118},
1389 {59, 109},
1390 {59, 102},
1391 {59, 96},
1392 {59, 90},
1393 {27, 104},
1394 {27, 98},
1395 {27, 92},
1396 {115, 118},
1397 {115, 111},
1398 {115, 104},
1399 {83, 126},
1400 {83, 121},
1401 {83, 113},
1402 {83, 105},
1403 {83, 99},
1404 {51, 118},
1405 {51, 111},
1406 {51, 104},
1407 {51, 98},
1408 {19, 116},
1409 {19, 109},
1410 {19, 102},
1411 {19, 98},
1412 {19, 93},
1413 {171, 113},
1414 {171, 107},
1415 {171, 99},
1416 {139, 120},
1417 {139, 113},
1418 {139, 107},
1419 {139, 99},
1420 {107, 120},
1421 {107, 113},
1422 {107, 107},
1423 {107, 99},
1424 {75, 120},
1425 {75, 113},
1426 {75, 107},
1427 {75, 99},
1428 {43, 120},
1429 {43, 113},
1430 {43, 107},
1431 {43, 99},
1432 {11, 120},
1433 {11, 113},
1434 {11, 107},
1435 {11, 99},
1436 {131, 107},
1437 {131, 99},
1438 {99, 120},
1439 {99, 113},
1440 {99, 107},
1441 {99, 99},
1442 {67, 120},
1443 {67, 113},
1444 {67, 107},
1445 {67, 99},
1446 {35, 120},
1447 {35, 113},
1448 {35, 107},
1449 {35, 99},
1450 {3, 120} } /* 5.x GHz, lowest power */
1451 };
1452
1453 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1454 {
1455 if (index < 0)
1456 return 0;
1457 if (index >= IWL_MAX_GAIN_ENTRIES)
1458 return IWL_MAX_GAIN_ENTRIES - 1;
1459 return (u8) index;
1460 }
1461
1462 /* Kick off thermal recalibration check every 60 seconds */
1463 #define REG_RECALIB_PERIOD (60)
1464
1465 /**
1466 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1467 *
1468 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1469 * or 6 Mbit (OFDM) rates.
1470 */
1471 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1472 s32 rate_index, const s8 *clip_pwrs,
1473 struct iwl_channel_info *ch_info,
1474 int band_index)
1475 {
1476 struct iwl3945_scan_power_info *scan_power_info;
1477 s8 power;
1478 u8 power_index;
1479
1480 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1481
1482 /* use this channel group's 6Mbit clipping/saturation pwr,
1483 * but cap at regulatory scan power restriction (set during init
1484 * based on eeprom channel data) for this channel. */
1485 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1486
1487 /* further limit to user's max power preference.
1488 * FIXME: Other spectrum management power limitations do not
1489 * seem to apply?? */
1490 power = min(power, priv->tx_power_user_lmt);
1491 scan_power_info->requested_power = power;
1492
1493 /* find difference between new scan *power* and current "normal"
1494 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1495 * current "normal" temperature-compensated Tx power *index* for
1496 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1497 * *index*. */
1498 power_index = ch_info->power_info[rate_index].power_table_index
1499 - (power - ch_info->power_info
1500 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1501
1502 /* store reference index that we use when adjusting *all* scan
1503 * powers. So we can accommodate user (all channel) or spectrum
1504 * management (single channel) power changes "between" temperature
1505 * feedback compensation procedures.
1506 * don't force fit this reference index into gain table; it may be a
1507 * negative number. This will help avoid errors when we're at
1508 * the lower bounds (highest gains, for warmest temperatures)
1509 * of the table. */
1510
1511 /* don't exceed table bounds for "real" setting */
1512 power_index = iwl3945_hw_reg_fix_power_index(power_index);
1513
1514 scan_power_info->power_table_index = power_index;
1515 scan_power_info->tpc.tx_gain =
1516 power_gain_table[band_index][power_index].tx_gain;
1517 scan_power_info->tpc.dsp_atten =
1518 power_gain_table[band_index][power_index].dsp_atten;
1519 }
1520
1521 /**
1522 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1523 *
1524 * Configures power settings for all rates for the current channel,
1525 * using values from channel info struct, and send to NIC
1526 */
1527 static int iwl3945_send_tx_power(struct iwl_priv *priv)
1528 {
1529 int rate_idx, i;
1530 const struct iwl_channel_info *ch_info = NULL;
1531 struct iwl3945_txpowertable_cmd txpower = {
1532 .channel = priv->active_rxon.channel,
1533 };
1534
1535 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1536 ch_info = iwl_get_channel_info(priv,
1537 priv->band,
1538 le16_to_cpu(priv->active_rxon.channel));
1539 if (!ch_info) {
1540 IWL_ERR(priv,
1541 "Failed to get channel info for channel %d [%d]\n",
1542 le16_to_cpu(priv->active_rxon.channel), priv->band);
1543 return -EINVAL;
1544 }
1545
1546 if (!is_channel_valid(ch_info)) {
1547 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
1548 "non-Tx channel.\n");
1549 return 0;
1550 }
1551
1552 /* fill cmd with power settings for all rates for current channel */
1553 /* Fill OFDM rate */
1554 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1555 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1556
1557 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1558 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1559
1560 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1561 le16_to_cpu(txpower.channel),
1562 txpower.band,
1563 txpower.power[i].tpc.tx_gain,
1564 txpower.power[i].tpc.dsp_atten,
1565 txpower.power[i].rate);
1566 }
1567 /* Fill CCK rates */
1568 for (rate_idx = IWL_FIRST_CCK_RATE;
1569 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1570 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1571 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1572
1573 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1574 le16_to_cpu(txpower.channel),
1575 txpower.band,
1576 txpower.power[i].tpc.tx_gain,
1577 txpower.power[i].tpc.dsp_atten,
1578 txpower.power[i].rate);
1579 }
1580
1581 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1582 sizeof(struct iwl3945_txpowertable_cmd),
1583 &txpower);
1584
1585 }
1586
1587 /**
1588 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1589 * @ch_info: Channel to update. Uses power_info.requested_power.
1590 *
1591 * Replace requested_power and base_power_index ch_info fields for
1592 * one channel.
1593 *
1594 * Called if user or spectrum management changes power preferences.
1595 * Takes into account h/w and modulation limitations (clip power).
1596 *
1597 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1598 *
1599 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1600 * properly fill out the scan powers, and actual h/w gain settings,
1601 * and send changes to NIC
1602 */
1603 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1604 struct iwl_channel_info *ch_info)
1605 {
1606 struct iwl3945_channel_power_info *power_info;
1607 int power_changed = 0;
1608 int i;
1609 const s8 *clip_pwrs;
1610 int power;
1611
1612 /* Get this chnlgrp's rate-to-max/clip-powers table */
1613 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1614
1615 /* Get this channel's rate-to-current-power settings table */
1616 power_info = ch_info->power_info;
1617
1618 /* update OFDM Txpower settings */
1619 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1620 i++, ++power_info) {
1621 int delta_idx;
1622
1623 /* limit new power to be no more than h/w capability */
1624 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1625 if (power == power_info->requested_power)
1626 continue;
1627
1628 /* find difference between old and new requested powers,
1629 * update base (non-temp-compensated) power index */
1630 delta_idx = (power - power_info->requested_power) * 2;
1631 power_info->base_power_index -= delta_idx;
1632
1633 /* save new requested power value */
1634 power_info->requested_power = power;
1635
1636 power_changed = 1;
1637 }
1638
1639 /* update CCK Txpower settings, based on OFDM 12M setting ...
1640 * ... all CCK power settings for a given channel are the *same*. */
1641 if (power_changed) {
1642 power =
1643 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1644 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1645
1646 /* do all CCK rates' iwl3945_channel_power_info structures */
1647 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1648 power_info->requested_power = power;
1649 power_info->base_power_index =
1650 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1651 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1652 ++power_info;
1653 }
1654 }
1655
1656 return 0;
1657 }
1658
1659 /**
1660 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1661 *
1662 * NOTE: Returned power limit may be less (but not more) than requested,
1663 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1664 * (no consideration for h/w clipping limitations).
1665 */
1666 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1667 {
1668 s8 max_power;
1669
1670 #if 0
1671 /* if we're using TGd limits, use lower of TGd or EEPROM */
1672 if (ch_info->tgd_data.max_power != 0)
1673 max_power = min(ch_info->tgd_data.max_power,
1674 ch_info->eeprom.max_power_avg);
1675
1676 /* else just use EEPROM limits */
1677 else
1678 #endif
1679 max_power = ch_info->eeprom.max_power_avg;
1680
1681 return min(max_power, ch_info->max_power_avg);
1682 }
1683
1684 /**
1685 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1686 *
1687 * Compensate txpower settings of *all* channels for temperature.
1688 * This only accounts for the difference between current temperature
1689 * and the factory calibration temperatures, and bases the new settings
1690 * on the channel's base_power_index.
1691 *
1692 * If RxOn is "associated", this sends the new Txpower to NIC!
1693 */
1694 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1695 {
1696 struct iwl_channel_info *ch_info = NULL;
1697 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1698 int delta_index;
1699 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1700 u8 a_band;
1701 u8 rate_index;
1702 u8 scan_tbl_index;
1703 u8 i;
1704 int ref_temp;
1705 int temperature = priv->temperature;
1706
1707 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1708 for (i = 0; i < priv->channel_count; i++) {
1709 ch_info = &priv->channel_info[i];
1710 a_band = is_channel_a_band(ch_info);
1711
1712 /* Get this chnlgrp's factory calibration temperature */
1713 ref_temp = (s16)eeprom->groups[ch_info->group_index].
1714 temperature;
1715
1716 /* get power index adjustment based on current and factory
1717 * temps */
1718 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1719 ref_temp);
1720
1721 /* set tx power value for all rates, OFDM and CCK */
1722 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1723 rate_index++) {
1724 int power_idx =
1725 ch_info->power_info[rate_index].base_power_index;
1726
1727 /* temperature compensate */
1728 power_idx += delta_index;
1729
1730 /* stay within table range */
1731 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1732 ch_info->power_info[rate_index].
1733 power_table_index = (u8) power_idx;
1734 ch_info->power_info[rate_index].tpc =
1735 power_gain_table[a_band][power_idx];
1736 }
1737
1738 /* Get this chnlgrp's rate-to-max/clip-powers table */
1739 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1740
1741 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1742 for (scan_tbl_index = 0;
1743 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1744 s32 actual_index = (scan_tbl_index == 0) ?
1745 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1746 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1747 actual_index, clip_pwrs,
1748 ch_info, a_band);
1749 }
1750 }
1751
1752 /* send Txpower command for current channel to ucode */
1753 return priv->cfg->ops->lib->send_tx_power(priv);
1754 }
1755
1756 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1757 {
1758 struct iwl_channel_info *ch_info;
1759 s8 max_power;
1760 u8 a_band;
1761 u8 i;
1762
1763 if (priv->tx_power_user_lmt == power) {
1764 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
1765 "limit: %ddBm.\n", power);
1766 return 0;
1767 }
1768
1769 IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
1770 priv->tx_power_user_lmt = power;
1771
1772 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1773
1774 for (i = 0; i < priv->channel_count; i++) {
1775 ch_info = &priv->channel_info[i];
1776 a_band = is_channel_a_band(ch_info);
1777
1778 /* find minimum power of all user and regulatory constraints
1779 * (does not consider h/w clipping limitations) */
1780 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1781 max_power = min(power, max_power);
1782 if (max_power != ch_info->curr_txpow) {
1783 ch_info->curr_txpow = max_power;
1784
1785 /* this considers the h/w clipping limitations */
1786 iwl3945_hw_reg_set_new_power(priv, ch_info);
1787 }
1788 }
1789
1790 /* update txpower settings for all channels,
1791 * send to NIC if associated. */
1792 is_temp_calib_needed(priv);
1793 iwl3945_hw_reg_comp_txpower_temp(priv);
1794
1795 return 0;
1796 }
1797
1798 static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
1799 {
1800 int rc = 0;
1801 struct iwl_rx_packet *pkt;
1802 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1803 struct iwl_host_cmd cmd = {
1804 .id = REPLY_RXON_ASSOC,
1805 .len = sizeof(rxon_assoc),
1806 .flags = CMD_WANT_SKB,
1807 .data = &rxon_assoc,
1808 };
1809 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1810 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1811
1812 if ((rxon1->flags == rxon2->flags) &&
1813 (rxon1->filter_flags == rxon2->filter_flags) &&
1814 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1815 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1816 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1817 return 0;
1818 }
1819
1820 rxon_assoc.flags = priv->staging_rxon.flags;
1821 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1822 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1823 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1824 rxon_assoc.reserved = 0;
1825
1826 rc = iwl_send_cmd_sync(priv, &cmd);
1827 if (rc)
1828 return rc;
1829
1830 pkt = (struct iwl_rx_packet *)cmd.reply_page;
1831 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
1832 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1833 rc = -EIO;
1834 }
1835
1836 priv->alloc_rxb_page--;
1837 free_pages(cmd.reply_page, priv->hw_params.rx_page_order);
1838
1839 return rc;
1840 }
1841
1842 /**
1843 * iwl3945_commit_rxon - commit staging_rxon to hardware
1844 *
1845 * The RXON command in staging_rxon is committed to the hardware and
1846 * the active_rxon structure is updated with the new data. This
1847 * function correctly transitions out of the RXON_ASSOC_MSK state if
1848 * a HW tune is required based on the RXON structure changes.
1849 */
1850 static int iwl3945_commit_rxon(struct iwl_priv *priv)
1851 {
1852 /* cast away the const for active_rxon in this function */
1853 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1854 struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon;
1855 int rc = 0;
1856 bool new_assoc =
1857 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
1858
1859 if (!iwl_is_alive(priv))
1860 return -1;
1861
1862 /* always get timestamp with Rx frame */
1863 staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1864
1865 /* select antenna */
1866 staging_rxon->flags &=
1867 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1868 staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1869
1870 rc = iwl_check_rxon_cmd(priv);
1871 if (rc) {
1872 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
1873 return -EINVAL;
1874 }
1875
1876 /* If we don't need to send a full RXON, we can use
1877 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1878 * and other flags for the current radio configuration. */
1879 if (!iwl_full_rxon_required(priv)) {
1880 rc = iwl_send_rxon_assoc(priv);
1881 if (rc) {
1882 IWL_ERR(priv, "Error setting RXON_ASSOC "
1883 "configuration (%d).\n", rc);
1884 return rc;
1885 }
1886
1887 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1888
1889 return 0;
1890 }
1891
1892 /* If we are currently associated and the new config requires
1893 * an RXON_ASSOC and the new config wants the associated mask enabled,
1894 * we must clear the associated from the active configuration
1895 * before we apply the new config */
1896 if (iwl_is_associated(priv) && new_assoc) {
1897 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1898 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1899
1900 /*
1901 * reserved4 and 5 could have been filled by the iwlcore code.
1902 * Let's clear them before pushing to the 3945.
1903 */
1904 active_rxon->reserved4 = 0;
1905 active_rxon->reserved5 = 0;
1906 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1907 sizeof(struct iwl3945_rxon_cmd),
1908 &priv->active_rxon);
1909
1910 /* If the mask clearing failed then we set
1911 * active_rxon back to what it was previously */
1912 if (rc) {
1913 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1914 IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1915 "configuration (%d).\n", rc);
1916 return rc;
1917 }
1918 }
1919
1920 IWL_DEBUG_INFO(priv, "Sending RXON\n"
1921 "* with%s RXON_FILTER_ASSOC_MSK\n"
1922 "* channel = %d\n"
1923 "* bssid = %pM\n",
1924 (new_assoc ? "" : "out"),
1925 le16_to_cpu(staging_rxon->channel),
1926 staging_rxon->bssid_addr);
1927
1928 /*
1929 * reserved4 and 5 could have been filled by the iwlcore code.
1930 * Let's clear them before pushing to the 3945.
1931 */
1932 staging_rxon->reserved4 = 0;
1933 staging_rxon->reserved5 = 0;
1934
1935 iwl_set_rxon_hwcrypto(priv, !iwl3945_mod_params.sw_crypto);
1936
1937 /* Apply the new configuration */
1938 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1939 sizeof(struct iwl3945_rxon_cmd),
1940 staging_rxon);
1941 if (rc) {
1942 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1943 return rc;
1944 }
1945
1946 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1947
1948 iwl_clear_stations_table(priv);
1949
1950 /* If we issue a new RXON command which required a tune then we must
1951 * send a new TXPOWER command or we won't be able to Tx any frames */
1952 rc = priv->cfg->ops->lib->send_tx_power(priv);
1953 if (rc) {
1954 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1955 return rc;
1956 }
1957
1958 /* Add the broadcast address so we can send broadcast frames */
1959 if (iwl_add_station(priv, iwl_bcast_addr, false, CMD_SYNC, NULL) ==
1960 IWL_INVALID_STATION) {
1961 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
1962 return -EIO;
1963 }
1964
1965 /* If we have set the ASSOC_MSK and we are in BSS mode then
1966 * add the IWL_AP_ID to the station rate table */
1967 if (iwl_is_associated(priv) &&
1968 (priv->iw_mode == NL80211_IFTYPE_STATION))
1969 if (iwl_add_station(priv, priv->active_rxon.bssid_addr,
1970 true, CMD_SYNC, NULL) == IWL_INVALID_STATION) {
1971 IWL_ERR(priv, "Error adding AP address for transmit\n");
1972 return -EIO;
1973 }
1974
1975 /* Init the hardware's rate fallback order based on the band */
1976 rc = iwl3945_init_hw_rate_table(priv);
1977 if (rc) {
1978 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
1979 return -EIO;
1980 }
1981
1982 return 0;
1983 }
1984
1985 /**
1986 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1987 *
1988 * -- reset periodic timer
1989 * -- see if temp has changed enough to warrant re-calibration ... if so:
1990 * -- correct coeffs for temp (can reset temp timer)
1991 * -- save this temp as "last",
1992 * -- send new set of gain settings to NIC
1993 * NOTE: This should continue working, even when we're not associated,
1994 * so we can keep our internal table of scan powers current. */
1995 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
1996 {
1997 /* This will kick in the "brute force"
1998 * iwl3945_hw_reg_comp_txpower_temp() below */
1999 if (!is_temp_calib_needed(priv))
2000 goto reschedule;
2001
2002 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2003 * This is based *only* on current temperature,
2004 * ignoring any previous power measurements */
2005 iwl3945_hw_reg_comp_txpower_temp(priv);
2006
2007 reschedule:
2008 queue_delayed_work(priv->workqueue,
2009 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
2010 }
2011
2012 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
2013 {
2014 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2015 thermal_periodic.work);
2016
2017 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2018 return;
2019
2020 mutex_lock(&priv->mutex);
2021 iwl3945_reg_txpower_periodic(priv);
2022 mutex_unlock(&priv->mutex);
2023 }
2024
2025 /**
2026 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
2027 * for the channel.
2028 *
2029 * This function is used when initializing channel-info structs.
2030 *
2031 * NOTE: These channel groups do *NOT* match the bands above!
2032 * These channel groups are based on factory-tested channels;
2033 * on A-band, EEPROM's "group frequency" entries represent the top
2034 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2035 */
2036 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
2037 const struct iwl_channel_info *ch_info)
2038 {
2039 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2040 struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
2041 u8 group;
2042 u16 group_index = 0; /* based on factory calib frequencies */
2043 u8 grp_channel;
2044
2045 /* Find the group index for the channel ... don't use index 1(?) */
2046 if (is_channel_a_band(ch_info)) {
2047 for (group = 1; group < 5; group++) {
2048 grp_channel = ch_grp[group].group_channel;
2049 if (ch_info->channel <= grp_channel) {
2050 group_index = group;
2051 break;
2052 }
2053 }
2054 /* group 4 has a few channels *above* its factory cal freq */
2055 if (group == 5)
2056 group_index = 4;
2057 } else
2058 group_index = 0; /* 2.4 GHz, group 0 */
2059
2060 IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
2061 group_index);
2062 return group_index;
2063 }
2064
2065 /**
2066 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
2067 *
2068 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2069 * into radio/DSP gain settings table for requested power.
2070 */
2071 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
2072 s8 requested_power,
2073 s32 setting_index, s32 *new_index)
2074 {
2075 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
2076 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2077 s32 index0, index1;
2078 s32 power = 2 * requested_power;
2079 s32 i;
2080 const struct iwl3945_eeprom_txpower_sample *samples;
2081 s32 gains0, gains1;
2082 s32 res;
2083 s32 denominator;
2084
2085 chnl_grp = &eeprom->groups[setting_index];
2086 samples = chnl_grp->samples;
2087 for (i = 0; i < 5; i++) {
2088 if (power == samples[i].power) {
2089 *new_index = samples[i].gain_index;
2090 return 0;
2091 }
2092 }
2093
2094 if (power > samples[1].power) {
2095 index0 = 0;
2096 index1 = 1;
2097 } else if (power > samples[2].power) {
2098 index0 = 1;
2099 index1 = 2;
2100 } else if (power > samples[3].power) {
2101 index0 = 2;
2102 index1 = 3;
2103 } else {
2104 index0 = 3;
2105 index1 = 4;
2106 }
2107
2108 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2109 if (denominator == 0)
2110 return -EINVAL;
2111 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2112 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2113 res = gains0 + (gains1 - gains0) *
2114 ((s32) power - (s32) samples[index0].power) / denominator +
2115 (1 << 18);
2116 *new_index = res >> 19;
2117 return 0;
2118 }
2119
2120 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2121 {
2122 u32 i;
2123 s32 rate_index;
2124 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2125 const struct iwl3945_eeprom_txpower_group *group;
2126
2127 IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
2128
2129 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2130 s8 *clip_pwrs; /* table of power levels for each rate */
2131 s8 satur_pwr; /* saturation power for each chnl group */
2132 group = &eeprom->groups[i];
2133
2134 /* sanity check on factory saturation power value */
2135 if (group->saturation_power < 40) {
2136 IWL_WARN(priv, "Error: saturation power is %d, "
2137 "less than minimum expected 40\n",
2138 group->saturation_power);
2139 return;
2140 }
2141
2142 /*
2143 * Derive requested power levels for each rate, based on
2144 * hardware capabilities (saturation power for band).
2145 * Basic value is 3dB down from saturation, with further
2146 * power reductions for highest 3 data rates. These
2147 * backoffs provide headroom for high rate modulation
2148 * power peaks, without too much distortion (clipping).
2149 */
2150 /* we'll fill in this array with h/w max power levels */
2151 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
2152
2153 /* divide factory saturation power by 2 to find -3dB level */
2154 satur_pwr = (s8) (group->saturation_power >> 1);
2155
2156 /* fill in channel group's nominal powers for each rate */
2157 for (rate_index = 0;
2158 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2159 switch (rate_index) {
2160 case IWL_RATE_36M_INDEX_TABLE:
2161 if (i == 0) /* B/G */
2162 *clip_pwrs = satur_pwr;
2163 else /* A */
2164 *clip_pwrs = satur_pwr - 5;
2165 break;
2166 case IWL_RATE_48M_INDEX_TABLE:
2167 if (i == 0)
2168 *clip_pwrs = satur_pwr - 7;
2169 else
2170 *clip_pwrs = satur_pwr - 10;
2171 break;
2172 case IWL_RATE_54M_INDEX_TABLE:
2173 if (i == 0)
2174 *clip_pwrs = satur_pwr - 9;
2175 else
2176 *clip_pwrs = satur_pwr - 12;
2177 break;
2178 default:
2179 *clip_pwrs = satur_pwr;
2180 break;
2181 }
2182 }
2183 }
2184 }
2185
2186 /**
2187 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2188 *
2189 * Second pass (during init) to set up priv->channel_info
2190 *
2191 * Set up Tx-power settings in our channel info database for each VALID
2192 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2193 * and current temperature.
2194 *
2195 * Since this is based on current temperature (at init time), these values may
2196 * not be valid for very long, but it gives us a starting/default point,
2197 * and allows us to active (i.e. using Tx) scan.
2198 *
2199 * This does *not* write values to NIC, just sets up our internal table.
2200 */
2201 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2202 {
2203 struct iwl_channel_info *ch_info = NULL;
2204 struct iwl3945_channel_power_info *pwr_info;
2205 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2206 int delta_index;
2207 u8 rate_index;
2208 u8 scan_tbl_index;
2209 const s8 *clip_pwrs; /* array of power levels for each rate */
2210 u8 gain, dsp_atten;
2211 s8 power;
2212 u8 pwr_index, base_pwr_index, a_band;
2213 u8 i;
2214 int temperature;
2215
2216 /* save temperature reference,
2217 * so we can determine next time to calibrate */
2218 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2219 priv->last_temperature = temperature;
2220
2221 iwl3945_hw_reg_init_channel_groups(priv);
2222
2223 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2224 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2225 i++, ch_info++) {
2226 a_band = is_channel_a_band(ch_info);
2227 if (!is_channel_valid(ch_info))
2228 continue;
2229
2230 /* find this channel's channel group (*not* "band") index */
2231 ch_info->group_index =
2232 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2233
2234 /* Get this chnlgrp's rate->max/clip-powers table */
2235 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
2236
2237 /* calculate power index *adjustment* value according to
2238 * diff between current temperature and factory temperature */
2239 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2240 eeprom->groups[ch_info->group_index].
2241 temperature);
2242
2243 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
2244 ch_info->channel, delta_index, temperature +
2245 IWL_TEMP_CONVERT);
2246
2247 /* set tx power value for all OFDM rates */
2248 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2249 rate_index++) {
2250 s32 uninitialized_var(power_idx);
2251 int rc;
2252
2253 /* use channel group's clip-power table,
2254 * but don't exceed channel's max power */
2255 s8 pwr = min(ch_info->max_power_avg,
2256 clip_pwrs[rate_index]);
2257
2258 pwr_info = &ch_info->power_info[rate_index];
2259
2260 /* get base (i.e. at factory-measured temperature)
2261 * power table index for this rate's power */
2262 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2263 ch_info->group_index,
2264 &power_idx);
2265 if (rc) {
2266 IWL_ERR(priv, "Invalid power index\n");
2267 return rc;
2268 }
2269 pwr_info->base_power_index = (u8) power_idx;
2270
2271 /* temperature compensate */
2272 power_idx += delta_index;
2273
2274 /* stay within range of gain table */
2275 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2276
2277 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2278 pwr_info->requested_power = pwr;
2279 pwr_info->power_table_index = (u8) power_idx;
2280 pwr_info->tpc.tx_gain =
2281 power_gain_table[a_band][power_idx].tx_gain;
2282 pwr_info->tpc.dsp_atten =
2283 power_gain_table[a_band][power_idx].dsp_atten;
2284 }
2285
2286 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2287 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2288 power = pwr_info->requested_power +
2289 IWL_CCK_FROM_OFDM_POWER_DIFF;
2290 pwr_index = pwr_info->power_table_index +
2291 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2292 base_pwr_index = pwr_info->base_power_index +
2293 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2294
2295 /* stay within table range */
2296 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2297 gain = power_gain_table[a_band][pwr_index].tx_gain;
2298 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2299
2300 /* fill each CCK rate's iwl3945_channel_power_info structure
2301 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2302 * NOTE: CCK rates start at end of OFDM rates! */
2303 for (rate_index = 0;
2304 rate_index < IWL_CCK_RATES; rate_index++) {
2305 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2306 pwr_info->requested_power = power;
2307 pwr_info->power_table_index = pwr_index;
2308 pwr_info->base_power_index = base_pwr_index;
2309 pwr_info->tpc.tx_gain = gain;
2310 pwr_info->tpc.dsp_atten = dsp_atten;
2311 }
2312
2313 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2314 for (scan_tbl_index = 0;
2315 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2316 s32 actual_index = (scan_tbl_index == 0) ?
2317 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2318 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2319 actual_index, clip_pwrs, ch_info, a_band);
2320 }
2321 }
2322
2323 return 0;
2324 }
2325
2326 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2327 {
2328 int rc;
2329
2330 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2331 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2332 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2333 if (rc < 0)
2334 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2335
2336 return 0;
2337 }
2338
2339 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2340 {
2341 int txq_id = txq->q.id;
2342
2343 struct iwl3945_shared *shared_data = priv->shared_virt;
2344
2345 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2346
2347 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2348 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2349
2350 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2351 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2352 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2353 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2354 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2355 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2356
2357 /* fake read to flush all prev. writes */
2358 iwl_read32(priv, FH39_TSSR_CBB_BASE);
2359
2360 return 0;
2361 }
2362
2363 /*
2364 * HCMD utils
2365 */
2366 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2367 {
2368 switch (cmd_id) {
2369 case REPLY_RXON:
2370 return sizeof(struct iwl3945_rxon_cmd);
2371 case POWER_TABLE_CMD:
2372 return sizeof(struct iwl3945_powertable_cmd);
2373 default:
2374 return len;
2375 }
2376 }
2377
2378
2379 static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2380 {
2381 struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2382 addsta->mode = cmd->mode;
2383 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2384 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2385 addsta->station_flags = cmd->station_flags;
2386 addsta->station_flags_msk = cmd->station_flags_msk;
2387 addsta->tid_disable_tx = cpu_to_le16(0);
2388 addsta->rate_n_flags = cmd->rate_n_flags;
2389 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2390 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2391 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2392
2393 return (u16)sizeof(struct iwl3945_addsta_cmd);
2394 }
2395
2396
2397 /**
2398 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2399 */
2400 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2401 {
2402 int rc, i, index, prev_index;
2403 struct iwl3945_rate_scaling_cmd rate_cmd = {
2404 .reserved = {0, 0, 0},
2405 };
2406 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2407
2408 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2409 index = iwl3945_rates[i].table_rs_index;
2410
2411 table[index].rate_n_flags =
2412 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2413 table[index].try_cnt = priv->retry_rate;
2414 prev_index = iwl3945_get_prev_ieee_rate(i);
2415 table[index].next_rate_index =
2416 iwl3945_rates[prev_index].table_rs_index;
2417 }
2418
2419 switch (priv->band) {
2420 case IEEE80211_BAND_5GHZ:
2421 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
2422 /* If one of the following CCK rates is used,
2423 * have it fall back to the 6M OFDM rate */
2424 for (i = IWL_RATE_1M_INDEX_TABLE;
2425 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2426 table[i].next_rate_index =
2427 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2428
2429 /* Don't fall back to CCK rates */
2430 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2431 IWL_RATE_9M_INDEX_TABLE;
2432
2433 /* Don't drop out of OFDM rates */
2434 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2435 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2436 break;
2437
2438 case IEEE80211_BAND_2GHZ:
2439 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
2440 /* If an OFDM rate is used, have it fall back to the
2441 * 1M CCK rates */
2442
2443 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2444 iwl_is_associated(priv)) {
2445
2446 index = IWL_FIRST_CCK_RATE;
2447 for (i = IWL_RATE_6M_INDEX_TABLE;
2448 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2449 table[i].next_rate_index =
2450 iwl3945_rates[index].table_rs_index;
2451
2452 index = IWL_RATE_11M_INDEX_TABLE;
2453 /* CCK shouldn't fall back to OFDM... */
2454 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2455 }
2456 break;
2457
2458 default:
2459 WARN_ON(1);
2460 break;
2461 }
2462
2463 /* Update the rate scaling for control frame Tx */
2464 rate_cmd.table_id = 0;
2465 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2466 &rate_cmd);
2467 if (rc)
2468 return rc;
2469
2470 /* Update the rate scaling for data frame Tx */
2471 rate_cmd.table_id = 1;
2472 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2473 &rate_cmd);
2474 }
2475
2476 /* Called when initializing driver */
2477 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2478 {
2479 memset((void *)&priv->hw_params, 0,
2480 sizeof(struct iwl_hw_params));
2481
2482 priv->shared_virt =
2483 pci_alloc_consistent(priv->pci_dev,
2484 sizeof(struct iwl3945_shared),
2485 &priv->shared_phys);
2486
2487 if (!priv->shared_virt) {
2488 IWL_ERR(priv, "failed to allocate pci memory\n");
2489 mutex_unlock(&priv->mutex);
2490 return -ENOMEM;
2491 }
2492
2493 /* Assign number of Usable TX queues */
2494 priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
2495
2496 priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2497 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K);
2498 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2499 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2500 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2501 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
2502
2503 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2504 priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
2505
2506 return 0;
2507 }
2508
2509 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2510 struct iwl3945_frame *frame, u8 rate)
2511 {
2512 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2513 unsigned int frame_size;
2514
2515 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2516 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2517
2518 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2519 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2520
2521 frame_size = iwl3945_fill_beacon_frame(priv,
2522 tx_beacon_cmd->frame,
2523 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2524
2525 BUG_ON(frame_size > MAX_MPDU_SIZE);
2526 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2527
2528 tx_beacon_cmd->tx.rate = rate;
2529 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2530 TX_CMD_FLG_TSF_MSK);
2531
2532 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2533 tx_beacon_cmd->tx.supp_rates[0] =
2534 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2535
2536 tx_beacon_cmd->tx.supp_rates[1] =
2537 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2538
2539 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2540 }
2541
2542 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2543 {
2544 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2545 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2546 }
2547
2548 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2549 {
2550 INIT_DELAYED_WORK(&priv->thermal_periodic,
2551 iwl3945_bg_reg_txpower_periodic);
2552 }
2553
2554 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2555 {
2556 cancel_delayed_work(&priv->thermal_periodic);
2557 }
2558
2559 /* check contents of special bootstrap uCode SRAM */
2560 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2561 {
2562 __le32 *image = priv->ucode_boot.v_addr;
2563 u32 len = priv->ucode_boot.len;
2564 u32 reg;
2565 u32 val;
2566
2567 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
2568
2569 /* verify BSM SRAM contents */
2570 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2571 for (reg = BSM_SRAM_LOWER_BOUND;
2572 reg < BSM_SRAM_LOWER_BOUND + len;
2573 reg += sizeof(u32), image++) {
2574 val = iwl_read_prph(priv, reg);
2575 if (val != le32_to_cpu(*image)) {
2576 IWL_ERR(priv, "BSM uCode verification failed at "
2577 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2578 BSM_SRAM_LOWER_BOUND,
2579 reg - BSM_SRAM_LOWER_BOUND, len,
2580 val, le32_to_cpu(*image));
2581 return -EIO;
2582 }
2583 }
2584
2585 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
2586
2587 return 0;
2588 }
2589
2590
2591 /******************************************************************************
2592 *
2593 * EEPROM related functions
2594 *
2595 ******************************************************************************/
2596
2597 /*
2598 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2599 * embedded controller) as EEPROM reader; each read is a series of pulses
2600 * to/from the EEPROM chip, not a single event, so even reads could conflict
2601 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2602 * simply claims ownership, which should be safe when this function is called
2603 * (i.e. before loading uCode!).
2604 */
2605 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2606 {
2607 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2608 return 0;
2609 }
2610
2611
2612 static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2613 {
2614 return;
2615 }
2616
2617 /**
2618 * iwl3945_load_bsm - Load bootstrap instructions
2619 *
2620 * BSM operation:
2621 *
2622 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2623 * in special SRAM that does not power down during RFKILL. When powering back
2624 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2625 * the bootstrap program into the on-board processor, and starts it.
2626 *
2627 * The bootstrap program loads (via DMA) instructions and data for a new
2628 * program from host DRAM locations indicated by the host driver in the
2629 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2630 * automatically.
2631 *
2632 * When initializing the NIC, the host driver points the BSM to the
2633 * "initialize" uCode image. This uCode sets up some internal data, then
2634 * notifies host via "initialize alive" that it is complete.
2635 *
2636 * The host then replaces the BSM_DRAM_* pointer values to point to the
2637 * normal runtime uCode instructions and a backup uCode data cache buffer
2638 * (filled initially with starting data values for the on-board processor),
2639 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2640 * which begins normal operation.
2641 *
2642 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2643 * the backup data cache in DRAM before SRAM is powered down.
2644 *
2645 * When powering back up, the BSM loads the bootstrap program. This reloads
2646 * the runtime uCode instructions and the backup data cache into SRAM,
2647 * and re-launches the runtime uCode from where it left off.
2648 */
2649 static int iwl3945_load_bsm(struct iwl_priv *priv)
2650 {
2651 __le32 *image = priv->ucode_boot.v_addr;
2652 u32 len = priv->ucode_boot.len;
2653 dma_addr_t pinst;
2654 dma_addr_t pdata;
2655 u32 inst_len;
2656 u32 data_len;
2657 int rc;
2658 int i;
2659 u32 done;
2660 u32 reg_offset;
2661
2662 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
2663
2664 /* make sure bootstrap program is no larger than BSM's SRAM size */
2665 if (len > IWL39_MAX_BSM_SIZE)
2666 return -EINVAL;
2667
2668 /* Tell bootstrap uCode where to find the "Initialize" uCode
2669 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2670 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2671 * after the "initialize" uCode has run, to point to
2672 * runtime/protocol instructions and backup data cache. */
2673 pinst = priv->ucode_init.p_addr;
2674 pdata = priv->ucode_init_data.p_addr;
2675 inst_len = priv->ucode_init.len;
2676 data_len = priv->ucode_init_data.len;
2677
2678 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2679 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2680 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2681 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2682
2683 /* Fill BSM memory with bootstrap instructions */
2684 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2685 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2686 reg_offset += sizeof(u32), image++)
2687 _iwl_write_prph(priv, reg_offset,
2688 le32_to_cpu(*image));
2689
2690 rc = iwl3945_verify_bsm(priv);
2691 if (rc)
2692 return rc;
2693
2694 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2695 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2696 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2697 IWL39_RTC_INST_LOWER_BOUND);
2698 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2699
2700 /* Load bootstrap code into instruction SRAM now,
2701 * to prepare to load "initialize" uCode */
2702 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2703 BSM_WR_CTRL_REG_BIT_START);
2704
2705 /* Wait for load of bootstrap uCode to finish */
2706 for (i = 0; i < 100; i++) {
2707 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2708 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2709 break;
2710 udelay(10);
2711 }
2712 if (i < 100)
2713 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
2714 else {
2715 IWL_ERR(priv, "BSM write did not complete!\n");
2716 return -EIO;
2717 }
2718
2719 /* Enable future boot loads whenever power management unit triggers it
2720 * (e.g. when powering back up after power-save shutdown) */
2721 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2722 BSM_WR_CTRL_REG_BIT_START_EN);
2723
2724 return 0;
2725 }
2726
2727 #define IWL3945_UCODE_GET(item) \
2728 static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2729 u32 api_ver) \
2730 { \
2731 return le32_to_cpu(ucode->u.v1.item); \
2732 }
2733
2734 static u32 iwl3945_ucode_get_header_size(u32 api_ver)
2735 {
2736 return UCODE_HEADER_SIZE(1);
2737 }
2738 static u32 iwl3945_ucode_get_build(const struct iwl_ucode_header *ucode,
2739 u32 api_ver)
2740 {
2741 return 0;
2742 }
2743 static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode,
2744 u32 api_ver)
2745 {
2746 return (u8 *) ucode->u.v1.data;
2747 }
2748
2749 IWL3945_UCODE_GET(inst_size);
2750 IWL3945_UCODE_GET(data_size);
2751 IWL3945_UCODE_GET(init_size);
2752 IWL3945_UCODE_GET(init_data_size);
2753 IWL3945_UCODE_GET(boot_size);
2754
2755 static struct iwl_hcmd_ops iwl3945_hcmd = {
2756 .rxon_assoc = iwl3945_send_rxon_assoc,
2757 .commit_rxon = iwl3945_commit_rxon,
2758 };
2759
2760 static struct iwl_ucode_ops iwl3945_ucode = {
2761 .get_header_size = iwl3945_ucode_get_header_size,
2762 .get_build = iwl3945_ucode_get_build,
2763 .get_inst_size = iwl3945_ucode_get_inst_size,
2764 .get_data_size = iwl3945_ucode_get_data_size,
2765 .get_init_size = iwl3945_ucode_get_init_size,
2766 .get_init_data_size = iwl3945_ucode_get_init_data_size,
2767 .get_boot_size = iwl3945_ucode_get_boot_size,
2768 .get_data = iwl3945_ucode_get_data,
2769 };
2770
2771 static struct iwl_lib_ops iwl3945_lib = {
2772 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2773 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2774 .txq_init = iwl3945_hw_tx_queue_init,
2775 .load_ucode = iwl3945_load_bsm,
2776 .dump_nic_event_log = iwl3945_dump_nic_event_log,
2777 .dump_nic_error_log = iwl3945_dump_nic_error_log,
2778 .apm_ops = {
2779 .init = iwl3945_apm_init,
2780 .stop = iwl_apm_stop,
2781 .config = iwl3945_nic_config,
2782 .set_pwr_src = iwl3945_set_pwr_src,
2783 },
2784 .eeprom_ops = {
2785 .regulatory_bands = {
2786 EEPROM_REGULATORY_BAND_1_CHANNELS,
2787 EEPROM_REGULATORY_BAND_2_CHANNELS,
2788 EEPROM_REGULATORY_BAND_3_CHANNELS,
2789 EEPROM_REGULATORY_BAND_4_CHANNELS,
2790 EEPROM_REGULATORY_BAND_5_CHANNELS,
2791 EEPROM_REGULATORY_BAND_NO_HT40,
2792 EEPROM_REGULATORY_BAND_NO_HT40,
2793 },
2794 .verify_signature = iwlcore_eeprom_verify_signature,
2795 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2796 .release_semaphore = iwl3945_eeprom_release_semaphore,
2797 .query_addr = iwlcore_eeprom_query_addr,
2798 },
2799 .send_tx_power = iwl3945_send_tx_power,
2800 .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
2801 .post_associate = iwl3945_post_associate,
2802 .isr = iwl_isr_legacy,
2803 .config_ap = iwl3945_config_ap,
2804 };
2805
2806 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2807 .get_hcmd_size = iwl3945_get_hcmd_size,
2808 .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
2809 .rts_tx_cmd_flag = iwlcore_rts_tx_cmd_flag,
2810 };
2811
2812 static struct iwl_ops iwl3945_ops = {
2813 .ucode = &iwl3945_ucode,
2814 .lib = &iwl3945_lib,
2815 .hcmd = &iwl3945_hcmd,
2816 .utils = &iwl3945_hcmd_utils,
2817 .led = &iwl3945_led_ops,
2818 };
2819
2820 static struct iwl_cfg iwl3945_bg_cfg = {
2821 .name = "3945BG",
2822 .fw_name_pre = IWL3945_FW_PRE,
2823 .ucode_api_max = IWL3945_UCODE_API_MAX,
2824 .ucode_api_min = IWL3945_UCODE_API_MIN,
2825 .sku = IWL_SKU_G,
2826 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2827 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2828 .ops = &iwl3945_ops,
2829 .num_of_queues = IWL39_NUM_QUEUES,
2830 .mod_params = &iwl3945_mod_params,
2831 .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2832 .set_l0s = false,
2833 .use_bsm = true,
2834 .use_isr_legacy = true,
2835 .ht_greenfield_support = false,
2836 .led_compensation = 64,
2837 };
2838
2839 static struct iwl_cfg iwl3945_abg_cfg = {
2840 .name = "3945ABG",
2841 .fw_name_pre = IWL3945_FW_PRE,
2842 .ucode_api_max = IWL3945_UCODE_API_MAX,
2843 .ucode_api_min = IWL3945_UCODE_API_MIN,
2844 .sku = IWL_SKU_A|IWL_SKU_G,
2845 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2846 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2847 .ops = &iwl3945_ops,
2848 .num_of_queues = IWL39_NUM_QUEUES,
2849 .mod_params = &iwl3945_mod_params,
2850 .use_isr_legacy = true,
2851 .ht_greenfield_support = false,
2852 .led_compensation = 64,
2853 };
2854
2855 struct pci_device_id iwl3945_hw_card_ids[] = {
2856 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2857 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2858 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2859 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2860 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2861 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2862 {0}
2863 };
2864
2865 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
AMDTP streaming driver for the Linux FireWire stack (Juju)