?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ALSA: hda - Add a position_fix quirk for MSI Wind U115
[firewire-audio.git] / sound / pci / hda / hda_intel.c
blob238651bab3f586a857008d75b539a0eec7dfb882
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <asm/io.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <linux/reboot.h>
49 #include <sound/core.h>
50 #include <sound/initval.h>
51 #include "hda_codec.h"
52
53
54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57 static char *model[SNDRV_CARDS];
58 static int position_fix[SNDRV_CARDS];
59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
61 static int probe_only[SNDRV_CARDS];
62 static int single_cmd;
63 static int enable_msi = -1;
64 #ifdef CONFIG_SND_HDA_PATCH_LOADER
65 static char *patch[SNDRV_CARDS];
66 #endif
67 #ifdef CONFIG_SND_HDA_INPUT_BEEP
68 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
69 CONFIG_SND_HDA_INPUT_BEEP_MODE};
70 #endif
71
72 module_param_array(index, int, NULL, 0444);
73 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
74 module_param_array(id, charp, NULL, 0444);
75 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
76 module_param_array(enable, bool, NULL, 0444);
77 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
78 module_param_array(model, charp, NULL, 0444);
79 MODULE_PARM_DESC(model, "Use the given board model.");
80 module_param_array(position_fix, int, NULL, 0444);
81 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
82 "(0 = auto, 1 = none, 2 = POSBUF).");
83 module_param_array(bdl_pos_adj, int, NULL, 0644);
84 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
85 module_param_array(probe_mask, int, NULL, 0444);
86 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
87 module_param_array(probe_only, bool, NULL, 0444);
88 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
89 module_param(single_cmd, bool, 0444);
90 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
91 "(for debugging only).");
92 module_param(enable_msi, int, 0444);
93 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
94 #ifdef CONFIG_SND_HDA_PATCH_LOADER
95 module_param_array(patch, charp, NULL, 0444);
96 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
97 #endif
98 #ifdef CONFIG_SND_HDA_INPUT_BEEP
99 module_param_array(beep_mode, int, NULL, 0444);
100 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
101 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
102 #endif
103
104 #ifdef CONFIG_SND_HDA_POWER_SAVE
105 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
106 module_param(power_save, int, 0644);
107 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
108 "(in second, 0 = disable).");
109
110 /* reset the HD-audio controller in power save mode.
111 * this may give more power-saving, but will take longer time to
112 * wake up.
113 */
114 static int power_save_controller = 1;
115 module_param(power_save_controller, bool, 0644);
116 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
117 #endif
118
119 MODULE_LICENSE("GPL");
120 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
121 "{Intel, ICH6M},"
122 "{Intel, ICH7},"
123 "{Intel, ESB2},"
124 "{Intel, ICH8},"
125 "{Intel, ICH9},"
126 "{Intel, ICH10},"
127 "{Intel, PCH},"
128 "{Intel, SCH},"
129 "{ATI, SB450},"
130 "{ATI, SB600},"
131 "{ATI, RS600},"
132 "{ATI, RS690},"
133 "{ATI, RS780},"
134 "{ATI, R600},"
135 "{ATI, RV630},"
136 "{ATI, RV610},"
137 "{ATI, RV670},"
138 "{ATI, RV635},"
139 "{ATI, RV620},"
140 "{ATI, RV770},"
141 "{VIA, VT8251},"
142 "{VIA, VT8237A},"
143 "{SiS, SIS966},"
144 "{ULI, M5461}}");
145 MODULE_DESCRIPTION("Intel HDA driver");
146
147 #ifdef CONFIG_SND_VERBOSE_PRINTK
148 #define SFX /* nop */
149 #else
150 #define SFX "hda-intel: "
151 #endif
152
153 /*
154 * registers
155 */
156 #define ICH6_REG_GCAP 0x00
157 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
158 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
159 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
160 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
161 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
162 #define ICH6_REG_VMIN 0x02
163 #define ICH6_REG_VMAJ 0x03
164 #define ICH6_REG_OUTPAY 0x04
165 #define ICH6_REG_INPAY 0x06
166 #define ICH6_REG_GCTL 0x08
167 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
168 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
169 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
170 #define ICH6_REG_WAKEEN 0x0c
171 #define ICH6_REG_STATESTS 0x0e
172 #define ICH6_REG_GSTS 0x10
173 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
174 #define ICH6_REG_INTCTL 0x20
175 #define ICH6_REG_INTSTS 0x24
176 #define ICH6_REG_WALCLK 0x30
177 #define ICH6_REG_SYNC 0x34
178 #define ICH6_REG_CORBLBASE 0x40
179 #define ICH6_REG_CORBUBASE 0x44
180 #define ICH6_REG_CORBWP 0x48
181 #define ICH6_REG_CORBRP 0x4a
182 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
183 #define ICH6_REG_CORBCTL 0x4c
184 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
185 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
186 #define ICH6_REG_CORBSTS 0x4d
187 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
188 #define ICH6_REG_CORBSIZE 0x4e
189
190 #define ICH6_REG_RIRBLBASE 0x50
191 #define ICH6_REG_RIRBUBASE 0x54
192 #define ICH6_REG_RIRBWP 0x58
193 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
194 #define ICH6_REG_RINTCNT 0x5a
195 #define ICH6_REG_RIRBCTL 0x5c
196 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
197 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
198 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
199 #define ICH6_REG_RIRBSTS 0x5d
200 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
201 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
202 #define ICH6_REG_RIRBSIZE 0x5e
203
204 #define ICH6_REG_IC 0x60
205 #define ICH6_REG_IR 0x64
206 #define ICH6_REG_IRS 0x68
207 #define ICH6_IRS_VALID (1<<1)
208 #define ICH6_IRS_BUSY (1<<0)
209
210 #define ICH6_REG_DPLBASE 0x70
211 #define ICH6_REG_DPUBASE 0x74
212 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
213
214 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
215 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
216
217 /* stream register offsets from stream base */
218 #define ICH6_REG_SD_CTL 0x00
219 #define ICH6_REG_SD_STS 0x03
220 #define ICH6_REG_SD_LPIB 0x04
221 #define ICH6_REG_SD_CBL 0x08
222 #define ICH6_REG_SD_LVI 0x0c
223 #define ICH6_REG_SD_FIFOW 0x0e
224 #define ICH6_REG_SD_FIFOSIZE 0x10
225 #define ICH6_REG_SD_FORMAT 0x12
226 #define ICH6_REG_SD_BDLPL 0x18
227 #define ICH6_REG_SD_BDLPU 0x1c
228
229 /* PCI space */
230 #define ICH6_PCIREG_TCSEL 0x44
231
232 /*
233 * other constants
234 */
235
236 /* max number of SDs */
237 /* ICH, ATI and VIA have 4 playback and 4 capture */
238 #define ICH6_NUM_CAPTURE 4
239 #define ICH6_NUM_PLAYBACK 4
240
241 /* ULI has 6 playback and 5 capture */
242 #define ULI_NUM_CAPTURE 5
243 #define ULI_NUM_PLAYBACK 6
244
245 /* ATI HDMI has 1 playback and 0 capture */
246 #define ATIHDMI_NUM_CAPTURE 0
247 #define ATIHDMI_NUM_PLAYBACK 1
248
249 /* TERA has 4 playback and 3 capture */
250 #define TERA_NUM_CAPTURE 3
251 #define TERA_NUM_PLAYBACK 4
252
253 /* this number is statically defined for simplicity */
254 #define MAX_AZX_DEV 16
255
256 /* max number of fragments - we may use more if allocating more pages for BDL */
257 #define BDL_SIZE 4096
258 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
259 #define AZX_MAX_FRAG 32
260 /* max buffer size - no h/w limit, you can increase as you like */
261 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
262 /* max number of PCM devics per card */
263 #define AZX_MAX_PCMS 8
264
265 /* RIRB int mask: overrun[2], response[0] */
266 #define RIRB_INT_RESPONSE 0x01
267 #define RIRB_INT_OVERRUN 0x04
268 #define RIRB_INT_MASK 0x05
269
270 /* STATESTS int mask: S3,SD2,SD1,SD0 */
271 #define AZX_MAX_CODECS 4
272 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
273
274 /* SD_CTL bits */
275 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
276 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
277 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
278 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
279 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
280 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
281 #define SD_CTL_STREAM_TAG_SHIFT 20
282
283 /* SD_CTL and SD_STS */
284 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
285 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
286 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
287 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
288 SD_INT_COMPLETE)
289
290 /* SD_STS */
291 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
292
293 /* INTCTL and INTSTS */
294 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
295 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
296 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
297
298 /* below are so far hardcoded - should read registers in future */
299 #define ICH6_MAX_CORB_ENTRIES 256
300 #define ICH6_MAX_RIRB_ENTRIES 256
301
302 /* position fix mode */
303 enum {
304 POS_FIX_AUTO,
305 POS_FIX_LPIB,
306 POS_FIX_POSBUF,
307 };
308
309 /* Defines for ATI HD Audio support in SB450 south bridge */
310 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
311 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
312
313 /* Defines for Nvidia HDA support */
314 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
315 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
316 #define NVIDIA_HDA_ISTRM_COH 0x4d
317 #define NVIDIA_HDA_OSTRM_COH 0x4c
318 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
319
320 /* Defines for Intel SCH HDA snoop control */
321 #define INTEL_SCH_HDA_DEVC 0x78
322 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
323
324 /* Define IN stream 0 FIFO size offset in VIA controller */
325 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
326 /* Define VIA HD Audio Device ID*/
327 #define VIA_HDAC_DEVICE_ID 0x3288
328
329 /* HD Audio class code */
330 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
331
332 /*
333 */
334
335 struct azx_dev {
336 struct snd_dma_buffer bdl; /* BDL buffer */
337 u32 *posbuf; /* position buffer pointer */
338
339 unsigned int bufsize; /* size of the play buffer in bytes */
340 unsigned int period_bytes; /* size of the period in bytes */
341 unsigned int frags; /* number for period in the play buffer */
342 unsigned int fifo_size; /* FIFO size */
343 unsigned long start_jiffies; /* start + minimum jiffies */
344 unsigned long min_jiffies; /* minimum jiffies before position is valid */
345
346 void __iomem *sd_addr; /* stream descriptor pointer */
347
348 u32 sd_int_sta_mask; /* stream int status mask */
349
350 /* pcm support */
351 struct snd_pcm_substream *substream; /* assigned substream,
352 * set in PCM open
353 */
354 unsigned int format_val; /* format value to be set in the
355 * controller and the codec
356 */
357 unsigned char stream_tag; /* assigned stream */
358 unsigned char index; /* stream index */
359
360 unsigned int opened :1;
361 unsigned int running :1;
362 unsigned int irq_pending :1;
363 unsigned int start_flag: 1; /* stream full start flag */
364 /*
365 * For VIA:
366 * A flag to ensure DMA position is 0
367 * when link position is not greater than FIFO size
368 */
369 unsigned int insufficient :1;
370 };
371
372 /* CORB/RIRB */
373 struct azx_rb {
374 u32 *buf; /* CORB/RIRB buffer
375 * Each CORB entry is 4byte, RIRB is 8byte
376 */
377 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
378 /* for RIRB */
379 unsigned short rp, wp; /* read/write pointers */
380 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
381 u32 res[AZX_MAX_CODECS]; /* last read value */
382 };
383
384 struct azx {
385 struct snd_card *card;
386 struct pci_dev *pci;
387 int dev_index;
388
389 /* chip type specific */
390 int driver_type;
391 int playback_streams;
392 int playback_index_offset;
393 int capture_streams;
394 int capture_index_offset;
395 int num_streams;
396
397 /* pci resources */
398 unsigned long addr;
399 void __iomem *remap_addr;
400 int irq;
401
402 /* locks */
403 spinlock_t reg_lock;
404 struct mutex open_mutex;
405
406 /* streams (x num_streams) */
407 struct azx_dev *azx_dev;
408
409 /* PCM */
410 struct snd_pcm *pcm[AZX_MAX_PCMS];
411
412 /* HD codec */
413 unsigned short codec_mask;
414 int codec_probe_mask; /* copied from probe_mask option */
415 struct hda_bus *bus;
416 unsigned int beep_mode;
417
418 /* CORB/RIRB */
419 struct azx_rb corb;
420 struct azx_rb rirb;
421
422 /* CORB/RIRB and position buffers */
423 struct snd_dma_buffer rb;
424 struct snd_dma_buffer posbuf;
425
426 /* flags */
427 int position_fix;
428 unsigned int running :1;
429 unsigned int initialized :1;
430 unsigned int single_cmd :1;
431 unsigned int polling_mode :1;
432 unsigned int msi :1;
433 unsigned int irq_pending_warned :1;
434 unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
435 unsigned int probing :1; /* codec probing phase */
436
437 /* for debugging */
438 unsigned int last_cmd[AZX_MAX_CODECS];
439
440 /* for pending irqs */
441 struct work_struct irq_pending_work;
442
443 /* reboot notifier (for mysterious hangup problem at power-down) */
444 struct notifier_block reboot_notifier;
445 };
446
447 /* driver types */
448 enum {
449 AZX_DRIVER_ICH,
450 AZX_DRIVER_SCH,
451 AZX_DRIVER_ATI,
452 AZX_DRIVER_ATIHDMI,
453 AZX_DRIVER_VIA,
454 AZX_DRIVER_SIS,
455 AZX_DRIVER_ULI,
456 AZX_DRIVER_NVIDIA,
457 AZX_DRIVER_TERA,
458 AZX_DRIVER_GENERIC,
459 AZX_NUM_DRIVERS, /* keep this as last entry */
460 };
461
462 static char *driver_short_names[] __devinitdata = {
463 [AZX_DRIVER_ICH] = "HDA Intel",
464 [AZX_DRIVER_SCH] = "HDA Intel MID",
465 [AZX_DRIVER_ATI] = "HDA ATI SB",
466 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
467 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
468 [AZX_DRIVER_SIS] = "HDA SIS966",
469 [AZX_DRIVER_ULI] = "HDA ULI M5461",
470 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
471 [AZX_DRIVER_TERA] = "HDA Teradici",
472 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
473 };
474
475 /*
476 * macros for easy use
477 */
478 #define azx_writel(chip,reg,value) \
479 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
480 #define azx_readl(chip,reg) \
481 readl((chip)->remap_addr + ICH6_REG_##reg)
482 #define azx_writew(chip,reg,value) \
483 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
484 #define azx_readw(chip,reg) \
485 readw((chip)->remap_addr + ICH6_REG_##reg)
486 #define azx_writeb(chip,reg,value) \
487 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
488 #define azx_readb(chip,reg) \
489 readb((chip)->remap_addr + ICH6_REG_##reg)
490
491 #define azx_sd_writel(dev,reg,value) \
492 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
493 #define azx_sd_readl(dev,reg) \
494 readl((dev)->sd_addr + ICH6_REG_##reg)
495 #define azx_sd_writew(dev,reg,value) \
496 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
497 #define azx_sd_readw(dev,reg) \
498 readw((dev)->sd_addr + ICH6_REG_##reg)
499 #define azx_sd_writeb(dev,reg,value) \
500 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
501 #define azx_sd_readb(dev,reg) \
502 readb((dev)->sd_addr + ICH6_REG_##reg)
503
504 /* for pcm support */
505 #define get_azx_dev(substream) (substream->runtime->private_data)
506
507 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
508
509 /*
510 * Interface for HD codec
511 */
512
513 /*
514 * CORB / RIRB interface
515 */
516 static int azx_alloc_cmd_io(struct azx *chip)
517 {
518 int err;
519
520 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
521 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
522 snd_dma_pci_data(chip->pci),
523 PAGE_SIZE, &chip->rb);
524 if (err < 0) {
525 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
526 return err;
527 }
528 return 0;
529 }
530
531 static void azx_init_cmd_io(struct azx *chip)
532 {
533 spin_lock_irq(&chip->reg_lock);
534 /* CORB set up */
535 chip->corb.addr = chip->rb.addr;
536 chip->corb.buf = (u32 *)chip->rb.area;
537 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
538 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
539
540 /* set the corb size to 256 entries (ULI requires explicitly) */
541 azx_writeb(chip, CORBSIZE, 0x02);
542 /* set the corb write pointer to 0 */
543 azx_writew(chip, CORBWP, 0);
544 /* reset the corb hw read pointer */
545 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
546 /* enable corb dma */
547 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
548
549 /* RIRB set up */
550 chip->rirb.addr = chip->rb.addr + 2048;
551 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
552 chip->rirb.wp = chip->rirb.rp = 0;
553 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
554 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
555 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
556
557 /* set the rirb size to 256 entries (ULI requires explicitly) */
558 azx_writeb(chip, RIRBSIZE, 0x02);
559 /* reset the rirb hw write pointer */
560 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
561 /* set N=1, get RIRB response interrupt for new entry */
562 azx_writew(chip, RINTCNT, 1);
563 /* enable rirb dma and response irq */
564 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
565 spin_unlock_irq(&chip->reg_lock);
566 }
567
568 static void azx_free_cmd_io(struct azx *chip)
569 {
570 spin_lock_irq(&chip->reg_lock);
571 /* disable ringbuffer DMAs */
572 azx_writeb(chip, RIRBCTL, 0);
573 azx_writeb(chip, CORBCTL, 0);
574 spin_unlock_irq(&chip->reg_lock);
575 }
576
577 static unsigned int azx_command_addr(u32 cmd)
578 {
579 unsigned int addr = cmd >> 28;
580
581 if (addr >= AZX_MAX_CODECS) {
582 snd_BUG();
583 addr = 0;
584 }
585
586 return addr;
587 }
588
589 static unsigned int azx_response_addr(u32 res)
590 {
591 unsigned int addr = res & 0xf;
592
593 if (addr >= AZX_MAX_CODECS) {
594 snd_BUG();
595 addr = 0;
596 }
597
598 return addr;
599 }
600
601 /* send a command */
602 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
603 {
604 struct azx *chip = bus->private_data;
605 unsigned int addr = azx_command_addr(val);
606 unsigned int wp;
607
608 spin_lock_irq(&chip->reg_lock);
609
610 /* add command to corb */
611 wp = azx_readb(chip, CORBWP);
612 wp++;
613 wp %= ICH6_MAX_CORB_ENTRIES;
614
615 chip->rirb.cmds[addr]++;
616 chip->corb.buf[wp] = cpu_to_le32(val);
617 azx_writel(chip, CORBWP, wp);
618
619 spin_unlock_irq(&chip->reg_lock);
620
621 return 0;
622 }
623
624 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
625
626 /* retrieve RIRB entry - called from interrupt handler */
627 static void azx_update_rirb(struct azx *chip)
628 {
629 unsigned int rp, wp;
630 unsigned int addr;
631 u32 res, res_ex;
632
633 wp = azx_readb(chip, RIRBWP);
634 if (wp == chip->rirb.wp)
635 return;
636 chip->rirb.wp = wp;
637
638 while (chip->rirb.rp != wp) {
639 chip->rirb.rp++;
640 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
641
642 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
643 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
644 res = le32_to_cpu(chip->rirb.buf[rp]);
645 addr = azx_response_addr(res_ex);
646 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
647 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
648 else if (chip->rirb.cmds[addr]) {
649 chip->rirb.res[addr] = res;
650 smp_wmb();
651 chip->rirb.cmds[addr]--;
652 } else
653 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
654 "last cmd=%#08x\n",
655 res, res_ex,
656 chip->last_cmd[addr]);
657 }
658 }
659
660 /* receive a response */
661 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
662 unsigned int addr)
663 {
664 struct azx *chip = bus->private_data;
665 unsigned long timeout;
666
667 again:
668 timeout = jiffies + msecs_to_jiffies(1000);
669 for (;;) {
670 if (chip->polling_mode) {
671 spin_lock_irq(&chip->reg_lock);
672 azx_update_rirb(chip);
673 spin_unlock_irq(&chip->reg_lock);
674 }
675 if (!chip->rirb.cmds[addr]) {
676 smp_rmb();
677 bus->rirb_error = 0;
678 return chip->rirb.res[addr]; /* the last value */
679 }
680 if (time_after(jiffies, timeout))
681 break;
682 if (bus->needs_damn_long_delay)
683 msleep(2); /* temporary workaround */
684 else {
685 udelay(10);
686 cond_resched();
687 }
688 }
689
690 if (!chip->polling_mode) {
691 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
692 "switching to polling mode: last cmd=0x%08x\n",
693 chip->last_cmd[addr]);
694 chip->polling_mode = 1;
695 goto again;
696 }
697
698 if (chip->msi) {
699 snd_printk(KERN_WARNING SFX "No response from codec, "
700 "disabling MSI: last cmd=0x%08x\n",
701 chip->last_cmd[addr]);
702 free_irq(chip->irq, chip);
703 chip->irq = -1;
704 pci_disable_msi(chip->pci);
705 chip->msi = 0;
706 if (azx_acquire_irq(chip, 1) < 0) {
707 bus->rirb_error = 1;
708 return -1;
709 }
710 goto again;
711 }
712
713 if (chip->probing) {
714 /* If this critical timeout happens during the codec probing
715 * phase, this is likely an access to a non-existing codec
716 * slot. Better to return an error and reset the system.
717 */
718 return -1;
719 }
720
721 /* a fatal communication error; need either to reset or to fallback
722 * to the single_cmd mode
723 */
724 bus->rirb_error = 1;
725 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
726 bus->response_reset = 1;
727 return -1; /* give a chance to retry */
728 }
729
730 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
731 "switching to single_cmd mode: last cmd=0x%08x\n",
732 chip->last_cmd[addr]);
733 chip->single_cmd = 1;
734 bus->response_reset = 0;
735 /* release CORB/RIRB */
736 azx_free_cmd_io(chip);
737 /* disable unsolicited responses */
738 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
739 return -1;
740 }
741
742 /*
743 * Use the single immediate command instead of CORB/RIRB for simplicity
744 *
745 * Note: according to Intel, this is not preferred use. The command was
746 * intended for the BIOS only, and may get confused with unsolicited
747 * responses. So, we shouldn't use it for normal operation from the
748 * driver.
749 * I left the codes, however, for debugging/testing purposes.
750 */
751
752 /* receive a response */
753 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
754 {
755 int timeout = 50;
756
757 while (timeout--) {
758 /* check IRV busy bit */
759 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
760 /* reuse rirb.res as the response return value */
761 chip->rirb.res[addr] = azx_readl(chip, IR);
762 return 0;
763 }
764 udelay(1);
765 }
766 if (printk_ratelimit())
767 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
768 azx_readw(chip, IRS));
769 chip->rirb.res[addr] = -1;
770 return -EIO;
771 }
772
773 /* send a command */
774 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
775 {
776 struct azx *chip = bus->private_data;
777 unsigned int addr = azx_command_addr(val);
778 int timeout = 50;
779
780 bus->rirb_error = 0;
781 while (timeout--) {
782 /* check ICB busy bit */
783 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
784 /* Clear IRV valid bit */
785 azx_writew(chip, IRS, azx_readw(chip, IRS) |
786 ICH6_IRS_VALID);
787 azx_writel(chip, IC, val);
788 azx_writew(chip, IRS, azx_readw(chip, IRS) |
789 ICH6_IRS_BUSY);
790 return azx_single_wait_for_response(chip, addr);
791 }
792 udelay(1);
793 }
794 if (printk_ratelimit())
795 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
796 azx_readw(chip, IRS), val);
797 return -EIO;
798 }
799
800 /* receive a response */
801 static unsigned int azx_single_get_response(struct hda_bus *bus,
802 unsigned int addr)
803 {
804 struct azx *chip = bus->private_data;
805 return chip->rirb.res[addr];
806 }
807
808 /*
809 * The below are the main callbacks from hda_codec.
810 *
811 * They are just the skeleton to call sub-callbacks according to the
812 * current setting of chip->single_cmd.
813 */
814
815 /* send a command */
816 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
817 {
818 struct azx *chip = bus->private_data;
819
820 chip->last_cmd[azx_command_addr(val)] = val;
821 if (chip->single_cmd)
822 return azx_single_send_cmd(bus, val);
823 else
824 return azx_corb_send_cmd(bus, val);
825 }
826
827 /* get a response */
828 static unsigned int azx_get_response(struct hda_bus *bus,
829 unsigned int addr)
830 {
831 struct azx *chip = bus->private_data;
832 if (chip->single_cmd)
833 return azx_single_get_response(bus, addr);
834 else
835 return azx_rirb_get_response(bus, addr);
836 }
837
838 #ifdef CONFIG_SND_HDA_POWER_SAVE
839 static void azx_power_notify(struct hda_bus *bus);
840 #endif
841
842 /* reset codec link */
843 static int azx_reset(struct azx *chip)
844 {
845 int count;
846
847 /* clear STATESTS */
848 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
849
850 /* reset controller */
851 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
852
853 count = 50;
854 while (azx_readb(chip, GCTL) && --count)
855 msleep(1);
856
857 /* delay for >= 100us for codec PLL to settle per spec
858 * Rev 0.9 section 5.5.1
859 */
860 msleep(1);
861
862 /* Bring controller out of reset */
863 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
864
865 count = 50;
866 while (!azx_readb(chip, GCTL) && --count)
867 msleep(1);
868
869 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
870 msleep(1);
871
872 /* check to see if controller is ready */
873 if (!azx_readb(chip, GCTL)) {
874 snd_printd(SFX "azx_reset: controller not ready!\n");
875 return -EBUSY;
876 }
877
878 /* Accept unsolicited responses */
879 if (!chip->single_cmd)
880 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
881 ICH6_GCTL_UNSOL);
882
883 /* detect codecs */
884 if (!chip->codec_mask) {
885 chip->codec_mask = azx_readw(chip, STATESTS);
886 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
887 }
888
889 return 0;
890 }
891
892
893 /*
894 * Lowlevel interface
895 */
896
897 /* enable interrupts */
898 static void azx_int_enable(struct azx *chip)
899 {
900 /* enable controller CIE and GIE */
901 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
902 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
903 }
904
905 /* disable interrupts */
906 static void azx_int_disable(struct azx *chip)
907 {
908 int i;
909
910 /* disable interrupts in stream descriptor */
911 for (i = 0; i < chip->num_streams; i++) {
912 struct azx_dev *azx_dev = &chip->azx_dev[i];
913 azx_sd_writeb(azx_dev, SD_CTL,
914 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
915 }
916
917 /* disable SIE for all streams */
918 azx_writeb(chip, INTCTL, 0);
919
920 /* disable controller CIE and GIE */
921 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
922 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
923 }
924
925 /* clear interrupts */
926 static void azx_int_clear(struct azx *chip)
927 {
928 int i;
929
930 /* clear stream status */
931 for (i = 0; i < chip->num_streams; i++) {
932 struct azx_dev *azx_dev = &chip->azx_dev[i];
933 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
934 }
935
936 /* clear STATESTS */
937 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
938
939 /* clear rirb status */
940 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
941
942 /* clear int status */
943 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
944 }
945
946 /* start a stream */
947 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
948 {
949 /*
950 * Before stream start, initialize parameter
951 */
952 azx_dev->insufficient = 1;
953
954 /* enable SIE */
955 azx_writeb(chip, INTCTL,
956 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
957 /* set DMA start and interrupt mask */
958 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
959 SD_CTL_DMA_START | SD_INT_MASK);
960 }
961
962 /* stop DMA */
963 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
964 {
965 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
966 ~(SD_CTL_DMA_START | SD_INT_MASK));
967 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
968 }
969
970 /* stop a stream */
971 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
972 {
973 azx_stream_clear(chip, azx_dev);
974 /* disable SIE */
975 azx_writeb(chip, INTCTL,
976 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
977 }
978
979
980 /*
981 * reset and start the controller registers
982 */
983 static void azx_init_chip(struct azx *chip)
984 {
985 if (chip->initialized)
986 return;
987
988 /* reset controller */
989 azx_reset(chip);
990
991 /* initialize interrupts */
992 azx_int_clear(chip);
993 azx_int_enable(chip);
994
995 /* initialize the codec command I/O */
996 if (!chip->single_cmd)
997 azx_init_cmd_io(chip);
998
999 /* program the position buffer */
1000 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1001 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1002
1003 chip->initialized = 1;
1004 }
1005
1006 /*
1007 * initialize the PCI registers
1008 */
1009 /* update bits in a PCI register byte */
1010 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1011 unsigned char mask, unsigned char val)
1012 {
1013 unsigned char data;
1014
1015 pci_read_config_byte(pci, reg, &data);
1016 data &= ~mask;
1017 data |= (val & mask);
1018 pci_write_config_byte(pci, reg, data);
1019 }
1020
1021 static void azx_init_pci(struct azx *chip)
1022 {
1023 unsigned short snoop;
1024
1025 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1026 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1027 * Ensuring these bits are 0 clears playback static on some HD Audio
1028 * codecs
1029 */
1030 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1031
1032 switch (chip->driver_type) {
1033 case AZX_DRIVER_ATI:
1034 /* For ATI SB450 azalia HD audio, we need to enable snoop */
1035 update_pci_byte(chip->pci,
1036 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
1037 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
1038 break;
1039 case AZX_DRIVER_NVIDIA:
1040 /* For NVIDIA HDA, enable snoop */
1041 update_pci_byte(chip->pci,
1042 NVIDIA_HDA_TRANSREG_ADDR,
1043 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1044 update_pci_byte(chip->pci,
1045 NVIDIA_HDA_ISTRM_COH,
1046 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1047 update_pci_byte(chip->pci,
1048 NVIDIA_HDA_OSTRM_COH,
1049 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1050 break;
1051 case AZX_DRIVER_SCH:
1052 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1053 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
1054 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
1055 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1056 pci_read_config_word(chip->pci,
1057 INTEL_SCH_HDA_DEVC, &snoop);
1058 snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1059 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1060 ? "Failed" : "OK");
1061 }
1062 break;
1063
1064 }
1065 }
1066
1067
1068 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1069
1070 /*
1071 * interrupt handler
1072 */
1073 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1074 {
1075 struct azx *chip = dev_id;
1076 struct azx_dev *azx_dev;
1077 u32 status;
1078 int i, ok;
1079
1080 spin_lock(&chip->reg_lock);
1081
1082 status = azx_readl(chip, INTSTS);
1083 if (status == 0) {
1084 spin_unlock(&chip->reg_lock);
1085 return IRQ_NONE;
1086 }
1087
1088 for (i = 0; i < chip->num_streams; i++) {
1089 azx_dev = &chip->azx_dev[i];
1090 if (status & azx_dev->sd_int_sta_mask) {
1091 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1092 if (!azx_dev->substream || !azx_dev->running)
1093 continue;
1094 /* check whether this IRQ is really acceptable */
1095 ok = azx_position_ok(chip, azx_dev);
1096 if (ok == 1) {
1097 azx_dev->irq_pending = 0;
1098 spin_unlock(&chip->reg_lock);
1099 snd_pcm_period_elapsed(azx_dev->substream);
1100 spin_lock(&chip->reg_lock);
1101 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1102 /* bogus IRQ, process it later */
1103 azx_dev->irq_pending = 1;
1104 queue_work(chip->bus->workq,
1105 &chip->irq_pending_work);
1106 }
1107 }
1108 }
1109
1110 /* clear rirb int */
1111 status = azx_readb(chip, RIRBSTS);
1112 if (status & RIRB_INT_MASK) {
1113 if (status & RIRB_INT_RESPONSE)
1114 azx_update_rirb(chip);
1115 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1116 }
1117
1118 #if 0
1119 /* clear state status int */
1120 if (azx_readb(chip, STATESTS) & 0x04)
1121 azx_writeb(chip, STATESTS, 0x04);
1122 #endif
1123 spin_unlock(&chip->reg_lock);
1124
1125 return IRQ_HANDLED;
1126 }
1127
1128
1129 /*
1130 * set up a BDL entry
1131 */
1132 static int setup_bdle(struct snd_pcm_substream *substream,
1133 struct azx_dev *azx_dev, u32 **bdlp,
1134 int ofs, int size, int with_ioc)
1135 {
1136 u32 *bdl = *bdlp;
1137
1138 while (size > 0) {
1139 dma_addr_t addr;
1140 int chunk;
1141
1142 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1143 return -EINVAL;
1144
1145 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1146 /* program the address field of the BDL entry */
1147 bdl[0] = cpu_to_le32((u32)addr);
1148 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1149 /* program the size field of the BDL entry */
1150 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1151 bdl[2] = cpu_to_le32(chunk);
1152 /* program the IOC to enable interrupt
1153 * only when the whole fragment is processed
1154 */
1155 size -= chunk;
1156 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1157 bdl += 4;
1158 azx_dev->frags++;
1159 ofs += chunk;
1160 }
1161 *bdlp = bdl;
1162 return ofs;
1163 }
1164
1165 /*
1166 * set up BDL entries
1167 */
1168 static int azx_setup_periods(struct azx *chip,
1169 struct snd_pcm_substream *substream,
1170 struct azx_dev *azx_dev)
1171 {
1172 u32 *bdl;
1173 int i, ofs, periods, period_bytes;
1174 int pos_adj;
1175
1176 /* reset BDL address */
1177 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1178 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1179
1180 period_bytes = azx_dev->period_bytes;
1181 periods = azx_dev->bufsize / period_bytes;
1182
1183 /* program the initial BDL entries */
1184 bdl = (u32 *)azx_dev->bdl.area;
1185 ofs = 0;
1186 azx_dev->frags = 0;
1187 pos_adj = bdl_pos_adj[chip->dev_index];
1188 if (pos_adj > 0) {
1189 struct snd_pcm_runtime *runtime = substream->runtime;
1190 int pos_align = pos_adj;
1191 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1192 if (!pos_adj)
1193 pos_adj = pos_align;
1194 else
1195 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1196 pos_align;
1197 pos_adj = frames_to_bytes(runtime, pos_adj);
1198 if (pos_adj >= period_bytes) {
1199 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1200 bdl_pos_adj[chip->dev_index]);
1201 pos_adj = 0;
1202 } else {
1203 ofs = setup_bdle(substream, azx_dev,
1204 &bdl, ofs, pos_adj, 1);
1205 if (ofs < 0)
1206 goto error;
1207 }
1208 } else
1209 pos_adj = 0;
1210 for (i = 0; i < periods; i++) {
1211 if (i == periods - 1 && pos_adj)
1212 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1213 period_bytes - pos_adj, 0);
1214 else
1215 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1216 period_bytes, 1);
1217 if (ofs < 0)
1218 goto error;
1219 }
1220 return 0;
1221
1222 error:
1223 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1224 azx_dev->bufsize, period_bytes);
1225 return -EINVAL;
1226 }
1227
1228 /* reset stream */
1229 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1230 {
1231 unsigned char val;
1232 int timeout;
1233
1234 azx_stream_clear(chip, azx_dev);
1235
1236 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1237 SD_CTL_STREAM_RESET);
1238 udelay(3);
1239 timeout = 300;
1240 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1241 --timeout)
1242 ;
1243 val &= ~SD_CTL_STREAM_RESET;
1244 azx_sd_writeb(azx_dev, SD_CTL, val);
1245 udelay(3);
1246
1247 timeout = 300;
1248 /* waiting for hardware to report that the stream is out of reset */
1249 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1250 --timeout)
1251 ;
1252
1253 /* reset first position - may not be synced with hw at this time */
1254 *azx_dev->posbuf = 0;
1255 }
1256
1257 /*
1258 * set up the SD for streaming
1259 */
1260 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1261 {
1262 /* make sure the run bit is zero for SD */
1263 azx_stream_clear(chip, azx_dev);
1264 /* program the stream_tag */
1265 azx_sd_writel(azx_dev, SD_CTL,
1266 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1267 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1268
1269 /* program the length of samples in cyclic buffer */
1270 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1271
1272 /* program the stream format */
1273 /* this value needs to be the same as the one programmed */
1274 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1275
1276 /* program the stream LVI (last valid index) of the BDL */
1277 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1278
1279 /* program the BDL address */
1280 /* lower BDL address */
1281 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1282 /* upper BDL address */
1283 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1284
1285 /* enable the position buffer */
1286 if (chip->position_fix == POS_FIX_POSBUF ||
1287 chip->position_fix == POS_FIX_AUTO ||
1288 chip->via_dmapos_patch) {
1289 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1290 azx_writel(chip, DPLBASE,
1291 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1292 }
1293
1294 /* set the interrupt enable bits in the descriptor control register */
1295 azx_sd_writel(azx_dev, SD_CTL,
1296 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1297
1298 return 0;
1299 }
1300
1301 /*
1302 * Probe the given codec address
1303 */
1304 static int probe_codec(struct azx *chip, int addr)
1305 {
1306 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1307 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1308 unsigned int res;
1309
1310 mutex_lock(&chip->bus->cmd_mutex);
1311 chip->probing = 1;
1312 azx_send_cmd(chip->bus, cmd);
1313 res = azx_get_response(chip->bus, addr);
1314 chip->probing = 0;
1315 mutex_unlock(&chip->bus->cmd_mutex);
1316 if (res == -1)
1317 return -EIO;
1318 snd_printdd(SFX "codec #%d probed OK\n", addr);
1319 return 0;
1320 }
1321
1322 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1323 struct hda_pcm *cpcm);
1324 static void azx_stop_chip(struct azx *chip);
1325
1326 static void azx_bus_reset(struct hda_bus *bus)
1327 {
1328 struct azx *chip = bus->private_data;
1329
1330 bus->in_reset = 1;
1331 azx_stop_chip(chip);
1332 azx_init_chip(chip);
1333 #ifdef CONFIG_PM
1334 if (chip->initialized) {
1335 int i;
1336
1337 for (i = 0; i < AZX_MAX_PCMS; i++)
1338 snd_pcm_suspend_all(chip->pcm[i]);
1339 snd_hda_suspend(chip->bus);
1340 snd_hda_resume(chip->bus);
1341 }
1342 #endif
1343 bus->in_reset = 0;
1344 }
1345
1346 /*
1347 * Codec initialization
1348 */
1349
1350 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1351 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1352 [AZX_DRIVER_TERA] = 1,
1353 };
1354
1355 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1356 {
1357 struct hda_bus_template bus_temp;
1358 int c, codecs, err;
1359 int max_slots;
1360
1361 memset(&bus_temp, 0, sizeof(bus_temp));
1362 bus_temp.private_data = chip;
1363 bus_temp.modelname = model;
1364 bus_temp.pci = chip->pci;
1365 bus_temp.ops.command = azx_send_cmd;
1366 bus_temp.ops.get_response = azx_get_response;
1367 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1368 bus_temp.ops.bus_reset = azx_bus_reset;
1369 #ifdef CONFIG_SND_HDA_POWER_SAVE
1370 bus_temp.power_save = &power_save;
1371 bus_temp.ops.pm_notify = azx_power_notify;
1372 #endif
1373
1374 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1375 if (err < 0)
1376 return err;
1377
1378 if (chip->driver_type == AZX_DRIVER_NVIDIA)
1379 chip->bus->needs_damn_long_delay = 1;
1380
1381 codecs = 0;
1382 max_slots = azx_max_codecs[chip->driver_type];
1383 if (!max_slots)
1384 max_slots = AZX_MAX_CODECS;
1385
1386 /* First try to probe all given codec slots */
1387 for (c = 0; c < max_slots; c++) {
1388 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1389 if (probe_codec(chip, c) < 0) {
1390 /* Some BIOSen give you wrong codec addresses
1391 * that don't exist
1392 */
1393 snd_printk(KERN_WARNING SFX
1394 "Codec #%d probe error; "
1395 "disabling it...\n", c);
1396 chip->codec_mask &= ~(1 << c);
1397 /* More badly, accessing to a non-existing
1398 * codec often screws up the controller chip,
1399 * and distrubs the further communications.
1400 * Thus if an error occurs during probing,
1401 * better to reset the controller chip to
1402 * get back to the sanity state.
1403 */
1404 azx_stop_chip(chip);
1405 azx_init_chip(chip);
1406 }
1407 }
1408 }
1409
1410 /* Then create codec instances */
1411 for (c = 0; c < max_slots; c++) {
1412 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1413 struct hda_codec *codec;
1414 err = snd_hda_codec_new(chip->bus, c, &codec);
1415 if (err < 0)
1416 continue;
1417 codec->beep_mode = chip->beep_mode;
1418 codecs++;
1419 }
1420 }
1421 if (!codecs) {
1422 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1423 return -ENXIO;
1424 }
1425 return 0;
1426 }
1427
1428 /* configure each codec instance */
1429 static int __devinit azx_codec_configure(struct azx *chip)
1430 {
1431 struct hda_codec *codec;
1432 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1433 snd_hda_codec_configure(codec);
1434 }
1435 return 0;
1436 }
1437
1438
1439 /*
1440 * PCM support
1441 */
1442
1443 /* assign a stream for the PCM */
1444 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1445 {
1446 int dev, i, nums;
1447 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1448 dev = chip->playback_index_offset;
1449 nums = chip->playback_streams;
1450 } else {
1451 dev = chip->capture_index_offset;
1452 nums = chip->capture_streams;
1453 }
1454 for (i = 0; i < nums; i++, dev++)
1455 if (!chip->azx_dev[dev].opened) {
1456 chip->azx_dev[dev].opened = 1;
1457 return &chip->azx_dev[dev];
1458 }
1459 return NULL;
1460 }
1461
1462 /* release the assigned stream */
1463 static inline void azx_release_device(struct azx_dev *azx_dev)
1464 {
1465 azx_dev->opened = 0;
1466 }
1467
1468 static struct snd_pcm_hardware azx_pcm_hw = {
1469 .info = (SNDRV_PCM_INFO_MMAP |
1470 SNDRV_PCM_INFO_INTERLEAVED |
1471 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1472 SNDRV_PCM_INFO_MMAP_VALID |
1473 /* No full-resume yet implemented */
1474 /* SNDRV_PCM_INFO_RESUME |*/
1475 SNDRV_PCM_INFO_PAUSE |
1476 SNDRV_PCM_INFO_SYNC_START),
1477 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1478 .rates = SNDRV_PCM_RATE_48000,
1479 .rate_min = 48000,
1480 .rate_max = 48000,
1481 .channels_min = 2,
1482 .channels_max = 2,
1483 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1484 .period_bytes_min = 128,
1485 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1486 .periods_min = 2,
1487 .periods_max = AZX_MAX_FRAG,
1488 .fifo_size = 0,
1489 };
1490
1491 struct azx_pcm {
1492 struct azx *chip;
1493 struct hda_codec *codec;
1494 struct hda_pcm_stream *hinfo[2];
1495 };
1496
1497 static int azx_pcm_open(struct snd_pcm_substream *substream)
1498 {
1499 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1500 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1501 struct azx *chip = apcm->chip;
1502 struct azx_dev *azx_dev;
1503 struct snd_pcm_runtime *runtime = substream->runtime;
1504 unsigned long flags;
1505 int err;
1506
1507 mutex_lock(&chip->open_mutex);
1508 azx_dev = azx_assign_device(chip, substream->stream);
1509 if (azx_dev == NULL) {
1510 mutex_unlock(&chip->open_mutex);
1511 return -EBUSY;
1512 }
1513 runtime->hw = azx_pcm_hw;
1514 runtime->hw.channels_min = hinfo->channels_min;
1515 runtime->hw.channels_max = hinfo->channels_max;
1516 runtime->hw.formats = hinfo->formats;
1517 runtime->hw.rates = hinfo->rates;
1518 snd_pcm_limit_hw_rates(runtime);
1519 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1520 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1521 128);
1522 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1523 128);
1524 snd_hda_power_up(apcm->codec);
1525 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1526 if (err < 0) {
1527 azx_release_device(azx_dev);
1528 snd_hda_power_down(apcm->codec);
1529 mutex_unlock(&chip->open_mutex);
1530 return err;
1531 }
1532 snd_pcm_limit_hw_rates(runtime);
1533 /* sanity check */
1534 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1535 snd_BUG_ON(!runtime->hw.channels_max) ||
1536 snd_BUG_ON(!runtime->hw.formats) ||
1537 snd_BUG_ON(!runtime->hw.rates)) {
1538 azx_release_device(azx_dev);
1539 hinfo->ops.close(hinfo, apcm->codec, substream);
1540 snd_hda_power_down(apcm->codec);
1541 mutex_unlock(&chip->open_mutex);
1542 return -EINVAL;
1543 }
1544 spin_lock_irqsave(&chip->reg_lock, flags);
1545 azx_dev->substream = substream;
1546 azx_dev->running = 0;
1547 spin_unlock_irqrestore(&chip->reg_lock, flags);
1548
1549 runtime->private_data = azx_dev;
1550 snd_pcm_set_sync(substream);
1551 mutex_unlock(&chip->open_mutex);
1552 return 0;
1553 }
1554
1555 static int azx_pcm_close(struct snd_pcm_substream *substream)
1556 {
1557 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1558 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1559 struct azx *chip = apcm->chip;
1560 struct azx_dev *azx_dev = get_azx_dev(substream);
1561 unsigned long flags;
1562
1563 mutex_lock(&chip->open_mutex);
1564 spin_lock_irqsave(&chip->reg_lock, flags);
1565 azx_dev->substream = NULL;
1566 azx_dev->running = 0;
1567 spin_unlock_irqrestore(&chip->reg_lock, flags);
1568 azx_release_device(azx_dev);
1569 hinfo->ops.close(hinfo, apcm->codec, substream);
1570 snd_hda_power_down(apcm->codec);
1571 mutex_unlock(&chip->open_mutex);
1572 return 0;
1573 }
1574
1575 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1576 struct snd_pcm_hw_params *hw_params)
1577 {
1578 struct azx_dev *azx_dev = get_azx_dev(substream);
1579
1580 azx_dev->bufsize = 0;
1581 azx_dev->period_bytes = 0;
1582 azx_dev->format_val = 0;
1583 return snd_pcm_lib_malloc_pages(substream,
1584 params_buffer_bytes(hw_params));
1585 }
1586
1587 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1588 {
1589 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1590 struct azx_dev *azx_dev = get_azx_dev(substream);
1591 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1592
1593 /* reset BDL address */
1594 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1595 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1596 azx_sd_writel(azx_dev, SD_CTL, 0);
1597 azx_dev->bufsize = 0;
1598 azx_dev->period_bytes = 0;
1599 azx_dev->format_val = 0;
1600
1601 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1602
1603 return snd_pcm_lib_free_pages(substream);
1604 }
1605
1606 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1607 {
1608 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1609 struct azx *chip = apcm->chip;
1610 struct azx_dev *azx_dev = get_azx_dev(substream);
1611 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1612 struct snd_pcm_runtime *runtime = substream->runtime;
1613 unsigned int bufsize, period_bytes, format_val;
1614 int err;
1615
1616 azx_stream_reset(chip, azx_dev);
1617 format_val = snd_hda_calc_stream_format(runtime->rate,
1618 runtime->channels,
1619 runtime->format,
1620 hinfo->maxbps);
1621 if (!format_val) {
1622 snd_printk(KERN_ERR SFX
1623 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1624 runtime->rate, runtime->channels, runtime->format);
1625 return -EINVAL;
1626 }
1627
1628 bufsize = snd_pcm_lib_buffer_bytes(substream);
1629 period_bytes = snd_pcm_lib_period_bytes(substream);
1630
1631 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1632 bufsize, format_val);
1633
1634 if (bufsize != azx_dev->bufsize ||
1635 period_bytes != azx_dev->period_bytes ||
1636 format_val != azx_dev->format_val) {
1637 azx_dev->bufsize = bufsize;
1638 azx_dev->period_bytes = period_bytes;
1639 azx_dev->format_val = format_val;
1640 err = azx_setup_periods(chip, substream, azx_dev);
1641 if (err < 0)
1642 return err;
1643 }
1644
1645 azx_dev->min_jiffies = (runtime->period_size * HZ) /
1646 (runtime->rate * 2);
1647 azx_setup_controller(chip, azx_dev);
1648 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1649 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1650 else
1651 azx_dev->fifo_size = 0;
1652
1653 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1654 azx_dev->format_val, substream);
1655 }
1656
1657 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1658 {
1659 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1660 struct azx *chip = apcm->chip;
1661 struct azx_dev *azx_dev;
1662 struct snd_pcm_substream *s;
1663 int rstart = 0, start, nsync = 0, sbits = 0;
1664 int nwait, timeout;
1665
1666 switch (cmd) {
1667 case SNDRV_PCM_TRIGGER_START:
1668 rstart = 1;
1669 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1670 case SNDRV_PCM_TRIGGER_RESUME:
1671 start = 1;
1672 break;
1673 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1674 case SNDRV_PCM_TRIGGER_SUSPEND:
1675 case SNDRV_PCM_TRIGGER_STOP:
1676 start = 0;
1677 break;
1678 default:
1679 return -EINVAL;
1680 }
1681
1682 snd_pcm_group_for_each_entry(s, substream) {
1683 if (s->pcm->card != substream->pcm->card)
1684 continue;
1685 azx_dev = get_azx_dev(s);
1686 sbits |= 1 << azx_dev->index;
1687 nsync++;
1688 snd_pcm_trigger_done(s, substream);
1689 }
1690
1691 spin_lock(&chip->reg_lock);
1692 if (nsync > 1) {
1693 /* first, set SYNC bits of corresponding streams */
1694 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1695 }
1696 snd_pcm_group_for_each_entry(s, substream) {
1697 if (s->pcm->card != substream->pcm->card)
1698 continue;
1699 azx_dev = get_azx_dev(s);
1700 if (rstart) {
1701 azx_dev->start_flag = 1;
1702 azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1703 }
1704 if (start)
1705 azx_stream_start(chip, azx_dev);
1706 else
1707 azx_stream_stop(chip, azx_dev);
1708 azx_dev->running = start;
1709 }
1710 spin_unlock(&chip->reg_lock);
1711 if (start) {
1712 if (nsync == 1)
1713 return 0;
1714 /* wait until all FIFOs get ready */
1715 for (timeout = 5000; timeout; timeout--) {
1716 nwait = 0;
1717 snd_pcm_group_for_each_entry(s, substream) {
1718 if (s->pcm->card != substream->pcm->card)
1719 continue;
1720 azx_dev = get_azx_dev(s);
1721 if (!(azx_sd_readb(azx_dev, SD_STS) &
1722 SD_STS_FIFO_READY))
1723 nwait++;
1724 }
1725 if (!nwait)
1726 break;
1727 cpu_relax();
1728 }
1729 } else {
1730 /* wait until all RUN bits are cleared */
1731 for (timeout = 5000; timeout; timeout--) {
1732 nwait = 0;
1733 snd_pcm_group_for_each_entry(s, substream) {
1734 if (s->pcm->card != substream->pcm->card)
1735 continue;
1736 azx_dev = get_azx_dev(s);
1737 if (azx_sd_readb(azx_dev, SD_CTL) &
1738 SD_CTL_DMA_START)
1739 nwait++;
1740 }
1741 if (!nwait)
1742 break;
1743 cpu_relax();
1744 }
1745 }
1746 if (nsync > 1) {
1747 spin_lock(&chip->reg_lock);
1748 /* reset SYNC bits */
1749 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1750 spin_unlock(&chip->reg_lock);
1751 }
1752 return 0;
1753 }
1754
1755 /* get the current DMA position with correction on VIA chips */
1756 static unsigned int azx_via_get_position(struct azx *chip,
1757 struct azx_dev *azx_dev)
1758 {
1759 unsigned int link_pos, mini_pos, bound_pos;
1760 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1761 unsigned int fifo_size;
1762
1763 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1764 if (azx_dev->index >= 4) {
1765 /* Playback, no problem using link position */
1766 return link_pos;
1767 }
1768
1769 /* Capture */
1770 /* For new chipset,
1771 * use mod to get the DMA position just like old chipset
1772 */
1773 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1774 mod_dma_pos %= azx_dev->period_bytes;
1775
1776 /* azx_dev->fifo_size can't get FIFO size of in stream.
1777 * Get from base address + offset.
1778 */
1779 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1780
1781 if (azx_dev->insufficient) {
1782 /* Link position never gather than FIFO size */
1783 if (link_pos <= fifo_size)
1784 return 0;
1785
1786 azx_dev->insufficient = 0;
1787 }
1788
1789 if (link_pos <= fifo_size)
1790 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1791 else
1792 mini_pos = link_pos - fifo_size;
1793
1794 /* Find nearest previous boudary */
1795 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1796 mod_link_pos = link_pos % azx_dev->period_bytes;
1797 if (mod_link_pos >= fifo_size)
1798 bound_pos = link_pos - mod_link_pos;
1799 else if (mod_dma_pos >= mod_mini_pos)
1800 bound_pos = mini_pos - mod_mini_pos;
1801 else {
1802 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1803 if (bound_pos >= azx_dev->bufsize)
1804 bound_pos = 0;
1805 }
1806
1807 /* Calculate real DMA position we want */
1808 return bound_pos + mod_dma_pos;
1809 }
1810
1811 static unsigned int azx_get_position(struct azx *chip,
1812 struct azx_dev *azx_dev)
1813 {
1814 unsigned int pos;
1815
1816 if (chip->via_dmapos_patch)
1817 pos = azx_via_get_position(chip, azx_dev);
1818 else if (chip->position_fix == POS_FIX_POSBUF ||
1819 chip->position_fix == POS_FIX_AUTO) {
1820 /* use the position buffer */
1821 pos = le32_to_cpu(*azx_dev->posbuf);
1822 } else {
1823 /* read LPIB */
1824 pos = azx_sd_readl(azx_dev, SD_LPIB);
1825 }
1826 if (pos >= azx_dev->bufsize)
1827 pos = 0;
1828 return pos;
1829 }
1830
1831 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1832 {
1833 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1834 struct azx *chip = apcm->chip;
1835 struct azx_dev *azx_dev = get_azx_dev(substream);
1836 return bytes_to_frames(substream->runtime,
1837 azx_get_position(chip, azx_dev));
1838 }
1839
1840 /*
1841 * Check whether the current DMA position is acceptable for updating
1842 * periods. Returns non-zero if it's OK.
1843 *
1844 * Many HD-audio controllers appear pretty inaccurate about
1845 * the update-IRQ timing. The IRQ is issued before actually the
1846 * data is processed. So, we need to process it afterwords in a
1847 * workqueue.
1848 */
1849 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1850 {
1851 unsigned int pos;
1852
1853 if (azx_dev->start_flag &&
1854 time_before_eq(jiffies, azx_dev->start_jiffies))
1855 return -1; /* bogus (too early) interrupt */
1856 azx_dev->start_flag = 0;
1857
1858 pos = azx_get_position(chip, azx_dev);
1859 if (chip->position_fix == POS_FIX_AUTO) {
1860 if (!pos) {
1861 printk(KERN_WARNING
1862 "hda-intel: Invalid position buffer, "
1863 "using LPIB read method instead.\n");
1864 chip->position_fix = POS_FIX_LPIB;
1865 pos = azx_get_position(chip, azx_dev);
1866 } else
1867 chip->position_fix = POS_FIX_POSBUF;
1868 }
1869
1870 if (!bdl_pos_adj[chip->dev_index])
1871 return 1; /* no delayed ack */
1872 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1873 return 0; /* NG - it's below the period boundary */
1874 return 1; /* OK, it's fine */
1875 }
1876
1877 /*
1878 * The work for pending PCM period updates.
1879 */
1880 static void azx_irq_pending_work(struct work_struct *work)
1881 {
1882 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1883 int i, pending;
1884
1885 if (!chip->irq_pending_warned) {
1886 printk(KERN_WARNING
1887 "hda-intel: IRQ timing workaround is activated "
1888 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1889 chip->card->number);
1890 chip->irq_pending_warned = 1;
1891 }
1892
1893 for (;;) {
1894 pending = 0;
1895 spin_lock_irq(&chip->reg_lock);
1896 for (i = 0; i < chip->num_streams; i++) {
1897 struct azx_dev *azx_dev = &chip->azx_dev[i];
1898 if (!azx_dev->irq_pending ||
1899 !azx_dev->substream ||
1900 !azx_dev->running)
1901 continue;
1902 if (azx_position_ok(chip, azx_dev)) {
1903 azx_dev->irq_pending = 0;
1904 spin_unlock(&chip->reg_lock);
1905 snd_pcm_period_elapsed(azx_dev->substream);
1906 spin_lock(&chip->reg_lock);
1907 } else
1908 pending++;
1909 }
1910 spin_unlock_irq(&chip->reg_lock);
1911 if (!pending)
1912 return;
1913 cond_resched();
1914 }
1915 }
1916
1917 /* clear irq_pending flags and assure no on-going workq */
1918 static void azx_clear_irq_pending(struct azx *chip)
1919 {
1920 int i;
1921
1922 spin_lock_irq(&chip->reg_lock);
1923 for (i = 0; i < chip->num_streams; i++)
1924 chip->azx_dev[i].irq_pending = 0;
1925 spin_unlock_irq(&chip->reg_lock);
1926 }
1927
1928 static struct snd_pcm_ops azx_pcm_ops = {
1929 .open = azx_pcm_open,
1930 .close = azx_pcm_close,
1931 .ioctl = snd_pcm_lib_ioctl,
1932 .hw_params = azx_pcm_hw_params,
1933 .hw_free = azx_pcm_hw_free,
1934 .prepare = azx_pcm_prepare,
1935 .trigger = azx_pcm_trigger,
1936 .pointer = azx_pcm_pointer,
1937 .page = snd_pcm_sgbuf_ops_page,
1938 };
1939
1940 static void azx_pcm_free(struct snd_pcm *pcm)
1941 {
1942 struct azx_pcm *apcm = pcm->private_data;
1943 if (apcm) {
1944 apcm->chip->pcm[pcm->device] = NULL;
1945 kfree(apcm);
1946 }
1947 }
1948
1949 static int
1950 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1951 struct hda_pcm *cpcm)
1952 {
1953 struct azx *chip = bus->private_data;
1954 struct snd_pcm *pcm;
1955 struct azx_pcm *apcm;
1956 int pcm_dev = cpcm->device;
1957 int s, err;
1958
1959 if (pcm_dev >= AZX_MAX_PCMS) {
1960 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1961 pcm_dev);
1962 return -EINVAL;
1963 }
1964 if (chip->pcm[pcm_dev]) {
1965 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1966 return -EBUSY;
1967 }
1968 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1969 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1970 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1971 &pcm);
1972 if (err < 0)
1973 return err;
1974 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
1975 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1976 if (apcm == NULL)
1977 return -ENOMEM;
1978 apcm->chip = chip;
1979 apcm->codec = codec;
1980 pcm->private_data = apcm;
1981 pcm->private_free = azx_pcm_free;
1982 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1983 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1984 chip->pcm[pcm_dev] = pcm;
1985 cpcm->pcm = pcm;
1986 for (s = 0; s < 2; s++) {
1987 apcm->hinfo[s] = &cpcm->stream[s];
1988 if (cpcm->stream[s].substreams)
1989 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1990 }
1991 /* buffer pre-allocation */
1992 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1993 snd_dma_pci_data(chip->pci),
1994 1024 * 64, 32 * 1024 * 1024);
1995 return 0;
1996 }
1997
1998 /*
1999 * mixer creation - all stuff is implemented in hda module
2000 */
2001 static int __devinit azx_mixer_create(struct azx *chip)
2002 {
2003 return snd_hda_build_controls(chip->bus);
2004 }
2005
2006
2007 /*
2008 * initialize SD streams
2009 */
2010 static int __devinit azx_init_stream(struct azx *chip)
2011 {
2012 int i;
2013
2014 /* initialize each stream (aka device)
2015 * assign the starting bdl address to each stream (device)
2016 * and initialize
2017 */
2018 for (i = 0; i < chip->num_streams; i++) {
2019 struct azx_dev *azx_dev = &chip->azx_dev[i];
2020 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2021 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2022 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2023 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2024 azx_dev->sd_int_sta_mask = 1 << i;
2025 /* stream tag: must be non-zero and unique */
2026 azx_dev->index = i;
2027 azx_dev->stream_tag = i + 1;
2028 }
2029
2030 return 0;
2031 }
2032
2033 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2034 {
2035 if (request_irq(chip->pci->irq, azx_interrupt,
2036 chip->msi ? 0 : IRQF_SHARED,
2037 "HDA Intel", chip)) {
2038 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2039 "disabling device\n", chip->pci->irq);
2040 if (do_disconnect)
2041 snd_card_disconnect(chip->card);
2042 return -1;
2043 }
2044 chip->irq = chip->pci->irq;
2045 pci_intx(chip->pci, !chip->msi);
2046 return 0;
2047 }
2048
2049
2050 static void azx_stop_chip(struct azx *chip)
2051 {
2052 if (!chip->initialized)
2053 return;
2054
2055 /* disable interrupts */
2056 azx_int_disable(chip);
2057 azx_int_clear(chip);
2058
2059 /* disable CORB/RIRB */
2060 azx_free_cmd_io(chip);
2061
2062 /* disable position buffer */
2063 azx_writel(chip, DPLBASE, 0);
2064 azx_writel(chip, DPUBASE, 0);
2065
2066 chip->initialized = 0;
2067 }
2068
2069 #ifdef CONFIG_SND_HDA_POWER_SAVE
2070 /* power-up/down the controller */
2071 static void azx_power_notify(struct hda_bus *bus)
2072 {
2073 struct azx *chip = bus->private_data;
2074 struct hda_codec *c;
2075 int power_on = 0;
2076
2077 list_for_each_entry(c, &bus->codec_list, list) {
2078 if (c->power_on) {
2079 power_on = 1;
2080 break;
2081 }
2082 }
2083 if (power_on)
2084 azx_init_chip(chip);
2085 else if (chip->running && power_save_controller)
2086 azx_stop_chip(chip);
2087 }
2088 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2089
2090 #ifdef CONFIG_PM
2091 /*
2092 * power management
2093 */
2094
2095 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2096 {
2097 struct hda_codec *codec;
2098
2099 list_for_each_entry(codec, &bus->codec_list, list) {
2100 if (snd_hda_codec_needs_resume(codec))
2101 return 1;
2102 }
2103 return 0;
2104 }
2105
2106 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2107 {
2108 struct snd_card *card = pci_get_drvdata(pci);
2109 struct azx *chip = card->private_data;
2110 int i;
2111
2112 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2113 azx_clear_irq_pending(chip);
2114 for (i = 0; i < AZX_MAX_PCMS; i++)
2115 snd_pcm_suspend_all(chip->pcm[i]);
2116 if (chip->initialized)
2117 snd_hda_suspend(chip->bus);
2118 azx_stop_chip(chip);
2119 if (chip->irq >= 0) {
2120 free_irq(chip->irq, chip);
2121 chip->irq = -1;
2122 }
2123 if (chip->msi)
2124 pci_disable_msi(chip->pci);
2125 pci_disable_device(pci);
2126 pci_save_state(pci);
2127 pci_set_power_state(pci, pci_choose_state(pci, state));
2128 return 0;
2129 }
2130
2131 static int azx_resume(struct pci_dev *pci)
2132 {
2133 struct snd_card *card = pci_get_drvdata(pci);
2134 struct azx *chip = card->private_data;
2135
2136 pci_set_power_state(pci, PCI_D0);
2137 pci_restore_state(pci);
2138 if (pci_enable_device(pci) < 0) {
2139 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2140 "disabling device\n");
2141 snd_card_disconnect(card);
2142 return -EIO;
2143 }
2144 pci_set_master(pci);
2145 if (chip->msi)
2146 if (pci_enable_msi(pci) < 0)
2147 chip->msi = 0;
2148 if (azx_acquire_irq(chip, 1) < 0)
2149 return -EIO;
2150 azx_init_pci(chip);
2151
2152 if (snd_hda_codecs_inuse(chip->bus))
2153 azx_init_chip(chip);
2154
2155 snd_hda_resume(chip->bus);
2156 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2157 return 0;
2158 }
2159 #endif /* CONFIG_PM */
2160
2161
2162 /*
2163 * reboot notifier for hang-up problem at power-down
2164 */
2165 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2166 {
2167 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2168 snd_hda_bus_reboot_notify(chip->bus);
2169 azx_stop_chip(chip);
2170 return NOTIFY_OK;
2171 }
2172
2173 static void azx_notifier_register(struct azx *chip)
2174 {
2175 chip->reboot_notifier.notifier_call = azx_halt;
2176 register_reboot_notifier(&chip->reboot_notifier);
2177 }
2178
2179 static void azx_notifier_unregister(struct azx *chip)
2180 {
2181 if (chip->reboot_notifier.notifier_call)
2182 unregister_reboot_notifier(&chip->reboot_notifier);
2183 }
2184
2185 /*
2186 * destructor
2187 */
2188 static int azx_free(struct azx *chip)
2189 {
2190 int i;
2191
2192 azx_notifier_unregister(chip);
2193
2194 if (chip->initialized) {
2195 azx_clear_irq_pending(chip);
2196 for (i = 0; i < chip->num_streams; i++)
2197 azx_stream_stop(chip, &chip->azx_dev[i]);
2198 azx_stop_chip(chip);
2199 }
2200
2201 if (chip->irq >= 0)
2202 free_irq(chip->irq, (void*)chip);
2203 if (chip->msi)
2204 pci_disable_msi(chip->pci);
2205 if (chip->remap_addr)
2206 iounmap(chip->remap_addr);
2207
2208 if (chip->azx_dev) {
2209 for (i = 0; i < chip->num_streams; i++)
2210 if (chip->azx_dev[i].bdl.area)
2211 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2212 }
2213 if (chip->rb.area)
2214 snd_dma_free_pages(&chip->rb);
2215 if (chip->posbuf.area)
2216 snd_dma_free_pages(&chip->posbuf);
2217 pci_release_regions(chip->pci);
2218 pci_disable_device(chip->pci);
2219 kfree(chip->azx_dev);
2220 kfree(chip);
2221
2222 return 0;
2223 }
2224
2225 static int azx_dev_free(struct snd_device *device)
2226 {
2227 return azx_free(device->device_data);
2228 }
2229
2230 /*
2231 * white/black-listing for position_fix
2232 */
2233 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2234 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2235 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2236 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2237 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2238 {}
2239 };
2240
2241 static int __devinit check_position_fix(struct azx *chip, int fix)
2242 {
2243 const struct snd_pci_quirk *q;
2244
2245 switch (fix) {
2246 case POS_FIX_LPIB:
2247 case POS_FIX_POSBUF:
2248 return fix;
2249 }
2250
2251 /* Check VIA/ATI HD Audio Controller exist */
2252 switch (chip->driver_type) {
2253 case AZX_DRIVER_VIA:
2254 case AZX_DRIVER_ATI:
2255 chip->via_dmapos_patch = 1;
2256 /* Use link position directly, avoid any transfer problem. */
2257 return POS_FIX_LPIB;
2258 }
2259 chip->via_dmapos_patch = 0;
2260
2261 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2262 if (q) {
2263 printk(KERN_INFO
2264 "hda_intel: position_fix set to %d "
2265 "for device %04x:%04x\n",
2266 q->value, q->subvendor, q->subdevice);
2267 return q->value;
2268 }
2269 return POS_FIX_AUTO;
2270 }
2271
2272 /*
2273 * black-lists for probe_mask
2274 */
2275 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2276 /* Thinkpad often breaks the controller communication when accessing
2277 * to the non-working (or non-existing) modem codec slot.
2278 */
2279 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2280 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2281 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2282 /* broken BIOS */
2283 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2284 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2285 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2286 /* forced codec slots */
2287 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2288 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2289 {}
2290 };
2291
2292 #define AZX_FORCE_CODEC_MASK 0x100
2293
2294 static void __devinit check_probe_mask(struct azx *chip, int dev)
2295 {
2296 const struct snd_pci_quirk *q;
2297
2298 chip->codec_probe_mask = probe_mask[dev];
2299 if (chip->codec_probe_mask == -1) {
2300 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2301 if (q) {
2302 printk(KERN_INFO
2303 "hda_intel: probe_mask set to 0x%x "
2304 "for device %04x:%04x\n",
2305 q->value, q->subvendor, q->subdevice);
2306 chip->codec_probe_mask = q->value;
2307 }
2308 }
2309
2310 /* check forced option */
2311 if (chip->codec_probe_mask != -1 &&
2312 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2313 chip->codec_mask = chip->codec_probe_mask & 0xff;
2314 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2315 chip->codec_mask);
2316 }
2317 }
2318
2319 /*
2320 * white/black-list for enable_msi
2321 */
2322 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2323 {}
2324 };
2325
2326 static void __devinit check_msi(struct azx *chip)
2327 {
2328 const struct snd_pci_quirk *q;
2329
2330 if (enable_msi >= 0) {
2331 chip->msi = !!enable_msi;
2332 return;
2333 }
2334 chip->msi = 1; /* enable MSI as default */
2335 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2336 if (q) {
2337 printk(KERN_INFO
2338 "hda_intel: msi for device %04x:%04x set to %d\n",
2339 q->subvendor, q->subdevice, q->value);
2340 chip->msi = q->value;
2341 }
2342 }
2343
2344
2345 /*
2346 * constructor
2347 */
2348 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2349 int dev, int driver_type,
2350 struct azx **rchip)
2351 {
2352 struct azx *chip;
2353 int i, err;
2354 unsigned short gcap;
2355 static struct snd_device_ops ops = {
2356 .dev_free = azx_dev_free,
2357 };
2358
2359 *rchip = NULL;
2360
2361 err = pci_enable_device(pci);
2362 if (err < 0)
2363 return err;
2364
2365 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2366 if (!chip) {
2367 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2368 pci_disable_device(pci);
2369 return -ENOMEM;
2370 }
2371
2372 spin_lock_init(&chip->reg_lock);
2373 mutex_init(&chip->open_mutex);
2374 chip->card = card;
2375 chip->pci = pci;
2376 chip->irq = -1;
2377 chip->driver_type = driver_type;
2378 check_msi(chip);
2379 chip->dev_index = dev;
2380 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2381
2382 chip->position_fix = check_position_fix(chip, position_fix[dev]);
2383 check_probe_mask(chip, dev);
2384
2385 chip->single_cmd = single_cmd;
2386
2387 if (bdl_pos_adj[dev] < 0) {
2388 switch (chip->driver_type) {
2389 case AZX_DRIVER_ICH:
2390 bdl_pos_adj[dev] = 1;
2391 break;
2392 default:
2393 bdl_pos_adj[dev] = 32;
2394 break;
2395 }
2396 }
2397
2398 #if BITS_PER_LONG != 64
2399 /* Fix up base address on ULI M5461 */
2400 if (chip->driver_type == AZX_DRIVER_ULI) {
2401 u16 tmp3;
2402 pci_read_config_word(pci, 0x40, &tmp3);
2403 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2404 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2405 }
2406 #endif
2407
2408 err = pci_request_regions(pci, "ICH HD audio");
2409 if (err < 0) {
2410 kfree(chip);
2411 pci_disable_device(pci);
2412 return err;
2413 }
2414
2415 chip->addr = pci_resource_start(pci, 0);
2416 chip->remap_addr = pci_ioremap_bar(pci, 0);
2417 if (chip->remap_addr == NULL) {
2418 snd_printk(KERN_ERR SFX "ioremap error\n");
2419 err = -ENXIO;
2420 goto errout;
2421 }
2422
2423 if (chip->msi)
2424 if (pci_enable_msi(pci) < 0)
2425 chip->msi = 0;
2426
2427 if (azx_acquire_irq(chip, 0) < 0) {
2428 err = -EBUSY;
2429 goto errout;
2430 }
2431
2432 pci_set_master(pci);
2433 synchronize_irq(chip->irq);
2434
2435 gcap = azx_readw(chip, GCAP);
2436 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2437
2438 /* disable SB600 64bit support for safety */
2439 if ((chip->driver_type == AZX_DRIVER_ATI) ||
2440 (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2441 struct pci_dev *p_smbus;
2442 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2443 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2444 NULL);
2445 if (p_smbus) {
2446 if (p_smbus->revision < 0x30)
2447 gcap &= ~ICH6_GCAP_64OK;
2448 pci_dev_put(p_smbus);
2449 }
2450 }
2451
2452 /* allow 64bit DMA address if supported by H/W */
2453 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2454 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2455 else {
2456 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2457 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2458 }
2459
2460 /* read number of streams from GCAP register instead of using
2461 * hardcoded value
2462 */
2463 chip->capture_streams = (gcap >> 8) & 0x0f;
2464 chip->playback_streams = (gcap >> 12) & 0x0f;
2465 if (!chip->playback_streams && !chip->capture_streams) {
2466 /* gcap didn't give any info, switching to old method */
2467
2468 switch (chip->driver_type) {
2469 case AZX_DRIVER_ULI:
2470 chip->playback_streams = ULI_NUM_PLAYBACK;
2471 chip->capture_streams = ULI_NUM_CAPTURE;
2472 break;
2473 case AZX_DRIVER_ATIHDMI:
2474 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2475 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2476 break;
2477 case AZX_DRIVER_GENERIC:
2478 default:
2479 chip->playback_streams = ICH6_NUM_PLAYBACK;
2480 chip->capture_streams = ICH6_NUM_CAPTURE;
2481 break;
2482 }
2483 }
2484 chip->capture_index_offset = 0;
2485 chip->playback_index_offset = chip->capture_streams;
2486 chip->num_streams = chip->playback_streams + chip->capture_streams;
2487 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2488 GFP_KERNEL);
2489 if (!chip->azx_dev) {
2490 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2491 goto errout;
2492 }
2493
2494 for (i = 0; i < chip->num_streams; i++) {
2495 /* allocate memory for the BDL for each stream */
2496 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2497 snd_dma_pci_data(chip->pci),
2498 BDL_SIZE, &chip->azx_dev[i].bdl);
2499 if (err < 0) {
2500 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2501 goto errout;
2502 }
2503 }
2504 /* allocate memory for the position buffer */
2505 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2506 snd_dma_pci_data(chip->pci),
2507 chip->num_streams * 8, &chip->posbuf);
2508 if (err < 0) {
2509 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2510 goto errout;
2511 }
2512 /* allocate CORB/RIRB */
2513 err = azx_alloc_cmd_io(chip);
2514 if (err < 0)
2515 goto errout;
2516
2517 /* initialize streams */
2518 azx_init_stream(chip);
2519
2520 /* initialize chip */
2521 azx_init_pci(chip);
2522 azx_init_chip(chip);
2523
2524 /* codec detection */
2525 if (!chip->codec_mask) {
2526 snd_printk(KERN_ERR SFX "no codecs found!\n");
2527 err = -ENODEV;
2528 goto errout;
2529 }
2530
2531 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2532 if (err <0) {
2533 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2534 goto errout;
2535 }
2536
2537 strcpy(card->driver, "HDA-Intel");
2538 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2539 sizeof(card->shortname));
2540 snprintf(card->longname, sizeof(card->longname),
2541 "%s at 0x%lx irq %i",
2542 card->shortname, chip->addr, chip->irq);
2543
2544 *rchip = chip;
2545 return 0;
2546
2547 errout:
2548 azx_free(chip);
2549 return err;
2550 }
2551
2552 static void power_down_all_codecs(struct azx *chip)
2553 {
2554 #ifdef CONFIG_SND_HDA_POWER_SAVE
2555 /* The codecs were powered up in snd_hda_codec_new().
2556 * Now all initialization done, so turn them down if possible
2557 */
2558 struct hda_codec *codec;
2559 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2560 snd_hda_power_down(codec);
2561 }
2562 #endif
2563 }
2564
2565 static int __devinit azx_probe(struct pci_dev *pci,
2566 const struct pci_device_id *pci_id)
2567 {
2568 static int dev;
2569 struct snd_card *card;
2570 struct azx *chip;
2571 int err;
2572
2573 if (dev >= SNDRV_CARDS)
2574 return -ENODEV;
2575 if (!enable[dev]) {
2576 dev++;
2577 return -ENOENT;
2578 }
2579
2580 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2581 if (err < 0) {
2582 snd_printk(KERN_ERR SFX "Error creating card!\n");
2583 return err;
2584 }
2585
2586 /* set this here since it's referred in snd_hda_load_patch() */
2587 snd_card_set_dev(card, &pci->dev);
2588
2589 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2590 if (err < 0)
2591 goto out_free;
2592 card->private_data = chip;
2593
2594 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2595 chip->beep_mode = beep_mode[dev];
2596 #endif
2597
2598 /* create codec instances */
2599 err = azx_codec_create(chip, model[dev]);
2600 if (err < 0)
2601 goto out_free;
2602 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2603 if (patch[dev]) {
2604 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2605 patch[dev]);
2606 err = snd_hda_load_patch(chip->bus, patch[dev]);
2607 if (err < 0)
2608 goto out_free;
2609 }
2610 #endif
2611 if (!probe_only[dev]) {
2612 err = azx_codec_configure(chip);
2613 if (err < 0)
2614 goto out_free;
2615 }
2616
2617 /* create PCM streams */
2618 err = snd_hda_build_pcms(chip->bus);
2619 if (err < 0)
2620 goto out_free;
2621
2622 /* create mixer controls */
2623 err = azx_mixer_create(chip);
2624 if (err < 0)
2625 goto out_free;
2626
2627 err = snd_card_register(card);
2628 if (err < 0)
2629 goto out_free;
2630
2631 pci_set_drvdata(pci, card);
2632 chip->running = 1;
2633 power_down_all_codecs(chip);
2634 azx_notifier_register(chip);
2635
2636 dev++;
2637 return err;
2638 out_free:
2639 snd_card_free(card);
2640 return err;
2641 }
2642
2643 static void __devexit azx_remove(struct pci_dev *pci)
2644 {
2645 snd_card_free(pci_get_drvdata(pci));
2646 pci_set_drvdata(pci, NULL);
2647 }
2648
2649 /* PCI IDs */
2650 static struct pci_device_id azx_ids[] = {
2651 /* ICH 6..10 */
2652 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2653 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2654 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2655 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2656 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2657 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2658 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2659 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2660 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2661 /* PCH */
2662 { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2663 /* SCH */
2664 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2665 /* ATI SB 450/600 */
2666 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2667 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2668 /* ATI HDMI */
2669 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2670 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2671 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2672 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2673 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2674 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2675 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2676 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2677 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2678 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2679 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2680 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2681 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2682 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2683 /* VIA VT8251/VT8237A */
2684 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2685 /* SIS966 */
2686 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2687 /* ULI M5461 */
2688 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2689 /* NVIDIA MCP */
2690 { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2691 { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2692 { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2693 { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2694 { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2695 { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2696 { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2697 { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2698 { PCI_DEVICE(0x10de, 0x0590), .driver_data = AZX_DRIVER_NVIDIA },
2699 { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2700 { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2701 { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2702 { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2703 { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2704 { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2705 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2706 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2707 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2708 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2709 { PCI_DEVICE(0x10de, 0x0d94), .driver_data = AZX_DRIVER_NVIDIA },
2710 { PCI_DEVICE(0x10de, 0x0d95), .driver_data = AZX_DRIVER_NVIDIA },
2711 { PCI_DEVICE(0x10de, 0x0d96), .driver_data = AZX_DRIVER_NVIDIA },
2712 { PCI_DEVICE(0x10de, 0x0d97), .driver_data = AZX_DRIVER_NVIDIA },
2713 /* Teradici */
2714 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2715 /* Creative X-Fi (CA0110-IBG) */
2716 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2717 /* the following entry conflicts with snd-ctxfi driver,
2718 * as ctxfi driver mutates from HD-audio to native mode with
2719 * a special command sequence.
2720 */
2721 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2722 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2723 .class_mask = 0xffffff,
2724 .driver_data = AZX_DRIVER_GENERIC },
2725 #else
2726 /* this entry seems still valid -- i.e. without emu20kx chip */
2727 { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2728 #endif
2729 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2730 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2731 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2732 .class_mask = 0xffffff,
2733 .driver_data = AZX_DRIVER_GENERIC },
2734 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2735 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2736 .class_mask = 0xffffff,
2737 .driver_data = AZX_DRIVER_GENERIC },
2738 { 0, }
2739 };
2740 MODULE_DEVICE_TABLE(pci, azx_ids);
2741
2742 /* pci_driver definition */
2743 static struct pci_driver driver = {
2744 .name = "HDA Intel",
2745 .id_table = azx_ids,
2746 .probe = azx_probe,
2747 .remove = __devexit_p(azx_remove),
2748 #ifdef CONFIG_PM
2749 .suspend = azx_suspend,
2750 .resume = azx_resume,
2751 #endif
2752 };
2753
2754 static int __init alsa_card_azx_init(void)
2755 {
2756 return pci_register_driver(&driver);
2757 }
2758
2759 static void __exit alsa_card_azx_exit(void)
2760 {
2761 pci_unregister_driver(&driver);
2762 }
2763
2764 module_init(alsa_card_azx_init)
2765 module_exit(alsa_card_azx_exit)
AMDTP streaming driver for the Linux FireWire stack (Juju)