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PCI: Change all drivers to use pci_device->revision
[firewire-audio.git] / drivers / ide / pci / via82cxxx.c
blob27e92fb9f95e0c49cdd1a874e017a8dc021a4f6a
1 /*
2 *
3 * Version 3.45
4 *
5 * VIA IDE driver for Linux. Supported southbridges:
6 *
7 * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
8 * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
9 * vt8235, vt8237, vt8237a
10 *
11 * Copyright (c) 2000-2002 Vojtech Pavlik
12 * Copyright (c) 2007 Bartlomiej Zolnierkiewicz
13 *
14 * Based on the work of:
15 * Michel Aubry
16 * Jeff Garzik
17 * Andre Hedrick
18 *
19 * Documentation:
20 * Obsolete device documentation publically available from via.com.tw
21 * Current device documentation available under NDA only
22 */
23
24 /*
25 * This program is free software; you can redistribute it and/or modify it
26 * under the terms of the GNU General Public License version 2 as published by
27 * the Free Software Foundation.
28 */
29
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/ioport.h>
33 #include <linux/blkdev.h>
34 #include <linux/pci.h>
35 #include <linux/init.h>
36 #include <linux/ide.h>
37 #include <linux/dmi.h>
38
39 #include <asm/io.h>
40
41 #ifdef CONFIG_PPC_CHRP
42 #include <asm/processor.h>
43 #endif
44
45 #include "ide-timing.h"
46
47 #define VIA_IDE_ENABLE 0x40
48 #define VIA_IDE_CONFIG 0x41
49 #define VIA_FIFO_CONFIG 0x43
50 #define VIA_MISC_1 0x44
51 #define VIA_MISC_2 0x45
52 #define VIA_MISC_3 0x46
53 #define VIA_DRIVE_TIMING 0x48
54 #define VIA_8BIT_TIMING 0x4e
55 #define VIA_ADDRESS_SETUP 0x4c
56 #define VIA_UDMA_TIMING 0x50
57
58 #define VIA_BAD_PREQ 0x01 /* Crashes if PREQ# till DDACK# set */
59 #define VIA_BAD_CLK66 0x02 /* 66 MHz clock doesn't work correctly */
60 #define VIA_SET_FIFO 0x04 /* Needs to have FIFO split set */
61 #define VIA_NO_UNMASK 0x08 /* Doesn't work with IRQ unmasking on */
62 #define VIA_BAD_ID 0x10 /* Has wrong vendor ID (0x1107) */
63 #define VIA_BAD_AST 0x20 /* Don't touch Address Setup Timing */
64
65 /*
66 * VIA SouthBridge chips.
67 */
68
69 static struct via_isa_bridge {
70 char *name;
71 u16 id;
72 u8 rev_min;
73 u8 rev_max;
74 u8 udma_mask;
75 u8 flags;
76 } via_isa_bridges[] = {
77 { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
78 { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
79 { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
80 { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
81 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
82 { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
83 { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
84 { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
85 { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, ATA_UDMA5, },
86 { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, ATA_UDMA5, },
87 { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, ATA_UDMA5, },
88 { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, ATA_UDMA5, },
89 { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, ATA_UDMA4, },
90 { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
91 { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, ATA_UDMA4, },
92 { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
93 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO },
94 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ },
95 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO },
96 { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO },
97 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO },
98 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK },
99 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
100 { NULL }
101 };
102
103 static unsigned int via_clock;
104 static char *via_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
105
106 struct via82cxxx_dev
107 {
108 struct via_isa_bridge *via_config;
109 unsigned int via_80w;
110 };
111
112 /**
113 * via_set_speed - write timing registers
114 * @dev: PCI device
115 * @dn: device
116 * @timing: IDE timing data to use
117 *
118 * via_set_speed writes timing values to the chipset registers
119 */
120
121 static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing)
122 {
123 struct pci_dev *dev = hwif->pci_dev;
124 struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev);
125 u8 t;
126
127 if (~vdev->via_config->flags & VIA_BAD_AST) {
128 pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
129 t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
130 pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
131 }
132
133 pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
134 ((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1));
135
136 pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
137 ((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1));
138
139 switch (vdev->via_config->udma_mask) {
140 case ATA_UDMA2: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
141 case ATA_UDMA4: t = timing->udma ? (0xe8 | (FIT(timing->udma, 2, 9) - 2)) : 0x0f; break;
142 case ATA_UDMA5: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
143 case ATA_UDMA6: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
144 default: return;
145 }
146
147 pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t);
148 }
149
150 /**
151 * via_set_drive - configure transfer mode
152 * @drive: Drive to set up
153 * @speed: desired speed
154 *
155 * via_set_drive() computes timing values configures the drive and
156 * the chipset to a desired transfer mode. It also can be called
157 * by upper layers.
158 */
159
160 static int via_set_drive(ide_drive_t *drive, u8 speed)
161 {
162 ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
163 struct via82cxxx_dev *vdev = pci_get_drvdata(drive->hwif->pci_dev);
164 struct ide_timing t, p;
165 unsigned int T, UT;
166
167 if (speed != XFER_PIO_SLOW)
168 ide_config_drive_speed(drive, speed);
169
170 T = 1000000000 / via_clock;
171
172 switch (vdev->via_config->udma_mask) {
173 case ATA_UDMA2: UT = T; break;
174 case ATA_UDMA4: UT = T/2; break;
175 case ATA_UDMA5: UT = T/3; break;
176 case ATA_UDMA6: UT = T/4; break;
177 default: UT = T;
178 }
179
180 ide_timing_compute(drive, speed, &t, T, UT);
181
182 if (peer->present) {
183 ide_timing_compute(peer, peer->current_speed, &p, T, UT);
184 ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
185 }
186
187 via_set_speed(HWIF(drive), drive->dn, &t);
188
189 if (!drive->init_speed)
190 drive->init_speed = speed;
191 drive->current_speed = speed;
192
193 return 0;
194 }
195
196 /**
197 * via82cxxx_tune_drive - PIO setup
198 * @drive: drive to set up
199 * @pio: mode to use (255 for 'best possible')
200 *
201 * A callback from the upper layers for PIO-only tuning.
202 */
203
204 static void via82cxxx_tune_drive(ide_drive_t *drive, u8 pio)
205 {
206 if (pio == 255) {
207 via_set_drive(drive, ide_find_best_pio_mode(drive));
208 return;
209 }
210
211 via_set_drive(drive, XFER_PIO_0 + min_t(u8, pio, 5));
212 }
213
214 /**
215 * via82cxxx_ide_dma_check - set up for DMA if possible
216 * @drive: IDE drive to set up
217 *
218 * Set up the drive for the highest supported speed considering the
219 * driver, controller and cable
220 */
221
222 static int via82cxxx_ide_dma_check (ide_drive_t *drive)
223 {
224 u8 speed = ide_max_dma_mode(drive);
225
226 if (speed == 0)
227 speed = ide_find_best_pio_mode(drive);
228
229 via_set_drive(drive, speed);
230
231 if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
232 return 0;
233
234 return -1;
235 }
236
237 static struct via_isa_bridge *via_config_find(struct pci_dev **isa)
238 {
239 struct via_isa_bridge *via_config;
240
241 for (via_config = via_isa_bridges; via_config->id; via_config++)
242 if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA +
243 !!(via_config->flags & VIA_BAD_ID),
244 via_config->id, NULL))) {
245
246 if ((*isa)->revision >= via_config->rev_min &&
247 (*isa)->revision <= via_config->rev_max)
248 break;
249 pci_dev_put(*isa);
250 }
251
252 return via_config;
253 }
254
255 /*
256 * Check and handle 80-wire cable presence
257 */
258 static void __devinit via_cable_detect(struct via82cxxx_dev *vdev, u32 u)
259 {
260 int i;
261
262 switch (vdev->via_config->udma_mask) {
263 case ATA_UDMA4:
264 for (i = 24; i >= 0; i -= 8)
265 if (((u >> (i & 16)) & 8) &&
266 ((u >> i) & 0x20) &&
267 (((u >> i) & 7) < 2)) {
268 /*
269 * 2x PCI clock and
270 * UDMA w/ < 3T/cycle
271 */
272 vdev->via_80w |= (1 << (1 - (i >> 4)));
273 }
274 break;
275
276 case ATA_UDMA5:
277 for (i = 24; i >= 0; i -= 8)
278 if (((u >> i) & 0x10) ||
279 (((u >> i) & 0x20) &&
280 (((u >> i) & 7) < 4))) {
281 /* BIOS 80-wire bit or
282 * UDMA w/ < 60ns/cycle
283 */
284 vdev->via_80w |= (1 << (1 - (i >> 4)));
285 }
286 break;
287
288 case ATA_UDMA6:
289 for (i = 24; i >= 0; i -= 8)
290 if (((u >> i) & 0x10) ||
291 (((u >> i) & 0x20) &&
292 (((u >> i) & 7) < 6))) {
293 /* BIOS 80-wire bit or
294 * UDMA w/ < 60ns/cycle
295 */
296 vdev->via_80w |= (1 << (1 - (i >> 4)));
297 }
298 break;
299 }
300 }
301
302 /**
303 * init_chipset_via82cxxx - initialization handler
304 * @dev: PCI device
305 * @name: Name of interface
306 *
307 * The initialization callback. Here we determine the IDE chip type
308 * and initialize its drive independent registers.
309 */
310
311 static unsigned int __devinit init_chipset_via82cxxx(struct pci_dev *dev, const char *name)
312 {
313 struct pci_dev *isa = NULL;
314 struct via82cxxx_dev *vdev;
315 struct via_isa_bridge *via_config;
316 u8 t, v;
317 u32 u;
318
319 vdev = kzalloc(sizeof(*vdev), GFP_KERNEL);
320 if (!vdev) {
321 printk(KERN_ERR "VP_IDE: out of memory :(\n");
322 return -ENOMEM;
323 }
324 pci_set_drvdata(dev, vdev);
325
326 /*
327 * Find the ISA bridge to see how good the IDE is.
328 */
329 vdev->via_config = via_config = via_config_find(&isa);
330
331 /* We checked this earlier so if it fails here deeep badness
332 is involved */
333
334 BUG_ON(!via_config->id);
335
336 /*
337 * Detect cable and configure Clk66
338 */
339 pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
340
341 via_cable_detect(vdev, u);
342
343 if (via_config->udma_mask == ATA_UDMA4) {
344 /* Enable Clk66 */
345 pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008);
346 } else if (via_config->flags & VIA_BAD_CLK66) {
347 /* Would cause trouble on 596a and 686 */
348 pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
349 }
350
351 /*
352 * Check whether interfaces are enabled.
353 */
354
355 pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);
356
357 /*
358 * Set up FIFO sizes and thresholds.
359 */
360
361 pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);
362
363 /* Disable PREQ# till DDACK# */
364 if (via_config->flags & VIA_BAD_PREQ) {
365 /* Would crash on 586b rev 41 */
366 t &= 0x7f;
367 }
368
369 /* Fix FIFO split between channels */
370 if (via_config->flags & VIA_SET_FIFO) {
371 t &= (t & 0x9f);
372 switch (v & 3) {
373 case 2: t |= 0x00; break; /* 16 on primary */
374 case 1: t |= 0x60; break; /* 16 on secondary */
375 case 3: t |= 0x20; break; /* 8 pri 8 sec */
376 }
377 }
378
379 pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);
380
381 /*
382 * Determine system bus clock.
383 */
384
385 via_clock = system_bus_clock() * 1000;
386
387 switch (via_clock) {
388 case 33000: via_clock = 33333; break;
389 case 37000: via_clock = 37500; break;
390 case 41000: via_clock = 41666; break;
391 }
392
393 if (via_clock < 20000 || via_clock > 50000) {
394 printk(KERN_WARNING "VP_IDE: User given PCI clock speed "
395 "impossible (%d), using 33 MHz instead.\n", via_clock);
396 printk(KERN_WARNING "VP_IDE: Use ide0=ata66 if you want "
397 "to assume 80-wire cable.\n");
398 via_clock = 33333;
399 }
400
401 /*
402 * Print the boot message.
403 */
404
405 printk(KERN_INFO "VP_IDE: VIA %s (rev %02x) IDE %sDMA%s "
406 "controller on pci%s\n",
407 via_config->name, isa->revision,
408 via_config->udma_mask ? "U" : "MW",
409 via_dma[via_config->udma_mask ?
410 (fls(via_config->udma_mask) - 1) : 0],
411 pci_name(dev));
412
413 pci_dev_put(isa);
414 return 0;
415 }
416
417 /*
418 * Cable special cases
419 */
420
421 static struct dmi_system_id cable_dmi_table[] = {
422 {
423 .ident = "Acer Ferrari 3400",
424 .matches = {
425 DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."),
426 DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"),
427 },
428 },
429 { }
430 };
431
432 static int via_cable_override(void)
433 {
434 /* Systems by DMI */
435 if (dmi_check_system(cable_dmi_table))
436 return 1;
437 return 0;
438 }
439
440 static u8 __devinit via82cxxx_cable_detect(ide_hwif_t *hwif)
441 {
442 struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev);
443
444 if (via_cable_override())
445 return ATA_CBL_PATA40_SHORT;
446
447 if ((vdev->via_80w >> hwif->channel) & 1)
448 return ATA_CBL_PATA80;
449 else
450 return ATA_CBL_PATA40;
451 }
452
453 static void __devinit init_hwif_via82cxxx(ide_hwif_t *hwif)
454 {
455 struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev);
456 int i;
457
458 hwif->autodma = 0;
459
460 hwif->tuneproc = &via82cxxx_tune_drive;
461 hwif->speedproc = &via_set_drive;
462
463
464 #ifdef CONFIG_PPC_CHRP
465 if(machine_is(chrp) && _chrp_type == _CHRP_Pegasos) {
466 hwif->irq = hwif->channel ? 15 : 14;
467 }
468 #endif
469
470 for (i = 0; i < 2; i++) {
471 hwif->drives[i].io_32bit = 1;
472 hwif->drives[i].unmask = (vdev->via_config->flags & VIA_NO_UNMASK) ? 0 : 1;
473 hwif->drives[i].autotune = 1;
474 hwif->drives[i].dn = hwif->channel * 2 + i;
475 }
476
477 if (!hwif->dma_base)
478 return;
479
480 hwif->atapi_dma = 1;
481
482 hwif->ultra_mask = vdev->via_config->udma_mask;
483 hwif->mwdma_mask = 0x07;
484 hwif->swdma_mask = 0x07;
485
486 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
487 hwif->cbl = via82cxxx_cable_detect(hwif);
488
489 hwif->ide_dma_check = &via82cxxx_ide_dma_check;
490 if (!noautodma)
491 hwif->autodma = 1;
492 hwif->drives[0].autodma = hwif->autodma;
493 hwif->drives[1].autodma = hwif->autodma;
494 }
495
496 static ide_pci_device_t via82cxxx_chipsets[] __devinitdata = {
497 { /* 0 */
498 .name = "VP_IDE",
499 .init_chipset = init_chipset_via82cxxx,
500 .init_hwif = init_hwif_via82cxxx,
501 .channels = 2,
502 .autodma = NOAUTODMA,
503 .enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}},
504 .bootable = ON_BOARD
505 },{ /* 1 */
506 .name = "VP_IDE",
507 .init_chipset = init_chipset_via82cxxx,
508 .init_hwif = init_hwif_via82cxxx,
509 .channels = 2,
510 .autodma = AUTODMA,
511 .enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
512 .bootable = ON_BOARD,
513 }
514 };
515
516 static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_id *id)
517 {
518 struct pci_dev *isa = NULL;
519 struct via_isa_bridge *via_config;
520 /*
521 * Find the ISA bridge and check we know what it is.
522 */
523 via_config = via_config_find(&isa);
524 pci_dev_put(isa);
525 if (!via_config->id) {
526 printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, disabling DMA.\n");
527 return -ENODEV;
528 }
529 return ide_setup_pci_device(dev, &via82cxxx_chipsets[id->driver_data]);
530 }
531
532 static struct pci_device_id via_pci_tbl[] = {
533 { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
534 { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
535 { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_6410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
536 { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_SATA_EIDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
537 { 0, },
538 };
539 MODULE_DEVICE_TABLE(pci, via_pci_tbl);
540
541 static struct pci_driver driver = {
542 .name = "VIA_IDE",
543 .id_table = via_pci_tbl,
544 .probe = via_init_one,
545 };
546
547 static int __init via_ide_init(void)
548 {
549 return ide_pci_register_driver(&driver);
550 }
551
552 module_init(via_ide_init);
553
554 MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick");
555 MODULE_DESCRIPTION("PCI driver module for VIA IDE");
556 MODULE_LICENSE("GPL");
AMDTP streaming driver for the Linux FireWire stack (Juju)