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x86: move phys_cpu_present_map to smpboot.c
[firewire-audio.git] / arch / x86 / kernel / mpparse_32.c
blobf7eceabc7da909873f655b20f10669b864ef0bb0
1 /*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16 #include <linux/mm.h>
17 #include <linux/init.h>
18 #include <linux/acpi.h>
19 #include <linux/delay.h>
20 #include <linux/bootmem.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/mc146818rtc.h>
23 #include <linux/bitops.h>
24
25 #include <asm/smp.h>
26 #include <asm/acpi.h>
27 #include <asm/mtrr.h>
28 #include <asm/mpspec.h>
29 #include <asm/io_apic.h>
30 #include <asm/bios_ebda.h>
31
32 #include <mach_apic.h>
33 #include <mach_apicdef.h>
34 #include <mach_mpparse.h>
35
36 /* Have we found an MP table */
37 int smp_found_config;
38 unsigned int __cpuinitdata maxcpus = NR_CPUS;
39
40 /*
41 * Various Linux-internal data structures created from the
42 * MP-table.
43 */
44 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
45 int mp_bus_id_to_type [MAX_MP_BUSSES];
46 #endif
47 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
48 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
49 static int mp_current_pci_id;
50
51 /* I/O APIC entries */
52 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
53
54 /* # of MP IRQ source entries */
55 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
56
57 /* MP IRQ source entries */
58 int mp_irq_entries;
59
60 int nr_ioapics;
61
62 int pic_mode;
63
64 unsigned int def_to_bigsmp = 0;
65
66 /* Processor that is doing the boot up */
67 unsigned int boot_cpu_physical_apicid = -1U;
68 /* Internal processor count */
69 unsigned int num_processors;
70
71 unsigned disabled_cpus __cpuinitdata;
72
73 /* Make it easy to share the UP and SMP code: */
74 #ifndef CONFIG_X86_SMP
75 physid_mask_t phys_cpu_present_map;
76 #endif
77
78 #ifndef CONFIG_SMP
79 DEFINE_PER_CPU(u16, x86_bios_cpu_apicid) = BAD_APICID;
80 #endif
81
82 /*
83 * Intel MP BIOS table parsing routines:
84 */
85
86
87 /*
88 * Checksum an MP configuration block.
89 */
90
91 static int __init mpf_checksum(unsigned char *mp, int len)
92 {
93 int sum = 0;
94
95 while (len--)
96 sum += *mp++;
97
98 return sum & 0xFF;
99 }
100
101 #ifdef CONFIG_X86_NUMAQ
102 /*
103 * Have to match translation table entries to main table entries by counter
104 * hence the mpc_record variable .... can't see a less disgusting way of
105 * doing this ....
106 */
107
108 static int mpc_record;
109 static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __cpuinitdata;
110 #endif
111
112 static void __cpuinit generic_processor_info(int apicid, int version)
113 {
114 int cpu;
115 cpumask_t tmp_map;
116 physid_mask_t phys_cpu;
117
118 /*
119 * Validate version
120 */
121 if (version == 0x0) {
122 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
123 "fixing up to 0x10. (tell your hw vendor)\n",
124 version);
125 version = 0x10;
126 }
127 apic_version[apicid] = version;
128
129 phys_cpu = apicid_to_cpu_present(apicid);
130 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
131
132 if (num_processors >= NR_CPUS) {
133 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
134 " Processor ignored.\n", NR_CPUS);
135 return;
136 }
137
138 if (num_processors >= maxcpus) {
139 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
140 " Processor ignored.\n", maxcpus);
141 return;
142 }
143
144 num_processors++;
145 cpus_complement(tmp_map, cpu_present_map);
146 cpu = first_cpu(tmp_map);
147
148 if (apicid == boot_cpu_physical_apicid)
149 /*
150 * x86_bios_cpu_apicid is required to have processors listed
151 * in same order as logical cpu numbers. Hence the first
152 * entry is BSP, and so on.
153 */
154 cpu = 0;
155
156 /*
157 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
158 * but we need to work other dependencies like SMP_SUSPEND etc
159 * before this can be done without some confusion.
160 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
161 * - Ashok Raj <ashok.raj@intel.com>
162 */
163 if (num_processors > 8) {
164 switch (boot_cpu_data.x86_vendor) {
165 case X86_VENDOR_INTEL:
166 if (!APIC_XAPIC(version)) {
167 def_to_bigsmp = 0;
168 break;
169 }
170 /* If P4 and above fall through */
171 case X86_VENDOR_AMD:
172 def_to_bigsmp = 1;
173 }
174 }
175 #ifdef CONFIG_SMP
176 /* are we being called early in kernel startup? */
177 if (x86_cpu_to_apicid_early_ptr) {
178 u16 *cpu_to_apicid = x86_cpu_to_apicid_early_ptr;
179 u16 *bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr;
180
181 cpu_to_apicid[cpu] = apicid;
182 bios_cpu_apicid[cpu] = apicid;
183 } else {
184 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
185 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
186 }
187 #endif
188 cpu_set(cpu, cpu_possible_map);
189 cpu_set(cpu, cpu_present_map);
190 }
191
192 static void __cpuinit MP_processor_info(struct mpc_config_processor *m)
193 {
194 int apicid;
195
196 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
197 disabled_cpus++;
198 return;
199 }
200
201 #ifdef CONFIG_X86_NUMAQ
202 apicid = mpc_apic_id(m, translation_table[mpc_record]);
203 #else
204 Dprintk("Processor #%d %u:%u APIC version %d\n",
205 m->mpc_apicid,
206 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
207 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
208 m->mpc_apicver);
209 apicid = m->mpc_apicid;
210 #endif
211
212 if (m->mpc_featureflag&(1<<0))
213 Dprintk(" Floating point unit present.\n");
214 if (m->mpc_featureflag&(1<<7))
215 Dprintk(" Machine Exception supported.\n");
216 if (m->mpc_featureflag&(1<<8))
217 Dprintk(" 64 bit compare & exchange supported.\n");
218 if (m->mpc_featureflag&(1<<9))
219 Dprintk(" Internal APIC present.\n");
220 if (m->mpc_featureflag&(1<<11))
221 Dprintk(" SEP present.\n");
222 if (m->mpc_featureflag&(1<<12))
223 Dprintk(" MTRR present.\n");
224 if (m->mpc_featureflag&(1<<13))
225 Dprintk(" PGE present.\n");
226 if (m->mpc_featureflag&(1<<14))
227 Dprintk(" MCA present.\n");
228 if (m->mpc_featureflag&(1<<15))
229 Dprintk(" CMOV present.\n");
230 if (m->mpc_featureflag&(1<<16))
231 Dprintk(" PAT present.\n");
232 if (m->mpc_featureflag&(1<<17))
233 Dprintk(" PSE present.\n");
234 if (m->mpc_featureflag&(1<<18))
235 Dprintk(" PSN present.\n");
236 if (m->mpc_featureflag&(1<<19))
237 Dprintk(" Cache Line Flush Instruction present.\n");
238 /* 20 Reserved */
239 if (m->mpc_featureflag&(1<<21))
240 Dprintk(" Debug Trace and EMON Store present.\n");
241 if (m->mpc_featureflag&(1<<22))
242 Dprintk(" ACPI Thermal Throttle Registers present.\n");
243 if (m->mpc_featureflag&(1<<23))
244 Dprintk(" MMX present.\n");
245 if (m->mpc_featureflag&(1<<24))
246 Dprintk(" FXSR present.\n");
247 if (m->mpc_featureflag&(1<<25))
248 Dprintk(" XMM present.\n");
249 if (m->mpc_featureflag&(1<<26))
250 Dprintk(" Willamette New Instructions present.\n");
251 if (m->mpc_featureflag&(1<<27))
252 Dprintk(" Self Snoop present.\n");
253 if (m->mpc_featureflag&(1<<28))
254 Dprintk(" HT present.\n");
255 if (m->mpc_featureflag&(1<<29))
256 Dprintk(" Thermal Monitor present.\n");
257 /* 30, 31 Reserved */
258
259
260 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
261 Dprintk(" Bootup CPU\n");
262 boot_cpu_physical_apicid = m->mpc_apicid;
263 }
264
265 generic_processor_info(apicid, m->mpc_apicver);
266 }
267
268 static void __init MP_bus_info (struct mpc_config_bus *m)
269 {
270 char str[7];
271
272 memcpy(str, m->mpc_bustype, 6);
273 str[6] = 0;
274
275 #ifdef CONFIG_X86_NUMAQ
276 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
277 #else
278 Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
279 #endif
280
281 #if MAX_MP_BUSSES < 256
282 if (m->mpc_busid >= MAX_MP_BUSSES) {
283 printk(KERN_WARNING "MP table busid value (%d) for bustype %s "
284 " is too large, max. supported is %d\n",
285 m->mpc_busid, str, MAX_MP_BUSSES - 1);
286 return;
287 }
288 #endif
289
290 set_bit(m->mpc_busid, mp_bus_not_pci);
291 if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
292 #ifdef CONFIG_X86_NUMAQ
293 mpc_oem_pci_bus(m, translation_table[mpc_record]);
294 #endif
295 clear_bit(m->mpc_busid, mp_bus_not_pci);
296 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
297 mp_current_pci_id++;
298 #if defined(CONFIG_EISA) || defined (CONFIG_MCA)
299 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
300 } else if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
301 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
302 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
303 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
304 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
305 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
306 } else {
307 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
308 #endif
309 }
310 }
311
312 static int bad_ioapic(unsigned long address)
313 {
314 if (nr_ioapics >= MAX_IO_APICS) {
315 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
316 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
317 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
318 }
319 if (!address) {
320 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
321 " found in table, skipping!\n");
322 return 1;
323 }
324 return 0;
325 }
326
327 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
328 {
329 if (!(m->mpc_flags & MPC_APIC_USABLE))
330 return;
331
332 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n",
333 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
334
335 if (bad_ioapic(m->mpc_apicaddr))
336 return;
337
338 mp_ioapics[nr_ioapics] = *m;
339 nr_ioapics++;
340 }
341
342 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
343 {
344 mp_irqs [mp_irq_entries] = *m;
345 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
346 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
347 m->mpc_irqtype, m->mpc_irqflag & 3,
348 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
349 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
350 if (++mp_irq_entries == MAX_IRQ_SOURCES)
351 panic("Max # of irq sources exceeded!!\n");
352 }
353
354 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
355 {
356 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
357 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
358 m->mpc_irqtype, m->mpc_irqflag & 3,
359 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
360 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
361 }
362
363 #ifdef CONFIG_X86_NUMAQ
364 static void __init MP_translation_info (struct mpc_config_translation *m)
365 {
366 printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
367
368 if (mpc_record >= MAX_MPC_ENTRY)
369 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
370 else
371 translation_table[mpc_record] = m; /* stash this for later */
372 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
373 node_set_online(m->trans_quad);
374 }
375
376 /*
377 * Read/parse the MPC oem tables
378 */
379
380 static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
381 unsigned short oemsize)
382 {
383 int count = sizeof (*oemtable); /* the header size */
384 unsigned char *oemptr = ((unsigned char *)oemtable)+count;
385
386 mpc_record = 0;
387 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
388 if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
389 {
390 printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
391 oemtable->oem_signature[0],
392 oemtable->oem_signature[1],
393 oemtable->oem_signature[2],
394 oemtable->oem_signature[3]);
395 return;
396 }
397 if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
398 {
399 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
400 return;
401 }
402 while (count < oemtable->oem_length) {
403 switch (*oemptr) {
404 case MP_TRANSLATION:
405 {
406 struct mpc_config_translation *m=
407 (struct mpc_config_translation *)oemptr;
408 MP_translation_info(m);
409 oemptr += sizeof(*m);
410 count += sizeof(*m);
411 ++mpc_record;
412 break;
413 }
414 default:
415 {
416 printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
417 return;
418 }
419 }
420 }
421 }
422
423 static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
424 char *productid)
425 {
426 if (strncmp(oem, "IBM NUMA", 8))
427 printk("Warning! May not be a NUMA-Q system!\n");
428 if (mpc->mpc_oemptr)
429 smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
430 mpc->mpc_oemsize);
431 }
432 #endif /* CONFIG_X86_NUMAQ */
433
434 /*
435 * Read/parse the MPC
436 */
437
438 static int __init smp_read_mpc(struct mp_config_table *mpc)
439 {
440 char str[16];
441 char oem[10];
442 int count=sizeof(*mpc);
443 unsigned char *mpt=((unsigned char *)mpc)+count;
444
445 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
446 printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
447 *(u32 *)mpc->mpc_signature);
448 return 0;
449 }
450 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
451 printk(KERN_ERR "SMP mptable: checksum error!\n");
452 return 0;
453 }
454 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
455 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
456 mpc->mpc_spec);
457 return 0;
458 }
459 if (!mpc->mpc_lapic) {
460 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
461 return 0;
462 }
463 memcpy(oem,mpc->mpc_oem,8);
464 oem[8]=0;
465 printk(KERN_INFO "OEM ID: %s ",oem);
466
467 memcpy(str,mpc->mpc_productid,12);
468 str[12]=0;
469 printk("Product ID: %s ",str);
470
471 mps_oem_check(mpc, oem, str);
472
473 printk("APIC at: 0x%X\n", mpc->mpc_lapic);
474
475 /*
476 * Save the local APIC address (it might be non-default) -- but only
477 * if we're not using ACPI.
478 */
479 if (!acpi_lapic)
480 mp_lapic_addr = mpc->mpc_lapic;
481
482 /*
483 * Now process the configuration blocks.
484 */
485 #ifdef CONFIG_X86_NUMAQ
486 mpc_record = 0;
487 #endif
488 while (count < mpc->mpc_length) {
489 switch(*mpt) {
490 case MP_PROCESSOR:
491 {
492 struct mpc_config_processor *m=
493 (struct mpc_config_processor *)mpt;
494 /* ACPI may have already provided this data */
495 if (!acpi_lapic)
496 MP_processor_info(m);
497 mpt += sizeof(*m);
498 count += sizeof(*m);
499 break;
500 }
501 case MP_BUS:
502 {
503 struct mpc_config_bus *m=
504 (struct mpc_config_bus *)mpt;
505 MP_bus_info(m);
506 mpt += sizeof(*m);
507 count += sizeof(*m);
508 break;
509 }
510 case MP_IOAPIC:
511 {
512 struct mpc_config_ioapic *m=
513 (struct mpc_config_ioapic *)mpt;
514 MP_ioapic_info(m);
515 mpt+=sizeof(*m);
516 count+=sizeof(*m);
517 break;
518 }
519 case MP_INTSRC:
520 {
521 struct mpc_config_intsrc *m=
522 (struct mpc_config_intsrc *)mpt;
523
524 MP_intsrc_info(m);
525 mpt+=sizeof(*m);
526 count+=sizeof(*m);
527 break;
528 }
529 case MP_LINTSRC:
530 {
531 struct mpc_config_lintsrc *m=
532 (struct mpc_config_lintsrc *)mpt;
533 MP_lintsrc_info(m);
534 mpt+=sizeof(*m);
535 count+=sizeof(*m);
536 break;
537 }
538 default:
539 {
540 count = mpc->mpc_length;
541 break;
542 }
543 }
544 #ifdef CONFIG_X86_NUMAQ
545 ++mpc_record;
546 #endif
547 }
548 setup_apic_routing();
549 if (!num_processors)
550 printk(KERN_ERR "SMP mptable: no processors registered!\n");
551 return num_processors;
552 }
553
554 static int __init ELCR_trigger(unsigned int irq)
555 {
556 unsigned int port;
557
558 port = 0x4d0 + (irq >> 3);
559 return (inb(port) >> (irq & 7)) & 1;
560 }
561
562 static void __init construct_default_ioirq_mptable(int mpc_default_type)
563 {
564 struct mpc_config_intsrc intsrc;
565 int i;
566 int ELCR_fallback = 0;
567
568 intsrc.mpc_type = MP_INTSRC;
569 intsrc.mpc_irqflag = 0; /* conforming */
570 intsrc.mpc_srcbus = 0;
571 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
572
573 intsrc.mpc_irqtype = mp_INT;
574
575 /*
576 * If true, we have an ISA/PCI system with no IRQ entries
577 * in the MP table. To prevent the PCI interrupts from being set up
578 * incorrectly, we try to use the ELCR. The sanity check to see if
579 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
580 * never be level sensitive, so we simply see if the ELCR agrees.
581 * If it does, we assume it's valid.
582 */
583 if (mpc_default_type == 5) {
584 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
585
586 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
587 printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
588 else {
589 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
590 ELCR_fallback = 1;
591 }
592 }
593
594 for (i = 0; i < 16; i++) {
595 switch (mpc_default_type) {
596 case 2:
597 if (i == 0 || i == 13)
598 continue; /* IRQ0 & IRQ13 not connected */
599 /* fall through */
600 default:
601 if (i == 2)
602 continue; /* IRQ2 is never connected */
603 }
604
605 if (ELCR_fallback) {
606 /*
607 * If the ELCR indicates a level-sensitive interrupt, we
608 * copy that information over to the MP table in the
609 * irqflag field (level sensitive, active high polarity).
610 */
611 if (ELCR_trigger(i))
612 intsrc.mpc_irqflag = 13;
613 else
614 intsrc.mpc_irqflag = 0;
615 }
616
617 intsrc.mpc_srcbusirq = i;
618 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
619 MP_intsrc_info(&intsrc);
620 }
621
622 intsrc.mpc_irqtype = mp_ExtINT;
623 intsrc.mpc_srcbusirq = 0;
624 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
625 MP_intsrc_info(&intsrc);
626 }
627
628 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
629 {
630 struct mpc_config_processor processor;
631 struct mpc_config_bus bus;
632 struct mpc_config_ioapic ioapic;
633 struct mpc_config_lintsrc lintsrc;
634 int linttypes[2] = { mp_ExtINT, mp_NMI };
635 int i;
636
637 /*
638 * local APIC has default address
639 */
640 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
641
642 /*
643 * 2 CPUs, numbered 0 & 1.
644 */
645 processor.mpc_type = MP_PROCESSOR;
646 /* Either an integrated APIC or a discrete 82489DX. */
647 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
648 processor.mpc_cpuflag = CPU_ENABLED;
649 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
650 (boot_cpu_data.x86_model << 4) |
651 boot_cpu_data.x86_mask;
652 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
653 processor.mpc_reserved[0] = 0;
654 processor.mpc_reserved[1] = 0;
655 for (i = 0; i < 2; i++) {
656 processor.mpc_apicid = i;
657 MP_processor_info(&processor);
658 }
659
660 bus.mpc_type = MP_BUS;
661 bus.mpc_busid = 0;
662 switch (mpc_default_type) {
663 default:
664 printk("???\n");
665 printk(KERN_ERR "Unknown standard configuration %d\n",
666 mpc_default_type);
667 /* fall through */
668 case 1:
669 case 5:
670 memcpy(bus.mpc_bustype, "ISA ", 6);
671 break;
672 case 2:
673 case 6:
674 case 3:
675 memcpy(bus.mpc_bustype, "EISA ", 6);
676 break;
677 case 4:
678 case 7:
679 memcpy(bus.mpc_bustype, "MCA ", 6);
680 }
681 MP_bus_info(&bus);
682 if (mpc_default_type > 4) {
683 bus.mpc_busid = 1;
684 memcpy(bus.mpc_bustype, "PCI ", 6);
685 MP_bus_info(&bus);
686 }
687
688 ioapic.mpc_type = MP_IOAPIC;
689 ioapic.mpc_apicid = 2;
690 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
691 ioapic.mpc_flags = MPC_APIC_USABLE;
692 ioapic.mpc_apicaddr = 0xFEC00000;
693 MP_ioapic_info(&ioapic);
694
695 /*
696 * We set up most of the low 16 IO-APIC pins according to MPS rules.
697 */
698 construct_default_ioirq_mptable(mpc_default_type);
699
700 lintsrc.mpc_type = MP_LINTSRC;
701 lintsrc.mpc_irqflag = 0; /* conforming */
702 lintsrc.mpc_srcbusid = 0;
703 lintsrc.mpc_srcbusirq = 0;
704 lintsrc.mpc_destapic = MP_APIC_ALL;
705 for (i = 0; i < 2; i++) {
706 lintsrc.mpc_irqtype = linttypes[i];
707 lintsrc.mpc_destapiclint = i;
708 MP_lintsrc_info(&lintsrc);
709 }
710 }
711
712 static struct intel_mp_floating *mpf_found;
713
714 /*
715 * Scan the memory blocks for an SMP configuration block.
716 */
717 void __init get_smp_config (void)
718 {
719 struct intel_mp_floating *mpf = mpf_found;
720
721 /*
722 * ACPI supports both logical (e.g. Hyper-Threading) and physical
723 * processors, where MPS only supports physical.
724 */
725 if (acpi_lapic && acpi_ioapic) {
726 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
727 return;
728 }
729 else if (acpi_lapic)
730 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
731
732 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
733 if (mpf->mpf_feature2 & (1<<7)) {
734 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
735 pic_mode = 1;
736 } else {
737 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
738 pic_mode = 0;
739 }
740
741 /*
742 * Now see if we need to read further.
743 */
744 if (mpf->mpf_feature1 != 0) {
745
746 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
747 construct_default_ISA_mptable(mpf->mpf_feature1);
748
749 } else if (mpf->mpf_physptr) {
750
751 /*
752 * Read the physical hardware table. Anything here will
753 * override the defaults.
754 */
755 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
756 smp_found_config = 0;
757 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
758 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
759 return;
760 }
761 /*
762 * If there are no explicit MP IRQ entries, then we are
763 * broken. We set up most of the low 16 IO-APIC pins to
764 * ISA defaults and hope it will work.
765 */
766 if (!mp_irq_entries) {
767 struct mpc_config_bus bus;
768
769 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
770
771 bus.mpc_type = MP_BUS;
772 bus.mpc_busid = 0;
773 memcpy(bus.mpc_bustype, "ISA ", 6);
774 MP_bus_info(&bus);
775
776 construct_default_ioirq_mptable(0);
777 }
778
779 } else
780 BUG();
781
782 printk(KERN_INFO "Processors: %d\n", num_processors);
783 /*
784 * Only use the first configuration found.
785 */
786 }
787
788 static int __init smp_scan_config (unsigned long base, unsigned long length)
789 {
790 unsigned long *bp = phys_to_virt(base);
791 struct intel_mp_floating *mpf;
792
793 printk(KERN_INFO "Scan SMP from %p for %ld bytes.\n", bp,length);
794 if (sizeof(*mpf) != 16)
795 printk("Error: MPF size\n");
796
797 while (length > 0) {
798 mpf = (struct intel_mp_floating *)bp;
799 if ((*bp == SMP_MAGIC_IDENT) &&
800 (mpf->mpf_length == 1) &&
801 !mpf_checksum((unsigned char *)bp, 16) &&
802 ((mpf->mpf_specification == 1)
803 || (mpf->mpf_specification == 4)) ) {
804
805 smp_found_config = 1;
806 printk(KERN_INFO "found SMP MP-table at [%p] %08lx\n",
807 mpf, virt_to_phys(mpf));
808 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE,
809 BOOTMEM_DEFAULT);
810 if (mpf->mpf_physptr) {
811 /*
812 * We cannot access to MPC table to compute
813 * table size yet, as only few megabytes from
814 * the bottom is mapped now.
815 * PC-9800's MPC table places on the very last
816 * of physical memory; so that simply reserving
817 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
818 * in reserve_bootmem.
819 */
820 unsigned long size = PAGE_SIZE;
821 unsigned long end = max_low_pfn * PAGE_SIZE;
822 if (mpf->mpf_physptr + size > end)
823 size = end - mpf->mpf_physptr;
824 reserve_bootmem(mpf->mpf_physptr, size,
825 BOOTMEM_DEFAULT);
826 }
827
828 mpf_found = mpf;
829 return 1;
830 }
831 bp += 4;
832 length -= 16;
833 }
834 return 0;
835 }
836
837 void __init find_smp_config (void)
838 {
839 unsigned int address;
840
841 /*
842 * FIXME: Linux assumes you have 640K of base ram..
843 * this continues the error...
844 *
845 * 1) Scan the bottom 1K for a signature
846 * 2) Scan the top 1K of base RAM
847 * 3) Scan the 64K of bios
848 */
849 if (smp_scan_config(0x0,0x400) ||
850 smp_scan_config(639*0x400,0x400) ||
851 smp_scan_config(0xF0000,0x10000))
852 return;
853 /*
854 * If it is an SMP machine we should know now, unless the
855 * configuration is in an EISA/MCA bus machine with an
856 * extended bios data area.
857 *
858 * there is a real-mode segmented pointer pointing to the
859 * 4K EBDA area at 0x40E, calculate and scan it here.
860 *
861 * NOTE! There are Linux loaders that will corrupt the EBDA
862 * area, and as such this kind of SMP config may be less
863 * trustworthy, simply because the SMP table may have been
864 * stomped on during early boot. These loaders are buggy and
865 * should be fixed.
866 *
867 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
868 */
869
870 address = get_bios_ebda();
871 if (address)
872 smp_scan_config(address, 0x400);
873 }
874
875 /* --------------------------------------------------------------------------
876 ACPI-based MP Configuration
877 -------------------------------------------------------------------------- */
878
879 #ifdef CONFIG_ACPI
880
881 void __init mp_register_lapic_address(u64 address)
882 {
883 mp_lapic_addr = (unsigned long) address;
884
885 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
886
887 if (boot_cpu_physical_apicid == -1U)
888 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
889
890 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
891 }
892
893 void __cpuinit mp_register_lapic (u8 id, u8 enabled)
894 {
895 if (MAX_APICS - id <= 0) {
896 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
897 id, MAX_APICS);
898 return;
899 }
900
901 if (!enabled) {
902 ++disabled_cpus;
903 return;
904 }
905
906 generic_processor_info(id, GET_APIC_VERSION(apic_read(APIC_LVR)));
907 }
908
909 #ifdef CONFIG_X86_IO_APIC
910
911 #define MP_ISA_BUS 0
912 #define MP_MAX_IOAPIC_PIN 127
913
914 static struct mp_ioapic_routing {
915 int apic_id;
916 int gsi_base;
917 int gsi_end;
918 u32 pin_programmed[4];
919 } mp_ioapic_routing[MAX_IO_APICS];
920
921 static int mp_find_ioapic (int gsi)
922 {
923 int i = 0;
924
925 /* Find the IOAPIC that manages this GSI. */
926 for (i = 0; i < nr_ioapics; i++) {
927 if ((gsi >= mp_ioapic_routing[i].gsi_base)
928 && (gsi <= mp_ioapic_routing[i].gsi_end))
929 return i;
930 }
931
932 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
933
934 return -1;
935 }
936
937 static u8 uniq_ioapic_id(u8 id)
938 {
939 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
940 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
941 return io_apic_get_unique_id(nr_ioapics, id);
942 else
943 return id;
944 }
945
946 void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base)
947 {
948 int idx = 0;
949
950 if (bad_ioapic(address))
951 return;
952
953 idx = nr_ioapics;
954
955 mp_ioapics[idx].mpc_type = MP_IOAPIC;
956 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
957 mp_ioapics[idx].mpc_apicaddr = address;
958
959 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
960 mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id);
961 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
962
963 /*
964 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
965 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
966 */
967 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
968 mp_ioapic_routing[idx].gsi_base = gsi_base;
969 mp_ioapic_routing[idx].gsi_end = gsi_base +
970 io_apic_get_redir_entries(idx);
971
972 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
973 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
974 mp_ioapics[idx].mpc_apicver,
975 mp_ioapics[idx].mpc_apicaddr,
976 mp_ioapic_routing[idx].gsi_base,
977 mp_ioapic_routing[idx].gsi_end);
978
979 nr_ioapics++;
980 }
981
982 void __init
983 mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
984 {
985 struct mpc_config_intsrc intsrc;
986 int ioapic = -1;
987 int pin = -1;
988
989 /*
990 * Convert 'gsi' to 'ioapic.pin'.
991 */
992 ioapic = mp_find_ioapic(gsi);
993 if (ioapic < 0)
994 return;
995 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
996
997 /*
998 * TBD: This check is for faulty timer entries, where the override
999 * erroneously sets the trigger to level, resulting in a HUGE
1000 * increase of timer interrupts!
1001 */
1002 if ((bus_irq == 0) && (trigger == 3))
1003 trigger = 1;
1004
1005 intsrc.mpc_type = MP_INTSRC;
1006 intsrc.mpc_irqtype = mp_INT;
1007 intsrc.mpc_irqflag = (trigger << 2) | polarity;
1008 intsrc.mpc_srcbus = MP_ISA_BUS;
1009 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
1010 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
1011 intsrc.mpc_dstirq = pin; /* INTIN# */
1012
1013 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
1014 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1015 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1016 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
1017
1018 mp_irqs[mp_irq_entries] = intsrc;
1019 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1020 panic("Max # of irq sources exceeded!\n");
1021 }
1022
1023 int es7000_plat;
1024
1025 void __init mp_config_acpi_legacy_irqs (void)
1026 {
1027 struct mpc_config_intsrc intsrc;
1028 int i = 0;
1029 int ioapic = -1;
1030
1031 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
1032 /*
1033 * Fabricate the legacy ISA bus (bus #31).
1034 */
1035 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
1036 #endif
1037 set_bit(MP_ISA_BUS, mp_bus_not_pci);
1038 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
1039
1040 /*
1041 * Older generations of ES7000 have no legacy identity mappings
1042 */
1043 if (es7000_plat == 1)
1044 return;
1045
1046 /*
1047 * Locate the IOAPIC that manages the ISA IRQs (0-15).
1048 */
1049 ioapic = mp_find_ioapic(0);
1050 if (ioapic < 0)
1051 return;
1052
1053 intsrc.mpc_type = MP_INTSRC;
1054 intsrc.mpc_irqflag = 0; /* Conforming */
1055 intsrc.mpc_srcbus = MP_ISA_BUS;
1056 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
1057
1058 /*
1059 * Use the default configuration for the IRQs 0-15. Unless
1060 * overridden by (MADT) interrupt source override entries.
1061 */
1062 for (i = 0; i < 16; i++) {
1063 int idx;
1064
1065 for (idx = 0; idx < mp_irq_entries; idx++) {
1066 struct mpc_config_intsrc *irq = mp_irqs + idx;
1067
1068 /* Do we already have a mapping for this ISA IRQ? */
1069 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
1070 break;
1071
1072 /* Do we already have a mapping for this IOAPIC pin */
1073 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
1074 (irq->mpc_dstirq == i))
1075 break;
1076 }
1077
1078 if (idx != mp_irq_entries) {
1079 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
1080 continue; /* IRQ already used */
1081 }
1082
1083 intsrc.mpc_irqtype = mp_INT;
1084 intsrc.mpc_srcbusirq = i; /* Identity mapped */
1085 intsrc.mpc_dstirq = i;
1086
1087 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
1088 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1089 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1090 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
1091 intsrc.mpc_dstirq);
1092
1093 mp_irqs[mp_irq_entries] = intsrc;
1094 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1095 panic("Max # of irq sources exceeded!\n");
1096 }
1097 }
1098
1099 #define MAX_GSI_NUM 4096
1100 #define IRQ_COMPRESSION_START 64
1101
1102 int mp_register_gsi(u32 gsi, int triggering, int polarity)
1103 {
1104 int ioapic = -1;
1105 int ioapic_pin = 0;
1106 int idx, bit = 0;
1107 static int pci_irq = IRQ_COMPRESSION_START;
1108 /*
1109 * Mapping between Global System Interrupts, which
1110 * represent all possible interrupts, and IRQs
1111 * assigned to actual devices.
1112 */
1113 static int gsi_to_irq[MAX_GSI_NUM];
1114
1115 /* Don't set up the ACPI SCI because it's already set up */
1116 if (acpi_gbl_FADT.sci_interrupt == gsi)
1117 return gsi;
1118
1119 ioapic = mp_find_ioapic(gsi);
1120 if (ioapic < 0) {
1121 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
1122 return gsi;
1123 }
1124
1125 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1126
1127 if (ioapic_renumber_irq)
1128 gsi = ioapic_renumber_irq(ioapic, gsi);
1129
1130 /*
1131 * Avoid pin reprogramming. PRTs typically include entries
1132 * with redundant pin->gsi mappings (but unique PCI devices);
1133 * we only program the IOAPIC on the first.
1134 */
1135 bit = ioapic_pin % 32;
1136 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
1137 if (idx > 3) {
1138 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1139 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
1140 ioapic_pin);
1141 return gsi;
1142 }
1143 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
1144 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1145 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
1146 return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]);
1147 }
1148
1149 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
1150
1151 /*
1152 * For GSI >= 64, use IRQ compression
1153 */
1154 if ((gsi >= IRQ_COMPRESSION_START)
1155 && (triggering == ACPI_LEVEL_SENSITIVE)) {
1156 /*
1157 * For PCI devices assign IRQs in order, avoiding gaps
1158 * due to unused I/O APIC pins.
1159 */
1160 int irq = gsi;
1161 if (gsi < MAX_GSI_NUM) {
1162 /*
1163 * Retain the VIA chipset work-around (gsi > 15), but
1164 * avoid a problem where the 8254 timer (IRQ0) is setup
1165 * via an override (so it's not on pin 0 of the ioapic),
1166 * and at the same time, the pin 0 interrupt is a PCI
1167 * type. The gsi > 15 test could cause these two pins
1168 * to be shared as IRQ0, and they are not shareable.
1169 * So test for this condition, and if necessary, avoid
1170 * the pin collision.
1171 */
1172 gsi = pci_irq++;
1173 /*
1174 * Don't assign IRQ used by ACPI SCI
1175 */
1176 if (gsi == acpi_gbl_FADT.sci_interrupt)
1177 gsi = pci_irq++;
1178 gsi_to_irq[irq] = gsi;
1179 } else {
1180 printk(KERN_ERR "GSI %u is too high\n", gsi);
1181 return gsi;
1182 }
1183 }
1184
1185 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
1186 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
1187 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1188 return gsi;
1189 }
1190
1191 #endif /* CONFIG_X86_IO_APIC */
1192 #endif /* CONFIG_ACPI */
AMDTP streaming driver for the Linux FireWire stack (Juju)