2 * arch/ppc/kernel/traps.c
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 * Modified by Cort Dougan (cort@cs.nmt.edu)
12 * and Paul Mackerras (paulus@cs.anu.edu.au)
16 * This file handles the architecture-dependent parts of hardware exceptions
19 #include <linux/errno.h>
20 #include <linux/sched.h>
21 #include <linux/kernel.h>
23 #include <linux/stddef.h>
24 #include <linux/unistd.h>
25 #include <linux/ptrace.h>
26 #include <linux/slab.h>
27 #include <linux/user.h>
28 #include <linux/a.out.h>
29 #include <linux/interrupt.h>
30 #include <linux/config.h>
31 #include <linux/init.h>
32 #include <linux/module.h>
33 #include <linux/prctl.h>
35 #include <asm/pgtable.h>
36 #include <asm/uaccess.h>
37 #include <asm/system.h>
41 #ifdef CONFIG_PMAC_BACKLIGHT
42 #include <asm/backlight.h>
44 #include <asm/perfmon.h>
47 void (*debugger
)(struct pt_regs
*regs
) = xmon
;
48 int (*debugger_bpt
)(struct pt_regs
*regs
) = xmon_bpt
;
49 int (*debugger_sstep
)(struct pt_regs
*regs
) = xmon_sstep
;
50 int (*debugger_iabr_match
)(struct pt_regs
*regs
) = xmon_iabr_match
;
51 int (*debugger_dabr_match
)(struct pt_regs
*regs
) = xmon_dabr_match
;
52 void (*debugger_fault_handler
)(struct pt_regs
*regs
);
55 void (*debugger
)(struct pt_regs
*regs
);
56 int (*debugger_bpt
)(struct pt_regs
*regs
);
57 int (*debugger_sstep
)(struct pt_regs
*regs
);
58 int (*debugger_iabr_match
)(struct pt_regs
*regs
);
59 int (*debugger_dabr_match
)(struct pt_regs
*regs
);
60 void (*debugger_fault_handler
)(struct pt_regs
*regs
);
62 #define debugger(regs) do { } while (0)
63 #define debugger_bpt(regs) 0
64 #define debugger_sstep(regs) 0
65 #define debugger_iabr_match(regs) 0
66 #define debugger_dabr_match(regs) 0
67 #define debugger_fault_handler ((void (*)(struct pt_regs *))0)
72 * Trap & Exception support
75 DEFINE_SPINLOCK(die_lock
);
77 void die(const char * str
, struct pt_regs
* fp
, long err
)
79 static int die_counter
;
82 spin_lock_irq(&die_lock
);
83 #ifdef CONFIG_PMAC_BACKLIGHT
84 if (_machine
== _MACH_Pmac
) {
85 set_backlight_enable(1);
86 set_backlight_level(BACKLIGHT_MAX
);
89 printk("Oops: %s, sig: %ld [#%d]\n", str
, err
, ++die_counter
);
95 printk("SMP NR_CPUS=%d ", NR_CPUS
);
101 spin_unlock_irq(&die_lock
);
102 /* do_exit() should take care of panic'ing from an interrupt
103 * context so we don't handle it here
108 void _exception(int signr
, struct pt_regs
*regs
, int code
, unsigned long addr
)
112 if (!user_mode(regs
)) {
114 die("Exception in kernel mode", regs
, signr
);
116 info
.si_signo
= signr
;
119 info
.si_addr
= (void __user
*) addr
;
120 force_sig_info(signr
, &info
, current
);
124 * I/O accesses can cause machine checks on powermacs.
125 * Check if the NIP corresponds to the address of a sync
126 * instruction for which there is an entry in the exception
128 * Note that the 601 only takes a machine check on TEA
129 * (transfer error ack) signal assertion, and does not
130 * set any of the top 16 bits of SRR1.
133 static inline int check_io_access(struct pt_regs
*regs
)
135 #ifdef CONFIG_PPC_PMAC
136 unsigned long msr
= regs
->msr
;
137 const struct exception_table_entry
*entry
;
138 unsigned int *nip
= (unsigned int *)regs
->nip
;
140 if (((msr
& 0xffff0000) == 0 || (msr
& (0x80000 | 0x40000)))
141 && (entry
= search_exception_tables(regs
->nip
)) != NULL
) {
143 * Check that it's a sync instruction, or somewhere
144 * in the twi; isync; nop sequence that inb/inw/inl uses.
145 * As the address is in the exception table
146 * we should be able to read the instr there.
147 * For the debug message, we look at the preceding
150 if (*nip
== 0x60000000) /* nop */
152 else if (*nip
== 0x4c00012c) /* isync */
154 if (*nip
== 0x7c0004ac || (*nip
>> 26) == 3) {
159 rb
= (*nip
>> 11) & 0x1f;
160 printk(KERN_DEBUG
"%s bad port %lx at %p\n",
161 (*nip
& 0x100)? "OUT to": "IN from",
162 regs
->gpr
[rb
] - _IO_BASE
, nip
);
164 regs
->nip
= entry
->fixup
;
168 #endif /* CONFIG_PPC_PMAC */
172 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
173 /* On 4xx, the reason for the machine check or program exception
175 #define get_reason(regs) ((regs)->dsisr)
176 #ifndef CONFIG_FSL_BOOKE
177 #define get_mc_reason(regs) ((regs)->dsisr)
179 #define get_mc_reason(regs) (mfspr(SPRN_MCSR))
181 #define REASON_FP ESR_FP
182 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
183 #define REASON_PRIVILEGED ESR_PPR
184 #define REASON_TRAP ESR_PTR
186 /* single-step stuff */
187 #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC)
188 #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
191 /* On non-4xx, the reason for the machine check or program
192 exception is in the MSR. */
193 #define get_reason(regs) ((regs)->msr)
194 #define get_mc_reason(regs) ((regs)->msr)
195 #define REASON_FP 0x100000
196 #define REASON_ILLEGAL 0x80000
197 #define REASON_PRIVILEGED 0x40000
198 #define REASON_TRAP 0x20000
200 #define single_stepping(regs) ((regs)->msr & MSR_SE)
201 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
205 * This is "fall-back" implementation for configurations
206 * which don't provide platform-specific machine check info
208 void __attribute__ ((weak
))
209 platform_machine_check(struct pt_regs
*regs
)
213 void MachineCheckException(struct pt_regs
*regs
)
215 unsigned long reason
= get_mc_reason(regs
);
217 if (user_mode(regs
)) {
219 _exception(SIGBUS
, regs
, BUS_ADRERR
, regs
->nip
);
223 #if defined(CONFIG_8xx) && defined(CONFIG_PCI)
224 /* the qspan pci read routines can cause machine checks -- Cort */
225 bad_page_fault(regs
, regs
->dar
, SIGBUS
);
229 if (debugger_fault_handler
) {
230 debugger_fault_handler(regs
);
235 if (check_io_access(regs
))
238 #if defined(CONFIG_4xx) && !defined(CONFIG_440A)
239 if (reason
& ESR_IMCP
) {
240 printk("Instruction");
241 mtspr(SPRN_ESR
, reason
& ~ESR_IMCP
);
244 printk(" machine check in kernel mode.\n");
245 #elif defined(CONFIG_440A)
246 printk("Machine check in kernel mode.\n");
247 if (reason
& ESR_IMCP
){
248 printk("Instruction Synchronous Machine Check exception\n");
249 mtspr(SPRN_ESR
, reason
& ~ESR_IMCP
);
252 u32 mcsr
= mfspr(SPRN_MCSR
);
254 printk("Instruction Read PLB Error\n");
256 printk("Data Read PLB Error\n");
258 printk("Data Write PLB Error\n");
259 if (mcsr
& MCSR_TLBP
)
260 printk("TLB Parity Error\n");
261 if (mcsr
& MCSR_ICP
){
262 flush_instruction_cache();
263 printk("I-Cache Parity Error\n");
265 if (mcsr
& MCSR_DCSP
)
266 printk("D-Cache Search Parity Error\n");
267 if (mcsr
& MCSR_DCFP
)
268 printk("D-Cache Flush Parity Error\n");
269 if (mcsr
& MCSR_IMPE
)
270 printk("Machine Check exception is imprecise\n");
273 mtspr(SPRN_MCSR
, mcsr
);
275 #elif defined (CONFIG_E500)
276 printk("Machine check in kernel mode.\n");
277 printk("Caused by (from MCSR=%lx): ", reason
);
279 if (reason
& MCSR_MCP
)
280 printk("Machine Check Signal\n");
281 if (reason
& MCSR_ICPERR
)
282 printk("Instruction Cache Parity Error\n");
283 if (reason
& MCSR_DCP_PERR
)
284 printk("Data Cache Push Parity Error\n");
285 if (reason
& MCSR_DCPERR
)
286 printk("Data Cache Parity Error\n");
287 if (reason
& MCSR_GL_CI
)
288 printk("Guarded Load or Cache-Inhibited stwcx.\n");
289 if (reason
& MCSR_BUS_IAERR
)
290 printk("Bus - Instruction Address Error\n");
291 if (reason
& MCSR_BUS_RAERR
)
292 printk("Bus - Read Address Error\n");
293 if (reason
& MCSR_BUS_WAERR
)
294 printk("Bus - Write Address Error\n");
295 if (reason
& MCSR_BUS_IBERR
)
296 printk("Bus - Instruction Data Error\n");
297 if (reason
& MCSR_BUS_RBERR
)
298 printk("Bus - Read Data Bus Error\n");
299 if (reason
& MCSR_BUS_WBERR
)
300 printk("Bus - Read Data Bus Error\n");
301 if (reason
& MCSR_BUS_IPERR
)
302 printk("Bus - Instruction Parity Error\n");
303 if (reason
& MCSR_BUS_RPERR
)
304 printk("Bus - Read Parity Error\n");
305 #elif defined (CONFIG_E200)
306 printk("Machine check in kernel mode.\n");
307 printk("Caused by (from MCSR=%lx): ", reason
);
309 if (reason
& MCSR_MCP
)
310 printk("Machine Check Signal\n");
311 if (reason
& MCSR_CP_PERR
)
312 printk("Cache Push Parity Error\n");
313 if (reason
& MCSR_CPERR
)
314 printk("Cache Parity Error\n");
315 if (reason
& MCSR_EXCP_ERR
)
316 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
317 if (reason
& MCSR_BUS_IRERR
)
318 printk("Bus - Read Bus Error on instruction fetch\n");
319 if (reason
& MCSR_BUS_DRERR
)
320 printk("Bus - Read Bus Error on data load\n");
321 if (reason
& MCSR_BUS_WRERR
)
322 printk("Bus - Write Bus Error on buffered store or cache line push\n");
323 #else /* !CONFIG_4xx && !CONFIG_E500 && !CONFIG_E200 */
324 printk("Machine check in kernel mode.\n");
325 printk("Caused by (from SRR1=%lx): ", reason
);
326 switch (reason
& 0x601F0000) {
328 printk("Machine check signal\n");
330 case 0: /* for 601 */
332 case 0x140000: /* 7450 MSS error and TEA */
333 printk("Transfer error ack signal\n");
336 printk("Data parity error signal\n");
339 printk("Address parity error signal\n");
342 printk("L1 Data Cache error\n");
345 printk("L1 Instruction Cache error\n");
348 printk("L2 data cache parity error\n");
351 printk("Unknown values in msr\n");
353 #endif /* CONFIG_4xx */
356 * Optional platform-provided routine to print out
357 * additional info, e.g. bus error registers.
359 platform_machine_check(regs
);
362 die("machine check", regs
, SIGBUS
);
365 void SMIException(struct pt_regs
*regs
)
368 #if !(defined(CONFIG_XMON) || defined(CONFIG_KGDB))
370 panic("System Management Interrupt");
374 void UnknownException(struct pt_regs
*regs
)
376 printk("Bad trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
377 regs
->nip
, regs
->msr
, regs
->trap
, print_tainted());
378 _exception(SIGTRAP
, regs
, 0, 0);
381 void InstructionBreakpoint(struct pt_regs
*regs
)
383 if (debugger_iabr_match(regs
))
385 _exception(SIGTRAP
, regs
, TRAP_BRKPT
, 0);
388 void RunModeException(struct pt_regs
*regs
)
390 _exception(SIGTRAP
, regs
, 0, 0);
393 /* Illegal instruction emulation support. Originally written to
394 * provide the PVR to user applications using the mfspr rd, PVR.
395 * Return non-zero if we can't emulate, or -EFAULT if the associated
396 * memory access caused an access fault. Return zero on success.
398 * There are a couple of ways to do this, either "decode" the instruction
399 * or directly match lots of bits. In this case, matching lots of
400 * bits is faster and easier.
403 #define INST_MFSPR_PVR 0x7c1f42a6
404 #define INST_MFSPR_PVR_MASK 0xfc1fffff
406 #define INST_DCBA 0x7c0005ec
407 #define INST_DCBA_MASK 0x7c0007fe
409 #define INST_MCRXR 0x7c000400
410 #define INST_MCRXR_MASK 0x7c0007fe
412 #define INST_STRING 0x7c00042a
413 #define INST_STRING_MASK 0x7c0007fe
414 #define INST_STRING_GEN_MASK 0x7c00067e
415 #define INST_LSWI 0x7c0004aa
416 #define INST_LSWX 0x7c00042a
417 #define INST_STSWI 0x7c0005aa
418 #define INST_STSWX 0x7c00052a
420 static int emulate_string_inst(struct pt_regs
*regs
, u32 instword
)
422 u8 rT
= (instword
>> 21) & 0x1f;
423 u8 rA
= (instword
>> 16) & 0x1f;
424 u8 NB_RB
= (instword
>> 11) & 0x1f;
429 /* Early out if we are an invalid form of lswx */
430 if ((instword
& INST_STRING_MASK
) == INST_LSWX
)
431 if ((rT
== rA
) || (rT
== NB_RB
))
434 EA
= (rA
== 0) ? 0 : regs
->gpr
[rA
];
436 switch (instword
& INST_STRING_MASK
) {
440 num_bytes
= regs
->xer
& 0x7f;
444 num_bytes
= (NB_RB
== 0) ? 32 : NB_RB
;
450 while (num_bytes
!= 0)
453 u32 shift
= 8 * (3 - (pos
& 0x3));
455 switch ((instword
& INST_STRING_MASK
)) {
458 if (get_user(val
, (u8 __user
*)EA
))
460 /* first time updating this reg,
464 regs
->gpr
[rT
] |= val
<< shift
;
468 val
= regs
->gpr
[rT
] >> shift
;
469 if (put_user(val
, (u8 __user
*)EA
))
473 /* move EA to next address */
477 /* manage our position within the register */
488 static int emulate_instruction(struct pt_regs
*regs
)
493 if (!user_mode(regs
))
495 CHECK_FULL_REGS(regs
);
497 if (get_user(instword
, (u32 __user
*)(regs
->nip
)))
500 /* Emulate the mfspr rD, PVR.
502 if ((instword
& INST_MFSPR_PVR_MASK
) == INST_MFSPR_PVR
) {
503 rd
= (instword
>> 21) & 0x1f;
504 regs
->gpr
[rd
] = mfspr(SPRN_PVR
);
508 /* Emulating the dcba insn is just a no-op. */
509 if ((instword
& INST_DCBA_MASK
) == INST_DCBA
)
512 /* Emulate the mcrxr insn. */
513 if ((instword
& INST_MCRXR_MASK
) == INST_MCRXR
) {
514 int shift
= (instword
>> 21) & 0x1c;
515 unsigned long msk
= 0xf0000000UL
>> shift
;
517 regs
->ccr
= (regs
->ccr
& ~msk
) | ((regs
->xer
>> shift
) & msk
);
518 regs
->xer
&= ~0xf0000000UL
;
522 /* Emulate load/store string insn. */
523 if ((instword
& INST_STRING_GEN_MASK
) == INST_STRING
)
524 return emulate_string_inst(regs
, instword
);
530 * After we have successfully emulated an instruction, we have to
531 * check if the instruction was being single-stepped, and if so,
532 * pretend we got a single-step exception. This was pointed out
533 * by Kumar Gala. -- paulus
535 static void emulate_single_step(struct pt_regs
*regs
)
537 if (single_stepping(regs
)) {
538 clear_single_step(regs
);
539 _exception(SIGTRAP
, regs
, TRAP_TRACE
, 0);
544 * Look through the list of trap instructions that are used for BUG(),
545 * BUG_ON() and WARN_ON() and see if we hit one. At this point we know
546 * that the exception was caused by a trap instruction of some kind.
547 * Returns 1 if we should continue (i.e. it was a WARN_ON) or 0
550 extern struct bug_entry __start___bug_table
[], __stop___bug_table
[];
552 #ifndef CONFIG_MODULES
553 #define module_find_bug(x) NULL
556 static struct bug_entry
*find_bug(unsigned long bugaddr
)
558 struct bug_entry
*bug
;
560 for (bug
= __start___bug_table
; bug
< __stop___bug_table
; ++bug
)
561 if (bugaddr
== bug
->bug_addr
)
563 return module_find_bug(bugaddr
);
566 int check_bug_trap(struct pt_regs
*regs
)
568 struct bug_entry
*bug
;
571 if (regs
->msr
& MSR_PR
)
572 return 0; /* not in kernel */
573 addr
= regs
->nip
; /* address of trap instruction */
574 if (addr
< PAGE_OFFSET
)
576 bug
= find_bug(regs
->nip
);
579 if (bug
->line
& BUG_WARNING_TRAP
) {
580 /* this is a WARN_ON rather than BUG/BUG_ON */
582 xmon_printf(KERN_ERR
"Badness in %s at %s:%d\n",
583 bug
->function
, bug
->file
,
584 bug
->line
& ~BUG_WARNING_TRAP
);
585 #endif /* CONFIG_XMON */
586 printk(KERN_ERR
"Badness in %s at %s:%d\n",
587 bug
->function
, bug
->file
,
588 bug
->line
& ~BUG_WARNING_TRAP
);
593 xmon_printf(KERN_CRIT
"kernel BUG in %s at %s:%d!\n",
594 bug
->function
, bug
->file
, bug
->line
);
596 #endif /* CONFIG_XMON */
597 printk(KERN_CRIT
"kernel BUG in %s at %s:%d!\n",
598 bug
->function
, bug
->file
, bug
->line
);
603 void ProgramCheckException(struct pt_regs
*regs
)
605 unsigned int reason
= get_reason(regs
);
606 extern int do_mathemu(struct pt_regs
*regs
);
608 #ifdef CONFIG_MATH_EMULATION
609 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
610 * but there seems to be a hardware bug on the 405GP (RevD)
611 * that means ESR is sometimes set incorrectly - either to
612 * ESR_DST (!?) or 0. In the process of chasing this with the
613 * hardware people - not sure if it can happen on any illegal
614 * instruction or only on FP instructions, whether there is a
615 * pattern to occurences etc. -dgibson 31/Mar/2003 */
616 if (!(reason
& REASON_TRAP
) && do_mathemu(regs
) == 0) {
617 emulate_single_step(regs
);
620 #endif /* CONFIG_MATH_EMULATION */
622 if (reason
& REASON_FP
) {
623 /* IEEE FP exception */
627 /* We must make sure the FP state is consistent with
631 if (regs
->msr
& MSR_FP
)
635 fpscr
= current
->thread
.fpscr
;
636 fpscr
&= fpscr
<< 22; /* mask summary bits with enables */
637 if (fpscr
& FPSCR_VX
)
639 else if (fpscr
& FPSCR_OX
)
641 else if (fpscr
& FPSCR_UX
)
643 else if (fpscr
& FPSCR_ZX
)
645 else if (fpscr
& FPSCR_XX
)
647 _exception(SIGFPE
, regs
, code
, regs
->nip
);
651 if (reason
& REASON_TRAP
) {
653 if (debugger_bpt(regs
))
655 if (check_bug_trap(regs
)) {
659 _exception(SIGTRAP
, regs
, TRAP_BRKPT
, 0);
663 /* Try to emulate it if we should. */
664 if (reason
& (REASON_ILLEGAL
| REASON_PRIVILEGED
)) {
665 switch (emulate_instruction(regs
)) {
668 emulate_single_step(regs
);
671 _exception(SIGSEGV
, regs
, SEGV_MAPERR
, regs
->nip
);
676 if (reason
& REASON_PRIVILEGED
)
677 _exception(SIGILL
, regs
, ILL_PRVOPC
, regs
->nip
);
679 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
682 void SingleStepException(struct pt_regs
*regs
)
684 regs
->msr
&= ~(MSR_SE
| MSR_BE
); /* Turn off 'trace' bits */
685 if (debugger_sstep(regs
))
687 _exception(SIGTRAP
, regs
, TRAP_TRACE
, 0);
690 void AlignmentException(struct pt_regs
*regs
)
694 fixed
= fix_alignment(regs
);
696 regs
->nip
+= 4; /* skip over emulated instruction */
697 emulate_single_step(regs
);
700 if (fixed
== -EFAULT
) {
701 /* fixed == -EFAULT means the operand address was bad */
703 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->dar
);
705 bad_page_fault(regs
, regs
->dar
, SIGSEGV
);
708 _exception(SIGBUS
, regs
, BUS_ADRALN
, regs
->dar
);
711 void StackOverflow(struct pt_regs
*regs
)
713 printk(KERN_CRIT
"Kernel stack overflow in process %p, r1=%lx\n",
714 current
, regs
->gpr
[1]);
717 panic("kernel stack overflow");
720 void nonrecoverable_exception(struct pt_regs
*regs
)
722 printk(KERN_ERR
"Non-recoverable exception at PC=%lx MSR=%lx\n",
723 regs
->nip
, regs
->msr
);
725 die("nonrecoverable exception", regs
, SIGKILL
);
728 void trace_syscall(struct pt_regs
*regs
)
730 printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n",
731 current
, current
->pid
, regs
->nip
, regs
->link
, regs
->gpr
[0],
732 regs
->ccr
&0x10000000?"Error=":"", regs
->gpr
[3], print_tainted());
736 void SoftwareEmulation(struct pt_regs
*regs
)
738 extern int do_mathemu(struct pt_regs
*);
739 extern int Soft_emulate_8xx(struct pt_regs
*);
742 CHECK_FULL_REGS(regs
);
744 if (!user_mode(regs
)) {
746 die("Kernel Mode Software FPU Emulation", regs
, SIGFPE
);
749 #ifdef CONFIG_MATH_EMULATION
750 errcode
= do_mathemu(regs
);
752 errcode
= Soft_emulate_8xx(regs
);
756 _exception(SIGFPE
, regs
, 0, 0);
757 else if (errcode
== -EFAULT
)
758 _exception(SIGSEGV
, regs
, 0, 0);
760 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
762 emulate_single_step(regs
);
764 #endif /* CONFIG_8xx */
766 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
768 void DebugException(struct pt_regs
*regs
, unsigned long debug_status
)
770 if (debug_status
& DBSR_IC
) { /* instruction completion */
771 regs
->msr
&= ~MSR_DE
;
772 if (user_mode(regs
)) {
773 current
->thread
.dbcr0
&= ~DBCR0_IC
;
775 /* Disable instruction completion */
776 mtspr(SPRN_DBCR0
, mfspr(SPRN_DBCR0
) & ~DBCR0_IC
);
777 /* Clear the instruction completion event */
778 mtspr(SPRN_DBSR
, DBSR_IC
);
779 if (debugger_sstep(regs
))
782 _exception(SIGTRAP
, regs
, TRAP_TRACE
, 0);
785 #endif /* CONFIG_4xx || CONFIG_BOOKE */
787 #if !defined(CONFIG_TAU_INT)
788 void TAUException(struct pt_regs
*regs
)
790 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
791 regs
->nip
, regs
->msr
, regs
->trap
, print_tainted());
793 #endif /* CONFIG_INT_TAU */
795 void AltivecUnavailException(struct pt_regs
*regs
)
797 static int kernel_altivec_count
;
799 #ifndef CONFIG_ALTIVEC
800 if (user_mode(regs
)) {
801 /* A user program has executed an altivec instruction,
802 but this kernel doesn't support altivec. */
803 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
807 /* The kernel has executed an altivec instruction without
808 first enabling altivec. Whinge but let it do it. */
809 if (++kernel_altivec_count
< 10)
810 printk(KERN_ERR
"AltiVec used in kernel (task=%p, pc=%lx)\n",
812 regs
->msr
|= MSR_VEC
;
815 #ifdef CONFIG_ALTIVEC
816 void AltivecAssistException(struct pt_regs
*regs
)
821 if (regs
->msr
& MSR_VEC
)
822 giveup_altivec(current
);
824 if (!user_mode(regs
)) {
825 printk(KERN_ERR
"altivec assist exception in kernel mode"
826 " at %lx\n", regs
->nip
);
828 die("altivec assist exception", regs
, SIGFPE
);
832 err
= emulate_altivec(regs
);
834 regs
->nip
+= 4; /* skip emulated instruction */
835 emulate_single_step(regs
);
839 if (err
== -EFAULT
) {
840 /* got an error reading the instruction */
841 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
843 /* didn't recognize the instruction */
844 /* XXX quick hack for now: set the non-Java bit in the VSCR */
845 printk(KERN_ERR
"unrecognized altivec instruction "
846 "in %s at %lx\n", current
->comm
, regs
->nip
);
847 current
->thread
.vscr
.u
[3] |= 0x10000;
850 #endif /* CONFIG_ALTIVEC */
852 void PerformanceMonitorException(struct pt_regs
*regs
)
857 #ifdef CONFIG_FSL_BOOKE
858 void CacheLockingException(struct pt_regs
*regs
, unsigned long address
,
859 unsigned long error_code
)
861 /* We treat cache locking instructions from the user
862 * as priv ops, in the future we could try to do
865 if (error_code
& (ESR_DLK
|ESR_ILK
))
866 _exception(SIGILL
, regs
, ILL_PRVOPC
, regs
->nip
);
869 #endif /* CONFIG_FSL_BOOKE */
872 void SPEFloatingPointException(struct pt_regs
*regs
)
874 unsigned long spefscr
;
878 spefscr
= current
->thread
.spefscr
;
879 fpexc_mode
= current
->thread
.fpexc_mode
;
881 /* Hardware does not neccessarily set sticky
882 * underflow/overflow/invalid flags */
883 if ((spefscr
& SPEFSCR_FOVF
) && (fpexc_mode
& PR_FP_EXC_OVF
)) {
885 spefscr
|= SPEFSCR_FOVFS
;
887 else if ((spefscr
& SPEFSCR_FUNF
) && (fpexc_mode
& PR_FP_EXC_UND
)) {
889 spefscr
|= SPEFSCR_FUNFS
;
891 else if ((spefscr
& SPEFSCR_FDBZ
) && (fpexc_mode
& PR_FP_EXC_DIV
))
893 else if ((spefscr
& SPEFSCR_FINV
) && (fpexc_mode
& PR_FP_EXC_INV
)) {
895 spefscr
|= SPEFSCR_FINVS
;
897 else if ((spefscr
& (SPEFSCR_FG
| SPEFSCR_FX
)) && (fpexc_mode
& PR_FP_EXC_RES
))
900 current
->thread
.spefscr
= spefscr
;
902 _exception(SIGFPE
, regs
, code
, regs
->nip
);
907 void __init
trap_init(void)