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tg3 / broadcom: Add code to disable rxc refclk
[firewire-audio.git] / drivers / net / tg3.c
blob369ddba95821e82e2dbd4527392956e15fb7e3ee
1 /*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2009 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
16 */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
38 #include <linux/ip.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
44
45 #include <net/checksum.h>
46 #include <net/ip.h>
47
48 #include <asm/system.h>
49 #include <asm/io.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
52
53 #ifdef CONFIG_SPARC
54 #include <asm/idprom.h>
55 #include <asm/prom.h>
56 #endif
57
58 #define BAR_0 0
59 #define BAR_2 2
60
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
63 #else
64 #define TG3_VLAN_TAG_USED 0
65 #endif
66
67 #include "tg3.h"
68
69 #define DRV_MODULE_NAME "tg3"
70 #define PFX DRV_MODULE_NAME ": "
71 #define DRV_MODULE_VERSION "3.102"
72 #define DRV_MODULE_RELDATE "September 1, 2009"
73
74 #define TG3_DEF_MAC_MODE 0
75 #define TG3_DEF_RX_MODE 0
76 #define TG3_DEF_TX_MODE 0
77 #define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87 /* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90 #define TG3_TX_TIMEOUT (5 * HZ)
91
92 /* hardware minimum and maximum for a single frame's data payload */
93 #define TG3_MIN_MTU 60
94 #define TG3_MAX_MTU(tp) \
95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
96
97 /* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101 #define TG3_RX_RING_SIZE 512
102 #define TG3_DEF_RX_RING_PENDING 200
103 #define TG3_RX_JUMBO_RING_SIZE 256
104 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
105 #define TG3_RSS_INDIR_TBL_SIZE 128
106
107 /* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
112 */
113 #define TG3_RX_RCB_RING_SIZE(tp) \
114 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
115 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
116
117 #define TG3_TX_RING_SIZE 512
118 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119
120 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_RING_SIZE)
122 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
123 TG3_RX_JUMBO_RING_SIZE)
124 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
125 TG3_RX_RCB_RING_SIZE(tp))
126 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 TG3_TX_RING_SIZE)
128 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129
130 #define TG3_DMA_BYTE_ENAB 64
131
132 #define TG3_RX_STD_DMA_SZ 1536
133 #define TG3_RX_JMB_DMA_SZ 9046
134
135 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
136
137 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
138 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
139
140 /* minimum number of free TX descriptors required to wake up TX process */
141 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
142
143 #define TG3_RAW_IP_ALIGN 2
144
145 /* number of ETHTOOL_GSTATS u64's */
146 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
147
148 #define TG3_NUM_TEST 6
149
150 #define FIRMWARE_TG3 "tigon/tg3.bin"
151 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
152 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
153
154 static char version[] __devinitdata =
155 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
156
157 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
158 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
159 MODULE_LICENSE("GPL");
160 MODULE_VERSION(DRV_MODULE_VERSION);
161 MODULE_FIRMWARE(FIRMWARE_TG3);
162 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
163 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
164
165 #define TG3_RSS_MIN_NUM_MSIX_VECS 2
166
167 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
168 module_param(tg3_debug, int, 0);
169 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
170
171 static struct pci_device_id tg3_pci_tbl[] = {
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
238 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
239 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
240 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
241 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
242 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
243 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
244 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
245 {}
246 };
247
248 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
249
250 static const struct {
251 const char string[ETH_GSTRING_LEN];
252 } ethtool_stats_keys[TG3_NUM_STATS] = {
253 { "rx_octets" },
254 { "rx_fragments" },
255 { "rx_ucast_packets" },
256 { "rx_mcast_packets" },
257 { "rx_bcast_packets" },
258 { "rx_fcs_errors" },
259 { "rx_align_errors" },
260 { "rx_xon_pause_rcvd" },
261 { "rx_xoff_pause_rcvd" },
262 { "rx_mac_ctrl_rcvd" },
263 { "rx_xoff_entered" },
264 { "rx_frame_too_long_errors" },
265 { "rx_jabbers" },
266 { "rx_undersize_packets" },
267 { "rx_in_length_errors" },
268 { "rx_out_length_errors" },
269 { "rx_64_or_less_octet_packets" },
270 { "rx_65_to_127_octet_packets" },
271 { "rx_128_to_255_octet_packets" },
272 { "rx_256_to_511_octet_packets" },
273 { "rx_512_to_1023_octet_packets" },
274 { "rx_1024_to_1522_octet_packets" },
275 { "rx_1523_to_2047_octet_packets" },
276 { "rx_2048_to_4095_octet_packets" },
277 { "rx_4096_to_8191_octet_packets" },
278 { "rx_8192_to_9022_octet_packets" },
279
280 { "tx_octets" },
281 { "tx_collisions" },
282
283 { "tx_xon_sent" },
284 { "tx_xoff_sent" },
285 { "tx_flow_control" },
286 { "tx_mac_errors" },
287 { "tx_single_collisions" },
288 { "tx_mult_collisions" },
289 { "tx_deferred" },
290 { "tx_excessive_collisions" },
291 { "tx_late_collisions" },
292 { "tx_collide_2times" },
293 { "tx_collide_3times" },
294 { "tx_collide_4times" },
295 { "tx_collide_5times" },
296 { "tx_collide_6times" },
297 { "tx_collide_7times" },
298 { "tx_collide_8times" },
299 { "tx_collide_9times" },
300 { "tx_collide_10times" },
301 { "tx_collide_11times" },
302 { "tx_collide_12times" },
303 { "tx_collide_13times" },
304 { "tx_collide_14times" },
305 { "tx_collide_15times" },
306 { "tx_ucast_packets" },
307 { "tx_mcast_packets" },
308 { "tx_bcast_packets" },
309 { "tx_carrier_sense_errors" },
310 { "tx_discards" },
311 { "tx_errors" },
312
313 { "dma_writeq_full" },
314 { "dma_write_prioq_full" },
315 { "rxbds_empty" },
316 { "rx_discards" },
317 { "rx_errors" },
318 { "rx_threshold_hit" },
319
320 { "dma_readq_full" },
321 { "dma_read_prioq_full" },
322 { "tx_comp_queue_full" },
323
324 { "ring_set_send_prod_index" },
325 { "ring_status_update" },
326 { "nic_irqs" },
327 { "nic_avoided_irqs" },
328 { "nic_tx_threshold_hit" }
329 };
330
331 static const struct {
332 const char string[ETH_GSTRING_LEN];
333 } ethtool_test_keys[TG3_NUM_TEST] = {
334 { "nvram test (online) " },
335 { "link test (online) " },
336 { "register test (offline)" },
337 { "memory test (offline)" },
338 { "loopback test (offline)" },
339 { "interrupt test (offline)" },
340 };
341
342 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
343 {
344 writel(val, tp->regs + off);
345 }
346
347 static u32 tg3_read32(struct tg3 *tp, u32 off)
348 {
349 return (readl(tp->regs + off));
350 }
351
352 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
353 {
354 writel(val, tp->aperegs + off);
355 }
356
357 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
358 {
359 return (readl(tp->aperegs + off));
360 }
361
362 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
363 {
364 unsigned long flags;
365
366 spin_lock_irqsave(&tp->indirect_lock, flags);
367 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
368 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
369 spin_unlock_irqrestore(&tp->indirect_lock, flags);
370 }
371
372 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
373 {
374 writel(val, tp->regs + off);
375 readl(tp->regs + off);
376 }
377
378 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
379 {
380 unsigned long flags;
381 u32 val;
382
383 spin_lock_irqsave(&tp->indirect_lock, flags);
384 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
385 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
386 spin_unlock_irqrestore(&tp->indirect_lock, flags);
387 return val;
388 }
389
390 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
391 {
392 unsigned long flags;
393
394 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
395 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
396 TG3_64BIT_REG_LOW, val);
397 return;
398 }
399 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
400 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
401 TG3_64BIT_REG_LOW, val);
402 return;
403 }
404
405 spin_lock_irqsave(&tp->indirect_lock, flags);
406 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
407 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
408 spin_unlock_irqrestore(&tp->indirect_lock, flags);
409
410 /* In indirect mode when disabling interrupts, we also need
411 * to clear the interrupt bit in the GRC local ctrl register.
412 */
413 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
414 (val == 0x1)) {
415 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
416 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
417 }
418 }
419
420 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
421 {
422 unsigned long flags;
423 u32 val;
424
425 spin_lock_irqsave(&tp->indirect_lock, flags);
426 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
427 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
428 spin_unlock_irqrestore(&tp->indirect_lock, flags);
429 return val;
430 }
431
432 /* usec_wait specifies the wait time in usec when writing to certain registers
433 * where it is unsafe to read back the register without some delay.
434 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
435 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
436 */
437 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
438 {
439 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
440 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
441 /* Non-posted methods */
442 tp->write32(tp, off, val);
443 else {
444 /* Posted method */
445 tg3_write32(tp, off, val);
446 if (usec_wait)
447 udelay(usec_wait);
448 tp->read32(tp, off);
449 }
450 /* Wait again after the read for the posted method to guarantee that
451 * the wait time is met.
452 */
453 if (usec_wait)
454 udelay(usec_wait);
455 }
456
457 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
458 {
459 tp->write32_mbox(tp, off, val);
460 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
461 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
462 tp->read32_mbox(tp, off);
463 }
464
465 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
466 {
467 void __iomem *mbox = tp->regs + off;
468 writel(val, mbox);
469 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
470 writel(val, mbox);
471 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
472 readl(mbox);
473 }
474
475 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
476 {
477 return (readl(tp->regs + off + GRCMBOX_BASE));
478 }
479
480 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
481 {
482 writel(val, tp->regs + off + GRCMBOX_BASE);
483 }
484
485 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
486 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
487 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
488 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
489 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
490
491 #define tw32(reg,val) tp->write32(tp, reg, val)
492 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
493 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
494 #define tr32(reg) tp->read32(tp, reg)
495
496 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
497 {
498 unsigned long flags;
499
500 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
501 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
502 return;
503
504 spin_lock_irqsave(&tp->indirect_lock, flags);
505 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
506 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
507 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
508
509 /* Always leave this as zero. */
510 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
511 } else {
512 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
513 tw32_f(TG3PCI_MEM_WIN_DATA, val);
514
515 /* Always leave this as zero. */
516 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
517 }
518 spin_unlock_irqrestore(&tp->indirect_lock, flags);
519 }
520
521 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
522 {
523 unsigned long flags;
524
525 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
526 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
527 *val = 0;
528 return;
529 }
530
531 spin_lock_irqsave(&tp->indirect_lock, flags);
532 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
533 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
534 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
535
536 /* Always leave this as zero. */
537 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
538 } else {
539 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
540 *val = tr32(TG3PCI_MEM_WIN_DATA);
541
542 /* Always leave this as zero. */
543 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
544 }
545 spin_unlock_irqrestore(&tp->indirect_lock, flags);
546 }
547
548 static void tg3_ape_lock_init(struct tg3 *tp)
549 {
550 int i;
551
552 /* Make sure the driver hasn't any stale locks. */
553 for (i = 0; i < 8; i++)
554 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
555 APE_LOCK_GRANT_DRIVER);
556 }
557
558 static int tg3_ape_lock(struct tg3 *tp, int locknum)
559 {
560 int i, off;
561 int ret = 0;
562 u32 status;
563
564 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
565 return 0;
566
567 switch (locknum) {
568 case TG3_APE_LOCK_GRC:
569 case TG3_APE_LOCK_MEM:
570 break;
571 default:
572 return -EINVAL;
573 }
574
575 off = 4 * locknum;
576
577 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
578
579 /* Wait for up to 1 millisecond to acquire lock. */
580 for (i = 0; i < 100; i++) {
581 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
582 if (status == APE_LOCK_GRANT_DRIVER)
583 break;
584 udelay(10);
585 }
586
587 if (status != APE_LOCK_GRANT_DRIVER) {
588 /* Revoke the lock request. */
589 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
590 APE_LOCK_GRANT_DRIVER);
591
592 ret = -EBUSY;
593 }
594
595 return ret;
596 }
597
598 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
599 {
600 int off;
601
602 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
603 return;
604
605 switch (locknum) {
606 case TG3_APE_LOCK_GRC:
607 case TG3_APE_LOCK_MEM:
608 break;
609 default:
610 return;
611 }
612
613 off = 4 * locknum;
614 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
615 }
616
617 static void tg3_disable_ints(struct tg3 *tp)
618 {
619 int i;
620
621 tw32(TG3PCI_MISC_HOST_CTRL,
622 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
623 for (i = 0; i < tp->irq_max; i++)
624 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
625 }
626
627 static void tg3_enable_ints(struct tg3 *tp)
628 {
629 int i;
630 u32 coal_now = 0;
631
632 tp->irq_sync = 0;
633 wmb();
634
635 tw32(TG3PCI_MISC_HOST_CTRL,
636 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
637
638 for (i = 0; i < tp->irq_cnt; i++) {
639 struct tg3_napi *tnapi = &tp->napi[i];
640 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
641 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
642 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
643
644 coal_now |= tnapi->coal_now;
645 }
646
647 /* Force an initial interrupt */
648 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
649 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
650 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
651 else
652 tw32(HOSTCC_MODE, tp->coalesce_mode |
653 HOSTCC_MODE_ENABLE | coal_now);
654 }
655
656 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
657 {
658 struct tg3 *tp = tnapi->tp;
659 struct tg3_hw_status *sblk = tnapi->hw_status;
660 unsigned int work_exists = 0;
661
662 /* check for phy events */
663 if (!(tp->tg3_flags &
664 (TG3_FLAG_USE_LINKCHG_REG |
665 TG3_FLAG_POLL_SERDES))) {
666 if (sblk->status & SD_STATUS_LINK_CHG)
667 work_exists = 1;
668 }
669 /* check for RX/TX work to do */
670 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
671 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
672 work_exists = 1;
673
674 return work_exists;
675 }
676
677 /* tg3_int_reenable
678 * similar to tg3_enable_ints, but it accurately determines whether there
679 * is new work pending and can return without flushing the PIO write
680 * which reenables interrupts
681 */
682 static void tg3_int_reenable(struct tg3_napi *tnapi)
683 {
684 struct tg3 *tp = tnapi->tp;
685
686 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
687 mmiowb();
688
689 /* When doing tagged status, this work check is unnecessary.
690 * The last_tag we write above tells the chip which piece of
691 * work we've completed.
692 */
693 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
694 tg3_has_work(tnapi))
695 tw32(HOSTCC_MODE, tp->coalesce_mode |
696 HOSTCC_MODE_ENABLE | tnapi->coal_now);
697 }
698
699 static void tg3_napi_disable(struct tg3 *tp)
700 {
701 int i;
702
703 for (i = tp->irq_cnt - 1; i >= 0; i--)
704 napi_disable(&tp->napi[i].napi);
705 }
706
707 static void tg3_napi_enable(struct tg3 *tp)
708 {
709 int i;
710
711 for (i = 0; i < tp->irq_cnt; i++)
712 napi_enable(&tp->napi[i].napi);
713 }
714
715 static inline void tg3_netif_stop(struct tg3 *tp)
716 {
717 tp->dev->trans_start = jiffies; /* prevent tx timeout */
718 tg3_napi_disable(tp);
719 netif_tx_disable(tp->dev);
720 }
721
722 static inline void tg3_netif_start(struct tg3 *tp)
723 {
724 /* NOTE: unconditional netif_tx_wake_all_queues is only
725 * appropriate so long as all callers are assured to
726 * have free tx slots (such as after tg3_init_hw)
727 */
728 netif_tx_wake_all_queues(tp->dev);
729
730 tg3_napi_enable(tp);
731 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
732 tg3_enable_ints(tp);
733 }
734
735 static void tg3_switch_clocks(struct tg3 *tp)
736 {
737 u32 clock_ctrl;
738 u32 orig_clock_ctrl;
739
740 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
741 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
742 return;
743
744 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
745
746 orig_clock_ctrl = clock_ctrl;
747 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
748 CLOCK_CTRL_CLKRUN_OENABLE |
749 0x1f);
750 tp->pci_clock_ctrl = clock_ctrl;
751
752 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
753 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
754 tw32_wait_f(TG3PCI_CLOCK_CTRL,
755 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
756 }
757 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
758 tw32_wait_f(TG3PCI_CLOCK_CTRL,
759 clock_ctrl |
760 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
761 40);
762 tw32_wait_f(TG3PCI_CLOCK_CTRL,
763 clock_ctrl | (CLOCK_CTRL_ALTCLK),
764 40);
765 }
766 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
767 }
768
769 #define PHY_BUSY_LOOPS 5000
770
771 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
772 {
773 u32 frame_val;
774 unsigned int loops;
775 int ret;
776
777 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
778 tw32_f(MAC_MI_MODE,
779 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
780 udelay(80);
781 }
782
783 *val = 0x0;
784
785 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
786 MI_COM_PHY_ADDR_MASK);
787 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
788 MI_COM_REG_ADDR_MASK);
789 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
790
791 tw32_f(MAC_MI_COM, frame_val);
792
793 loops = PHY_BUSY_LOOPS;
794 while (loops != 0) {
795 udelay(10);
796 frame_val = tr32(MAC_MI_COM);
797
798 if ((frame_val & MI_COM_BUSY) == 0) {
799 udelay(5);
800 frame_val = tr32(MAC_MI_COM);
801 break;
802 }
803 loops -= 1;
804 }
805
806 ret = -EBUSY;
807 if (loops != 0) {
808 *val = frame_val & MI_COM_DATA_MASK;
809 ret = 0;
810 }
811
812 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
813 tw32_f(MAC_MI_MODE, tp->mi_mode);
814 udelay(80);
815 }
816
817 return ret;
818 }
819
820 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
821 {
822 u32 frame_val;
823 unsigned int loops;
824 int ret;
825
826 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
827 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
828 return 0;
829
830 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
831 tw32_f(MAC_MI_MODE,
832 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
833 udelay(80);
834 }
835
836 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
837 MI_COM_PHY_ADDR_MASK);
838 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
839 MI_COM_REG_ADDR_MASK);
840 frame_val |= (val & MI_COM_DATA_MASK);
841 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
842
843 tw32_f(MAC_MI_COM, frame_val);
844
845 loops = PHY_BUSY_LOOPS;
846 while (loops != 0) {
847 udelay(10);
848 frame_val = tr32(MAC_MI_COM);
849 if ((frame_val & MI_COM_BUSY) == 0) {
850 udelay(5);
851 frame_val = tr32(MAC_MI_COM);
852 break;
853 }
854 loops -= 1;
855 }
856
857 ret = -EBUSY;
858 if (loops != 0)
859 ret = 0;
860
861 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
862 tw32_f(MAC_MI_MODE, tp->mi_mode);
863 udelay(80);
864 }
865
866 return ret;
867 }
868
869 static int tg3_bmcr_reset(struct tg3 *tp)
870 {
871 u32 phy_control;
872 int limit, err;
873
874 /* OK, reset it, and poll the BMCR_RESET bit until it
875 * clears or we time out.
876 */
877 phy_control = BMCR_RESET;
878 err = tg3_writephy(tp, MII_BMCR, phy_control);
879 if (err != 0)
880 return -EBUSY;
881
882 limit = 5000;
883 while (limit--) {
884 err = tg3_readphy(tp, MII_BMCR, &phy_control);
885 if (err != 0)
886 return -EBUSY;
887
888 if ((phy_control & BMCR_RESET) == 0) {
889 udelay(40);
890 break;
891 }
892 udelay(10);
893 }
894 if (limit < 0)
895 return -EBUSY;
896
897 return 0;
898 }
899
900 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
901 {
902 struct tg3 *tp = bp->priv;
903 u32 val;
904
905 spin_lock_bh(&tp->lock);
906
907 if (tg3_readphy(tp, reg, &val))
908 val = -EIO;
909
910 spin_unlock_bh(&tp->lock);
911
912 return val;
913 }
914
915 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
916 {
917 struct tg3 *tp = bp->priv;
918 u32 ret = 0;
919
920 spin_lock_bh(&tp->lock);
921
922 if (tg3_writephy(tp, reg, val))
923 ret = -EIO;
924
925 spin_unlock_bh(&tp->lock);
926
927 return ret;
928 }
929
930 static int tg3_mdio_reset(struct mii_bus *bp)
931 {
932 return 0;
933 }
934
935 static void tg3_mdio_config_5785(struct tg3 *tp)
936 {
937 u32 val;
938 struct phy_device *phydev;
939
940 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
941 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
942 case TG3_PHY_ID_BCM50610:
943 case TG3_PHY_ID_BCM50610M:
944 val = MAC_PHYCFG2_50610_LED_MODES;
945 break;
946 case TG3_PHY_ID_BCMAC131:
947 val = MAC_PHYCFG2_AC131_LED_MODES;
948 break;
949 case TG3_PHY_ID_RTL8211C:
950 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
951 break;
952 case TG3_PHY_ID_RTL8201E:
953 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
954 break;
955 default:
956 return;
957 }
958
959 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
960 tw32(MAC_PHYCFG2, val);
961
962 val = tr32(MAC_PHYCFG1);
963 val &= ~(MAC_PHYCFG1_RGMII_INT |
964 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
965 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
966 tw32(MAC_PHYCFG1, val);
967
968 return;
969 }
970
971 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
972 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
973 MAC_PHYCFG2_FMODE_MASK_MASK |
974 MAC_PHYCFG2_GMODE_MASK_MASK |
975 MAC_PHYCFG2_ACT_MASK_MASK |
976 MAC_PHYCFG2_QUAL_MASK_MASK |
977 MAC_PHYCFG2_INBAND_ENABLE;
978
979 tw32(MAC_PHYCFG2, val);
980
981 val = tr32(MAC_PHYCFG1);
982 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
983 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
984 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
985 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
986 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
987 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
988 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
989 }
990 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
991 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
992 tw32(MAC_PHYCFG1, val);
993
994 val = tr32(MAC_EXT_RGMII_MODE);
995 val &= ~(MAC_RGMII_MODE_RX_INT_B |
996 MAC_RGMII_MODE_RX_QUALITY |
997 MAC_RGMII_MODE_RX_ACTIVITY |
998 MAC_RGMII_MODE_RX_ENG_DET |
999 MAC_RGMII_MODE_TX_ENABLE |
1000 MAC_RGMII_MODE_TX_LOWPWR |
1001 MAC_RGMII_MODE_TX_RESET);
1002 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1003 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1004 val |= MAC_RGMII_MODE_RX_INT_B |
1005 MAC_RGMII_MODE_RX_QUALITY |
1006 MAC_RGMII_MODE_RX_ACTIVITY |
1007 MAC_RGMII_MODE_RX_ENG_DET;
1008 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1009 val |= MAC_RGMII_MODE_TX_ENABLE |
1010 MAC_RGMII_MODE_TX_LOWPWR |
1011 MAC_RGMII_MODE_TX_RESET;
1012 }
1013 tw32(MAC_EXT_RGMII_MODE, val);
1014 }
1015
1016 static void tg3_mdio_start(struct tg3 *tp)
1017 {
1018 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1019 tw32_f(MAC_MI_MODE, tp->mi_mode);
1020 udelay(80);
1021
1022 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1023 u32 funcnum, is_serdes;
1024
1025 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1026 if (funcnum)
1027 tp->phy_addr = 2;
1028 else
1029 tp->phy_addr = 1;
1030
1031 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1032 if (is_serdes)
1033 tp->phy_addr += 7;
1034 } else
1035 tp->phy_addr = TG3_PHY_MII_ADDR;
1036
1037 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1038 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1039 tg3_mdio_config_5785(tp);
1040 }
1041
1042 static int tg3_mdio_init(struct tg3 *tp)
1043 {
1044 int i;
1045 u32 reg;
1046 struct phy_device *phydev;
1047
1048 tg3_mdio_start(tp);
1049
1050 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1051 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1052 return 0;
1053
1054 tp->mdio_bus = mdiobus_alloc();
1055 if (tp->mdio_bus == NULL)
1056 return -ENOMEM;
1057
1058 tp->mdio_bus->name = "tg3 mdio bus";
1059 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1060 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1061 tp->mdio_bus->priv = tp;
1062 tp->mdio_bus->parent = &tp->pdev->dev;
1063 tp->mdio_bus->read = &tg3_mdio_read;
1064 tp->mdio_bus->write = &tg3_mdio_write;
1065 tp->mdio_bus->reset = &tg3_mdio_reset;
1066 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1067 tp->mdio_bus->irq = &tp->mdio_irq[0];
1068
1069 for (i = 0; i < PHY_MAX_ADDR; i++)
1070 tp->mdio_bus->irq[i] = PHY_POLL;
1071
1072 /* The bus registration will look for all the PHYs on the mdio bus.
1073 * Unfortunately, it does not ensure the PHY is powered up before
1074 * accessing the PHY ID registers. A chip reset is the
1075 * quickest way to bring the device back to an operational state..
1076 */
1077 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1078 tg3_bmcr_reset(tp);
1079
1080 i = mdiobus_register(tp->mdio_bus);
1081 if (i) {
1082 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1083 tp->dev->name, i);
1084 mdiobus_free(tp->mdio_bus);
1085 return i;
1086 }
1087
1088 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1089
1090 if (!phydev || !phydev->drv) {
1091 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1092 mdiobus_unregister(tp->mdio_bus);
1093 mdiobus_free(tp->mdio_bus);
1094 return -ENODEV;
1095 }
1096
1097 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1098 case TG3_PHY_ID_BCM57780:
1099 phydev->interface = PHY_INTERFACE_MODE_GMII;
1100 break;
1101 case TG3_PHY_ID_BCM50610:
1102 case TG3_PHY_ID_BCM50610M:
1103 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1104 PHY_BRCM_RX_REFCLK_UNUSED;
1105 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1106 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1107 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1108 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1109 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1110 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1111 /* fallthru */
1112 case TG3_PHY_ID_RTL8211C:
1113 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1114 break;
1115 case TG3_PHY_ID_RTL8201E:
1116 case TG3_PHY_ID_BCMAC131:
1117 phydev->interface = PHY_INTERFACE_MODE_MII;
1118 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1119 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1120 break;
1121 }
1122
1123 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1124
1125 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1126 tg3_mdio_config_5785(tp);
1127
1128 return 0;
1129 }
1130
1131 static void tg3_mdio_fini(struct tg3 *tp)
1132 {
1133 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1134 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1135 mdiobus_unregister(tp->mdio_bus);
1136 mdiobus_free(tp->mdio_bus);
1137 }
1138 }
1139
1140 /* tp->lock is held. */
1141 static inline void tg3_generate_fw_event(struct tg3 *tp)
1142 {
1143 u32 val;
1144
1145 val = tr32(GRC_RX_CPU_EVENT);
1146 val |= GRC_RX_CPU_DRIVER_EVENT;
1147 tw32_f(GRC_RX_CPU_EVENT, val);
1148
1149 tp->last_event_jiffies = jiffies;
1150 }
1151
1152 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1153
1154 /* tp->lock is held. */
1155 static void tg3_wait_for_event_ack(struct tg3 *tp)
1156 {
1157 int i;
1158 unsigned int delay_cnt;
1159 long time_remain;
1160
1161 /* If enough time has passed, no wait is necessary. */
1162 time_remain = (long)(tp->last_event_jiffies + 1 +
1163 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1164 (long)jiffies;
1165 if (time_remain < 0)
1166 return;
1167
1168 /* Check if we can shorten the wait time. */
1169 delay_cnt = jiffies_to_usecs(time_remain);
1170 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1171 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1172 delay_cnt = (delay_cnt >> 3) + 1;
1173
1174 for (i = 0; i < delay_cnt; i++) {
1175 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1176 break;
1177 udelay(8);
1178 }
1179 }
1180
1181 /* tp->lock is held. */
1182 static void tg3_ump_link_report(struct tg3 *tp)
1183 {
1184 u32 reg;
1185 u32 val;
1186
1187 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1188 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1189 return;
1190
1191 tg3_wait_for_event_ack(tp);
1192
1193 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1194
1195 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1196
1197 val = 0;
1198 if (!tg3_readphy(tp, MII_BMCR, &reg))
1199 val = reg << 16;
1200 if (!tg3_readphy(tp, MII_BMSR, &reg))
1201 val |= (reg & 0xffff);
1202 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1203
1204 val = 0;
1205 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1206 val = reg << 16;
1207 if (!tg3_readphy(tp, MII_LPA, &reg))
1208 val |= (reg & 0xffff);
1209 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1210
1211 val = 0;
1212 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1213 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1214 val = reg << 16;
1215 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1216 val |= (reg & 0xffff);
1217 }
1218 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1219
1220 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1221 val = reg << 16;
1222 else
1223 val = 0;
1224 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1225
1226 tg3_generate_fw_event(tp);
1227 }
1228
1229 static void tg3_link_report(struct tg3 *tp)
1230 {
1231 if (!netif_carrier_ok(tp->dev)) {
1232 if (netif_msg_link(tp))
1233 printk(KERN_INFO PFX "%s: Link is down.\n",
1234 tp->dev->name);
1235 tg3_ump_link_report(tp);
1236 } else if (netif_msg_link(tp)) {
1237 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1238 tp->dev->name,
1239 (tp->link_config.active_speed == SPEED_1000 ?
1240 1000 :
1241 (tp->link_config.active_speed == SPEED_100 ?
1242 100 : 10)),
1243 (tp->link_config.active_duplex == DUPLEX_FULL ?
1244 "full" : "half"));
1245
1246 printk(KERN_INFO PFX
1247 "%s: Flow control is %s for TX and %s for RX.\n",
1248 tp->dev->name,
1249 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1250 "on" : "off",
1251 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1252 "on" : "off");
1253 tg3_ump_link_report(tp);
1254 }
1255 }
1256
1257 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1258 {
1259 u16 miireg;
1260
1261 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1262 miireg = ADVERTISE_PAUSE_CAP;
1263 else if (flow_ctrl & FLOW_CTRL_TX)
1264 miireg = ADVERTISE_PAUSE_ASYM;
1265 else if (flow_ctrl & FLOW_CTRL_RX)
1266 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1267 else
1268 miireg = 0;
1269
1270 return miireg;
1271 }
1272
1273 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1274 {
1275 u16 miireg;
1276
1277 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1278 miireg = ADVERTISE_1000XPAUSE;
1279 else if (flow_ctrl & FLOW_CTRL_TX)
1280 miireg = ADVERTISE_1000XPSE_ASYM;
1281 else if (flow_ctrl & FLOW_CTRL_RX)
1282 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1283 else
1284 miireg = 0;
1285
1286 return miireg;
1287 }
1288
1289 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1290 {
1291 u8 cap = 0;
1292
1293 if (lcladv & ADVERTISE_1000XPAUSE) {
1294 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1295 if (rmtadv & LPA_1000XPAUSE)
1296 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1297 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1298 cap = FLOW_CTRL_RX;
1299 } else {
1300 if (rmtadv & LPA_1000XPAUSE)
1301 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1302 }
1303 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1304 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1305 cap = FLOW_CTRL_TX;
1306 }
1307
1308 return cap;
1309 }
1310
1311 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1312 {
1313 u8 autoneg;
1314 u8 flowctrl = 0;
1315 u32 old_rx_mode = tp->rx_mode;
1316 u32 old_tx_mode = tp->tx_mode;
1317
1318 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1319 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1320 else
1321 autoneg = tp->link_config.autoneg;
1322
1323 if (autoneg == AUTONEG_ENABLE &&
1324 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1325 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1326 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1327 else
1328 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1329 } else
1330 flowctrl = tp->link_config.flowctrl;
1331
1332 tp->link_config.active_flowctrl = flowctrl;
1333
1334 if (flowctrl & FLOW_CTRL_RX)
1335 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1336 else
1337 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1338
1339 if (old_rx_mode != tp->rx_mode)
1340 tw32_f(MAC_RX_MODE, tp->rx_mode);
1341
1342 if (flowctrl & FLOW_CTRL_TX)
1343 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1344 else
1345 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1346
1347 if (old_tx_mode != tp->tx_mode)
1348 tw32_f(MAC_TX_MODE, tp->tx_mode);
1349 }
1350
1351 static void tg3_adjust_link(struct net_device *dev)
1352 {
1353 u8 oldflowctrl, linkmesg = 0;
1354 u32 mac_mode, lcl_adv, rmt_adv;
1355 struct tg3 *tp = netdev_priv(dev);
1356 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1357
1358 spin_lock_bh(&tp->lock);
1359
1360 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1361 MAC_MODE_HALF_DUPLEX);
1362
1363 oldflowctrl = tp->link_config.active_flowctrl;
1364
1365 if (phydev->link) {
1366 lcl_adv = 0;
1367 rmt_adv = 0;
1368
1369 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1370 mac_mode |= MAC_MODE_PORT_MODE_MII;
1371 else if (phydev->speed == SPEED_1000 ||
1372 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1373 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1374 else
1375 mac_mode |= MAC_MODE_PORT_MODE_MII;
1376
1377 if (phydev->duplex == DUPLEX_HALF)
1378 mac_mode |= MAC_MODE_HALF_DUPLEX;
1379 else {
1380 lcl_adv = tg3_advert_flowctrl_1000T(
1381 tp->link_config.flowctrl);
1382
1383 if (phydev->pause)
1384 rmt_adv = LPA_PAUSE_CAP;
1385 if (phydev->asym_pause)
1386 rmt_adv |= LPA_PAUSE_ASYM;
1387 }
1388
1389 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1390 } else
1391 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1392
1393 if (mac_mode != tp->mac_mode) {
1394 tp->mac_mode = mac_mode;
1395 tw32_f(MAC_MODE, tp->mac_mode);
1396 udelay(40);
1397 }
1398
1399 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1400 if (phydev->speed == SPEED_10)
1401 tw32(MAC_MI_STAT,
1402 MAC_MI_STAT_10MBPS_MODE |
1403 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1404 else
1405 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1406 }
1407
1408 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1409 tw32(MAC_TX_LENGTHS,
1410 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1411 (6 << TX_LENGTHS_IPG_SHIFT) |
1412 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1413 else
1414 tw32(MAC_TX_LENGTHS,
1415 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1416 (6 << TX_LENGTHS_IPG_SHIFT) |
1417 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1418
1419 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1420 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1421 phydev->speed != tp->link_config.active_speed ||
1422 phydev->duplex != tp->link_config.active_duplex ||
1423 oldflowctrl != tp->link_config.active_flowctrl)
1424 linkmesg = 1;
1425
1426 tp->link_config.active_speed = phydev->speed;
1427 tp->link_config.active_duplex = phydev->duplex;
1428
1429 spin_unlock_bh(&tp->lock);
1430
1431 if (linkmesg)
1432 tg3_link_report(tp);
1433 }
1434
1435 static int tg3_phy_init(struct tg3 *tp)
1436 {
1437 struct phy_device *phydev;
1438
1439 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1440 return 0;
1441
1442 /* Bring the PHY back to a known state. */
1443 tg3_bmcr_reset(tp);
1444
1445 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1446
1447 /* Attach the MAC to the PHY. */
1448 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1449 phydev->dev_flags, phydev->interface);
1450 if (IS_ERR(phydev)) {
1451 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1452 return PTR_ERR(phydev);
1453 }
1454
1455 /* Mask with MAC supported features. */
1456 switch (phydev->interface) {
1457 case PHY_INTERFACE_MODE_GMII:
1458 case PHY_INTERFACE_MODE_RGMII:
1459 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1460 phydev->supported &= (PHY_GBIT_FEATURES |
1461 SUPPORTED_Pause |
1462 SUPPORTED_Asym_Pause);
1463 break;
1464 }
1465 /* fallthru */
1466 case PHY_INTERFACE_MODE_MII:
1467 phydev->supported &= (PHY_BASIC_FEATURES |
1468 SUPPORTED_Pause |
1469 SUPPORTED_Asym_Pause);
1470 break;
1471 default:
1472 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1473 return -EINVAL;
1474 }
1475
1476 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1477
1478 phydev->advertising = phydev->supported;
1479
1480 return 0;
1481 }
1482
1483 static void tg3_phy_start(struct tg3 *tp)
1484 {
1485 struct phy_device *phydev;
1486
1487 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1488 return;
1489
1490 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1491
1492 if (tp->link_config.phy_is_low_power) {
1493 tp->link_config.phy_is_low_power = 0;
1494 phydev->speed = tp->link_config.orig_speed;
1495 phydev->duplex = tp->link_config.orig_duplex;
1496 phydev->autoneg = tp->link_config.orig_autoneg;
1497 phydev->advertising = tp->link_config.orig_advertising;
1498 }
1499
1500 phy_start(phydev);
1501
1502 phy_start_aneg(phydev);
1503 }
1504
1505 static void tg3_phy_stop(struct tg3 *tp)
1506 {
1507 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1508 return;
1509
1510 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1511 }
1512
1513 static void tg3_phy_fini(struct tg3 *tp)
1514 {
1515 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1516 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1517 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1518 }
1519 }
1520
1521 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1522 {
1523 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1524 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1525 }
1526
1527 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1528 {
1529 u32 phytest;
1530
1531 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1532 u32 phy;
1533
1534 tg3_writephy(tp, MII_TG3_FET_TEST,
1535 phytest | MII_TG3_FET_SHADOW_EN);
1536 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1537 if (enable)
1538 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1539 else
1540 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1541 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1542 }
1543 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1544 }
1545 }
1546
1547 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1548 {
1549 u32 reg;
1550
1551 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1552 return;
1553
1554 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1555 tg3_phy_fet_toggle_apd(tp, enable);
1556 return;
1557 }
1558
1559 reg = MII_TG3_MISC_SHDW_WREN |
1560 MII_TG3_MISC_SHDW_SCR5_SEL |
1561 MII_TG3_MISC_SHDW_SCR5_LPED |
1562 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1563 MII_TG3_MISC_SHDW_SCR5_SDTL |
1564 MII_TG3_MISC_SHDW_SCR5_C125OE;
1565 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1566 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1567
1568 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1569
1570
1571 reg = MII_TG3_MISC_SHDW_WREN |
1572 MII_TG3_MISC_SHDW_APD_SEL |
1573 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1574 if (enable)
1575 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1576
1577 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1578 }
1579
1580 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1581 {
1582 u32 phy;
1583
1584 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1585 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1586 return;
1587
1588 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1589 u32 ephy;
1590
1591 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1592 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1593
1594 tg3_writephy(tp, MII_TG3_FET_TEST,
1595 ephy | MII_TG3_FET_SHADOW_EN);
1596 if (!tg3_readphy(tp, reg, &phy)) {
1597 if (enable)
1598 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1599 else
1600 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1601 tg3_writephy(tp, reg, phy);
1602 }
1603 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1604 }
1605 } else {
1606 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1607 MII_TG3_AUXCTL_SHDWSEL_MISC;
1608 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1609 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1610 if (enable)
1611 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1612 else
1613 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1614 phy |= MII_TG3_AUXCTL_MISC_WREN;
1615 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1616 }
1617 }
1618 }
1619
1620 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1621 {
1622 u32 val;
1623
1624 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1625 return;
1626
1627 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1628 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1629 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1630 (val | (1 << 15) | (1 << 4)));
1631 }
1632
1633 static void tg3_phy_apply_otp(struct tg3 *tp)
1634 {
1635 u32 otp, phy;
1636
1637 if (!tp->phy_otp)
1638 return;
1639
1640 otp = tp->phy_otp;
1641
1642 /* Enable SM_DSP clock and tx 6dB coding. */
1643 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1644 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1645 MII_TG3_AUXCTL_ACTL_TX_6DB;
1646 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1647
1648 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1649 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1650 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1651
1652 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1653 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1654 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1655
1656 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1657 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1658 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1659
1660 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1661 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1662
1663 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1664 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1665
1666 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1667 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1668 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1669
1670 /* Turn off SM_DSP clock. */
1671 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1672 MII_TG3_AUXCTL_ACTL_TX_6DB;
1673 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1674 }
1675
1676 static int tg3_wait_macro_done(struct tg3 *tp)
1677 {
1678 int limit = 100;
1679
1680 while (limit--) {
1681 u32 tmp32;
1682
1683 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1684 if ((tmp32 & 0x1000) == 0)
1685 break;
1686 }
1687 }
1688 if (limit < 0)
1689 return -EBUSY;
1690
1691 return 0;
1692 }
1693
1694 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1695 {
1696 static const u32 test_pat[4][6] = {
1697 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1698 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1699 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1700 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1701 };
1702 int chan;
1703
1704 for (chan = 0; chan < 4; chan++) {
1705 int i;
1706
1707 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1708 (chan * 0x2000) | 0x0200);
1709 tg3_writephy(tp, 0x16, 0x0002);
1710
1711 for (i = 0; i < 6; i++)
1712 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1713 test_pat[chan][i]);
1714
1715 tg3_writephy(tp, 0x16, 0x0202);
1716 if (tg3_wait_macro_done(tp)) {
1717 *resetp = 1;
1718 return -EBUSY;
1719 }
1720
1721 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1722 (chan * 0x2000) | 0x0200);
1723 tg3_writephy(tp, 0x16, 0x0082);
1724 if (tg3_wait_macro_done(tp)) {
1725 *resetp = 1;
1726 return -EBUSY;
1727 }
1728
1729 tg3_writephy(tp, 0x16, 0x0802);
1730 if (tg3_wait_macro_done(tp)) {
1731 *resetp = 1;
1732 return -EBUSY;
1733 }
1734
1735 for (i = 0; i < 6; i += 2) {
1736 u32 low, high;
1737
1738 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1739 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1740 tg3_wait_macro_done(tp)) {
1741 *resetp = 1;
1742 return -EBUSY;
1743 }
1744 low &= 0x7fff;
1745 high &= 0x000f;
1746 if (low != test_pat[chan][i] ||
1747 high != test_pat[chan][i+1]) {
1748 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1749 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1750 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1751
1752 return -EBUSY;
1753 }
1754 }
1755 }
1756
1757 return 0;
1758 }
1759
1760 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1761 {
1762 int chan;
1763
1764 for (chan = 0; chan < 4; chan++) {
1765 int i;
1766
1767 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1768 (chan * 0x2000) | 0x0200);
1769 tg3_writephy(tp, 0x16, 0x0002);
1770 for (i = 0; i < 6; i++)
1771 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1772 tg3_writephy(tp, 0x16, 0x0202);
1773 if (tg3_wait_macro_done(tp))
1774 return -EBUSY;
1775 }
1776
1777 return 0;
1778 }
1779
1780 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1781 {
1782 u32 reg32, phy9_orig;
1783 int retries, do_phy_reset, err;
1784
1785 retries = 10;
1786 do_phy_reset = 1;
1787 do {
1788 if (do_phy_reset) {
1789 err = tg3_bmcr_reset(tp);
1790 if (err)
1791 return err;
1792 do_phy_reset = 0;
1793 }
1794
1795 /* Disable transmitter and interrupt. */
1796 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1797 continue;
1798
1799 reg32 |= 0x3000;
1800 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1801
1802 /* Set full-duplex, 1000 mbps. */
1803 tg3_writephy(tp, MII_BMCR,
1804 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1805
1806 /* Set to master mode. */
1807 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1808 continue;
1809
1810 tg3_writephy(tp, MII_TG3_CTRL,
1811 (MII_TG3_CTRL_AS_MASTER |
1812 MII_TG3_CTRL_ENABLE_AS_MASTER));
1813
1814 /* Enable SM_DSP_CLOCK and 6dB. */
1815 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1816
1817 /* Block the PHY control access. */
1818 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1819 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1820
1821 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1822 if (!err)
1823 break;
1824 } while (--retries);
1825
1826 err = tg3_phy_reset_chanpat(tp);
1827 if (err)
1828 return err;
1829
1830 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1831 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1832
1833 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1834 tg3_writephy(tp, 0x16, 0x0000);
1835
1836 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1837 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1838 /* Set Extended packet length bit for jumbo frames */
1839 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1840 }
1841 else {
1842 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1843 }
1844
1845 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1846
1847 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1848 reg32 &= ~0x3000;
1849 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1850 } else if (!err)
1851 err = -EBUSY;
1852
1853 return err;
1854 }
1855
1856 /* This will reset the tigon3 PHY if there is no valid
1857 * link unless the FORCE argument is non-zero.
1858 */
1859 static int tg3_phy_reset(struct tg3 *tp)
1860 {
1861 u32 cpmuctrl;
1862 u32 phy_status;
1863 int err;
1864
1865 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1866 u32 val;
1867
1868 val = tr32(GRC_MISC_CFG);
1869 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1870 udelay(40);
1871 }
1872 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1873 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1874 if (err != 0)
1875 return -EBUSY;
1876
1877 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1878 netif_carrier_off(tp->dev);
1879 tg3_link_report(tp);
1880 }
1881
1882 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1883 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1884 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1885 err = tg3_phy_reset_5703_4_5(tp);
1886 if (err)
1887 return err;
1888 goto out;
1889 }
1890
1891 cpmuctrl = 0;
1892 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1893 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1894 cpmuctrl = tr32(TG3_CPMU_CTRL);
1895 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1896 tw32(TG3_CPMU_CTRL,
1897 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1898 }
1899
1900 err = tg3_bmcr_reset(tp);
1901 if (err)
1902 return err;
1903
1904 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1905 u32 phy;
1906
1907 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1908 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1909
1910 tw32(TG3_CPMU_CTRL, cpmuctrl);
1911 }
1912
1913 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1914 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1915 u32 val;
1916
1917 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1918 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1919 CPMU_LSPD_1000MB_MACCLK_12_5) {
1920 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1921 udelay(40);
1922 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1923 }
1924 }
1925
1926 tg3_phy_apply_otp(tp);
1927
1928 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1929 tg3_phy_toggle_apd(tp, true);
1930 else
1931 tg3_phy_toggle_apd(tp, false);
1932
1933 out:
1934 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1935 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1936 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1937 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1938 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1939 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1940 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1941 }
1942 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1943 tg3_writephy(tp, 0x1c, 0x8d68);
1944 tg3_writephy(tp, 0x1c, 0x8d68);
1945 }
1946 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1947 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1948 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1949 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1950 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1951 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1952 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1953 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1954 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1955 }
1956 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1957 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1958 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1959 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1960 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1961 tg3_writephy(tp, MII_TG3_TEST1,
1962 MII_TG3_TEST1_TRIM_EN | 0x4);
1963 } else
1964 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1965 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1966 }
1967 /* Set Extended packet length bit (bit 14) on all chips that */
1968 /* support jumbo frames */
1969 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1970 /* Cannot do read-modify-write on 5401 */
1971 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1972 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1973 u32 phy_reg;
1974
1975 /* Set bit 14 with read-modify-write to preserve other bits */
1976 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1977 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1978 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1979 }
1980
1981 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1982 * jumbo frames transmission.
1983 */
1984 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1985 u32 phy_reg;
1986
1987 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1988 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1989 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1990 }
1991
1992 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1993 /* adjust output voltage */
1994 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
1995 }
1996
1997 tg3_phy_toggle_automdix(tp, 1);
1998 tg3_phy_set_wirespeed(tp);
1999 return 0;
2000 }
2001
2002 static void tg3_frob_aux_power(struct tg3 *tp)
2003 {
2004 struct tg3 *tp_peer = tp;
2005
2006 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
2007 return;
2008
2009 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2010 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2011 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2012 struct net_device *dev_peer;
2013
2014 dev_peer = pci_get_drvdata(tp->pdev_peer);
2015 /* remove_one() may have been run on the peer. */
2016 if (!dev_peer)
2017 tp_peer = tp;
2018 else
2019 tp_peer = netdev_priv(dev_peer);
2020 }
2021
2022 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2023 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2024 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2025 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2026 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2027 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2028 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2029 (GRC_LCLCTRL_GPIO_OE0 |
2030 GRC_LCLCTRL_GPIO_OE1 |
2031 GRC_LCLCTRL_GPIO_OE2 |
2032 GRC_LCLCTRL_GPIO_OUTPUT0 |
2033 GRC_LCLCTRL_GPIO_OUTPUT1),
2034 100);
2035 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2036 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2037 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2038 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2039 GRC_LCLCTRL_GPIO_OE1 |
2040 GRC_LCLCTRL_GPIO_OE2 |
2041 GRC_LCLCTRL_GPIO_OUTPUT0 |
2042 GRC_LCLCTRL_GPIO_OUTPUT1 |
2043 tp->grc_local_ctrl;
2044 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2045
2046 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2047 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2048
2049 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2050 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2051 } else {
2052 u32 no_gpio2;
2053 u32 grc_local_ctrl = 0;
2054
2055 if (tp_peer != tp &&
2056 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2057 return;
2058
2059 /* Workaround to prevent overdrawing Amps. */
2060 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2061 ASIC_REV_5714) {
2062 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2063 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2064 grc_local_ctrl, 100);
2065 }
2066
2067 /* On 5753 and variants, GPIO2 cannot be used. */
2068 no_gpio2 = tp->nic_sram_data_cfg &
2069 NIC_SRAM_DATA_CFG_NO_GPIO2;
2070
2071 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2072 GRC_LCLCTRL_GPIO_OE1 |
2073 GRC_LCLCTRL_GPIO_OE2 |
2074 GRC_LCLCTRL_GPIO_OUTPUT1 |
2075 GRC_LCLCTRL_GPIO_OUTPUT2;
2076 if (no_gpio2) {
2077 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2078 GRC_LCLCTRL_GPIO_OUTPUT2);
2079 }
2080 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2081 grc_local_ctrl, 100);
2082
2083 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2084
2085 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2086 grc_local_ctrl, 100);
2087
2088 if (!no_gpio2) {
2089 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2090 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2091 grc_local_ctrl, 100);
2092 }
2093 }
2094 } else {
2095 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2096 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2097 if (tp_peer != tp &&
2098 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2099 return;
2100
2101 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2102 (GRC_LCLCTRL_GPIO_OE1 |
2103 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2104
2105 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2106 GRC_LCLCTRL_GPIO_OE1, 100);
2107
2108 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2109 (GRC_LCLCTRL_GPIO_OE1 |
2110 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2111 }
2112 }
2113 }
2114
2115 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2116 {
2117 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2118 return 1;
2119 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2120 if (speed != SPEED_10)
2121 return 1;
2122 } else if (speed == SPEED_10)
2123 return 1;
2124
2125 return 0;
2126 }
2127
2128 static int tg3_setup_phy(struct tg3 *, int);
2129
2130 #define RESET_KIND_SHUTDOWN 0
2131 #define RESET_KIND_INIT 1
2132 #define RESET_KIND_SUSPEND 2
2133
2134 static void tg3_write_sig_post_reset(struct tg3 *, int);
2135 static int tg3_halt_cpu(struct tg3 *, u32);
2136
2137 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2138 {
2139 u32 val;
2140
2141 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2142 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2143 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2144 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2145
2146 sg_dig_ctrl |=
2147 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2148 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2149 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2150 }
2151 return;
2152 }
2153
2154 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2155 tg3_bmcr_reset(tp);
2156 val = tr32(GRC_MISC_CFG);
2157 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2158 udelay(40);
2159 return;
2160 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2161 u32 phytest;
2162 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2163 u32 phy;
2164
2165 tg3_writephy(tp, MII_ADVERTISE, 0);
2166 tg3_writephy(tp, MII_BMCR,
2167 BMCR_ANENABLE | BMCR_ANRESTART);
2168
2169 tg3_writephy(tp, MII_TG3_FET_TEST,
2170 phytest | MII_TG3_FET_SHADOW_EN);
2171 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2172 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2173 tg3_writephy(tp,
2174 MII_TG3_FET_SHDW_AUXMODE4,
2175 phy);
2176 }
2177 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2178 }
2179 return;
2180 } else if (do_low_power) {
2181 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2182 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2183
2184 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2185 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2186 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2187 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2188 MII_TG3_AUXCTL_PCTL_VREG_11V);
2189 }
2190
2191 /* The PHY should not be powered down on some chips because
2192 * of bugs.
2193 */
2194 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2195 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2196 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2197 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2198 return;
2199
2200 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2201 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2202 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2203 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2204 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2205 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2206 }
2207
2208 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2209 }
2210
2211 /* tp->lock is held. */
2212 static int tg3_nvram_lock(struct tg3 *tp)
2213 {
2214 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2215 int i;
2216
2217 if (tp->nvram_lock_cnt == 0) {
2218 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2219 for (i = 0; i < 8000; i++) {
2220 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2221 break;
2222 udelay(20);
2223 }
2224 if (i == 8000) {
2225 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2226 return -ENODEV;
2227 }
2228 }
2229 tp->nvram_lock_cnt++;
2230 }
2231 return 0;
2232 }
2233
2234 /* tp->lock is held. */
2235 static void tg3_nvram_unlock(struct tg3 *tp)
2236 {
2237 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2238 if (tp->nvram_lock_cnt > 0)
2239 tp->nvram_lock_cnt--;
2240 if (tp->nvram_lock_cnt == 0)
2241 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2242 }
2243 }
2244
2245 /* tp->lock is held. */
2246 static void tg3_enable_nvram_access(struct tg3 *tp)
2247 {
2248 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2249 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2250 u32 nvaccess = tr32(NVRAM_ACCESS);
2251
2252 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2253 }
2254 }
2255
2256 /* tp->lock is held. */
2257 static void tg3_disable_nvram_access(struct tg3 *tp)
2258 {
2259 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2260 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2261 u32 nvaccess = tr32(NVRAM_ACCESS);
2262
2263 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2264 }
2265 }
2266
2267 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2268 u32 offset, u32 *val)
2269 {
2270 u32 tmp;
2271 int i;
2272
2273 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2274 return -EINVAL;
2275
2276 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2277 EEPROM_ADDR_DEVID_MASK |
2278 EEPROM_ADDR_READ);
2279 tw32(GRC_EEPROM_ADDR,
2280 tmp |
2281 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2282 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2283 EEPROM_ADDR_ADDR_MASK) |
2284 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2285
2286 for (i = 0; i < 1000; i++) {
2287 tmp = tr32(GRC_EEPROM_ADDR);
2288
2289 if (tmp & EEPROM_ADDR_COMPLETE)
2290 break;
2291 msleep(1);
2292 }
2293 if (!(tmp & EEPROM_ADDR_COMPLETE))
2294 return -EBUSY;
2295
2296 tmp = tr32(GRC_EEPROM_DATA);
2297
2298 /*
2299 * The data will always be opposite the native endian
2300 * format. Perform a blind byteswap to compensate.
2301 */
2302 *val = swab32(tmp);
2303
2304 return 0;
2305 }
2306
2307 #define NVRAM_CMD_TIMEOUT 10000
2308
2309 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2310 {
2311 int i;
2312
2313 tw32(NVRAM_CMD, nvram_cmd);
2314 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2315 udelay(10);
2316 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2317 udelay(10);
2318 break;
2319 }
2320 }
2321
2322 if (i == NVRAM_CMD_TIMEOUT)
2323 return -EBUSY;
2324
2325 return 0;
2326 }
2327
2328 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2329 {
2330 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2331 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2332 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2333 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2334 (tp->nvram_jedecnum == JEDEC_ATMEL))
2335
2336 addr = ((addr / tp->nvram_pagesize) <<
2337 ATMEL_AT45DB0X1B_PAGE_POS) +
2338 (addr % tp->nvram_pagesize);
2339
2340 return addr;
2341 }
2342
2343 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2344 {
2345 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2346 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2347 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2348 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2349 (tp->nvram_jedecnum == JEDEC_ATMEL))
2350
2351 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2352 tp->nvram_pagesize) +
2353 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2354
2355 return addr;
2356 }
2357
2358 /* NOTE: Data read in from NVRAM is byteswapped according to
2359 * the byteswapping settings for all other register accesses.
2360 * tg3 devices are BE devices, so on a BE machine, the data
2361 * returned will be exactly as it is seen in NVRAM. On a LE
2362 * machine, the 32-bit value will be byteswapped.
2363 */
2364 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2365 {
2366 int ret;
2367
2368 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2369 return tg3_nvram_read_using_eeprom(tp, offset, val);
2370
2371 offset = tg3_nvram_phys_addr(tp, offset);
2372
2373 if (offset > NVRAM_ADDR_MSK)
2374 return -EINVAL;
2375
2376 ret = tg3_nvram_lock(tp);
2377 if (ret)
2378 return ret;
2379
2380 tg3_enable_nvram_access(tp);
2381
2382 tw32(NVRAM_ADDR, offset);
2383 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2384 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2385
2386 if (ret == 0)
2387 *val = tr32(NVRAM_RDDATA);
2388
2389 tg3_disable_nvram_access(tp);
2390
2391 tg3_nvram_unlock(tp);
2392
2393 return ret;
2394 }
2395
2396 /* Ensures NVRAM data is in bytestream format. */
2397 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2398 {
2399 u32 v;
2400 int res = tg3_nvram_read(tp, offset, &v);
2401 if (!res)
2402 *val = cpu_to_be32(v);
2403 return res;
2404 }
2405
2406 /* tp->lock is held. */
2407 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2408 {
2409 u32 addr_high, addr_low;
2410 int i;
2411
2412 addr_high = ((tp->dev->dev_addr[0] << 8) |
2413 tp->dev->dev_addr[1]);
2414 addr_low = ((tp->dev->dev_addr[2] << 24) |
2415 (tp->dev->dev_addr[3] << 16) |
2416 (tp->dev->dev_addr[4] << 8) |
2417 (tp->dev->dev_addr[5] << 0));
2418 for (i = 0; i < 4; i++) {
2419 if (i == 1 && skip_mac_1)
2420 continue;
2421 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2422 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2423 }
2424
2425 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2426 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2427 for (i = 0; i < 12; i++) {
2428 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2429 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2430 }
2431 }
2432
2433 addr_high = (tp->dev->dev_addr[0] +
2434 tp->dev->dev_addr[1] +
2435 tp->dev->dev_addr[2] +
2436 tp->dev->dev_addr[3] +
2437 tp->dev->dev_addr[4] +
2438 tp->dev->dev_addr[5]) &
2439 TX_BACKOFF_SEED_MASK;
2440 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2441 }
2442
2443 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2444 {
2445 u32 misc_host_ctrl;
2446 bool device_should_wake, do_low_power;
2447
2448 /* Make sure register accesses (indirect or otherwise)
2449 * will function correctly.
2450 */
2451 pci_write_config_dword(tp->pdev,
2452 TG3PCI_MISC_HOST_CTRL,
2453 tp->misc_host_ctrl);
2454
2455 switch (state) {
2456 case PCI_D0:
2457 pci_enable_wake(tp->pdev, state, false);
2458 pci_set_power_state(tp->pdev, PCI_D0);
2459
2460 /* Switch out of Vaux if it is a NIC */
2461 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2462 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2463
2464 return 0;
2465
2466 case PCI_D1:
2467 case PCI_D2:
2468 case PCI_D3hot:
2469 break;
2470
2471 default:
2472 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2473 tp->dev->name, state);
2474 return -EINVAL;
2475 }
2476
2477 /* Restore the CLKREQ setting. */
2478 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2479 u16 lnkctl;
2480
2481 pci_read_config_word(tp->pdev,
2482 tp->pcie_cap + PCI_EXP_LNKCTL,
2483 &lnkctl);
2484 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2485 pci_write_config_word(tp->pdev,
2486 tp->pcie_cap + PCI_EXP_LNKCTL,
2487 lnkctl);
2488 }
2489
2490 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2491 tw32(TG3PCI_MISC_HOST_CTRL,
2492 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2493
2494 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2495 device_may_wakeup(&tp->pdev->dev) &&
2496 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2497
2498 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2499 do_low_power = false;
2500 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2501 !tp->link_config.phy_is_low_power) {
2502 struct phy_device *phydev;
2503 u32 phyid, advertising;
2504
2505 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2506
2507 tp->link_config.phy_is_low_power = 1;
2508
2509 tp->link_config.orig_speed = phydev->speed;
2510 tp->link_config.orig_duplex = phydev->duplex;
2511 tp->link_config.orig_autoneg = phydev->autoneg;
2512 tp->link_config.orig_advertising = phydev->advertising;
2513
2514 advertising = ADVERTISED_TP |
2515 ADVERTISED_Pause |
2516 ADVERTISED_Autoneg |
2517 ADVERTISED_10baseT_Half;
2518
2519 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2520 device_should_wake) {
2521 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2522 advertising |=
2523 ADVERTISED_100baseT_Half |
2524 ADVERTISED_100baseT_Full |
2525 ADVERTISED_10baseT_Full;
2526 else
2527 advertising |= ADVERTISED_10baseT_Full;
2528 }
2529
2530 phydev->advertising = advertising;
2531
2532 phy_start_aneg(phydev);
2533
2534 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2535 if (phyid != TG3_PHY_ID_BCMAC131) {
2536 phyid &= TG3_PHY_OUI_MASK;
2537 if (phyid == TG3_PHY_OUI_1 ||
2538 phyid == TG3_PHY_OUI_2 ||
2539 phyid == TG3_PHY_OUI_3)
2540 do_low_power = true;
2541 }
2542 }
2543 } else {
2544 do_low_power = true;
2545
2546 if (tp->link_config.phy_is_low_power == 0) {
2547 tp->link_config.phy_is_low_power = 1;
2548 tp->link_config.orig_speed = tp->link_config.speed;
2549 tp->link_config.orig_duplex = tp->link_config.duplex;
2550 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2551 }
2552
2553 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2554 tp->link_config.speed = SPEED_10;
2555 tp->link_config.duplex = DUPLEX_HALF;
2556 tp->link_config.autoneg = AUTONEG_ENABLE;
2557 tg3_setup_phy(tp, 0);
2558 }
2559 }
2560
2561 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2562 u32 val;
2563
2564 val = tr32(GRC_VCPU_EXT_CTRL);
2565 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2566 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2567 int i;
2568 u32 val;
2569
2570 for (i = 0; i < 200; i++) {
2571 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2572 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2573 break;
2574 msleep(1);
2575 }
2576 }
2577 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2578 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2579 WOL_DRV_STATE_SHUTDOWN |
2580 WOL_DRV_WOL |
2581 WOL_SET_MAGIC_PKT);
2582
2583 if (device_should_wake) {
2584 u32 mac_mode;
2585
2586 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2587 if (do_low_power) {
2588 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2589 udelay(40);
2590 }
2591
2592 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2593 mac_mode = MAC_MODE_PORT_MODE_GMII;
2594 else
2595 mac_mode = MAC_MODE_PORT_MODE_MII;
2596
2597 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2598 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2599 ASIC_REV_5700) {
2600 u32 speed = (tp->tg3_flags &
2601 TG3_FLAG_WOL_SPEED_100MB) ?
2602 SPEED_100 : SPEED_10;
2603 if (tg3_5700_link_polarity(tp, speed))
2604 mac_mode |= MAC_MODE_LINK_POLARITY;
2605 else
2606 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2607 }
2608 } else {
2609 mac_mode = MAC_MODE_PORT_MODE_TBI;
2610 }
2611
2612 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2613 tw32(MAC_LED_CTRL, tp->led_ctrl);
2614
2615 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2616 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2617 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2618 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2619 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2620 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2621
2622 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2623 mac_mode |= tp->mac_mode &
2624 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2625 if (mac_mode & MAC_MODE_APE_TX_EN)
2626 mac_mode |= MAC_MODE_TDE_ENABLE;
2627 }
2628
2629 tw32_f(MAC_MODE, mac_mode);
2630 udelay(100);
2631
2632 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2633 udelay(10);
2634 }
2635
2636 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2637 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2638 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2639 u32 base_val;
2640
2641 base_val = tp->pci_clock_ctrl;
2642 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2643 CLOCK_CTRL_TXCLK_DISABLE);
2644
2645 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2646 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2647 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2648 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2649 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2650 /* do nothing */
2651 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2652 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2653 u32 newbits1, newbits2;
2654
2655 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2656 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2657 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2658 CLOCK_CTRL_TXCLK_DISABLE |
2659 CLOCK_CTRL_ALTCLK);
2660 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2661 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2662 newbits1 = CLOCK_CTRL_625_CORE;
2663 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2664 } else {
2665 newbits1 = CLOCK_CTRL_ALTCLK;
2666 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2667 }
2668
2669 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2670 40);
2671
2672 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2673 40);
2674
2675 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2676 u32 newbits3;
2677
2678 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2679 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2680 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2681 CLOCK_CTRL_TXCLK_DISABLE |
2682 CLOCK_CTRL_44MHZ_CORE);
2683 } else {
2684 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2685 }
2686
2687 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2688 tp->pci_clock_ctrl | newbits3, 40);
2689 }
2690 }
2691
2692 if (!(device_should_wake) &&
2693 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2694 tg3_power_down_phy(tp, do_low_power);
2695
2696 tg3_frob_aux_power(tp);
2697
2698 /* Workaround for unstable PLL clock */
2699 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2700 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2701 u32 val = tr32(0x7d00);
2702
2703 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2704 tw32(0x7d00, val);
2705 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2706 int err;
2707
2708 err = tg3_nvram_lock(tp);
2709 tg3_halt_cpu(tp, RX_CPU_BASE);
2710 if (!err)
2711 tg3_nvram_unlock(tp);
2712 }
2713 }
2714
2715 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2716
2717 if (device_should_wake)
2718 pci_enable_wake(tp->pdev, state, true);
2719
2720 /* Finally, set the new power state. */
2721 pci_set_power_state(tp->pdev, state);
2722
2723 return 0;
2724 }
2725
2726 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2727 {
2728 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2729 case MII_TG3_AUX_STAT_10HALF:
2730 *speed = SPEED_10;
2731 *duplex = DUPLEX_HALF;
2732 break;
2733
2734 case MII_TG3_AUX_STAT_10FULL:
2735 *speed = SPEED_10;
2736 *duplex = DUPLEX_FULL;
2737 break;
2738
2739 case MII_TG3_AUX_STAT_100HALF:
2740 *speed = SPEED_100;
2741 *duplex = DUPLEX_HALF;
2742 break;
2743
2744 case MII_TG3_AUX_STAT_100FULL:
2745 *speed = SPEED_100;
2746 *duplex = DUPLEX_FULL;
2747 break;
2748
2749 case MII_TG3_AUX_STAT_1000HALF:
2750 *speed = SPEED_1000;
2751 *duplex = DUPLEX_HALF;
2752 break;
2753
2754 case MII_TG3_AUX_STAT_1000FULL:
2755 *speed = SPEED_1000;
2756 *duplex = DUPLEX_FULL;
2757 break;
2758
2759 default:
2760 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2761 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2762 SPEED_10;
2763 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2764 DUPLEX_HALF;
2765 break;
2766 }
2767 *speed = SPEED_INVALID;
2768 *duplex = DUPLEX_INVALID;
2769 break;
2770 }
2771 }
2772
2773 static void tg3_phy_copper_begin(struct tg3 *tp)
2774 {
2775 u32 new_adv;
2776 int i;
2777
2778 if (tp->link_config.phy_is_low_power) {
2779 /* Entering low power mode. Disable gigabit and
2780 * 100baseT advertisements.
2781 */
2782 tg3_writephy(tp, MII_TG3_CTRL, 0);
2783
2784 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2785 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2786 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2787 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2788
2789 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2790 } else if (tp->link_config.speed == SPEED_INVALID) {
2791 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2792 tp->link_config.advertising &=
2793 ~(ADVERTISED_1000baseT_Half |
2794 ADVERTISED_1000baseT_Full);
2795
2796 new_adv = ADVERTISE_CSMA;
2797 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2798 new_adv |= ADVERTISE_10HALF;
2799 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2800 new_adv |= ADVERTISE_10FULL;
2801 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2802 new_adv |= ADVERTISE_100HALF;
2803 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2804 new_adv |= ADVERTISE_100FULL;
2805
2806 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2807
2808 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2809
2810 if (tp->link_config.advertising &
2811 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2812 new_adv = 0;
2813 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2814 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2815 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2816 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2817 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2818 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2819 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2820 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2821 MII_TG3_CTRL_ENABLE_AS_MASTER);
2822 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2823 } else {
2824 tg3_writephy(tp, MII_TG3_CTRL, 0);
2825 }
2826 } else {
2827 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2828 new_adv |= ADVERTISE_CSMA;
2829
2830 /* Asking for a specific link mode. */
2831 if (tp->link_config.speed == SPEED_1000) {
2832 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2833
2834 if (tp->link_config.duplex == DUPLEX_FULL)
2835 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2836 else
2837 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2838 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2839 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2840 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2841 MII_TG3_CTRL_ENABLE_AS_MASTER);
2842 } else {
2843 if (tp->link_config.speed == SPEED_100) {
2844 if (tp->link_config.duplex == DUPLEX_FULL)
2845 new_adv |= ADVERTISE_100FULL;
2846 else
2847 new_adv |= ADVERTISE_100HALF;
2848 } else {
2849 if (tp->link_config.duplex == DUPLEX_FULL)
2850 new_adv |= ADVERTISE_10FULL;
2851 else
2852 new_adv |= ADVERTISE_10HALF;
2853 }
2854 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2855
2856 new_adv = 0;
2857 }
2858
2859 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2860 }
2861
2862 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2863 tp->link_config.speed != SPEED_INVALID) {
2864 u32 bmcr, orig_bmcr;
2865
2866 tp->link_config.active_speed = tp->link_config.speed;
2867 tp->link_config.active_duplex = tp->link_config.duplex;
2868
2869 bmcr = 0;
2870 switch (tp->link_config.speed) {
2871 default:
2872 case SPEED_10:
2873 break;
2874
2875 case SPEED_100:
2876 bmcr |= BMCR_SPEED100;
2877 break;
2878
2879 case SPEED_1000:
2880 bmcr |= TG3_BMCR_SPEED1000;
2881 break;
2882 }
2883
2884 if (tp->link_config.duplex == DUPLEX_FULL)
2885 bmcr |= BMCR_FULLDPLX;
2886
2887 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2888 (bmcr != orig_bmcr)) {
2889 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2890 for (i = 0; i < 1500; i++) {
2891 u32 tmp;
2892
2893 udelay(10);
2894 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2895 tg3_readphy(tp, MII_BMSR, &tmp))
2896 continue;
2897 if (!(tmp & BMSR_LSTATUS)) {
2898 udelay(40);
2899 break;
2900 }
2901 }
2902 tg3_writephy(tp, MII_BMCR, bmcr);
2903 udelay(40);
2904 }
2905 } else {
2906 tg3_writephy(tp, MII_BMCR,
2907 BMCR_ANENABLE | BMCR_ANRESTART);
2908 }
2909 }
2910
2911 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2912 {
2913 int err;
2914
2915 /* Turn off tap power management. */
2916 /* Set Extended packet length bit */
2917 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2918
2919 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2920 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2921
2922 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2923 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2924
2925 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2926 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2927
2928 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2929 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2930
2931 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2932 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2933
2934 udelay(40);
2935
2936 return err;
2937 }
2938
2939 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2940 {
2941 u32 adv_reg, all_mask = 0;
2942
2943 if (mask & ADVERTISED_10baseT_Half)
2944 all_mask |= ADVERTISE_10HALF;
2945 if (mask & ADVERTISED_10baseT_Full)
2946 all_mask |= ADVERTISE_10FULL;
2947 if (mask & ADVERTISED_100baseT_Half)
2948 all_mask |= ADVERTISE_100HALF;
2949 if (mask & ADVERTISED_100baseT_Full)
2950 all_mask |= ADVERTISE_100FULL;
2951
2952 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2953 return 0;
2954
2955 if ((adv_reg & all_mask) != all_mask)
2956 return 0;
2957 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2958 u32 tg3_ctrl;
2959
2960 all_mask = 0;
2961 if (mask & ADVERTISED_1000baseT_Half)
2962 all_mask |= ADVERTISE_1000HALF;
2963 if (mask & ADVERTISED_1000baseT_Full)
2964 all_mask |= ADVERTISE_1000FULL;
2965
2966 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2967 return 0;
2968
2969 if ((tg3_ctrl & all_mask) != all_mask)
2970 return 0;
2971 }
2972 return 1;
2973 }
2974
2975 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2976 {
2977 u32 curadv, reqadv;
2978
2979 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2980 return 1;
2981
2982 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2983 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2984
2985 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2986 if (curadv != reqadv)
2987 return 0;
2988
2989 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2990 tg3_readphy(tp, MII_LPA, rmtadv);
2991 } else {
2992 /* Reprogram the advertisement register, even if it
2993 * does not affect the current link. If the link
2994 * gets renegotiated in the future, we can save an
2995 * additional renegotiation cycle by advertising
2996 * it correctly in the first place.
2997 */
2998 if (curadv != reqadv) {
2999 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3000 ADVERTISE_PAUSE_ASYM);
3001 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3002 }
3003 }
3004
3005 return 1;
3006 }
3007
3008 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3009 {
3010 int current_link_up;
3011 u32 bmsr, dummy;
3012 u32 lcl_adv, rmt_adv;
3013 u16 current_speed;
3014 u8 current_duplex;
3015 int i, err;
3016
3017 tw32(MAC_EVENT, 0);
3018
3019 tw32_f(MAC_STATUS,
3020 (MAC_STATUS_SYNC_CHANGED |
3021 MAC_STATUS_CFG_CHANGED |
3022 MAC_STATUS_MI_COMPLETION |
3023 MAC_STATUS_LNKSTATE_CHANGED));
3024 udelay(40);
3025
3026 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3027 tw32_f(MAC_MI_MODE,
3028 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3029 udelay(80);
3030 }
3031
3032 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3033
3034 /* Some third-party PHYs need to be reset on link going
3035 * down.
3036 */
3037 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3038 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3039 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3040 netif_carrier_ok(tp->dev)) {
3041 tg3_readphy(tp, MII_BMSR, &bmsr);
3042 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3043 !(bmsr & BMSR_LSTATUS))
3044 force_reset = 1;
3045 }
3046 if (force_reset)
3047 tg3_phy_reset(tp);
3048
3049 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3050 tg3_readphy(tp, MII_BMSR, &bmsr);
3051 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3052 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3053 bmsr = 0;
3054
3055 if (!(bmsr & BMSR_LSTATUS)) {
3056 err = tg3_init_5401phy_dsp(tp);
3057 if (err)
3058 return err;
3059
3060 tg3_readphy(tp, MII_BMSR, &bmsr);
3061 for (i = 0; i < 1000; i++) {
3062 udelay(10);
3063 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3064 (bmsr & BMSR_LSTATUS)) {
3065 udelay(40);
3066 break;
3067 }
3068 }
3069
3070 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3071 !(bmsr & BMSR_LSTATUS) &&
3072 tp->link_config.active_speed == SPEED_1000) {
3073 err = tg3_phy_reset(tp);
3074 if (!err)
3075 err = tg3_init_5401phy_dsp(tp);
3076 if (err)
3077 return err;
3078 }
3079 }
3080 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3081 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3082 /* 5701 {A0,B0} CRC bug workaround */
3083 tg3_writephy(tp, 0x15, 0x0a75);
3084 tg3_writephy(tp, 0x1c, 0x8c68);
3085 tg3_writephy(tp, 0x1c, 0x8d68);
3086 tg3_writephy(tp, 0x1c, 0x8c68);
3087 }
3088
3089 /* Clear pending interrupts... */
3090 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3091 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3092
3093 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3094 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3095 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3096 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3097
3098 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3099 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3100 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3101 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3102 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3103 else
3104 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3105 }
3106
3107 current_link_up = 0;
3108 current_speed = SPEED_INVALID;
3109 current_duplex = DUPLEX_INVALID;
3110
3111 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3112 u32 val;
3113
3114 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3115 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3116 if (!(val & (1 << 10))) {
3117 val |= (1 << 10);
3118 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3119 goto relink;
3120 }
3121 }
3122
3123 bmsr = 0;
3124 for (i = 0; i < 100; i++) {
3125 tg3_readphy(tp, MII_BMSR, &bmsr);
3126 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3127 (bmsr & BMSR_LSTATUS))
3128 break;
3129 udelay(40);
3130 }
3131
3132 if (bmsr & BMSR_LSTATUS) {
3133 u32 aux_stat, bmcr;
3134
3135 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3136 for (i = 0; i < 2000; i++) {
3137 udelay(10);
3138 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3139 aux_stat)
3140 break;
3141 }
3142
3143 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3144 &current_speed,
3145 &current_duplex);
3146
3147 bmcr = 0;
3148 for (i = 0; i < 200; i++) {
3149 tg3_readphy(tp, MII_BMCR, &bmcr);
3150 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3151 continue;
3152 if (bmcr && bmcr != 0x7fff)
3153 break;
3154 udelay(10);
3155 }
3156
3157 lcl_adv = 0;
3158 rmt_adv = 0;
3159
3160 tp->link_config.active_speed = current_speed;
3161 tp->link_config.active_duplex = current_duplex;
3162
3163 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3164 if ((bmcr & BMCR_ANENABLE) &&
3165 tg3_copper_is_advertising_all(tp,
3166 tp->link_config.advertising)) {
3167 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3168 &rmt_adv))
3169 current_link_up = 1;
3170 }
3171 } else {
3172 if (!(bmcr & BMCR_ANENABLE) &&
3173 tp->link_config.speed == current_speed &&
3174 tp->link_config.duplex == current_duplex &&
3175 tp->link_config.flowctrl ==
3176 tp->link_config.active_flowctrl) {
3177 current_link_up = 1;
3178 }
3179 }
3180
3181 if (current_link_up == 1 &&
3182 tp->link_config.active_duplex == DUPLEX_FULL)
3183 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3184 }
3185
3186 relink:
3187 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3188 u32 tmp;
3189
3190 tg3_phy_copper_begin(tp);
3191
3192 tg3_readphy(tp, MII_BMSR, &tmp);
3193 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3194 (tmp & BMSR_LSTATUS))
3195 current_link_up = 1;
3196 }
3197
3198 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3199 if (current_link_up == 1) {
3200 if (tp->link_config.active_speed == SPEED_100 ||
3201 tp->link_config.active_speed == SPEED_10)
3202 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3203 else
3204 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3205 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3206 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3207 else
3208 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3209
3210 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3211 if (tp->link_config.active_duplex == DUPLEX_HALF)
3212 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3213
3214 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3215 if (current_link_up == 1 &&
3216 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3217 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3218 else
3219 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3220 }
3221
3222 /* ??? Without this setting Netgear GA302T PHY does not
3223 * ??? send/receive packets...
3224 */
3225 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3226 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3227 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3228 tw32_f(MAC_MI_MODE, tp->mi_mode);
3229 udelay(80);
3230 }
3231
3232 tw32_f(MAC_MODE, tp->mac_mode);
3233 udelay(40);
3234
3235 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3236 /* Polled via timer. */
3237 tw32_f(MAC_EVENT, 0);
3238 } else {
3239 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3240 }
3241 udelay(40);
3242
3243 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3244 current_link_up == 1 &&
3245 tp->link_config.active_speed == SPEED_1000 &&
3246 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3247 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3248 udelay(120);
3249 tw32_f(MAC_STATUS,
3250 (MAC_STATUS_SYNC_CHANGED |
3251 MAC_STATUS_CFG_CHANGED));
3252 udelay(40);
3253 tg3_write_mem(tp,
3254 NIC_SRAM_FIRMWARE_MBOX,
3255 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3256 }
3257
3258 /* Prevent send BD corruption. */
3259 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3260 u16 oldlnkctl, newlnkctl;
3261
3262 pci_read_config_word(tp->pdev,
3263 tp->pcie_cap + PCI_EXP_LNKCTL,
3264 &oldlnkctl);
3265 if (tp->link_config.active_speed == SPEED_100 ||
3266 tp->link_config.active_speed == SPEED_10)
3267 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3268 else
3269 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3270 if (newlnkctl != oldlnkctl)
3271 pci_write_config_word(tp->pdev,
3272 tp->pcie_cap + PCI_EXP_LNKCTL,
3273 newlnkctl);
3274 }
3275
3276 if (current_link_up != netif_carrier_ok(tp->dev)) {
3277 if (current_link_up)
3278 netif_carrier_on(tp->dev);
3279 else
3280 netif_carrier_off(tp->dev);
3281 tg3_link_report(tp);
3282 }
3283
3284 return 0;
3285 }
3286
3287 struct tg3_fiber_aneginfo {
3288 int state;
3289 #define ANEG_STATE_UNKNOWN 0
3290 #define ANEG_STATE_AN_ENABLE 1
3291 #define ANEG_STATE_RESTART_INIT 2
3292 #define ANEG_STATE_RESTART 3
3293 #define ANEG_STATE_DISABLE_LINK_OK 4
3294 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3295 #define ANEG_STATE_ABILITY_DETECT 6
3296 #define ANEG_STATE_ACK_DETECT_INIT 7
3297 #define ANEG_STATE_ACK_DETECT 8
3298 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3299 #define ANEG_STATE_COMPLETE_ACK 10
3300 #define ANEG_STATE_IDLE_DETECT_INIT 11
3301 #define ANEG_STATE_IDLE_DETECT 12
3302 #define ANEG_STATE_LINK_OK 13
3303 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3304 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3305
3306 u32 flags;
3307 #define MR_AN_ENABLE 0x00000001
3308 #define MR_RESTART_AN 0x00000002
3309 #define MR_AN_COMPLETE 0x00000004
3310 #define MR_PAGE_RX 0x00000008
3311 #define MR_NP_LOADED 0x00000010
3312 #define MR_TOGGLE_TX 0x00000020
3313 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3314 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3315 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3316 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3317 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3318 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3319 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3320 #define MR_TOGGLE_RX 0x00002000
3321 #define MR_NP_RX 0x00004000
3322
3323 #define MR_LINK_OK 0x80000000
3324
3325 unsigned long link_time, cur_time;
3326
3327 u32 ability_match_cfg;
3328 int ability_match_count;
3329
3330 char ability_match, idle_match, ack_match;
3331
3332 u32 txconfig, rxconfig;
3333 #define ANEG_CFG_NP 0x00000080
3334 #define ANEG_CFG_ACK 0x00000040
3335 #define ANEG_CFG_RF2 0x00000020
3336 #define ANEG_CFG_RF1 0x00000010
3337 #define ANEG_CFG_PS2 0x00000001
3338 #define ANEG_CFG_PS1 0x00008000
3339 #define ANEG_CFG_HD 0x00004000
3340 #define ANEG_CFG_FD 0x00002000
3341 #define ANEG_CFG_INVAL 0x00001f06
3342
3343 };
3344 #define ANEG_OK 0
3345 #define ANEG_DONE 1
3346 #define ANEG_TIMER_ENAB 2
3347 #define ANEG_FAILED -1
3348
3349 #define ANEG_STATE_SETTLE_TIME 10000
3350
3351 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3352 struct tg3_fiber_aneginfo *ap)
3353 {
3354 u16 flowctrl;
3355 unsigned long delta;
3356 u32 rx_cfg_reg;
3357 int ret;
3358
3359 if (ap->state == ANEG_STATE_UNKNOWN) {
3360 ap->rxconfig = 0;
3361 ap->link_time = 0;
3362 ap->cur_time = 0;
3363 ap->ability_match_cfg = 0;
3364 ap->ability_match_count = 0;
3365 ap->ability_match = 0;
3366 ap->idle_match = 0;
3367 ap->ack_match = 0;
3368 }
3369 ap->cur_time++;
3370
3371 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3372 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3373
3374 if (rx_cfg_reg != ap->ability_match_cfg) {
3375 ap->ability_match_cfg = rx_cfg_reg;
3376 ap->ability_match = 0;
3377 ap->ability_match_count = 0;
3378 } else {
3379 if (++ap->ability_match_count > 1) {
3380 ap->ability_match = 1;
3381 ap->ability_match_cfg = rx_cfg_reg;
3382 }
3383 }
3384 if (rx_cfg_reg & ANEG_CFG_ACK)
3385 ap->ack_match = 1;
3386 else
3387 ap->ack_match = 0;
3388
3389 ap->idle_match = 0;
3390 } else {
3391 ap->idle_match = 1;
3392 ap->ability_match_cfg = 0;
3393 ap->ability_match_count = 0;
3394 ap->ability_match = 0;
3395 ap->ack_match = 0;
3396
3397 rx_cfg_reg = 0;
3398 }
3399
3400 ap->rxconfig = rx_cfg_reg;
3401 ret = ANEG_OK;
3402
3403 switch(ap->state) {
3404 case ANEG_STATE_UNKNOWN:
3405 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3406 ap->state = ANEG_STATE_AN_ENABLE;
3407
3408 /* fallthru */
3409 case ANEG_STATE_AN_ENABLE:
3410 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3411 if (ap->flags & MR_AN_ENABLE) {
3412 ap->link_time = 0;
3413 ap->cur_time = 0;
3414 ap->ability_match_cfg = 0;
3415 ap->ability_match_count = 0;
3416 ap->ability_match = 0;
3417 ap->idle_match = 0;
3418 ap->ack_match = 0;
3419
3420 ap->state = ANEG_STATE_RESTART_INIT;
3421 } else {
3422 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3423 }
3424 break;
3425
3426 case ANEG_STATE_RESTART_INIT:
3427 ap->link_time = ap->cur_time;
3428 ap->flags &= ~(MR_NP_LOADED);
3429 ap->txconfig = 0;
3430 tw32(MAC_TX_AUTO_NEG, 0);
3431 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3432 tw32_f(MAC_MODE, tp->mac_mode);
3433 udelay(40);
3434
3435 ret = ANEG_TIMER_ENAB;
3436 ap->state = ANEG_STATE_RESTART;
3437
3438 /* fallthru */
3439 case ANEG_STATE_RESTART:
3440 delta = ap->cur_time - ap->link_time;
3441 if (delta > ANEG_STATE_SETTLE_TIME) {
3442 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3443 } else {
3444 ret = ANEG_TIMER_ENAB;
3445 }
3446 break;
3447
3448 case ANEG_STATE_DISABLE_LINK_OK:
3449 ret = ANEG_DONE;
3450 break;
3451
3452 case ANEG_STATE_ABILITY_DETECT_INIT:
3453 ap->flags &= ~(MR_TOGGLE_TX);
3454 ap->txconfig = ANEG_CFG_FD;
3455 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3456 if (flowctrl & ADVERTISE_1000XPAUSE)
3457 ap->txconfig |= ANEG_CFG_PS1;
3458 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3459 ap->txconfig |= ANEG_CFG_PS2;
3460 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3461 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3462 tw32_f(MAC_MODE, tp->mac_mode);
3463 udelay(40);
3464
3465 ap->state = ANEG_STATE_ABILITY_DETECT;
3466 break;
3467
3468 case ANEG_STATE_ABILITY_DETECT:
3469 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3470 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3471 }
3472 break;
3473
3474 case ANEG_STATE_ACK_DETECT_INIT:
3475 ap->txconfig |= ANEG_CFG_ACK;
3476 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3477 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3478 tw32_f(MAC_MODE, tp->mac_mode);
3479 udelay(40);
3480
3481 ap->state = ANEG_STATE_ACK_DETECT;
3482
3483 /* fallthru */
3484 case ANEG_STATE_ACK_DETECT:
3485 if (ap->ack_match != 0) {
3486 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3487 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3488 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3489 } else {
3490 ap->state = ANEG_STATE_AN_ENABLE;
3491 }
3492 } else if (ap->ability_match != 0 &&
3493 ap->rxconfig == 0) {
3494 ap->state = ANEG_STATE_AN_ENABLE;
3495 }
3496 break;
3497
3498 case ANEG_STATE_COMPLETE_ACK_INIT:
3499 if (ap->rxconfig & ANEG_CFG_INVAL) {
3500 ret = ANEG_FAILED;
3501 break;
3502 }
3503 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3504 MR_LP_ADV_HALF_DUPLEX |
3505 MR_LP_ADV_SYM_PAUSE |
3506 MR_LP_ADV_ASYM_PAUSE |
3507 MR_LP_ADV_REMOTE_FAULT1 |
3508 MR_LP_ADV_REMOTE_FAULT2 |
3509 MR_LP_ADV_NEXT_PAGE |
3510 MR_TOGGLE_RX |
3511 MR_NP_RX);
3512 if (ap->rxconfig & ANEG_CFG_FD)
3513 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3514 if (ap->rxconfig & ANEG_CFG_HD)
3515 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3516 if (ap->rxconfig & ANEG_CFG_PS1)
3517 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3518 if (ap->rxconfig & ANEG_CFG_PS2)
3519 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3520 if (ap->rxconfig & ANEG_CFG_RF1)
3521 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3522 if (ap->rxconfig & ANEG_CFG_RF2)
3523 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3524 if (ap->rxconfig & ANEG_CFG_NP)
3525 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3526
3527 ap->link_time = ap->cur_time;
3528
3529 ap->flags ^= (MR_TOGGLE_TX);
3530 if (ap->rxconfig & 0x0008)
3531 ap->flags |= MR_TOGGLE_RX;
3532 if (ap->rxconfig & ANEG_CFG_NP)
3533 ap->flags |= MR_NP_RX;
3534 ap->flags |= MR_PAGE_RX;
3535
3536 ap->state = ANEG_STATE_COMPLETE_ACK;
3537 ret = ANEG_TIMER_ENAB;
3538 break;
3539
3540 case ANEG_STATE_COMPLETE_ACK:
3541 if (ap->ability_match != 0 &&
3542 ap->rxconfig == 0) {
3543 ap->state = ANEG_STATE_AN_ENABLE;
3544 break;
3545 }
3546 delta = ap->cur_time - ap->link_time;
3547 if (delta > ANEG_STATE_SETTLE_TIME) {
3548 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3549 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3550 } else {
3551 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3552 !(ap->flags & MR_NP_RX)) {
3553 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3554 } else {
3555 ret = ANEG_FAILED;
3556 }
3557 }
3558 }
3559 break;
3560
3561 case ANEG_STATE_IDLE_DETECT_INIT:
3562 ap->link_time = ap->cur_time;
3563 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3564 tw32_f(MAC_MODE, tp->mac_mode);
3565 udelay(40);
3566
3567 ap->state = ANEG_STATE_IDLE_DETECT;
3568 ret = ANEG_TIMER_ENAB;
3569 break;
3570
3571 case ANEG_STATE_IDLE_DETECT:
3572 if (ap->ability_match != 0 &&
3573 ap->rxconfig == 0) {
3574 ap->state = ANEG_STATE_AN_ENABLE;
3575 break;
3576 }
3577 delta = ap->cur_time - ap->link_time;
3578 if (delta > ANEG_STATE_SETTLE_TIME) {
3579 /* XXX another gem from the Broadcom driver :( */
3580 ap->state = ANEG_STATE_LINK_OK;
3581 }
3582 break;
3583
3584 case ANEG_STATE_LINK_OK:
3585 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3586 ret = ANEG_DONE;
3587 break;
3588
3589 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3590 /* ??? unimplemented */
3591 break;
3592
3593 case ANEG_STATE_NEXT_PAGE_WAIT:
3594 /* ??? unimplemented */
3595 break;
3596
3597 default:
3598 ret = ANEG_FAILED;
3599 break;
3600 }
3601
3602 return ret;
3603 }
3604
3605 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3606 {
3607 int res = 0;
3608 struct tg3_fiber_aneginfo aninfo;
3609 int status = ANEG_FAILED;
3610 unsigned int tick;
3611 u32 tmp;
3612
3613 tw32_f(MAC_TX_AUTO_NEG, 0);
3614
3615 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3616 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3617 udelay(40);
3618
3619 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3620 udelay(40);
3621
3622 memset(&aninfo, 0, sizeof(aninfo));
3623 aninfo.flags |= MR_AN_ENABLE;
3624 aninfo.state = ANEG_STATE_UNKNOWN;
3625 aninfo.cur_time = 0;
3626 tick = 0;
3627 while (++tick < 195000) {
3628 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3629 if (status == ANEG_DONE || status == ANEG_FAILED)
3630 break;
3631
3632 udelay(1);
3633 }
3634
3635 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3636 tw32_f(MAC_MODE, tp->mac_mode);
3637 udelay(40);
3638
3639 *txflags = aninfo.txconfig;
3640 *rxflags = aninfo.flags;
3641
3642 if (status == ANEG_DONE &&
3643 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3644 MR_LP_ADV_FULL_DUPLEX)))
3645 res = 1;
3646
3647 return res;
3648 }
3649
3650 static void tg3_init_bcm8002(struct tg3 *tp)
3651 {
3652 u32 mac_status = tr32(MAC_STATUS);
3653 int i;
3654
3655 /* Reset when initting first time or we have a link. */
3656 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3657 !(mac_status & MAC_STATUS_PCS_SYNCED))
3658 return;
3659
3660 /* Set PLL lock range. */
3661 tg3_writephy(tp, 0x16, 0x8007);
3662
3663 /* SW reset */
3664 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3665
3666 /* Wait for reset to complete. */
3667 /* XXX schedule_timeout() ... */
3668 for (i = 0; i < 500; i++)
3669 udelay(10);
3670
3671 /* Config mode; select PMA/Ch 1 regs. */
3672 tg3_writephy(tp, 0x10, 0x8411);
3673
3674 /* Enable auto-lock and comdet, select txclk for tx. */
3675 tg3_writephy(tp, 0x11, 0x0a10);
3676
3677 tg3_writephy(tp, 0x18, 0x00a0);
3678 tg3_writephy(tp, 0x16, 0x41ff);
3679
3680 /* Assert and deassert POR. */
3681 tg3_writephy(tp, 0x13, 0x0400);
3682 udelay(40);
3683 tg3_writephy(tp, 0x13, 0x0000);
3684
3685 tg3_writephy(tp, 0x11, 0x0a50);
3686 udelay(40);
3687 tg3_writephy(tp, 0x11, 0x0a10);
3688
3689 /* Wait for signal to stabilize */
3690 /* XXX schedule_timeout() ... */
3691 for (i = 0; i < 15000; i++)
3692 udelay(10);
3693
3694 /* Deselect the channel register so we can read the PHYID
3695 * later.
3696 */
3697 tg3_writephy(tp, 0x10, 0x8011);
3698 }
3699
3700 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3701 {
3702 u16 flowctrl;
3703 u32 sg_dig_ctrl, sg_dig_status;
3704 u32 serdes_cfg, expected_sg_dig_ctrl;
3705 int workaround, port_a;
3706 int current_link_up;
3707
3708 serdes_cfg = 0;
3709 expected_sg_dig_ctrl = 0;
3710 workaround = 0;
3711 port_a = 1;
3712 current_link_up = 0;
3713
3714 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3715 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3716 workaround = 1;
3717 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3718 port_a = 0;
3719
3720 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3721 /* preserve bits 20-23 for voltage regulator */
3722 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3723 }
3724
3725 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3726
3727 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3728 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3729 if (workaround) {
3730 u32 val = serdes_cfg;
3731
3732 if (port_a)
3733 val |= 0xc010000;
3734 else
3735 val |= 0x4010000;
3736 tw32_f(MAC_SERDES_CFG, val);
3737 }
3738
3739 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3740 }
3741 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3742 tg3_setup_flow_control(tp, 0, 0);
3743 current_link_up = 1;
3744 }
3745 goto out;
3746 }
3747
3748 /* Want auto-negotiation. */
3749 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3750
3751 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3752 if (flowctrl & ADVERTISE_1000XPAUSE)
3753 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3754 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3755 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3756
3757 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3758 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3759 tp->serdes_counter &&
3760 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3761 MAC_STATUS_RCVD_CFG)) ==
3762 MAC_STATUS_PCS_SYNCED)) {
3763 tp->serdes_counter--;
3764 current_link_up = 1;
3765 goto out;
3766 }
3767 restart_autoneg:
3768 if (workaround)
3769 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3770 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3771 udelay(5);
3772 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3773
3774 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3775 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3776 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3777 MAC_STATUS_SIGNAL_DET)) {
3778 sg_dig_status = tr32(SG_DIG_STATUS);
3779 mac_status = tr32(MAC_STATUS);
3780
3781 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3782 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3783 u32 local_adv = 0, remote_adv = 0;
3784
3785 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3786 local_adv |= ADVERTISE_1000XPAUSE;
3787 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3788 local_adv |= ADVERTISE_1000XPSE_ASYM;
3789
3790 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3791 remote_adv |= LPA_1000XPAUSE;
3792 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3793 remote_adv |= LPA_1000XPAUSE_ASYM;
3794
3795 tg3_setup_flow_control(tp, local_adv, remote_adv);
3796 current_link_up = 1;
3797 tp->serdes_counter = 0;
3798 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3799 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3800 if (tp->serdes_counter)
3801 tp->serdes_counter--;
3802 else {
3803 if (workaround) {
3804 u32 val = serdes_cfg;
3805
3806 if (port_a)
3807 val |= 0xc010000;
3808 else
3809 val |= 0x4010000;
3810
3811 tw32_f(MAC_SERDES_CFG, val);
3812 }
3813
3814 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3815 udelay(40);
3816
3817 /* Link parallel detection - link is up */
3818 /* only if we have PCS_SYNC and not */
3819 /* receiving config code words */
3820 mac_status = tr32(MAC_STATUS);
3821 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3822 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3823 tg3_setup_flow_control(tp, 0, 0);
3824 current_link_up = 1;
3825 tp->tg3_flags2 |=
3826 TG3_FLG2_PARALLEL_DETECT;
3827 tp->serdes_counter =
3828 SERDES_PARALLEL_DET_TIMEOUT;
3829 } else
3830 goto restart_autoneg;
3831 }
3832 }
3833 } else {
3834 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3835 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3836 }
3837
3838 out:
3839 return current_link_up;
3840 }
3841
3842 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3843 {
3844 int current_link_up = 0;
3845
3846 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3847 goto out;
3848
3849 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3850 u32 txflags, rxflags;
3851 int i;
3852
3853 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3854 u32 local_adv = 0, remote_adv = 0;
3855
3856 if (txflags & ANEG_CFG_PS1)
3857 local_adv |= ADVERTISE_1000XPAUSE;
3858 if (txflags & ANEG_CFG_PS2)
3859 local_adv |= ADVERTISE_1000XPSE_ASYM;
3860
3861 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3862 remote_adv |= LPA_1000XPAUSE;
3863 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3864 remote_adv |= LPA_1000XPAUSE_ASYM;
3865
3866 tg3_setup_flow_control(tp, local_adv, remote_adv);
3867
3868 current_link_up = 1;
3869 }
3870 for (i = 0; i < 30; i++) {
3871 udelay(20);
3872 tw32_f(MAC_STATUS,
3873 (MAC_STATUS_SYNC_CHANGED |
3874 MAC_STATUS_CFG_CHANGED));
3875 udelay(40);
3876 if ((tr32(MAC_STATUS) &
3877 (MAC_STATUS_SYNC_CHANGED |
3878 MAC_STATUS_CFG_CHANGED)) == 0)
3879 break;
3880 }
3881
3882 mac_status = tr32(MAC_STATUS);
3883 if (current_link_up == 0 &&
3884 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3885 !(mac_status & MAC_STATUS_RCVD_CFG))
3886 current_link_up = 1;
3887 } else {
3888 tg3_setup_flow_control(tp, 0, 0);
3889
3890 /* Forcing 1000FD link up. */
3891 current_link_up = 1;
3892
3893 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3894 udelay(40);
3895
3896 tw32_f(MAC_MODE, tp->mac_mode);
3897 udelay(40);
3898 }
3899
3900 out:
3901 return current_link_up;
3902 }
3903
3904 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3905 {
3906 u32 orig_pause_cfg;
3907 u16 orig_active_speed;
3908 u8 orig_active_duplex;
3909 u32 mac_status;
3910 int current_link_up;
3911 int i;
3912
3913 orig_pause_cfg = tp->link_config.active_flowctrl;
3914 orig_active_speed = tp->link_config.active_speed;
3915 orig_active_duplex = tp->link_config.active_duplex;
3916
3917 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3918 netif_carrier_ok(tp->dev) &&
3919 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3920 mac_status = tr32(MAC_STATUS);
3921 mac_status &= (MAC_STATUS_PCS_SYNCED |
3922 MAC_STATUS_SIGNAL_DET |
3923 MAC_STATUS_CFG_CHANGED |
3924 MAC_STATUS_RCVD_CFG);
3925 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3926 MAC_STATUS_SIGNAL_DET)) {
3927 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3928 MAC_STATUS_CFG_CHANGED));
3929 return 0;
3930 }
3931 }
3932
3933 tw32_f(MAC_TX_AUTO_NEG, 0);
3934
3935 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3936 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3937 tw32_f(MAC_MODE, tp->mac_mode);
3938 udelay(40);
3939
3940 if (tp->phy_id == PHY_ID_BCM8002)
3941 tg3_init_bcm8002(tp);
3942
3943 /* Enable link change event even when serdes polling. */
3944 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3945 udelay(40);
3946
3947 current_link_up = 0;
3948 mac_status = tr32(MAC_STATUS);
3949
3950 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3951 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3952 else
3953 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3954
3955 tp->napi[0].hw_status->status =
3956 (SD_STATUS_UPDATED |
3957 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3958
3959 for (i = 0; i < 100; i++) {
3960 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3961 MAC_STATUS_CFG_CHANGED));
3962 udelay(5);
3963 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3964 MAC_STATUS_CFG_CHANGED |
3965 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3966 break;
3967 }
3968
3969 mac_status = tr32(MAC_STATUS);
3970 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3971 current_link_up = 0;
3972 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3973 tp->serdes_counter == 0) {
3974 tw32_f(MAC_MODE, (tp->mac_mode |
3975 MAC_MODE_SEND_CONFIGS));
3976 udelay(1);
3977 tw32_f(MAC_MODE, tp->mac_mode);
3978 }
3979 }
3980
3981 if (current_link_up == 1) {
3982 tp->link_config.active_speed = SPEED_1000;
3983 tp->link_config.active_duplex = DUPLEX_FULL;
3984 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3985 LED_CTRL_LNKLED_OVERRIDE |
3986 LED_CTRL_1000MBPS_ON));
3987 } else {
3988 tp->link_config.active_speed = SPEED_INVALID;
3989 tp->link_config.active_duplex = DUPLEX_INVALID;
3990 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3991 LED_CTRL_LNKLED_OVERRIDE |
3992 LED_CTRL_TRAFFIC_OVERRIDE));
3993 }
3994
3995 if (current_link_up != netif_carrier_ok(tp->dev)) {
3996 if (current_link_up)
3997 netif_carrier_on(tp->dev);
3998 else
3999 netif_carrier_off(tp->dev);
4000 tg3_link_report(tp);
4001 } else {
4002 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4003 if (orig_pause_cfg != now_pause_cfg ||
4004 orig_active_speed != tp->link_config.active_speed ||
4005 orig_active_duplex != tp->link_config.active_duplex)
4006 tg3_link_report(tp);
4007 }
4008
4009 return 0;
4010 }
4011
4012 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4013 {
4014 int current_link_up, err = 0;
4015 u32 bmsr, bmcr;
4016 u16 current_speed;
4017 u8 current_duplex;
4018 u32 local_adv, remote_adv;
4019
4020 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4021 tw32_f(MAC_MODE, tp->mac_mode);
4022 udelay(40);
4023
4024 tw32(MAC_EVENT, 0);
4025
4026 tw32_f(MAC_STATUS,
4027 (MAC_STATUS_SYNC_CHANGED |
4028 MAC_STATUS_CFG_CHANGED |
4029 MAC_STATUS_MI_COMPLETION |
4030 MAC_STATUS_LNKSTATE_CHANGED));
4031 udelay(40);
4032
4033 if (force_reset)
4034 tg3_phy_reset(tp);
4035
4036 current_link_up = 0;
4037 current_speed = SPEED_INVALID;
4038 current_duplex = DUPLEX_INVALID;
4039
4040 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4041 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4042 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4043 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4044 bmsr |= BMSR_LSTATUS;
4045 else
4046 bmsr &= ~BMSR_LSTATUS;
4047 }
4048
4049 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4050
4051 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4052 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4053 /* do nothing, just check for link up at the end */
4054 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4055 u32 adv, new_adv;
4056
4057 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4058 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4059 ADVERTISE_1000XPAUSE |
4060 ADVERTISE_1000XPSE_ASYM |
4061 ADVERTISE_SLCT);
4062
4063 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4064
4065 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4066 new_adv |= ADVERTISE_1000XHALF;
4067 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4068 new_adv |= ADVERTISE_1000XFULL;
4069
4070 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4071 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4072 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4073 tg3_writephy(tp, MII_BMCR, bmcr);
4074
4075 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4076 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4077 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4078
4079 return err;
4080 }
4081 } else {
4082 u32 new_bmcr;
4083
4084 bmcr &= ~BMCR_SPEED1000;
4085 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4086
4087 if (tp->link_config.duplex == DUPLEX_FULL)
4088 new_bmcr |= BMCR_FULLDPLX;
4089
4090 if (new_bmcr != bmcr) {
4091 /* BMCR_SPEED1000 is a reserved bit that needs
4092 * to be set on write.
4093 */
4094 new_bmcr |= BMCR_SPEED1000;
4095
4096 /* Force a linkdown */
4097 if (netif_carrier_ok(tp->dev)) {
4098 u32 adv;
4099
4100 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4101 adv &= ~(ADVERTISE_1000XFULL |
4102 ADVERTISE_1000XHALF |
4103 ADVERTISE_SLCT);
4104 tg3_writephy(tp, MII_ADVERTISE, adv);
4105 tg3_writephy(tp, MII_BMCR, bmcr |
4106 BMCR_ANRESTART |
4107 BMCR_ANENABLE);
4108 udelay(10);
4109 netif_carrier_off(tp->dev);
4110 }
4111 tg3_writephy(tp, MII_BMCR, new_bmcr);
4112 bmcr = new_bmcr;
4113 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4114 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4115 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4116 ASIC_REV_5714) {
4117 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4118 bmsr |= BMSR_LSTATUS;
4119 else
4120 bmsr &= ~BMSR_LSTATUS;
4121 }
4122 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4123 }
4124 }
4125
4126 if (bmsr & BMSR_LSTATUS) {
4127 current_speed = SPEED_1000;
4128 current_link_up = 1;
4129 if (bmcr & BMCR_FULLDPLX)
4130 current_duplex = DUPLEX_FULL;
4131 else
4132 current_duplex = DUPLEX_HALF;
4133
4134 local_adv = 0;
4135 remote_adv = 0;
4136
4137 if (bmcr & BMCR_ANENABLE) {
4138 u32 common;
4139
4140 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4141 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4142 common = local_adv & remote_adv;
4143 if (common & (ADVERTISE_1000XHALF |
4144 ADVERTISE_1000XFULL)) {
4145 if (common & ADVERTISE_1000XFULL)
4146 current_duplex = DUPLEX_FULL;
4147 else
4148 current_duplex = DUPLEX_HALF;
4149 }
4150 else
4151 current_link_up = 0;
4152 }
4153 }
4154
4155 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4156 tg3_setup_flow_control(tp, local_adv, remote_adv);
4157
4158 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4159 if (tp->link_config.active_duplex == DUPLEX_HALF)
4160 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4161
4162 tw32_f(MAC_MODE, tp->mac_mode);
4163 udelay(40);
4164
4165 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4166
4167 tp->link_config.active_speed = current_speed;
4168 tp->link_config.active_duplex = current_duplex;
4169
4170 if (current_link_up != netif_carrier_ok(tp->dev)) {
4171 if (current_link_up)
4172 netif_carrier_on(tp->dev);
4173 else {
4174 netif_carrier_off(tp->dev);
4175 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4176 }
4177 tg3_link_report(tp);
4178 }
4179 return err;
4180 }
4181
4182 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4183 {
4184 if (tp->serdes_counter) {
4185 /* Give autoneg time to complete. */
4186 tp->serdes_counter--;
4187 return;
4188 }
4189 if (!netif_carrier_ok(tp->dev) &&
4190 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4191 u32 bmcr;
4192
4193 tg3_readphy(tp, MII_BMCR, &bmcr);
4194 if (bmcr & BMCR_ANENABLE) {
4195 u32 phy1, phy2;
4196
4197 /* Select shadow register 0x1f */
4198 tg3_writephy(tp, 0x1c, 0x7c00);
4199 tg3_readphy(tp, 0x1c, &phy1);
4200
4201 /* Select expansion interrupt status register */
4202 tg3_writephy(tp, 0x17, 0x0f01);
4203 tg3_readphy(tp, 0x15, &phy2);
4204 tg3_readphy(tp, 0x15, &phy2);
4205
4206 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4207 /* We have signal detect and not receiving
4208 * config code words, link is up by parallel
4209 * detection.
4210 */
4211
4212 bmcr &= ~BMCR_ANENABLE;
4213 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4214 tg3_writephy(tp, MII_BMCR, bmcr);
4215 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4216 }
4217 }
4218 }
4219 else if (netif_carrier_ok(tp->dev) &&
4220 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4221 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4222 u32 phy2;
4223
4224 /* Select expansion interrupt status register */
4225 tg3_writephy(tp, 0x17, 0x0f01);
4226 tg3_readphy(tp, 0x15, &phy2);
4227 if (phy2 & 0x20) {
4228 u32 bmcr;
4229
4230 /* Config code words received, turn on autoneg. */
4231 tg3_readphy(tp, MII_BMCR, &bmcr);
4232 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4233
4234 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4235
4236 }
4237 }
4238 }
4239
4240 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4241 {
4242 int err;
4243
4244 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4245 err = tg3_setup_fiber_phy(tp, force_reset);
4246 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4247 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4248 } else {
4249 err = tg3_setup_copper_phy(tp, force_reset);
4250 }
4251
4252 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4253 u32 val, scale;
4254
4255 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4256 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4257 scale = 65;
4258 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4259 scale = 6;
4260 else
4261 scale = 12;
4262
4263 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4264 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4265 tw32(GRC_MISC_CFG, val);
4266 }
4267
4268 if (tp->link_config.active_speed == SPEED_1000 &&
4269 tp->link_config.active_duplex == DUPLEX_HALF)
4270 tw32(MAC_TX_LENGTHS,
4271 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4272 (6 << TX_LENGTHS_IPG_SHIFT) |
4273 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4274 else
4275 tw32(MAC_TX_LENGTHS,
4276 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4277 (6 << TX_LENGTHS_IPG_SHIFT) |
4278 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4279
4280 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4281 if (netif_carrier_ok(tp->dev)) {
4282 tw32(HOSTCC_STAT_COAL_TICKS,
4283 tp->coal.stats_block_coalesce_usecs);
4284 } else {
4285 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4286 }
4287 }
4288
4289 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4290 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4291 if (!netif_carrier_ok(tp->dev))
4292 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4293 tp->pwrmgmt_thresh;
4294 else
4295 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4296 tw32(PCIE_PWR_MGMT_THRESH, val);
4297 }
4298
4299 return err;
4300 }
4301
4302 /* This is called whenever we suspect that the system chipset is re-
4303 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4304 * is bogus tx completions. We try to recover by setting the
4305 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4306 * in the workqueue.
4307 */
4308 static void tg3_tx_recover(struct tg3 *tp)
4309 {
4310 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4311 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4312
4313 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4314 "mapped I/O cycles to the network device, attempting to "
4315 "recover. Please report the problem to the driver maintainer "
4316 "and include system chipset information.\n", tp->dev->name);
4317
4318 spin_lock(&tp->lock);
4319 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4320 spin_unlock(&tp->lock);
4321 }
4322
4323 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4324 {
4325 smp_mb();
4326 return tnapi->tx_pending -
4327 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4328 }
4329
4330 /* Tigon3 never reports partial packet sends. So we do not
4331 * need special logic to handle SKBs that have not had all
4332 * of their frags sent yet, like SunGEM does.
4333 */
4334 static void tg3_tx(struct tg3_napi *tnapi)
4335 {
4336 struct tg3 *tp = tnapi->tp;
4337 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4338 u32 sw_idx = tnapi->tx_cons;
4339 struct netdev_queue *txq;
4340 int index = tnapi - tp->napi;
4341
4342 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4343 index--;
4344
4345 txq = netdev_get_tx_queue(tp->dev, index);
4346
4347 while (sw_idx != hw_idx) {
4348 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
4349 struct sk_buff *skb = ri->skb;
4350 int i, tx_bug = 0;
4351
4352 if (unlikely(skb == NULL)) {
4353 tg3_tx_recover(tp);
4354 return;
4355 }
4356
4357 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4358
4359 ri->skb = NULL;
4360
4361 sw_idx = NEXT_TX(sw_idx);
4362
4363 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4364 ri = &tnapi->tx_buffers[sw_idx];
4365 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4366 tx_bug = 1;
4367 sw_idx = NEXT_TX(sw_idx);
4368 }
4369
4370 dev_kfree_skb(skb);
4371
4372 if (unlikely(tx_bug)) {
4373 tg3_tx_recover(tp);
4374 return;
4375 }
4376 }
4377
4378 tnapi->tx_cons = sw_idx;
4379
4380 /* Need to make the tx_cons update visible to tg3_start_xmit()
4381 * before checking for netif_queue_stopped(). Without the
4382 * memory barrier, there is a small possibility that tg3_start_xmit()
4383 * will miss it and cause the queue to be stopped forever.
4384 */
4385 smp_mb();
4386
4387 if (unlikely(netif_tx_queue_stopped(txq) &&
4388 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4389 __netif_tx_lock(txq, smp_processor_id());
4390 if (netif_tx_queue_stopped(txq) &&
4391 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4392 netif_tx_wake_queue(txq);
4393 __netif_tx_unlock(txq);
4394 }
4395 }
4396
4397 /* Returns size of skb allocated or < 0 on error.
4398 *
4399 * We only need to fill in the address because the other members
4400 * of the RX descriptor are invariant, see tg3_init_rings.
4401 *
4402 * Note the purposeful assymetry of cpu vs. chip accesses. For
4403 * posting buffers we only dirty the first cache line of the RX
4404 * descriptor (containing the address). Whereas for the RX status
4405 * buffers the cpu only reads the last cacheline of the RX descriptor
4406 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4407 */
4408 static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
4409 int src_idx, u32 dest_idx_unmasked)
4410 {
4411 struct tg3 *tp = tnapi->tp;
4412 struct tg3_rx_buffer_desc *desc;
4413 struct ring_info *map, *src_map;
4414 struct sk_buff *skb;
4415 dma_addr_t mapping;
4416 int skb_size, dest_idx;
4417 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4418
4419 src_map = NULL;
4420 switch (opaque_key) {
4421 case RXD_OPAQUE_RING_STD:
4422 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4423 desc = &tpr->rx_std[dest_idx];
4424 map = &tpr->rx_std_buffers[dest_idx];
4425 if (src_idx >= 0)
4426 src_map = &tpr->rx_std_buffers[src_idx];
4427 skb_size = tp->rx_pkt_map_sz;
4428 break;
4429
4430 case RXD_OPAQUE_RING_JUMBO:
4431 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4432 desc = &tpr->rx_jmb[dest_idx].std;
4433 map = &tpr->rx_jmb_buffers[dest_idx];
4434 if (src_idx >= 0)
4435 src_map = &tpr->rx_jmb_buffers[src_idx];
4436 skb_size = TG3_RX_JMB_MAP_SZ;
4437 break;
4438
4439 default:
4440 return -EINVAL;
4441 }
4442
4443 /* Do not overwrite any of the map or rp information
4444 * until we are sure we can commit to a new buffer.
4445 *
4446 * Callers depend upon this behavior and assume that
4447 * we leave everything unchanged if we fail.
4448 */
4449 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4450 if (skb == NULL)
4451 return -ENOMEM;
4452
4453 skb_reserve(skb, tp->rx_offset);
4454
4455 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4456 PCI_DMA_FROMDEVICE);
4457 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4458 dev_kfree_skb(skb);
4459 return -EIO;
4460 }
4461
4462 map->skb = skb;
4463 pci_unmap_addr_set(map, mapping, mapping);
4464
4465 if (src_map != NULL)
4466 src_map->skb = NULL;
4467
4468 desc->addr_hi = ((u64)mapping >> 32);
4469 desc->addr_lo = ((u64)mapping & 0xffffffff);
4470
4471 return skb_size;
4472 }
4473
4474 /* We only need to move over in the address because the other
4475 * members of the RX descriptor are invariant. See notes above
4476 * tg3_alloc_rx_skb for full details.
4477 */
4478 static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key,
4479 int src_idx, u32 dest_idx_unmasked)
4480 {
4481 struct tg3 *tp = tnapi->tp;
4482 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4483 struct ring_info *src_map, *dest_map;
4484 int dest_idx;
4485 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4486
4487 switch (opaque_key) {
4488 case RXD_OPAQUE_RING_STD:
4489 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4490 dest_desc = &tpr->rx_std[dest_idx];
4491 dest_map = &tpr->rx_std_buffers[dest_idx];
4492 src_desc = &tpr->rx_std[src_idx];
4493 src_map = &tpr->rx_std_buffers[src_idx];
4494 break;
4495
4496 case RXD_OPAQUE_RING_JUMBO:
4497 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4498 dest_desc = &tpr->rx_jmb[dest_idx].std;
4499 dest_map = &tpr->rx_jmb_buffers[dest_idx];
4500 src_desc = &tpr->rx_jmb[src_idx].std;
4501 src_map = &tpr->rx_jmb_buffers[src_idx];
4502 break;
4503
4504 default:
4505 return;
4506 }
4507
4508 dest_map->skb = src_map->skb;
4509 pci_unmap_addr_set(dest_map, mapping,
4510 pci_unmap_addr(src_map, mapping));
4511 dest_desc->addr_hi = src_desc->addr_hi;
4512 dest_desc->addr_lo = src_desc->addr_lo;
4513
4514 src_map->skb = NULL;
4515 }
4516
4517 /* The RX ring scheme is composed of multiple rings which post fresh
4518 * buffers to the chip, and one special ring the chip uses to report
4519 * status back to the host.
4520 *
4521 * The special ring reports the status of received packets to the
4522 * host. The chip does not write into the original descriptor the
4523 * RX buffer was obtained from. The chip simply takes the original
4524 * descriptor as provided by the host, updates the status and length
4525 * field, then writes this into the next status ring entry.
4526 *
4527 * Each ring the host uses to post buffers to the chip is described
4528 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4529 * it is first placed into the on-chip ram. When the packet's length
4530 * is known, it walks down the TG3_BDINFO entries to select the ring.
4531 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4532 * which is within the range of the new packet's length is chosen.
4533 *
4534 * The "separate ring for rx status" scheme may sound queer, but it makes
4535 * sense from a cache coherency perspective. If only the host writes
4536 * to the buffer post rings, and only the chip writes to the rx status
4537 * rings, then cache lines never move beyond shared-modified state.
4538 * If both the host and chip were to write into the same ring, cache line
4539 * eviction could occur since both entities want it in an exclusive state.
4540 */
4541 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4542 {
4543 struct tg3 *tp = tnapi->tp;
4544 u32 work_mask, rx_std_posted = 0;
4545 u32 sw_idx = tnapi->rx_rcb_ptr;
4546 u16 hw_idx;
4547 int received;
4548 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4549
4550 hw_idx = *(tnapi->rx_rcb_prod_idx);
4551 /*
4552 * We need to order the read of hw_idx and the read of
4553 * the opaque cookie.
4554 */
4555 rmb();
4556 work_mask = 0;
4557 received = 0;
4558 while (sw_idx != hw_idx && budget > 0) {
4559 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4560 unsigned int len;
4561 struct sk_buff *skb;
4562 dma_addr_t dma_addr;
4563 u32 opaque_key, desc_idx, *post_ptr;
4564
4565 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4566 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4567 if (opaque_key == RXD_OPAQUE_RING_STD) {
4568 struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4569 dma_addr = pci_unmap_addr(ri, mapping);
4570 skb = ri->skb;
4571 post_ptr = &tpr->rx_std_ptr;
4572 rx_std_posted++;
4573 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4574 struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4575 dma_addr = pci_unmap_addr(ri, mapping);
4576 skb = ri->skb;
4577 post_ptr = &tpr->rx_jmb_ptr;
4578 } else
4579 goto next_pkt_nopost;
4580
4581 work_mask |= opaque_key;
4582
4583 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4584 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4585 drop_it:
4586 tg3_recycle_rx(tnapi, opaque_key,
4587 desc_idx, *post_ptr);
4588 drop_it_no_recycle:
4589 /* Other statistics kept track of by card. */
4590 tp->net_stats.rx_dropped++;
4591 goto next_pkt;
4592 }
4593
4594 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4595 ETH_FCS_LEN;
4596
4597 if (len > RX_COPY_THRESHOLD
4598 && tp->rx_offset == NET_IP_ALIGN
4599 /* rx_offset will likely not equal NET_IP_ALIGN
4600 * if this is a 5701 card running in PCI-X mode
4601 * [see tg3_get_invariants()]
4602 */
4603 ) {
4604 int skb_size;
4605
4606 skb_size = tg3_alloc_rx_skb(tnapi, opaque_key,
4607 desc_idx, *post_ptr);
4608 if (skb_size < 0)
4609 goto drop_it;
4610
4611 pci_unmap_single(tp->pdev, dma_addr, skb_size,
4612 PCI_DMA_FROMDEVICE);
4613
4614 skb_put(skb, len);
4615 } else {
4616 struct sk_buff *copy_skb;
4617
4618 tg3_recycle_rx(tnapi, opaque_key,
4619 desc_idx, *post_ptr);
4620
4621 copy_skb = netdev_alloc_skb(tp->dev,
4622 len + TG3_RAW_IP_ALIGN);
4623 if (copy_skb == NULL)
4624 goto drop_it_no_recycle;
4625
4626 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4627 skb_put(copy_skb, len);
4628 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4629 skb_copy_from_linear_data(skb, copy_skb->data, len);
4630 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4631
4632 /* We'll reuse the original ring buffer. */
4633 skb = copy_skb;
4634 }
4635
4636 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4637 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4638 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4639 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4640 skb->ip_summed = CHECKSUM_UNNECESSARY;
4641 else
4642 skb->ip_summed = CHECKSUM_NONE;
4643
4644 skb->protocol = eth_type_trans(skb, tp->dev);
4645
4646 if (len > (tp->dev->mtu + ETH_HLEN) &&
4647 skb->protocol != htons(ETH_P_8021Q)) {
4648 dev_kfree_skb(skb);
4649 goto next_pkt;
4650 }
4651
4652 #if TG3_VLAN_TAG_USED
4653 if (tp->vlgrp != NULL &&
4654 desc->type_flags & RXD_FLAG_VLAN) {
4655 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4656 desc->err_vlan & RXD_VLAN_MASK, skb);
4657 } else
4658 #endif
4659 napi_gro_receive(&tnapi->napi, skb);
4660
4661 received++;
4662 budget--;
4663
4664 next_pkt:
4665 (*post_ptr)++;
4666
4667 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4668 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4669
4670 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4671 TG3_64BIT_REG_LOW, idx);
4672 work_mask &= ~RXD_OPAQUE_RING_STD;
4673 rx_std_posted = 0;
4674 }
4675 next_pkt_nopost:
4676 sw_idx++;
4677 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4678
4679 /* Refresh hw_idx to see if there is new work */
4680 if (sw_idx == hw_idx) {
4681 hw_idx = *(tnapi->rx_rcb_prod_idx);
4682 rmb();
4683 }
4684 }
4685
4686 /* ACK the status ring. */
4687 tnapi->rx_rcb_ptr = sw_idx;
4688 tw32_rx_mbox(tnapi->consmbox, sw_idx);
4689
4690 /* Refill RX ring(s). */
4691 if (work_mask & RXD_OPAQUE_RING_STD) {
4692 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
4693 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4694 sw_idx);
4695 }
4696 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4697 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
4698 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4699 sw_idx);
4700 }
4701 mmiowb();
4702
4703 return received;
4704 }
4705
4706 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4707 {
4708 struct tg3 *tp = tnapi->tp;
4709 struct tg3_hw_status *sblk = tnapi->hw_status;
4710
4711 /* handle link change and other phy events */
4712 if (!(tp->tg3_flags &
4713 (TG3_FLAG_USE_LINKCHG_REG |
4714 TG3_FLAG_POLL_SERDES))) {
4715 if (sblk->status & SD_STATUS_LINK_CHG) {
4716 sblk->status = SD_STATUS_UPDATED |
4717 (sblk->status & ~SD_STATUS_LINK_CHG);
4718 spin_lock(&tp->lock);
4719 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4720 tw32_f(MAC_STATUS,
4721 (MAC_STATUS_SYNC_CHANGED |
4722 MAC_STATUS_CFG_CHANGED |
4723 MAC_STATUS_MI_COMPLETION |
4724 MAC_STATUS_LNKSTATE_CHANGED));
4725 udelay(40);
4726 } else
4727 tg3_setup_phy(tp, 0);
4728 spin_unlock(&tp->lock);
4729 }
4730 }
4731
4732 /* run TX completion thread */
4733 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4734 tg3_tx(tnapi);
4735 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4736 return work_done;
4737 }
4738
4739 /* run RX thread, within the bounds set by NAPI.
4740 * All RX "locking" is done by ensuring outside
4741 * code synchronizes with tg3->napi.poll()
4742 */
4743 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4744 work_done += tg3_rx(tnapi, budget - work_done);
4745
4746 return work_done;
4747 }
4748
4749 static int tg3_poll(struct napi_struct *napi, int budget)
4750 {
4751 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4752 struct tg3 *tp = tnapi->tp;
4753 int work_done = 0;
4754 struct tg3_hw_status *sblk = tnapi->hw_status;
4755
4756 while (1) {
4757 work_done = tg3_poll_work(tnapi, work_done, budget);
4758
4759 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4760 goto tx_recovery;
4761
4762 if (unlikely(work_done >= budget))
4763 break;
4764
4765 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4766 /* tp->last_tag is used in tg3_int_reenable() below
4767 * to tell the hw how much work has been processed,
4768 * so we must read it before checking for more work.
4769 */
4770 tnapi->last_tag = sblk->status_tag;
4771 tnapi->last_irq_tag = tnapi->last_tag;
4772 rmb();
4773 } else
4774 sblk->status &= ~SD_STATUS_UPDATED;
4775
4776 if (likely(!tg3_has_work(tnapi))) {
4777 napi_complete(napi);
4778 tg3_int_reenable(tnapi);
4779 break;
4780 }
4781 }
4782
4783 return work_done;
4784
4785 tx_recovery:
4786 /* work_done is guaranteed to be less than budget. */
4787 napi_complete(napi);
4788 schedule_work(&tp->reset_task);
4789 return work_done;
4790 }
4791
4792 static void tg3_irq_quiesce(struct tg3 *tp)
4793 {
4794 int i;
4795
4796 BUG_ON(tp->irq_sync);
4797
4798 tp->irq_sync = 1;
4799 smp_mb();
4800
4801 for (i = 0; i < tp->irq_cnt; i++)
4802 synchronize_irq(tp->napi[i].irq_vec);
4803 }
4804
4805 static inline int tg3_irq_sync(struct tg3 *tp)
4806 {
4807 return tp->irq_sync;
4808 }
4809
4810 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4811 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4812 * with as well. Most of the time, this is not necessary except when
4813 * shutting down the device.
4814 */
4815 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4816 {
4817 spin_lock_bh(&tp->lock);
4818 if (irq_sync)
4819 tg3_irq_quiesce(tp);
4820 }
4821
4822 static inline void tg3_full_unlock(struct tg3 *tp)
4823 {
4824 spin_unlock_bh(&tp->lock);
4825 }
4826
4827 /* One-shot MSI handler - Chip automatically disables interrupt
4828 * after sending MSI so driver doesn't have to do it.
4829 */
4830 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4831 {
4832 struct tg3_napi *tnapi = dev_id;
4833 struct tg3 *tp = tnapi->tp;
4834
4835 prefetch(tnapi->hw_status);
4836 if (tnapi->rx_rcb)
4837 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4838
4839 if (likely(!tg3_irq_sync(tp)))
4840 napi_schedule(&tnapi->napi);
4841
4842 return IRQ_HANDLED;
4843 }
4844
4845 /* MSI ISR - No need to check for interrupt sharing and no need to
4846 * flush status block and interrupt mailbox. PCI ordering rules
4847 * guarantee that MSI will arrive after the status block.
4848 */
4849 static irqreturn_t tg3_msi(int irq, void *dev_id)
4850 {
4851 struct tg3_napi *tnapi = dev_id;
4852 struct tg3 *tp = tnapi->tp;
4853
4854 prefetch(tnapi->hw_status);
4855 if (tnapi->rx_rcb)
4856 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4857 /*
4858 * Writing any value to intr-mbox-0 clears PCI INTA# and
4859 * chip-internal interrupt pending events.
4860 * Writing non-zero to intr-mbox-0 additional tells the
4861 * NIC to stop sending us irqs, engaging "in-intr-handler"
4862 * event coalescing.
4863 */
4864 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4865 if (likely(!tg3_irq_sync(tp)))
4866 napi_schedule(&tnapi->napi);
4867
4868 return IRQ_RETVAL(1);
4869 }
4870
4871 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4872 {
4873 struct tg3_napi *tnapi = dev_id;
4874 struct tg3 *tp = tnapi->tp;
4875 struct tg3_hw_status *sblk = tnapi->hw_status;
4876 unsigned int handled = 1;
4877
4878 /* In INTx mode, it is possible for the interrupt to arrive at
4879 * the CPU before the status block posted prior to the interrupt.
4880 * Reading the PCI State register will confirm whether the
4881 * interrupt is ours and will flush the status block.
4882 */
4883 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4884 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4885 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4886 handled = 0;
4887 goto out;
4888 }
4889 }
4890
4891 /*
4892 * Writing any value to intr-mbox-0 clears PCI INTA# and
4893 * chip-internal interrupt pending events.
4894 * Writing non-zero to intr-mbox-0 additional tells the
4895 * NIC to stop sending us irqs, engaging "in-intr-handler"
4896 * event coalescing.
4897 *
4898 * Flush the mailbox to de-assert the IRQ immediately to prevent
4899 * spurious interrupts. The flush impacts performance but
4900 * excessive spurious interrupts can be worse in some cases.
4901 */
4902 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4903 if (tg3_irq_sync(tp))
4904 goto out;
4905 sblk->status &= ~SD_STATUS_UPDATED;
4906 if (likely(tg3_has_work(tnapi))) {
4907 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4908 napi_schedule(&tnapi->napi);
4909 } else {
4910 /* No work, shared interrupt perhaps? re-enable
4911 * interrupts, and flush that PCI write
4912 */
4913 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4914 0x00000000);
4915 }
4916 out:
4917 return IRQ_RETVAL(handled);
4918 }
4919
4920 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4921 {
4922 struct tg3_napi *tnapi = dev_id;
4923 struct tg3 *tp = tnapi->tp;
4924 struct tg3_hw_status *sblk = tnapi->hw_status;
4925 unsigned int handled = 1;
4926
4927 /* In INTx mode, it is possible for the interrupt to arrive at
4928 * the CPU before the status block posted prior to the interrupt.
4929 * Reading the PCI State register will confirm whether the
4930 * interrupt is ours and will flush the status block.
4931 */
4932 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
4933 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4934 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4935 handled = 0;
4936 goto out;
4937 }
4938 }
4939
4940 /*
4941 * writing any value to intr-mbox-0 clears PCI INTA# and
4942 * chip-internal interrupt pending events.
4943 * writing non-zero to intr-mbox-0 additional tells the
4944 * NIC to stop sending us irqs, engaging "in-intr-handler"
4945 * event coalescing.
4946 *
4947 * Flush the mailbox to de-assert the IRQ immediately to prevent
4948 * spurious interrupts. The flush impacts performance but
4949 * excessive spurious interrupts can be worse in some cases.
4950 */
4951 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4952
4953 /*
4954 * In a shared interrupt configuration, sometimes other devices'
4955 * interrupts will scream. We record the current status tag here
4956 * so that the above check can report that the screaming interrupts
4957 * are unhandled. Eventually they will be silenced.
4958 */
4959 tnapi->last_irq_tag = sblk->status_tag;
4960
4961 if (tg3_irq_sync(tp))
4962 goto out;
4963
4964 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4965
4966 napi_schedule(&tnapi->napi);
4967
4968 out:
4969 return IRQ_RETVAL(handled);
4970 }
4971
4972 /* ISR for interrupt test */
4973 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4974 {
4975 struct tg3_napi *tnapi = dev_id;
4976 struct tg3 *tp = tnapi->tp;
4977 struct tg3_hw_status *sblk = tnapi->hw_status;
4978
4979 if ((sblk->status & SD_STATUS_UPDATED) ||
4980 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4981 tg3_disable_ints(tp);
4982 return IRQ_RETVAL(1);
4983 }
4984 return IRQ_RETVAL(0);
4985 }
4986
4987 static int tg3_init_hw(struct tg3 *, int);
4988 static int tg3_halt(struct tg3 *, int, int);
4989
4990 /* Restart hardware after configuration changes, self-test, etc.
4991 * Invoked with tp->lock held.
4992 */
4993 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4994 __releases(tp->lock)
4995 __acquires(tp->lock)
4996 {
4997 int err;
4998
4999 err = tg3_init_hw(tp, reset_phy);
5000 if (err) {
5001 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5002 "aborting.\n", tp->dev->name);
5003 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5004 tg3_full_unlock(tp);
5005 del_timer_sync(&tp->timer);
5006 tp->irq_sync = 0;
5007 tg3_napi_enable(tp);
5008 dev_close(tp->dev);
5009 tg3_full_lock(tp, 0);
5010 }
5011 return err;
5012 }
5013
5014 #ifdef CONFIG_NET_POLL_CONTROLLER
5015 static void tg3_poll_controller(struct net_device *dev)
5016 {
5017 int i;
5018 struct tg3 *tp = netdev_priv(dev);
5019
5020 for (i = 0; i < tp->irq_cnt; i++)
5021 tg3_interrupt(tp->napi[i].irq_vec, dev);
5022 }
5023 #endif
5024
5025 static void tg3_reset_task(struct work_struct *work)
5026 {
5027 struct tg3 *tp = container_of(work, struct tg3, reset_task);
5028 int err;
5029 unsigned int restart_timer;
5030
5031 tg3_full_lock(tp, 0);
5032
5033 if (!netif_running(tp->dev)) {
5034 tg3_full_unlock(tp);
5035 return;
5036 }
5037
5038 tg3_full_unlock(tp);
5039
5040 tg3_phy_stop(tp);
5041
5042 tg3_netif_stop(tp);
5043
5044 tg3_full_lock(tp, 1);
5045
5046 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5047 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5048
5049 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5050 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5051 tp->write32_rx_mbox = tg3_write_flush_reg32;
5052 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5053 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5054 }
5055
5056 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5057 err = tg3_init_hw(tp, 1);
5058 if (err)
5059 goto out;
5060
5061 tg3_netif_start(tp);
5062
5063 if (restart_timer)
5064 mod_timer(&tp->timer, jiffies + 1);
5065
5066 out:
5067 tg3_full_unlock(tp);
5068
5069 if (!err)
5070 tg3_phy_start(tp);
5071 }
5072
5073 static void tg3_dump_short_state(struct tg3 *tp)
5074 {
5075 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5076 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5077 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5078 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5079 }
5080
5081 static void tg3_tx_timeout(struct net_device *dev)
5082 {
5083 struct tg3 *tp = netdev_priv(dev);
5084
5085 if (netif_msg_tx_err(tp)) {
5086 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5087 dev->name);
5088 tg3_dump_short_state(tp);
5089 }
5090
5091 schedule_work(&tp->reset_task);
5092 }
5093
5094 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5095 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5096 {
5097 u32 base = (u32) mapping & 0xffffffff;
5098
5099 return ((base > 0xffffdcc0) &&
5100 (base + len + 8 < base));
5101 }
5102
5103 /* Test for DMA addresses > 40-bit */
5104 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5105 int len)
5106 {
5107 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5108 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5109 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5110 return 0;
5111 #else
5112 return 0;
5113 #endif
5114 }
5115
5116 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5117
5118 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5119 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
5120 u32 last_plus_one, u32 *start,
5121 u32 base_flags, u32 mss)
5122 {
5123 struct tg3_napi *tnapi = &tp->napi[0];
5124 struct sk_buff *new_skb;
5125 dma_addr_t new_addr = 0;
5126 u32 entry = *start;
5127 int i, ret = 0;
5128
5129 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5130 new_skb = skb_copy(skb, GFP_ATOMIC);
5131 else {
5132 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5133
5134 new_skb = skb_copy_expand(skb,
5135 skb_headroom(skb) + more_headroom,
5136 skb_tailroom(skb), GFP_ATOMIC);
5137 }
5138
5139 if (!new_skb) {
5140 ret = -1;
5141 } else {
5142 /* New SKB is guaranteed to be linear. */
5143 entry = *start;
5144 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5145 new_addr = skb_shinfo(new_skb)->dma_head;
5146
5147 /* Make sure new skb does not cross any 4G boundaries.
5148 * Drop the packet if it does.
5149 */
5150 if (ret || ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5151 tg3_4g_overflow_test(new_addr, new_skb->len))) {
5152 if (!ret)
5153 skb_dma_unmap(&tp->pdev->dev, new_skb,
5154 DMA_TO_DEVICE);
5155 ret = -1;
5156 dev_kfree_skb(new_skb);
5157 new_skb = NULL;
5158 } else {
5159 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5160 base_flags, 1 | (mss << 1));
5161 *start = NEXT_TX(entry);
5162 }
5163 }
5164
5165 /* Now clean up the sw ring entries. */
5166 i = 0;
5167 while (entry != last_plus_one) {
5168 if (i == 0)
5169 tnapi->tx_buffers[entry].skb = new_skb;
5170 else
5171 tnapi->tx_buffers[entry].skb = NULL;
5172 entry = NEXT_TX(entry);
5173 i++;
5174 }
5175
5176 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5177 dev_kfree_skb(skb);
5178
5179 return ret;
5180 }
5181
5182 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5183 dma_addr_t mapping, int len, u32 flags,
5184 u32 mss_and_is_end)
5185 {
5186 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5187 int is_end = (mss_and_is_end & 0x1);
5188 u32 mss = (mss_and_is_end >> 1);
5189 u32 vlan_tag = 0;
5190
5191 if (is_end)
5192 flags |= TXD_FLAG_END;
5193 if (flags & TXD_FLAG_VLAN) {
5194 vlan_tag = flags >> 16;
5195 flags &= 0xffff;
5196 }
5197 vlan_tag |= (mss << TXD_MSS_SHIFT);
5198
5199 txd->addr_hi = ((u64) mapping >> 32);
5200 txd->addr_lo = ((u64) mapping & 0xffffffff);
5201 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5202 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5203 }
5204
5205 /* hard_start_xmit for devices that don't have any bugs and
5206 * support TG3_FLG2_HW_TSO_2 only.
5207 */
5208 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5209 struct net_device *dev)
5210 {
5211 struct tg3 *tp = netdev_priv(dev);
5212 u32 len, entry, base_flags, mss;
5213 struct skb_shared_info *sp;
5214 dma_addr_t mapping;
5215 struct tg3_napi *tnapi;
5216 struct netdev_queue *txq;
5217
5218 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5219 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5220 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5221 tnapi++;
5222
5223 /* We are running in BH disabled context with netif_tx_lock
5224 * and TX reclaim runs via tp->napi.poll inside of a software
5225 * interrupt. Furthermore, IRQ processing runs lockless so we have
5226 * no IRQ context deadlocks to worry about either. Rejoice!
5227 */
5228 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5229 if (!netif_tx_queue_stopped(txq)) {
5230 netif_tx_stop_queue(txq);
5231
5232 /* This is a hard error, log it. */
5233 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5234 "queue awake!\n", dev->name);
5235 }
5236 return NETDEV_TX_BUSY;
5237 }
5238
5239 entry = tnapi->tx_prod;
5240 base_flags = 0;
5241 mss = 0;
5242 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5243 int tcp_opt_len, ip_tcp_len;
5244 u32 hdrlen;
5245
5246 if (skb_header_cloned(skb) &&
5247 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5248 dev_kfree_skb(skb);
5249 goto out_unlock;
5250 }
5251
5252 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5253 hdrlen = skb_headlen(skb) - ETH_HLEN;
5254 else {
5255 struct iphdr *iph = ip_hdr(skb);
5256
5257 tcp_opt_len = tcp_optlen(skb);
5258 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5259
5260 iph->check = 0;
5261 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5262 hdrlen = ip_tcp_len + tcp_opt_len;
5263 }
5264
5265 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
5266 mss |= (hdrlen & 0xc) << 12;
5267 if (hdrlen & 0x10)
5268 base_flags |= 0x00000010;
5269 base_flags |= (hdrlen & 0x3e0) << 5;
5270 } else
5271 mss |= hdrlen << 9;
5272
5273 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5274 TXD_FLAG_CPU_POST_DMA);
5275
5276 tcp_hdr(skb)->check = 0;
5277
5278 }
5279 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5280 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5281 #if TG3_VLAN_TAG_USED
5282 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5283 base_flags |= (TXD_FLAG_VLAN |
5284 (vlan_tx_tag_get(skb) << 16));
5285 #endif
5286
5287 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5288 dev_kfree_skb(skb);
5289 goto out_unlock;
5290 }
5291
5292 sp = skb_shinfo(skb);
5293
5294 mapping = sp->dma_head;
5295
5296 tnapi->tx_buffers[entry].skb = skb;
5297
5298 len = skb_headlen(skb);
5299
5300 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5301 !mss && skb->len > ETH_DATA_LEN)
5302 base_flags |= TXD_FLAG_JMB_PKT;
5303
5304 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5305 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5306
5307 entry = NEXT_TX(entry);
5308
5309 /* Now loop through additional data fragments, and queue them. */
5310 if (skb_shinfo(skb)->nr_frags > 0) {
5311 unsigned int i, last;
5312
5313 last = skb_shinfo(skb)->nr_frags - 1;
5314 for (i = 0; i <= last; i++) {
5315 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5316
5317 len = frag->size;
5318 mapping = sp->dma_maps[i];
5319 tnapi->tx_buffers[entry].skb = NULL;
5320
5321 tg3_set_txd(tnapi, entry, mapping, len,
5322 base_flags, (i == last) | (mss << 1));
5323
5324 entry = NEXT_TX(entry);
5325 }
5326 }
5327
5328 /* Packets are ready, update Tx producer idx local and on card. */
5329 tw32_tx_mbox(tnapi->prodmbox, entry);
5330
5331 tnapi->tx_prod = entry;
5332 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5333 netif_tx_stop_queue(txq);
5334 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5335 netif_tx_wake_queue(txq);
5336 }
5337
5338 out_unlock:
5339 mmiowb();
5340
5341 return NETDEV_TX_OK;
5342 }
5343
5344 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5345 struct net_device *);
5346
5347 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5348 * TSO header is greater than 80 bytes.
5349 */
5350 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5351 {
5352 struct sk_buff *segs, *nskb;
5353 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5354
5355 /* Estimate the number of fragments in the worst case */
5356 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5357 netif_stop_queue(tp->dev);
5358 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5359 return NETDEV_TX_BUSY;
5360
5361 netif_wake_queue(tp->dev);
5362 }
5363
5364 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5365 if (IS_ERR(segs))
5366 goto tg3_tso_bug_end;
5367
5368 do {
5369 nskb = segs;
5370 segs = segs->next;
5371 nskb->next = NULL;
5372 tg3_start_xmit_dma_bug(nskb, tp->dev);
5373 } while (segs);
5374
5375 tg3_tso_bug_end:
5376 dev_kfree_skb(skb);
5377
5378 return NETDEV_TX_OK;
5379 }
5380
5381 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5382 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5383 */
5384 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5385 struct net_device *dev)
5386 {
5387 struct tg3 *tp = netdev_priv(dev);
5388 u32 len, entry, base_flags, mss;
5389 struct skb_shared_info *sp;
5390 int would_hit_hwbug;
5391 dma_addr_t mapping;
5392 struct tg3_napi *tnapi = &tp->napi[0];
5393
5394 len = skb_headlen(skb);
5395
5396 /* We are running in BH disabled context with netif_tx_lock
5397 * and TX reclaim runs via tp->napi.poll inside of a software
5398 * interrupt. Furthermore, IRQ processing runs lockless so we have
5399 * no IRQ context deadlocks to worry about either. Rejoice!
5400 */
5401 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5402 if (!netif_queue_stopped(dev)) {
5403 netif_stop_queue(dev);
5404
5405 /* This is a hard error, log it. */
5406 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5407 "queue awake!\n", dev->name);
5408 }
5409 return NETDEV_TX_BUSY;
5410 }
5411
5412 entry = tnapi->tx_prod;
5413 base_flags = 0;
5414 if (skb->ip_summed == CHECKSUM_PARTIAL)
5415 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5416 mss = 0;
5417 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5418 struct iphdr *iph;
5419 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5420
5421 if (skb_header_cloned(skb) &&
5422 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5423 dev_kfree_skb(skb);
5424 goto out_unlock;
5425 }
5426
5427 tcp_opt_len = tcp_optlen(skb);
5428 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5429
5430 hdr_len = ip_tcp_len + tcp_opt_len;
5431 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5432 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5433 return (tg3_tso_bug(tp, skb));
5434
5435 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5436 TXD_FLAG_CPU_POST_DMA);
5437
5438 iph = ip_hdr(skb);
5439 iph->check = 0;
5440 iph->tot_len = htons(mss + hdr_len);
5441 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5442 tcp_hdr(skb)->check = 0;
5443 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5444 } else
5445 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5446 iph->daddr, 0,
5447 IPPROTO_TCP,
5448 0);
5449
5450 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5451 mss |= hdr_len << 9;
5452 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5453 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5454 if (tcp_opt_len || iph->ihl > 5) {
5455 int tsflags;
5456
5457 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5458 mss |= (tsflags << 11);
5459 }
5460 } else {
5461 if (tcp_opt_len || iph->ihl > 5) {
5462 int tsflags;
5463
5464 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5465 base_flags |= tsflags << 12;
5466 }
5467 }
5468 }
5469 #if TG3_VLAN_TAG_USED
5470 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5471 base_flags |= (TXD_FLAG_VLAN |
5472 (vlan_tx_tag_get(skb) << 16));
5473 #endif
5474
5475 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5476 dev_kfree_skb(skb);
5477 goto out_unlock;
5478 }
5479
5480 sp = skb_shinfo(skb);
5481
5482 mapping = sp->dma_head;
5483
5484 tnapi->tx_buffers[entry].skb = skb;
5485
5486 would_hit_hwbug = 0;
5487
5488 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5489 would_hit_hwbug = 1;
5490
5491 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5492 tg3_4g_overflow_test(mapping, len))
5493 would_hit_hwbug = 1;
5494
5495 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5496 tg3_40bit_overflow_test(tp, mapping, len))
5497 would_hit_hwbug = 1;
5498
5499 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5500 would_hit_hwbug = 1;
5501
5502 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5503 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5504
5505 entry = NEXT_TX(entry);
5506
5507 /* Now loop through additional data fragments, and queue them. */
5508 if (skb_shinfo(skb)->nr_frags > 0) {
5509 unsigned int i, last;
5510
5511 last = skb_shinfo(skb)->nr_frags - 1;
5512 for (i = 0; i <= last; i++) {
5513 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5514
5515 len = frag->size;
5516 mapping = sp->dma_maps[i];
5517
5518 tnapi->tx_buffers[entry].skb = NULL;
5519
5520 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5521 len <= 8)
5522 would_hit_hwbug = 1;
5523
5524 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5525 tg3_4g_overflow_test(mapping, len))
5526 would_hit_hwbug = 1;
5527
5528 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5529 tg3_40bit_overflow_test(tp, mapping, len))
5530 would_hit_hwbug = 1;
5531
5532 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5533 tg3_set_txd(tnapi, entry, mapping, len,
5534 base_flags, (i == last)|(mss << 1));
5535 else
5536 tg3_set_txd(tnapi, entry, mapping, len,
5537 base_flags, (i == last));
5538
5539 entry = NEXT_TX(entry);
5540 }
5541 }
5542
5543 if (would_hit_hwbug) {
5544 u32 last_plus_one = entry;
5545 u32 start;
5546
5547 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5548 start &= (TG3_TX_RING_SIZE - 1);
5549
5550 /* If the workaround fails due to memory/mapping
5551 * failure, silently drop this packet.
5552 */
5553 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5554 &start, base_flags, mss))
5555 goto out_unlock;
5556
5557 entry = start;
5558 }
5559
5560 /* Packets are ready, update Tx producer idx local and on card. */
5561 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, entry);
5562
5563 tnapi->tx_prod = entry;
5564 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5565 netif_stop_queue(dev);
5566 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5567 netif_wake_queue(tp->dev);
5568 }
5569
5570 out_unlock:
5571 mmiowb();
5572
5573 return NETDEV_TX_OK;
5574 }
5575
5576 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5577 int new_mtu)
5578 {
5579 dev->mtu = new_mtu;
5580
5581 if (new_mtu > ETH_DATA_LEN) {
5582 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5583 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5584 ethtool_op_set_tso(dev, 0);
5585 }
5586 else
5587 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5588 } else {
5589 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5590 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5591 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5592 }
5593 }
5594
5595 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5596 {
5597 struct tg3 *tp = netdev_priv(dev);
5598 int err;
5599
5600 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5601 return -EINVAL;
5602
5603 if (!netif_running(dev)) {
5604 /* We'll just catch it later when the
5605 * device is up'd.
5606 */
5607 tg3_set_mtu(dev, tp, new_mtu);
5608 return 0;
5609 }
5610
5611 tg3_phy_stop(tp);
5612
5613 tg3_netif_stop(tp);
5614
5615 tg3_full_lock(tp, 1);
5616
5617 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5618
5619 tg3_set_mtu(dev, tp, new_mtu);
5620
5621 err = tg3_restart_hw(tp, 0);
5622
5623 if (!err)
5624 tg3_netif_start(tp);
5625
5626 tg3_full_unlock(tp);
5627
5628 if (!err)
5629 tg3_phy_start(tp);
5630
5631 return err;
5632 }
5633
5634 static void tg3_rx_prodring_free(struct tg3 *tp,
5635 struct tg3_rx_prodring_set *tpr)
5636 {
5637 int i;
5638 struct ring_info *rxp;
5639
5640 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5641 rxp = &tpr->rx_std_buffers[i];
5642
5643 if (rxp->skb == NULL)
5644 continue;
5645
5646 pci_unmap_single(tp->pdev,
5647 pci_unmap_addr(rxp, mapping),
5648 tp->rx_pkt_map_sz,
5649 PCI_DMA_FROMDEVICE);
5650 dev_kfree_skb_any(rxp->skb);
5651 rxp->skb = NULL;
5652 }
5653
5654 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5655 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5656 rxp = &tpr->rx_jmb_buffers[i];
5657
5658 if (rxp->skb == NULL)
5659 continue;
5660
5661 pci_unmap_single(tp->pdev,
5662 pci_unmap_addr(rxp, mapping),
5663 TG3_RX_JMB_MAP_SZ,
5664 PCI_DMA_FROMDEVICE);
5665 dev_kfree_skb_any(rxp->skb);
5666 rxp->skb = NULL;
5667 }
5668 }
5669 }
5670
5671 /* Initialize tx/rx rings for packet processing.
5672 *
5673 * The chip has been shut down and the driver detached from
5674 * the networking, so no interrupts or new tx packets will
5675 * end up in the driver. tp->{tx,}lock are held and thus
5676 * we may not sleep.
5677 */
5678 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5679 struct tg3_rx_prodring_set *tpr)
5680 {
5681 u32 i, rx_pkt_dma_sz;
5682 struct tg3_napi *tnapi = &tp->napi[0];
5683
5684 /* Zero out all descriptors. */
5685 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5686
5687 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5688 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5689 tp->dev->mtu > ETH_DATA_LEN)
5690 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5691 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
5692
5693 /* Initialize invariants of the rings, we only set this
5694 * stuff once. This works because the card does not
5695 * write into the rx buffer posting rings.
5696 */
5697 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5698 struct tg3_rx_buffer_desc *rxd;
5699
5700 rxd = &tpr->rx_std[i];
5701 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
5702 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5703 rxd->opaque = (RXD_OPAQUE_RING_STD |
5704 (i << RXD_OPAQUE_INDEX_SHIFT));
5705 }
5706
5707 /* Now allocate fresh SKBs for each rx ring. */
5708 for (i = 0; i < tp->rx_pending; i++) {
5709 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5710 printk(KERN_WARNING PFX
5711 "%s: Using a smaller RX standard ring, "
5712 "only %d out of %d buffers were allocated "
5713 "successfully.\n",
5714 tp->dev->name, i, tp->rx_pending);
5715 if (i == 0)
5716 goto initfail;
5717 tp->rx_pending = i;
5718 break;
5719 }
5720 }
5721
5722 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5723 goto done;
5724
5725 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
5726
5727 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5728 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5729 struct tg3_rx_buffer_desc *rxd;
5730
5731 rxd = &tpr->rx_jmb[i].std;
5732 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5733 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5734 RXD_FLAG_JUMBO;
5735 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5736 (i << RXD_OPAQUE_INDEX_SHIFT));
5737 }
5738
5739 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5740 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO,
5741 -1, i) < 0) {
5742 printk(KERN_WARNING PFX
5743 "%s: Using a smaller RX jumbo ring, "
5744 "only %d out of %d buffers were "
5745 "allocated successfully.\n",
5746 tp->dev->name, i, tp->rx_jumbo_pending);
5747 if (i == 0)
5748 goto initfail;
5749 tp->rx_jumbo_pending = i;
5750 break;
5751 }
5752 }
5753 }
5754
5755 done:
5756 return 0;
5757
5758 initfail:
5759 tg3_rx_prodring_free(tp, tpr);
5760 return -ENOMEM;
5761 }
5762
5763 static void tg3_rx_prodring_fini(struct tg3 *tp,
5764 struct tg3_rx_prodring_set *tpr)
5765 {
5766 kfree(tpr->rx_std_buffers);
5767 tpr->rx_std_buffers = NULL;
5768 kfree(tpr->rx_jmb_buffers);
5769 tpr->rx_jmb_buffers = NULL;
5770 if (tpr->rx_std) {
5771 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5772 tpr->rx_std, tpr->rx_std_mapping);
5773 tpr->rx_std = NULL;
5774 }
5775 if (tpr->rx_jmb) {
5776 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5777 tpr->rx_jmb, tpr->rx_jmb_mapping);
5778 tpr->rx_jmb = NULL;
5779 }
5780 }
5781
5782 static int tg3_rx_prodring_init(struct tg3 *tp,
5783 struct tg3_rx_prodring_set *tpr)
5784 {
5785 tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5786 TG3_RX_RING_SIZE, GFP_KERNEL);
5787 if (!tpr->rx_std_buffers)
5788 return -ENOMEM;
5789
5790 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5791 &tpr->rx_std_mapping);
5792 if (!tpr->rx_std)
5793 goto err_out;
5794
5795 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5796 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5797 TG3_RX_JUMBO_RING_SIZE,
5798 GFP_KERNEL);
5799 if (!tpr->rx_jmb_buffers)
5800 goto err_out;
5801
5802 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5803 TG3_RX_JUMBO_RING_BYTES,
5804 &tpr->rx_jmb_mapping);
5805 if (!tpr->rx_jmb)
5806 goto err_out;
5807 }
5808
5809 return 0;
5810
5811 err_out:
5812 tg3_rx_prodring_fini(tp, tpr);
5813 return -ENOMEM;
5814 }
5815
5816 /* Free up pending packets in all rx/tx rings.
5817 *
5818 * The chip has been shut down and the driver detached from
5819 * the networking, so no interrupts or new tx packets will
5820 * end up in the driver. tp->{tx,}lock is not held and we are not
5821 * in an interrupt context and thus may sleep.
5822 */
5823 static void tg3_free_rings(struct tg3 *tp)
5824 {
5825 int i, j;
5826
5827 for (j = 0; j < tp->irq_cnt; j++) {
5828 struct tg3_napi *tnapi = &tp->napi[j];
5829
5830 if (!tnapi->tx_buffers)
5831 continue;
5832
5833 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5834 struct tx_ring_info *txp;
5835 struct sk_buff *skb;
5836
5837 txp = &tnapi->tx_buffers[i];
5838 skb = txp->skb;
5839
5840 if (skb == NULL) {
5841 i++;
5842 continue;
5843 }
5844
5845 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5846
5847 txp->skb = NULL;
5848
5849 i += skb_shinfo(skb)->nr_frags + 1;
5850
5851 dev_kfree_skb_any(skb);
5852 }
5853 }
5854
5855 tg3_rx_prodring_free(tp, &tp->prodring[0]);
5856 }
5857
5858 /* Initialize tx/rx rings for packet processing.
5859 *
5860 * The chip has been shut down and the driver detached from
5861 * the networking, so no interrupts or new tx packets will
5862 * end up in the driver. tp->{tx,}lock are held and thus
5863 * we may not sleep.
5864 */
5865 static int tg3_init_rings(struct tg3 *tp)
5866 {
5867 int i;
5868
5869 /* Free up all the SKBs. */
5870 tg3_free_rings(tp);
5871
5872 for (i = 0; i < tp->irq_cnt; i++) {
5873 struct tg3_napi *tnapi = &tp->napi[i];
5874
5875 tnapi->last_tag = 0;
5876 tnapi->last_irq_tag = 0;
5877 tnapi->hw_status->status = 0;
5878 tnapi->hw_status->status_tag = 0;
5879 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5880
5881 tnapi->tx_prod = 0;
5882 tnapi->tx_cons = 0;
5883 if (tnapi->tx_ring)
5884 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
5885
5886 tnapi->rx_rcb_ptr = 0;
5887 if (tnapi->rx_rcb)
5888 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5889 }
5890
5891 return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
5892 }
5893
5894 /*
5895 * Must not be invoked with interrupt sources disabled and
5896 * the hardware shutdown down.
5897 */
5898 static void tg3_free_consistent(struct tg3 *tp)
5899 {
5900 int i;
5901
5902 for (i = 0; i < tp->irq_cnt; i++) {
5903 struct tg3_napi *tnapi = &tp->napi[i];
5904
5905 if (tnapi->tx_ring) {
5906 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5907 tnapi->tx_ring, tnapi->tx_desc_mapping);
5908 tnapi->tx_ring = NULL;
5909 }
5910
5911 kfree(tnapi->tx_buffers);
5912 tnapi->tx_buffers = NULL;
5913
5914 if (tnapi->rx_rcb) {
5915 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5916 tnapi->rx_rcb,
5917 tnapi->rx_rcb_mapping);
5918 tnapi->rx_rcb = NULL;
5919 }
5920
5921 if (tnapi->hw_status) {
5922 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5923 tnapi->hw_status,
5924 tnapi->status_mapping);
5925 tnapi->hw_status = NULL;
5926 }
5927 }
5928
5929 if (tp->hw_stats) {
5930 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5931 tp->hw_stats, tp->stats_mapping);
5932 tp->hw_stats = NULL;
5933 }
5934
5935 tg3_rx_prodring_fini(tp, &tp->prodring[0]);
5936 }
5937
5938 /*
5939 * Must not be invoked with interrupt sources disabled and
5940 * the hardware shutdown down. Can sleep.
5941 */
5942 static int tg3_alloc_consistent(struct tg3 *tp)
5943 {
5944 int i;
5945
5946 if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
5947 return -ENOMEM;
5948
5949 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5950 sizeof(struct tg3_hw_stats),
5951 &tp->stats_mapping);
5952 if (!tp->hw_stats)
5953 goto err_out;
5954
5955 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5956
5957 for (i = 0; i < tp->irq_cnt; i++) {
5958 struct tg3_napi *tnapi = &tp->napi[i];
5959 struct tg3_hw_status *sblk;
5960
5961 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
5962 TG3_HW_STATUS_SIZE,
5963 &tnapi->status_mapping);
5964 if (!tnapi->hw_status)
5965 goto err_out;
5966
5967 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5968 sblk = tnapi->hw_status;
5969
5970 /*
5971 * When RSS is enabled, the status block format changes
5972 * slightly. The "rx_jumbo_consumer", "reserved",
5973 * and "rx_mini_consumer" members get mapped to the
5974 * other three rx return ring producer indexes.
5975 */
5976 switch (i) {
5977 default:
5978 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
5979 break;
5980 case 2:
5981 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
5982 break;
5983 case 3:
5984 tnapi->rx_rcb_prod_idx = &sblk->reserved;
5985 break;
5986 case 4:
5987 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
5988 break;
5989 }
5990
5991 /*
5992 * If multivector RSS is enabled, vector 0 does not handle
5993 * rx or tx interrupts. Don't allocate any resources for it.
5994 */
5995 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
5996 continue;
5997
5998 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
5999 TG3_RX_RCB_RING_BYTES(tp),
6000 &tnapi->rx_rcb_mapping);
6001 if (!tnapi->rx_rcb)
6002 goto err_out;
6003
6004 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6005
6006 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
6007 TG3_TX_RING_SIZE, GFP_KERNEL);
6008 if (!tnapi->tx_buffers)
6009 goto err_out;
6010
6011 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6012 TG3_TX_RING_BYTES,
6013 &tnapi->tx_desc_mapping);
6014 if (!tnapi->tx_ring)
6015 goto err_out;
6016 }
6017
6018 return 0;
6019
6020 err_out:
6021 tg3_free_consistent(tp);
6022 return -ENOMEM;
6023 }
6024
6025 #define MAX_WAIT_CNT 1000
6026
6027 /* To stop a block, clear the enable bit and poll till it
6028 * clears. tp->lock is held.
6029 */
6030 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6031 {
6032 unsigned int i;
6033 u32 val;
6034
6035 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6036 switch (ofs) {
6037 case RCVLSC_MODE:
6038 case DMAC_MODE:
6039 case MBFREE_MODE:
6040 case BUFMGR_MODE:
6041 case MEMARB_MODE:
6042 /* We can't enable/disable these bits of the
6043 * 5705/5750, just say success.
6044 */
6045 return 0;
6046
6047 default:
6048 break;
6049 }
6050 }
6051
6052 val = tr32(ofs);
6053 val &= ~enable_bit;
6054 tw32_f(ofs, val);
6055
6056 for (i = 0; i < MAX_WAIT_CNT; i++) {
6057 udelay(100);
6058 val = tr32(ofs);
6059 if ((val & enable_bit) == 0)
6060 break;
6061 }
6062
6063 if (i == MAX_WAIT_CNT && !silent) {
6064 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6065 "ofs=%lx enable_bit=%x\n",
6066 ofs, enable_bit);
6067 return -ENODEV;
6068 }
6069
6070 return 0;
6071 }
6072
6073 /* tp->lock is held. */
6074 static int tg3_abort_hw(struct tg3 *tp, int silent)
6075 {
6076 int i, err;
6077
6078 tg3_disable_ints(tp);
6079
6080 tp->rx_mode &= ~RX_MODE_ENABLE;
6081 tw32_f(MAC_RX_MODE, tp->rx_mode);
6082 udelay(10);
6083
6084 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6085 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6086 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6087 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6088 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6089 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6090
6091 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6092 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6093 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6094 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6095 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6096 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6097 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6098
6099 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6100 tw32_f(MAC_MODE, tp->mac_mode);
6101 udelay(40);
6102
6103 tp->tx_mode &= ~TX_MODE_ENABLE;
6104 tw32_f(MAC_TX_MODE, tp->tx_mode);
6105
6106 for (i = 0; i < MAX_WAIT_CNT; i++) {
6107 udelay(100);
6108 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6109 break;
6110 }
6111 if (i >= MAX_WAIT_CNT) {
6112 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6113 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6114 tp->dev->name, tr32(MAC_TX_MODE));
6115 err |= -ENODEV;
6116 }
6117
6118 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6119 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6120 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6121
6122 tw32(FTQ_RESET, 0xffffffff);
6123 tw32(FTQ_RESET, 0x00000000);
6124
6125 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6126 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6127
6128 for (i = 0; i < tp->irq_cnt; i++) {
6129 struct tg3_napi *tnapi = &tp->napi[i];
6130 if (tnapi->hw_status)
6131 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6132 }
6133 if (tp->hw_stats)
6134 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6135
6136 return err;
6137 }
6138
6139 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6140 {
6141 int i;
6142 u32 apedata;
6143
6144 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6145 if (apedata != APE_SEG_SIG_MAGIC)
6146 return;
6147
6148 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6149 if (!(apedata & APE_FW_STATUS_READY))
6150 return;
6151
6152 /* Wait for up to 1 millisecond for APE to service previous event. */
6153 for (i = 0; i < 10; i++) {
6154 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6155 return;
6156
6157 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6158
6159 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6160 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6161 event | APE_EVENT_STATUS_EVENT_PENDING);
6162
6163 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6164
6165 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6166 break;
6167
6168 udelay(100);
6169 }
6170
6171 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6172 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6173 }
6174
6175 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6176 {
6177 u32 event;
6178 u32 apedata;
6179
6180 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6181 return;
6182
6183 switch (kind) {
6184 case RESET_KIND_INIT:
6185 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6186 APE_HOST_SEG_SIG_MAGIC);
6187 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6188 APE_HOST_SEG_LEN_MAGIC);
6189 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6190 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6191 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6192 APE_HOST_DRIVER_ID_MAGIC);
6193 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6194 APE_HOST_BEHAV_NO_PHYLOCK);
6195
6196 event = APE_EVENT_STATUS_STATE_START;
6197 break;
6198 case RESET_KIND_SHUTDOWN:
6199 /* With the interface we are currently using,
6200 * APE does not track driver state. Wiping
6201 * out the HOST SEGMENT SIGNATURE forces
6202 * the APE to assume OS absent status.
6203 */
6204 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6205
6206 event = APE_EVENT_STATUS_STATE_UNLOAD;
6207 break;
6208 case RESET_KIND_SUSPEND:
6209 event = APE_EVENT_STATUS_STATE_SUSPEND;
6210 break;
6211 default:
6212 return;
6213 }
6214
6215 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6216
6217 tg3_ape_send_event(tp, event);
6218 }
6219
6220 /* tp->lock is held. */
6221 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6222 {
6223 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6224 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6225
6226 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6227 switch (kind) {
6228 case RESET_KIND_INIT:
6229 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6230 DRV_STATE_START);
6231 break;
6232
6233 case RESET_KIND_SHUTDOWN:
6234 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6235 DRV_STATE_UNLOAD);
6236 break;
6237
6238 case RESET_KIND_SUSPEND:
6239 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6240 DRV_STATE_SUSPEND);
6241 break;
6242
6243 default:
6244 break;
6245 }
6246 }
6247
6248 if (kind == RESET_KIND_INIT ||
6249 kind == RESET_KIND_SUSPEND)
6250 tg3_ape_driver_state_change(tp, kind);
6251 }
6252
6253 /* tp->lock is held. */
6254 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6255 {
6256 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6257 switch (kind) {
6258 case RESET_KIND_INIT:
6259 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6260 DRV_STATE_START_DONE);
6261 break;
6262
6263 case RESET_KIND_SHUTDOWN:
6264 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6265 DRV_STATE_UNLOAD_DONE);
6266 break;
6267
6268 default:
6269 break;
6270 }
6271 }
6272
6273 if (kind == RESET_KIND_SHUTDOWN)
6274 tg3_ape_driver_state_change(tp, kind);
6275 }
6276
6277 /* tp->lock is held. */
6278 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6279 {
6280 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6281 switch (kind) {
6282 case RESET_KIND_INIT:
6283 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6284 DRV_STATE_START);
6285 break;
6286
6287 case RESET_KIND_SHUTDOWN:
6288 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6289 DRV_STATE_UNLOAD);
6290 break;
6291
6292 case RESET_KIND_SUSPEND:
6293 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6294 DRV_STATE_SUSPEND);
6295 break;
6296
6297 default:
6298 break;
6299 }
6300 }
6301 }
6302
6303 static int tg3_poll_fw(struct tg3 *tp)
6304 {
6305 int i;
6306 u32 val;
6307
6308 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6309 /* Wait up to 20ms for init done. */
6310 for (i = 0; i < 200; i++) {
6311 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6312 return 0;
6313 udelay(100);
6314 }
6315 return -ENODEV;
6316 }
6317
6318 /* Wait for firmware initialization to complete. */
6319 for (i = 0; i < 100000; i++) {
6320 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6321 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6322 break;
6323 udelay(10);
6324 }
6325
6326 /* Chip might not be fitted with firmware. Some Sun onboard
6327 * parts are configured like that. So don't signal the timeout
6328 * of the above loop as an error, but do report the lack of
6329 * running firmware once.
6330 */
6331 if (i >= 100000 &&
6332 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6333 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6334
6335 printk(KERN_INFO PFX "%s: No firmware running.\n",
6336 tp->dev->name);
6337 }
6338
6339 return 0;
6340 }
6341
6342 /* Save PCI command register before chip reset */
6343 static void tg3_save_pci_state(struct tg3 *tp)
6344 {
6345 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6346 }
6347
6348 /* Restore PCI state after chip reset */
6349 static void tg3_restore_pci_state(struct tg3 *tp)
6350 {
6351 u32 val;
6352
6353 /* Re-enable indirect register accesses. */
6354 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6355 tp->misc_host_ctrl);
6356
6357 /* Set MAX PCI retry to zero. */
6358 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6359 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6360 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6361 val |= PCISTATE_RETRY_SAME_DMA;
6362 /* Allow reads and writes to the APE register and memory space. */
6363 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6364 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6365 PCISTATE_ALLOW_APE_SHMEM_WR;
6366 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6367
6368 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6369
6370 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6371 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6372 pcie_set_readrq(tp->pdev, 4096);
6373 else {
6374 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6375 tp->pci_cacheline_sz);
6376 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6377 tp->pci_lat_timer);
6378 }
6379 }
6380
6381 /* Make sure PCI-X relaxed ordering bit is clear. */
6382 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6383 u16 pcix_cmd;
6384
6385 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6386 &pcix_cmd);
6387 pcix_cmd &= ~PCI_X_CMD_ERO;
6388 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6389 pcix_cmd);
6390 }
6391
6392 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6393
6394 /* Chip reset on 5780 will reset MSI enable bit,
6395 * so need to restore it.
6396 */
6397 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6398 u16 ctrl;
6399
6400 pci_read_config_word(tp->pdev,
6401 tp->msi_cap + PCI_MSI_FLAGS,
6402 &ctrl);
6403 pci_write_config_word(tp->pdev,
6404 tp->msi_cap + PCI_MSI_FLAGS,
6405 ctrl | PCI_MSI_FLAGS_ENABLE);
6406 val = tr32(MSGINT_MODE);
6407 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6408 }
6409 }
6410 }
6411
6412 static void tg3_stop_fw(struct tg3 *);
6413
6414 /* tp->lock is held. */
6415 static int tg3_chip_reset(struct tg3 *tp)
6416 {
6417 u32 val;
6418 void (*write_op)(struct tg3 *, u32, u32);
6419 int i, err;
6420
6421 tg3_nvram_lock(tp);
6422
6423 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6424
6425 /* No matching tg3_nvram_unlock() after this because
6426 * chip reset below will undo the nvram lock.
6427 */
6428 tp->nvram_lock_cnt = 0;
6429
6430 /* GRC_MISC_CFG core clock reset will clear the memory
6431 * enable bit in PCI register 4 and the MSI enable bit
6432 * on some chips, so we save relevant registers here.
6433 */
6434 tg3_save_pci_state(tp);
6435
6436 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6437 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6438 tw32(GRC_FASTBOOT_PC, 0);
6439
6440 /*
6441 * We must avoid the readl() that normally takes place.
6442 * It locks machines, causes machine checks, and other
6443 * fun things. So, temporarily disable the 5701
6444 * hardware workaround, while we do the reset.
6445 */
6446 write_op = tp->write32;
6447 if (write_op == tg3_write_flush_reg32)
6448 tp->write32 = tg3_write32;
6449
6450 /* Prevent the irq handler from reading or writing PCI registers
6451 * during chip reset when the memory enable bit in the PCI command
6452 * register may be cleared. The chip does not generate interrupt
6453 * at this time, but the irq handler may still be called due to irq
6454 * sharing or irqpoll.
6455 */
6456 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6457 for (i = 0; i < tp->irq_cnt; i++) {
6458 struct tg3_napi *tnapi = &tp->napi[i];
6459 if (tnapi->hw_status) {
6460 tnapi->hw_status->status = 0;
6461 tnapi->hw_status->status_tag = 0;
6462 }
6463 tnapi->last_tag = 0;
6464 tnapi->last_irq_tag = 0;
6465 }
6466 smp_mb();
6467
6468 for (i = 0; i < tp->irq_cnt; i++)
6469 synchronize_irq(tp->napi[i].irq_vec);
6470
6471 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6472 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6473 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6474 }
6475
6476 /* do the reset */
6477 val = GRC_MISC_CFG_CORECLK_RESET;
6478
6479 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6480 if (tr32(0x7e2c) == 0x60) {
6481 tw32(0x7e2c, 0x20);
6482 }
6483 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6484 tw32(GRC_MISC_CFG, (1 << 29));
6485 val |= (1 << 29);
6486 }
6487 }
6488
6489 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6490 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6491 tw32(GRC_VCPU_EXT_CTRL,
6492 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6493 }
6494
6495 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6496 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6497 tw32(GRC_MISC_CFG, val);
6498
6499 /* restore 5701 hardware bug workaround write method */
6500 tp->write32 = write_op;
6501
6502 /* Unfortunately, we have to delay before the PCI read back.
6503 * Some 575X chips even will not respond to a PCI cfg access
6504 * when the reset command is given to the chip.
6505 *
6506 * How do these hardware designers expect things to work
6507 * properly if the PCI write is posted for a long period
6508 * of time? It is always necessary to have some method by
6509 * which a register read back can occur to push the write
6510 * out which does the reset.
6511 *
6512 * For most tg3 variants the trick below was working.
6513 * Ho hum...
6514 */
6515 udelay(120);
6516
6517 /* Flush PCI posted writes. The normal MMIO registers
6518 * are inaccessible at this time so this is the only
6519 * way to make this reliably (actually, this is no longer
6520 * the case, see above). I tried to use indirect
6521 * register read/write but this upset some 5701 variants.
6522 */
6523 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6524
6525 udelay(120);
6526
6527 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6528 u16 val16;
6529
6530 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6531 int i;
6532 u32 cfg_val;
6533
6534 /* Wait for link training to complete. */
6535 for (i = 0; i < 5000; i++)
6536 udelay(100);
6537
6538 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6539 pci_write_config_dword(tp->pdev, 0xc4,
6540 cfg_val | (1 << 15));
6541 }
6542
6543 /* Clear the "no snoop" and "relaxed ordering" bits. */
6544 pci_read_config_word(tp->pdev,
6545 tp->pcie_cap + PCI_EXP_DEVCTL,
6546 &val16);
6547 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6548 PCI_EXP_DEVCTL_NOSNOOP_EN);
6549 /*
6550 * Older PCIe devices only support the 128 byte
6551 * MPS setting. Enforce the restriction.
6552 */
6553 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6554 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6555 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6556 pci_write_config_word(tp->pdev,
6557 tp->pcie_cap + PCI_EXP_DEVCTL,
6558 val16);
6559
6560 pcie_set_readrq(tp->pdev, 4096);
6561
6562 /* Clear error status */
6563 pci_write_config_word(tp->pdev,
6564 tp->pcie_cap + PCI_EXP_DEVSTA,
6565 PCI_EXP_DEVSTA_CED |
6566 PCI_EXP_DEVSTA_NFED |
6567 PCI_EXP_DEVSTA_FED |
6568 PCI_EXP_DEVSTA_URD);
6569 }
6570
6571 tg3_restore_pci_state(tp);
6572
6573 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6574
6575 val = 0;
6576 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6577 val = tr32(MEMARB_MODE);
6578 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6579
6580 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6581 tg3_stop_fw(tp);
6582 tw32(0x5000, 0x400);
6583 }
6584
6585 tw32(GRC_MODE, tp->grc_mode);
6586
6587 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6588 val = tr32(0xc4);
6589
6590 tw32(0xc4, val | (1 << 15));
6591 }
6592
6593 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6594 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6595 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6596 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6597 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6598 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6599 }
6600
6601 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6602 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6603 tw32_f(MAC_MODE, tp->mac_mode);
6604 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6605 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6606 tw32_f(MAC_MODE, tp->mac_mode);
6607 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6608 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6609 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6610 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6611 tw32_f(MAC_MODE, tp->mac_mode);
6612 } else
6613 tw32_f(MAC_MODE, 0);
6614 udelay(40);
6615
6616 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6617
6618 err = tg3_poll_fw(tp);
6619 if (err)
6620 return err;
6621
6622 tg3_mdio_start(tp);
6623
6624 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6625 u8 phy_addr;
6626
6627 phy_addr = tp->phy_addr;
6628 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6629
6630 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6631 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6632 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6633 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6634 TG3_PCIEPHY_TX0CTRL1_NB_EN;
6635 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6636 udelay(10);
6637
6638 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6639 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6640 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6641 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6642 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6643 udelay(10);
6644
6645 tp->phy_addr = phy_addr;
6646 }
6647
6648 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6649 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6650 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6651 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
6652 val = tr32(0x7c00);
6653
6654 tw32(0x7c00, val | (1 << 25));
6655 }
6656
6657 /* Reprobe ASF enable state. */
6658 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6659 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6660 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6661 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6662 u32 nic_cfg;
6663
6664 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6665 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6666 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6667 tp->last_event_jiffies = jiffies;
6668 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6669 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6670 }
6671 }
6672
6673 return 0;
6674 }
6675
6676 /* tp->lock is held. */
6677 static void tg3_stop_fw(struct tg3 *tp)
6678 {
6679 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6680 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6681 /* Wait for RX cpu to ACK the previous event. */
6682 tg3_wait_for_event_ack(tp);
6683
6684 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6685
6686 tg3_generate_fw_event(tp);
6687
6688 /* Wait for RX cpu to ACK this event. */
6689 tg3_wait_for_event_ack(tp);
6690 }
6691 }
6692
6693 /* tp->lock is held. */
6694 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6695 {
6696 int err;
6697
6698 tg3_stop_fw(tp);
6699
6700 tg3_write_sig_pre_reset(tp, kind);
6701
6702 tg3_abort_hw(tp, silent);
6703 err = tg3_chip_reset(tp);
6704
6705 __tg3_set_mac_addr(tp, 0);
6706
6707 tg3_write_sig_legacy(tp, kind);
6708 tg3_write_sig_post_reset(tp, kind);
6709
6710 if (err)
6711 return err;
6712
6713 return 0;
6714 }
6715
6716 #define RX_CPU_SCRATCH_BASE 0x30000
6717 #define RX_CPU_SCRATCH_SIZE 0x04000
6718 #define TX_CPU_SCRATCH_BASE 0x34000
6719 #define TX_CPU_SCRATCH_SIZE 0x04000
6720
6721 /* tp->lock is held. */
6722 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6723 {
6724 int i;
6725
6726 BUG_ON(offset == TX_CPU_BASE &&
6727 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6728
6729 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6730 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6731
6732 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6733 return 0;
6734 }
6735 if (offset == RX_CPU_BASE) {
6736 for (i = 0; i < 10000; i++) {
6737 tw32(offset + CPU_STATE, 0xffffffff);
6738 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6739 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6740 break;
6741 }
6742
6743 tw32(offset + CPU_STATE, 0xffffffff);
6744 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6745 udelay(10);
6746 } else {
6747 for (i = 0; i < 10000; i++) {
6748 tw32(offset + CPU_STATE, 0xffffffff);
6749 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6750 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6751 break;
6752 }
6753 }
6754
6755 if (i >= 10000) {
6756 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6757 "and %s CPU\n",
6758 tp->dev->name,
6759 (offset == RX_CPU_BASE ? "RX" : "TX"));
6760 return -ENODEV;
6761 }
6762
6763 /* Clear firmware's nvram arbitration. */
6764 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6765 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6766 return 0;
6767 }
6768
6769 struct fw_info {
6770 unsigned int fw_base;
6771 unsigned int fw_len;
6772 const __be32 *fw_data;
6773 };
6774
6775 /* tp->lock is held. */
6776 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6777 int cpu_scratch_size, struct fw_info *info)
6778 {
6779 int err, lock_err, i;
6780 void (*write_op)(struct tg3 *, u32, u32);
6781
6782 if (cpu_base == TX_CPU_BASE &&
6783 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6784 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6785 "TX cpu firmware on %s which is 5705.\n",
6786 tp->dev->name);
6787 return -EINVAL;
6788 }
6789
6790 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6791 write_op = tg3_write_mem;
6792 else
6793 write_op = tg3_write_indirect_reg32;
6794
6795 /* It is possible that bootcode is still loading at this point.
6796 * Get the nvram lock first before halting the cpu.
6797 */
6798 lock_err = tg3_nvram_lock(tp);
6799 err = tg3_halt_cpu(tp, cpu_base);
6800 if (!lock_err)
6801 tg3_nvram_unlock(tp);
6802 if (err)
6803 goto out;
6804
6805 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6806 write_op(tp, cpu_scratch_base + i, 0);
6807 tw32(cpu_base + CPU_STATE, 0xffffffff);
6808 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6809 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6810 write_op(tp, (cpu_scratch_base +
6811 (info->fw_base & 0xffff) +
6812 (i * sizeof(u32))),
6813 be32_to_cpu(info->fw_data[i]));
6814
6815 err = 0;
6816
6817 out:
6818 return err;
6819 }
6820
6821 /* tp->lock is held. */
6822 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6823 {
6824 struct fw_info info;
6825 const __be32 *fw_data;
6826 int err, i;
6827
6828 fw_data = (void *)tp->fw->data;
6829
6830 /* Firmware blob starts with version numbers, followed by
6831 start address and length. We are setting complete length.
6832 length = end_address_of_bss - start_address_of_text.
6833 Remainder is the blob to be loaded contiguously
6834 from start address. */
6835
6836 info.fw_base = be32_to_cpu(fw_data[1]);
6837 info.fw_len = tp->fw->size - 12;
6838 info.fw_data = &fw_data[3];
6839
6840 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6841 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6842 &info);
6843 if (err)
6844 return err;
6845
6846 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6847 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6848 &info);
6849 if (err)
6850 return err;
6851
6852 /* Now startup only the RX cpu. */
6853 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6854 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6855
6856 for (i = 0; i < 5; i++) {
6857 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6858 break;
6859 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6860 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
6861 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6862 udelay(1000);
6863 }
6864 if (i >= 5) {
6865 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6866 "to set RX CPU PC, is %08x should be %08x\n",
6867 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6868 info.fw_base);
6869 return -ENODEV;
6870 }
6871 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6872 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6873
6874 return 0;
6875 }
6876
6877 /* 5705 needs a special version of the TSO firmware. */
6878
6879 /* tp->lock is held. */
6880 static int tg3_load_tso_firmware(struct tg3 *tp)
6881 {
6882 struct fw_info info;
6883 const __be32 *fw_data;
6884 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6885 int err, i;
6886
6887 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6888 return 0;
6889
6890 fw_data = (void *)tp->fw->data;
6891
6892 /* Firmware blob starts with version numbers, followed by
6893 start address and length. We are setting complete length.
6894 length = end_address_of_bss - start_address_of_text.
6895 Remainder is the blob to be loaded contiguously
6896 from start address. */
6897
6898 info.fw_base = be32_to_cpu(fw_data[1]);
6899 cpu_scratch_size = tp->fw_len;
6900 info.fw_len = tp->fw->size - 12;
6901 info.fw_data = &fw_data[3];
6902
6903 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6904 cpu_base = RX_CPU_BASE;
6905 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6906 } else {
6907 cpu_base = TX_CPU_BASE;
6908 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6909 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6910 }
6911
6912 err = tg3_load_firmware_cpu(tp, cpu_base,
6913 cpu_scratch_base, cpu_scratch_size,
6914 &info);
6915 if (err)
6916 return err;
6917
6918 /* Now startup the cpu. */
6919 tw32(cpu_base + CPU_STATE, 0xffffffff);
6920 tw32_f(cpu_base + CPU_PC, info.fw_base);
6921
6922 for (i = 0; i < 5; i++) {
6923 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6924 break;
6925 tw32(cpu_base + CPU_STATE, 0xffffffff);
6926 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
6927 tw32_f(cpu_base + CPU_PC, info.fw_base);
6928 udelay(1000);
6929 }
6930 if (i >= 5) {
6931 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6932 "to set CPU PC, is %08x should be %08x\n",
6933 tp->dev->name, tr32(cpu_base + CPU_PC),
6934 info.fw_base);
6935 return -ENODEV;
6936 }
6937 tw32(cpu_base + CPU_STATE, 0xffffffff);
6938 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6939 return 0;
6940 }
6941
6942
6943 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6944 {
6945 struct tg3 *tp = netdev_priv(dev);
6946 struct sockaddr *addr = p;
6947 int err = 0, skip_mac_1 = 0;
6948
6949 if (!is_valid_ether_addr(addr->sa_data))
6950 return -EINVAL;
6951
6952 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6953
6954 if (!netif_running(dev))
6955 return 0;
6956
6957 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6958 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6959
6960 addr0_high = tr32(MAC_ADDR_0_HIGH);
6961 addr0_low = tr32(MAC_ADDR_0_LOW);
6962 addr1_high = tr32(MAC_ADDR_1_HIGH);
6963 addr1_low = tr32(MAC_ADDR_1_LOW);
6964
6965 /* Skip MAC addr 1 if ASF is using it. */
6966 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6967 !(addr1_high == 0 && addr1_low == 0))
6968 skip_mac_1 = 1;
6969 }
6970 spin_lock_bh(&tp->lock);
6971 __tg3_set_mac_addr(tp, skip_mac_1);
6972 spin_unlock_bh(&tp->lock);
6973
6974 return err;
6975 }
6976
6977 /* tp->lock is held. */
6978 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6979 dma_addr_t mapping, u32 maxlen_flags,
6980 u32 nic_addr)
6981 {
6982 tg3_write_mem(tp,
6983 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6984 ((u64) mapping >> 32));
6985 tg3_write_mem(tp,
6986 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6987 ((u64) mapping & 0xffffffff));
6988 tg3_write_mem(tp,
6989 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6990 maxlen_flags);
6991
6992 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6993 tg3_write_mem(tp,
6994 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6995 nic_addr);
6996 }
6997
6998 static void __tg3_set_rx_mode(struct net_device *);
6999 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7000 {
7001 int i;
7002
7003 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7004 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7005 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7006 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7007
7008 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7009 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7010 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7011 } else {
7012 tw32(HOSTCC_TXCOL_TICKS, 0);
7013 tw32(HOSTCC_TXMAX_FRAMES, 0);
7014 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7015
7016 tw32(HOSTCC_RXCOL_TICKS, 0);
7017 tw32(HOSTCC_RXMAX_FRAMES, 0);
7018 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7019 }
7020
7021 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7022 u32 val = ec->stats_block_coalesce_usecs;
7023
7024 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7025 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7026
7027 if (!netif_carrier_ok(tp->dev))
7028 val = 0;
7029
7030 tw32(HOSTCC_STAT_COAL_TICKS, val);
7031 }
7032
7033 for (i = 0; i < tp->irq_cnt - 1; i++) {
7034 u32 reg;
7035
7036 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7037 tw32(reg, ec->rx_coalesce_usecs);
7038 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7039 tw32(reg, ec->tx_coalesce_usecs);
7040 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7041 tw32(reg, ec->rx_max_coalesced_frames);
7042 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7043 tw32(reg, ec->tx_max_coalesced_frames);
7044 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7045 tw32(reg, ec->rx_max_coalesced_frames_irq);
7046 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7047 tw32(reg, ec->tx_max_coalesced_frames_irq);
7048 }
7049
7050 for (; i < tp->irq_max - 1; i++) {
7051 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7052 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7053 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7054 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7055 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7056 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7057 }
7058 }
7059
7060 /* tp->lock is held. */
7061 static void tg3_rings_reset(struct tg3 *tp)
7062 {
7063 int i;
7064 u32 stblk, txrcb, rxrcb, limit;
7065 struct tg3_napi *tnapi = &tp->napi[0];
7066
7067 /* Disable all transmit rings but the first. */
7068 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7069 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7070 else
7071 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7072
7073 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7074 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7075 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7076 BDINFO_FLAGS_DISABLED);
7077
7078
7079 /* Disable all receive return rings but the first. */
7080 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7081 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7082 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7083 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7084 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7085 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7086 else
7087 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7088
7089 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7090 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7091 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7092 BDINFO_FLAGS_DISABLED);
7093
7094 /* Disable interrupts */
7095 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7096
7097 /* Zero mailbox registers. */
7098 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7099 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7100 tp->napi[i].tx_prod = 0;
7101 tp->napi[i].tx_cons = 0;
7102 tw32_mailbox(tp->napi[i].prodmbox, 0);
7103 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7104 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7105 }
7106 } else {
7107 tp->napi[0].tx_prod = 0;
7108 tp->napi[0].tx_cons = 0;
7109 tw32_mailbox(tp->napi[0].prodmbox, 0);
7110 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7111 }
7112
7113 /* Make sure the NIC-based send BD rings are disabled. */
7114 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7115 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7116 for (i = 0; i < 16; i++)
7117 tw32_tx_mbox(mbox + i * 8, 0);
7118 }
7119
7120 txrcb = NIC_SRAM_SEND_RCB;
7121 rxrcb = NIC_SRAM_RCV_RET_RCB;
7122
7123 /* Clear status block in ram. */
7124 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7125
7126 /* Set status block DMA address */
7127 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7128 ((u64) tnapi->status_mapping >> 32));
7129 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7130 ((u64) tnapi->status_mapping & 0xffffffff));
7131
7132 if (tnapi->tx_ring) {
7133 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7134 (TG3_TX_RING_SIZE <<
7135 BDINFO_FLAGS_MAXLEN_SHIFT),
7136 NIC_SRAM_TX_BUFFER_DESC);
7137 txrcb += TG3_BDINFO_SIZE;
7138 }
7139
7140 if (tnapi->rx_rcb) {
7141 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7142 (TG3_RX_RCB_RING_SIZE(tp) <<
7143 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7144 rxrcb += TG3_BDINFO_SIZE;
7145 }
7146
7147 stblk = HOSTCC_STATBLCK_RING1;
7148
7149 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7150 u64 mapping = (u64)tnapi->status_mapping;
7151 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7152 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7153
7154 /* Clear status block in ram. */
7155 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7156
7157 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7158 (TG3_TX_RING_SIZE <<
7159 BDINFO_FLAGS_MAXLEN_SHIFT),
7160 NIC_SRAM_TX_BUFFER_DESC);
7161
7162 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7163 (TG3_RX_RCB_RING_SIZE(tp) <<
7164 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7165
7166 stblk += 8;
7167 txrcb += TG3_BDINFO_SIZE;
7168 rxrcb += TG3_BDINFO_SIZE;
7169 }
7170 }
7171
7172 /* tp->lock is held. */
7173 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7174 {
7175 u32 val, rdmac_mode;
7176 int i, err, limit;
7177 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7178
7179 tg3_disable_ints(tp);
7180
7181 tg3_stop_fw(tp);
7182
7183 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7184
7185 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7186 tg3_abort_hw(tp, 1);
7187 }
7188
7189 if (reset_phy &&
7190 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7191 tg3_phy_reset(tp);
7192
7193 err = tg3_chip_reset(tp);
7194 if (err)
7195 return err;
7196
7197 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7198
7199 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7200 val = tr32(TG3_CPMU_CTRL);
7201 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7202 tw32(TG3_CPMU_CTRL, val);
7203
7204 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7205 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7206 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7207 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7208
7209 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7210 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7211 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7212 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7213
7214 val = tr32(TG3_CPMU_HST_ACC);
7215 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7216 val |= CPMU_HST_ACC_MACCLK_6_25;
7217 tw32(TG3_CPMU_HST_ACC, val);
7218 }
7219
7220 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7221 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7222 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7223 PCIE_PWR_MGMT_L1_THRESH_4MS;
7224 tw32(PCIE_PWR_MGMT_THRESH, val);
7225
7226 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7227 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7228
7229 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7230
7231 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7232 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7233 }
7234
7235 /* This works around an issue with Athlon chipsets on
7236 * B3 tigon3 silicon. This bit has no effect on any
7237 * other revision. But do not set this on PCI Express
7238 * chips and don't even touch the clocks if the CPMU is present.
7239 */
7240 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7241 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7242 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7243 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7244 }
7245
7246 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7247 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7248 val = tr32(TG3PCI_PCISTATE);
7249 val |= PCISTATE_RETRY_SAME_DMA;
7250 tw32(TG3PCI_PCISTATE, val);
7251 }
7252
7253 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7254 /* Allow reads and writes to the
7255 * APE register and memory space.
7256 */
7257 val = tr32(TG3PCI_PCISTATE);
7258 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7259 PCISTATE_ALLOW_APE_SHMEM_WR;
7260 tw32(TG3PCI_PCISTATE, val);
7261 }
7262
7263 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7264 /* Enable some hw fixes. */
7265 val = tr32(TG3PCI_MSI_DATA);
7266 val |= (1 << 26) | (1 << 28) | (1 << 29);
7267 tw32(TG3PCI_MSI_DATA, val);
7268 }
7269
7270 /* Descriptor ring init may make accesses to the
7271 * NIC SRAM area to setup the TX descriptors, so we
7272 * can only do this after the hardware has been
7273 * successfully reset.
7274 */
7275 err = tg3_init_rings(tp);
7276 if (err)
7277 return err;
7278
7279 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7280 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
7281 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
7282 /* This value is determined during the probe time DMA
7283 * engine test, tg3_test_dma.
7284 */
7285 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7286 }
7287
7288 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7289 GRC_MODE_4X_NIC_SEND_RINGS |
7290 GRC_MODE_NO_TX_PHDR_CSUM |
7291 GRC_MODE_NO_RX_PHDR_CSUM);
7292 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7293
7294 /* Pseudo-header checksum is done by hardware logic and not
7295 * the offload processers, so make the chip do the pseudo-
7296 * header checksums on receive. For transmit it is more
7297 * convenient to do the pseudo-header checksum in software
7298 * as Linux does that on transmit for us in all cases.
7299 */
7300 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7301
7302 tw32(GRC_MODE,
7303 tp->grc_mode |
7304 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7305
7306 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7307 val = tr32(GRC_MISC_CFG);
7308 val &= ~0xff;
7309 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7310 tw32(GRC_MISC_CFG, val);
7311
7312 /* Initialize MBUF/DESC pool. */
7313 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7314 /* Do nothing. */
7315 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7316 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7317 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7318 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7319 else
7320 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7321 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7322 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7323 }
7324 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7325 int fw_len;
7326
7327 fw_len = tp->fw_len;
7328 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7329 tw32(BUFMGR_MB_POOL_ADDR,
7330 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7331 tw32(BUFMGR_MB_POOL_SIZE,
7332 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7333 }
7334
7335 if (tp->dev->mtu <= ETH_DATA_LEN) {
7336 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7337 tp->bufmgr_config.mbuf_read_dma_low_water);
7338 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7339 tp->bufmgr_config.mbuf_mac_rx_low_water);
7340 tw32(BUFMGR_MB_HIGH_WATER,
7341 tp->bufmgr_config.mbuf_high_water);
7342 } else {
7343 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7344 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7345 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7346 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7347 tw32(BUFMGR_MB_HIGH_WATER,
7348 tp->bufmgr_config.mbuf_high_water_jumbo);
7349 }
7350 tw32(BUFMGR_DMA_LOW_WATER,
7351 tp->bufmgr_config.dma_low_water);
7352 tw32(BUFMGR_DMA_HIGH_WATER,
7353 tp->bufmgr_config.dma_high_water);
7354
7355 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7356 for (i = 0; i < 2000; i++) {
7357 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7358 break;
7359 udelay(10);
7360 }
7361 if (i >= 2000) {
7362 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7363 tp->dev->name);
7364 return -ENODEV;
7365 }
7366
7367 /* Setup replenish threshold. */
7368 val = tp->rx_pending / 8;
7369 if (val == 0)
7370 val = 1;
7371 else if (val > tp->rx_std_max_post)
7372 val = tp->rx_std_max_post;
7373 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7374 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7375 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7376
7377 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7378 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7379 }
7380
7381 tw32(RCVBDI_STD_THRESH, val);
7382
7383 /* Initialize TG3_BDINFO's at:
7384 * RCVDBDI_STD_BD: standard eth size rx ring
7385 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7386 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7387 *
7388 * like so:
7389 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7390 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7391 * ring attribute flags
7392 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7393 *
7394 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7395 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7396 *
7397 * The size of each ring is fixed in the firmware, but the location is
7398 * configurable.
7399 */
7400 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7401 ((u64) tpr->rx_std_mapping >> 32));
7402 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7403 ((u64) tpr->rx_std_mapping & 0xffffffff));
7404 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7405 NIC_SRAM_RX_BUFFER_DESC);
7406
7407 /* Disable the mini ring */
7408 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7409 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7410 BDINFO_FLAGS_DISABLED);
7411
7412 /* Program the jumbo buffer descriptor ring control
7413 * blocks on those devices that have them.
7414 */
7415 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7416 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7417 /* Setup replenish threshold. */
7418 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7419
7420 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7421 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7422 ((u64) tpr->rx_jmb_mapping >> 32));
7423 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7424 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7425 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7426 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7427 BDINFO_FLAGS_USE_EXT_RECV);
7428 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7429 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7430 } else {
7431 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7432 BDINFO_FLAGS_DISABLED);
7433 }
7434
7435 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7436 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7437 (RX_STD_MAX_SIZE << 2);
7438 else
7439 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7440 } else
7441 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7442
7443 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7444
7445 tpr->rx_std_ptr = tp->rx_pending;
7446 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7447 tpr->rx_std_ptr);
7448
7449 tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7450 tp->rx_jumbo_pending : 0;
7451 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7452 tpr->rx_jmb_ptr);
7453
7454 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7455 tw32(STD_REPLENISH_LWM, 32);
7456 tw32(JMB_REPLENISH_LWM, 16);
7457 }
7458
7459 tg3_rings_reset(tp);
7460
7461 /* Initialize MAC address and backoff seed. */
7462 __tg3_set_mac_addr(tp, 0);
7463
7464 /* MTU + ethernet header + FCS + optional VLAN tag */
7465 tw32(MAC_RX_MTU_SIZE,
7466 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7467
7468 /* The slot time is changed by tg3_setup_phy if we
7469 * run at gigabit with half duplex.
7470 */
7471 tw32(MAC_TX_LENGTHS,
7472 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7473 (6 << TX_LENGTHS_IPG_SHIFT) |
7474 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7475
7476 /* Receive rules. */
7477 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7478 tw32(RCVLPC_CONFIG, 0x0181);
7479
7480 /* Calculate RDMAC_MODE setting early, we need it to determine
7481 * the RCVLPC_STATE_ENABLE mask.
7482 */
7483 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7484 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7485 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7486 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7487 RDMAC_MODE_LNGREAD_ENAB);
7488
7489 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7490 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7491 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7492 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7493 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7494 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7495
7496 /* If statement applies to 5705 and 5750 PCI devices only */
7497 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7498 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7499 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7500 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7501 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7502 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7503 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7504 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7505 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7506 }
7507 }
7508
7509 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7510 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7511
7512 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7513 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7514
7515 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7516 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7517 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7518
7519 /* Receive/send statistics. */
7520 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7521 val = tr32(RCVLPC_STATS_ENABLE);
7522 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7523 tw32(RCVLPC_STATS_ENABLE, val);
7524 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7525 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7526 val = tr32(RCVLPC_STATS_ENABLE);
7527 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7528 tw32(RCVLPC_STATS_ENABLE, val);
7529 } else {
7530 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7531 }
7532 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7533 tw32(SNDDATAI_STATSENAB, 0xffffff);
7534 tw32(SNDDATAI_STATSCTRL,
7535 (SNDDATAI_SCTRL_ENABLE |
7536 SNDDATAI_SCTRL_FASTUPD));
7537
7538 /* Setup host coalescing engine. */
7539 tw32(HOSTCC_MODE, 0);
7540 for (i = 0; i < 2000; i++) {
7541 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7542 break;
7543 udelay(10);
7544 }
7545
7546 __tg3_set_coalesce(tp, &tp->coal);
7547
7548 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7549 /* Status/statistics block address. See tg3_timer,
7550 * the tg3_periodic_fetch_stats call there, and
7551 * tg3_get_stats to see how this works for 5705/5750 chips.
7552 */
7553 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7554 ((u64) tp->stats_mapping >> 32));
7555 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7556 ((u64) tp->stats_mapping & 0xffffffff));
7557 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7558
7559 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7560
7561 /* Clear statistics and status block memory areas */
7562 for (i = NIC_SRAM_STATS_BLK;
7563 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7564 i += sizeof(u32)) {
7565 tg3_write_mem(tp, i, 0);
7566 udelay(40);
7567 }
7568 }
7569
7570 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7571
7572 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7573 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7574 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7575 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7576
7577 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7578 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7579 /* reset to prevent losing 1st rx packet intermittently */
7580 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7581 udelay(10);
7582 }
7583
7584 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7585 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7586 else
7587 tp->mac_mode = 0;
7588 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7589 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7590 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7591 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7592 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7593 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7594 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7595 udelay(40);
7596
7597 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7598 * If TG3_FLG2_IS_NIC is zero, we should read the
7599 * register to preserve the GPIO settings for LOMs. The GPIOs,
7600 * whether used as inputs or outputs, are set by boot code after
7601 * reset.
7602 */
7603 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7604 u32 gpio_mask;
7605
7606 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7607 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7608 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7609
7610 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7611 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7612 GRC_LCLCTRL_GPIO_OUTPUT3;
7613
7614 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7615 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7616
7617 tp->grc_local_ctrl &= ~gpio_mask;
7618 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7619
7620 /* GPIO1 must be driven high for eeprom write protect */
7621 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7622 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7623 GRC_LCLCTRL_GPIO_OUTPUT1);
7624 }
7625 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7626 udelay(100);
7627
7628 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7629 val = tr32(MSGINT_MODE);
7630 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7631 tw32(MSGINT_MODE, val);
7632 }
7633
7634 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7635 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7636 udelay(40);
7637 }
7638
7639 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7640 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7641 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7642 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7643 WDMAC_MODE_LNGREAD_ENAB);
7644
7645 /* If statement applies to 5705 and 5750 PCI devices only */
7646 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7647 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7648 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7649 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7650 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7651 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7652 /* nothing */
7653 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7654 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7655 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7656 val |= WDMAC_MODE_RX_ACCEL;
7657 }
7658 }
7659
7660 /* Enable host coalescing bug fix */
7661 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7662 val |= WDMAC_MODE_STATUS_TAG_FIX;
7663
7664 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7665 val |= WDMAC_MODE_BURST_ALL_DATA;
7666
7667 tw32_f(WDMAC_MODE, val);
7668 udelay(40);
7669
7670 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7671 u16 pcix_cmd;
7672
7673 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7674 &pcix_cmd);
7675 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7676 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7677 pcix_cmd |= PCI_X_CMD_READ_2K;
7678 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7679 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7680 pcix_cmd |= PCI_X_CMD_READ_2K;
7681 }
7682 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7683 pcix_cmd);
7684 }
7685
7686 tw32_f(RDMAC_MODE, rdmac_mode);
7687 udelay(40);
7688
7689 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7690 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7691 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7692
7693 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7694 tw32(SNDDATAC_MODE,
7695 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7696 else
7697 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7698
7699 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7700 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7701 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7702 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7703 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7704 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7705 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
7706 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
7707 val |= SNDBDI_MODE_MULTI_TXQ_EN;
7708 tw32(SNDBDI_MODE, val);
7709 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7710
7711 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7712 err = tg3_load_5701_a0_firmware_fix(tp);
7713 if (err)
7714 return err;
7715 }
7716
7717 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7718 err = tg3_load_tso_firmware(tp);
7719 if (err)
7720 return err;
7721 }
7722
7723 tp->tx_mode = TX_MODE_ENABLE;
7724 tw32_f(MAC_TX_MODE, tp->tx_mode);
7725 udelay(100);
7726
7727 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
7728 u32 reg = MAC_RSS_INDIR_TBL_0;
7729 u8 *ent = (u8 *)&val;
7730
7731 /* Setup the indirection table */
7732 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
7733 int idx = i % sizeof(val);
7734
7735 ent[idx] = i % (tp->irq_cnt - 1);
7736 if (idx == sizeof(val) - 1) {
7737 tw32(reg, val);
7738 reg += 4;
7739 }
7740 }
7741
7742 /* Setup the "secret" hash key. */
7743 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
7744 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
7745 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
7746 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
7747 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
7748 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
7749 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
7750 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
7751 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
7752 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
7753 }
7754
7755 tp->rx_mode = RX_MODE_ENABLE;
7756 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7757 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7758
7759 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
7760 tp->rx_mode |= RX_MODE_RSS_ENABLE |
7761 RX_MODE_RSS_ITBL_HASH_BITS_7 |
7762 RX_MODE_RSS_IPV6_HASH_EN |
7763 RX_MODE_RSS_TCP_IPV6_HASH_EN |
7764 RX_MODE_RSS_IPV4_HASH_EN |
7765 RX_MODE_RSS_TCP_IPV4_HASH_EN;
7766
7767 tw32_f(MAC_RX_MODE, tp->rx_mode);
7768 udelay(10);
7769
7770 tw32(MAC_LED_CTRL, tp->led_ctrl);
7771
7772 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7773 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7774 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7775 udelay(10);
7776 }
7777 tw32_f(MAC_RX_MODE, tp->rx_mode);
7778 udelay(10);
7779
7780 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7781 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7782 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7783 /* Set drive transmission level to 1.2V */
7784 /* only if the signal pre-emphasis bit is not set */
7785 val = tr32(MAC_SERDES_CFG);
7786 val &= 0xfffff000;
7787 val |= 0x880;
7788 tw32(MAC_SERDES_CFG, val);
7789 }
7790 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7791 tw32(MAC_SERDES_CFG, 0x616000);
7792 }
7793
7794 /* Prevent chip from dropping frames when flow control
7795 * is enabled.
7796 */
7797 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7798
7799 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7800 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7801 /* Use hardware link auto-negotiation */
7802 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7803 }
7804
7805 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7806 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7807 u32 tmp;
7808
7809 tmp = tr32(SERDES_RX_CTRL);
7810 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7811 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7812 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7813 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7814 }
7815
7816 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7817 if (tp->link_config.phy_is_low_power) {
7818 tp->link_config.phy_is_low_power = 0;
7819 tp->link_config.speed = tp->link_config.orig_speed;
7820 tp->link_config.duplex = tp->link_config.orig_duplex;
7821 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7822 }
7823
7824 err = tg3_setup_phy(tp, 0);
7825 if (err)
7826 return err;
7827
7828 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7829 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
7830 u32 tmp;
7831
7832 /* Clear CRC stats. */
7833 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7834 tg3_writephy(tp, MII_TG3_TEST1,
7835 tmp | MII_TG3_TEST1_CRC_EN);
7836 tg3_readphy(tp, 0x14, &tmp);
7837 }
7838 }
7839 }
7840
7841 __tg3_set_rx_mode(tp->dev);
7842
7843 /* Initialize receive rules. */
7844 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7845 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7846 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7847 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7848
7849 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7850 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7851 limit = 8;
7852 else
7853 limit = 16;
7854 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7855 limit -= 4;
7856 switch (limit) {
7857 case 16:
7858 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7859 case 15:
7860 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7861 case 14:
7862 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7863 case 13:
7864 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7865 case 12:
7866 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7867 case 11:
7868 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7869 case 10:
7870 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7871 case 9:
7872 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7873 case 8:
7874 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7875 case 7:
7876 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7877 case 6:
7878 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7879 case 5:
7880 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7881 case 4:
7882 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7883 case 3:
7884 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7885 case 2:
7886 case 1:
7887
7888 default:
7889 break;
7890 }
7891
7892 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7893 /* Write our heartbeat update interval to APE. */
7894 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7895 APE_HOST_HEARTBEAT_INT_DISABLE);
7896
7897 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7898
7899 return 0;
7900 }
7901
7902 /* Called at device open time to get the chip ready for
7903 * packet processing. Invoked with tp->lock held.
7904 */
7905 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7906 {
7907 tg3_switch_clocks(tp);
7908
7909 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7910
7911 return tg3_reset_hw(tp, reset_phy);
7912 }
7913
7914 #define TG3_STAT_ADD32(PSTAT, REG) \
7915 do { u32 __val = tr32(REG); \
7916 (PSTAT)->low += __val; \
7917 if ((PSTAT)->low < __val) \
7918 (PSTAT)->high += 1; \
7919 } while (0)
7920
7921 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7922 {
7923 struct tg3_hw_stats *sp = tp->hw_stats;
7924
7925 if (!netif_carrier_ok(tp->dev))
7926 return;
7927
7928 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7929 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7930 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7931 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7932 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7933 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7934 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7935 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7936 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7937 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7938 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7939 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7940 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7941
7942 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7943 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7944 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7945 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7946 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7947 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7948 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7949 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7950 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7951 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7952 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7953 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7954 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7955 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7956
7957 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7958 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7959 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7960 }
7961
7962 static void tg3_timer(unsigned long __opaque)
7963 {
7964 struct tg3 *tp = (struct tg3 *) __opaque;
7965
7966 if (tp->irq_sync)
7967 goto restart_timer;
7968
7969 spin_lock(&tp->lock);
7970
7971 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7972 /* All of this garbage is because when using non-tagged
7973 * IRQ status the mailbox/status_block protocol the chip
7974 * uses with the cpu is race prone.
7975 */
7976 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
7977 tw32(GRC_LOCAL_CTRL,
7978 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7979 } else {
7980 tw32(HOSTCC_MODE, tp->coalesce_mode |
7981 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
7982 }
7983
7984 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7985 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7986 spin_unlock(&tp->lock);
7987 schedule_work(&tp->reset_task);
7988 return;
7989 }
7990 }
7991
7992 /* This part only runs once per second. */
7993 if (!--tp->timer_counter) {
7994 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7995 tg3_periodic_fetch_stats(tp);
7996
7997 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7998 u32 mac_stat;
7999 int phy_event;
8000
8001 mac_stat = tr32(MAC_STATUS);
8002
8003 phy_event = 0;
8004 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8005 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8006 phy_event = 1;
8007 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8008 phy_event = 1;
8009
8010 if (phy_event)
8011 tg3_setup_phy(tp, 0);
8012 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8013 u32 mac_stat = tr32(MAC_STATUS);
8014 int need_setup = 0;
8015
8016 if (netif_carrier_ok(tp->dev) &&
8017 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8018 need_setup = 1;
8019 }
8020 if (! netif_carrier_ok(tp->dev) &&
8021 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8022 MAC_STATUS_SIGNAL_DET))) {
8023 need_setup = 1;
8024 }
8025 if (need_setup) {
8026 if (!tp->serdes_counter) {
8027 tw32_f(MAC_MODE,
8028 (tp->mac_mode &
8029 ~MAC_MODE_PORT_MODE_MASK));
8030 udelay(40);
8031 tw32_f(MAC_MODE, tp->mac_mode);
8032 udelay(40);
8033 }
8034 tg3_setup_phy(tp, 0);
8035 }
8036 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8037 tg3_serdes_parallel_detect(tp);
8038
8039 tp->timer_counter = tp->timer_multiplier;
8040 }
8041
8042 /* Heartbeat is only sent once every 2 seconds.
8043 *
8044 * The heartbeat is to tell the ASF firmware that the host
8045 * driver is still alive. In the event that the OS crashes,
8046 * ASF needs to reset the hardware to free up the FIFO space
8047 * that may be filled with rx packets destined for the host.
8048 * If the FIFO is full, ASF will no longer function properly.
8049 *
8050 * Unintended resets have been reported on real time kernels
8051 * where the timer doesn't run on time. Netpoll will also have
8052 * same problem.
8053 *
8054 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8055 * to check the ring condition when the heartbeat is expiring
8056 * before doing the reset. This will prevent most unintended
8057 * resets.
8058 */
8059 if (!--tp->asf_counter) {
8060 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8061 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8062 tg3_wait_for_event_ack(tp);
8063
8064 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8065 FWCMD_NICDRV_ALIVE3);
8066 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8067 /* 5 seconds timeout */
8068 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8069
8070 tg3_generate_fw_event(tp);
8071 }
8072 tp->asf_counter = tp->asf_multiplier;
8073 }
8074
8075 spin_unlock(&tp->lock);
8076
8077 restart_timer:
8078 tp->timer.expires = jiffies + tp->timer_offset;
8079 add_timer(&tp->timer);
8080 }
8081
8082 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8083 {
8084 irq_handler_t fn;
8085 unsigned long flags;
8086 char *name;
8087 struct tg3_napi *tnapi = &tp->napi[irq_num];
8088
8089 if (tp->irq_cnt == 1)
8090 name = tp->dev->name;
8091 else {
8092 name = &tnapi->irq_lbl[0];
8093 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8094 name[IFNAMSIZ-1] = 0;
8095 }
8096
8097 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8098 fn = tg3_msi;
8099 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8100 fn = tg3_msi_1shot;
8101 flags = IRQF_SAMPLE_RANDOM;
8102 } else {
8103 fn = tg3_interrupt;
8104 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8105 fn = tg3_interrupt_tagged;
8106 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8107 }
8108
8109 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8110 }
8111
8112 static int tg3_test_interrupt(struct tg3 *tp)
8113 {
8114 struct tg3_napi *tnapi = &tp->napi[0];
8115 struct net_device *dev = tp->dev;
8116 int err, i, intr_ok = 0;
8117 u32 val;
8118
8119 if (!netif_running(dev))
8120 return -ENODEV;
8121
8122 tg3_disable_ints(tp);
8123
8124 free_irq(tnapi->irq_vec, tnapi);
8125
8126 /*
8127 * Turn off MSI one shot mode. Otherwise this test has no
8128 * observable way to know whether the interrupt was delivered.
8129 */
8130 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8131 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8132 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8133 tw32(MSGINT_MODE, val);
8134 }
8135
8136 err = request_irq(tnapi->irq_vec, tg3_test_isr,
8137 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8138 if (err)
8139 return err;
8140
8141 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8142 tg3_enable_ints(tp);
8143
8144 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8145 tnapi->coal_now);
8146
8147 for (i = 0; i < 5; i++) {
8148 u32 int_mbox, misc_host_ctrl;
8149
8150 int_mbox = tr32_mailbox(tnapi->int_mbox);
8151 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8152
8153 if ((int_mbox != 0) ||
8154 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8155 intr_ok = 1;
8156 break;
8157 }
8158
8159 msleep(10);
8160 }
8161
8162 tg3_disable_ints(tp);
8163
8164 free_irq(tnapi->irq_vec, tnapi);
8165
8166 err = tg3_request_irq(tp, 0);
8167
8168 if (err)
8169 return err;
8170
8171 if (intr_ok) {
8172 /* Reenable MSI one shot mode. */
8173 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8174 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8175 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8176 tw32(MSGINT_MODE, val);
8177 }
8178 return 0;
8179 }
8180
8181 return -EIO;
8182 }
8183
8184 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8185 * successfully restored
8186 */
8187 static int tg3_test_msi(struct tg3 *tp)
8188 {
8189 int err;
8190 u16 pci_cmd;
8191
8192 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8193 return 0;
8194
8195 /* Turn off SERR reporting in case MSI terminates with Master
8196 * Abort.
8197 */
8198 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8199 pci_write_config_word(tp->pdev, PCI_COMMAND,
8200 pci_cmd & ~PCI_COMMAND_SERR);
8201
8202 err = tg3_test_interrupt(tp);
8203
8204 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8205
8206 if (!err)
8207 return 0;
8208
8209 /* other failures */
8210 if (err != -EIO)
8211 return err;
8212
8213 /* MSI test failed, go back to INTx mode */
8214 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8215 "switching to INTx mode. Please report this failure to "
8216 "the PCI maintainer and include system chipset information.\n",
8217 tp->dev->name);
8218
8219 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8220
8221 pci_disable_msi(tp->pdev);
8222
8223 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8224
8225 err = tg3_request_irq(tp, 0);
8226 if (err)
8227 return err;
8228
8229 /* Need to reset the chip because the MSI cycle may have terminated
8230 * with Master Abort.
8231 */
8232 tg3_full_lock(tp, 1);
8233
8234 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8235 err = tg3_init_hw(tp, 1);
8236
8237 tg3_full_unlock(tp);
8238
8239 if (err)
8240 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8241
8242 return err;
8243 }
8244
8245 static int tg3_request_firmware(struct tg3 *tp)
8246 {
8247 const __be32 *fw_data;
8248
8249 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8250 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8251 tp->dev->name, tp->fw_needed);
8252 return -ENOENT;
8253 }
8254
8255 fw_data = (void *)tp->fw->data;
8256
8257 /* Firmware blob starts with version numbers, followed by
8258 * start address and _full_ length including BSS sections
8259 * (which must be longer than the actual data, of course
8260 */
8261
8262 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8263 if (tp->fw_len < (tp->fw->size - 12)) {
8264 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8265 tp->dev->name, tp->fw_len, tp->fw_needed);
8266 release_firmware(tp->fw);
8267 tp->fw = NULL;
8268 return -EINVAL;
8269 }
8270
8271 /* We no longer need firmware; we have it. */
8272 tp->fw_needed = NULL;
8273 return 0;
8274 }
8275
8276 static bool tg3_enable_msix(struct tg3 *tp)
8277 {
8278 int i, rc, cpus = num_online_cpus();
8279 struct msix_entry msix_ent[tp->irq_max];
8280
8281 if (cpus == 1)
8282 /* Just fallback to the simpler MSI mode. */
8283 return false;
8284
8285 /*
8286 * We want as many rx rings enabled as there are cpus.
8287 * The first MSIX vector only deals with link interrupts, etc,
8288 * so we add one to the number of vectors we are requesting.
8289 */
8290 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8291
8292 for (i = 0; i < tp->irq_max; i++) {
8293 msix_ent[i].entry = i;
8294 msix_ent[i].vector = 0;
8295 }
8296
8297 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8298 if (rc != 0) {
8299 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8300 return false;
8301 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8302 return false;
8303 printk(KERN_NOTICE
8304 "%s: Requested %d MSI-X vectors, received %d\n",
8305 tp->dev->name, tp->irq_cnt, rc);
8306 tp->irq_cnt = rc;
8307 }
8308
8309 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8310
8311 for (i = 0; i < tp->irq_max; i++)
8312 tp->napi[i].irq_vec = msix_ent[i].vector;
8313
8314 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8315
8316 return true;
8317 }
8318
8319 static void tg3_ints_init(struct tg3 *tp)
8320 {
8321 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8322 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8323 /* All MSI supporting chips should support tagged
8324 * status. Assert that this is the case.
8325 */
8326 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8327 "Not using MSI.\n", tp->dev->name);
8328 goto defcfg;
8329 }
8330
8331 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8332 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8333 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8334 pci_enable_msi(tp->pdev) == 0)
8335 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8336
8337 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8338 u32 msi_mode = tr32(MSGINT_MODE);
8339 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8340 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8341 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8342 }
8343 defcfg:
8344 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8345 tp->irq_cnt = 1;
8346 tp->napi[0].irq_vec = tp->pdev->irq;
8347 tp->dev->real_num_tx_queues = 1;
8348 }
8349 }
8350
8351 static void tg3_ints_fini(struct tg3 *tp)
8352 {
8353 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8354 pci_disable_msix(tp->pdev);
8355 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8356 pci_disable_msi(tp->pdev);
8357 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8358 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8359 }
8360
8361 static int tg3_open(struct net_device *dev)
8362 {
8363 struct tg3 *tp = netdev_priv(dev);
8364 int i, err;
8365
8366 if (tp->fw_needed) {
8367 err = tg3_request_firmware(tp);
8368 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8369 if (err)
8370 return err;
8371 } else if (err) {
8372 printk(KERN_WARNING "%s: TSO capability disabled.\n",
8373 tp->dev->name);
8374 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8375 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8376 printk(KERN_NOTICE "%s: TSO capability restored.\n",
8377 tp->dev->name);
8378 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8379 }
8380 }
8381
8382 netif_carrier_off(tp->dev);
8383
8384 err = tg3_set_power_state(tp, PCI_D0);
8385 if (err)
8386 return err;
8387
8388 tg3_full_lock(tp, 0);
8389
8390 tg3_disable_ints(tp);
8391 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8392
8393 tg3_full_unlock(tp);
8394
8395 /*
8396 * Setup interrupts first so we know how
8397 * many NAPI resources to allocate
8398 */
8399 tg3_ints_init(tp);
8400
8401 /* The placement of this call is tied
8402 * to the setup and use of Host TX descriptors.
8403 */
8404 err = tg3_alloc_consistent(tp);
8405 if (err)
8406 goto err_out1;
8407
8408 tg3_napi_enable(tp);
8409
8410 for (i = 0; i < tp->irq_cnt; i++) {
8411 struct tg3_napi *tnapi = &tp->napi[i];
8412 err = tg3_request_irq(tp, i);
8413 if (err) {
8414 for (i--; i >= 0; i--)
8415 free_irq(tnapi->irq_vec, tnapi);
8416 break;
8417 }
8418 }
8419
8420 if (err)
8421 goto err_out2;
8422
8423 tg3_full_lock(tp, 0);
8424
8425 err = tg3_init_hw(tp, 1);
8426 if (err) {
8427 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8428 tg3_free_rings(tp);
8429 } else {
8430 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8431 tp->timer_offset = HZ;
8432 else
8433 tp->timer_offset = HZ / 10;
8434
8435 BUG_ON(tp->timer_offset > HZ);
8436 tp->timer_counter = tp->timer_multiplier =
8437 (HZ / tp->timer_offset);
8438 tp->asf_counter = tp->asf_multiplier =
8439 ((HZ / tp->timer_offset) * 2);
8440
8441 init_timer(&tp->timer);
8442 tp->timer.expires = jiffies + tp->timer_offset;
8443 tp->timer.data = (unsigned long) tp;
8444 tp->timer.function = tg3_timer;
8445 }
8446
8447 tg3_full_unlock(tp);
8448
8449 if (err)
8450 goto err_out3;
8451
8452 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8453 err = tg3_test_msi(tp);
8454
8455 if (err) {
8456 tg3_full_lock(tp, 0);
8457 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8458 tg3_free_rings(tp);
8459 tg3_full_unlock(tp);
8460
8461 goto err_out2;
8462 }
8463
8464 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8465 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8466 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8467 u32 val = tr32(PCIE_TRANSACTION_CFG);
8468
8469 tw32(PCIE_TRANSACTION_CFG,
8470 val | PCIE_TRANS_CFG_1SHOT_MSI);
8471 }
8472 }
8473
8474 tg3_phy_start(tp);
8475
8476 tg3_full_lock(tp, 0);
8477
8478 add_timer(&tp->timer);
8479 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8480 tg3_enable_ints(tp);
8481
8482 tg3_full_unlock(tp);
8483
8484 netif_tx_start_all_queues(dev);
8485
8486 return 0;
8487
8488 err_out3:
8489 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8490 struct tg3_napi *tnapi = &tp->napi[i];
8491 free_irq(tnapi->irq_vec, tnapi);
8492 }
8493
8494 err_out2:
8495 tg3_napi_disable(tp);
8496 tg3_free_consistent(tp);
8497
8498 err_out1:
8499 tg3_ints_fini(tp);
8500 return err;
8501 }
8502
8503 #if 0
8504 /*static*/ void tg3_dump_state(struct tg3 *tp)
8505 {
8506 u32 val32, val32_2, val32_3, val32_4, val32_5;
8507 u16 val16;
8508 int i;
8509 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8510
8511 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8512 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8513 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8514 val16, val32);
8515
8516 /* MAC block */
8517 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8518 tr32(MAC_MODE), tr32(MAC_STATUS));
8519 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8520 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8521 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8522 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8523 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8524 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8525
8526 /* Send data initiator control block */
8527 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8528 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8529 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8530 tr32(SNDDATAI_STATSCTRL));
8531
8532 /* Send data completion control block */
8533 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8534
8535 /* Send BD ring selector block */
8536 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8537 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8538
8539 /* Send BD initiator control block */
8540 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8541 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8542
8543 /* Send BD completion control block */
8544 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8545
8546 /* Receive list placement control block */
8547 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8548 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8549 printk(" RCVLPC_STATSCTRL[%08x]\n",
8550 tr32(RCVLPC_STATSCTRL));
8551
8552 /* Receive data and receive BD initiator control block */
8553 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8554 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8555
8556 /* Receive data completion control block */
8557 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8558 tr32(RCVDCC_MODE));
8559
8560 /* Receive BD initiator control block */
8561 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8562 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8563
8564 /* Receive BD completion control block */
8565 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8566 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8567
8568 /* Receive list selector control block */
8569 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8570 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8571
8572 /* Mbuf cluster free block */
8573 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8574 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8575
8576 /* Host coalescing control block */
8577 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8578 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8579 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8580 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8581 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8582 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8583 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8584 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8585 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8586 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8587 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8588 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8589
8590 /* Memory arbiter control block */
8591 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8592 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8593
8594 /* Buffer manager control block */
8595 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8596 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8597 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8598 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8599 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8600 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8601 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8602 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8603
8604 /* Read DMA control block */
8605 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8606 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8607
8608 /* Write DMA control block */
8609 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8610 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8611
8612 /* DMA completion block */
8613 printk("DEBUG: DMAC_MODE[%08x]\n",
8614 tr32(DMAC_MODE));
8615
8616 /* GRC block */
8617 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8618 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8619 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8620 tr32(GRC_LOCAL_CTRL));
8621
8622 /* TG3_BDINFOs */
8623 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8624 tr32(RCVDBDI_JUMBO_BD + 0x0),
8625 tr32(RCVDBDI_JUMBO_BD + 0x4),
8626 tr32(RCVDBDI_JUMBO_BD + 0x8),
8627 tr32(RCVDBDI_JUMBO_BD + 0xc));
8628 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8629 tr32(RCVDBDI_STD_BD + 0x0),
8630 tr32(RCVDBDI_STD_BD + 0x4),
8631 tr32(RCVDBDI_STD_BD + 0x8),
8632 tr32(RCVDBDI_STD_BD + 0xc));
8633 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8634 tr32(RCVDBDI_MINI_BD + 0x0),
8635 tr32(RCVDBDI_MINI_BD + 0x4),
8636 tr32(RCVDBDI_MINI_BD + 0x8),
8637 tr32(RCVDBDI_MINI_BD + 0xc));
8638
8639 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8640 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8641 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8642 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8643 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8644 val32, val32_2, val32_3, val32_4);
8645
8646 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8647 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8648 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8649 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8650 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8651 val32, val32_2, val32_3, val32_4);
8652
8653 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8654 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8655 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8656 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8657 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8658 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8659 val32, val32_2, val32_3, val32_4, val32_5);
8660
8661 /* SW status block */
8662 printk(KERN_DEBUG
8663 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8664 sblk->status,
8665 sblk->status_tag,
8666 sblk->rx_jumbo_consumer,
8667 sblk->rx_consumer,
8668 sblk->rx_mini_consumer,
8669 sblk->idx[0].rx_producer,
8670 sblk->idx[0].tx_consumer);
8671
8672 /* SW statistics block */
8673 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8674 ((u32 *)tp->hw_stats)[0],
8675 ((u32 *)tp->hw_stats)[1],
8676 ((u32 *)tp->hw_stats)[2],
8677 ((u32 *)tp->hw_stats)[3]);
8678
8679 /* Mailboxes */
8680 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8681 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8682 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8683 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8684 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8685
8686 /* NIC side send descriptors. */
8687 for (i = 0; i < 6; i++) {
8688 unsigned long txd;
8689
8690 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8691 + (i * sizeof(struct tg3_tx_buffer_desc));
8692 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8693 i,
8694 readl(txd + 0x0), readl(txd + 0x4),
8695 readl(txd + 0x8), readl(txd + 0xc));
8696 }
8697
8698 /* NIC side RX descriptors. */
8699 for (i = 0; i < 6; i++) {
8700 unsigned long rxd;
8701
8702 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8703 + (i * sizeof(struct tg3_rx_buffer_desc));
8704 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8705 i,
8706 readl(rxd + 0x0), readl(rxd + 0x4),
8707 readl(rxd + 0x8), readl(rxd + 0xc));
8708 rxd += (4 * sizeof(u32));
8709 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8710 i,
8711 readl(rxd + 0x0), readl(rxd + 0x4),
8712 readl(rxd + 0x8), readl(rxd + 0xc));
8713 }
8714
8715 for (i = 0; i < 6; i++) {
8716 unsigned long rxd;
8717
8718 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8719 + (i * sizeof(struct tg3_rx_buffer_desc));
8720 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8721 i,
8722 readl(rxd + 0x0), readl(rxd + 0x4),
8723 readl(rxd + 0x8), readl(rxd + 0xc));
8724 rxd += (4 * sizeof(u32));
8725 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8726 i,
8727 readl(rxd + 0x0), readl(rxd + 0x4),
8728 readl(rxd + 0x8), readl(rxd + 0xc));
8729 }
8730 }
8731 #endif
8732
8733 static struct net_device_stats *tg3_get_stats(struct net_device *);
8734 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8735
8736 static int tg3_close(struct net_device *dev)
8737 {
8738 int i;
8739 struct tg3 *tp = netdev_priv(dev);
8740
8741 tg3_napi_disable(tp);
8742 cancel_work_sync(&tp->reset_task);
8743
8744 netif_tx_stop_all_queues(dev);
8745
8746 del_timer_sync(&tp->timer);
8747
8748 tg3_phy_stop(tp);
8749
8750 tg3_full_lock(tp, 1);
8751 #if 0
8752 tg3_dump_state(tp);
8753 #endif
8754
8755 tg3_disable_ints(tp);
8756
8757 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8758 tg3_free_rings(tp);
8759 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8760
8761 tg3_full_unlock(tp);
8762
8763 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8764 struct tg3_napi *tnapi = &tp->napi[i];
8765 free_irq(tnapi->irq_vec, tnapi);
8766 }
8767
8768 tg3_ints_fini(tp);
8769
8770 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8771 sizeof(tp->net_stats_prev));
8772 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8773 sizeof(tp->estats_prev));
8774
8775 tg3_free_consistent(tp);
8776
8777 tg3_set_power_state(tp, PCI_D3hot);
8778
8779 netif_carrier_off(tp->dev);
8780
8781 return 0;
8782 }
8783
8784 static inline unsigned long get_stat64(tg3_stat64_t *val)
8785 {
8786 unsigned long ret;
8787
8788 #if (BITS_PER_LONG == 32)
8789 ret = val->low;
8790 #else
8791 ret = ((u64)val->high << 32) | ((u64)val->low);
8792 #endif
8793 return ret;
8794 }
8795
8796 static inline u64 get_estat64(tg3_stat64_t *val)
8797 {
8798 return ((u64)val->high << 32) | ((u64)val->low);
8799 }
8800
8801 static unsigned long calc_crc_errors(struct tg3 *tp)
8802 {
8803 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8804
8805 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8806 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8807 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8808 u32 val;
8809
8810 spin_lock_bh(&tp->lock);
8811 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8812 tg3_writephy(tp, MII_TG3_TEST1,
8813 val | MII_TG3_TEST1_CRC_EN);
8814 tg3_readphy(tp, 0x14, &val);
8815 } else
8816 val = 0;
8817 spin_unlock_bh(&tp->lock);
8818
8819 tp->phy_crc_errors += val;
8820
8821 return tp->phy_crc_errors;
8822 }
8823
8824 return get_stat64(&hw_stats->rx_fcs_errors);
8825 }
8826
8827 #define ESTAT_ADD(member) \
8828 estats->member = old_estats->member + \
8829 get_estat64(&hw_stats->member)
8830
8831 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8832 {
8833 struct tg3_ethtool_stats *estats = &tp->estats;
8834 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8835 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8836
8837 if (!hw_stats)
8838 return old_estats;
8839
8840 ESTAT_ADD(rx_octets);
8841 ESTAT_ADD(rx_fragments);
8842 ESTAT_ADD(rx_ucast_packets);
8843 ESTAT_ADD(rx_mcast_packets);
8844 ESTAT_ADD(rx_bcast_packets);
8845 ESTAT_ADD(rx_fcs_errors);
8846 ESTAT_ADD(rx_align_errors);
8847 ESTAT_ADD(rx_xon_pause_rcvd);
8848 ESTAT_ADD(rx_xoff_pause_rcvd);
8849 ESTAT_ADD(rx_mac_ctrl_rcvd);
8850 ESTAT_ADD(rx_xoff_entered);
8851 ESTAT_ADD(rx_frame_too_long_errors);
8852 ESTAT_ADD(rx_jabbers);
8853 ESTAT_ADD(rx_undersize_packets);
8854 ESTAT_ADD(rx_in_length_errors);
8855 ESTAT_ADD(rx_out_length_errors);
8856 ESTAT_ADD(rx_64_or_less_octet_packets);
8857 ESTAT_ADD(rx_65_to_127_octet_packets);
8858 ESTAT_ADD(rx_128_to_255_octet_packets);
8859 ESTAT_ADD(rx_256_to_511_octet_packets);
8860 ESTAT_ADD(rx_512_to_1023_octet_packets);
8861 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8862 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8863 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8864 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8865 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8866
8867 ESTAT_ADD(tx_octets);
8868 ESTAT_ADD(tx_collisions);
8869 ESTAT_ADD(tx_xon_sent);
8870 ESTAT_ADD(tx_xoff_sent);
8871 ESTAT_ADD(tx_flow_control);
8872 ESTAT_ADD(tx_mac_errors);
8873 ESTAT_ADD(tx_single_collisions);
8874 ESTAT_ADD(tx_mult_collisions);
8875 ESTAT_ADD(tx_deferred);
8876 ESTAT_ADD(tx_excessive_collisions);
8877 ESTAT_ADD(tx_late_collisions);
8878 ESTAT_ADD(tx_collide_2times);
8879 ESTAT_ADD(tx_collide_3times);
8880 ESTAT_ADD(tx_collide_4times);
8881 ESTAT_ADD(tx_collide_5times);
8882 ESTAT_ADD(tx_collide_6times);
8883 ESTAT_ADD(tx_collide_7times);
8884 ESTAT_ADD(tx_collide_8times);
8885 ESTAT_ADD(tx_collide_9times);
8886 ESTAT_ADD(tx_collide_10times);
8887 ESTAT_ADD(tx_collide_11times);
8888 ESTAT_ADD(tx_collide_12times);
8889 ESTAT_ADD(tx_collide_13times);
8890 ESTAT_ADD(tx_collide_14times);
8891 ESTAT_ADD(tx_collide_15times);
8892 ESTAT_ADD(tx_ucast_packets);
8893 ESTAT_ADD(tx_mcast_packets);
8894 ESTAT_ADD(tx_bcast_packets);
8895 ESTAT_ADD(tx_carrier_sense_errors);
8896 ESTAT_ADD(tx_discards);
8897 ESTAT_ADD(tx_errors);
8898
8899 ESTAT_ADD(dma_writeq_full);
8900 ESTAT_ADD(dma_write_prioq_full);
8901 ESTAT_ADD(rxbds_empty);
8902 ESTAT_ADD(rx_discards);
8903 ESTAT_ADD(rx_errors);
8904 ESTAT_ADD(rx_threshold_hit);
8905
8906 ESTAT_ADD(dma_readq_full);
8907 ESTAT_ADD(dma_read_prioq_full);
8908 ESTAT_ADD(tx_comp_queue_full);
8909
8910 ESTAT_ADD(ring_set_send_prod_index);
8911 ESTAT_ADD(ring_status_update);
8912 ESTAT_ADD(nic_irqs);
8913 ESTAT_ADD(nic_avoided_irqs);
8914 ESTAT_ADD(nic_tx_threshold_hit);
8915
8916 return estats;
8917 }
8918
8919 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8920 {
8921 struct tg3 *tp = netdev_priv(dev);
8922 struct net_device_stats *stats = &tp->net_stats;
8923 struct net_device_stats *old_stats = &tp->net_stats_prev;
8924 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8925
8926 if (!hw_stats)
8927 return old_stats;
8928
8929 stats->rx_packets = old_stats->rx_packets +
8930 get_stat64(&hw_stats->rx_ucast_packets) +
8931 get_stat64(&hw_stats->rx_mcast_packets) +
8932 get_stat64(&hw_stats->rx_bcast_packets);
8933
8934 stats->tx_packets = old_stats->tx_packets +
8935 get_stat64(&hw_stats->tx_ucast_packets) +
8936 get_stat64(&hw_stats->tx_mcast_packets) +
8937 get_stat64(&hw_stats->tx_bcast_packets);
8938
8939 stats->rx_bytes = old_stats->rx_bytes +
8940 get_stat64(&hw_stats->rx_octets);
8941 stats->tx_bytes = old_stats->tx_bytes +
8942 get_stat64(&hw_stats->tx_octets);
8943
8944 stats->rx_errors = old_stats->rx_errors +
8945 get_stat64(&hw_stats->rx_errors);
8946 stats->tx_errors = old_stats->tx_errors +
8947 get_stat64(&hw_stats->tx_errors) +
8948 get_stat64(&hw_stats->tx_mac_errors) +
8949 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8950 get_stat64(&hw_stats->tx_discards);
8951
8952 stats->multicast = old_stats->multicast +
8953 get_stat64(&hw_stats->rx_mcast_packets);
8954 stats->collisions = old_stats->collisions +
8955 get_stat64(&hw_stats->tx_collisions);
8956
8957 stats->rx_length_errors = old_stats->rx_length_errors +
8958 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8959 get_stat64(&hw_stats->rx_undersize_packets);
8960
8961 stats->rx_over_errors = old_stats->rx_over_errors +
8962 get_stat64(&hw_stats->rxbds_empty);
8963 stats->rx_frame_errors = old_stats->rx_frame_errors +
8964 get_stat64(&hw_stats->rx_align_errors);
8965 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8966 get_stat64(&hw_stats->tx_discards);
8967 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8968 get_stat64(&hw_stats->tx_carrier_sense_errors);
8969
8970 stats->rx_crc_errors = old_stats->rx_crc_errors +
8971 calc_crc_errors(tp);
8972
8973 stats->rx_missed_errors = old_stats->rx_missed_errors +
8974 get_stat64(&hw_stats->rx_discards);
8975
8976 return stats;
8977 }
8978
8979 static inline u32 calc_crc(unsigned char *buf, int len)
8980 {
8981 u32 reg;
8982 u32 tmp;
8983 int j, k;
8984
8985 reg = 0xffffffff;
8986
8987 for (j = 0; j < len; j++) {
8988 reg ^= buf[j];
8989
8990 for (k = 0; k < 8; k++) {
8991 tmp = reg & 0x01;
8992
8993 reg >>= 1;
8994
8995 if (tmp) {
8996 reg ^= 0xedb88320;
8997 }
8998 }
8999 }
9000
9001 return ~reg;
9002 }
9003
9004 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9005 {
9006 /* accept or reject all multicast frames */
9007 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9008 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9009 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9010 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9011 }
9012
9013 static void __tg3_set_rx_mode(struct net_device *dev)
9014 {
9015 struct tg3 *tp = netdev_priv(dev);
9016 u32 rx_mode;
9017
9018 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9019 RX_MODE_KEEP_VLAN_TAG);
9020
9021 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9022 * flag clear.
9023 */
9024 #if TG3_VLAN_TAG_USED
9025 if (!tp->vlgrp &&
9026 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9027 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9028 #else
9029 /* By definition, VLAN is disabled always in this
9030 * case.
9031 */
9032 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9033 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9034 #endif
9035
9036 if (dev->flags & IFF_PROMISC) {
9037 /* Promiscuous mode. */
9038 rx_mode |= RX_MODE_PROMISC;
9039 } else if (dev->flags & IFF_ALLMULTI) {
9040 /* Accept all multicast. */
9041 tg3_set_multi (tp, 1);
9042 } else if (dev->mc_count < 1) {
9043 /* Reject all multicast. */
9044 tg3_set_multi (tp, 0);
9045 } else {
9046 /* Accept one or more multicast(s). */
9047 struct dev_mc_list *mclist;
9048 unsigned int i;
9049 u32 mc_filter[4] = { 0, };
9050 u32 regidx;
9051 u32 bit;
9052 u32 crc;
9053
9054 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9055 i++, mclist = mclist->next) {
9056
9057 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9058 bit = ~crc & 0x7f;
9059 regidx = (bit & 0x60) >> 5;
9060 bit &= 0x1f;
9061 mc_filter[regidx] |= (1 << bit);
9062 }
9063
9064 tw32(MAC_HASH_REG_0, mc_filter[0]);
9065 tw32(MAC_HASH_REG_1, mc_filter[1]);
9066 tw32(MAC_HASH_REG_2, mc_filter[2]);
9067 tw32(MAC_HASH_REG_3, mc_filter[3]);
9068 }
9069
9070 if (rx_mode != tp->rx_mode) {
9071 tp->rx_mode = rx_mode;
9072 tw32_f(MAC_RX_MODE, rx_mode);
9073 udelay(10);
9074 }
9075 }
9076
9077 static void tg3_set_rx_mode(struct net_device *dev)
9078 {
9079 struct tg3 *tp = netdev_priv(dev);
9080
9081 if (!netif_running(dev))
9082 return;
9083
9084 tg3_full_lock(tp, 0);
9085 __tg3_set_rx_mode(dev);
9086 tg3_full_unlock(tp);
9087 }
9088
9089 #define TG3_REGDUMP_LEN (32 * 1024)
9090
9091 static int tg3_get_regs_len(struct net_device *dev)
9092 {
9093 return TG3_REGDUMP_LEN;
9094 }
9095
9096 static void tg3_get_regs(struct net_device *dev,
9097 struct ethtool_regs *regs, void *_p)
9098 {
9099 u32 *p = _p;
9100 struct tg3 *tp = netdev_priv(dev);
9101 u8 *orig_p = _p;
9102 int i;
9103
9104 regs->version = 0;
9105
9106 memset(p, 0, TG3_REGDUMP_LEN);
9107
9108 if (tp->link_config.phy_is_low_power)
9109 return;
9110
9111 tg3_full_lock(tp, 0);
9112
9113 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
9114 #define GET_REG32_LOOP(base,len) \
9115 do { p = (u32 *)(orig_p + (base)); \
9116 for (i = 0; i < len; i += 4) \
9117 __GET_REG32((base) + i); \
9118 } while (0)
9119 #define GET_REG32_1(reg) \
9120 do { p = (u32 *)(orig_p + (reg)); \
9121 __GET_REG32((reg)); \
9122 } while (0)
9123
9124 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9125 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9126 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9127 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9128 GET_REG32_1(SNDDATAC_MODE);
9129 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9130 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9131 GET_REG32_1(SNDBDC_MODE);
9132 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9133 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9134 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9135 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9136 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9137 GET_REG32_1(RCVDCC_MODE);
9138 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9139 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9140 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9141 GET_REG32_1(MBFREE_MODE);
9142 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9143 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9144 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9145 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9146 GET_REG32_LOOP(WDMAC_MODE, 0x08);
9147 GET_REG32_1(RX_CPU_MODE);
9148 GET_REG32_1(RX_CPU_STATE);
9149 GET_REG32_1(RX_CPU_PGMCTR);
9150 GET_REG32_1(RX_CPU_HWBKPT);
9151 GET_REG32_1(TX_CPU_MODE);
9152 GET_REG32_1(TX_CPU_STATE);
9153 GET_REG32_1(TX_CPU_PGMCTR);
9154 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9155 GET_REG32_LOOP(FTQ_RESET, 0x120);
9156 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9157 GET_REG32_1(DMAC_MODE);
9158 GET_REG32_LOOP(GRC_MODE, 0x4c);
9159 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9160 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9161
9162 #undef __GET_REG32
9163 #undef GET_REG32_LOOP
9164 #undef GET_REG32_1
9165
9166 tg3_full_unlock(tp);
9167 }
9168
9169 static int tg3_get_eeprom_len(struct net_device *dev)
9170 {
9171 struct tg3 *tp = netdev_priv(dev);
9172
9173 return tp->nvram_size;
9174 }
9175
9176 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9177 {
9178 struct tg3 *tp = netdev_priv(dev);
9179 int ret;
9180 u8 *pd;
9181 u32 i, offset, len, b_offset, b_count;
9182 __be32 val;
9183
9184 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9185 return -EINVAL;
9186
9187 if (tp->link_config.phy_is_low_power)
9188 return -EAGAIN;
9189
9190 offset = eeprom->offset;
9191 len = eeprom->len;
9192 eeprom->len = 0;
9193
9194 eeprom->magic = TG3_EEPROM_MAGIC;
9195
9196 if (offset & 3) {
9197 /* adjustments to start on required 4 byte boundary */
9198 b_offset = offset & 3;
9199 b_count = 4 - b_offset;
9200 if (b_count > len) {
9201 /* i.e. offset=1 len=2 */
9202 b_count = len;
9203 }
9204 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9205 if (ret)
9206 return ret;
9207 memcpy(data, ((char*)&val) + b_offset, b_count);
9208 len -= b_count;
9209 offset += b_count;
9210 eeprom->len += b_count;
9211 }
9212
9213 /* read bytes upto the last 4 byte boundary */
9214 pd = &data[eeprom->len];
9215 for (i = 0; i < (len - (len & 3)); i += 4) {
9216 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9217 if (ret) {
9218 eeprom->len += i;
9219 return ret;
9220 }
9221 memcpy(pd + i, &val, 4);
9222 }
9223 eeprom->len += i;
9224
9225 if (len & 3) {
9226 /* read last bytes not ending on 4 byte boundary */
9227 pd = &data[eeprom->len];
9228 b_count = len & 3;
9229 b_offset = offset + len - b_count;
9230 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9231 if (ret)
9232 return ret;
9233 memcpy(pd, &val, b_count);
9234 eeprom->len += b_count;
9235 }
9236 return 0;
9237 }
9238
9239 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9240
9241 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9242 {
9243 struct tg3 *tp = netdev_priv(dev);
9244 int ret;
9245 u32 offset, len, b_offset, odd_len;
9246 u8 *buf;
9247 __be32 start, end;
9248
9249 if (tp->link_config.phy_is_low_power)
9250 return -EAGAIN;
9251
9252 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9253 eeprom->magic != TG3_EEPROM_MAGIC)
9254 return -EINVAL;
9255
9256 offset = eeprom->offset;
9257 len = eeprom->len;
9258
9259 if ((b_offset = (offset & 3))) {
9260 /* adjustments to start on required 4 byte boundary */
9261 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9262 if (ret)
9263 return ret;
9264 len += b_offset;
9265 offset &= ~3;
9266 if (len < 4)
9267 len = 4;
9268 }
9269
9270 odd_len = 0;
9271 if (len & 3) {
9272 /* adjustments to end on required 4 byte boundary */
9273 odd_len = 1;
9274 len = (len + 3) & ~3;
9275 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9276 if (ret)
9277 return ret;
9278 }
9279
9280 buf = data;
9281 if (b_offset || odd_len) {
9282 buf = kmalloc(len, GFP_KERNEL);
9283 if (!buf)
9284 return -ENOMEM;
9285 if (b_offset)
9286 memcpy(buf, &start, 4);
9287 if (odd_len)
9288 memcpy(buf+len-4, &end, 4);
9289 memcpy(buf + b_offset, data, eeprom->len);
9290 }
9291
9292 ret = tg3_nvram_write_block(tp, offset, len, buf);
9293
9294 if (buf != data)
9295 kfree(buf);
9296
9297 return ret;
9298 }
9299
9300 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9301 {
9302 struct tg3 *tp = netdev_priv(dev);
9303
9304 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9305 struct phy_device *phydev;
9306 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9307 return -EAGAIN;
9308 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9309 return phy_ethtool_gset(phydev, cmd);
9310 }
9311
9312 cmd->supported = (SUPPORTED_Autoneg);
9313
9314 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9315 cmd->supported |= (SUPPORTED_1000baseT_Half |
9316 SUPPORTED_1000baseT_Full);
9317
9318 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9319 cmd->supported |= (SUPPORTED_100baseT_Half |
9320 SUPPORTED_100baseT_Full |
9321 SUPPORTED_10baseT_Half |
9322 SUPPORTED_10baseT_Full |
9323 SUPPORTED_TP);
9324 cmd->port = PORT_TP;
9325 } else {
9326 cmd->supported |= SUPPORTED_FIBRE;
9327 cmd->port = PORT_FIBRE;
9328 }
9329
9330 cmd->advertising = tp->link_config.advertising;
9331 if (netif_running(dev)) {
9332 cmd->speed = tp->link_config.active_speed;
9333 cmd->duplex = tp->link_config.active_duplex;
9334 }
9335 cmd->phy_address = tp->phy_addr;
9336 cmd->transceiver = XCVR_INTERNAL;
9337 cmd->autoneg = tp->link_config.autoneg;
9338 cmd->maxtxpkt = 0;
9339 cmd->maxrxpkt = 0;
9340 return 0;
9341 }
9342
9343 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9344 {
9345 struct tg3 *tp = netdev_priv(dev);
9346
9347 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9348 struct phy_device *phydev;
9349 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9350 return -EAGAIN;
9351 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9352 return phy_ethtool_sset(phydev, cmd);
9353 }
9354
9355 if (cmd->autoneg != AUTONEG_ENABLE &&
9356 cmd->autoneg != AUTONEG_DISABLE)
9357 return -EINVAL;
9358
9359 if (cmd->autoneg == AUTONEG_DISABLE &&
9360 cmd->duplex != DUPLEX_FULL &&
9361 cmd->duplex != DUPLEX_HALF)
9362 return -EINVAL;
9363
9364 if (cmd->autoneg == AUTONEG_ENABLE) {
9365 u32 mask = ADVERTISED_Autoneg |
9366 ADVERTISED_Pause |
9367 ADVERTISED_Asym_Pause;
9368
9369 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9370 mask |= ADVERTISED_1000baseT_Half |
9371 ADVERTISED_1000baseT_Full;
9372
9373 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9374 mask |= ADVERTISED_100baseT_Half |
9375 ADVERTISED_100baseT_Full |
9376 ADVERTISED_10baseT_Half |
9377 ADVERTISED_10baseT_Full |
9378 ADVERTISED_TP;
9379 else
9380 mask |= ADVERTISED_FIBRE;
9381
9382 if (cmd->advertising & ~mask)
9383 return -EINVAL;
9384
9385 mask &= (ADVERTISED_1000baseT_Half |
9386 ADVERTISED_1000baseT_Full |
9387 ADVERTISED_100baseT_Half |
9388 ADVERTISED_100baseT_Full |
9389 ADVERTISED_10baseT_Half |
9390 ADVERTISED_10baseT_Full);
9391
9392 cmd->advertising &= mask;
9393 } else {
9394 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9395 if (cmd->speed != SPEED_1000)
9396 return -EINVAL;
9397
9398 if (cmd->duplex != DUPLEX_FULL)
9399 return -EINVAL;
9400 } else {
9401 if (cmd->speed != SPEED_100 &&
9402 cmd->speed != SPEED_10)
9403 return -EINVAL;
9404 }
9405 }
9406
9407 tg3_full_lock(tp, 0);
9408
9409 tp->link_config.autoneg = cmd->autoneg;
9410 if (cmd->autoneg == AUTONEG_ENABLE) {
9411 tp->link_config.advertising = (cmd->advertising |
9412 ADVERTISED_Autoneg);
9413 tp->link_config.speed = SPEED_INVALID;
9414 tp->link_config.duplex = DUPLEX_INVALID;
9415 } else {
9416 tp->link_config.advertising = 0;
9417 tp->link_config.speed = cmd->speed;
9418 tp->link_config.duplex = cmd->duplex;
9419 }
9420
9421 tp->link_config.orig_speed = tp->link_config.speed;
9422 tp->link_config.orig_duplex = tp->link_config.duplex;
9423 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9424
9425 if (netif_running(dev))
9426 tg3_setup_phy(tp, 1);
9427
9428 tg3_full_unlock(tp);
9429
9430 return 0;
9431 }
9432
9433 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9434 {
9435 struct tg3 *tp = netdev_priv(dev);
9436
9437 strcpy(info->driver, DRV_MODULE_NAME);
9438 strcpy(info->version, DRV_MODULE_VERSION);
9439 strcpy(info->fw_version, tp->fw_ver);
9440 strcpy(info->bus_info, pci_name(tp->pdev));
9441 }
9442
9443 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9444 {
9445 struct tg3 *tp = netdev_priv(dev);
9446
9447 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9448 device_can_wakeup(&tp->pdev->dev))
9449 wol->supported = WAKE_MAGIC;
9450 else
9451 wol->supported = 0;
9452 wol->wolopts = 0;
9453 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9454 device_can_wakeup(&tp->pdev->dev))
9455 wol->wolopts = WAKE_MAGIC;
9456 memset(&wol->sopass, 0, sizeof(wol->sopass));
9457 }
9458
9459 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9460 {
9461 struct tg3 *tp = netdev_priv(dev);
9462 struct device *dp = &tp->pdev->dev;
9463
9464 if (wol->wolopts & ~WAKE_MAGIC)
9465 return -EINVAL;
9466 if ((wol->wolopts & WAKE_MAGIC) &&
9467 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9468 return -EINVAL;
9469
9470 spin_lock_bh(&tp->lock);
9471 if (wol->wolopts & WAKE_MAGIC) {
9472 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9473 device_set_wakeup_enable(dp, true);
9474 } else {
9475 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9476 device_set_wakeup_enable(dp, false);
9477 }
9478 spin_unlock_bh(&tp->lock);
9479
9480 return 0;
9481 }
9482
9483 static u32 tg3_get_msglevel(struct net_device *dev)
9484 {
9485 struct tg3 *tp = netdev_priv(dev);
9486 return tp->msg_enable;
9487 }
9488
9489 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9490 {
9491 struct tg3 *tp = netdev_priv(dev);
9492 tp->msg_enable = value;
9493 }
9494
9495 static int tg3_set_tso(struct net_device *dev, u32 value)
9496 {
9497 struct tg3 *tp = netdev_priv(dev);
9498
9499 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9500 if (value)
9501 return -EINVAL;
9502 return 0;
9503 }
9504 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9505 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9506 if (value) {
9507 dev->features |= NETIF_F_TSO6;
9508 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9509 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9510 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9511 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9512 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
9513 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
9514 dev->features |= NETIF_F_TSO_ECN;
9515 } else
9516 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9517 }
9518 return ethtool_op_set_tso(dev, value);
9519 }
9520
9521 static int tg3_nway_reset(struct net_device *dev)
9522 {
9523 struct tg3 *tp = netdev_priv(dev);
9524 int r;
9525
9526 if (!netif_running(dev))
9527 return -EAGAIN;
9528
9529 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9530 return -EINVAL;
9531
9532 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9533 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9534 return -EAGAIN;
9535 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9536 } else {
9537 u32 bmcr;
9538
9539 spin_lock_bh(&tp->lock);
9540 r = -EINVAL;
9541 tg3_readphy(tp, MII_BMCR, &bmcr);
9542 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9543 ((bmcr & BMCR_ANENABLE) ||
9544 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9545 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9546 BMCR_ANENABLE);
9547 r = 0;
9548 }
9549 spin_unlock_bh(&tp->lock);
9550 }
9551
9552 return r;
9553 }
9554
9555 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9556 {
9557 struct tg3 *tp = netdev_priv(dev);
9558
9559 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9560 ering->rx_mini_max_pending = 0;
9561 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9562 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9563 else
9564 ering->rx_jumbo_max_pending = 0;
9565
9566 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9567
9568 ering->rx_pending = tp->rx_pending;
9569 ering->rx_mini_pending = 0;
9570 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9571 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9572 else
9573 ering->rx_jumbo_pending = 0;
9574
9575 ering->tx_pending = tp->napi[0].tx_pending;
9576 }
9577
9578 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9579 {
9580 struct tg3 *tp = netdev_priv(dev);
9581 int i, irq_sync = 0, err = 0;
9582
9583 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9584 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9585 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9586 (ering->tx_pending <= MAX_SKB_FRAGS) ||
9587 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9588 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9589 return -EINVAL;
9590
9591 if (netif_running(dev)) {
9592 tg3_phy_stop(tp);
9593 tg3_netif_stop(tp);
9594 irq_sync = 1;
9595 }
9596
9597 tg3_full_lock(tp, irq_sync);
9598
9599 tp->rx_pending = ering->rx_pending;
9600
9601 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9602 tp->rx_pending > 63)
9603 tp->rx_pending = 63;
9604 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9605
9606 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9607 tp->napi[i].tx_pending = ering->tx_pending;
9608
9609 if (netif_running(dev)) {
9610 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9611 err = tg3_restart_hw(tp, 1);
9612 if (!err)
9613 tg3_netif_start(tp);
9614 }
9615
9616 tg3_full_unlock(tp);
9617
9618 if (irq_sync && !err)
9619 tg3_phy_start(tp);
9620
9621 return err;
9622 }
9623
9624 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9625 {
9626 struct tg3 *tp = netdev_priv(dev);
9627
9628 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9629
9630 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9631 epause->rx_pause = 1;
9632 else
9633 epause->rx_pause = 0;
9634
9635 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9636 epause->tx_pause = 1;
9637 else
9638 epause->tx_pause = 0;
9639 }
9640
9641 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9642 {
9643 struct tg3 *tp = netdev_priv(dev);
9644 int err = 0;
9645
9646 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9647 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9648 return -EAGAIN;
9649
9650 if (epause->autoneg) {
9651 u32 newadv;
9652 struct phy_device *phydev;
9653
9654 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9655
9656 if (epause->rx_pause) {
9657 if (epause->tx_pause)
9658 newadv = ADVERTISED_Pause;
9659 else
9660 newadv = ADVERTISED_Pause |
9661 ADVERTISED_Asym_Pause;
9662 } else if (epause->tx_pause) {
9663 newadv = ADVERTISED_Asym_Pause;
9664 } else
9665 newadv = 0;
9666
9667 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9668 u32 oldadv = phydev->advertising &
9669 (ADVERTISED_Pause |
9670 ADVERTISED_Asym_Pause);
9671 if (oldadv != newadv) {
9672 phydev->advertising &=
9673 ~(ADVERTISED_Pause |
9674 ADVERTISED_Asym_Pause);
9675 phydev->advertising |= newadv;
9676 err = phy_start_aneg(phydev);
9677 }
9678 } else {
9679 tp->link_config.advertising &=
9680 ~(ADVERTISED_Pause |
9681 ADVERTISED_Asym_Pause);
9682 tp->link_config.advertising |= newadv;
9683 }
9684 } else {
9685 if (epause->rx_pause)
9686 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9687 else
9688 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9689
9690 if (epause->tx_pause)
9691 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9692 else
9693 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9694
9695 if (netif_running(dev))
9696 tg3_setup_flow_control(tp, 0, 0);
9697 }
9698 } else {
9699 int irq_sync = 0;
9700
9701 if (netif_running(dev)) {
9702 tg3_netif_stop(tp);
9703 irq_sync = 1;
9704 }
9705
9706 tg3_full_lock(tp, irq_sync);
9707
9708 if (epause->autoneg)
9709 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9710 else
9711 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9712 if (epause->rx_pause)
9713 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9714 else
9715 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9716 if (epause->tx_pause)
9717 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9718 else
9719 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9720
9721 if (netif_running(dev)) {
9722 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9723 err = tg3_restart_hw(tp, 1);
9724 if (!err)
9725 tg3_netif_start(tp);
9726 }
9727
9728 tg3_full_unlock(tp);
9729 }
9730
9731 return err;
9732 }
9733
9734 static u32 tg3_get_rx_csum(struct net_device *dev)
9735 {
9736 struct tg3 *tp = netdev_priv(dev);
9737 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9738 }
9739
9740 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9741 {
9742 struct tg3 *tp = netdev_priv(dev);
9743
9744 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9745 if (data != 0)
9746 return -EINVAL;
9747 return 0;
9748 }
9749
9750 spin_lock_bh(&tp->lock);
9751 if (data)
9752 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9753 else
9754 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9755 spin_unlock_bh(&tp->lock);
9756
9757 return 0;
9758 }
9759
9760 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9761 {
9762 struct tg3 *tp = netdev_priv(dev);
9763
9764 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9765 if (data != 0)
9766 return -EINVAL;
9767 return 0;
9768 }
9769
9770 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9771 ethtool_op_set_tx_ipv6_csum(dev, data);
9772 else
9773 ethtool_op_set_tx_csum(dev, data);
9774
9775 return 0;
9776 }
9777
9778 static int tg3_get_sset_count (struct net_device *dev, int sset)
9779 {
9780 switch (sset) {
9781 case ETH_SS_TEST:
9782 return TG3_NUM_TEST;
9783 case ETH_SS_STATS:
9784 return TG3_NUM_STATS;
9785 default:
9786 return -EOPNOTSUPP;
9787 }
9788 }
9789
9790 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9791 {
9792 switch (stringset) {
9793 case ETH_SS_STATS:
9794 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9795 break;
9796 case ETH_SS_TEST:
9797 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9798 break;
9799 default:
9800 WARN_ON(1); /* we need a WARN() */
9801 break;
9802 }
9803 }
9804
9805 static int tg3_phys_id(struct net_device *dev, u32 data)
9806 {
9807 struct tg3 *tp = netdev_priv(dev);
9808 int i;
9809
9810 if (!netif_running(tp->dev))
9811 return -EAGAIN;
9812
9813 if (data == 0)
9814 data = UINT_MAX / 2;
9815
9816 for (i = 0; i < (data * 2); i++) {
9817 if ((i % 2) == 0)
9818 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9819 LED_CTRL_1000MBPS_ON |
9820 LED_CTRL_100MBPS_ON |
9821 LED_CTRL_10MBPS_ON |
9822 LED_CTRL_TRAFFIC_OVERRIDE |
9823 LED_CTRL_TRAFFIC_BLINK |
9824 LED_CTRL_TRAFFIC_LED);
9825
9826 else
9827 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9828 LED_CTRL_TRAFFIC_OVERRIDE);
9829
9830 if (msleep_interruptible(500))
9831 break;
9832 }
9833 tw32(MAC_LED_CTRL, tp->led_ctrl);
9834 return 0;
9835 }
9836
9837 static void tg3_get_ethtool_stats (struct net_device *dev,
9838 struct ethtool_stats *estats, u64 *tmp_stats)
9839 {
9840 struct tg3 *tp = netdev_priv(dev);
9841 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9842 }
9843
9844 #define NVRAM_TEST_SIZE 0x100
9845 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9846 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9847 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
9848 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9849 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9850
9851 static int tg3_test_nvram(struct tg3 *tp)
9852 {
9853 u32 csum, magic;
9854 __be32 *buf;
9855 int i, j, k, err = 0, size;
9856
9857 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9858 return 0;
9859
9860 if (tg3_nvram_read(tp, 0, &magic) != 0)
9861 return -EIO;
9862
9863 if (magic == TG3_EEPROM_MAGIC)
9864 size = NVRAM_TEST_SIZE;
9865 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9866 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9867 TG3_EEPROM_SB_FORMAT_1) {
9868 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9869 case TG3_EEPROM_SB_REVISION_0:
9870 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9871 break;
9872 case TG3_EEPROM_SB_REVISION_2:
9873 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9874 break;
9875 case TG3_EEPROM_SB_REVISION_3:
9876 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9877 break;
9878 default:
9879 return 0;
9880 }
9881 } else
9882 return 0;
9883 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9884 size = NVRAM_SELFBOOT_HW_SIZE;
9885 else
9886 return -EIO;
9887
9888 buf = kmalloc(size, GFP_KERNEL);
9889 if (buf == NULL)
9890 return -ENOMEM;
9891
9892 err = -EIO;
9893 for (i = 0, j = 0; i < size; i += 4, j++) {
9894 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9895 if (err)
9896 break;
9897 }
9898 if (i < size)
9899 goto out;
9900
9901 /* Selfboot format */
9902 magic = be32_to_cpu(buf[0]);
9903 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9904 TG3_EEPROM_MAGIC_FW) {
9905 u8 *buf8 = (u8 *) buf, csum8 = 0;
9906
9907 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9908 TG3_EEPROM_SB_REVISION_2) {
9909 /* For rev 2, the csum doesn't include the MBA. */
9910 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9911 csum8 += buf8[i];
9912 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9913 csum8 += buf8[i];
9914 } else {
9915 for (i = 0; i < size; i++)
9916 csum8 += buf8[i];
9917 }
9918
9919 if (csum8 == 0) {
9920 err = 0;
9921 goto out;
9922 }
9923
9924 err = -EIO;
9925 goto out;
9926 }
9927
9928 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9929 TG3_EEPROM_MAGIC_HW) {
9930 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9931 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9932 u8 *buf8 = (u8 *) buf;
9933
9934 /* Separate the parity bits and the data bytes. */
9935 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9936 if ((i == 0) || (i == 8)) {
9937 int l;
9938 u8 msk;
9939
9940 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9941 parity[k++] = buf8[i] & msk;
9942 i++;
9943 }
9944 else if (i == 16) {
9945 int l;
9946 u8 msk;
9947
9948 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9949 parity[k++] = buf8[i] & msk;
9950 i++;
9951
9952 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9953 parity[k++] = buf8[i] & msk;
9954 i++;
9955 }
9956 data[j++] = buf8[i];
9957 }
9958
9959 err = -EIO;
9960 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9961 u8 hw8 = hweight8(data[i]);
9962
9963 if ((hw8 & 0x1) && parity[i])
9964 goto out;
9965 else if (!(hw8 & 0x1) && !parity[i])
9966 goto out;
9967 }
9968 err = 0;
9969 goto out;
9970 }
9971
9972 /* Bootstrap checksum at offset 0x10 */
9973 csum = calc_crc((unsigned char *) buf, 0x10);
9974 if (csum != be32_to_cpu(buf[0x10/4]))
9975 goto out;
9976
9977 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9978 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9979 if (csum != be32_to_cpu(buf[0xfc/4]))
9980 goto out;
9981
9982 err = 0;
9983
9984 out:
9985 kfree(buf);
9986 return err;
9987 }
9988
9989 #define TG3_SERDES_TIMEOUT_SEC 2
9990 #define TG3_COPPER_TIMEOUT_SEC 6
9991
9992 static int tg3_test_link(struct tg3 *tp)
9993 {
9994 int i, max;
9995
9996 if (!netif_running(tp->dev))
9997 return -ENODEV;
9998
9999 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10000 max = TG3_SERDES_TIMEOUT_SEC;
10001 else
10002 max = TG3_COPPER_TIMEOUT_SEC;
10003
10004 for (i = 0; i < max; i++) {
10005 if (netif_carrier_ok(tp->dev))
10006 return 0;
10007
10008 if (msleep_interruptible(1000))
10009 break;
10010 }
10011
10012 return -EIO;
10013 }
10014
10015 /* Only test the commonly used registers */
10016 static int tg3_test_registers(struct tg3 *tp)
10017 {
10018 int i, is_5705, is_5750;
10019 u32 offset, read_mask, write_mask, val, save_val, read_val;
10020 static struct {
10021 u16 offset;
10022 u16 flags;
10023 #define TG3_FL_5705 0x1
10024 #define TG3_FL_NOT_5705 0x2
10025 #define TG3_FL_NOT_5788 0x4
10026 #define TG3_FL_NOT_5750 0x8
10027 u32 read_mask;
10028 u32 write_mask;
10029 } reg_tbl[] = {
10030 /* MAC Control Registers */
10031 { MAC_MODE, TG3_FL_NOT_5705,
10032 0x00000000, 0x00ef6f8c },
10033 { MAC_MODE, TG3_FL_5705,
10034 0x00000000, 0x01ef6b8c },
10035 { MAC_STATUS, TG3_FL_NOT_5705,
10036 0x03800107, 0x00000000 },
10037 { MAC_STATUS, TG3_FL_5705,
10038 0x03800100, 0x00000000 },
10039 { MAC_ADDR_0_HIGH, 0x0000,
10040 0x00000000, 0x0000ffff },
10041 { MAC_ADDR_0_LOW, 0x0000,
10042 0x00000000, 0xffffffff },
10043 { MAC_RX_MTU_SIZE, 0x0000,
10044 0x00000000, 0x0000ffff },
10045 { MAC_TX_MODE, 0x0000,
10046 0x00000000, 0x00000070 },
10047 { MAC_TX_LENGTHS, 0x0000,
10048 0x00000000, 0x00003fff },
10049 { MAC_RX_MODE, TG3_FL_NOT_5705,
10050 0x00000000, 0x000007fc },
10051 { MAC_RX_MODE, TG3_FL_5705,
10052 0x00000000, 0x000007dc },
10053 { MAC_HASH_REG_0, 0x0000,
10054 0x00000000, 0xffffffff },
10055 { MAC_HASH_REG_1, 0x0000,
10056 0x00000000, 0xffffffff },
10057 { MAC_HASH_REG_2, 0x0000,
10058 0x00000000, 0xffffffff },
10059 { MAC_HASH_REG_3, 0x0000,
10060 0x00000000, 0xffffffff },
10061
10062 /* Receive Data and Receive BD Initiator Control Registers. */
10063 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10064 0x00000000, 0xffffffff },
10065 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10066 0x00000000, 0xffffffff },
10067 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10068 0x00000000, 0x00000003 },
10069 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10070 0x00000000, 0xffffffff },
10071 { RCVDBDI_STD_BD+0, 0x0000,
10072 0x00000000, 0xffffffff },
10073 { RCVDBDI_STD_BD+4, 0x0000,
10074 0x00000000, 0xffffffff },
10075 { RCVDBDI_STD_BD+8, 0x0000,
10076 0x00000000, 0xffff0002 },
10077 { RCVDBDI_STD_BD+0xc, 0x0000,
10078 0x00000000, 0xffffffff },
10079
10080 /* Receive BD Initiator Control Registers. */
10081 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10082 0x00000000, 0xffffffff },
10083 { RCVBDI_STD_THRESH, TG3_FL_5705,
10084 0x00000000, 0x000003ff },
10085 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10086 0x00000000, 0xffffffff },
10087
10088 /* Host Coalescing Control Registers. */
10089 { HOSTCC_MODE, TG3_FL_NOT_5705,
10090 0x00000000, 0x00000004 },
10091 { HOSTCC_MODE, TG3_FL_5705,
10092 0x00000000, 0x000000f6 },
10093 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10094 0x00000000, 0xffffffff },
10095 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10096 0x00000000, 0x000003ff },
10097 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10098 0x00000000, 0xffffffff },
10099 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10100 0x00000000, 0x000003ff },
10101 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10102 0x00000000, 0xffffffff },
10103 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10104 0x00000000, 0x000000ff },
10105 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10106 0x00000000, 0xffffffff },
10107 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10108 0x00000000, 0x000000ff },
10109 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10110 0x00000000, 0xffffffff },
10111 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10112 0x00000000, 0xffffffff },
10113 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10114 0x00000000, 0xffffffff },
10115 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10116 0x00000000, 0x000000ff },
10117 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10118 0x00000000, 0xffffffff },
10119 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10120 0x00000000, 0x000000ff },
10121 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10122 0x00000000, 0xffffffff },
10123 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10124 0x00000000, 0xffffffff },
10125 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10126 0x00000000, 0xffffffff },
10127 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10128 0x00000000, 0xffffffff },
10129 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10130 0x00000000, 0xffffffff },
10131 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10132 0xffffffff, 0x00000000 },
10133 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10134 0xffffffff, 0x00000000 },
10135
10136 /* Buffer Manager Control Registers. */
10137 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10138 0x00000000, 0x007fff80 },
10139 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10140 0x00000000, 0x007fffff },
10141 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10142 0x00000000, 0x0000003f },
10143 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10144 0x00000000, 0x000001ff },
10145 { BUFMGR_MB_HIGH_WATER, 0x0000,
10146 0x00000000, 0x000001ff },
10147 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10148 0xffffffff, 0x00000000 },
10149 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10150 0xffffffff, 0x00000000 },
10151
10152 /* Mailbox Registers */
10153 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10154 0x00000000, 0x000001ff },
10155 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10156 0x00000000, 0x000001ff },
10157 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10158 0x00000000, 0x000007ff },
10159 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10160 0x00000000, 0x000001ff },
10161
10162 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10163 };
10164
10165 is_5705 = is_5750 = 0;
10166 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10167 is_5705 = 1;
10168 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10169 is_5750 = 1;
10170 }
10171
10172 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10173 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10174 continue;
10175
10176 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10177 continue;
10178
10179 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10180 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10181 continue;
10182
10183 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10184 continue;
10185
10186 offset = (u32) reg_tbl[i].offset;
10187 read_mask = reg_tbl[i].read_mask;
10188 write_mask = reg_tbl[i].write_mask;
10189
10190 /* Save the original register content */
10191 save_val = tr32(offset);
10192
10193 /* Determine the read-only value. */
10194 read_val = save_val & read_mask;
10195
10196 /* Write zero to the register, then make sure the read-only bits
10197 * are not changed and the read/write bits are all zeros.
10198 */
10199 tw32(offset, 0);
10200
10201 val = tr32(offset);
10202
10203 /* Test the read-only and read/write bits. */
10204 if (((val & read_mask) != read_val) || (val & write_mask))
10205 goto out;
10206
10207 /* Write ones to all the bits defined by RdMask and WrMask, then
10208 * make sure the read-only bits are not changed and the
10209 * read/write bits are all ones.
10210 */
10211 tw32(offset, read_mask | write_mask);
10212
10213 val = tr32(offset);
10214
10215 /* Test the read-only bits. */
10216 if ((val & read_mask) != read_val)
10217 goto out;
10218
10219 /* Test the read/write bits. */
10220 if ((val & write_mask) != write_mask)
10221 goto out;
10222
10223 tw32(offset, save_val);
10224 }
10225
10226 return 0;
10227
10228 out:
10229 if (netif_msg_hw(tp))
10230 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10231 offset);
10232 tw32(offset, save_val);
10233 return -EIO;
10234 }
10235
10236 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10237 {
10238 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10239 int i;
10240 u32 j;
10241
10242 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10243 for (j = 0; j < len; j += 4) {
10244 u32 val;
10245
10246 tg3_write_mem(tp, offset + j, test_pattern[i]);
10247 tg3_read_mem(tp, offset + j, &val);
10248 if (val != test_pattern[i])
10249 return -EIO;
10250 }
10251 }
10252 return 0;
10253 }
10254
10255 static int tg3_test_memory(struct tg3 *tp)
10256 {
10257 static struct mem_entry {
10258 u32 offset;
10259 u32 len;
10260 } mem_tbl_570x[] = {
10261 { 0x00000000, 0x00b50},
10262 { 0x00002000, 0x1c000},
10263 { 0xffffffff, 0x00000}
10264 }, mem_tbl_5705[] = {
10265 { 0x00000100, 0x0000c},
10266 { 0x00000200, 0x00008},
10267 { 0x00004000, 0x00800},
10268 { 0x00006000, 0x01000},
10269 { 0x00008000, 0x02000},
10270 { 0x00010000, 0x0e000},
10271 { 0xffffffff, 0x00000}
10272 }, mem_tbl_5755[] = {
10273 { 0x00000200, 0x00008},
10274 { 0x00004000, 0x00800},
10275 { 0x00006000, 0x00800},
10276 { 0x00008000, 0x02000},
10277 { 0x00010000, 0x0c000},
10278 { 0xffffffff, 0x00000}
10279 }, mem_tbl_5906[] = {
10280 { 0x00000200, 0x00008},
10281 { 0x00004000, 0x00400},
10282 { 0x00006000, 0x00400},
10283 { 0x00008000, 0x01000},
10284 { 0x00010000, 0x01000},
10285 { 0xffffffff, 0x00000}
10286 };
10287 struct mem_entry *mem_tbl;
10288 int err = 0;
10289 int i;
10290
10291 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10292 mem_tbl = mem_tbl_5755;
10293 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10294 mem_tbl = mem_tbl_5906;
10295 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10296 mem_tbl = mem_tbl_5705;
10297 else
10298 mem_tbl = mem_tbl_570x;
10299
10300 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10301 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10302 mem_tbl[i].len)) != 0)
10303 break;
10304 }
10305
10306 return err;
10307 }
10308
10309 #define TG3_MAC_LOOPBACK 0
10310 #define TG3_PHY_LOOPBACK 1
10311
10312 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10313 {
10314 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10315 u32 desc_idx, coal_now;
10316 struct sk_buff *skb, *rx_skb;
10317 u8 *tx_data;
10318 dma_addr_t map;
10319 int num_pkts, tx_len, rx_len, i, err;
10320 struct tg3_rx_buffer_desc *desc;
10321 struct tg3_napi *tnapi, *rnapi;
10322 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10323
10324 if (tp->irq_cnt > 1) {
10325 tnapi = &tp->napi[1];
10326 rnapi = &tp->napi[1];
10327 } else {
10328 tnapi = &tp->napi[0];
10329 rnapi = &tp->napi[0];
10330 }
10331 coal_now = tnapi->coal_now | rnapi->coal_now;
10332
10333 if (loopback_mode == TG3_MAC_LOOPBACK) {
10334 /* HW errata - mac loopback fails in some cases on 5780.
10335 * Normal traffic and PHY loopback are not affected by
10336 * errata.
10337 */
10338 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10339 return 0;
10340
10341 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10342 MAC_MODE_PORT_INT_LPBACK;
10343 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10344 mac_mode |= MAC_MODE_LINK_POLARITY;
10345 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10346 mac_mode |= MAC_MODE_PORT_MODE_MII;
10347 else
10348 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10349 tw32(MAC_MODE, mac_mode);
10350 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10351 u32 val;
10352
10353 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10354 tg3_phy_fet_toggle_apd(tp, false);
10355 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10356 } else
10357 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10358
10359 tg3_phy_toggle_automdix(tp, 0);
10360
10361 tg3_writephy(tp, MII_BMCR, val);
10362 udelay(40);
10363
10364 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10365 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10366 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10367 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
10368 mac_mode |= MAC_MODE_PORT_MODE_MII;
10369 } else
10370 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10371
10372 /* reset to prevent losing 1st rx packet intermittently */
10373 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10374 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10375 udelay(10);
10376 tw32_f(MAC_RX_MODE, tp->rx_mode);
10377 }
10378 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10379 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10380 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10381 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10382 mac_mode |= MAC_MODE_LINK_POLARITY;
10383 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10384 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10385 }
10386 tw32(MAC_MODE, mac_mode);
10387 }
10388 else
10389 return -EINVAL;
10390
10391 err = -EIO;
10392
10393 tx_len = 1514;
10394 skb = netdev_alloc_skb(tp->dev, tx_len);
10395 if (!skb)
10396 return -ENOMEM;
10397
10398 tx_data = skb_put(skb, tx_len);
10399 memcpy(tx_data, tp->dev->dev_addr, 6);
10400 memset(tx_data + 6, 0x0, 8);
10401
10402 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10403
10404 for (i = 14; i < tx_len; i++)
10405 tx_data[i] = (u8) (i & 0xff);
10406
10407 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
10408 dev_kfree_skb(skb);
10409 return -EIO;
10410 }
10411
10412 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10413 rnapi->coal_now);
10414
10415 udelay(10);
10416
10417 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10418
10419 num_pkts = 0;
10420
10421 tg3_set_txd(tnapi, tnapi->tx_prod,
10422 skb_shinfo(skb)->dma_head, tx_len, 0, 1);
10423
10424 tnapi->tx_prod++;
10425 num_pkts++;
10426
10427 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10428 tr32_mailbox(tnapi->prodmbox);
10429
10430 udelay(10);
10431
10432 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10433 for (i = 0; i < 35; i++) {
10434 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10435 coal_now);
10436
10437 udelay(10);
10438
10439 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10440 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10441 if ((tx_idx == tnapi->tx_prod) &&
10442 (rx_idx == (rx_start_idx + num_pkts)))
10443 break;
10444 }
10445
10446 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
10447 dev_kfree_skb(skb);
10448
10449 if (tx_idx != tnapi->tx_prod)
10450 goto out;
10451
10452 if (rx_idx != rx_start_idx + num_pkts)
10453 goto out;
10454
10455 desc = &rnapi->rx_rcb[rx_start_idx];
10456 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10457 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10458 if (opaque_key != RXD_OPAQUE_RING_STD)
10459 goto out;
10460
10461 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10462 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10463 goto out;
10464
10465 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10466 if (rx_len != tx_len)
10467 goto out;
10468
10469 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10470
10471 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10472 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10473
10474 for (i = 14; i < tx_len; i++) {
10475 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10476 goto out;
10477 }
10478 err = 0;
10479
10480 /* tg3_free_rings will unmap and free the rx_skb */
10481 out:
10482 return err;
10483 }
10484
10485 #define TG3_MAC_LOOPBACK_FAILED 1
10486 #define TG3_PHY_LOOPBACK_FAILED 2
10487 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10488 TG3_PHY_LOOPBACK_FAILED)
10489
10490 static int tg3_test_loopback(struct tg3 *tp)
10491 {
10492 int err = 0;
10493 u32 cpmuctrl = 0;
10494
10495 if (!netif_running(tp->dev))
10496 return TG3_LOOPBACK_FAILED;
10497
10498 err = tg3_reset_hw(tp, 1);
10499 if (err)
10500 return TG3_LOOPBACK_FAILED;
10501
10502 /* Turn off gphy autopowerdown. */
10503 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10504 tg3_phy_toggle_apd(tp, false);
10505
10506 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10507 int i;
10508 u32 status;
10509
10510 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10511
10512 /* Wait for up to 40 microseconds to acquire lock. */
10513 for (i = 0; i < 4; i++) {
10514 status = tr32(TG3_CPMU_MUTEX_GNT);
10515 if (status == CPMU_MUTEX_GNT_DRIVER)
10516 break;
10517 udelay(10);
10518 }
10519
10520 if (status != CPMU_MUTEX_GNT_DRIVER)
10521 return TG3_LOOPBACK_FAILED;
10522
10523 /* Turn off link-based power management. */
10524 cpmuctrl = tr32(TG3_CPMU_CTRL);
10525 tw32(TG3_CPMU_CTRL,
10526 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10527 CPMU_CTRL_LINK_AWARE_MODE));
10528 }
10529
10530 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10531 err |= TG3_MAC_LOOPBACK_FAILED;
10532
10533 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10534 tw32(TG3_CPMU_CTRL, cpmuctrl);
10535
10536 /* Release the mutex */
10537 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10538 }
10539
10540 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10541 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10542 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10543 err |= TG3_PHY_LOOPBACK_FAILED;
10544 }
10545
10546 /* Re-enable gphy autopowerdown. */
10547 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10548 tg3_phy_toggle_apd(tp, true);
10549
10550 return err;
10551 }
10552
10553 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10554 u64 *data)
10555 {
10556 struct tg3 *tp = netdev_priv(dev);
10557
10558 if (tp->link_config.phy_is_low_power)
10559 tg3_set_power_state(tp, PCI_D0);
10560
10561 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10562
10563 if (tg3_test_nvram(tp) != 0) {
10564 etest->flags |= ETH_TEST_FL_FAILED;
10565 data[0] = 1;
10566 }
10567 if (tg3_test_link(tp) != 0) {
10568 etest->flags |= ETH_TEST_FL_FAILED;
10569 data[1] = 1;
10570 }
10571 if (etest->flags & ETH_TEST_FL_OFFLINE) {
10572 int err, err2 = 0, irq_sync = 0;
10573
10574 if (netif_running(dev)) {
10575 tg3_phy_stop(tp);
10576 tg3_netif_stop(tp);
10577 irq_sync = 1;
10578 }
10579
10580 tg3_full_lock(tp, irq_sync);
10581
10582 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10583 err = tg3_nvram_lock(tp);
10584 tg3_halt_cpu(tp, RX_CPU_BASE);
10585 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10586 tg3_halt_cpu(tp, TX_CPU_BASE);
10587 if (!err)
10588 tg3_nvram_unlock(tp);
10589
10590 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10591 tg3_phy_reset(tp);
10592
10593 if (tg3_test_registers(tp) != 0) {
10594 etest->flags |= ETH_TEST_FL_FAILED;
10595 data[2] = 1;
10596 }
10597 if (tg3_test_memory(tp) != 0) {
10598 etest->flags |= ETH_TEST_FL_FAILED;
10599 data[3] = 1;
10600 }
10601 if ((data[4] = tg3_test_loopback(tp)) != 0)
10602 etest->flags |= ETH_TEST_FL_FAILED;
10603
10604 tg3_full_unlock(tp);
10605
10606 if (tg3_test_interrupt(tp) != 0) {
10607 etest->flags |= ETH_TEST_FL_FAILED;
10608 data[5] = 1;
10609 }
10610
10611 tg3_full_lock(tp, 0);
10612
10613 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10614 if (netif_running(dev)) {
10615 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10616 err2 = tg3_restart_hw(tp, 1);
10617 if (!err2)
10618 tg3_netif_start(tp);
10619 }
10620
10621 tg3_full_unlock(tp);
10622
10623 if (irq_sync && !err2)
10624 tg3_phy_start(tp);
10625 }
10626 if (tp->link_config.phy_is_low_power)
10627 tg3_set_power_state(tp, PCI_D3hot);
10628
10629 }
10630
10631 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10632 {
10633 struct mii_ioctl_data *data = if_mii(ifr);
10634 struct tg3 *tp = netdev_priv(dev);
10635 int err;
10636
10637 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10638 struct phy_device *phydev;
10639 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10640 return -EAGAIN;
10641 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10642 return phy_mii_ioctl(phydev, data, cmd);
10643 }
10644
10645 switch(cmd) {
10646 case SIOCGMIIPHY:
10647 data->phy_id = tp->phy_addr;
10648
10649 /* fallthru */
10650 case SIOCGMIIREG: {
10651 u32 mii_regval;
10652
10653 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10654 break; /* We have no PHY */
10655
10656 if (tp->link_config.phy_is_low_power)
10657 return -EAGAIN;
10658
10659 spin_lock_bh(&tp->lock);
10660 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10661 spin_unlock_bh(&tp->lock);
10662
10663 data->val_out = mii_regval;
10664
10665 return err;
10666 }
10667
10668 case SIOCSMIIREG:
10669 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10670 break; /* We have no PHY */
10671
10672 if (tp->link_config.phy_is_low_power)
10673 return -EAGAIN;
10674
10675 spin_lock_bh(&tp->lock);
10676 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10677 spin_unlock_bh(&tp->lock);
10678
10679 return err;
10680
10681 default:
10682 /* do nothing */
10683 break;
10684 }
10685 return -EOPNOTSUPP;
10686 }
10687
10688 #if TG3_VLAN_TAG_USED
10689 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10690 {
10691 struct tg3 *tp = netdev_priv(dev);
10692
10693 if (!netif_running(dev)) {
10694 tp->vlgrp = grp;
10695 return;
10696 }
10697
10698 tg3_netif_stop(tp);
10699
10700 tg3_full_lock(tp, 0);
10701
10702 tp->vlgrp = grp;
10703
10704 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10705 __tg3_set_rx_mode(dev);
10706
10707 tg3_netif_start(tp);
10708
10709 tg3_full_unlock(tp);
10710 }
10711 #endif
10712
10713 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10714 {
10715 struct tg3 *tp = netdev_priv(dev);
10716
10717 memcpy(ec, &tp->coal, sizeof(*ec));
10718 return 0;
10719 }
10720
10721 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10722 {
10723 struct tg3 *tp = netdev_priv(dev);
10724 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10725 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10726
10727 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10728 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10729 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10730 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10731 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10732 }
10733
10734 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10735 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10736 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10737 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10738 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10739 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10740 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10741 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10742 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10743 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10744 return -EINVAL;
10745
10746 /* No rx interrupts will be generated if both are zero */
10747 if ((ec->rx_coalesce_usecs == 0) &&
10748 (ec->rx_max_coalesced_frames == 0))
10749 return -EINVAL;
10750
10751 /* No tx interrupts will be generated if both are zero */
10752 if ((ec->tx_coalesce_usecs == 0) &&
10753 (ec->tx_max_coalesced_frames == 0))
10754 return -EINVAL;
10755
10756 /* Only copy relevant parameters, ignore all others. */
10757 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10758 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10759 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10760 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10761 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10762 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10763 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10764 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10765 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10766
10767 if (netif_running(dev)) {
10768 tg3_full_lock(tp, 0);
10769 __tg3_set_coalesce(tp, &tp->coal);
10770 tg3_full_unlock(tp);
10771 }
10772 return 0;
10773 }
10774
10775 static const struct ethtool_ops tg3_ethtool_ops = {
10776 .get_settings = tg3_get_settings,
10777 .set_settings = tg3_set_settings,
10778 .get_drvinfo = tg3_get_drvinfo,
10779 .get_regs_len = tg3_get_regs_len,
10780 .get_regs = tg3_get_regs,
10781 .get_wol = tg3_get_wol,
10782 .set_wol = tg3_set_wol,
10783 .get_msglevel = tg3_get_msglevel,
10784 .set_msglevel = tg3_set_msglevel,
10785 .nway_reset = tg3_nway_reset,
10786 .get_link = ethtool_op_get_link,
10787 .get_eeprom_len = tg3_get_eeprom_len,
10788 .get_eeprom = tg3_get_eeprom,
10789 .set_eeprom = tg3_set_eeprom,
10790 .get_ringparam = tg3_get_ringparam,
10791 .set_ringparam = tg3_set_ringparam,
10792 .get_pauseparam = tg3_get_pauseparam,
10793 .set_pauseparam = tg3_set_pauseparam,
10794 .get_rx_csum = tg3_get_rx_csum,
10795 .set_rx_csum = tg3_set_rx_csum,
10796 .set_tx_csum = tg3_set_tx_csum,
10797 .set_sg = ethtool_op_set_sg,
10798 .set_tso = tg3_set_tso,
10799 .self_test = tg3_self_test,
10800 .get_strings = tg3_get_strings,
10801 .phys_id = tg3_phys_id,
10802 .get_ethtool_stats = tg3_get_ethtool_stats,
10803 .get_coalesce = tg3_get_coalesce,
10804 .set_coalesce = tg3_set_coalesce,
10805 .get_sset_count = tg3_get_sset_count,
10806 };
10807
10808 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10809 {
10810 u32 cursize, val, magic;
10811
10812 tp->nvram_size = EEPROM_CHIP_SIZE;
10813
10814 if (tg3_nvram_read(tp, 0, &magic) != 0)
10815 return;
10816
10817 if ((magic != TG3_EEPROM_MAGIC) &&
10818 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10819 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10820 return;
10821
10822 /*
10823 * Size the chip by reading offsets at increasing powers of two.
10824 * When we encounter our validation signature, we know the addressing
10825 * has wrapped around, and thus have our chip size.
10826 */
10827 cursize = 0x10;
10828
10829 while (cursize < tp->nvram_size) {
10830 if (tg3_nvram_read(tp, cursize, &val) != 0)
10831 return;
10832
10833 if (val == magic)
10834 break;
10835
10836 cursize <<= 1;
10837 }
10838
10839 tp->nvram_size = cursize;
10840 }
10841
10842 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10843 {
10844 u32 val;
10845
10846 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10847 tg3_nvram_read(tp, 0, &val) != 0)
10848 return;
10849
10850 /* Selfboot format */
10851 if (val != TG3_EEPROM_MAGIC) {
10852 tg3_get_eeprom_size(tp);
10853 return;
10854 }
10855
10856 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10857 if (val != 0) {
10858 /* This is confusing. We want to operate on the
10859 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10860 * call will read from NVRAM and byteswap the data
10861 * according to the byteswapping settings for all
10862 * other register accesses. This ensures the data we
10863 * want will always reside in the lower 16-bits.
10864 * However, the data in NVRAM is in LE format, which
10865 * means the data from the NVRAM read will always be
10866 * opposite the endianness of the CPU. The 16-bit
10867 * byteswap then brings the data to CPU endianness.
10868 */
10869 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
10870 return;
10871 }
10872 }
10873 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10874 }
10875
10876 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10877 {
10878 u32 nvcfg1;
10879
10880 nvcfg1 = tr32(NVRAM_CFG1);
10881 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10882 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10883 } else {
10884 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10885 tw32(NVRAM_CFG1, nvcfg1);
10886 }
10887
10888 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10889 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10890 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10891 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10892 tp->nvram_jedecnum = JEDEC_ATMEL;
10893 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10894 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10895 break;
10896 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10897 tp->nvram_jedecnum = JEDEC_ATMEL;
10898 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10899 break;
10900 case FLASH_VENDOR_ATMEL_EEPROM:
10901 tp->nvram_jedecnum = JEDEC_ATMEL;
10902 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10903 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10904 break;
10905 case FLASH_VENDOR_ST:
10906 tp->nvram_jedecnum = JEDEC_ST;
10907 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10908 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10909 break;
10910 case FLASH_VENDOR_SAIFUN:
10911 tp->nvram_jedecnum = JEDEC_SAIFUN;
10912 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10913 break;
10914 case FLASH_VENDOR_SST_SMALL:
10915 case FLASH_VENDOR_SST_LARGE:
10916 tp->nvram_jedecnum = JEDEC_SST;
10917 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10918 break;
10919 }
10920 } else {
10921 tp->nvram_jedecnum = JEDEC_ATMEL;
10922 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10923 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10924 }
10925 }
10926
10927 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
10928 {
10929 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10930 case FLASH_5752PAGE_SIZE_256:
10931 tp->nvram_pagesize = 256;
10932 break;
10933 case FLASH_5752PAGE_SIZE_512:
10934 tp->nvram_pagesize = 512;
10935 break;
10936 case FLASH_5752PAGE_SIZE_1K:
10937 tp->nvram_pagesize = 1024;
10938 break;
10939 case FLASH_5752PAGE_SIZE_2K:
10940 tp->nvram_pagesize = 2048;
10941 break;
10942 case FLASH_5752PAGE_SIZE_4K:
10943 tp->nvram_pagesize = 4096;
10944 break;
10945 case FLASH_5752PAGE_SIZE_264:
10946 tp->nvram_pagesize = 264;
10947 break;
10948 case FLASH_5752PAGE_SIZE_528:
10949 tp->nvram_pagesize = 528;
10950 break;
10951 }
10952 }
10953
10954 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10955 {
10956 u32 nvcfg1;
10957
10958 nvcfg1 = tr32(NVRAM_CFG1);
10959
10960 /* NVRAM protection for TPM */
10961 if (nvcfg1 & (1 << 27))
10962 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10963
10964 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10965 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10966 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10967 tp->nvram_jedecnum = JEDEC_ATMEL;
10968 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10969 break;
10970 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10971 tp->nvram_jedecnum = JEDEC_ATMEL;
10972 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10973 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10974 break;
10975 case FLASH_5752VENDOR_ST_M45PE10:
10976 case FLASH_5752VENDOR_ST_M45PE20:
10977 case FLASH_5752VENDOR_ST_M45PE40:
10978 tp->nvram_jedecnum = JEDEC_ST;
10979 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10980 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10981 break;
10982 }
10983
10984 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10985 tg3_nvram_get_pagesize(tp, nvcfg1);
10986 } else {
10987 /* For eeprom, set pagesize to maximum eeprom size */
10988 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10989
10990 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10991 tw32(NVRAM_CFG1, nvcfg1);
10992 }
10993 }
10994
10995 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10996 {
10997 u32 nvcfg1, protect = 0;
10998
10999 nvcfg1 = tr32(NVRAM_CFG1);
11000
11001 /* NVRAM protection for TPM */
11002 if (nvcfg1 & (1 << 27)) {
11003 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
11004 protect = 1;
11005 }
11006
11007 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11008 switch (nvcfg1) {
11009 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11010 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11011 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11012 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11013 tp->nvram_jedecnum = JEDEC_ATMEL;
11014 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11015 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11016 tp->nvram_pagesize = 264;
11017 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11018 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11019 tp->nvram_size = (protect ? 0x3e200 :
11020 TG3_NVRAM_SIZE_512KB);
11021 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11022 tp->nvram_size = (protect ? 0x1f200 :
11023 TG3_NVRAM_SIZE_256KB);
11024 else
11025 tp->nvram_size = (protect ? 0x1f200 :
11026 TG3_NVRAM_SIZE_128KB);
11027 break;
11028 case FLASH_5752VENDOR_ST_M45PE10:
11029 case FLASH_5752VENDOR_ST_M45PE20:
11030 case FLASH_5752VENDOR_ST_M45PE40:
11031 tp->nvram_jedecnum = JEDEC_ST;
11032 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11033 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11034 tp->nvram_pagesize = 256;
11035 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11036 tp->nvram_size = (protect ?
11037 TG3_NVRAM_SIZE_64KB :
11038 TG3_NVRAM_SIZE_128KB);
11039 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11040 tp->nvram_size = (protect ?
11041 TG3_NVRAM_SIZE_64KB :
11042 TG3_NVRAM_SIZE_256KB);
11043 else
11044 tp->nvram_size = (protect ?
11045 TG3_NVRAM_SIZE_128KB :
11046 TG3_NVRAM_SIZE_512KB);
11047 break;
11048 }
11049 }
11050
11051 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11052 {
11053 u32 nvcfg1;
11054
11055 nvcfg1 = tr32(NVRAM_CFG1);
11056
11057 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11058 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11059 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11060 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11061 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11062 tp->nvram_jedecnum = JEDEC_ATMEL;
11063 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11064 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11065
11066 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11067 tw32(NVRAM_CFG1, nvcfg1);
11068 break;
11069 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11070 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11071 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11072 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11073 tp->nvram_jedecnum = JEDEC_ATMEL;
11074 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11075 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11076 tp->nvram_pagesize = 264;
11077 break;
11078 case FLASH_5752VENDOR_ST_M45PE10:
11079 case FLASH_5752VENDOR_ST_M45PE20:
11080 case FLASH_5752VENDOR_ST_M45PE40:
11081 tp->nvram_jedecnum = JEDEC_ST;
11082 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11083 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11084 tp->nvram_pagesize = 256;
11085 break;
11086 }
11087 }
11088
11089 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11090 {
11091 u32 nvcfg1, protect = 0;
11092
11093 nvcfg1 = tr32(NVRAM_CFG1);
11094
11095 /* NVRAM protection for TPM */
11096 if (nvcfg1 & (1 << 27)) {
11097 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
11098 protect = 1;
11099 }
11100
11101 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11102 switch (nvcfg1) {
11103 case FLASH_5761VENDOR_ATMEL_ADB021D:
11104 case FLASH_5761VENDOR_ATMEL_ADB041D:
11105 case FLASH_5761VENDOR_ATMEL_ADB081D:
11106 case FLASH_5761VENDOR_ATMEL_ADB161D:
11107 case FLASH_5761VENDOR_ATMEL_MDB021D:
11108 case FLASH_5761VENDOR_ATMEL_MDB041D:
11109 case FLASH_5761VENDOR_ATMEL_MDB081D:
11110 case FLASH_5761VENDOR_ATMEL_MDB161D:
11111 tp->nvram_jedecnum = JEDEC_ATMEL;
11112 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11113 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11114 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11115 tp->nvram_pagesize = 256;
11116 break;
11117 case FLASH_5761VENDOR_ST_A_M45PE20:
11118 case FLASH_5761VENDOR_ST_A_M45PE40:
11119 case FLASH_5761VENDOR_ST_A_M45PE80:
11120 case FLASH_5761VENDOR_ST_A_M45PE16:
11121 case FLASH_5761VENDOR_ST_M_M45PE20:
11122 case FLASH_5761VENDOR_ST_M_M45PE40:
11123 case FLASH_5761VENDOR_ST_M_M45PE80:
11124 case FLASH_5761VENDOR_ST_M_M45PE16:
11125 tp->nvram_jedecnum = JEDEC_ST;
11126 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11127 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11128 tp->nvram_pagesize = 256;
11129 break;
11130 }
11131
11132 if (protect) {
11133 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11134 } else {
11135 switch (nvcfg1) {
11136 case FLASH_5761VENDOR_ATMEL_ADB161D:
11137 case FLASH_5761VENDOR_ATMEL_MDB161D:
11138 case FLASH_5761VENDOR_ST_A_M45PE16:
11139 case FLASH_5761VENDOR_ST_M_M45PE16:
11140 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11141 break;
11142 case FLASH_5761VENDOR_ATMEL_ADB081D:
11143 case FLASH_5761VENDOR_ATMEL_MDB081D:
11144 case FLASH_5761VENDOR_ST_A_M45PE80:
11145 case FLASH_5761VENDOR_ST_M_M45PE80:
11146 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11147 break;
11148 case FLASH_5761VENDOR_ATMEL_ADB041D:
11149 case FLASH_5761VENDOR_ATMEL_MDB041D:
11150 case FLASH_5761VENDOR_ST_A_M45PE40:
11151 case FLASH_5761VENDOR_ST_M_M45PE40:
11152 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11153 break;
11154 case FLASH_5761VENDOR_ATMEL_ADB021D:
11155 case FLASH_5761VENDOR_ATMEL_MDB021D:
11156 case FLASH_5761VENDOR_ST_A_M45PE20:
11157 case FLASH_5761VENDOR_ST_M_M45PE20:
11158 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11159 break;
11160 }
11161 }
11162 }
11163
11164 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11165 {
11166 tp->nvram_jedecnum = JEDEC_ATMEL;
11167 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11168 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11169 }
11170
11171 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11172 {
11173 u32 nvcfg1;
11174
11175 nvcfg1 = tr32(NVRAM_CFG1);
11176
11177 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11178 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11179 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11180 tp->nvram_jedecnum = JEDEC_ATMEL;
11181 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11182 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11183
11184 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11185 tw32(NVRAM_CFG1, nvcfg1);
11186 return;
11187 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11188 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11189 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11190 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11191 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11192 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11193 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11194 tp->nvram_jedecnum = JEDEC_ATMEL;
11195 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11196 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11197
11198 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11199 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11200 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11201 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11202 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11203 break;
11204 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11205 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11206 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11207 break;
11208 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11209 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11210 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11211 break;
11212 }
11213 break;
11214 case FLASH_5752VENDOR_ST_M45PE10:
11215 case FLASH_5752VENDOR_ST_M45PE20:
11216 case FLASH_5752VENDOR_ST_M45PE40:
11217 tp->nvram_jedecnum = JEDEC_ST;
11218 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11219 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11220
11221 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11222 case FLASH_5752VENDOR_ST_M45PE10:
11223 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11224 break;
11225 case FLASH_5752VENDOR_ST_M45PE20:
11226 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11227 break;
11228 case FLASH_5752VENDOR_ST_M45PE40:
11229 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11230 break;
11231 }
11232 break;
11233 default:
11234 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11235 return;
11236 }
11237
11238 tg3_nvram_get_pagesize(tp, nvcfg1);
11239 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11240 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11241 }
11242
11243
11244 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11245 {
11246 u32 nvcfg1;
11247
11248 nvcfg1 = tr32(NVRAM_CFG1);
11249
11250 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11251 case FLASH_5717VENDOR_ATMEL_EEPROM:
11252 case FLASH_5717VENDOR_MICRO_EEPROM:
11253 tp->nvram_jedecnum = JEDEC_ATMEL;
11254 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11255 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11256
11257 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11258 tw32(NVRAM_CFG1, nvcfg1);
11259 return;
11260 case FLASH_5717VENDOR_ATMEL_MDB011D:
11261 case FLASH_5717VENDOR_ATMEL_ADB011B:
11262 case FLASH_5717VENDOR_ATMEL_ADB011D:
11263 case FLASH_5717VENDOR_ATMEL_MDB021D:
11264 case FLASH_5717VENDOR_ATMEL_ADB021B:
11265 case FLASH_5717VENDOR_ATMEL_ADB021D:
11266 case FLASH_5717VENDOR_ATMEL_45USPT:
11267 tp->nvram_jedecnum = JEDEC_ATMEL;
11268 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11269 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11270
11271 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11272 case FLASH_5717VENDOR_ATMEL_MDB021D:
11273 case FLASH_5717VENDOR_ATMEL_ADB021B:
11274 case FLASH_5717VENDOR_ATMEL_ADB021D:
11275 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11276 break;
11277 default:
11278 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11279 break;
11280 }
11281 break;
11282 case FLASH_5717VENDOR_ST_M_M25PE10:
11283 case FLASH_5717VENDOR_ST_A_M25PE10:
11284 case FLASH_5717VENDOR_ST_M_M45PE10:
11285 case FLASH_5717VENDOR_ST_A_M45PE10:
11286 case FLASH_5717VENDOR_ST_M_M25PE20:
11287 case FLASH_5717VENDOR_ST_A_M25PE20:
11288 case FLASH_5717VENDOR_ST_M_M45PE20:
11289 case FLASH_5717VENDOR_ST_A_M45PE20:
11290 case FLASH_5717VENDOR_ST_25USPT:
11291 case FLASH_5717VENDOR_ST_45USPT:
11292 tp->nvram_jedecnum = JEDEC_ST;
11293 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11294 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11295
11296 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11297 case FLASH_5717VENDOR_ST_M_M25PE20:
11298 case FLASH_5717VENDOR_ST_A_M25PE20:
11299 case FLASH_5717VENDOR_ST_M_M45PE20:
11300 case FLASH_5717VENDOR_ST_A_M45PE20:
11301 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11302 break;
11303 default:
11304 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11305 break;
11306 }
11307 break;
11308 default:
11309 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11310 return;
11311 }
11312
11313 tg3_nvram_get_pagesize(tp, nvcfg1);
11314 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11315 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11316 }
11317
11318 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11319 static void __devinit tg3_nvram_init(struct tg3 *tp)
11320 {
11321 tw32_f(GRC_EEPROM_ADDR,
11322 (EEPROM_ADDR_FSM_RESET |
11323 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11324 EEPROM_ADDR_CLKPERD_SHIFT)));
11325
11326 msleep(1);
11327
11328 /* Enable seeprom accesses. */
11329 tw32_f(GRC_LOCAL_CTRL,
11330 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11331 udelay(100);
11332
11333 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11334 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11335 tp->tg3_flags |= TG3_FLAG_NVRAM;
11336
11337 if (tg3_nvram_lock(tp)) {
11338 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11339 "tg3_nvram_init failed.\n", tp->dev->name);
11340 return;
11341 }
11342 tg3_enable_nvram_access(tp);
11343
11344 tp->nvram_size = 0;
11345
11346 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11347 tg3_get_5752_nvram_info(tp);
11348 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11349 tg3_get_5755_nvram_info(tp);
11350 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11351 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11352 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11353 tg3_get_5787_nvram_info(tp);
11354 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11355 tg3_get_5761_nvram_info(tp);
11356 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11357 tg3_get_5906_nvram_info(tp);
11358 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11359 tg3_get_57780_nvram_info(tp);
11360 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11361 tg3_get_5717_nvram_info(tp);
11362 else
11363 tg3_get_nvram_info(tp);
11364
11365 if (tp->nvram_size == 0)
11366 tg3_get_nvram_size(tp);
11367
11368 tg3_disable_nvram_access(tp);
11369 tg3_nvram_unlock(tp);
11370
11371 } else {
11372 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11373
11374 tg3_get_eeprom_size(tp);
11375 }
11376 }
11377
11378 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11379 u32 offset, u32 len, u8 *buf)
11380 {
11381 int i, j, rc = 0;
11382 u32 val;
11383
11384 for (i = 0; i < len; i += 4) {
11385 u32 addr;
11386 __be32 data;
11387
11388 addr = offset + i;
11389
11390 memcpy(&data, buf + i, 4);
11391
11392 /*
11393 * The SEEPROM interface expects the data to always be opposite
11394 * the native endian format. We accomplish this by reversing
11395 * all the operations that would have been performed on the
11396 * data from a call to tg3_nvram_read_be32().
11397 */
11398 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11399
11400 val = tr32(GRC_EEPROM_ADDR);
11401 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11402
11403 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11404 EEPROM_ADDR_READ);
11405 tw32(GRC_EEPROM_ADDR, val |
11406 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11407 (addr & EEPROM_ADDR_ADDR_MASK) |
11408 EEPROM_ADDR_START |
11409 EEPROM_ADDR_WRITE);
11410
11411 for (j = 0; j < 1000; j++) {
11412 val = tr32(GRC_EEPROM_ADDR);
11413
11414 if (val & EEPROM_ADDR_COMPLETE)
11415 break;
11416 msleep(1);
11417 }
11418 if (!(val & EEPROM_ADDR_COMPLETE)) {
11419 rc = -EBUSY;
11420 break;
11421 }
11422 }
11423
11424 return rc;
11425 }
11426
11427 /* offset and length are dword aligned */
11428 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11429 u8 *buf)
11430 {
11431 int ret = 0;
11432 u32 pagesize = tp->nvram_pagesize;
11433 u32 pagemask = pagesize - 1;
11434 u32 nvram_cmd;
11435 u8 *tmp;
11436
11437 tmp = kmalloc(pagesize, GFP_KERNEL);
11438 if (tmp == NULL)
11439 return -ENOMEM;
11440
11441 while (len) {
11442 int j;
11443 u32 phy_addr, page_off, size;
11444
11445 phy_addr = offset & ~pagemask;
11446
11447 for (j = 0; j < pagesize; j += 4) {
11448 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11449 (__be32 *) (tmp + j));
11450 if (ret)
11451 break;
11452 }
11453 if (ret)
11454 break;
11455
11456 page_off = offset & pagemask;
11457 size = pagesize;
11458 if (len < size)
11459 size = len;
11460
11461 len -= size;
11462
11463 memcpy(tmp + page_off, buf, size);
11464
11465 offset = offset + (pagesize - page_off);
11466
11467 tg3_enable_nvram_access(tp);
11468
11469 /*
11470 * Before we can erase the flash page, we need
11471 * to issue a special "write enable" command.
11472 */
11473 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11474
11475 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11476 break;
11477
11478 /* Erase the target page */
11479 tw32(NVRAM_ADDR, phy_addr);
11480
11481 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11482 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11483
11484 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11485 break;
11486
11487 /* Issue another write enable to start the write. */
11488 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11489
11490 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11491 break;
11492
11493 for (j = 0; j < pagesize; j += 4) {
11494 __be32 data;
11495
11496 data = *((__be32 *) (tmp + j));
11497
11498 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11499
11500 tw32(NVRAM_ADDR, phy_addr + j);
11501
11502 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11503 NVRAM_CMD_WR;
11504
11505 if (j == 0)
11506 nvram_cmd |= NVRAM_CMD_FIRST;
11507 else if (j == (pagesize - 4))
11508 nvram_cmd |= NVRAM_CMD_LAST;
11509
11510 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11511 break;
11512 }
11513 if (ret)
11514 break;
11515 }
11516
11517 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11518 tg3_nvram_exec_cmd(tp, nvram_cmd);
11519
11520 kfree(tmp);
11521
11522 return ret;
11523 }
11524
11525 /* offset and length are dword aligned */
11526 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11527 u8 *buf)
11528 {
11529 int i, ret = 0;
11530
11531 for (i = 0; i < len; i += 4, offset += 4) {
11532 u32 page_off, phy_addr, nvram_cmd;
11533 __be32 data;
11534
11535 memcpy(&data, buf + i, 4);
11536 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11537
11538 page_off = offset % tp->nvram_pagesize;
11539
11540 phy_addr = tg3_nvram_phys_addr(tp, offset);
11541
11542 tw32(NVRAM_ADDR, phy_addr);
11543
11544 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11545
11546 if ((page_off == 0) || (i == 0))
11547 nvram_cmd |= NVRAM_CMD_FIRST;
11548 if (page_off == (tp->nvram_pagesize - 4))
11549 nvram_cmd |= NVRAM_CMD_LAST;
11550
11551 if (i == (len - 4))
11552 nvram_cmd |= NVRAM_CMD_LAST;
11553
11554 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11555 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11556 (tp->nvram_jedecnum == JEDEC_ST) &&
11557 (nvram_cmd & NVRAM_CMD_FIRST)) {
11558
11559 if ((ret = tg3_nvram_exec_cmd(tp,
11560 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11561 NVRAM_CMD_DONE)))
11562
11563 break;
11564 }
11565 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11566 /* We always do complete word writes to eeprom. */
11567 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11568 }
11569
11570 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11571 break;
11572 }
11573 return ret;
11574 }
11575
11576 /* offset and length are dword aligned */
11577 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11578 {
11579 int ret;
11580
11581 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11582 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11583 ~GRC_LCLCTRL_GPIO_OUTPUT1);
11584 udelay(40);
11585 }
11586
11587 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11588 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11589 }
11590 else {
11591 u32 grc_mode;
11592
11593 ret = tg3_nvram_lock(tp);
11594 if (ret)
11595 return ret;
11596
11597 tg3_enable_nvram_access(tp);
11598 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11599 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
11600 tw32(NVRAM_WRITE1, 0x406);
11601
11602 grc_mode = tr32(GRC_MODE);
11603 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11604
11605 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11606 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11607
11608 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11609 buf);
11610 }
11611 else {
11612 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11613 buf);
11614 }
11615
11616 grc_mode = tr32(GRC_MODE);
11617 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11618
11619 tg3_disable_nvram_access(tp);
11620 tg3_nvram_unlock(tp);
11621 }
11622
11623 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11624 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11625 udelay(40);
11626 }
11627
11628 return ret;
11629 }
11630
11631 struct subsys_tbl_ent {
11632 u16 subsys_vendor, subsys_devid;
11633 u32 phy_id;
11634 };
11635
11636 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11637 /* Broadcom boards. */
11638 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11639 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11640 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11641 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11642 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11643 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11644 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11645 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11646 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11647 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11648 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11649
11650 /* 3com boards. */
11651 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11652 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11653 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11654 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11655 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11656
11657 /* DELL boards. */
11658 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11659 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11660 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11661 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11662
11663 /* Compaq boards. */
11664 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11665 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11666 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11667 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11668 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11669
11670 /* IBM boards. */
11671 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11672 };
11673
11674 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11675 {
11676 int i;
11677
11678 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11679 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11680 tp->pdev->subsystem_vendor) &&
11681 (subsys_id_to_phy_id[i].subsys_devid ==
11682 tp->pdev->subsystem_device))
11683 return &subsys_id_to_phy_id[i];
11684 }
11685 return NULL;
11686 }
11687
11688 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11689 {
11690 u32 val;
11691 u16 pmcsr;
11692
11693 /* On some early chips the SRAM cannot be accessed in D3hot state,
11694 * so need make sure we're in D0.
11695 */
11696 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11697 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11698 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11699 msleep(1);
11700
11701 /* Make sure register accesses (indirect or otherwise)
11702 * will function correctly.
11703 */
11704 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11705 tp->misc_host_ctrl);
11706
11707 /* The memory arbiter has to be enabled in order for SRAM accesses
11708 * to succeed. Normally on powerup the tg3 chip firmware will make
11709 * sure it is enabled, but other entities such as system netboot
11710 * code might disable it.
11711 */
11712 val = tr32(MEMARB_MODE);
11713 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11714
11715 tp->phy_id = PHY_ID_INVALID;
11716 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11717
11718 /* Assume an onboard device and WOL capable by default. */
11719 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11720
11721 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11722 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11723 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11724 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11725 }
11726 val = tr32(VCPU_CFGSHDW);
11727 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11728 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11729 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11730 (val & VCPU_CFGSHDW_WOL_MAGPKT))
11731 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11732 goto done;
11733 }
11734
11735 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11736 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11737 u32 nic_cfg, led_cfg;
11738 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11739 int eeprom_phy_serdes = 0;
11740
11741 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11742 tp->nic_sram_data_cfg = nic_cfg;
11743
11744 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11745 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11746 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11747 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11748 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11749 (ver > 0) && (ver < 0x100))
11750 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11751
11752 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11753 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11754
11755 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11756 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11757 eeprom_phy_serdes = 1;
11758
11759 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11760 if (nic_phy_id != 0) {
11761 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11762 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11763
11764 eeprom_phy_id = (id1 >> 16) << 10;
11765 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11766 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11767 } else
11768 eeprom_phy_id = 0;
11769
11770 tp->phy_id = eeprom_phy_id;
11771 if (eeprom_phy_serdes) {
11772 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11773 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11774 else
11775 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11776 }
11777
11778 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11779 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11780 SHASTA_EXT_LED_MODE_MASK);
11781 else
11782 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11783
11784 switch (led_cfg) {
11785 default:
11786 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11787 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11788 break;
11789
11790 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11791 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11792 break;
11793
11794 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11795 tp->led_ctrl = LED_CTRL_MODE_MAC;
11796
11797 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11798 * read on some older 5700/5701 bootcode.
11799 */
11800 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11801 ASIC_REV_5700 ||
11802 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11803 ASIC_REV_5701)
11804 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11805
11806 break;
11807
11808 case SHASTA_EXT_LED_SHARED:
11809 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11810 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11811 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11812 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11813 LED_CTRL_MODE_PHY_2);
11814 break;
11815
11816 case SHASTA_EXT_LED_MAC:
11817 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11818 break;
11819
11820 case SHASTA_EXT_LED_COMBO:
11821 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11822 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11823 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11824 LED_CTRL_MODE_PHY_2);
11825 break;
11826
11827 }
11828
11829 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11830 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11831 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11832 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11833
11834 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11835 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11836
11837 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11838 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11839 if ((tp->pdev->subsystem_vendor ==
11840 PCI_VENDOR_ID_ARIMA) &&
11841 (tp->pdev->subsystem_device == 0x205a ||
11842 tp->pdev->subsystem_device == 0x2063))
11843 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11844 } else {
11845 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11846 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11847 }
11848
11849 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11850 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11851 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11852 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11853 }
11854
11855 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11856 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11857 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11858
11859 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11860 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11861 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11862
11863 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11864 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11865 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11866
11867 if (cfg2 & (1 << 17))
11868 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11869
11870 /* serdes signal pre-emphasis in register 0x590 set by */
11871 /* bootcode if bit 18 is set */
11872 if (cfg2 & (1 << 18))
11873 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11874
11875 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11876 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11877 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11878 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11879
11880 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11881 u32 cfg3;
11882
11883 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11884 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11885 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11886 }
11887
11888 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11889 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11890 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11891 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11892 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11893 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11894 }
11895 done:
11896 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11897 device_set_wakeup_enable(&tp->pdev->dev,
11898 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11899 }
11900
11901 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11902 {
11903 int i;
11904 u32 val;
11905
11906 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11907 tw32(OTP_CTRL, cmd);
11908
11909 /* Wait for up to 1 ms for command to execute. */
11910 for (i = 0; i < 100; i++) {
11911 val = tr32(OTP_STATUS);
11912 if (val & OTP_STATUS_CMD_DONE)
11913 break;
11914 udelay(10);
11915 }
11916
11917 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11918 }
11919
11920 /* Read the gphy configuration from the OTP region of the chip. The gphy
11921 * configuration is a 32-bit value that straddles the alignment boundary.
11922 * We do two 32-bit reads and then shift and merge the results.
11923 */
11924 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11925 {
11926 u32 bhalf_otp, thalf_otp;
11927
11928 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11929
11930 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11931 return 0;
11932
11933 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11934
11935 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11936 return 0;
11937
11938 thalf_otp = tr32(OTP_READ_DATA);
11939
11940 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11941
11942 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11943 return 0;
11944
11945 bhalf_otp = tr32(OTP_READ_DATA);
11946
11947 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11948 }
11949
11950 static int __devinit tg3_phy_probe(struct tg3 *tp)
11951 {
11952 u32 hw_phy_id_1, hw_phy_id_2;
11953 u32 hw_phy_id, hw_phy_id_masked;
11954 int err;
11955
11956 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11957 return tg3_phy_init(tp);
11958
11959 /* Reading the PHY ID register can conflict with ASF
11960 * firmware access to the PHY hardware.
11961 */
11962 err = 0;
11963 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11964 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11965 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11966 } else {
11967 /* Now read the physical PHY_ID from the chip and verify
11968 * that it is sane. If it doesn't look good, we fall back
11969 * to either the hard-coded table based PHY_ID and failing
11970 * that the value found in the eeprom area.
11971 */
11972 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11973 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11974
11975 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11976 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11977 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11978
11979 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11980 }
11981
11982 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11983 tp->phy_id = hw_phy_id;
11984 if (hw_phy_id_masked == PHY_ID_BCM8002)
11985 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11986 else
11987 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11988 } else {
11989 if (tp->phy_id != PHY_ID_INVALID) {
11990 /* Do nothing, phy ID already set up in
11991 * tg3_get_eeprom_hw_cfg().
11992 */
11993 } else {
11994 struct subsys_tbl_ent *p;
11995
11996 /* No eeprom signature? Try the hardcoded
11997 * subsys device table.
11998 */
11999 p = lookup_by_subsys(tp);
12000 if (!p)
12001 return -ENODEV;
12002
12003 tp->phy_id = p->phy_id;
12004 if (!tp->phy_id ||
12005 tp->phy_id == PHY_ID_BCM8002)
12006 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12007 }
12008 }
12009
12010 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12011 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12012 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12013 u32 bmsr, adv_reg, tg3_ctrl, mask;
12014
12015 tg3_readphy(tp, MII_BMSR, &bmsr);
12016 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12017 (bmsr & BMSR_LSTATUS))
12018 goto skip_phy_reset;
12019
12020 err = tg3_phy_reset(tp);
12021 if (err)
12022 return err;
12023
12024 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12025 ADVERTISE_100HALF | ADVERTISE_100FULL |
12026 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12027 tg3_ctrl = 0;
12028 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12029 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12030 MII_TG3_CTRL_ADV_1000_FULL);
12031 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12032 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12033 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12034 MII_TG3_CTRL_ENABLE_AS_MASTER);
12035 }
12036
12037 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12038 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12039 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12040 if (!tg3_copper_is_advertising_all(tp, mask)) {
12041 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12042
12043 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12044 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12045
12046 tg3_writephy(tp, MII_BMCR,
12047 BMCR_ANENABLE | BMCR_ANRESTART);
12048 }
12049 tg3_phy_set_wirespeed(tp);
12050
12051 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12052 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12053 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12054 }
12055
12056 skip_phy_reset:
12057 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12058 err = tg3_init_5401phy_dsp(tp);
12059 if (err)
12060 return err;
12061 }
12062
12063 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12064 err = tg3_init_5401phy_dsp(tp);
12065 }
12066
12067 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12068 tp->link_config.advertising =
12069 (ADVERTISED_1000baseT_Half |
12070 ADVERTISED_1000baseT_Full |
12071 ADVERTISED_Autoneg |
12072 ADVERTISED_FIBRE);
12073 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12074 tp->link_config.advertising &=
12075 ~(ADVERTISED_1000baseT_Half |
12076 ADVERTISED_1000baseT_Full);
12077
12078 return err;
12079 }
12080
12081 static void __devinit tg3_read_partno(struct tg3 *tp)
12082 {
12083 unsigned char vpd_data[256]; /* in little-endian format */
12084 unsigned int i;
12085 u32 magic;
12086
12087 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12088 tg3_nvram_read(tp, 0x0, &magic))
12089 goto out_not_found;
12090
12091 if (magic == TG3_EEPROM_MAGIC) {
12092 for (i = 0; i < 256; i += 4) {
12093 u32 tmp;
12094
12095 /* The data is in little-endian format in NVRAM.
12096 * Use the big-endian read routines to preserve
12097 * the byte order as it exists in NVRAM.
12098 */
12099 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
12100 goto out_not_found;
12101
12102 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12103 }
12104 } else {
12105 int vpd_cap;
12106
12107 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
12108 for (i = 0; i < 256; i += 4) {
12109 u32 tmp, j = 0;
12110 __le32 v;
12111 u16 tmp16;
12112
12113 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
12114 i);
12115 while (j++ < 100) {
12116 pci_read_config_word(tp->pdev, vpd_cap +
12117 PCI_VPD_ADDR, &tmp16);
12118 if (tmp16 & 0x8000)
12119 break;
12120 msleep(1);
12121 }
12122 if (!(tmp16 & 0x8000))
12123 goto out_not_found;
12124
12125 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
12126 &tmp);
12127 v = cpu_to_le32(tmp);
12128 memcpy(&vpd_data[i], &v, sizeof(v));
12129 }
12130 }
12131
12132 /* Now parse and find the part number. */
12133 for (i = 0; i < 254; ) {
12134 unsigned char val = vpd_data[i];
12135 unsigned int block_end;
12136
12137 if (val == 0x82 || val == 0x91) {
12138 i = (i + 3 +
12139 (vpd_data[i + 1] +
12140 (vpd_data[i + 2] << 8)));
12141 continue;
12142 }
12143
12144 if (val != 0x90)
12145 goto out_not_found;
12146
12147 block_end = (i + 3 +
12148 (vpd_data[i + 1] +
12149 (vpd_data[i + 2] << 8)));
12150 i += 3;
12151
12152 if (block_end > 256)
12153 goto out_not_found;
12154
12155 while (i < (block_end - 2)) {
12156 if (vpd_data[i + 0] == 'P' &&
12157 vpd_data[i + 1] == 'N') {
12158 int partno_len = vpd_data[i + 2];
12159
12160 i += 3;
12161 if (partno_len > 24 || (partno_len + i) > 256)
12162 goto out_not_found;
12163
12164 memcpy(tp->board_part_number,
12165 &vpd_data[i], partno_len);
12166
12167 /* Success. */
12168 return;
12169 }
12170 i += 3 + vpd_data[i + 2];
12171 }
12172
12173 /* Part number not found. */
12174 goto out_not_found;
12175 }
12176
12177 out_not_found:
12178 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12179 strcpy(tp->board_part_number, "BCM95906");
12180 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12181 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12182 strcpy(tp->board_part_number, "BCM57780");
12183 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12184 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12185 strcpy(tp->board_part_number, "BCM57760");
12186 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12187 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12188 strcpy(tp->board_part_number, "BCM57790");
12189 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12190 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12191 strcpy(tp->board_part_number, "BCM57788");
12192 else
12193 strcpy(tp->board_part_number, "none");
12194 }
12195
12196 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12197 {
12198 u32 val;
12199
12200 if (tg3_nvram_read(tp, offset, &val) ||
12201 (val & 0xfc000000) != 0x0c000000 ||
12202 tg3_nvram_read(tp, offset + 4, &val) ||
12203 val != 0)
12204 return 0;
12205
12206 return 1;
12207 }
12208
12209 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12210 {
12211 u32 val, offset, start, ver_offset;
12212 int i;
12213 bool newver = false;
12214
12215 if (tg3_nvram_read(tp, 0xc, &offset) ||
12216 tg3_nvram_read(tp, 0x4, &start))
12217 return;
12218
12219 offset = tg3_nvram_logical_addr(tp, offset);
12220
12221 if (tg3_nvram_read(tp, offset, &val))
12222 return;
12223
12224 if ((val & 0xfc000000) == 0x0c000000) {
12225 if (tg3_nvram_read(tp, offset + 4, &val))
12226 return;
12227
12228 if (val == 0)
12229 newver = true;
12230 }
12231
12232 if (newver) {
12233 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12234 return;
12235
12236 offset = offset + ver_offset - start;
12237 for (i = 0; i < 16; i += 4) {
12238 __be32 v;
12239 if (tg3_nvram_read_be32(tp, offset + i, &v))
12240 return;
12241
12242 memcpy(tp->fw_ver + i, &v, sizeof(v));
12243 }
12244 } else {
12245 u32 major, minor;
12246
12247 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12248 return;
12249
12250 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12251 TG3_NVM_BCVER_MAJSFT;
12252 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12253 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12254 }
12255 }
12256
12257 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12258 {
12259 u32 val, major, minor;
12260
12261 /* Use native endian representation */
12262 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12263 return;
12264
12265 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12266 TG3_NVM_HWSB_CFG1_MAJSFT;
12267 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12268 TG3_NVM_HWSB_CFG1_MINSFT;
12269
12270 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12271 }
12272
12273 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12274 {
12275 u32 offset, major, minor, build;
12276
12277 tp->fw_ver[0] = 's';
12278 tp->fw_ver[1] = 'b';
12279 tp->fw_ver[2] = '\0';
12280
12281 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12282 return;
12283
12284 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12285 case TG3_EEPROM_SB_REVISION_0:
12286 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12287 break;
12288 case TG3_EEPROM_SB_REVISION_2:
12289 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12290 break;
12291 case TG3_EEPROM_SB_REVISION_3:
12292 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12293 break;
12294 default:
12295 return;
12296 }
12297
12298 if (tg3_nvram_read(tp, offset, &val))
12299 return;
12300
12301 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12302 TG3_EEPROM_SB_EDH_BLD_SHFT;
12303 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12304 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12305 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12306
12307 if (minor > 99 || build > 26)
12308 return;
12309
12310 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12311
12312 if (build > 0) {
12313 tp->fw_ver[8] = 'a' + build - 1;
12314 tp->fw_ver[9] = '\0';
12315 }
12316 }
12317
12318 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12319 {
12320 u32 val, offset, start;
12321 int i, vlen;
12322
12323 for (offset = TG3_NVM_DIR_START;
12324 offset < TG3_NVM_DIR_END;
12325 offset += TG3_NVM_DIRENT_SIZE) {
12326 if (tg3_nvram_read(tp, offset, &val))
12327 return;
12328
12329 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12330 break;
12331 }
12332
12333 if (offset == TG3_NVM_DIR_END)
12334 return;
12335
12336 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12337 start = 0x08000000;
12338 else if (tg3_nvram_read(tp, offset - 4, &start))
12339 return;
12340
12341 if (tg3_nvram_read(tp, offset + 4, &offset) ||
12342 !tg3_fw_img_is_valid(tp, offset) ||
12343 tg3_nvram_read(tp, offset + 8, &val))
12344 return;
12345
12346 offset += val - start;
12347
12348 vlen = strlen(tp->fw_ver);
12349
12350 tp->fw_ver[vlen++] = ',';
12351 tp->fw_ver[vlen++] = ' ';
12352
12353 for (i = 0; i < 4; i++) {
12354 __be32 v;
12355 if (tg3_nvram_read_be32(tp, offset, &v))
12356 return;
12357
12358 offset += sizeof(v);
12359
12360 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12361 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12362 break;
12363 }
12364
12365 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12366 vlen += sizeof(v);
12367 }
12368 }
12369
12370 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12371 {
12372 int vlen;
12373 u32 apedata;
12374
12375 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12376 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12377 return;
12378
12379 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12380 if (apedata != APE_SEG_SIG_MAGIC)
12381 return;
12382
12383 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12384 if (!(apedata & APE_FW_STATUS_READY))
12385 return;
12386
12387 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12388
12389 vlen = strlen(tp->fw_ver);
12390
12391 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12392 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12393 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12394 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12395 (apedata & APE_FW_VERSION_BLDMSK));
12396 }
12397
12398 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12399 {
12400 u32 val;
12401
12402 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12403 tp->fw_ver[0] = 's';
12404 tp->fw_ver[1] = 'b';
12405 tp->fw_ver[2] = '\0';
12406
12407 return;
12408 }
12409
12410 if (tg3_nvram_read(tp, 0, &val))
12411 return;
12412
12413 if (val == TG3_EEPROM_MAGIC)
12414 tg3_read_bc_ver(tp);
12415 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12416 tg3_read_sb_ver(tp, val);
12417 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12418 tg3_read_hwsb_ver(tp);
12419 else
12420 return;
12421
12422 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12423 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12424 return;
12425
12426 tg3_read_mgmtfw_ver(tp);
12427
12428 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12429 }
12430
12431 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12432
12433 static int __devinit tg3_get_invariants(struct tg3 *tp)
12434 {
12435 static struct pci_device_id write_reorder_chipsets[] = {
12436 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12437 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12438 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12439 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12440 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12441 PCI_DEVICE_ID_VIA_8385_0) },
12442 { },
12443 };
12444 u32 misc_ctrl_reg;
12445 u32 pci_state_reg, grc_misc_cfg;
12446 u32 val;
12447 u16 pci_cmd;
12448 int err;
12449
12450 /* Force memory write invalidate off. If we leave it on,
12451 * then on 5700_BX chips we have to enable a workaround.
12452 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12453 * to match the cacheline size. The Broadcom driver have this
12454 * workaround but turns MWI off all the times so never uses
12455 * it. This seems to suggest that the workaround is insufficient.
12456 */
12457 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12458 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12459 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12460
12461 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12462 * has the register indirect write enable bit set before
12463 * we try to access any of the MMIO registers. It is also
12464 * critical that the PCI-X hw workaround situation is decided
12465 * before that as well.
12466 */
12467 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12468 &misc_ctrl_reg);
12469
12470 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12471 MISC_HOST_CTRL_CHIPREV_SHIFT);
12472 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12473 u32 prod_id_asic_rev;
12474
12475 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717C ||
12476 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717S ||
12477 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718C ||
12478 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718S)
12479 pci_read_config_dword(tp->pdev,
12480 TG3PCI_GEN2_PRODID_ASICREV,
12481 &prod_id_asic_rev);
12482 else
12483 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12484 &prod_id_asic_rev);
12485
12486 tp->pci_chip_rev_id = prod_id_asic_rev;
12487 }
12488
12489 /* Wrong chip ID in 5752 A0. This code can be removed later
12490 * as A0 is not in production.
12491 */
12492 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12493 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12494
12495 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12496 * we need to disable memory and use config. cycles
12497 * only to access all registers. The 5702/03 chips
12498 * can mistakenly decode the special cycles from the
12499 * ICH chipsets as memory write cycles, causing corruption
12500 * of register and memory space. Only certain ICH bridges
12501 * will drive special cycles with non-zero data during the
12502 * address phase which can fall within the 5703's address
12503 * range. This is not an ICH bug as the PCI spec allows
12504 * non-zero address during special cycles. However, only
12505 * these ICH bridges are known to drive non-zero addresses
12506 * during special cycles.
12507 *
12508 * Since special cycles do not cross PCI bridges, we only
12509 * enable this workaround if the 5703 is on the secondary
12510 * bus of these ICH bridges.
12511 */
12512 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12513 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12514 static struct tg3_dev_id {
12515 u32 vendor;
12516 u32 device;
12517 u32 rev;
12518 } ich_chipsets[] = {
12519 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12520 PCI_ANY_ID },
12521 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12522 PCI_ANY_ID },
12523 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12524 0xa },
12525 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12526 PCI_ANY_ID },
12527 { },
12528 };
12529 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12530 struct pci_dev *bridge = NULL;
12531
12532 while (pci_id->vendor != 0) {
12533 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12534 bridge);
12535 if (!bridge) {
12536 pci_id++;
12537 continue;
12538 }
12539 if (pci_id->rev != PCI_ANY_ID) {
12540 if (bridge->revision > pci_id->rev)
12541 continue;
12542 }
12543 if (bridge->subordinate &&
12544 (bridge->subordinate->number ==
12545 tp->pdev->bus->number)) {
12546
12547 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12548 pci_dev_put(bridge);
12549 break;
12550 }
12551 }
12552 }
12553
12554 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12555 static struct tg3_dev_id {
12556 u32 vendor;
12557 u32 device;
12558 } bridge_chipsets[] = {
12559 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12560 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12561 { },
12562 };
12563 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12564 struct pci_dev *bridge = NULL;
12565
12566 while (pci_id->vendor != 0) {
12567 bridge = pci_get_device(pci_id->vendor,
12568 pci_id->device,
12569 bridge);
12570 if (!bridge) {
12571 pci_id++;
12572 continue;
12573 }
12574 if (bridge->subordinate &&
12575 (bridge->subordinate->number <=
12576 tp->pdev->bus->number) &&
12577 (bridge->subordinate->subordinate >=
12578 tp->pdev->bus->number)) {
12579 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12580 pci_dev_put(bridge);
12581 break;
12582 }
12583 }
12584 }
12585
12586 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12587 * DMA addresses > 40-bit. This bridge may have other additional
12588 * 57xx devices behind it in some 4-port NIC designs for example.
12589 * Any tg3 device found behind the bridge will also need the 40-bit
12590 * DMA workaround.
12591 */
12592 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12593 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12594 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12595 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12596 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12597 }
12598 else {
12599 struct pci_dev *bridge = NULL;
12600
12601 do {
12602 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12603 PCI_DEVICE_ID_SERVERWORKS_EPB,
12604 bridge);
12605 if (bridge && bridge->subordinate &&
12606 (bridge->subordinate->number <=
12607 tp->pdev->bus->number) &&
12608 (bridge->subordinate->subordinate >=
12609 tp->pdev->bus->number)) {
12610 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12611 pci_dev_put(bridge);
12612 break;
12613 }
12614 } while (bridge);
12615 }
12616
12617 /* Initialize misc host control in PCI block. */
12618 tp->misc_host_ctrl |= (misc_ctrl_reg &
12619 MISC_HOST_CTRL_CHIPREV);
12620 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12621 tp->misc_host_ctrl);
12622
12623 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12624 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12625 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12626 tp->pdev_peer = tg3_find_peer(tp);
12627
12628 /* Intentionally exclude ASIC_REV_5906 */
12629 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12630 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12631 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12632 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12633 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12634 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12635 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12636 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12637
12638 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12639 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12640 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12641 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12642 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12643 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12644
12645 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12646 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12647 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12648
12649 /* 5700 B0 chips do not support checksumming correctly due
12650 * to hardware bugs.
12651 */
12652 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12653 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12654 else {
12655 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12656 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12657 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12658 tp->dev->features |= NETIF_F_IPV6_CSUM;
12659 }
12660
12661 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12662 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12663 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12664 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12665 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12666 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12667 tp->pdev_peer == tp->pdev))
12668 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12669
12670 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12671 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12672 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12673 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12674 } else {
12675 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12676 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12677 ASIC_REV_5750 &&
12678 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12679 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12680 }
12681 }
12682
12683 tp->irq_max = 1;
12684
12685 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12686 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
12687 tp->irq_max = TG3_IRQ_MAX_VECS;
12688 }
12689
12690 if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
12691 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12692 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
12693 else {
12694 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
12695 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
12696 }
12697 }
12698
12699 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12700 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12701 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12702 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
12703
12704 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12705 &pci_state_reg);
12706
12707 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12708 if (tp->pcie_cap != 0) {
12709 u16 lnkctl;
12710
12711 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12712
12713 pcie_set_readrq(tp->pdev, 4096);
12714
12715 pci_read_config_word(tp->pdev,
12716 tp->pcie_cap + PCI_EXP_LNKCTL,
12717 &lnkctl);
12718 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12719 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12720 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12721 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12722 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12723 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12724 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
12725 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
12726 }
12727 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12728 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12729 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12730 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12731 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12732 if (!tp->pcix_cap) {
12733 printk(KERN_ERR PFX "Cannot find PCI-X "
12734 "capability, aborting.\n");
12735 return -EIO;
12736 }
12737
12738 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12739 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12740 }
12741
12742 /* If we have an AMD 762 or VIA K8T800 chipset, write
12743 * reordering to the mailbox registers done by the host
12744 * controller can cause major troubles. We read back from
12745 * every mailbox register write to force the writes to be
12746 * posted to the chip in order.
12747 */
12748 if (pci_dev_present(write_reorder_chipsets) &&
12749 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12750 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12751
12752 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12753 &tp->pci_cacheline_sz);
12754 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12755 &tp->pci_lat_timer);
12756 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12757 tp->pci_lat_timer < 64) {
12758 tp->pci_lat_timer = 64;
12759 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12760 tp->pci_lat_timer);
12761 }
12762
12763 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12764 /* 5700 BX chips need to have their TX producer index
12765 * mailboxes written twice to workaround a bug.
12766 */
12767 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12768
12769 /* If we are in PCI-X mode, enable register write workaround.
12770 *
12771 * The workaround is to use indirect register accesses
12772 * for all chip writes not to mailbox registers.
12773 */
12774 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12775 u32 pm_reg;
12776
12777 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12778
12779 /* The chip can have it's power management PCI config
12780 * space registers clobbered due to this bug.
12781 * So explicitly force the chip into D0 here.
12782 */
12783 pci_read_config_dword(tp->pdev,
12784 tp->pm_cap + PCI_PM_CTRL,
12785 &pm_reg);
12786 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12787 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12788 pci_write_config_dword(tp->pdev,
12789 tp->pm_cap + PCI_PM_CTRL,
12790 pm_reg);
12791
12792 /* Also, force SERR#/PERR# in PCI command. */
12793 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12794 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12795 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12796 }
12797 }
12798
12799 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12800 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12801 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12802 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12803
12804 /* Chip-specific fixup from Broadcom driver */
12805 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12806 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12807 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12808 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12809 }
12810
12811 /* Default fast path register access methods */
12812 tp->read32 = tg3_read32;
12813 tp->write32 = tg3_write32;
12814 tp->read32_mbox = tg3_read32;
12815 tp->write32_mbox = tg3_write32;
12816 tp->write32_tx_mbox = tg3_write32;
12817 tp->write32_rx_mbox = tg3_write32;
12818
12819 /* Various workaround register access methods */
12820 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12821 tp->write32 = tg3_write_indirect_reg32;
12822 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12823 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12824 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12825 /*
12826 * Back to back register writes can cause problems on these
12827 * chips, the workaround is to read back all reg writes
12828 * except those to mailbox regs.
12829 *
12830 * See tg3_write_indirect_reg32().
12831 */
12832 tp->write32 = tg3_write_flush_reg32;
12833 }
12834
12835 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12836 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12837 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12838 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12839 tp->write32_rx_mbox = tg3_write_flush_reg32;
12840 }
12841
12842 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12843 tp->read32 = tg3_read_indirect_reg32;
12844 tp->write32 = tg3_write_indirect_reg32;
12845 tp->read32_mbox = tg3_read_indirect_mbox;
12846 tp->write32_mbox = tg3_write_indirect_mbox;
12847 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12848 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12849
12850 iounmap(tp->regs);
12851 tp->regs = NULL;
12852
12853 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12854 pci_cmd &= ~PCI_COMMAND_MEMORY;
12855 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12856 }
12857 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12858 tp->read32_mbox = tg3_read32_mbox_5906;
12859 tp->write32_mbox = tg3_write32_mbox_5906;
12860 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12861 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12862 }
12863
12864 if (tp->write32 == tg3_write_indirect_reg32 ||
12865 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12866 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12867 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12868 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12869
12870 /* Get eeprom hw config before calling tg3_set_power_state().
12871 * In particular, the TG3_FLG2_IS_NIC flag must be
12872 * determined before calling tg3_set_power_state() so that
12873 * we know whether or not to switch out of Vaux power.
12874 * When the flag is set, it means that GPIO1 is used for eeprom
12875 * write protect and also implies that it is a LOM where GPIOs
12876 * are not used to switch power.
12877 */
12878 tg3_get_eeprom_hw_cfg(tp);
12879
12880 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12881 /* Allow reads and writes to the
12882 * APE register and memory space.
12883 */
12884 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12885 PCISTATE_ALLOW_APE_SHMEM_WR;
12886 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12887 pci_state_reg);
12888 }
12889
12890 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12891 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12892 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12893 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12894 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12895 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12896
12897 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12898 * GPIO1 driven high will bring 5700's external PHY out of reset.
12899 * It is also used as eeprom write protect on LOMs.
12900 */
12901 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12902 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12903 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12904 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12905 GRC_LCLCTRL_GPIO_OUTPUT1);
12906 /* Unused GPIO3 must be driven as output on 5752 because there
12907 * are no pull-up resistors on unused GPIO pins.
12908 */
12909 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12910 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12911
12912 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12913 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12914 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12915
12916 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12917 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
12918 /* Turn off the debug UART. */
12919 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12920 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12921 /* Keep VMain power. */
12922 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12923 GRC_LCLCTRL_GPIO_OUTPUT0;
12924 }
12925
12926 /* Force the chip into D0. */
12927 err = tg3_set_power_state(tp, PCI_D0);
12928 if (err) {
12929 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12930 pci_name(tp->pdev));
12931 return err;
12932 }
12933
12934 /* Derive initial jumbo mode from MTU assigned in
12935 * ether_setup() via the alloc_etherdev() call
12936 */
12937 if (tp->dev->mtu > ETH_DATA_LEN &&
12938 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12939 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12940
12941 /* Determine WakeOnLan speed to use. */
12942 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12943 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12944 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12945 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12946 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12947 } else {
12948 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12949 }
12950
12951 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12952 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12953
12954 /* A few boards don't want Ethernet@WireSpeed phy feature */
12955 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12956 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12957 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12958 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12959 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
12960 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12961 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12962
12963 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12964 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12965 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12966 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12967 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12968
12969 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12970 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
12971 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12972 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
12973 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
12974 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12975 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12976 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12977 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12978 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12979 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12980 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12981 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12982 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12983 } else
12984 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12985 }
12986
12987 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12988 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12989 tp->phy_otp = tg3_read_otp_phycfg(tp);
12990 if (tp->phy_otp == 0)
12991 tp->phy_otp = TG3_OTP_DEFAULT;
12992 }
12993
12994 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12995 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12996 else
12997 tp->mi_mode = MAC_MI_MODE_BASE;
12998
12999 tp->coalesce_mode = 0;
13000 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13001 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13002 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13003
13004 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13005 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13006 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13007
13008 err = tg3_mdio_init(tp);
13009 if (err)
13010 return err;
13011
13012 /* Initialize data/descriptor byte/word swapping. */
13013 val = tr32(GRC_MODE);
13014 val &= GRC_MODE_HOST_STACKUP;
13015 tw32(GRC_MODE, val | tp->grc_mode);
13016
13017 tg3_switch_clocks(tp);
13018
13019 /* Clear this out for sanity. */
13020 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13021
13022 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13023 &pci_state_reg);
13024 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13025 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13026 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13027
13028 if (chiprevid == CHIPREV_ID_5701_A0 ||
13029 chiprevid == CHIPREV_ID_5701_B0 ||
13030 chiprevid == CHIPREV_ID_5701_B2 ||
13031 chiprevid == CHIPREV_ID_5701_B5) {
13032 void __iomem *sram_base;
13033
13034 /* Write some dummy words into the SRAM status block
13035 * area, see if it reads back correctly. If the return
13036 * value is bad, force enable the PCIX workaround.
13037 */
13038 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13039
13040 writel(0x00000000, sram_base);
13041 writel(0x00000000, sram_base + 4);
13042 writel(0xffffffff, sram_base + 4);
13043 if (readl(sram_base) != 0x00000000)
13044 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13045 }
13046 }
13047
13048 udelay(50);
13049 tg3_nvram_init(tp);
13050
13051 grc_misc_cfg = tr32(GRC_MISC_CFG);
13052 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13053
13054 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13055 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13056 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13057 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13058
13059 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13060 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13061 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13062 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13063 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13064 HOSTCC_MODE_CLRTICK_TXBD);
13065
13066 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13067 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13068 tp->misc_host_ctrl);
13069 }
13070
13071 /* Preserve the APE MAC_MODE bits */
13072 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13073 tp->mac_mode = tr32(MAC_MODE) |
13074 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13075 else
13076 tp->mac_mode = TG3_DEF_MAC_MODE;
13077
13078 /* these are limited to 10/100 only */
13079 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13080 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13081 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13082 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13083 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13084 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13085 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13086 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13087 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13088 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13089 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13090 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13091 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13092 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13093
13094 err = tg3_phy_probe(tp);
13095 if (err) {
13096 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13097 pci_name(tp->pdev), err);
13098 /* ... but do not return immediately ... */
13099 tg3_mdio_fini(tp);
13100 }
13101
13102 tg3_read_partno(tp);
13103 tg3_read_fw_ver(tp);
13104
13105 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13106 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13107 } else {
13108 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13109 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13110 else
13111 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13112 }
13113
13114 /* 5700 {AX,BX} chips have a broken status block link
13115 * change bit implementation, so we must use the
13116 * status register in those cases.
13117 */
13118 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13119 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13120 else
13121 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13122
13123 /* The led_ctrl is set during tg3_phy_probe, here we might
13124 * have to force the link status polling mechanism based
13125 * upon subsystem IDs.
13126 */
13127 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13128 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13129 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13130 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13131 TG3_FLAG_USE_LINKCHG_REG);
13132 }
13133
13134 /* For all SERDES we poll the MAC status register. */
13135 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13136 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13137 else
13138 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13139
13140 tp->rx_offset = NET_IP_ALIGN;
13141 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13142 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13143 tp->rx_offset = 0;
13144
13145 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13146
13147 /* Increment the rx prod index on the rx std ring by at most
13148 * 8 for these chips to workaround hw errata.
13149 */
13150 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13151 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13152 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13153 tp->rx_std_max_post = 8;
13154
13155 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13156 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13157 PCIE_PWR_MGMT_L1_THRESH_MSK;
13158
13159 return err;
13160 }
13161
13162 #ifdef CONFIG_SPARC
13163 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13164 {
13165 struct net_device *dev = tp->dev;
13166 struct pci_dev *pdev = tp->pdev;
13167 struct device_node *dp = pci_device_to_OF_node(pdev);
13168 const unsigned char *addr;
13169 int len;
13170
13171 addr = of_get_property(dp, "local-mac-address", &len);
13172 if (addr && len == 6) {
13173 memcpy(dev->dev_addr, addr, 6);
13174 memcpy(dev->perm_addr, dev->dev_addr, 6);
13175 return 0;
13176 }
13177 return -ENODEV;
13178 }
13179
13180 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13181 {
13182 struct net_device *dev = tp->dev;
13183
13184 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13185 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13186 return 0;
13187 }
13188 #endif
13189
13190 static int __devinit tg3_get_device_address(struct tg3 *tp)
13191 {
13192 struct net_device *dev = tp->dev;
13193 u32 hi, lo, mac_offset;
13194 int addr_ok = 0;
13195
13196 #ifdef CONFIG_SPARC
13197 if (!tg3_get_macaddr_sparc(tp))
13198 return 0;
13199 #endif
13200
13201 mac_offset = 0x7c;
13202 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13203 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13204 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13205 mac_offset = 0xcc;
13206 if (tg3_nvram_lock(tp))
13207 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13208 else
13209 tg3_nvram_unlock(tp);
13210 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13211 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13212 mac_offset = 0xcc;
13213 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13214 mac_offset = 0x10;
13215
13216 /* First try to get it from MAC address mailbox. */
13217 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13218 if ((hi >> 16) == 0x484b) {
13219 dev->dev_addr[0] = (hi >> 8) & 0xff;
13220 dev->dev_addr[1] = (hi >> 0) & 0xff;
13221
13222 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13223 dev->dev_addr[2] = (lo >> 24) & 0xff;
13224 dev->dev_addr[3] = (lo >> 16) & 0xff;
13225 dev->dev_addr[4] = (lo >> 8) & 0xff;
13226 dev->dev_addr[5] = (lo >> 0) & 0xff;
13227
13228 /* Some old bootcode may report a 0 MAC address in SRAM */
13229 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13230 }
13231 if (!addr_ok) {
13232 /* Next, try NVRAM. */
13233 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13234 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13235 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13236 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13237 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13238 }
13239 /* Finally just fetch it out of the MAC control regs. */
13240 else {
13241 hi = tr32(MAC_ADDR_0_HIGH);
13242 lo = tr32(MAC_ADDR_0_LOW);
13243
13244 dev->dev_addr[5] = lo & 0xff;
13245 dev->dev_addr[4] = (lo >> 8) & 0xff;
13246 dev->dev_addr[3] = (lo >> 16) & 0xff;
13247 dev->dev_addr[2] = (lo >> 24) & 0xff;
13248 dev->dev_addr[1] = hi & 0xff;
13249 dev->dev_addr[0] = (hi >> 8) & 0xff;
13250 }
13251 }
13252
13253 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13254 #ifdef CONFIG_SPARC
13255 if (!tg3_get_default_macaddr_sparc(tp))
13256 return 0;
13257 #endif
13258 return -EINVAL;
13259 }
13260 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13261 return 0;
13262 }
13263
13264 #define BOUNDARY_SINGLE_CACHELINE 1
13265 #define BOUNDARY_MULTI_CACHELINE 2
13266
13267 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13268 {
13269 int cacheline_size;
13270 u8 byte;
13271 int goal;
13272
13273 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13274 if (byte == 0)
13275 cacheline_size = 1024;
13276 else
13277 cacheline_size = (int) byte * 4;
13278
13279 /* On 5703 and later chips, the boundary bits have no
13280 * effect.
13281 */
13282 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13283 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13284 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13285 goto out;
13286
13287 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13288 goal = BOUNDARY_MULTI_CACHELINE;
13289 #else
13290 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13291 goal = BOUNDARY_SINGLE_CACHELINE;
13292 #else
13293 goal = 0;
13294 #endif
13295 #endif
13296
13297 if (!goal)
13298 goto out;
13299
13300 /* PCI controllers on most RISC systems tend to disconnect
13301 * when a device tries to burst across a cache-line boundary.
13302 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13303 *
13304 * Unfortunately, for PCI-E there are only limited
13305 * write-side controls for this, and thus for reads
13306 * we will still get the disconnects. We'll also waste
13307 * these PCI cycles for both read and write for chips
13308 * other than 5700 and 5701 which do not implement the
13309 * boundary bits.
13310 */
13311 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13312 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13313 switch (cacheline_size) {
13314 case 16:
13315 case 32:
13316 case 64:
13317 case 128:
13318 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13319 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13320 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13321 } else {
13322 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13323 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13324 }
13325 break;
13326
13327 case 256:
13328 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13329 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13330 break;
13331
13332 default:
13333 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13334 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13335 break;
13336 }
13337 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13338 switch (cacheline_size) {
13339 case 16:
13340 case 32:
13341 case 64:
13342 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13343 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13344 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13345 break;
13346 }
13347 /* fallthrough */
13348 case 128:
13349 default:
13350 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13351 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13352 break;
13353 }
13354 } else {
13355 switch (cacheline_size) {
13356 case 16:
13357 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13358 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13359 DMA_RWCTRL_WRITE_BNDRY_16);
13360 break;
13361 }
13362 /* fallthrough */
13363 case 32:
13364 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13365 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13366 DMA_RWCTRL_WRITE_BNDRY_32);
13367 break;
13368 }
13369 /* fallthrough */
13370 case 64:
13371 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13372 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13373 DMA_RWCTRL_WRITE_BNDRY_64);
13374 break;
13375 }
13376 /* fallthrough */
13377 case 128:
13378 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13379 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13380 DMA_RWCTRL_WRITE_BNDRY_128);
13381 break;
13382 }
13383 /* fallthrough */
13384 case 256:
13385 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13386 DMA_RWCTRL_WRITE_BNDRY_256);
13387 break;
13388 case 512:
13389 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13390 DMA_RWCTRL_WRITE_BNDRY_512);
13391 break;
13392 case 1024:
13393 default:
13394 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13395 DMA_RWCTRL_WRITE_BNDRY_1024);
13396 break;
13397 }
13398 }
13399
13400 out:
13401 return val;
13402 }
13403
13404 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13405 {
13406 struct tg3_internal_buffer_desc test_desc;
13407 u32 sram_dma_descs;
13408 int i, ret;
13409
13410 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13411
13412 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13413 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13414 tw32(RDMAC_STATUS, 0);
13415 tw32(WDMAC_STATUS, 0);
13416
13417 tw32(BUFMGR_MODE, 0);
13418 tw32(FTQ_RESET, 0);
13419
13420 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13421 test_desc.addr_lo = buf_dma & 0xffffffff;
13422 test_desc.nic_mbuf = 0x00002100;
13423 test_desc.len = size;
13424
13425 /*
13426 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13427 * the *second* time the tg3 driver was getting loaded after an
13428 * initial scan.
13429 *
13430 * Broadcom tells me:
13431 * ...the DMA engine is connected to the GRC block and a DMA
13432 * reset may affect the GRC block in some unpredictable way...
13433 * The behavior of resets to individual blocks has not been tested.
13434 *
13435 * Broadcom noted the GRC reset will also reset all sub-components.
13436 */
13437 if (to_device) {
13438 test_desc.cqid_sqid = (13 << 8) | 2;
13439
13440 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13441 udelay(40);
13442 } else {
13443 test_desc.cqid_sqid = (16 << 8) | 7;
13444
13445 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13446 udelay(40);
13447 }
13448 test_desc.flags = 0x00000005;
13449
13450 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13451 u32 val;
13452
13453 val = *(((u32 *)&test_desc) + i);
13454 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13455 sram_dma_descs + (i * sizeof(u32)));
13456 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13457 }
13458 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13459
13460 if (to_device) {
13461 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13462 } else {
13463 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13464 }
13465
13466 ret = -ENODEV;
13467 for (i = 0; i < 40; i++) {
13468 u32 val;
13469
13470 if (to_device)
13471 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13472 else
13473 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13474 if ((val & 0xffff) == sram_dma_descs) {
13475 ret = 0;
13476 break;
13477 }
13478
13479 udelay(100);
13480 }
13481
13482 return ret;
13483 }
13484
13485 #define TEST_BUFFER_SIZE 0x2000
13486
13487 static int __devinit tg3_test_dma(struct tg3 *tp)
13488 {
13489 dma_addr_t buf_dma;
13490 u32 *buf, saved_dma_rwctrl;
13491 int ret;
13492
13493 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13494 if (!buf) {
13495 ret = -ENOMEM;
13496 goto out_nofree;
13497 }
13498
13499 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13500 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13501
13502 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13503
13504 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13505 /* DMA read watermark not used on PCIE */
13506 tp->dma_rwctrl |= 0x00180000;
13507 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13508 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13509 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13510 tp->dma_rwctrl |= 0x003f0000;
13511 else
13512 tp->dma_rwctrl |= 0x003f000f;
13513 } else {
13514 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13515 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13516 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13517 u32 read_water = 0x7;
13518
13519 /* If the 5704 is behind the EPB bridge, we can
13520 * do the less restrictive ONE_DMA workaround for
13521 * better performance.
13522 */
13523 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13524 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13525 tp->dma_rwctrl |= 0x8000;
13526 else if (ccval == 0x6 || ccval == 0x7)
13527 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13528
13529 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13530 read_water = 4;
13531 /* Set bit 23 to enable PCIX hw bug fix */
13532 tp->dma_rwctrl |=
13533 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13534 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13535 (1 << 23);
13536 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13537 /* 5780 always in PCIX mode */
13538 tp->dma_rwctrl |= 0x00144000;
13539 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13540 /* 5714 always in PCIX mode */
13541 tp->dma_rwctrl |= 0x00148000;
13542 } else {
13543 tp->dma_rwctrl |= 0x001b000f;
13544 }
13545 }
13546
13547 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13548 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13549 tp->dma_rwctrl &= 0xfffffff0;
13550
13551 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13552 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13553 /* Remove this if it causes problems for some boards. */
13554 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13555
13556 /* On 5700/5701 chips, we need to set this bit.
13557 * Otherwise the chip will issue cacheline transactions
13558 * to streamable DMA memory with not all the byte
13559 * enables turned on. This is an error on several
13560 * RISC PCI controllers, in particular sparc64.
13561 *
13562 * On 5703/5704 chips, this bit has been reassigned
13563 * a different meaning. In particular, it is used
13564 * on those chips to enable a PCI-X workaround.
13565 */
13566 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13567 }
13568
13569 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13570
13571 #if 0
13572 /* Unneeded, already done by tg3_get_invariants. */
13573 tg3_switch_clocks(tp);
13574 #endif
13575
13576 ret = 0;
13577 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13578 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13579 goto out;
13580
13581 /* It is best to perform DMA test with maximum write burst size
13582 * to expose the 5700/5701 write DMA bug.
13583 */
13584 saved_dma_rwctrl = tp->dma_rwctrl;
13585 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13586 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13587
13588 while (1) {
13589 u32 *p = buf, i;
13590
13591 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13592 p[i] = i;
13593
13594 /* Send the buffer to the chip. */
13595 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13596 if (ret) {
13597 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13598 break;
13599 }
13600
13601 #if 0
13602 /* validate data reached card RAM correctly. */
13603 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13604 u32 val;
13605 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13606 if (le32_to_cpu(val) != p[i]) {
13607 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
13608 /* ret = -ENODEV here? */
13609 }
13610 p[i] = 0;
13611 }
13612 #endif
13613 /* Now read it back. */
13614 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13615 if (ret) {
13616 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13617
13618 break;
13619 }
13620
13621 /* Verify it. */
13622 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13623 if (p[i] == i)
13624 continue;
13625
13626 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13627 DMA_RWCTRL_WRITE_BNDRY_16) {
13628 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13629 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13630 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13631 break;
13632 } else {
13633 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13634 ret = -ENODEV;
13635 goto out;
13636 }
13637 }
13638
13639 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13640 /* Success. */
13641 ret = 0;
13642 break;
13643 }
13644 }
13645 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13646 DMA_RWCTRL_WRITE_BNDRY_16) {
13647 static struct pci_device_id dma_wait_state_chipsets[] = {
13648 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13649 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13650 { },
13651 };
13652
13653 /* DMA test passed without adjusting DMA boundary,
13654 * now look for chipsets that are known to expose the
13655 * DMA bug without failing the test.
13656 */
13657 if (pci_dev_present(dma_wait_state_chipsets)) {
13658 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13659 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13660 }
13661 else
13662 /* Safe to use the calculated DMA boundary. */
13663 tp->dma_rwctrl = saved_dma_rwctrl;
13664
13665 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13666 }
13667
13668 out:
13669 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13670 out_nofree:
13671 return ret;
13672 }
13673
13674 static void __devinit tg3_init_link_config(struct tg3 *tp)
13675 {
13676 tp->link_config.advertising =
13677 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13678 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13679 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13680 ADVERTISED_Autoneg | ADVERTISED_MII);
13681 tp->link_config.speed = SPEED_INVALID;
13682 tp->link_config.duplex = DUPLEX_INVALID;
13683 tp->link_config.autoneg = AUTONEG_ENABLE;
13684 tp->link_config.active_speed = SPEED_INVALID;
13685 tp->link_config.active_duplex = DUPLEX_INVALID;
13686 tp->link_config.phy_is_low_power = 0;
13687 tp->link_config.orig_speed = SPEED_INVALID;
13688 tp->link_config.orig_duplex = DUPLEX_INVALID;
13689 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13690 }
13691
13692 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13693 {
13694 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
13695 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
13696 tp->bufmgr_config.mbuf_read_dma_low_water =
13697 DEFAULT_MB_RDMA_LOW_WATER_5705;
13698 tp->bufmgr_config.mbuf_mac_rx_low_water =
13699 DEFAULT_MB_MACRX_LOW_WATER_5705;
13700 tp->bufmgr_config.mbuf_high_water =
13701 DEFAULT_MB_HIGH_WATER_5705;
13702 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13703 tp->bufmgr_config.mbuf_mac_rx_low_water =
13704 DEFAULT_MB_MACRX_LOW_WATER_5906;
13705 tp->bufmgr_config.mbuf_high_water =
13706 DEFAULT_MB_HIGH_WATER_5906;
13707 }
13708
13709 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13710 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13711 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13712 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13713 tp->bufmgr_config.mbuf_high_water_jumbo =
13714 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13715 } else {
13716 tp->bufmgr_config.mbuf_read_dma_low_water =
13717 DEFAULT_MB_RDMA_LOW_WATER;
13718 tp->bufmgr_config.mbuf_mac_rx_low_water =
13719 DEFAULT_MB_MACRX_LOW_WATER;
13720 tp->bufmgr_config.mbuf_high_water =
13721 DEFAULT_MB_HIGH_WATER;
13722
13723 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13724 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13725 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13726 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13727 tp->bufmgr_config.mbuf_high_water_jumbo =
13728 DEFAULT_MB_HIGH_WATER_JUMBO;
13729 }
13730
13731 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13732 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13733 }
13734
13735 static char * __devinit tg3_phy_string(struct tg3 *tp)
13736 {
13737 switch (tp->phy_id & PHY_ID_MASK) {
13738 case PHY_ID_BCM5400: return "5400";
13739 case PHY_ID_BCM5401: return "5401";
13740 case PHY_ID_BCM5411: return "5411";
13741 case PHY_ID_BCM5701: return "5701";
13742 case PHY_ID_BCM5703: return "5703";
13743 case PHY_ID_BCM5704: return "5704";
13744 case PHY_ID_BCM5705: return "5705";
13745 case PHY_ID_BCM5750: return "5750";
13746 case PHY_ID_BCM5752: return "5752";
13747 case PHY_ID_BCM5714: return "5714";
13748 case PHY_ID_BCM5780: return "5780";
13749 case PHY_ID_BCM5755: return "5755";
13750 case PHY_ID_BCM5787: return "5787";
13751 case PHY_ID_BCM5784: return "5784";
13752 case PHY_ID_BCM5756: return "5722/5756";
13753 case PHY_ID_BCM5906: return "5906";
13754 case PHY_ID_BCM5761: return "5761";
13755 case PHY_ID_BCM8002: return "8002/serdes";
13756 case 0: return "serdes";
13757 default: return "unknown";
13758 }
13759 }
13760
13761 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13762 {
13763 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13764 strcpy(str, "PCI Express");
13765 return str;
13766 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13767 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13768
13769 strcpy(str, "PCIX:");
13770
13771 if ((clock_ctrl == 7) ||
13772 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13773 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13774 strcat(str, "133MHz");
13775 else if (clock_ctrl == 0)
13776 strcat(str, "33MHz");
13777 else if (clock_ctrl == 2)
13778 strcat(str, "50MHz");
13779 else if (clock_ctrl == 4)
13780 strcat(str, "66MHz");
13781 else if (clock_ctrl == 6)
13782 strcat(str, "100MHz");
13783 } else {
13784 strcpy(str, "PCI:");
13785 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13786 strcat(str, "66MHz");
13787 else
13788 strcat(str, "33MHz");
13789 }
13790 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13791 strcat(str, ":32-bit");
13792 else
13793 strcat(str, ":64-bit");
13794 return str;
13795 }
13796
13797 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13798 {
13799 struct pci_dev *peer;
13800 unsigned int func, devnr = tp->pdev->devfn & ~7;
13801
13802 for (func = 0; func < 8; func++) {
13803 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13804 if (peer && peer != tp->pdev)
13805 break;
13806 pci_dev_put(peer);
13807 }
13808 /* 5704 can be configured in single-port mode, set peer to
13809 * tp->pdev in that case.
13810 */
13811 if (!peer) {
13812 peer = tp->pdev;
13813 return peer;
13814 }
13815
13816 /*
13817 * We don't need to keep the refcount elevated; there's no way
13818 * to remove one half of this device without removing the other
13819 */
13820 pci_dev_put(peer);
13821
13822 return peer;
13823 }
13824
13825 static void __devinit tg3_init_coal(struct tg3 *tp)
13826 {
13827 struct ethtool_coalesce *ec = &tp->coal;
13828
13829 memset(ec, 0, sizeof(*ec));
13830 ec->cmd = ETHTOOL_GCOALESCE;
13831 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13832 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13833 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13834 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13835 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13836 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13837 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13838 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13839 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13840
13841 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13842 HOSTCC_MODE_CLRTICK_TXBD)) {
13843 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13844 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13845 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13846 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13847 }
13848
13849 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13850 ec->rx_coalesce_usecs_irq = 0;
13851 ec->tx_coalesce_usecs_irq = 0;
13852 ec->stats_block_coalesce_usecs = 0;
13853 }
13854 }
13855
13856 static const struct net_device_ops tg3_netdev_ops = {
13857 .ndo_open = tg3_open,
13858 .ndo_stop = tg3_close,
13859 .ndo_start_xmit = tg3_start_xmit,
13860 .ndo_get_stats = tg3_get_stats,
13861 .ndo_validate_addr = eth_validate_addr,
13862 .ndo_set_multicast_list = tg3_set_rx_mode,
13863 .ndo_set_mac_address = tg3_set_mac_addr,
13864 .ndo_do_ioctl = tg3_ioctl,
13865 .ndo_tx_timeout = tg3_tx_timeout,
13866 .ndo_change_mtu = tg3_change_mtu,
13867 #if TG3_VLAN_TAG_USED
13868 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13869 #endif
13870 #ifdef CONFIG_NET_POLL_CONTROLLER
13871 .ndo_poll_controller = tg3_poll_controller,
13872 #endif
13873 };
13874
13875 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13876 .ndo_open = tg3_open,
13877 .ndo_stop = tg3_close,
13878 .ndo_start_xmit = tg3_start_xmit_dma_bug,
13879 .ndo_get_stats = tg3_get_stats,
13880 .ndo_validate_addr = eth_validate_addr,
13881 .ndo_set_multicast_list = tg3_set_rx_mode,
13882 .ndo_set_mac_address = tg3_set_mac_addr,
13883 .ndo_do_ioctl = tg3_ioctl,
13884 .ndo_tx_timeout = tg3_tx_timeout,
13885 .ndo_change_mtu = tg3_change_mtu,
13886 #if TG3_VLAN_TAG_USED
13887 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13888 #endif
13889 #ifdef CONFIG_NET_POLL_CONTROLLER
13890 .ndo_poll_controller = tg3_poll_controller,
13891 #endif
13892 };
13893
13894 static int __devinit tg3_init_one(struct pci_dev *pdev,
13895 const struct pci_device_id *ent)
13896 {
13897 static int tg3_version_printed = 0;
13898 struct net_device *dev;
13899 struct tg3 *tp;
13900 int i, err, pm_cap;
13901 u32 sndmbx, rcvmbx, intmbx;
13902 char str[40];
13903 u64 dma_mask, persist_dma_mask;
13904
13905 if (tg3_version_printed++ == 0)
13906 printk(KERN_INFO "%s", version);
13907
13908 err = pci_enable_device(pdev);
13909 if (err) {
13910 printk(KERN_ERR PFX "Cannot enable PCI device, "
13911 "aborting.\n");
13912 return err;
13913 }
13914
13915 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13916 if (err) {
13917 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13918 "aborting.\n");
13919 goto err_out_disable_pdev;
13920 }
13921
13922 pci_set_master(pdev);
13923
13924 /* Find power-management capability. */
13925 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13926 if (pm_cap == 0) {
13927 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13928 "aborting.\n");
13929 err = -EIO;
13930 goto err_out_free_res;
13931 }
13932
13933 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
13934 if (!dev) {
13935 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13936 err = -ENOMEM;
13937 goto err_out_free_res;
13938 }
13939
13940 SET_NETDEV_DEV(dev, &pdev->dev);
13941
13942 #if TG3_VLAN_TAG_USED
13943 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13944 #endif
13945
13946 tp = netdev_priv(dev);
13947 tp->pdev = pdev;
13948 tp->dev = dev;
13949 tp->pm_cap = pm_cap;
13950 tp->rx_mode = TG3_DEF_RX_MODE;
13951 tp->tx_mode = TG3_DEF_TX_MODE;
13952
13953 if (tg3_debug > 0)
13954 tp->msg_enable = tg3_debug;
13955 else
13956 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13957
13958 /* The word/byte swap controls here control register access byte
13959 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13960 * setting below.
13961 */
13962 tp->misc_host_ctrl =
13963 MISC_HOST_CTRL_MASK_PCI_INT |
13964 MISC_HOST_CTRL_WORD_SWAP |
13965 MISC_HOST_CTRL_INDIR_ACCESS |
13966 MISC_HOST_CTRL_PCISTATE_RW;
13967
13968 /* The NONFRM (non-frame) byte/word swap controls take effect
13969 * on descriptor entries, anything which isn't packet data.
13970 *
13971 * The StrongARM chips on the board (one for tx, one for rx)
13972 * are running in big-endian mode.
13973 */
13974 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13975 GRC_MODE_WSWAP_NONFRM_DATA);
13976 #ifdef __BIG_ENDIAN
13977 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13978 #endif
13979 spin_lock_init(&tp->lock);
13980 spin_lock_init(&tp->indirect_lock);
13981 INIT_WORK(&tp->reset_task, tg3_reset_task);
13982
13983 tp->regs = pci_ioremap_bar(pdev, BAR_0);
13984 if (!tp->regs) {
13985 printk(KERN_ERR PFX "Cannot map device registers, "
13986 "aborting.\n");
13987 err = -ENOMEM;
13988 goto err_out_free_dev;
13989 }
13990
13991 tg3_init_link_config(tp);
13992
13993 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13994 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13995
13996 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
13997 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
13998 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
13999 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14000 struct tg3_napi *tnapi = &tp->napi[i];
14001
14002 tnapi->tp = tp;
14003 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14004
14005 tnapi->int_mbox = intmbx;
14006 if (i < 4)
14007 intmbx += 0x8;
14008 else
14009 intmbx += 0x4;
14010
14011 tnapi->consmbox = rcvmbx;
14012 tnapi->prodmbox = sndmbx;
14013
14014 if (i)
14015 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14016 else
14017 tnapi->coal_now = HOSTCC_MODE_NOW;
14018
14019 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14020 break;
14021
14022 /*
14023 * If we support MSIX, we'll be using RSS. If we're using
14024 * RSS, the first vector only handles link interrupts and the
14025 * remaining vectors handle rx and tx interrupts. Reuse the
14026 * mailbox values for the next iteration. The values we setup
14027 * above are still useful for the single vectored mode.
14028 */
14029 if (!i)
14030 continue;
14031
14032 rcvmbx += 0x8;
14033
14034 if (sndmbx & 0x4)
14035 sndmbx -= 0x4;
14036 else
14037 sndmbx += 0xc;
14038 }
14039
14040 netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
14041 dev->ethtool_ops = &tg3_ethtool_ops;
14042 dev->watchdog_timeo = TG3_TX_TIMEOUT;
14043 dev->irq = pdev->irq;
14044
14045 err = tg3_get_invariants(tp);
14046 if (err) {
14047 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14048 "aborting.\n");
14049 goto err_out_iounmap;
14050 }
14051
14052 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
14053 dev->netdev_ops = &tg3_netdev_ops;
14054 else
14055 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14056
14057
14058 /* The EPB bridge inside 5714, 5715, and 5780 and any
14059 * device behind the EPB cannot support DMA addresses > 40-bit.
14060 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14061 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14062 * do DMA address check in tg3_start_xmit().
14063 */
14064 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14065 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14066 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14067 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14068 #ifdef CONFIG_HIGHMEM
14069 dma_mask = DMA_BIT_MASK(64);
14070 #endif
14071 } else
14072 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14073
14074 /* Configure DMA attributes. */
14075 if (dma_mask > DMA_BIT_MASK(32)) {
14076 err = pci_set_dma_mask(pdev, dma_mask);
14077 if (!err) {
14078 dev->features |= NETIF_F_HIGHDMA;
14079 err = pci_set_consistent_dma_mask(pdev,
14080 persist_dma_mask);
14081 if (err < 0) {
14082 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14083 "DMA for consistent allocations\n");
14084 goto err_out_iounmap;
14085 }
14086 }
14087 }
14088 if (err || dma_mask == DMA_BIT_MASK(32)) {
14089 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14090 if (err) {
14091 printk(KERN_ERR PFX "No usable DMA configuration, "
14092 "aborting.\n");
14093 goto err_out_iounmap;
14094 }
14095 }
14096
14097 tg3_init_bufmgr_config(tp);
14098
14099 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14100 tp->fw_needed = FIRMWARE_TG3;
14101
14102 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
14103 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14104 }
14105 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14106 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
14107 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
14108 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
14109 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
14110 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
14111 } else {
14112 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
14113 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
14114 tp->fw_needed = FIRMWARE_TG3TSO5;
14115 else
14116 tp->fw_needed = FIRMWARE_TG3TSO;
14117 }
14118
14119 /* TSO is on by default on chips that support hardware TSO.
14120 * Firmware TSO on older chips gives lower performance, so it
14121 * is off by default, but can be enabled using ethtool.
14122 */
14123 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
14124 if (dev->features & NETIF_F_IP_CSUM)
14125 dev->features |= NETIF_F_TSO;
14126 if ((dev->features & NETIF_F_IPV6_CSUM) &&
14127 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
14128 dev->features |= NETIF_F_TSO6;
14129 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14130 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14131 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14132 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14133 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14134 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
14135 dev->features |= NETIF_F_TSO_ECN;
14136 }
14137
14138
14139 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14140 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14141 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14142 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14143 tp->rx_pending = 63;
14144 }
14145
14146 err = tg3_get_device_address(tp);
14147 if (err) {
14148 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14149 "aborting.\n");
14150 goto err_out_fw;
14151 }
14152
14153 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14154 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14155 if (!tp->aperegs) {
14156 printk(KERN_ERR PFX "Cannot map APE registers, "
14157 "aborting.\n");
14158 err = -ENOMEM;
14159 goto err_out_fw;
14160 }
14161
14162 tg3_ape_lock_init(tp);
14163
14164 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14165 tg3_read_dash_ver(tp);
14166 }
14167
14168 /*
14169 * Reset chip in case UNDI or EFI driver did not shutdown
14170 * DMA self test will enable WDMAC and we'll see (spurious)
14171 * pending DMA on the PCI bus at that point.
14172 */
14173 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14174 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14175 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14176 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14177 }
14178
14179 err = tg3_test_dma(tp);
14180 if (err) {
14181 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
14182 goto err_out_apeunmap;
14183 }
14184
14185 /* flow control autonegotiation is default behavior */
14186 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14187 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14188
14189 tg3_init_coal(tp);
14190
14191 pci_set_drvdata(pdev, dev);
14192
14193 err = register_netdev(dev);
14194 if (err) {
14195 printk(KERN_ERR PFX "Cannot register net device, "
14196 "aborting.\n");
14197 goto err_out_apeunmap;
14198 }
14199
14200 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14201 dev->name,
14202 tp->board_part_number,
14203 tp->pci_chip_rev_id,
14204 tg3_bus_string(tp, str),
14205 dev->dev_addr);
14206
14207 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14208 struct phy_device *phydev;
14209 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14210 printk(KERN_INFO
14211 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14212 tp->dev->name, phydev->drv->name,
14213 dev_name(&phydev->dev));
14214 } else
14215 printk(KERN_INFO
14216 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14217 tp->dev->name, tg3_phy_string(tp),
14218 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14219 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14220 "10/100/1000Base-T")),
14221 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14222
14223 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14224 dev->name,
14225 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14226 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14227 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14228 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14229 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14230 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14231 dev->name, tp->dma_rwctrl,
14232 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
14233 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
14234
14235 return 0;
14236
14237 err_out_apeunmap:
14238 if (tp->aperegs) {
14239 iounmap(tp->aperegs);
14240 tp->aperegs = NULL;
14241 }
14242
14243 err_out_fw:
14244 if (tp->fw)
14245 release_firmware(tp->fw);
14246
14247 err_out_iounmap:
14248 if (tp->regs) {
14249 iounmap(tp->regs);
14250 tp->regs = NULL;
14251 }
14252
14253 err_out_free_dev:
14254 free_netdev(dev);
14255
14256 err_out_free_res:
14257 pci_release_regions(pdev);
14258
14259 err_out_disable_pdev:
14260 pci_disable_device(pdev);
14261 pci_set_drvdata(pdev, NULL);
14262 return err;
14263 }
14264
14265 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14266 {
14267 struct net_device *dev = pci_get_drvdata(pdev);
14268
14269 if (dev) {
14270 struct tg3 *tp = netdev_priv(dev);
14271
14272 if (tp->fw)
14273 release_firmware(tp->fw);
14274
14275 flush_scheduled_work();
14276
14277 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14278 tg3_phy_fini(tp);
14279 tg3_mdio_fini(tp);
14280 }
14281
14282 unregister_netdev(dev);
14283 if (tp->aperegs) {
14284 iounmap(tp->aperegs);
14285 tp->aperegs = NULL;
14286 }
14287 if (tp->regs) {
14288 iounmap(tp->regs);
14289 tp->regs = NULL;
14290 }
14291 free_netdev(dev);
14292 pci_release_regions(pdev);
14293 pci_disable_device(pdev);
14294 pci_set_drvdata(pdev, NULL);
14295 }
14296 }
14297
14298 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14299 {
14300 struct net_device *dev = pci_get_drvdata(pdev);
14301 struct tg3 *tp = netdev_priv(dev);
14302 pci_power_t target_state;
14303 int err;
14304
14305 /* PCI register 4 needs to be saved whether netif_running() or not.
14306 * MSI address and data need to be saved if using MSI and
14307 * netif_running().
14308 */
14309 pci_save_state(pdev);
14310
14311 if (!netif_running(dev))
14312 return 0;
14313
14314 flush_scheduled_work();
14315 tg3_phy_stop(tp);
14316 tg3_netif_stop(tp);
14317
14318 del_timer_sync(&tp->timer);
14319
14320 tg3_full_lock(tp, 1);
14321 tg3_disable_ints(tp);
14322 tg3_full_unlock(tp);
14323
14324 netif_device_detach(dev);
14325
14326 tg3_full_lock(tp, 0);
14327 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14328 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14329 tg3_full_unlock(tp);
14330
14331 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14332
14333 err = tg3_set_power_state(tp, target_state);
14334 if (err) {
14335 int err2;
14336
14337 tg3_full_lock(tp, 0);
14338
14339 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14340 err2 = tg3_restart_hw(tp, 1);
14341 if (err2)
14342 goto out;
14343
14344 tp->timer.expires = jiffies + tp->timer_offset;
14345 add_timer(&tp->timer);
14346
14347 netif_device_attach(dev);
14348 tg3_netif_start(tp);
14349
14350 out:
14351 tg3_full_unlock(tp);
14352
14353 if (!err2)
14354 tg3_phy_start(tp);
14355 }
14356
14357 return err;
14358 }
14359
14360 static int tg3_resume(struct pci_dev *pdev)
14361 {
14362 struct net_device *dev = pci_get_drvdata(pdev);
14363 struct tg3 *tp = netdev_priv(dev);
14364 int err;
14365
14366 pci_restore_state(tp->pdev);
14367
14368 if (!netif_running(dev))
14369 return 0;
14370
14371 err = tg3_set_power_state(tp, PCI_D0);
14372 if (err)
14373 return err;
14374
14375 netif_device_attach(dev);
14376
14377 tg3_full_lock(tp, 0);
14378
14379 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14380 err = tg3_restart_hw(tp, 1);
14381 if (err)
14382 goto out;
14383
14384 tp->timer.expires = jiffies + tp->timer_offset;
14385 add_timer(&tp->timer);
14386
14387 tg3_netif_start(tp);
14388
14389 out:
14390 tg3_full_unlock(tp);
14391
14392 if (!err)
14393 tg3_phy_start(tp);
14394
14395 return err;
14396 }
14397
14398 static struct pci_driver tg3_driver = {
14399 .name = DRV_MODULE_NAME,
14400 .id_table = tg3_pci_tbl,
14401 .probe = tg3_init_one,
14402 .remove = __devexit_p(tg3_remove_one),
14403 .suspend = tg3_suspend,
14404 .resume = tg3_resume
14405 };
14406
14407 static int __init tg3_init(void)
14408 {
14409 return pci_register_driver(&tg3_driver);
14410 }
14411
14412 static void __exit tg3_cleanup(void)
14413 {
14414 pci_unregister_driver(&tg3_driver);
14415 }
14416
14417 module_init(tg3_init);
14418 module_exit(tg3_cleanup);
AMDTP streaming driver for the Linux FireWire stack (Juju)