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libertas: convert CMD_MESH_ACCESS to a direct command
[firewire-audio.git] / drivers / net / ns83820.c
blob3652c6c926a60da1ae934fc9e2690e20df6e3152
1 #define VERSION "0.23"
2 /* ns83820.c by Benjamin LaHaise with contributions.
3 *
4 * Questions/comments/discussion to linux-ns83820@kvack.org.
5 *
6 * $Revision: 1.34.2.23 $
7 *
8 * Copyright 2001 Benjamin LaHaise.
9 * Copyright 2001, 2002 Red Hat.
10 *
11 * Mmmm, chocolate vanilla mocha...
12 *
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 *
29 * ChangeLog
30 * =========
31 * 20010414 0.1 - created
32 * 20010622 0.2 - basic rx and tx.
33 * 20010711 0.3 - added duplex and link state detection support.
34 * 20010713 0.4 - zero copy, no hangs.
35 * 0.5 - 64 bit dma support (davem will hate me for this)
36 * - disable jumbo frames to avoid tx hangs
37 * - work around tx deadlocks on my 1.02 card via
38 * fiddling with TXCFG
39 * 20010810 0.6 - use pci dma api for ringbuffers, work on ia64
40 * 20010816 0.7 - misc cleanups
41 * 20010826 0.8 - fix critical zero copy bugs
42 * 0.9 - internal experiment
43 * 20010827 0.10 - fix ia64 unaligned access.
44 * 20010906 0.11 - accept all packets with checksum errors as
45 * otherwise fragments get lost
46 * - fix >> 32 bugs
47 * 0.12 - add statistics counters
48 * - add allmulti/promisc support
49 * 20011009 0.13 - hotplug support, other smaller pci api cleanups
50 * 20011204 0.13a - optical transceiver support added
51 * by Michael Clark <michael@metaparadigm.com>
52 * 20011205 0.13b - call register_netdev earlier in initialization
53 * suppress duplicate link status messages
54 * 20011117 0.14 - ethtool GDRVINFO, GLINK support from jgarzik
55 * 20011204 0.15 get ppc (big endian) working
56 * 20011218 0.16 various cleanups
57 * 20020310 0.17 speedups
58 * 20020610 0.18 - actually use the pci dma api for highmem
59 * - remove pci latency register fiddling
60 * 0.19 - better bist support
61 * - add ihr and reset_phy parameters
62 * - gmii bus probing
63 * - fix missed txok introduced during performance
64 * tuning
65 * 0.20 - fix stupid RFEN thinko. i am such a smurf.
66 * 20040828 0.21 - add hardware vlan accleration
67 * by Neil Horman <nhorman@redhat.com>
68 * 20050406 0.22 - improved DAC ifdefs from Andi Kleen
69 * - removal of dead code from Adrian Bunk
70 * - fix half duplex collision behaviour
71 * Driver Overview
72 * ===============
73 *
74 * This driver was originally written for the National Semiconductor
75 * 83820 chip, a 10/100/1000 Mbps 64 bit PCI ethernet NIC. Hopefully
76 * this code will turn out to be a) clean, b) correct, and c) fast.
77 * With that in mind, I'm aiming to split the code up as much as
78 * reasonably possible. At present there are X major sections that
79 * break down into a) packet receive, b) packet transmit, c) link
80 * management, d) initialization and configuration. Where possible,
81 * these code paths are designed to run in parallel.
82 *
83 * This driver has been tested and found to work with the following
84 * cards (in no particular order):
85 *
86 * Cameo SOHO-GA2000T SOHO-GA2500T
87 * D-Link DGE-500T
88 * PureData PDP8023Z-TG
89 * SMC SMC9452TX SMC9462TX
90 * Netgear GA621
91 *
92 * Special thanks to SMC for providing hardware to test this driver on.
93 *
94 * Reports of success or failure would be greatly appreciated.
95 */
96 //#define dprintk printk
97 #define dprintk(x...) do { } while (0)
98
99 #include <linux/module.h>
100 #include <linux/moduleparam.h>
101 #include <linux/types.h>
102 #include <linux/pci.h>
103 #include <linux/dma-mapping.h>
104 #include <linux/netdevice.h>
105 #include <linux/etherdevice.h>
106 #include <linux/delay.h>
107 #include <linux/workqueue.h>
108 #include <linux/init.h>
109 #include <linux/ip.h> /* for iph */
110 #include <linux/in.h> /* for IPPROTO_... */
111 #include <linux/compiler.h>
112 #include <linux/prefetch.h>
113 #include <linux/ethtool.h>
114 #include <linux/timer.h>
115 #include <linux/if_vlan.h>
116 #include <linux/rtnetlink.h>
117 #include <linux/jiffies.h>
118
119 #include <asm/io.h>
120 #include <asm/uaccess.h>
121 #include <asm/system.h>
122
123 #define DRV_NAME "ns83820"
124
125 /* Global parameters. See module_param near the bottom. */
126 static int ihr = 2;
127 static int reset_phy = 0;
128 static int lnksts = 0; /* CFG_LNKSTS bit polarity */
129
130 /* Dprintk is used for more interesting debug events */
131 #undef Dprintk
132 #define Dprintk dprintk
133
134 /* tunables */
135 #define RX_BUF_SIZE 1500 /* 8192 */
136 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
137 #define NS83820_VLAN_ACCEL_SUPPORT
138 #endif
139
140 /* Must not exceed ~65000. */
141 #define NR_RX_DESC 64
142 #define NR_TX_DESC 128
143
144 /* not tunable */
145 #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14) /* rx/tx mac addr + type */
146
147 #define MIN_TX_DESC_FREE 8
148
149 /* register defines */
150 #define CFGCS 0x04
151
152 #define CR_TXE 0x00000001
153 #define CR_TXD 0x00000002
154 /* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE
155 * The Receive engine skips one descriptor and moves
156 * onto the next one!! */
157 #define CR_RXE 0x00000004
158 #define CR_RXD 0x00000008
159 #define CR_TXR 0x00000010
160 #define CR_RXR 0x00000020
161 #define CR_SWI 0x00000080
162 #define CR_RST 0x00000100
163
164 #define PTSCR_EEBIST_FAIL 0x00000001
165 #define PTSCR_EEBIST_EN 0x00000002
166 #define PTSCR_EELOAD_EN 0x00000004
167 #define PTSCR_RBIST_FAIL 0x000001b8
168 #define PTSCR_RBIST_DONE 0x00000200
169 #define PTSCR_RBIST_EN 0x00000400
170 #define PTSCR_RBIST_RST 0x00002000
171
172 #define MEAR_EEDI 0x00000001
173 #define MEAR_EEDO 0x00000002
174 #define MEAR_EECLK 0x00000004
175 #define MEAR_EESEL 0x00000008
176 #define MEAR_MDIO 0x00000010
177 #define MEAR_MDDIR 0x00000020
178 #define MEAR_MDC 0x00000040
179
180 #define ISR_TXDESC3 0x40000000
181 #define ISR_TXDESC2 0x20000000
182 #define ISR_TXDESC1 0x10000000
183 #define ISR_TXDESC0 0x08000000
184 #define ISR_RXDESC3 0x04000000
185 #define ISR_RXDESC2 0x02000000
186 #define ISR_RXDESC1 0x01000000
187 #define ISR_RXDESC0 0x00800000
188 #define ISR_TXRCMP 0x00400000
189 #define ISR_RXRCMP 0x00200000
190 #define ISR_DPERR 0x00100000
191 #define ISR_SSERR 0x00080000
192 #define ISR_RMABT 0x00040000
193 #define ISR_RTABT 0x00020000
194 #define ISR_RXSOVR 0x00010000
195 #define ISR_HIBINT 0x00008000
196 #define ISR_PHY 0x00004000
197 #define ISR_PME 0x00002000
198 #define ISR_SWI 0x00001000
199 #define ISR_MIB 0x00000800
200 #define ISR_TXURN 0x00000400
201 #define ISR_TXIDLE 0x00000200
202 #define ISR_TXERR 0x00000100
203 #define ISR_TXDESC 0x00000080
204 #define ISR_TXOK 0x00000040
205 #define ISR_RXORN 0x00000020
206 #define ISR_RXIDLE 0x00000010
207 #define ISR_RXEARLY 0x00000008
208 #define ISR_RXERR 0x00000004
209 #define ISR_RXDESC 0x00000002
210 #define ISR_RXOK 0x00000001
211
212 #define TXCFG_CSI 0x80000000
213 #define TXCFG_HBI 0x40000000
214 #define TXCFG_MLB 0x20000000
215 #define TXCFG_ATP 0x10000000
216 #define TXCFG_ECRETRY 0x00800000
217 #define TXCFG_BRST_DIS 0x00080000
218 #define TXCFG_MXDMA1024 0x00000000
219 #define TXCFG_MXDMA512 0x00700000
220 #define TXCFG_MXDMA256 0x00600000
221 #define TXCFG_MXDMA128 0x00500000
222 #define TXCFG_MXDMA64 0x00400000
223 #define TXCFG_MXDMA32 0x00300000
224 #define TXCFG_MXDMA16 0x00200000
225 #define TXCFG_MXDMA8 0x00100000
226
227 #define CFG_LNKSTS 0x80000000
228 #define CFG_SPDSTS 0x60000000
229 #define CFG_SPDSTS1 0x40000000
230 #define CFG_SPDSTS0 0x20000000
231 #define CFG_DUPSTS 0x10000000
232 #define CFG_TBI_EN 0x01000000
233 #define CFG_MODE_1000 0x00400000
234 /* Ramit : Dont' ever use AUTO_1000, it never works and is buggy.
235 * Read the Phy response and then configure the MAC accordingly */
236 #define CFG_AUTO_1000 0x00200000
237 #define CFG_PINT_CTL 0x001c0000
238 #define CFG_PINT_DUPSTS 0x00100000
239 #define CFG_PINT_LNKSTS 0x00080000
240 #define CFG_PINT_SPDSTS 0x00040000
241 #define CFG_TMRTEST 0x00020000
242 #define CFG_MRM_DIS 0x00010000
243 #define CFG_MWI_DIS 0x00008000
244 #define CFG_T64ADDR 0x00004000
245 #define CFG_PCI64_DET 0x00002000
246 #define CFG_DATA64_EN 0x00001000
247 #define CFG_M64ADDR 0x00000800
248 #define CFG_PHY_RST 0x00000400
249 #define CFG_PHY_DIS 0x00000200
250 #define CFG_EXTSTS_EN 0x00000100
251 #define CFG_REQALG 0x00000080
252 #define CFG_SB 0x00000040
253 #define CFG_POW 0x00000020
254 #define CFG_EXD 0x00000010
255 #define CFG_PESEL 0x00000008
256 #define CFG_BROM_DIS 0x00000004
257 #define CFG_EXT_125 0x00000002
258 #define CFG_BEM 0x00000001
259
260 #define EXTSTS_UDPPKT 0x00200000
261 #define EXTSTS_TCPPKT 0x00080000
262 #define EXTSTS_IPPKT 0x00020000
263 #define EXTSTS_VPKT 0x00010000
264 #define EXTSTS_VTG_MASK 0x0000ffff
265
266 #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
267
268 #define MIBC_MIBS 0x00000008
269 #define MIBC_ACLR 0x00000004
270 #define MIBC_FRZ 0x00000002
271 #define MIBC_WRN 0x00000001
272
273 #define PCR_PSEN (1 << 31)
274 #define PCR_PS_MCAST (1 << 30)
275 #define PCR_PS_DA (1 << 29)
276 #define PCR_STHI_8 (3 << 23)
277 #define PCR_STLO_4 (1 << 23)
278 #define PCR_FFHI_8K (3 << 21)
279 #define PCR_FFLO_4K (1 << 21)
280 #define PCR_PAUSE_CNT 0xFFFE
281
282 #define RXCFG_AEP 0x80000000
283 #define RXCFG_ARP 0x40000000
284 #define RXCFG_STRIPCRC 0x20000000
285 #define RXCFG_RX_FD 0x10000000
286 #define RXCFG_ALP 0x08000000
287 #define RXCFG_AIRL 0x04000000
288 #define RXCFG_MXDMA512 0x00700000
289 #define RXCFG_DRTH 0x0000003e
290 #define RXCFG_DRTH0 0x00000002
291
292 #define RFCR_RFEN 0x80000000
293 #define RFCR_AAB 0x40000000
294 #define RFCR_AAM 0x20000000
295 #define RFCR_AAU 0x10000000
296 #define RFCR_APM 0x08000000
297 #define RFCR_APAT 0x07800000
298 #define RFCR_APAT3 0x04000000
299 #define RFCR_APAT2 0x02000000
300 #define RFCR_APAT1 0x01000000
301 #define RFCR_APAT0 0x00800000
302 #define RFCR_AARP 0x00400000
303 #define RFCR_MHEN 0x00200000
304 #define RFCR_UHEN 0x00100000
305 #define RFCR_ULM 0x00080000
306
307 #define VRCR_RUDPE 0x00000080
308 #define VRCR_RTCPE 0x00000040
309 #define VRCR_RIPE 0x00000020
310 #define VRCR_IPEN 0x00000010
311 #define VRCR_DUTF 0x00000008
312 #define VRCR_DVTF 0x00000004
313 #define VRCR_VTREN 0x00000002
314 #define VRCR_VTDEN 0x00000001
315
316 #define VTCR_PPCHK 0x00000008
317 #define VTCR_GCHK 0x00000004
318 #define VTCR_VPPTI 0x00000002
319 #define VTCR_VGTI 0x00000001
320
321 #define CR 0x00
322 #define CFG 0x04
323 #define MEAR 0x08
324 #define PTSCR 0x0c
325 #define ISR 0x10
326 #define IMR 0x14
327 #define IER 0x18
328 #define IHR 0x1c
329 #define TXDP 0x20
330 #define TXDP_HI 0x24
331 #define TXCFG 0x28
332 #define GPIOR 0x2c
333 #define RXDP 0x30
334 #define RXDP_HI 0x34
335 #define RXCFG 0x38
336 #define PQCR 0x3c
337 #define WCSR 0x40
338 #define PCR 0x44
339 #define RFCR 0x48
340 #define RFDR 0x4c
341
342 #define SRR 0x58
343
344 #define VRCR 0xbc
345 #define VTCR 0xc0
346 #define VDR 0xc4
347 #define CCSR 0xcc
348
349 #define TBICR 0xe0
350 #define TBISR 0xe4
351 #define TANAR 0xe8
352 #define TANLPAR 0xec
353 #define TANER 0xf0
354 #define TESR 0xf4
355
356 #define TBICR_MR_AN_ENABLE 0x00001000
357 #define TBICR_MR_RESTART_AN 0x00000200
358
359 #define TBISR_MR_LINK_STATUS 0x00000020
360 #define TBISR_MR_AN_COMPLETE 0x00000004
361
362 #define TANAR_PS2 0x00000100
363 #define TANAR_PS1 0x00000080
364 #define TANAR_HALF_DUP 0x00000040
365 #define TANAR_FULL_DUP 0x00000020
366
367 #define GPIOR_GP5_OE 0x00000200
368 #define GPIOR_GP4_OE 0x00000100
369 #define GPIOR_GP3_OE 0x00000080
370 #define GPIOR_GP2_OE 0x00000040
371 #define GPIOR_GP1_OE 0x00000020
372 #define GPIOR_GP3_OUT 0x00000004
373 #define GPIOR_GP1_OUT 0x00000001
374
375 #define LINK_AUTONEGOTIATE 0x01
376 #define LINK_DOWN 0x02
377 #define LINK_UP 0x04
378
379 #define HW_ADDR_LEN sizeof(dma_addr_t)
380 #define desc_addr_set(desc, addr) \
381 do { \
382 ((desc)[0] = cpu_to_le32(addr)); \
383 if (HW_ADDR_LEN == 8) \
384 (desc)[1] = cpu_to_le32(((u64)addr) >> 32); \
385 } while(0)
386 #define desc_addr_get(desc) \
387 (le32_to_cpu((desc)[0]) | \
388 (HW_ADDR_LEN == 8 ? ((dma_addr_t)le32_to_cpu((desc)[1]))<<32 : 0))
389
390 #define DESC_LINK 0
391 #define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4)
392 #define DESC_CMDSTS (DESC_BUFPTR + HW_ADDR_LEN/4)
393 #define DESC_EXTSTS (DESC_CMDSTS + 4/4)
394
395 #define CMDSTS_OWN 0x80000000
396 #define CMDSTS_MORE 0x40000000
397 #define CMDSTS_INTR 0x20000000
398 #define CMDSTS_ERR 0x10000000
399 #define CMDSTS_OK 0x08000000
400 #define CMDSTS_RUNT 0x00200000
401 #define CMDSTS_LEN_MASK 0x0000ffff
402
403 #define CMDSTS_DEST_MASK 0x01800000
404 #define CMDSTS_DEST_SELF 0x00800000
405 #define CMDSTS_DEST_MULTI 0x01000000
406
407 #define DESC_SIZE 8 /* Should be cache line sized */
408
409 struct rx_info {
410 spinlock_t lock;
411 int up;
412 long idle;
413
414 struct sk_buff *skbs[NR_RX_DESC];
415
416 __le32 *next_rx_desc;
417 u16 next_rx, next_empty;
418
419 __le32 *descs;
420 dma_addr_t phy_descs;
421 };
422
423
424 struct ns83820 {
425 struct net_device_stats stats;
426 u8 __iomem *base;
427
428 struct pci_dev *pci_dev;
429 struct net_device *ndev;
430
431 #ifdef NS83820_VLAN_ACCEL_SUPPORT
432 struct vlan_group *vlgrp;
433 #endif
434
435 struct rx_info rx_info;
436 struct tasklet_struct rx_tasklet;
437
438 unsigned ihr;
439 struct work_struct tq_refill;
440
441 /* protects everything below. irqsave when using. */
442 spinlock_t misc_lock;
443
444 u32 CFG_cache;
445
446 u32 MEAR_cache;
447 u32 IMR_cache;
448
449 unsigned linkstate;
450
451 spinlock_t tx_lock;
452
453 u16 tx_done_idx;
454 u16 tx_idx;
455 volatile u16 tx_free_idx; /* idx of free desc chain */
456 u16 tx_intr_idx;
457
458 atomic_t nr_tx_skbs;
459 struct sk_buff *tx_skbs[NR_TX_DESC];
460
461 char pad[16] __attribute__((aligned(16)));
462 __le32 *tx_descs;
463 dma_addr_t tx_phy_descs;
464
465 struct timer_list tx_watchdog;
466 };
467
468 static inline struct ns83820 *PRIV(struct net_device *dev)
469 {
470 return netdev_priv(dev);
471 }
472
473 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
474
475 static inline void kick_rx(struct net_device *ndev)
476 {
477 struct ns83820 *dev = PRIV(ndev);
478 dprintk("kick_rx: maybe kicking\n");
479 if (test_and_clear_bit(0, &dev->rx_info.idle)) {
480 dprintk("actually kicking\n");
481 writel(dev->rx_info.phy_descs +
482 (4 * DESC_SIZE * dev->rx_info.next_rx),
483 dev->base + RXDP);
484 if (dev->rx_info.next_rx == dev->rx_info.next_empty)
485 printk(KERN_DEBUG "%s: uh-oh: next_rx == next_empty???\n",
486 ndev->name);
487 __kick_rx(dev);
488 }
489 }
490
491 //free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC
492 #define start_tx_okay(dev) \
493 (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE)
494
495
496 #ifdef NS83820_VLAN_ACCEL_SUPPORT
497 static void ns83820_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
498 {
499 struct ns83820 *dev = PRIV(ndev);
500
501 spin_lock_irq(&dev->misc_lock);
502 spin_lock(&dev->tx_lock);
503
504 dev->vlgrp = grp;
505
506 spin_unlock(&dev->tx_lock);
507 spin_unlock_irq(&dev->misc_lock);
508 }
509 #endif
510
511 /* Packet Receiver
512 *
513 * The hardware supports linked lists of receive descriptors for
514 * which ownership is transfered back and forth by means of an
515 * ownership bit. While the hardware does support the use of a
516 * ring for receive descriptors, we only make use of a chain in
517 * an attempt to reduce bus traffic under heavy load scenarios.
518 * This will also make bugs a bit more obvious. The current code
519 * only makes use of a single rx chain; I hope to implement
520 * priority based rx for version 1.0. Goal: even under overload
521 * conditions, still route realtime traffic with as low jitter as
522 * possible.
523 */
524 static inline void build_rx_desc(struct ns83820 *dev, __le32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts)
525 {
526 desc_addr_set(desc + DESC_LINK, link);
527 desc_addr_set(desc + DESC_BUFPTR, buf);
528 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
529 mb();
530 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
531 }
532
533 #define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC)
534 static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb)
535 {
536 unsigned next_empty;
537 u32 cmdsts;
538 __le32 *sg;
539 dma_addr_t buf;
540
541 next_empty = dev->rx_info.next_empty;
542
543 /* don't overrun last rx marker */
544 if (unlikely(nr_rx_empty(dev) <= 2)) {
545 kfree_skb(skb);
546 return 1;
547 }
548
549 #if 0
550 dprintk("next_empty[%d] nr_used[%d] next_rx[%d]\n",
551 dev->rx_info.next_empty,
552 dev->rx_info.nr_used,
553 dev->rx_info.next_rx
554 );
555 #endif
556
557 sg = dev->rx_info.descs + (next_empty * DESC_SIZE);
558 BUG_ON(NULL != dev->rx_info.skbs[next_empty]);
559 dev->rx_info.skbs[next_empty] = skb;
560
561 dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC;
562 cmdsts = REAL_RX_BUF_SIZE | CMDSTS_INTR;
563 buf = pci_map_single(dev->pci_dev, skb->data,
564 REAL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
565 build_rx_desc(dev, sg, 0, buf, cmdsts, 0);
566 /* update link of previous rx */
567 if (likely(next_empty != dev->rx_info.next_rx))
568 dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4));
569
570 return 0;
571 }
572
573 static inline int rx_refill(struct net_device *ndev, gfp_t gfp)
574 {
575 struct ns83820 *dev = PRIV(ndev);
576 unsigned i;
577 unsigned long flags = 0;
578
579 if (unlikely(nr_rx_empty(dev) <= 2))
580 return 0;
581
582 dprintk("rx_refill(%p)\n", ndev);
583 if (gfp == GFP_ATOMIC)
584 spin_lock_irqsave(&dev->rx_info.lock, flags);
585 for (i=0; i<NR_RX_DESC; i++) {
586 struct sk_buff *skb;
587 long res;
588 /* extra 16 bytes for alignment */
589 skb = __dev_alloc_skb(REAL_RX_BUF_SIZE+16, gfp);
590 if (unlikely(!skb))
591 break;
592
593 res = (long)skb->data & 0xf;
594 res = 0x10 - res;
595 res &= 0xf;
596 skb_reserve(skb, res);
597
598 if (gfp != GFP_ATOMIC)
599 spin_lock_irqsave(&dev->rx_info.lock, flags);
600 res = ns83820_add_rx_skb(dev, skb);
601 if (gfp != GFP_ATOMIC)
602 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
603 if (res) {
604 i = 1;
605 break;
606 }
607 }
608 if (gfp == GFP_ATOMIC)
609 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
610
611 return i ? 0 : -ENOMEM;
612 }
613
614 static void rx_refill_atomic(struct net_device *ndev);
615 static void fastcall rx_refill_atomic(struct net_device *ndev)
616 {
617 rx_refill(ndev, GFP_ATOMIC);
618 }
619
620 /* REFILL */
621 static inline void queue_refill(struct work_struct *work)
622 {
623 struct ns83820 *dev = container_of(work, struct ns83820, tq_refill);
624 struct net_device *ndev = dev->ndev;
625
626 rx_refill(ndev, GFP_KERNEL);
627 if (dev->rx_info.up)
628 kick_rx(ndev);
629 }
630
631 static inline void clear_rx_desc(struct ns83820 *dev, unsigned i)
632 {
633 build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0);
634 }
635
636 static void fastcall phy_intr(struct net_device *ndev)
637 {
638 struct ns83820 *dev = PRIV(ndev);
639 static const char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" };
640 u32 cfg, new_cfg;
641 u32 tbisr, tanar, tanlpar;
642 int speed, fullduplex, newlinkstate;
643
644 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
645
646 if (dev->CFG_cache & CFG_TBI_EN) {
647 /* we have an optical transceiver */
648 tbisr = readl(dev->base + TBISR);
649 tanar = readl(dev->base + TANAR);
650 tanlpar = readl(dev->base + TANLPAR);
651 dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n",
652 tbisr, tanar, tanlpar);
653
654 if ( (fullduplex = (tanlpar & TANAR_FULL_DUP)
655 && (tanar & TANAR_FULL_DUP)) ) {
656
657 /* both of us are full duplex */
658 writel(readl(dev->base + TXCFG)
659 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
660 dev->base + TXCFG);
661 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
662 dev->base + RXCFG);
663 /* Light up full duplex LED */
664 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
665 dev->base + GPIOR);
666
667 } else if(((tanlpar & TANAR_HALF_DUP)
668 && (tanar & TANAR_HALF_DUP))
669 || ((tanlpar & TANAR_FULL_DUP)
670 && (tanar & TANAR_HALF_DUP))
671 || ((tanlpar & TANAR_HALF_DUP)
672 && (tanar & TANAR_FULL_DUP))) {
673
674 /* one or both of us are half duplex */
675 writel((readl(dev->base + TXCFG)
676 & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP,
677 dev->base + TXCFG);
678 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD,
679 dev->base + RXCFG);
680 /* Turn off full duplex LED */
681 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT,
682 dev->base + GPIOR);
683 }
684
685 speed = 4; /* 1000F */
686
687 } else {
688 /* we have a copper transceiver */
689 new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS);
690
691 if (cfg & CFG_SPDSTS1)
692 new_cfg |= CFG_MODE_1000;
693 else
694 new_cfg &= ~CFG_MODE_1000;
695
696 speed = ((cfg / CFG_SPDSTS0) & 3);
697 fullduplex = (cfg & CFG_DUPSTS);
698
699 if (fullduplex) {
700 new_cfg |= CFG_SB;
701 writel(readl(dev->base + TXCFG)
702 | TXCFG_CSI | TXCFG_HBI,
703 dev->base + TXCFG);
704 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
705 dev->base + RXCFG);
706 } else {
707 writel(readl(dev->base + TXCFG)
708 & ~(TXCFG_CSI | TXCFG_HBI),
709 dev->base + TXCFG);
710 writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD),
711 dev->base + RXCFG);
712 }
713
714 if ((cfg & CFG_LNKSTS) &&
715 ((new_cfg ^ dev->CFG_cache) != 0)) {
716 writel(new_cfg, dev->base + CFG);
717 dev->CFG_cache = new_cfg;
718 }
719
720 dev->CFG_cache &= ~CFG_SPDSTS;
721 dev->CFG_cache |= cfg & CFG_SPDSTS;
722 }
723
724 newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN;
725
726 if (newlinkstate & LINK_UP
727 && dev->linkstate != newlinkstate) {
728 netif_start_queue(ndev);
729 netif_wake_queue(ndev);
730 printk(KERN_INFO "%s: link now %s mbps, %s duplex and up.\n",
731 ndev->name,
732 speeds[speed],
733 fullduplex ? "full" : "half");
734 } else if (newlinkstate & LINK_DOWN
735 && dev->linkstate != newlinkstate) {
736 netif_stop_queue(ndev);
737 printk(KERN_INFO "%s: link now down.\n", ndev->name);
738 }
739
740 dev->linkstate = newlinkstate;
741 }
742
743 static int ns83820_setup_rx(struct net_device *ndev)
744 {
745 struct ns83820 *dev = PRIV(ndev);
746 unsigned i;
747 int ret;
748
749 dprintk("ns83820_setup_rx(%p)\n", ndev);
750
751 dev->rx_info.idle = 1;
752 dev->rx_info.next_rx = 0;
753 dev->rx_info.next_rx_desc = dev->rx_info.descs;
754 dev->rx_info.next_empty = 0;
755
756 for (i=0; i<NR_RX_DESC; i++)
757 clear_rx_desc(dev, i);
758
759 writel(0, dev->base + RXDP_HI);
760 writel(dev->rx_info.phy_descs, dev->base + RXDP);
761
762 ret = rx_refill(ndev, GFP_KERNEL);
763 if (!ret) {
764 dprintk("starting receiver\n");
765 /* prevent the interrupt handler from stomping on us */
766 spin_lock_irq(&dev->rx_info.lock);
767
768 writel(0x0001, dev->base + CCSR);
769 writel(0, dev->base + RFCR);
770 writel(0x7fc00000, dev->base + RFCR);
771 writel(0xffc00000, dev->base + RFCR);
772
773 dev->rx_info.up = 1;
774
775 phy_intr(ndev);
776
777 /* Okay, let it rip */
778 spin_lock_irq(&dev->misc_lock);
779 dev->IMR_cache |= ISR_PHY;
780 dev->IMR_cache |= ISR_RXRCMP;
781 //dev->IMR_cache |= ISR_RXERR;
782 //dev->IMR_cache |= ISR_RXOK;
783 dev->IMR_cache |= ISR_RXORN;
784 dev->IMR_cache |= ISR_RXSOVR;
785 dev->IMR_cache |= ISR_RXDESC;
786 dev->IMR_cache |= ISR_RXIDLE;
787 dev->IMR_cache |= ISR_TXDESC;
788 dev->IMR_cache |= ISR_TXIDLE;
789
790 writel(dev->IMR_cache, dev->base + IMR);
791 writel(1, dev->base + IER);
792 spin_unlock(&dev->misc_lock);
793
794 kick_rx(ndev);
795
796 spin_unlock_irq(&dev->rx_info.lock);
797 }
798 return ret;
799 }
800
801 static void ns83820_cleanup_rx(struct ns83820 *dev)
802 {
803 unsigned i;
804 unsigned long flags;
805
806 dprintk("ns83820_cleanup_rx(%p)\n", dev);
807
808 /* disable receive interrupts */
809 spin_lock_irqsave(&dev->misc_lock, flags);
810 dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE);
811 writel(dev->IMR_cache, dev->base + IMR);
812 spin_unlock_irqrestore(&dev->misc_lock, flags);
813
814 /* synchronize with the interrupt handler and kill it */
815 dev->rx_info.up = 0;
816 synchronize_irq(dev->pci_dev->irq);
817
818 /* touch the pci bus... */
819 readl(dev->base + IMR);
820
821 /* assumes the transmitter is already disabled and reset */
822 writel(0, dev->base + RXDP_HI);
823 writel(0, dev->base + RXDP);
824
825 for (i=0; i<NR_RX_DESC; i++) {
826 struct sk_buff *skb = dev->rx_info.skbs[i];
827 dev->rx_info.skbs[i] = NULL;
828 clear_rx_desc(dev, i);
829 if (skb)
830 kfree_skb(skb);
831 }
832 }
833
834 static void fastcall ns83820_rx_kick(struct net_device *ndev)
835 {
836 struct ns83820 *dev = PRIV(ndev);
837 /*if (nr_rx_empty(dev) >= NR_RX_DESC/4)*/ {
838 if (dev->rx_info.up) {
839 rx_refill_atomic(ndev);
840 kick_rx(ndev);
841 }
842 }
843
844 if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4)
845 schedule_work(&dev->tq_refill);
846 else
847 kick_rx(ndev);
848 if (dev->rx_info.idle)
849 printk(KERN_DEBUG "%s: BAD\n", ndev->name);
850 }
851
852 /* rx_irq
853 *
854 */
855 static void fastcall rx_irq(struct net_device *ndev)
856 {
857 struct ns83820 *dev = PRIV(ndev);
858 struct rx_info *info = &dev->rx_info;
859 unsigned next_rx;
860 int rx_rc, len;
861 u32 cmdsts;
862 __le32 *desc;
863 unsigned long flags;
864 int nr = 0;
865
866 dprintk("rx_irq(%p)\n", ndev);
867 dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n",
868 readl(dev->base + RXDP),
869 (long)(dev->rx_info.phy_descs),
870 (int)dev->rx_info.next_rx,
871 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
872 (int)dev->rx_info.next_empty,
873 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
874 );
875
876 spin_lock_irqsave(&info->lock, flags);
877 if (!info->up)
878 goto out;
879
880 dprintk("walking descs\n");
881 next_rx = info->next_rx;
882 desc = info->next_rx_desc;
883 while ((CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) &&
884 (cmdsts != CMDSTS_OWN)) {
885 struct sk_buff *skb;
886 u32 extsts = le32_to_cpu(desc[DESC_EXTSTS]);
887 dma_addr_t bufptr = desc_addr_get(desc + DESC_BUFPTR);
888
889 dprintk("cmdsts: %08x\n", cmdsts);
890 dprintk("link: %08x\n", cpu_to_le32(desc[DESC_LINK]));
891 dprintk("extsts: %08x\n", extsts);
892
893 skb = info->skbs[next_rx];
894 info->skbs[next_rx] = NULL;
895 info->next_rx = (next_rx + 1) % NR_RX_DESC;
896
897 mb();
898 clear_rx_desc(dev, next_rx);
899
900 pci_unmap_single(dev->pci_dev, bufptr,
901 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
902 len = cmdsts & CMDSTS_LEN_MASK;
903 #ifdef NS83820_VLAN_ACCEL_SUPPORT
904 /* NH: As was mentioned below, this chip is kinda
905 * brain dead about vlan tag stripping. Frames
906 * that are 64 bytes with a vlan header appended
907 * like arp frames, or pings, are flagged as Runts
908 * when the tag is stripped and hardware. This
909 * also means that the OK bit in the descriptor
910 * is cleared when the frame comes in so we have
911 * to do a specific length check here to make sure
912 * the frame would have been ok, had we not stripped
913 * the tag.
914 */
915 if (likely((CMDSTS_OK & cmdsts) ||
916 ((cmdsts & CMDSTS_RUNT) && len >= 56))) {
917 #else
918 if (likely(CMDSTS_OK & cmdsts)) {
919 #endif
920 skb_put(skb, len);
921 if (unlikely(!skb))
922 goto netdev_mangle_me_harder_failed;
923 if (cmdsts & CMDSTS_DEST_MULTI)
924 dev->stats.multicast ++;
925 dev->stats.rx_packets ++;
926 dev->stats.rx_bytes += len;
927 if ((extsts & 0x002a0000) && !(extsts & 0x00540000)) {
928 skb->ip_summed = CHECKSUM_UNNECESSARY;
929 } else {
930 skb->ip_summed = CHECKSUM_NONE;
931 }
932 skb->protocol = eth_type_trans(skb, ndev);
933 #ifdef NS83820_VLAN_ACCEL_SUPPORT
934 if(extsts & EXTSTS_VPKT) {
935 unsigned short tag;
936 tag = ntohs(extsts & EXTSTS_VTG_MASK);
937 rx_rc = vlan_hwaccel_rx(skb,dev->vlgrp,tag);
938 } else {
939 rx_rc = netif_rx(skb);
940 }
941 #else
942 rx_rc = netif_rx(skb);
943 #endif
944 if (NET_RX_DROP == rx_rc) {
945 netdev_mangle_me_harder_failed:
946 dev->stats.rx_dropped ++;
947 }
948 } else {
949 kfree_skb(skb);
950 }
951
952 nr++;
953 next_rx = info->next_rx;
954 desc = info->descs + (DESC_SIZE * next_rx);
955 }
956 info->next_rx = next_rx;
957 info->next_rx_desc = info->descs + (DESC_SIZE * next_rx);
958
959 out:
960 if (0 && !nr) {
961 Dprintk("dazed: cmdsts_f: %08x\n", cmdsts);
962 }
963
964 spin_unlock_irqrestore(&info->lock, flags);
965 }
966
967 static void rx_action(unsigned long _dev)
968 {
969 struct net_device *ndev = (void *)_dev;
970 struct ns83820 *dev = PRIV(ndev);
971 rx_irq(ndev);
972 writel(ihr, dev->base + IHR);
973
974 spin_lock_irq(&dev->misc_lock);
975 dev->IMR_cache |= ISR_RXDESC;
976 writel(dev->IMR_cache, dev->base + IMR);
977 spin_unlock_irq(&dev->misc_lock);
978
979 rx_irq(ndev);
980 ns83820_rx_kick(ndev);
981 }
982
983 /* Packet Transmit code
984 */
985 static inline void kick_tx(struct ns83820 *dev)
986 {
987 dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n",
988 dev, dev->tx_idx, dev->tx_free_idx);
989 writel(CR_TXE, dev->base + CR);
990 }
991
992 /* No spinlock needed on the transmit irq path as the interrupt handler is
993 * serialized.
994 */
995 static void do_tx_done(struct net_device *ndev)
996 {
997 struct ns83820 *dev = PRIV(ndev);
998 u32 cmdsts, tx_done_idx;
999 __le32 *desc;
1000
1001 dprintk("do_tx_done(%p)\n", ndev);
1002 tx_done_idx = dev->tx_done_idx;
1003 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1004
1005 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1006 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1007 while ((tx_done_idx != dev->tx_free_idx) &&
1008 !(CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) ) {
1009 struct sk_buff *skb;
1010 unsigned len;
1011 dma_addr_t addr;
1012
1013 if (cmdsts & CMDSTS_ERR)
1014 dev->stats.tx_errors ++;
1015 if (cmdsts & CMDSTS_OK)
1016 dev->stats.tx_packets ++;
1017 if (cmdsts & CMDSTS_OK)
1018 dev->stats.tx_bytes += cmdsts & 0xffff;
1019
1020 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1021 tx_done_idx, dev->tx_free_idx, cmdsts);
1022 skb = dev->tx_skbs[tx_done_idx];
1023 dev->tx_skbs[tx_done_idx] = NULL;
1024 dprintk("done(%p)\n", skb);
1025
1026 len = cmdsts & CMDSTS_LEN_MASK;
1027 addr = desc_addr_get(desc + DESC_BUFPTR);
1028 if (skb) {
1029 pci_unmap_single(dev->pci_dev,
1030 addr,
1031 len,
1032 PCI_DMA_TODEVICE);
1033 dev_kfree_skb_irq(skb);
1034 atomic_dec(&dev->nr_tx_skbs);
1035 } else
1036 pci_unmap_page(dev->pci_dev,
1037 addr,
1038 len,
1039 PCI_DMA_TODEVICE);
1040
1041 tx_done_idx = (tx_done_idx + 1) % NR_TX_DESC;
1042 dev->tx_done_idx = tx_done_idx;
1043 desc[DESC_CMDSTS] = cpu_to_le32(0);
1044 mb();
1045 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1046 }
1047
1048 /* Allow network stack to resume queueing packets after we've
1049 * finished transmitting at least 1/4 of the packets in the queue.
1050 */
1051 if (netif_queue_stopped(ndev) && start_tx_okay(dev)) {
1052 dprintk("start_queue(%p)\n", ndev);
1053 netif_start_queue(ndev);
1054 netif_wake_queue(ndev);
1055 }
1056 }
1057
1058 static void ns83820_cleanup_tx(struct ns83820 *dev)
1059 {
1060 unsigned i;
1061
1062 for (i=0; i<NR_TX_DESC; i++) {
1063 struct sk_buff *skb = dev->tx_skbs[i];
1064 dev->tx_skbs[i] = NULL;
1065 if (skb) {
1066 __le32 *desc = dev->tx_descs + (i * DESC_SIZE);
1067 pci_unmap_single(dev->pci_dev,
1068 desc_addr_get(desc + DESC_BUFPTR),
1069 le32_to_cpu(desc[DESC_CMDSTS]) & CMDSTS_LEN_MASK,
1070 PCI_DMA_TODEVICE);
1071 dev_kfree_skb_irq(skb);
1072 atomic_dec(&dev->nr_tx_skbs);
1073 }
1074 }
1075
1076 memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4);
1077 }
1078
1079 /* transmit routine. This code relies on the network layer serializing
1080 * its calls in, but will run happily in parallel with the interrupt
1081 * handler. This code currently has provisions for fragmenting tx buffers
1082 * while trying to track down a bug in either the zero copy code or
1083 * the tx fifo (hence the MAX_FRAG_LEN).
1084 */
1085 static int ns83820_hard_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1086 {
1087 struct ns83820 *dev = PRIV(ndev);
1088 u32 free_idx, cmdsts, extsts;
1089 int nr_free, nr_frags;
1090 unsigned tx_done_idx, last_idx;
1091 dma_addr_t buf;
1092 unsigned len;
1093 skb_frag_t *frag;
1094 int stopped = 0;
1095 int do_intr = 0;
1096 volatile __le32 *first_desc;
1097
1098 dprintk("ns83820_hard_start_xmit\n");
1099
1100 nr_frags = skb_shinfo(skb)->nr_frags;
1101 again:
1102 if (unlikely(dev->CFG_cache & CFG_LNKSTS)) {
1103 netif_stop_queue(ndev);
1104 if (unlikely(dev->CFG_cache & CFG_LNKSTS))
1105 return 1;
1106 netif_start_queue(ndev);
1107 }
1108
1109 last_idx = free_idx = dev->tx_free_idx;
1110 tx_done_idx = dev->tx_done_idx;
1111 nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC;
1112 nr_free -= 1;
1113 if (nr_free <= nr_frags) {
1114 dprintk("stop_queue - not enough(%p)\n", ndev);
1115 netif_stop_queue(ndev);
1116
1117 /* Check again: we may have raced with a tx done irq */
1118 if (dev->tx_done_idx != tx_done_idx) {
1119 dprintk("restart queue(%p)\n", ndev);
1120 netif_start_queue(ndev);
1121 goto again;
1122 }
1123 return 1;
1124 }
1125
1126 if (free_idx == dev->tx_intr_idx) {
1127 do_intr = 1;
1128 dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC;
1129 }
1130
1131 nr_free -= nr_frags;
1132 if (nr_free < MIN_TX_DESC_FREE) {
1133 dprintk("stop_queue - last entry(%p)\n", ndev);
1134 netif_stop_queue(ndev);
1135 stopped = 1;
1136 }
1137
1138 frag = skb_shinfo(skb)->frags;
1139 if (!nr_frags)
1140 frag = NULL;
1141 extsts = 0;
1142 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1143 extsts |= EXTSTS_IPPKT;
1144 if (IPPROTO_TCP == ip_hdr(skb)->protocol)
1145 extsts |= EXTSTS_TCPPKT;
1146 else if (IPPROTO_UDP == ip_hdr(skb)->protocol)
1147 extsts |= EXTSTS_UDPPKT;
1148 }
1149
1150 #ifdef NS83820_VLAN_ACCEL_SUPPORT
1151 if(vlan_tx_tag_present(skb)) {
1152 /* fetch the vlan tag info out of the
1153 * ancilliary data if the vlan code
1154 * is using hw vlan acceleration
1155 */
1156 short tag = vlan_tx_tag_get(skb);
1157 extsts |= (EXTSTS_VPKT | htons(tag));
1158 }
1159 #endif
1160
1161 len = skb->len;
1162 if (nr_frags)
1163 len -= skb->data_len;
1164 buf = pci_map_single(dev->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1165
1166 first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
1167
1168 for (;;) {
1169 volatile __le32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
1170
1171 dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len,
1172 (unsigned long long)buf);
1173 last_idx = free_idx;
1174 free_idx = (free_idx + 1) % NR_TX_DESC;
1175 desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4));
1176 desc_addr_set(desc + DESC_BUFPTR, buf);
1177 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
1178
1179 cmdsts = ((nr_frags) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0);
1180 cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN;
1181 cmdsts |= len;
1182 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
1183
1184 if (!nr_frags)
1185 break;
1186
1187 buf = pci_map_page(dev->pci_dev, frag->page,
1188 frag->page_offset,
1189 frag->size, PCI_DMA_TODEVICE);
1190 dprintk("frag: buf=%08Lx page=%08lx offset=%08lx\n",
1191 (long long)buf, (long) page_to_pfn(frag->page),
1192 frag->page_offset);
1193 len = frag->size;
1194 frag++;
1195 nr_frags--;
1196 }
1197 dprintk("done pkt\n");
1198
1199 spin_lock_irq(&dev->tx_lock);
1200 dev->tx_skbs[last_idx] = skb;
1201 first_desc[DESC_CMDSTS] |= cpu_to_le32(CMDSTS_OWN);
1202 dev->tx_free_idx = free_idx;
1203 atomic_inc(&dev->nr_tx_skbs);
1204 spin_unlock_irq(&dev->tx_lock);
1205
1206 kick_tx(dev);
1207
1208 /* Check again: we may have raced with a tx done irq */
1209 if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev))
1210 netif_start_queue(ndev);
1211
1212 /* set the transmit start time to catch transmit timeouts */
1213 ndev->trans_start = jiffies;
1214 return 0;
1215 }
1216
1217 static void ns83820_update_stats(struct ns83820 *dev)
1218 {
1219 u8 __iomem *base = dev->base;
1220
1221 /* the DP83820 will freeze counters, so we need to read all of them */
1222 dev->stats.rx_errors += readl(base + 0x60) & 0xffff;
1223 dev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff;
1224 dev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff;
1225 dev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff;
1226 /*dev->stats.rx_symbol_errors +=*/ readl(base + 0x70);
1227 dev->stats.rx_length_errors += readl(base + 0x74) & 0xffff;
1228 dev->stats.rx_length_errors += readl(base + 0x78) & 0xffff;
1229 /*dev->stats.rx_badopcode_errors += */ readl(base + 0x7c);
1230 /*dev->stats.rx_pause_count += */ readl(base + 0x80);
1231 /*dev->stats.tx_pause_count += */ readl(base + 0x84);
1232 dev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff;
1233 }
1234
1235 static struct net_device_stats *ns83820_get_stats(struct net_device *ndev)
1236 {
1237 struct ns83820 *dev = PRIV(ndev);
1238
1239 /* somewhat overkill */
1240 spin_lock_irq(&dev->misc_lock);
1241 ns83820_update_stats(dev);
1242 spin_unlock_irq(&dev->misc_lock);
1243
1244 return &dev->stats;
1245 }
1246
1247 /* Let ethtool retrieve info */
1248 static int ns83820_get_settings(struct net_device *ndev,
1249 struct ethtool_cmd *cmd)
1250 {
1251 struct ns83820 *dev = PRIV(ndev);
1252 u32 cfg, tanar, tbicr;
1253 int have_optical = 0;
1254 int fullduplex = 0;
1255
1256 /*
1257 * Here's the list of available ethtool commands from other drivers:
1258 * cmd->advertising =
1259 * cmd->speed =
1260 * cmd->duplex =
1261 * cmd->port = 0;
1262 * cmd->phy_address =
1263 * cmd->transceiver = 0;
1264 * cmd->autoneg =
1265 * cmd->maxtxpkt = 0;
1266 * cmd->maxrxpkt = 0;
1267 */
1268
1269 /* read current configuration */
1270 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1271 tanar = readl(dev->base + TANAR);
1272 tbicr = readl(dev->base + TBICR);
1273
1274 if (dev->CFG_cache & CFG_TBI_EN) {
1275 /* we have an optical interface */
1276 have_optical = 1;
1277 fullduplex = (cfg & CFG_DUPSTS) ? 1 : 0;
1278
1279 } else {
1280 /* We have copper */
1281 fullduplex = (cfg & CFG_DUPSTS) ? 1 : 0;
1282 }
1283
1284 cmd->supported = SUPPORTED_Autoneg;
1285
1286 /* we have optical interface */
1287 if (dev->CFG_cache & CFG_TBI_EN) {
1288 cmd->supported |= SUPPORTED_1000baseT_Half |
1289 SUPPORTED_1000baseT_Full |
1290 SUPPORTED_FIBRE;
1291 cmd->port = PORT_FIBRE;
1292 } /* TODO: else copper related support */
1293
1294 cmd->duplex = fullduplex ? DUPLEX_FULL : DUPLEX_HALF;
1295 switch (cfg / CFG_SPDSTS0 & 3) {
1296 case 2:
1297 cmd->speed = SPEED_1000;
1298 break;
1299 case 1:
1300 cmd->speed = SPEED_100;
1301 break;
1302 default:
1303 cmd->speed = SPEED_10;
1304 break;
1305 }
1306 cmd->autoneg = (tbicr & TBICR_MR_AN_ENABLE) ? 1: 0;
1307 return 0;
1308 }
1309
1310 /* Let ethool change settings*/
1311 static int ns83820_set_settings(struct net_device *ndev,
1312 struct ethtool_cmd *cmd)
1313 {
1314 struct ns83820 *dev = PRIV(ndev);
1315 u32 cfg, tanar;
1316 int have_optical = 0;
1317 int fullduplex = 0;
1318
1319 /* read current configuration */
1320 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1321 tanar = readl(dev->base + TANAR);
1322
1323 if (dev->CFG_cache & CFG_TBI_EN) {
1324 /* we have optical */
1325 have_optical = 1;
1326 fullduplex = (tanar & TANAR_FULL_DUP);
1327
1328 } else {
1329 /* we have copper */
1330 fullduplex = cfg & CFG_DUPSTS;
1331 }
1332
1333 spin_lock_irq(&dev->misc_lock);
1334 spin_lock(&dev->tx_lock);
1335
1336 /* Set duplex */
1337 if (cmd->duplex != fullduplex) {
1338 if (have_optical) {
1339 /*set full duplex*/
1340 if (cmd->duplex == DUPLEX_FULL) {
1341 /* force full duplex */
1342 writel(readl(dev->base + TXCFG)
1343 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
1344 dev->base + TXCFG);
1345 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
1346 dev->base + RXCFG);
1347 /* Light up full duplex LED */
1348 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
1349 dev->base + GPIOR);
1350 } else {
1351 /*TODO: set half duplex */
1352 }
1353
1354 } else {
1355 /*we have copper*/
1356 /* TODO: Set duplex for copper cards */
1357 }
1358 printk(KERN_INFO "%s: Duplex set via ethtool\n",
1359 ndev->name);
1360 }
1361
1362 /* Set autonegotiation */
1363 if (1) {
1364 if (cmd->autoneg == AUTONEG_ENABLE) {
1365 /* restart auto negotiation */
1366 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
1367 dev->base + TBICR);
1368 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
1369 dev->linkstate = LINK_AUTONEGOTIATE;
1370
1371 printk(KERN_INFO "%s: autoneg enabled via ethtool\n",
1372 ndev->name);
1373 } else {
1374 /* disable auto negotiation */
1375 writel(0x00000000, dev->base + TBICR);
1376 }
1377
1378 printk(KERN_INFO "%s: autoneg %s via ethtool\n", ndev->name,
1379 cmd->autoneg ? "ENABLED" : "DISABLED");
1380 }
1381
1382 phy_intr(ndev);
1383 spin_unlock(&dev->tx_lock);
1384 spin_unlock_irq(&dev->misc_lock);
1385
1386 return 0;
1387 }
1388 /* end ethtool get/set support -df */
1389
1390 static void ns83820_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info)
1391 {
1392 struct ns83820 *dev = PRIV(ndev);
1393 strcpy(info->driver, "ns83820");
1394 strcpy(info->version, VERSION);
1395 strcpy(info->bus_info, pci_name(dev->pci_dev));
1396 }
1397
1398 static u32 ns83820_get_link(struct net_device *ndev)
1399 {
1400 struct ns83820 *dev = PRIV(ndev);
1401 u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1402 return cfg & CFG_LNKSTS ? 1 : 0;
1403 }
1404
1405 static const struct ethtool_ops ops = {
1406 .get_settings = ns83820_get_settings,
1407 .set_settings = ns83820_set_settings,
1408 .get_drvinfo = ns83820_get_drvinfo,
1409 .get_link = ns83820_get_link
1410 };
1411
1412 /* this function is called in irq context from the ISR */
1413 static void ns83820_mib_isr(struct ns83820 *dev)
1414 {
1415 unsigned long flags;
1416 spin_lock_irqsave(&dev->misc_lock, flags);
1417 ns83820_update_stats(dev);
1418 spin_unlock_irqrestore(&dev->misc_lock, flags);
1419 }
1420
1421 static void ns83820_do_isr(struct net_device *ndev, u32 isr);
1422 static irqreturn_t ns83820_irq(int foo, void *data)
1423 {
1424 struct net_device *ndev = data;
1425 struct ns83820 *dev = PRIV(ndev);
1426 u32 isr;
1427 dprintk("ns83820_irq(%p)\n", ndev);
1428
1429 dev->ihr = 0;
1430
1431 isr = readl(dev->base + ISR);
1432 dprintk("irq: %08x\n", isr);
1433 ns83820_do_isr(ndev, isr);
1434 return IRQ_HANDLED;
1435 }
1436
1437 static void ns83820_do_isr(struct net_device *ndev, u32 isr)
1438 {
1439 struct ns83820 *dev = PRIV(ndev);
1440 unsigned long flags;
1441
1442 #ifdef DEBUG
1443 if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC))
1444 Dprintk("odd isr? 0x%08x\n", isr);
1445 #endif
1446
1447 if (ISR_RXIDLE & isr) {
1448 dev->rx_info.idle = 1;
1449 Dprintk("oh dear, we are idle\n");
1450 ns83820_rx_kick(ndev);
1451 }
1452
1453 if ((ISR_RXDESC | ISR_RXOK) & isr) {
1454 prefetch(dev->rx_info.next_rx_desc);
1455
1456 spin_lock_irqsave(&dev->misc_lock, flags);
1457 dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK);
1458 writel(dev->IMR_cache, dev->base + IMR);
1459 spin_unlock_irqrestore(&dev->misc_lock, flags);
1460
1461 tasklet_schedule(&dev->rx_tasklet);
1462 //rx_irq(ndev);
1463 //writel(4, dev->base + IHR);
1464 }
1465
1466 if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr)
1467 ns83820_rx_kick(ndev);
1468
1469 if (unlikely(ISR_RXSOVR & isr)) {
1470 //printk("overrun: rxsovr\n");
1471 dev->stats.rx_fifo_errors ++;
1472 }
1473
1474 if (unlikely(ISR_RXORN & isr)) {
1475 //printk("overrun: rxorn\n");
1476 dev->stats.rx_fifo_errors ++;
1477 }
1478
1479 if ((ISR_RXRCMP & isr) && dev->rx_info.up)
1480 writel(CR_RXE, dev->base + CR);
1481
1482 if (ISR_TXIDLE & isr) {
1483 u32 txdp;
1484 txdp = readl(dev->base + TXDP);
1485 dprintk("txdp: %08x\n", txdp);
1486 txdp -= dev->tx_phy_descs;
1487 dev->tx_idx = txdp / (DESC_SIZE * 4);
1488 if (dev->tx_idx >= NR_TX_DESC) {
1489 printk(KERN_ALERT "%s: BUG -- txdp out of range\n", ndev->name);
1490 dev->tx_idx = 0;
1491 }
1492 /* The may have been a race between a pci originated read
1493 * and the descriptor update from the cpu. Just in case,
1494 * kick the transmitter if the hardware thinks it is on a
1495 * different descriptor than we are.
1496 */
1497 if (dev->tx_idx != dev->tx_free_idx)
1498 kick_tx(dev);
1499 }
1500
1501 /* Defer tx ring processing until more than a minimum amount of
1502 * work has accumulated
1503 */
1504 if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) {
1505 spin_lock_irqsave(&dev->tx_lock, flags);
1506 do_tx_done(ndev);
1507 spin_unlock_irqrestore(&dev->tx_lock, flags);
1508
1509 /* Disable TxOk if there are no outstanding tx packets.
1510 */
1511 if ((dev->tx_done_idx == dev->tx_free_idx) &&
1512 (dev->IMR_cache & ISR_TXOK)) {
1513 spin_lock_irqsave(&dev->misc_lock, flags);
1514 dev->IMR_cache &= ~ISR_TXOK;
1515 writel(dev->IMR_cache, dev->base + IMR);
1516 spin_unlock_irqrestore(&dev->misc_lock, flags);
1517 }
1518 }
1519
1520 /* The TxIdle interrupt can come in before the transmit has
1521 * completed. Normally we reap packets off of the combination
1522 * of TxDesc and TxIdle and leave TxOk disabled (since it
1523 * occurs on every packet), but when no further irqs of this
1524 * nature are expected, we must enable TxOk.
1525 */
1526 if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) {
1527 spin_lock_irqsave(&dev->misc_lock, flags);
1528 dev->IMR_cache |= ISR_TXOK;
1529 writel(dev->IMR_cache, dev->base + IMR);
1530 spin_unlock_irqrestore(&dev->misc_lock, flags);
1531 }
1532
1533 /* MIB interrupt: one of the statistics counters is about to overflow */
1534 if (unlikely(ISR_MIB & isr))
1535 ns83820_mib_isr(dev);
1536
1537 /* PHY: Link up/down/negotiation state change */
1538 if (unlikely(ISR_PHY & isr))
1539 phy_intr(ndev);
1540
1541 #if 0 /* Still working on the interrupt mitigation strategy */
1542 if (dev->ihr)
1543 writel(dev->ihr, dev->base + IHR);
1544 #endif
1545 }
1546
1547 static void ns83820_do_reset(struct ns83820 *dev, u32 which)
1548 {
1549 Dprintk("resetting chip...\n");
1550 writel(which, dev->base + CR);
1551 do {
1552 schedule();
1553 } while (readl(dev->base + CR) & which);
1554 Dprintk("okay!\n");
1555 }
1556
1557 static int ns83820_stop(struct net_device *ndev)
1558 {
1559 struct ns83820 *dev = PRIV(ndev);
1560
1561 /* FIXME: protect against interrupt handler? */
1562 del_timer_sync(&dev->tx_watchdog);
1563
1564 /* disable interrupts */
1565 writel(0, dev->base + IMR);
1566 writel(0, dev->base + IER);
1567 readl(dev->base + IER);
1568
1569 dev->rx_info.up = 0;
1570 synchronize_irq(dev->pci_dev->irq);
1571
1572 ns83820_do_reset(dev, CR_RST);
1573
1574 synchronize_irq(dev->pci_dev->irq);
1575
1576 spin_lock_irq(&dev->misc_lock);
1577 dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK);
1578 spin_unlock_irq(&dev->misc_lock);
1579
1580 ns83820_cleanup_rx(dev);
1581 ns83820_cleanup_tx(dev);
1582
1583 return 0;
1584 }
1585
1586 static void ns83820_tx_timeout(struct net_device *ndev)
1587 {
1588 struct ns83820 *dev = PRIV(ndev);
1589 u32 tx_done_idx;
1590 __le32 *desc;
1591 unsigned long flags;
1592
1593 spin_lock_irqsave(&dev->tx_lock, flags);
1594
1595 tx_done_idx = dev->tx_done_idx;
1596 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1597
1598 printk(KERN_INFO "%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1599 ndev->name,
1600 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1601
1602 #if defined(DEBUG)
1603 {
1604 u32 isr;
1605 isr = readl(dev->base + ISR);
1606 printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache);
1607 ns83820_do_isr(ndev, isr);
1608 }
1609 #endif
1610
1611 do_tx_done(ndev);
1612
1613 tx_done_idx = dev->tx_done_idx;
1614 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1615
1616 printk(KERN_INFO "%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1617 ndev->name,
1618 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1619
1620 spin_unlock_irqrestore(&dev->tx_lock, flags);
1621 }
1622
1623 static void ns83820_tx_watch(unsigned long data)
1624 {
1625 struct net_device *ndev = (void *)data;
1626 struct ns83820 *dev = PRIV(ndev);
1627
1628 #if defined(DEBUG)
1629 printk("ns83820_tx_watch: %u %u %d\n",
1630 dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs)
1631 );
1632 #endif
1633
1634 if (time_after(jiffies, ndev->trans_start + 1*HZ) &&
1635 dev->tx_done_idx != dev->tx_free_idx) {
1636 printk(KERN_DEBUG "%s: ns83820_tx_watch: %u %u %d\n",
1637 ndev->name,
1638 dev->tx_done_idx, dev->tx_free_idx,
1639 atomic_read(&dev->nr_tx_skbs));
1640 ns83820_tx_timeout(ndev);
1641 }
1642
1643 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1644 }
1645
1646 static int ns83820_open(struct net_device *ndev)
1647 {
1648 struct ns83820 *dev = PRIV(ndev);
1649 unsigned i;
1650 u32 desc;
1651 int ret;
1652
1653 dprintk("ns83820_open\n");
1654
1655 writel(0, dev->base + PQCR);
1656
1657 ret = ns83820_setup_rx(ndev);
1658 if (ret)
1659 goto failed;
1660
1661 memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
1662 for (i=0; i<NR_TX_DESC; i++) {
1663 dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
1664 = cpu_to_le32(
1665 dev->tx_phy_descs
1666 + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4);
1667 }
1668
1669 dev->tx_idx = 0;
1670 dev->tx_done_idx = 0;
1671 desc = dev->tx_phy_descs;
1672 writel(0, dev->base + TXDP_HI);
1673 writel(desc, dev->base + TXDP);
1674
1675 init_timer(&dev->tx_watchdog);
1676 dev->tx_watchdog.data = (unsigned long)ndev;
1677 dev->tx_watchdog.function = ns83820_tx_watch;
1678 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1679
1680 netif_start_queue(ndev); /* FIXME: wait for phy to come up */
1681
1682 return 0;
1683
1684 failed:
1685 ns83820_stop(ndev);
1686 return ret;
1687 }
1688
1689 static void ns83820_getmac(struct ns83820 *dev, u8 *mac)
1690 {
1691 unsigned i;
1692 for (i=0; i<3; i++) {
1693 u32 data;
1694
1695 /* Read from the perfect match memory: this is loaded by
1696 * the chip from the EEPROM via the EELOAD self test.
1697 */
1698 writel(i*2, dev->base + RFCR);
1699 data = readl(dev->base + RFDR);
1700
1701 *mac++ = data;
1702 *mac++ = data >> 8;
1703 }
1704 }
1705
1706 static int ns83820_change_mtu(struct net_device *ndev, int new_mtu)
1707 {
1708 if (new_mtu > RX_BUF_SIZE)
1709 return -EINVAL;
1710 ndev->mtu = new_mtu;
1711 return 0;
1712 }
1713
1714 static void ns83820_set_multicast(struct net_device *ndev)
1715 {
1716 struct ns83820 *dev = PRIV(ndev);
1717 u8 __iomem *rfcr = dev->base + RFCR;
1718 u32 and_mask = 0xffffffff;
1719 u32 or_mask = 0;
1720 u32 val;
1721
1722 if (ndev->flags & IFF_PROMISC)
1723 or_mask |= RFCR_AAU | RFCR_AAM;
1724 else
1725 and_mask &= ~(RFCR_AAU | RFCR_AAM);
1726
1727 if (ndev->flags & IFF_ALLMULTI || ndev->mc_count)
1728 or_mask |= RFCR_AAM;
1729 else
1730 and_mask &= ~RFCR_AAM;
1731
1732 spin_lock_irq(&dev->misc_lock);
1733 val = (readl(rfcr) & and_mask) | or_mask;
1734 /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */
1735 writel(val & ~RFCR_RFEN, rfcr);
1736 writel(val, rfcr);
1737 spin_unlock_irq(&dev->misc_lock);
1738 }
1739
1740 static void ns83820_run_bist(struct net_device *ndev, const char *name, u32 enable, u32 done, u32 fail)
1741 {
1742 struct ns83820 *dev = PRIV(ndev);
1743 int timed_out = 0;
1744 unsigned long start;
1745 u32 status;
1746 int loops = 0;
1747
1748 dprintk("%s: start %s\n", ndev->name, name);
1749
1750 start = jiffies;
1751
1752 writel(enable, dev->base + PTSCR);
1753 for (;;) {
1754 loops++;
1755 status = readl(dev->base + PTSCR);
1756 if (!(status & enable))
1757 break;
1758 if (status & done)
1759 break;
1760 if (status & fail)
1761 break;
1762 if (time_after_eq(jiffies, start + HZ)) {
1763 timed_out = 1;
1764 break;
1765 }
1766 schedule_timeout_uninterruptible(1);
1767 }
1768
1769 if (status & fail)
1770 printk(KERN_INFO "%s: %s failed! (0x%08x & 0x%08x)\n",
1771 ndev->name, name, status, fail);
1772 else if (timed_out)
1773 printk(KERN_INFO "%s: run_bist %s timed out! (%08x)\n",
1774 ndev->name, name, status);
1775
1776 dprintk("%s: done %s in %d loops\n", ndev->name, name, loops);
1777 }
1778
1779 #ifdef PHY_CODE_IS_FINISHED
1780 static void ns83820_mii_write_bit(struct ns83820 *dev, int bit)
1781 {
1782 /* drive MDC low */
1783 dev->MEAR_cache &= ~MEAR_MDC;
1784 writel(dev->MEAR_cache, dev->base + MEAR);
1785 readl(dev->base + MEAR);
1786
1787 /* enable output, set bit */
1788 dev->MEAR_cache |= MEAR_MDDIR;
1789 if (bit)
1790 dev->MEAR_cache |= MEAR_MDIO;
1791 else
1792 dev->MEAR_cache &= ~MEAR_MDIO;
1793
1794 /* set the output bit */
1795 writel(dev->MEAR_cache, dev->base + MEAR);
1796 readl(dev->base + MEAR);
1797
1798 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1799 udelay(1);
1800
1801 /* drive MDC high causing the data bit to be latched */
1802 dev->MEAR_cache |= MEAR_MDC;
1803 writel(dev->MEAR_cache, dev->base + MEAR);
1804 readl(dev->base + MEAR);
1805
1806 /* Wait again... */
1807 udelay(1);
1808 }
1809
1810 static int ns83820_mii_read_bit(struct ns83820 *dev)
1811 {
1812 int bit;
1813
1814 /* drive MDC low, disable output */
1815 dev->MEAR_cache &= ~MEAR_MDC;
1816 dev->MEAR_cache &= ~MEAR_MDDIR;
1817 writel(dev->MEAR_cache, dev->base + MEAR);
1818 readl(dev->base + MEAR);
1819
1820 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1821 udelay(1);
1822
1823 /* drive MDC high causing the data bit to be latched */
1824 bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
1825 dev->MEAR_cache |= MEAR_MDC;
1826 writel(dev->MEAR_cache, dev->base + MEAR);
1827
1828 /* Wait again... */
1829 udelay(1);
1830
1831 return bit;
1832 }
1833
1834 static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg)
1835 {
1836 unsigned data = 0;
1837 int i;
1838
1839 /* read some garbage so that we eventually sync up */
1840 for (i=0; i<64; i++)
1841 ns83820_mii_read_bit(dev);
1842
1843 ns83820_mii_write_bit(dev, 0); /* start */
1844 ns83820_mii_write_bit(dev, 1);
1845 ns83820_mii_write_bit(dev, 1); /* opcode read */
1846 ns83820_mii_write_bit(dev, 0);
1847
1848 /* write out the phy address: 5 bits, msb first */
1849 for (i=0; i<5; i++)
1850 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1851
1852 /* write out the register address, 5 bits, msb first */
1853 for (i=0; i<5; i++)
1854 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1855
1856 ns83820_mii_read_bit(dev); /* turn around cycles */
1857 ns83820_mii_read_bit(dev);
1858
1859 /* read in the register data, 16 bits msb first */
1860 for (i=0; i<16; i++) {
1861 data <<= 1;
1862 data |= ns83820_mii_read_bit(dev);
1863 }
1864
1865 return data;
1866 }
1867
1868 static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data)
1869 {
1870 int i;
1871
1872 /* read some garbage so that we eventually sync up */
1873 for (i=0; i<64; i++)
1874 ns83820_mii_read_bit(dev);
1875
1876 ns83820_mii_write_bit(dev, 0); /* start */
1877 ns83820_mii_write_bit(dev, 1);
1878 ns83820_mii_write_bit(dev, 0); /* opcode read */
1879 ns83820_mii_write_bit(dev, 1);
1880
1881 /* write out the phy address: 5 bits, msb first */
1882 for (i=0; i<5; i++)
1883 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1884
1885 /* write out the register address, 5 bits, msb first */
1886 for (i=0; i<5; i++)
1887 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1888
1889 ns83820_mii_read_bit(dev); /* turn around cycles */
1890 ns83820_mii_read_bit(dev);
1891
1892 /* read in the register data, 16 bits msb first */
1893 for (i=0; i<16; i++)
1894 ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1);
1895
1896 return data;
1897 }
1898
1899 static void ns83820_probe_phy(struct net_device *ndev)
1900 {
1901 struct ns83820 *dev = PRIV(ndev);
1902 static int first;
1903 int i;
1904 #define MII_PHYIDR1 0x02
1905 #define MII_PHYIDR2 0x03
1906
1907 #if 0
1908 if (!first) {
1909 unsigned tmp;
1910 ns83820_mii_read_reg(dev, 1, 0x09);
1911 ns83820_mii_write_reg(dev, 1, 0x10, 0x0d3e);
1912
1913 tmp = ns83820_mii_read_reg(dev, 1, 0x00);
1914 ns83820_mii_write_reg(dev, 1, 0x00, tmp | 0x8000);
1915 udelay(1300);
1916 ns83820_mii_read_reg(dev, 1, 0x09);
1917 }
1918 #endif
1919 first = 1;
1920
1921 for (i=1; i<2; i++) {
1922 int j;
1923 unsigned a, b;
1924 a = ns83820_mii_read_reg(dev, i, MII_PHYIDR1);
1925 b = ns83820_mii_read_reg(dev, i, MII_PHYIDR2);
1926
1927 //printk("%s: phy %d: 0x%04x 0x%04x\n",
1928 // ndev->name, i, a, b);
1929
1930 for (j=0; j<0x16; j+=4) {
1931 dprintk("%s: [0x%02x] %04x %04x %04x %04x\n",
1932 ndev->name, j,
1933 ns83820_mii_read_reg(dev, i, 0 + j),
1934 ns83820_mii_read_reg(dev, i, 1 + j),
1935 ns83820_mii_read_reg(dev, i, 2 + j),
1936 ns83820_mii_read_reg(dev, i, 3 + j)
1937 );
1938 }
1939 }
1940 {
1941 unsigned a, b;
1942 /* read firmware version: memory addr is 0x8402 and 0x8403 */
1943 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1944 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1945 a = ns83820_mii_read_reg(dev, 1, 0x1d);
1946
1947 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1948 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1949 b = ns83820_mii_read_reg(dev, 1, 0x1d);
1950 dprintk("version: 0x%04x 0x%04x\n", a, b);
1951 }
1952 }
1953 #endif
1954
1955 static int __devinit ns83820_init_one(struct pci_dev *pci_dev, const struct pci_device_id *id)
1956 {
1957 struct net_device *ndev;
1958 struct ns83820 *dev;
1959 long addr;
1960 int err;
1961 int using_dac = 0;
1962 DECLARE_MAC_BUF(mac);
1963
1964 /* See if we can set the dma mask early on; failure is fatal. */
1965 if (sizeof(dma_addr_t) == 8 &&
1966 !pci_set_dma_mask(pci_dev, DMA_64BIT_MASK)) {
1967 using_dac = 1;
1968 } else if (!pci_set_dma_mask(pci_dev, DMA_32BIT_MASK)) {
1969 using_dac = 0;
1970 } else {
1971 dev_warn(&pci_dev->dev, "pci_set_dma_mask failed!\n");
1972 return -ENODEV;
1973 }
1974
1975 ndev = alloc_etherdev(sizeof(struct ns83820));
1976 dev = PRIV(ndev);
1977
1978 err = -ENOMEM;
1979 if (!dev)
1980 goto out;
1981
1982 dev->ndev = ndev;
1983
1984 spin_lock_init(&dev->rx_info.lock);
1985 spin_lock_init(&dev->tx_lock);
1986 spin_lock_init(&dev->misc_lock);
1987 dev->pci_dev = pci_dev;
1988
1989 SET_NETDEV_DEV(ndev, &pci_dev->dev);
1990
1991 INIT_WORK(&dev->tq_refill, queue_refill);
1992 tasklet_init(&dev->rx_tasklet, rx_action, (unsigned long)ndev);
1993
1994 err = pci_enable_device(pci_dev);
1995 if (err) {
1996 dev_info(&pci_dev->dev, "pci_enable_dev failed: %d\n", err);
1997 goto out_free;
1998 }
1999
2000 pci_set_master(pci_dev);
2001 addr = pci_resource_start(pci_dev, 1);
2002 dev->base = ioremap_nocache(addr, PAGE_SIZE);
2003 dev->tx_descs = pci_alloc_consistent(pci_dev,
2004 4 * DESC_SIZE * NR_TX_DESC, &dev->tx_phy_descs);
2005 dev->rx_info.descs = pci_alloc_consistent(pci_dev,
2006 4 * DESC_SIZE * NR_RX_DESC, &dev->rx_info.phy_descs);
2007 err = -ENOMEM;
2008 if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
2009 goto out_disable;
2010
2011 dprintk("%p: %08lx %p: %08lx\n",
2012 dev->tx_descs, (long)dev->tx_phy_descs,
2013 dev->rx_info.descs, (long)dev->rx_info.phy_descs);
2014
2015 /* disable interrupts */
2016 writel(0, dev->base + IMR);
2017 writel(0, dev->base + IER);
2018 readl(dev->base + IER);
2019
2020 dev->IMR_cache = 0;
2021
2022 err = request_irq(pci_dev->irq, ns83820_irq, IRQF_SHARED,
2023 DRV_NAME, ndev);
2024 if (err) {
2025 dev_info(&pci_dev->dev, "unable to register irq %d, err %d\n",
2026 pci_dev->irq, err);
2027 goto out_disable;
2028 }
2029
2030 /*
2031 * FIXME: we are holding rtnl_lock() over obscenely long area only
2032 * because some of the setup code uses dev->name. It's Wrong(tm) -
2033 * we should be using driver-specific names for all that stuff.
2034 * For now that will do, but we really need to come back and kill
2035 * most of the dev_alloc_name() users later.
2036 */
2037 rtnl_lock();
2038 err = dev_alloc_name(ndev, ndev->name);
2039 if (err < 0) {
2040 dev_info(&pci_dev->dev, "unable to get netdev name: %d\n", err);
2041 goto out_free_irq;
2042 }
2043
2044 printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n",
2045 ndev->name, le32_to_cpu(readl(dev->base + 0x22c)),
2046 pci_dev->subsystem_vendor, pci_dev->subsystem_device);
2047
2048 ndev->open = ns83820_open;
2049 ndev->stop = ns83820_stop;
2050 ndev->hard_start_xmit = ns83820_hard_start_xmit;
2051 ndev->get_stats = ns83820_get_stats;
2052 ndev->change_mtu = ns83820_change_mtu;
2053 ndev->set_multicast_list = ns83820_set_multicast;
2054 SET_ETHTOOL_OPS(ndev, &ops);
2055 ndev->tx_timeout = ns83820_tx_timeout;
2056 ndev->watchdog_timeo = 5 * HZ;
2057 pci_set_drvdata(pci_dev, ndev);
2058
2059 ns83820_do_reset(dev, CR_RST);
2060
2061 /* Must reset the ram bist before running it */
2062 writel(PTSCR_RBIST_RST, dev->base + PTSCR);
2063 ns83820_run_bist(ndev, "sram bist", PTSCR_RBIST_EN,
2064 PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL);
2065 ns83820_run_bist(ndev, "eeprom bist", PTSCR_EEBIST_EN, 0,
2066 PTSCR_EEBIST_FAIL);
2067 ns83820_run_bist(ndev, "eeprom load", PTSCR_EELOAD_EN, 0, 0);
2068
2069 /* I love config registers */
2070 dev->CFG_cache = readl(dev->base + CFG);
2071
2072 if ((dev->CFG_cache & CFG_PCI64_DET)) {
2073 printk(KERN_INFO "%s: detected 64 bit PCI data bus.\n",
2074 ndev->name);
2075 /*dev->CFG_cache |= CFG_DATA64_EN;*/
2076 if (!(dev->CFG_cache & CFG_DATA64_EN))
2077 printk(KERN_INFO "%s: EEPROM did not enable 64 bit bus. Disabled.\n",
2078 ndev->name);
2079 } else
2080 dev->CFG_cache &= ~(CFG_DATA64_EN);
2081
2082 dev->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS |
2083 CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 |
2084 CFG_M64ADDR);
2085 dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
2086 CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL;
2087 dev->CFG_cache |= CFG_REQALG;
2088 dev->CFG_cache |= CFG_POW;
2089 dev->CFG_cache |= CFG_TMRTEST;
2090
2091 /* When compiled with 64 bit addressing, we must always enable
2092 * the 64 bit descriptor format.
2093 */
2094 if (sizeof(dma_addr_t) == 8)
2095 dev->CFG_cache |= CFG_M64ADDR;
2096 if (using_dac)
2097 dev->CFG_cache |= CFG_T64ADDR;
2098
2099 /* Big endian mode does not seem to do what the docs suggest */
2100 dev->CFG_cache &= ~CFG_BEM;
2101
2102 /* setup optical transceiver if we have one */
2103 if (dev->CFG_cache & CFG_TBI_EN) {
2104 printk(KERN_INFO "%s: enabling optical transceiver\n",
2105 ndev->name);
2106 writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
2107
2108 /* setup auto negotiation feature advertisement */
2109 writel(readl(dev->base + TANAR)
2110 | TANAR_HALF_DUP | TANAR_FULL_DUP,
2111 dev->base + TANAR);
2112
2113 /* start auto negotiation */
2114 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
2115 dev->base + TBICR);
2116 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
2117 dev->linkstate = LINK_AUTONEGOTIATE;
2118
2119 dev->CFG_cache |= CFG_MODE_1000;
2120 }
2121
2122 writel(dev->CFG_cache, dev->base + CFG);
2123 dprintk("CFG: %08x\n", dev->CFG_cache);
2124
2125 if (reset_phy) {
2126 printk(KERN_INFO "%s: resetting phy\n", ndev->name);
2127 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
2128 msleep(10);
2129 writel(dev->CFG_cache, dev->base + CFG);
2130 }
2131
2132 #if 0 /* Huh? This sets the PCI latency register. Should be done via
2133 * the PCI layer. FIXME.
2134 */
2135 if (readl(dev->base + SRR))
2136 writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
2137 #endif
2138
2139 /* Note! The DMA burst size interacts with packet
2140 * transmission, such that the largest packet that
2141 * can be transmitted is 8192 - FLTH - burst size.
2142 * If only the transmit fifo was larger...
2143 */
2144 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2145 * some DELL and COMPAQ SMP systems */
2146 writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
2147 | ((1600 / 32) * 0x100),
2148 dev->base + TXCFG);
2149
2150 /* Flush the interrupt holdoff timer */
2151 writel(0x000, dev->base + IHR);
2152 writel(0x100, dev->base + IHR);
2153 writel(0x000, dev->base + IHR);
2154
2155 /* Set Rx to full duplex, don't accept runt, errored, long or length
2156 * range errored packets. Use 512 byte DMA.
2157 */
2158 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2159 * some DELL and COMPAQ SMP systems
2160 * Turn on ALP, only we are accpeting Jumbo Packets */
2161 writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
2162 | RXCFG_STRIPCRC
2163 //| RXCFG_ALP
2164 | (RXCFG_MXDMA512) | 0, dev->base + RXCFG);
2165
2166 /* Disable priority queueing */
2167 writel(0, dev->base + PQCR);
2168
2169 /* Enable IP checksum validation and detetion of VLAN headers.
2170 * Note: do not set the reject options as at least the 0x102
2171 * revision of the chip does not properly accept IP fragments
2172 * at least for UDP.
2173 */
2174 /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since
2175 * the MAC it calculates the packetsize AFTER stripping the VLAN
2176 * header, and if a VLAN Tagged packet of 64 bytes is received (like
2177 * a ping with a VLAN header) then the card, strips the 4 byte VLAN
2178 * tag and then checks the packet size, so if RXCFG_ARP is not enabled,
2179 * it discrards it!. These guys......
2180 * also turn on tag stripping if hardware acceleration is enabled
2181 */
2182 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2183 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN|VRCR_VTREN)
2184 #else
2185 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN)
2186 #endif
2187 writel(VRCR_INIT_VALUE, dev->base + VRCR);
2188
2189 /* Enable per-packet TCP/UDP/IP checksumming
2190 * and per packet vlan tag insertion if
2191 * vlan hardware acceleration is enabled
2192 */
2193 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2194 #define VTCR_INIT_VALUE (VTCR_PPCHK|VTCR_VPPTI)
2195 #else
2196 #define VTCR_INIT_VALUE VTCR_PPCHK
2197 #endif
2198 writel(VTCR_INIT_VALUE, dev->base + VTCR);
2199
2200 /* Ramit : Enable async and sync pause frames */
2201 /* writel(0, dev->base + PCR); */
2202 writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
2203 PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT),
2204 dev->base + PCR);
2205
2206 /* Disable Wake On Lan */
2207 writel(0, dev->base + WCSR);
2208
2209 ns83820_getmac(dev, ndev->dev_addr);
2210
2211 /* Yes, we support dumb IP checksum on transmit */
2212 ndev->features |= NETIF_F_SG;
2213 ndev->features |= NETIF_F_IP_CSUM;
2214
2215 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2216 /* We also support hardware vlan acceleration */
2217 ndev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2218 ndev->vlan_rx_register = ns83820_vlan_rx_register;
2219 #endif
2220
2221 if (using_dac) {
2222 printk(KERN_INFO "%s: using 64 bit addressing.\n",
2223 ndev->name);
2224 ndev->features |= NETIF_F_HIGHDMA;
2225 }
2226
2227 printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %s io=0x%08lx irq=%d f=%s\n",
2228 ndev->name,
2229 (unsigned)readl(dev->base + SRR) >> 8,
2230 (unsigned)readl(dev->base + SRR) & 0xff,
2231 print_mac(mac, ndev->dev_addr),
2232 addr, pci_dev->irq,
2233 (ndev->features & NETIF_F_HIGHDMA) ? "h,sg" : "sg"
2234 );
2235
2236 #ifdef PHY_CODE_IS_FINISHED
2237 ns83820_probe_phy(ndev);
2238 #endif
2239
2240 err = register_netdevice(ndev);
2241 if (err) {
2242 printk(KERN_INFO "ns83820: unable to register netdev: %d\n", err);
2243 goto out_cleanup;
2244 }
2245 rtnl_unlock();
2246
2247 return 0;
2248
2249 out_cleanup:
2250 writel(0, dev->base + IMR); /* paranoia */
2251 writel(0, dev->base + IER);
2252 readl(dev->base + IER);
2253 out_free_irq:
2254 rtnl_unlock();
2255 free_irq(pci_dev->irq, ndev);
2256 out_disable:
2257 if (dev->base)
2258 iounmap(dev->base);
2259 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_TX_DESC, dev->tx_descs, dev->tx_phy_descs);
2260 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_RX_DESC, dev->rx_info.descs, dev->rx_info.phy_descs);
2261 pci_disable_device(pci_dev);
2262 out_free:
2263 free_netdev(ndev);
2264 pci_set_drvdata(pci_dev, NULL);
2265 out:
2266 return err;
2267 }
2268
2269 static void __devexit ns83820_remove_one(struct pci_dev *pci_dev)
2270 {
2271 struct net_device *ndev = pci_get_drvdata(pci_dev);
2272 struct ns83820 *dev = PRIV(ndev); /* ok even if NULL */
2273
2274 if (!ndev) /* paranoia */
2275 return;
2276
2277 writel(0, dev->base + IMR); /* paranoia */
2278 writel(0, dev->base + IER);
2279 readl(dev->base + IER);
2280
2281 unregister_netdev(ndev);
2282 free_irq(dev->pci_dev->irq, ndev);
2283 iounmap(dev->base);
2284 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_TX_DESC,
2285 dev->tx_descs, dev->tx_phy_descs);
2286 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_RX_DESC,
2287 dev->rx_info.descs, dev->rx_info.phy_descs);
2288 pci_disable_device(dev->pci_dev);
2289 free_netdev(ndev);
2290 pci_set_drvdata(pci_dev, NULL);
2291 }
2292
2293 static struct pci_device_id ns83820_pci_tbl[] = {
2294 { 0x100b, 0x0022, PCI_ANY_ID, PCI_ANY_ID, 0, .driver_data = 0, },
2295 { 0, },
2296 };
2297
2298 static struct pci_driver driver = {
2299 .name = "ns83820",
2300 .id_table = ns83820_pci_tbl,
2301 .probe = ns83820_init_one,
2302 .remove = __devexit_p(ns83820_remove_one),
2303 #if 0 /* FIXME: implement */
2304 .suspend = ,
2305 .resume = ,
2306 #endif
2307 };
2308
2309
2310 static int __init ns83820_init(void)
2311 {
2312 printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n");
2313 return pci_register_driver(&driver);
2314 }
2315
2316 static void __exit ns83820_exit(void)
2317 {
2318 pci_unregister_driver(&driver);
2319 }
2320
2321 MODULE_AUTHOR("Benjamin LaHaise <bcrl@kvack.org>");
2322 MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver");
2323 MODULE_LICENSE("GPL");
2324
2325 MODULE_DEVICE_TABLE(pci, ns83820_pci_tbl);
2326
2327 module_param(lnksts, int, 0);
2328 MODULE_PARM_DESC(lnksts, "Polarity of LNKSTS bit");
2329
2330 module_param(ihr, int, 0);
2331 MODULE_PARM_DESC(ihr, "Time in 100 us increments to delay interrupts (range 0-127)");
2332
2333 module_param(reset_phy, int, 0);
2334 MODULE_PARM_DESC(reset_phy, "Set to 1 to reset the PHY on startup");
2335
2336 module_init(ns83820_init);
2337 module_exit(ns83820_exit);
AMDTP streaming driver for the Linux FireWire stack (Juju)