1 #ifndef _PPC64_PGTABLE_H
2 #define _PPC64_PGTABLE_H
5 * This file contains the functions and defines necessary to modify and use
6 * the ppc64 hashed page table.
10 #include <linux/config.h>
11 #include <linux/stddef.h>
12 #include <asm/processor.h> /* For TASK_SIZE */
15 #include <asm/tlbflush.h>
17 #endif /* __ASSEMBLY__ */
19 #ifdef CONFIG_PPC_64K_PAGES
20 #include <asm/pgtable-64k.h>
22 #include <asm/pgtable-4k.h>
25 #define FIRST_USER_ADDRESS 0
28 * Size of EA range mapped by our pagetables.
30 #define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
31 PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
32 #define PGTABLE_RANGE (1UL << PGTABLE_EADDR_SIZE)
34 #if TASK_SIZE_USER64 > PGTABLE_RANGE
35 #error TASK_SIZE_USER64 exceeds pagetable range
38 #if TASK_SIZE_USER64 > (1UL << (USER_ESID_BITS + SID_SHIFT))
39 #error TASK_SIZE_USER64 exceeds user VSID range
43 * Define the address range of the vmalloc VM area.
45 #define VMALLOC_START (0xD000000000000000ul)
46 #define VMALLOC_SIZE (0x80000000000UL)
47 #define VMALLOC_END (VMALLOC_START + VMALLOC_SIZE)
50 * Common bits in a linux-style PTE. These match the bits in the
51 * (hardware-defined) PowerPC PTE as closely as possible. Additional
52 * bits may be defined in pgtable-*.h
54 #define _PAGE_PRESENT 0x0001 /* software: pte contains a translation */
55 #define _PAGE_USER 0x0002 /* matches one of the PP bits */
56 #define _PAGE_FILE 0x0002 /* (!present only) software: pte holds file offset */
57 #define _PAGE_EXEC 0x0004 /* No execute on POWER4 and newer (we invert) */
58 #define _PAGE_GUARDED 0x0008
59 #define _PAGE_COHERENT 0x0010 /* M: enforce memory coherence (SMP systems) */
60 #define _PAGE_NO_CACHE 0x0020 /* I: cache inhibit */
61 #define _PAGE_WRITETHRU 0x0040 /* W: cache write-through */
62 #define _PAGE_DIRTY 0x0080 /* C: page changed */
63 #define _PAGE_ACCESSED 0x0100 /* R: page referenced */
64 #define _PAGE_RW 0x0200 /* software: user write access allowed */
65 #define _PAGE_HASHPTE 0x0400 /* software: pte has an associated HPTE */
66 #define _PAGE_BUSY 0x0800 /* software: PTE & hash are busy */
68 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT)
70 #define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY)
72 /* __pgprot defined in asm-ppc64/page.h */
73 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
75 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER)
76 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER | _PAGE_EXEC)
77 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
78 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
79 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
80 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
81 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_WRENABLE)
82 #define PAGE_KERNEL_CI __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
83 _PAGE_WRENABLE | _PAGE_NO_CACHE | _PAGE_GUARDED)
84 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_EXEC)
86 #define PAGE_AGP __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_NO_CACHE)
90 #define _PTEIDX_SECONDARY 0x8
91 #define _PTEIDX_GROUP_IX 0x7
95 * POWER4 and newer have per page execute protection, older chips can only
96 * do this on a segment (256MB) basis.
98 * Also, write permissions imply read permissions.
99 * This is the closest we can get..
101 * Note due to the way vm flags are laid out, the bits are XWR
103 #define __P000 PAGE_NONE
104 #define __P001 PAGE_READONLY
105 #define __P010 PAGE_COPY
106 #define __P011 PAGE_COPY
107 #define __P100 PAGE_READONLY_X
108 #define __P101 PAGE_READONLY_X
109 #define __P110 PAGE_COPY_X
110 #define __P111 PAGE_COPY_X
112 #define __S000 PAGE_NONE
113 #define __S001 PAGE_READONLY
114 #define __S010 PAGE_SHARED
115 #define __S011 PAGE_SHARED
116 #define __S100 PAGE_READONLY_X
117 #define __S101 PAGE_READONLY_X
118 #define __S110 PAGE_SHARED_X
119 #define __S111 PAGE_SHARED_X
124 * ZERO_PAGE is a global shared page that is always zero: used
125 * for zero-mapped memory areas etc..
127 extern unsigned long empty_zero_page
[PAGE_SIZE
/sizeof(unsigned long)];
128 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
129 #endif /* __ASSEMBLY__ */
131 #ifdef CONFIG_HUGETLB_PAGE
133 #define HAVE_ARCH_UNMAPPED_AREA
134 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
141 * Conversion functions: convert a page and protection to a page entry,
142 * and a page entry and page directory to the page they refer to.
144 * mk_pte takes a (struct page *) as input
146 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
148 static inline pte_t
pfn_pte(unsigned long pfn
, pgprot_t pgprot
)
153 pte_val(pte
) = (pfn
<< PTE_RPN_SHIFT
) | pgprot_val(pgprot
);
157 #define pte_modify(_pte, newprot) \
158 (__pte((pte_val(_pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)))
160 #define pte_none(pte) ((pte_val(pte) & ~_PAGE_HPTEFLAGS) == 0)
161 #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
163 /* pte_clear moved to later in this file */
165 #define pte_pfn(x) ((unsigned long)((pte_val(x)>>PTE_RPN_SHIFT)))
166 #define pte_page(x) pfn_to_page(pte_pfn(x))
168 #define pmd_set(pmdp, pmdval) (pmd_val(*(pmdp)) = (pmdval))
169 #define pmd_none(pmd) (!pmd_val(pmd))
170 #define pmd_bad(pmd) (pmd_val(pmd) == 0)
171 #define pmd_present(pmd) (pmd_val(pmd) != 0)
172 #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0)
173 #define pmd_page_kernel(pmd) (pmd_val(pmd) & ~PMD_MASKED_BITS)
174 #define pmd_page(pmd) virt_to_page(pmd_page_kernel(pmd))
176 #define pud_set(pudp, pudval) (pud_val(*(pudp)) = (pudval))
177 #define pud_none(pud) (!pud_val(pud))
178 #define pud_bad(pud) ((pud_val(pud)) == 0)
179 #define pud_present(pud) (pud_val(pud) != 0)
180 #define pud_clear(pudp) (pud_val(*(pudp)) = 0)
181 #define pud_page(pud) (pud_val(pud) & ~PUD_MASKED_BITS)
183 #define pgd_set(pgdp, pudp) ({pgd_val(*(pgdp)) = (unsigned long)(pudp);})
186 * Find an entry in a page-table-directory. We combine the address region
187 * (the high order N bits) and the pgd portion of the address.
189 /* to avoid overflow in free_pgtables we don't use PTRS_PER_PGD here */
190 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & 0x1ff)
192 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
194 #define pmd_offset(pudp,addr) \
195 (((pmd_t *) pud_page(*(pudp))) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
197 #define pte_offset_kernel(dir,addr) \
198 (((pte_t *) pmd_page_kernel(*(dir))) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
200 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
201 #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
202 #define pte_unmap(pte) do { } while(0)
203 #define pte_unmap_nested(pte) do { } while(0)
205 /* to find an entry in a kernel page-table-directory */
206 /* This now only contains the vmalloc pages */
207 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
210 * The following only work if pte_present() is true.
211 * Undefined behaviour if not..
213 static inline int pte_read(pte_t pte
) { return pte_val(pte
) & _PAGE_USER
;}
214 static inline int pte_write(pte_t pte
) { return pte_val(pte
) & _PAGE_RW
;}
215 static inline int pte_exec(pte_t pte
) { return pte_val(pte
) & _PAGE_EXEC
;}
216 static inline int pte_dirty(pte_t pte
) { return pte_val(pte
) & _PAGE_DIRTY
;}
217 static inline int pte_young(pte_t pte
) { return pte_val(pte
) & _PAGE_ACCESSED
;}
218 static inline int pte_file(pte_t pte
) { return pte_val(pte
) & _PAGE_FILE
;}
220 static inline void pte_uncache(pte_t pte
) { pte_val(pte
) |= _PAGE_NO_CACHE
; }
221 static inline void pte_cache(pte_t pte
) { pte_val(pte
) &= ~_PAGE_NO_CACHE
; }
223 static inline pte_t
pte_rdprotect(pte_t pte
) {
224 pte_val(pte
) &= ~_PAGE_USER
; return pte
; }
225 static inline pte_t
pte_exprotect(pte_t pte
) {
226 pte_val(pte
) &= ~_PAGE_EXEC
; return pte
; }
227 static inline pte_t
pte_wrprotect(pte_t pte
) {
228 pte_val(pte
) &= ~(_PAGE_RW
); return pte
; }
229 static inline pte_t
pte_mkclean(pte_t pte
) {
230 pte_val(pte
) &= ~(_PAGE_DIRTY
); return pte
; }
231 static inline pte_t
pte_mkold(pte_t pte
) {
232 pte_val(pte
) &= ~_PAGE_ACCESSED
; return pte
; }
233 static inline pte_t
pte_mkread(pte_t pte
) {
234 pte_val(pte
) |= _PAGE_USER
; return pte
; }
235 static inline pte_t
pte_mkexec(pte_t pte
) {
236 pte_val(pte
) |= _PAGE_USER
| _PAGE_EXEC
; return pte
; }
237 static inline pte_t
pte_mkwrite(pte_t pte
) {
238 pte_val(pte
) |= _PAGE_RW
; return pte
; }
239 static inline pte_t
pte_mkdirty(pte_t pte
) {
240 pte_val(pte
) |= _PAGE_DIRTY
; return pte
; }
241 static inline pte_t
pte_mkyoung(pte_t pte
) {
242 pte_val(pte
) |= _PAGE_ACCESSED
; return pte
; }
243 static inline pte_t
pte_mkhuge(pte_t pte
) {
246 /* Atomic PTE updates */
247 static inline unsigned long pte_update(pte_t
*p
, unsigned long clr
)
249 unsigned long old
, tmp
;
251 __asm__
__volatile__(
252 "1: ldarx %0,0,%3 # pte_update\n\
258 : "=&r" (old
), "=&r" (tmp
), "=m" (*p
)
259 : "r" (p
), "r" (clr
), "m" (*p
), "i" (_PAGE_BUSY
)
264 /* PTE updating functions, this function puts the PTE in the
265 * batch, doesn't actually triggers the hash flush immediately,
266 * you need to call flush_tlb_pending() to do that.
267 * Pass -1 for "normal" size (4K or 64K)
269 extern void hpte_update(struct mm_struct
*mm
, unsigned long addr
,
270 pte_t
*ptep
, unsigned long pte
, int huge
);
272 static inline int __ptep_test_and_clear_young(struct mm_struct
*mm
,
273 unsigned long addr
, pte_t
*ptep
)
277 if ((pte_val(*ptep
) & (_PAGE_ACCESSED
| _PAGE_HASHPTE
)) == 0)
279 old
= pte_update(ptep
, _PAGE_ACCESSED
);
280 if (old
& _PAGE_HASHPTE
) {
281 hpte_update(mm
, addr
, ptep
, old
, 0);
284 return (old
& _PAGE_ACCESSED
) != 0;
286 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
287 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \
290 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
295 * On RW/DIRTY bit transitions we can avoid flushing the hpte. For the
296 * moment we always flush but we need to fix hpte_update and test if the
297 * optimisation is worth it.
299 static inline int __ptep_test_and_clear_dirty(struct mm_struct
*mm
,
300 unsigned long addr
, pte_t
*ptep
)
304 if ((pte_val(*ptep
) & _PAGE_DIRTY
) == 0)
306 old
= pte_update(ptep
, _PAGE_DIRTY
);
307 if (old
& _PAGE_HASHPTE
)
308 hpte_update(mm
, addr
, ptep
, old
, 0);
309 return (old
& _PAGE_DIRTY
) != 0;
311 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
312 #define ptep_test_and_clear_dirty(__vma, __addr, __ptep) \
315 __r = __ptep_test_and_clear_dirty((__vma)->vm_mm, __addr, __ptep); \
319 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
320 static inline void ptep_set_wrprotect(struct mm_struct
*mm
, unsigned long addr
,
325 if ((pte_val(*ptep
) & _PAGE_RW
) == 0)
327 old
= pte_update(ptep
, _PAGE_RW
);
328 if (old
& _PAGE_HASHPTE
)
329 hpte_update(mm
, addr
, ptep
, old
, 0);
333 * We currently remove entries from the hashtable regardless of whether
334 * the entry was young or dirty. The generic routines only flush if the
335 * entry was young or dirty which is not good enough.
337 * We should be more intelligent about this but for the moment we override
338 * these functions and force a tlb flush unconditionally
340 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
341 #define ptep_clear_flush_young(__vma, __address, __ptep) \
343 int __young = __ptep_test_and_clear_young((__vma)->vm_mm, __address, \
348 #define __HAVE_ARCH_PTEP_CLEAR_DIRTY_FLUSH
349 #define ptep_clear_flush_dirty(__vma, __address, __ptep) \
351 int __dirty = __ptep_test_and_clear_dirty((__vma)->vm_mm, __address, \
353 flush_tlb_page(__vma, __address); \
357 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
358 static inline pte_t
ptep_get_and_clear(struct mm_struct
*mm
,
359 unsigned long addr
, pte_t
*ptep
)
361 unsigned long old
= pte_update(ptep
, ~0UL);
363 if (old
& _PAGE_HASHPTE
)
364 hpte_update(mm
, addr
, ptep
, old
, 0);
368 static inline void pte_clear(struct mm_struct
*mm
, unsigned long addr
,
371 unsigned long old
= pte_update(ptep
, ~0UL);
373 if (old
& _PAGE_HASHPTE
)
374 hpte_update(mm
, addr
, ptep
, old
, 0);
378 * set_pte stores a linux PTE into the linux page table.
380 static inline void set_pte_at(struct mm_struct
*mm
, unsigned long addr
,
381 pte_t
*ptep
, pte_t pte
)
383 if (pte_present(*ptep
)) {
384 pte_clear(mm
, addr
, ptep
);
387 pte
= __pte(pte_val(pte
) & ~_PAGE_HPTEFLAGS
);
389 #ifdef CONFIG_PPC_64K_PAGES
390 if (mmu_virtual_psize
!= MMU_PAGE_64K
)
391 pte
= __pte(pte_val(pte
) | _PAGE_COMBO
);
392 #endif /* CONFIG_PPC_64K_PAGES */
397 /* Set the dirty and/or accessed bits atomically in a linux PTE, this
398 * function doesn't need to flush the hash entry
400 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
401 static inline void __ptep_set_access_flags(pte_t
*ptep
, pte_t entry
, int dirty
)
403 unsigned long bits
= pte_val(entry
) &
404 (_PAGE_DIRTY
| _PAGE_ACCESSED
| _PAGE_RW
| _PAGE_EXEC
);
405 unsigned long old
, tmp
;
407 __asm__
__volatile__(
414 :"=&r" (old
), "=&r" (tmp
), "=m" (*ptep
)
415 :"r" (bits
), "r" (ptep
), "m" (*ptep
), "i" (_PAGE_BUSY
)
418 #define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
420 __ptep_set_access_flags(__ptep, __entry, __dirty); \
421 flush_tlb_page_nohash(__vma, __address); \
425 * Macro to mark a page protection value as "uncacheable".
427 #define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
430 extern pgprot_t
phys_mem_access_prot(struct file
*file
, unsigned long pfn
,
431 unsigned long size
, pgprot_t vma_prot
);
432 #define __HAVE_PHYS_MEM_ACCESS_PROT
434 #define __HAVE_ARCH_PTE_SAME
435 #define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)
437 #define pte_ERROR(e) \
438 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
439 #define pmd_ERROR(e) \
440 printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
441 #define pgd_ERROR(e) \
442 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
444 extern pgd_t swapper_pg_dir
[];
446 extern void paging_init(void);
448 #ifdef CONFIG_HUGETLB_PAGE
449 #define hugetlb_free_pgd_range(tlb, addr, end, floor, ceiling) \
450 free_pgd_range(tlb, addr, end, floor, ceiling)
454 * This gets called at the end of handling a page fault, when
455 * the kernel has put a new PTE into the page table for the process.
456 * We use it to put a corresponding HPTE into the hash table
457 * ahead of time, instead of waiting for the inevitable extra
458 * hash-table miss exception.
460 struct vm_area_struct
;
461 extern void update_mmu_cache(struct vm_area_struct
*, unsigned long, pte_t
);
463 /* Encode and de-code a swap entry */
464 #define __swp_type(entry) (((entry).val >> 1) & 0x3f)
465 #define __swp_offset(entry) ((entry).val >> 8)
466 #define __swp_entry(type, offset) ((swp_entry_t){((type)<< 1)|((offset)<<8)})
467 #define __pte_to_swp_entry(pte) ((swp_entry_t){pte_val(pte) >> PTE_RPN_SHIFT})
468 #define __swp_entry_to_pte(x) ((pte_t) { (x).val << PTE_RPN_SHIFT })
469 #define pte_to_pgoff(pte) (pte_val(pte) >> PTE_RPN_SHIFT)
470 #define pgoff_to_pte(off) ((pte_t) {((off) << PTE_RPN_SHIFT)|_PAGE_FILE})
471 #define PTE_FILE_MAX_BITS (BITS_PER_LONG - PTE_RPN_SHIFT)
474 * kern_addr_valid is intended to indicate whether an address is a valid
475 * kernel address. Most 32-bit archs define it as always true (like this)
476 * but most 64-bit archs actually perform a test. What should we do here?
477 * The only use is in fs/ncpfs/dir.c
479 #define kern_addr_valid(addr) (1)
481 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
482 remap_pfn_range(vma, vaddr, pfn, size, prot)
484 void pgtable_cache_init(void);
487 * find_linux_pte returns the address of a linux pte for a given
488 * effective address and directory. If not found, it returns zero.
489 */static inline pte_t
*find_linux_pte(pgd_t
*pgdir
, unsigned long ea
)
496 pg
= pgdir
+ pgd_index(ea
);
497 if (!pgd_none(*pg
)) {
498 pu
= pud_offset(pg
, ea
);
499 if (!pud_none(*pu
)) {
500 pm
= pmd_offset(pu
, ea
);
501 if (pmd_present(*pm
))
502 pt
= pte_offset_kernel(pm
, ea
);
508 #include <asm-generic/pgtable.h>
510 #endif /* __ASSEMBLY__ */
512 #endif /* _PPC64_PGTABLE_H */