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[ARM] pxa: separate PXA25x and PXA27x UDC register definitions
[firewire-audio.git] / drivers / usb / gadget / pxa2xx_udc.c
blob63db96adc0b03b1d4d81209596d975f90cebe043
1 /*
2 * linux/drivers/usb/gadget/pxa2xx_udc.c
3 * Intel PXA25x and IXP4xx on-chip full speed USB device controllers
4 *
5 * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
6 * Copyright (C) 2003 Robert Schwebel, Pengutronix
7 * Copyright (C) 2003 Benedikt Spranger, Pengutronix
8 * Copyright (C) 2003 David Brownell
9 * Copyright (C) 2003 Joshua Wise
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 */
26
27 /* #define VERBOSE_DEBUG */
28
29 #include <linux/device.h>
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/ioport.h>
33 #include <linux/types.h>
34 #include <linux/errno.h>
35 #include <linux/delay.h>
36 #include <linux/slab.h>
37 #include <linux/init.h>
38 #include <linux/timer.h>
39 #include <linux/list.h>
40 #include <linux/interrupt.h>
41 #include <linux/mm.h>
42 #include <linux/platform_device.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/irq.h>
45 #include <linux/clk.h>
46 #include <linux/err.h>
47 #include <linux/seq_file.h>
48 #include <linux/debugfs.h>
49 #include <linux/io.h>
50
51 #include <asm/byteorder.h>
52 #include <asm/dma.h>
53 #include <asm/gpio.h>
54 #include <asm/system.h>
55 #include <asm/mach-types.h>
56 #include <asm/unaligned.h>
57
58 #include <linux/usb/ch9.h>
59 #include <linux/usb/gadget.h>
60
61 /*
62 * This driver is PXA25x only. Grab the right register definitions.
63 */
64 #ifdef CONFIG_ARCH_PXA
65 #include <asm/arch/pxa25x-udc.h>
66 #endif
67
68 #include <asm/mach/udc_pxa2xx.h>
69
70
71 /*
72 * This driver handles the USB Device Controller (UDC) in Intel's PXA 25x
73 * series processors. The UDC for the IXP 4xx series is very similar.
74 * There are fifteen endpoints, in addition to ep0.
75 *
76 * Such controller drivers work with a gadget driver. The gadget driver
77 * returns descriptors, implements configuration and data protocols used
78 * by the host to interact with this device, and allocates endpoints to
79 * the different protocol interfaces. The controller driver virtualizes
80 * usb hardware so that the gadget drivers will be more portable.
81 *
82 * This UDC hardware wants to implement a bit too much USB protocol, so
83 * it constrains the sorts of USB configuration change events that work.
84 * The errata for these chips are misleading; some "fixed" bugs from
85 * pxa250 a0/a1 b0/b1/b2 sure act like they're still there.
86 *
87 * Note that the UDC hardware supports DMA (except on IXP) but that's
88 * not used here. IN-DMA (to host) is simple enough, when the data is
89 * suitably aligned (16 bytes) ... the network stack doesn't do that,
90 * other software can. OUT-DMA is buggy in most chip versions, as well
91 * as poorly designed (data toggle not automatic). So this driver won't
92 * bother using DMA. (Mostly-working IN-DMA support was available in
93 * kernels before 2.6.23, but was never enabled or well tested.)
94 */
95
96 #define DRIVER_VERSION "30-June-2007"
97 #define DRIVER_DESC "PXA 25x USB Device Controller driver"
98
99
100 static const char driver_name [] = "pxa2xx_udc";
101
102 static const char ep0name [] = "ep0";
103
104
105 #ifdef CONFIG_ARCH_IXP4XX
106
107 /* cpu-specific register addresses are compiled in to this code */
108 #ifdef CONFIG_ARCH_PXA
109 #error "Can't configure both IXP and PXA"
110 #endif
111
112 /* IXP doesn't yet support <linux/clk.h> */
113 #define clk_get(dev,name) NULL
114 #define clk_enable(clk) do { } while (0)
115 #define clk_disable(clk) do { } while (0)
116 #define clk_put(clk) do { } while (0)
117
118 #endif
119
120 #include "pxa2xx_udc.h"
121
122
123 #ifdef CONFIG_USB_PXA2XX_SMALL
124 #define SIZE_STR " (small)"
125 #else
126 #define SIZE_STR ""
127 #endif
128
129 /* ---------------------------------------------------------------------------
130 * endpoint related parts of the api to the usb controller hardware,
131 * used by gadget driver; and the inner talker-to-hardware core.
132 * ---------------------------------------------------------------------------
133 */
134
135 static void pxa2xx_ep_fifo_flush (struct usb_ep *ep);
136 static void nuke (struct pxa2xx_ep *, int status);
137
138 /* one GPIO should be used to detect VBUS from the host */
139 static int is_vbus_present(void)
140 {
141 struct pxa2xx_udc_mach_info *mach = the_controller->mach;
142
143 if (mach->gpio_vbus) {
144 int value = gpio_get_value(mach->gpio_vbus);
145 return mach->gpio_vbus_inverted ? !value : value;
146 }
147 if (mach->udc_is_connected)
148 return mach->udc_is_connected();
149 return 1;
150 }
151
152 /* one GPIO should control a D+ pullup, so host sees this device (or not) */
153 static void pullup_off(void)
154 {
155 struct pxa2xx_udc_mach_info *mach = the_controller->mach;
156
157 if (mach->gpio_pullup)
158 gpio_set_value(mach->gpio_pullup, 0);
159 else if (mach->udc_command)
160 mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT);
161 }
162
163 static void pullup_on(void)
164 {
165 struct pxa2xx_udc_mach_info *mach = the_controller->mach;
166
167 if (mach->gpio_pullup)
168 gpio_set_value(mach->gpio_pullup, 1);
169 else if (mach->udc_command)
170 mach->udc_command(PXA2XX_UDC_CMD_CONNECT);
171 }
172
173 static void pio_irq_enable(int bEndpointAddress)
174 {
175 bEndpointAddress &= 0xf;
176 if (bEndpointAddress < 8)
177 UICR0 &= ~(1 << bEndpointAddress);
178 else {
179 bEndpointAddress -= 8;
180 UICR1 &= ~(1 << bEndpointAddress);
181 }
182 }
183
184 static void pio_irq_disable(int bEndpointAddress)
185 {
186 bEndpointAddress &= 0xf;
187 if (bEndpointAddress < 8)
188 UICR0 |= 1 << bEndpointAddress;
189 else {
190 bEndpointAddress -= 8;
191 UICR1 |= 1 << bEndpointAddress;
192 }
193 }
194
195 /* The UDCCR reg contains mask and interrupt status bits,
196 * so using '|=' isn't safe as it may ack an interrupt.
197 */
198 #define UDCCR_MASK_BITS (UDCCR_REM | UDCCR_SRM | UDCCR_UDE)
199
200 static inline void udc_set_mask_UDCCR(int mask)
201 {
202 UDCCR = (UDCCR & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS);
203 }
204
205 static inline void udc_clear_mask_UDCCR(int mask)
206 {
207 UDCCR = (UDCCR & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS);
208 }
209
210 static inline void udc_ack_int_UDCCR(int mask)
211 {
212 /* udccr contains the bits we dont want to change */
213 __u32 udccr = UDCCR & UDCCR_MASK_BITS;
214
215 UDCCR = udccr | (mask & ~UDCCR_MASK_BITS);
216 }
217
218 /*
219 * endpoint enable/disable
220 *
221 * we need to verify the descriptors used to enable endpoints. since pxa2xx
222 * endpoint configurations are fixed, and are pretty much always enabled,
223 * there's not a lot to manage here.
224 *
225 * because pxa2xx can't selectively initialize bulk (or interrupt) endpoints,
226 * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
227 * for a single interface (with only the default altsetting) and for gadget
228 * drivers that don't halt endpoints (not reset by set_interface). that also
229 * means that if you use ISO, you must violate the USB spec rule that all
230 * iso endpoints must be in non-default altsettings.
231 */
232 static int pxa2xx_ep_enable (struct usb_ep *_ep,
233 const struct usb_endpoint_descriptor *desc)
234 {
235 struct pxa2xx_ep *ep;
236 struct pxa2xx_udc *dev;
237
238 ep = container_of (_ep, struct pxa2xx_ep, ep);
239 if (!_ep || !desc || ep->desc || _ep->name == ep0name
240 || desc->bDescriptorType != USB_DT_ENDPOINT
241 || ep->bEndpointAddress != desc->bEndpointAddress
242 || ep->fifo_size < le16_to_cpu
243 (desc->wMaxPacketSize)) {
244 DMSG("%s, bad ep or descriptor\n", __func__);
245 return -EINVAL;
246 }
247
248 /* xfer types must match, except that interrupt ~= bulk */
249 if (ep->bmAttributes != desc->bmAttributes
250 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
251 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
252 DMSG("%s, %s type mismatch\n", __func__, _ep->name);
253 return -EINVAL;
254 }
255
256 /* hardware _could_ do smaller, but driver doesn't */
257 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
258 && le16_to_cpu (desc->wMaxPacketSize)
259 != BULK_FIFO_SIZE)
260 || !desc->wMaxPacketSize) {
261 DMSG("%s, bad %s maxpacket\n", __func__, _ep->name);
262 return -ERANGE;
263 }
264
265 dev = ep->dev;
266 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
267 DMSG("%s, bogus device state\n", __func__);
268 return -ESHUTDOWN;
269 }
270
271 ep->desc = desc;
272 ep->stopped = 0;
273 ep->pio_irqs = 0;
274 ep->ep.maxpacket = le16_to_cpu (desc->wMaxPacketSize);
275
276 /* flush fifo (mostly for OUT buffers) */
277 pxa2xx_ep_fifo_flush (_ep);
278
279 /* ... reset halt state too, if we could ... */
280
281 DBG(DBG_VERBOSE, "enabled %s\n", _ep->name);
282 return 0;
283 }
284
285 static int pxa2xx_ep_disable (struct usb_ep *_ep)
286 {
287 struct pxa2xx_ep *ep;
288 unsigned long flags;
289
290 ep = container_of (_ep, struct pxa2xx_ep, ep);
291 if (!_ep || !ep->desc) {
292 DMSG("%s, %s not enabled\n", __func__,
293 _ep ? ep->ep.name : NULL);
294 return -EINVAL;
295 }
296 local_irq_save(flags);
297
298 nuke (ep, -ESHUTDOWN);
299
300 /* flush fifo (mostly for IN buffers) */
301 pxa2xx_ep_fifo_flush (_ep);
302
303 ep->desc = NULL;
304 ep->stopped = 1;
305
306 local_irq_restore(flags);
307 DBG(DBG_VERBOSE, "%s disabled\n", _ep->name);
308 return 0;
309 }
310
311 /*-------------------------------------------------------------------------*/
312
313 /* for the pxa2xx, these can just wrap kmalloc/kfree. gadget drivers
314 * must still pass correctly initialized endpoints, since other controller
315 * drivers may care about how it's currently set up (dma issues etc).
316 */
317
318 /*
319 * pxa2xx_ep_alloc_request - allocate a request data structure
320 */
321 static struct usb_request *
322 pxa2xx_ep_alloc_request (struct usb_ep *_ep, gfp_t gfp_flags)
323 {
324 struct pxa2xx_request *req;
325
326 req = kzalloc(sizeof(*req), gfp_flags);
327 if (!req)
328 return NULL;
329
330 INIT_LIST_HEAD (&req->queue);
331 return &req->req;
332 }
333
334
335 /*
336 * pxa2xx_ep_free_request - deallocate a request data structure
337 */
338 static void
339 pxa2xx_ep_free_request (struct usb_ep *_ep, struct usb_request *_req)
340 {
341 struct pxa2xx_request *req;
342
343 req = container_of (_req, struct pxa2xx_request, req);
344 WARN_ON (!list_empty (&req->queue));
345 kfree(req);
346 }
347
348 /*-------------------------------------------------------------------------*/
349
350 /*
351 * done - retire a request; caller blocked irqs
352 */
353 static void done(struct pxa2xx_ep *ep, struct pxa2xx_request *req, int status)
354 {
355 unsigned stopped = ep->stopped;
356
357 list_del_init(&req->queue);
358
359 if (likely (req->req.status == -EINPROGRESS))
360 req->req.status = status;
361 else
362 status = req->req.status;
363
364 if (status && status != -ESHUTDOWN)
365 DBG(DBG_VERBOSE, "complete %s req %p stat %d len %u/%u\n",
366 ep->ep.name, &req->req, status,
367 req->req.actual, req->req.length);
368
369 /* don't modify queue heads during completion callback */
370 ep->stopped = 1;
371 req->req.complete(&ep->ep, &req->req);
372 ep->stopped = stopped;
373 }
374
375
376 static inline void ep0_idle (struct pxa2xx_udc *dev)
377 {
378 dev->ep0state = EP0_IDLE;
379 }
380
381 static int
382 write_packet(volatile u32 *uddr, struct pxa2xx_request *req, unsigned max)
383 {
384 u8 *buf;
385 unsigned length, count;
386
387 buf = req->req.buf + req->req.actual;
388 prefetch(buf);
389
390 /* how big will this packet be? */
391 length = min(req->req.length - req->req.actual, max);
392 req->req.actual += length;
393
394 count = length;
395 while (likely(count--))
396 *uddr = *buf++;
397
398 return length;
399 }
400
401 /*
402 * write to an IN endpoint fifo, as many packets as possible.
403 * irqs will use this to write the rest later.
404 * caller guarantees at least one packet buffer is ready (or a zlp).
405 */
406 static int
407 write_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
408 {
409 unsigned max;
410
411 max = le16_to_cpu(ep->desc->wMaxPacketSize);
412 do {
413 unsigned count;
414 int is_last, is_short;
415
416 count = write_packet(ep->reg_uddr, req, max);
417
418 /* last packet is usually short (or a zlp) */
419 if (unlikely (count != max))
420 is_last = is_short = 1;
421 else {
422 if (likely(req->req.length != req->req.actual)
423 || req->req.zero)
424 is_last = 0;
425 else
426 is_last = 1;
427 /* interrupt/iso maxpacket may not fill the fifo */
428 is_short = unlikely (max < ep->fifo_size);
429 }
430
431 DBG(DBG_VERY_NOISY, "wrote %s %d bytes%s%s %d left %p\n",
432 ep->ep.name, count,
433 is_last ? "/L" : "", is_short ? "/S" : "",
434 req->req.length - req->req.actual, req);
435
436 /* let loose that packet. maybe try writing another one,
437 * double buffering might work. TSP, TPC, and TFS
438 * bit values are the same for all normal IN endpoints.
439 */
440 *ep->reg_udccs = UDCCS_BI_TPC;
441 if (is_short)
442 *ep->reg_udccs = UDCCS_BI_TSP;
443
444 /* requests complete when all IN data is in the FIFO */
445 if (is_last) {
446 done (ep, req, 0);
447 if (list_empty(&ep->queue))
448 pio_irq_disable (ep->bEndpointAddress);
449 return 1;
450 }
451
452 // TODO experiment: how robust can fifo mode tweaking be?
453 // double buffering is off in the default fifo mode, which
454 // prevents TFS from being set here.
455
456 } while (*ep->reg_udccs & UDCCS_BI_TFS);
457 return 0;
458 }
459
460 /* caller asserts req->pending (ep0 irq status nyet cleared); starts
461 * ep0 data stage. these chips want very simple state transitions.
462 */
463 static inline
464 void ep0start(struct pxa2xx_udc *dev, u32 flags, const char *tag)
465 {
466 UDCCS0 = flags|UDCCS0_SA|UDCCS0_OPR;
467 USIR0 = USIR0_IR0;
468 dev->req_pending = 0;
469 DBG(DBG_VERY_NOISY, "%s %s, %02x/%02x\n",
470 __func__, tag, UDCCS0, flags);
471 }
472
473 static int
474 write_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
475 {
476 unsigned count;
477 int is_short;
478
479 count = write_packet(&UDDR0, req, EP0_FIFO_SIZE);
480 ep->dev->stats.write.bytes += count;
481
482 /* last packet "must be" short (or a zlp) */
483 is_short = (count != EP0_FIFO_SIZE);
484
485 DBG(DBG_VERY_NOISY, "ep0in %d bytes %d left %p\n", count,
486 req->req.length - req->req.actual, req);
487
488 if (unlikely (is_short)) {
489 if (ep->dev->req_pending)
490 ep0start(ep->dev, UDCCS0_IPR, "short IN");
491 else
492 UDCCS0 = UDCCS0_IPR;
493
494 count = req->req.length;
495 done (ep, req, 0);
496 ep0_idle(ep->dev);
497 #ifndef CONFIG_ARCH_IXP4XX
498 #if 1
499 /* This seems to get rid of lost status irqs in some cases:
500 * host responds quickly, or next request involves config
501 * change automagic, or should have been hidden, or ...
502 *
503 * FIXME get rid of all udelays possible...
504 */
505 if (count >= EP0_FIFO_SIZE) {
506 count = 100;
507 do {
508 if ((UDCCS0 & UDCCS0_OPR) != 0) {
509 /* clear OPR, generate ack */
510 UDCCS0 = UDCCS0_OPR;
511 break;
512 }
513 count--;
514 udelay(1);
515 } while (count);
516 }
517 #endif
518 #endif
519 } else if (ep->dev->req_pending)
520 ep0start(ep->dev, 0, "IN");
521 return is_short;
522 }
523
524
525 /*
526 * read_fifo - unload packet(s) from the fifo we use for usb OUT
527 * transfers and put them into the request. caller should have made
528 * sure there's at least one packet ready.
529 *
530 * returns true if the request completed because of short packet or the
531 * request buffer having filled (and maybe overran till end-of-packet).
532 */
533 static int
534 read_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
535 {
536 for (;;) {
537 u32 udccs;
538 u8 *buf;
539 unsigned bufferspace, count, is_short;
540
541 /* make sure there's a packet in the FIFO.
542 * UDCCS_{BO,IO}_RPC are all the same bit value.
543 * UDCCS_{BO,IO}_RNE are all the same bit value.
544 */
545 udccs = *ep->reg_udccs;
546 if (unlikely ((udccs & UDCCS_BO_RPC) == 0))
547 break;
548 buf = req->req.buf + req->req.actual;
549 prefetchw(buf);
550 bufferspace = req->req.length - req->req.actual;
551
552 /* read all bytes from this packet */
553 if (likely (udccs & UDCCS_BO_RNE)) {
554 count = 1 + (0x0ff & *ep->reg_ubcr);
555 req->req.actual += min (count, bufferspace);
556 } else /* zlp */
557 count = 0;
558 is_short = (count < ep->ep.maxpacket);
559 DBG(DBG_VERY_NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n",
560 ep->ep.name, udccs, count,
561 is_short ? "/S" : "",
562 req, req->req.actual, req->req.length);
563 while (likely (count-- != 0)) {
564 u8 byte = (u8) *ep->reg_uddr;
565
566 if (unlikely (bufferspace == 0)) {
567 /* this happens when the driver's buffer
568 * is smaller than what the host sent.
569 * discard the extra data.
570 */
571 if (req->req.status != -EOVERFLOW)
572 DMSG("%s overflow %d\n",
573 ep->ep.name, count);
574 req->req.status = -EOVERFLOW;
575 } else {
576 *buf++ = byte;
577 bufferspace--;
578 }
579 }
580 *ep->reg_udccs = UDCCS_BO_RPC;
581 /* RPC/RSP/RNE could now reflect the other packet buffer */
582
583 /* iso is one request per packet */
584 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
585 if (udccs & UDCCS_IO_ROF)
586 req->req.status = -EHOSTUNREACH;
587 /* more like "is_done" */
588 is_short = 1;
589 }
590
591 /* completion */
592 if (is_short || req->req.actual == req->req.length) {
593 done (ep, req, 0);
594 if (list_empty(&ep->queue))
595 pio_irq_disable (ep->bEndpointAddress);
596 return 1;
597 }
598
599 /* finished that packet. the next one may be waiting... */
600 }
601 return 0;
602 }
603
604 /*
605 * special ep0 version of the above. no UBCR0 or double buffering; status
606 * handshaking is magic. most device protocols don't need control-OUT.
607 * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other
608 * protocols do use them.
609 */
610 static int
611 read_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
612 {
613 u8 *buf, byte;
614 unsigned bufferspace;
615
616 buf = req->req.buf + req->req.actual;
617 bufferspace = req->req.length - req->req.actual;
618
619 while (UDCCS0 & UDCCS0_RNE) {
620 byte = (u8) UDDR0;
621
622 if (unlikely (bufferspace == 0)) {
623 /* this happens when the driver's buffer
624 * is smaller than what the host sent.
625 * discard the extra data.
626 */
627 if (req->req.status != -EOVERFLOW)
628 DMSG("%s overflow\n", ep->ep.name);
629 req->req.status = -EOVERFLOW;
630 } else {
631 *buf++ = byte;
632 req->req.actual++;
633 bufferspace--;
634 }
635 }
636
637 UDCCS0 = UDCCS0_OPR | UDCCS0_IPR;
638
639 /* completion */
640 if (req->req.actual >= req->req.length)
641 return 1;
642
643 /* finished that packet. the next one may be waiting... */
644 return 0;
645 }
646
647 /*-------------------------------------------------------------------------*/
648
649 static int
650 pxa2xx_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
651 {
652 struct pxa2xx_request *req;
653 struct pxa2xx_ep *ep;
654 struct pxa2xx_udc *dev;
655 unsigned long flags;
656
657 req = container_of(_req, struct pxa2xx_request, req);
658 if (unlikely (!_req || !_req->complete || !_req->buf
659 || !list_empty(&req->queue))) {
660 DMSG("%s, bad params\n", __func__);
661 return -EINVAL;
662 }
663
664 ep = container_of(_ep, struct pxa2xx_ep, ep);
665 if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
666 DMSG("%s, bad ep\n", __func__);
667 return -EINVAL;
668 }
669
670 dev = ep->dev;
671 if (unlikely (!dev->driver
672 || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
673 DMSG("%s, bogus device state\n", __func__);
674 return -ESHUTDOWN;
675 }
676
677 /* iso is always one packet per request, that's the only way
678 * we can report per-packet status. that also helps with dma.
679 */
680 if (unlikely (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
681 && req->req.length > le16_to_cpu
682 (ep->desc->wMaxPacketSize)))
683 return -EMSGSIZE;
684
685 DBG(DBG_NOISY, "%s queue req %p, len %d buf %p\n",
686 _ep->name, _req, _req->length, _req->buf);
687
688 local_irq_save(flags);
689
690 _req->status = -EINPROGRESS;
691 _req->actual = 0;
692
693 /* kickstart this i/o queue? */
694 if (list_empty(&ep->queue) && !ep->stopped) {
695 if (ep->desc == NULL/* ep0 */) {
696 unsigned length = _req->length;
697
698 switch (dev->ep0state) {
699 case EP0_IN_DATA_PHASE:
700 dev->stats.write.ops++;
701 if (write_ep0_fifo(ep, req))
702 req = NULL;
703 break;
704
705 case EP0_OUT_DATA_PHASE:
706 dev->stats.read.ops++;
707 /* messy ... */
708 if (dev->req_config) {
709 DBG(DBG_VERBOSE, "ep0 config ack%s\n",
710 dev->has_cfr ? "" : " raced");
711 if (dev->has_cfr)
712 UDCCFR = UDCCFR_AREN|UDCCFR_ACM
713 |UDCCFR_MB1;
714 done(ep, req, 0);
715 dev->ep0state = EP0_END_XFER;
716 local_irq_restore (flags);
717 return 0;
718 }
719 if (dev->req_pending)
720 ep0start(dev, UDCCS0_IPR, "OUT");
721 if (length == 0 || ((UDCCS0 & UDCCS0_RNE) != 0
722 && read_ep0_fifo(ep, req))) {
723 ep0_idle(dev);
724 done(ep, req, 0);
725 req = NULL;
726 }
727 break;
728
729 default:
730 DMSG("ep0 i/o, odd state %d\n", dev->ep0state);
731 local_irq_restore (flags);
732 return -EL2HLT;
733 }
734 /* can the FIFO can satisfy the request immediately? */
735 } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
736 if ((*ep->reg_udccs & UDCCS_BI_TFS) != 0
737 && write_fifo(ep, req))
738 req = NULL;
739 } else if ((*ep->reg_udccs & UDCCS_BO_RFS) != 0
740 && read_fifo(ep, req)) {
741 req = NULL;
742 }
743
744 if (likely (req && ep->desc))
745 pio_irq_enable(ep->bEndpointAddress);
746 }
747
748 /* pio or dma irq handler advances the queue. */
749 if (likely(req != NULL))
750 list_add_tail(&req->queue, &ep->queue);
751 local_irq_restore(flags);
752
753 return 0;
754 }
755
756
757 /*
758 * nuke - dequeue ALL requests
759 */
760 static void nuke(struct pxa2xx_ep *ep, int status)
761 {
762 struct pxa2xx_request *req;
763
764 /* called with irqs blocked */
765 while (!list_empty(&ep->queue)) {
766 req = list_entry(ep->queue.next,
767 struct pxa2xx_request,
768 queue);
769 done(ep, req, status);
770 }
771 if (ep->desc)
772 pio_irq_disable (ep->bEndpointAddress);
773 }
774
775
776 /* dequeue JUST ONE request */
777 static int pxa2xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
778 {
779 struct pxa2xx_ep *ep;
780 struct pxa2xx_request *req;
781 unsigned long flags;
782
783 ep = container_of(_ep, struct pxa2xx_ep, ep);
784 if (!_ep || ep->ep.name == ep0name)
785 return -EINVAL;
786
787 local_irq_save(flags);
788
789 /* make sure it's actually queued on this endpoint */
790 list_for_each_entry (req, &ep->queue, queue) {
791 if (&req->req == _req)
792 break;
793 }
794 if (&req->req != _req) {
795 local_irq_restore(flags);
796 return -EINVAL;
797 }
798
799 done(ep, req, -ECONNRESET);
800
801 local_irq_restore(flags);
802 return 0;
803 }
804
805 /*-------------------------------------------------------------------------*/
806
807 static int pxa2xx_ep_set_halt(struct usb_ep *_ep, int value)
808 {
809 struct pxa2xx_ep *ep;
810 unsigned long flags;
811
812 ep = container_of(_ep, struct pxa2xx_ep, ep);
813 if (unlikely (!_ep
814 || (!ep->desc && ep->ep.name != ep0name))
815 || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
816 DMSG("%s, bad ep\n", __func__);
817 return -EINVAL;
818 }
819 if (value == 0) {
820 /* this path (reset toggle+halt) is needed to implement
821 * SET_INTERFACE on normal hardware. but it can't be
822 * done from software on the PXA UDC, and the hardware
823 * forgets to do it as part of SET_INTERFACE automagic.
824 */
825 DMSG("only host can clear %s halt\n", _ep->name);
826 return -EROFS;
827 }
828
829 local_irq_save(flags);
830
831 if ((ep->bEndpointAddress & USB_DIR_IN) != 0
832 && ((*ep->reg_udccs & UDCCS_BI_TFS) == 0
833 || !list_empty(&ep->queue))) {
834 local_irq_restore(flags);
835 return -EAGAIN;
836 }
837
838 /* FST bit is the same for control, bulk in, bulk out, interrupt in */
839 *ep->reg_udccs = UDCCS_BI_FST|UDCCS_BI_FTF;
840
841 /* ep0 needs special care */
842 if (!ep->desc) {
843 start_watchdog(ep->dev);
844 ep->dev->req_pending = 0;
845 ep->dev->ep0state = EP0_STALL;
846
847 /* and bulk/intr endpoints like dropping stalls too */
848 } else {
849 unsigned i;
850 for (i = 0; i < 1000; i += 20) {
851 if (*ep->reg_udccs & UDCCS_BI_SST)
852 break;
853 udelay(20);
854 }
855 }
856 local_irq_restore(flags);
857
858 DBG(DBG_VERBOSE, "%s halt\n", _ep->name);
859 return 0;
860 }
861
862 static int pxa2xx_ep_fifo_status(struct usb_ep *_ep)
863 {
864 struct pxa2xx_ep *ep;
865
866 ep = container_of(_ep, struct pxa2xx_ep, ep);
867 if (!_ep) {
868 DMSG("%s, bad ep\n", __func__);
869 return -ENODEV;
870 }
871 /* pxa can't report unclaimed bytes from IN fifos */
872 if ((ep->bEndpointAddress & USB_DIR_IN) != 0)
873 return -EOPNOTSUPP;
874 if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN
875 || (*ep->reg_udccs & UDCCS_BO_RFS) == 0)
876 return 0;
877 else
878 return (*ep->reg_ubcr & 0xfff) + 1;
879 }
880
881 static void pxa2xx_ep_fifo_flush(struct usb_ep *_ep)
882 {
883 struct pxa2xx_ep *ep;
884
885 ep = container_of(_ep, struct pxa2xx_ep, ep);
886 if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) {
887 DMSG("%s, bad ep\n", __func__);
888 return;
889 }
890
891 /* toggle and halt bits stay unchanged */
892
893 /* for OUT, just read and discard the FIFO contents. */
894 if ((ep->bEndpointAddress & USB_DIR_IN) == 0) {
895 while (((*ep->reg_udccs) & UDCCS_BO_RNE) != 0)
896 (void) *ep->reg_uddr;
897 return;
898 }
899
900 /* most IN status is the same, but ISO can't stall */
901 *ep->reg_udccs = UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR
902 | (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
903 ? 0 : UDCCS_BI_SST;
904 }
905
906
907 static struct usb_ep_ops pxa2xx_ep_ops = {
908 .enable = pxa2xx_ep_enable,
909 .disable = pxa2xx_ep_disable,
910
911 .alloc_request = pxa2xx_ep_alloc_request,
912 .free_request = pxa2xx_ep_free_request,
913
914 .queue = pxa2xx_ep_queue,
915 .dequeue = pxa2xx_ep_dequeue,
916
917 .set_halt = pxa2xx_ep_set_halt,
918 .fifo_status = pxa2xx_ep_fifo_status,
919 .fifo_flush = pxa2xx_ep_fifo_flush,
920 };
921
922
923 /* ---------------------------------------------------------------------------
924 * device-scoped parts of the api to the usb controller hardware
925 * ---------------------------------------------------------------------------
926 */
927
928 static int pxa2xx_udc_get_frame(struct usb_gadget *_gadget)
929 {
930 return ((UFNRH & 0x07) << 8) | (UFNRL & 0xff);
931 }
932
933 static int pxa2xx_udc_wakeup(struct usb_gadget *_gadget)
934 {
935 /* host may not have enabled remote wakeup */
936 if ((UDCCS0 & UDCCS0_DRWF) == 0)
937 return -EHOSTUNREACH;
938 udc_set_mask_UDCCR(UDCCR_RSM);
939 return 0;
940 }
941
942 static void stop_activity(struct pxa2xx_udc *, struct usb_gadget_driver *);
943 static void udc_enable (struct pxa2xx_udc *);
944 static void udc_disable(struct pxa2xx_udc *);
945
946 /* We disable the UDC -- and its 48 MHz clock -- whenever it's not
947 * in active use.
948 */
949 static int pullup(struct pxa2xx_udc *udc)
950 {
951 int is_active = udc->vbus && udc->pullup && !udc->suspended;
952 DMSG("%s\n", is_active ? "active" : "inactive");
953 if (is_active) {
954 if (!udc->active) {
955 udc->active = 1;
956 /* Enable clock for USB device */
957 clk_enable(udc->clk);
958 udc_enable(udc);
959 }
960 } else {
961 if (udc->active) {
962 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
963 DMSG("disconnect %s\n", udc->driver
964 ? udc->driver->driver.name
965 : "(no driver)");
966 stop_activity(udc, udc->driver);
967 }
968 udc_disable(udc);
969 /* Disable clock for USB device */
970 clk_disable(udc->clk);
971 udc->active = 0;
972 }
973
974 }
975 return 0;
976 }
977
978 /* VBUS reporting logically comes from a transceiver */
979 static int pxa2xx_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
980 {
981 struct pxa2xx_udc *udc;
982
983 udc = container_of(_gadget, struct pxa2xx_udc, gadget);
984 udc->vbus = (is_active != 0);
985 DMSG("vbus %s\n", is_active ? "supplied" : "inactive");
986 pullup(udc);
987 return 0;
988 }
989
990 /* drivers may have software control over D+ pullup */
991 static int pxa2xx_udc_pullup(struct usb_gadget *_gadget, int is_active)
992 {
993 struct pxa2xx_udc *udc;
994
995 udc = container_of(_gadget, struct pxa2xx_udc, gadget);
996
997 /* not all boards support pullup control */
998 if (!udc->mach->gpio_pullup && !udc->mach->udc_command)
999 return -EOPNOTSUPP;
1000
1001 udc->pullup = (is_active != 0);
1002 pullup(udc);
1003 return 0;
1004 }
1005
1006 static const struct usb_gadget_ops pxa2xx_udc_ops = {
1007 .get_frame = pxa2xx_udc_get_frame,
1008 .wakeup = pxa2xx_udc_wakeup,
1009 .vbus_session = pxa2xx_udc_vbus_session,
1010 .pullup = pxa2xx_udc_pullup,
1011
1012 // .vbus_draw ... boards may consume current from VBUS, up to
1013 // 100-500mA based on config. the 500uA suspend ceiling means
1014 // that exclusively vbus-powered PXA designs violate USB specs.
1015 };
1016
1017 /*-------------------------------------------------------------------------*/
1018
1019 #ifdef CONFIG_USB_GADGET_DEBUG_FS
1020
1021 static int
1022 udc_seq_show(struct seq_file *m, void *_d)
1023 {
1024 struct pxa2xx_udc *dev = m->private;
1025 unsigned long flags;
1026 int i;
1027 u32 tmp;
1028
1029 local_irq_save(flags);
1030
1031 /* basic device status */
1032 seq_printf(m, DRIVER_DESC "\n"
1033 "%s version: %s\nGadget driver: %s\nHost %s\n\n",
1034 driver_name, DRIVER_VERSION SIZE_STR "(pio)",
1035 dev->driver ? dev->driver->driver.name : "(none)",
1036 is_vbus_present() ? "full speed" : "disconnected");
1037
1038 /* registers for device and ep0 */
1039 seq_printf(m,
1040 "uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
1041 UICR1, UICR0, USIR1, USIR0, UFNRH, UFNRL);
1042
1043 tmp = UDCCR;
1044 seq_printf(m,
1045 "udccr %02X =%s%s%s%s%s%s%s%s\n", tmp,
1046 (tmp & UDCCR_REM) ? " rem" : "",
1047 (tmp & UDCCR_RSTIR) ? " rstir" : "",
1048 (tmp & UDCCR_SRM) ? " srm" : "",
1049 (tmp & UDCCR_SUSIR) ? " susir" : "",
1050 (tmp & UDCCR_RESIR) ? " resir" : "",
1051 (tmp & UDCCR_RSM) ? " rsm" : "",
1052 (tmp & UDCCR_UDA) ? " uda" : "",
1053 (tmp & UDCCR_UDE) ? " ude" : "");
1054
1055 tmp = UDCCS0;
1056 seq_printf(m,
1057 "udccs0 %02X =%s%s%s%s%s%s%s%s\n", tmp,
1058 (tmp & UDCCS0_SA) ? " sa" : "",
1059 (tmp & UDCCS0_RNE) ? " rne" : "",
1060 (tmp & UDCCS0_FST) ? " fst" : "",
1061 (tmp & UDCCS0_SST) ? " sst" : "",
1062 (tmp & UDCCS0_DRWF) ? " dwrf" : "",
1063 (tmp & UDCCS0_FTF) ? " ftf" : "",
1064 (tmp & UDCCS0_IPR) ? " ipr" : "",
1065 (tmp & UDCCS0_OPR) ? " opr" : "");
1066
1067 if (dev->has_cfr) {
1068 tmp = UDCCFR;
1069 seq_printf(m,
1070 "udccfr %02X =%s%s\n", tmp,
1071 (tmp & UDCCFR_AREN) ? " aren" : "",
1072 (tmp & UDCCFR_ACM) ? " acm" : "");
1073 }
1074
1075 if (!is_vbus_present() || !dev->driver)
1076 goto done;
1077
1078 seq_printf(m, "ep0 IN %lu/%lu, OUT %lu/%lu\nirqs %lu\n\n",
1079 dev->stats.write.bytes, dev->stats.write.ops,
1080 dev->stats.read.bytes, dev->stats.read.ops,
1081 dev->stats.irqs);
1082
1083 /* dump endpoint queues */
1084 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1085 struct pxa2xx_ep *ep = &dev->ep [i];
1086 struct pxa2xx_request *req;
1087
1088 if (i != 0) {
1089 const struct usb_endpoint_descriptor *desc;
1090
1091 desc = ep->desc;
1092 if (!desc)
1093 continue;
1094 tmp = *dev->ep [i].reg_udccs;
1095 seq_printf(m,
1096 "%s max %d %s udccs %02x irqs %lu\n",
1097 ep->ep.name, le16_to_cpu(desc->wMaxPacketSize),
1098 "pio", tmp, ep->pio_irqs);
1099 /* TODO translate all five groups of udccs bits! */
1100
1101 } else /* ep0 should only have one transfer queued */
1102 seq_printf(m, "ep0 max 16 pio irqs %lu\n",
1103 ep->pio_irqs);
1104
1105 if (list_empty(&ep->queue)) {
1106 seq_printf(m, "\t(nothing queued)\n");
1107 continue;
1108 }
1109 list_for_each_entry(req, &ep->queue, queue) {
1110 seq_printf(m,
1111 "\treq %p len %d/%d buf %p\n",
1112 &req->req, req->req.actual,
1113 req->req.length, req->req.buf);
1114 }
1115 }
1116
1117 done:
1118 local_irq_restore(flags);
1119 return 0;
1120 }
1121
1122 static int
1123 udc_debugfs_open(struct inode *inode, struct file *file)
1124 {
1125 return single_open(file, udc_seq_show, inode->i_private);
1126 }
1127
1128 static const struct file_operations debug_fops = {
1129 .open = udc_debugfs_open,
1130 .read = seq_read,
1131 .llseek = seq_lseek,
1132 .release = single_release,
1133 .owner = THIS_MODULE,
1134 };
1135
1136 #define create_debug_files(dev) \
1137 do { \
1138 dev->debugfs_udc = debugfs_create_file(dev->gadget.name, \
1139 S_IRUGO, NULL, dev, &debug_fops); \
1140 } while (0)
1141 #define remove_debug_files(dev) \
1142 do { \
1143 if (dev->debugfs_udc) \
1144 debugfs_remove(dev->debugfs_udc); \
1145 } while (0)
1146
1147 #else /* !CONFIG_USB_GADGET_DEBUG_FILES */
1148
1149 #define create_debug_files(dev) do {} while (0)
1150 #define remove_debug_files(dev) do {} while (0)
1151
1152 #endif /* CONFIG_USB_GADGET_DEBUG_FILES */
1153
1154 /*-------------------------------------------------------------------------*/
1155
1156 /*
1157 * udc_disable - disable USB device controller
1158 */
1159 static void udc_disable(struct pxa2xx_udc *dev)
1160 {
1161 /* block all irqs */
1162 udc_set_mask_UDCCR(UDCCR_SRM|UDCCR_REM);
1163 UICR0 = UICR1 = 0xff;
1164 UFNRH = UFNRH_SIM;
1165
1166 /* if hardware supports it, disconnect from usb */
1167 pullup_off();
1168
1169 udc_clear_mask_UDCCR(UDCCR_UDE);
1170
1171 ep0_idle (dev);
1172 dev->gadget.speed = USB_SPEED_UNKNOWN;
1173 }
1174
1175
1176 /*
1177 * udc_reinit - initialize software state
1178 */
1179 static void udc_reinit(struct pxa2xx_udc *dev)
1180 {
1181 u32 i;
1182
1183 /* device/ep0 records init */
1184 INIT_LIST_HEAD (&dev->gadget.ep_list);
1185 INIT_LIST_HEAD (&dev->gadget.ep0->ep_list);
1186 dev->ep0state = EP0_IDLE;
1187
1188 /* basic endpoint records init */
1189 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1190 struct pxa2xx_ep *ep = &dev->ep[i];
1191
1192 if (i != 0)
1193 list_add_tail (&ep->ep.ep_list, &dev->gadget.ep_list);
1194
1195 ep->desc = NULL;
1196 ep->stopped = 0;
1197 INIT_LIST_HEAD (&ep->queue);
1198 ep->pio_irqs = 0;
1199 }
1200
1201 /* the rest was statically initialized, and is read-only */
1202 }
1203
1204 /* until it's enabled, this UDC should be completely invisible
1205 * to any USB host.
1206 */
1207 static void udc_enable (struct pxa2xx_udc *dev)
1208 {
1209 udc_clear_mask_UDCCR(UDCCR_UDE);
1210
1211 /* try to clear these bits before we enable the udc */
1212 udc_ack_int_UDCCR(UDCCR_SUSIR|/*UDCCR_RSTIR|*/UDCCR_RESIR);
1213
1214 ep0_idle(dev);
1215 dev->gadget.speed = USB_SPEED_UNKNOWN;
1216 dev->stats.irqs = 0;
1217
1218 /*
1219 * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual:
1220 * - enable UDC
1221 * - if RESET is already in progress, ack interrupt
1222 * - unmask reset interrupt
1223 */
1224 udc_set_mask_UDCCR(UDCCR_UDE);
1225 if (!(UDCCR & UDCCR_UDA))
1226 udc_ack_int_UDCCR(UDCCR_RSTIR);
1227
1228 if (dev->has_cfr /* UDC_RES2 is defined */) {
1229 /* pxa255 (a0+) can avoid a set_config race that could
1230 * prevent gadget drivers from configuring correctly
1231 */
1232 UDCCFR = UDCCFR_ACM | UDCCFR_MB1;
1233 } else {
1234 /* "USB test mode" for pxa250 errata 40-42 (stepping a0, a1)
1235 * which could result in missing packets and interrupts.
1236 * supposedly one bit per endpoint, controlling whether it
1237 * double buffers or not; ACM/AREN bits fit into the holes.
1238 * zero bits (like USIR0_IRx) disable double buffering.
1239 */
1240 UDC_RES1 = 0x00;
1241 UDC_RES2 = 0x00;
1242 }
1243
1244 /* enable suspend/resume and reset irqs */
1245 udc_clear_mask_UDCCR(UDCCR_SRM | UDCCR_REM);
1246
1247 /* enable ep0 irqs */
1248 UICR0 &= ~UICR0_IM0;
1249
1250 /* if hardware supports it, pullup D+ and wait for reset */
1251 pullup_on();
1252 }
1253
1254
1255 /* when a driver is successfully registered, it will receive
1256 * control requests including set_configuration(), which enables
1257 * non-control requests. then usb traffic follows until a
1258 * disconnect is reported. then a host may connect again, or
1259 * the driver might get unbound.
1260 */
1261 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1262 {
1263 struct pxa2xx_udc *dev = the_controller;
1264 int retval;
1265
1266 if (!driver
1267 || driver->speed < USB_SPEED_FULL
1268 || !driver->bind
1269 || !driver->disconnect
1270 || !driver->setup)
1271 return -EINVAL;
1272 if (!dev)
1273 return -ENODEV;
1274 if (dev->driver)
1275 return -EBUSY;
1276
1277 /* first hook up the driver ... */
1278 dev->driver = driver;
1279 dev->gadget.dev.driver = &driver->driver;
1280 dev->pullup = 1;
1281
1282 retval = device_add (&dev->gadget.dev);
1283 if (retval) {
1284 fail:
1285 dev->driver = NULL;
1286 dev->gadget.dev.driver = NULL;
1287 return retval;
1288 }
1289 retval = driver->bind(&dev->gadget);
1290 if (retval) {
1291 DMSG("bind to driver %s --> error %d\n",
1292 driver->driver.name, retval);
1293 device_del (&dev->gadget.dev);
1294 goto fail;
1295 }
1296
1297 /* ... then enable host detection and ep0; and we're ready
1298 * for set_configuration as well as eventual disconnect.
1299 */
1300 DMSG("registered gadget driver '%s'\n", driver->driver.name);
1301 pullup(dev);
1302 dump_state(dev);
1303 return 0;
1304 }
1305 EXPORT_SYMBOL(usb_gadget_register_driver);
1306
1307 static void
1308 stop_activity(struct pxa2xx_udc *dev, struct usb_gadget_driver *driver)
1309 {
1310 int i;
1311
1312 /* don't disconnect drivers more than once */
1313 if (dev->gadget.speed == USB_SPEED_UNKNOWN)
1314 driver = NULL;
1315 dev->gadget.speed = USB_SPEED_UNKNOWN;
1316
1317 /* prevent new request submissions, kill any outstanding requests */
1318 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1319 struct pxa2xx_ep *ep = &dev->ep[i];
1320
1321 ep->stopped = 1;
1322 nuke(ep, -ESHUTDOWN);
1323 }
1324 del_timer_sync(&dev->timer);
1325
1326 /* report disconnect; the driver is already quiesced */
1327 if (driver)
1328 driver->disconnect(&dev->gadget);
1329
1330 /* re-init driver-visible data structures */
1331 udc_reinit(dev);
1332 }
1333
1334 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1335 {
1336 struct pxa2xx_udc *dev = the_controller;
1337
1338 if (!dev)
1339 return -ENODEV;
1340 if (!driver || driver != dev->driver || !driver->unbind)
1341 return -EINVAL;
1342
1343 local_irq_disable();
1344 dev->pullup = 0;
1345 pullup(dev);
1346 stop_activity(dev, driver);
1347 local_irq_enable();
1348
1349 driver->unbind(&dev->gadget);
1350 dev->gadget.dev.driver = NULL;
1351 dev->driver = NULL;
1352
1353 device_del (&dev->gadget.dev);
1354
1355 DMSG("unregistered gadget driver '%s'\n", driver->driver.name);
1356 dump_state(dev);
1357 return 0;
1358 }
1359 EXPORT_SYMBOL(usb_gadget_unregister_driver);
1360
1361
1362 /*-------------------------------------------------------------------------*/
1363
1364 #ifdef CONFIG_ARCH_LUBBOCK
1365
1366 /* Lubbock has separate connect and disconnect irqs. More typical designs
1367 * use one GPIO as the VBUS IRQ, and another to control the D+ pullup.
1368 */
1369
1370 static irqreturn_t
1371 lubbock_vbus_irq(int irq, void *_dev)
1372 {
1373 struct pxa2xx_udc *dev = _dev;
1374 int vbus;
1375
1376 dev->stats.irqs++;
1377 switch (irq) {
1378 case LUBBOCK_USB_IRQ:
1379 vbus = 1;
1380 disable_irq(LUBBOCK_USB_IRQ);
1381 enable_irq(LUBBOCK_USB_DISC_IRQ);
1382 break;
1383 case LUBBOCK_USB_DISC_IRQ:
1384 vbus = 0;
1385 disable_irq(LUBBOCK_USB_DISC_IRQ);
1386 enable_irq(LUBBOCK_USB_IRQ);
1387 break;
1388 default:
1389 return IRQ_NONE;
1390 }
1391
1392 pxa2xx_udc_vbus_session(&dev->gadget, vbus);
1393 return IRQ_HANDLED;
1394 }
1395
1396 #endif
1397
1398 static irqreturn_t udc_vbus_irq(int irq, void *_dev)
1399 {
1400 struct pxa2xx_udc *dev = _dev;
1401 int vbus = gpio_get_value(dev->mach->gpio_vbus);
1402
1403 if (dev->mach->gpio_vbus_inverted)
1404 vbus = !vbus;
1405
1406 pxa2xx_udc_vbus_session(&dev->gadget, vbus);
1407 return IRQ_HANDLED;
1408 }
1409
1410
1411 /*-------------------------------------------------------------------------*/
1412
1413 static inline void clear_ep_state (struct pxa2xx_udc *dev)
1414 {
1415 unsigned i;
1416
1417 /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
1418 * fifos, and pending transactions mustn't be continued in any case.
1419 */
1420 for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++)
1421 nuke(&dev->ep[i], -ECONNABORTED);
1422 }
1423
1424 static void udc_watchdog(unsigned long _dev)
1425 {
1426 struct pxa2xx_udc *dev = (void *)_dev;
1427
1428 local_irq_disable();
1429 if (dev->ep0state == EP0_STALL
1430 && (UDCCS0 & UDCCS0_FST) == 0
1431 && (UDCCS0 & UDCCS0_SST) == 0) {
1432 UDCCS0 = UDCCS0_FST|UDCCS0_FTF;
1433 DBG(DBG_VERBOSE, "ep0 re-stall\n");
1434 start_watchdog(dev);
1435 }
1436 local_irq_enable();
1437 }
1438
1439 static void handle_ep0 (struct pxa2xx_udc *dev)
1440 {
1441 u32 udccs0 = UDCCS0;
1442 struct pxa2xx_ep *ep = &dev->ep [0];
1443 struct pxa2xx_request *req;
1444 union {
1445 struct usb_ctrlrequest r;
1446 u8 raw [8];
1447 u32 word [2];
1448 } u;
1449
1450 if (list_empty(&ep->queue))
1451 req = NULL;
1452 else
1453 req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
1454
1455 /* clear stall status */
1456 if (udccs0 & UDCCS0_SST) {
1457 nuke(ep, -EPIPE);
1458 UDCCS0 = UDCCS0_SST;
1459 del_timer(&dev->timer);
1460 ep0_idle(dev);
1461 }
1462
1463 /* previous request unfinished? non-error iff back-to-back ... */
1464 if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) {
1465 nuke(ep, 0);
1466 del_timer(&dev->timer);
1467 ep0_idle(dev);
1468 }
1469
1470 switch (dev->ep0state) {
1471 case EP0_IDLE:
1472 /* late-breaking status? */
1473 udccs0 = UDCCS0;
1474
1475 /* start control request? */
1476 if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))
1477 == (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) {
1478 int i;
1479
1480 nuke (ep, -EPROTO);
1481
1482 /* read SETUP packet */
1483 for (i = 0; i < 8; i++) {
1484 if (unlikely(!(UDCCS0 & UDCCS0_RNE))) {
1485 bad_setup:
1486 DMSG("SETUP %d!\n", i);
1487 goto stall;
1488 }
1489 u.raw [i] = (u8) UDDR0;
1490 }
1491 if (unlikely((UDCCS0 & UDCCS0_RNE) != 0))
1492 goto bad_setup;
1493
1494 got_setup:
1495 DBG(DBG_VERBOSE, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1496 u.r.bRequestType, u.r.bRequest,
1497 le16_to_cpu(u.r.wValue),
1498 le16_to_cpu(u.r.wIndex),
1499 le16_to_cpu(u.r.wLength));
1500
1501 /* cope with automagic for some standard requests. */
1502 dev->req_std = (u.r.bRequestType & USB_TYPE_MASK)
1503 == USB_TYPE_STANDARD;
1504 dev->req_config = 0;
1505 dev->req_pending = 1;
1506 switch (u.r.bRequest) {
1507 /* hardware restricts gadget drivers here! */
1508 case USB_REQ_SET_CONFIGURATION:
1509 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1510 /* reflect hardware's automagic
1511 * up to the gadget driver.
1512 */
1513 config_change:
1514 dev->req_config = 1;
1515 clear_ep_state(dev);
1516 /* if !has_cfr, there's no synch
1517 * else use AREN (later) not SA|OPR
1518 * USIR0_IR0 acts edge sensitive
1519 */
1520 }
1521 break;
1522 /* ... and here, even more ... */
1523 case USB_REQ_SET_INTERFACE:
1524 if (u.r.bRequestType == USB_RECIP_INTERFACE) {
1525 /* udc hardware is broken by design:
1526 * - altsetting may only be zero;
1527 * - hw resets all interfaces' eps;
1528 * - ep reset doesn't include halt(?).
1529 */
1530 DMSG("broken set_interface (%d/%d)\n",
1531 le16_to_cpu(u.r.wIndex),
1532 le16_to_cpu(u.r.wValue));
1533 goto config_change;
1534 }
1535 break;
1536 /* hardware was supposed to hide this */
1537 case USB_REQ_SET_ADDRESS:
1538 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1539 ep0start(dev, 0, "address");
1540 return;
1541 }
1542 break;
1543 }
1544
1545 if (u.r.bRequestType & USB_DIR_IN)
1546 dev->ep0state = EP0_IN_DATA_PHASE;
1547 else
1548 dev->ep0state = EP0_OUT_DATA_PHASE;
1549
1550 i = dev->driver->setup(&dev->gadget, &u.r);
1551 if (i < 0) {
1552 /* hardware automagic preventing STALL... */
1553 if (dev->req_config) {
1554 /* hardware sometimes neglects to tell
1555 * tell us about config change events,
1556 * so later ones may fail...
1557 */
1558 WARN("config change %02x fail %d?\n",
1559 u.r.bRequest, i);
1560 return;
1561 /* TODO experiment: if has_cfr,
1562 * hardware didn't ACK; maybe we
1563 * could actually STALL!
1564 */
1565 }
1566 DBG(DBG_VERBOSE, "protocol STALL, "
1567 "%02x err %d\n", UDCCS0, i);
1568 stall:
1569 /* the watchdog timer helps deal with cases
1570 * where udc seems to clear FST wrongly, and
1571 * then NAKs instead of STALLing.
1572 */
1573 ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall");
1574 start_watchdog(dev);
1575 dev->ep0state = EP0_STALL;
1576
1577 /* deferred i/o == no response yet */
1578 } else if (dev->req_pending) {
1579 if (likely(dev->ep0state == EP0_IN_DATA_PHASE
1580 || dev->req_std || u.r.wLength))
1581 ep0start(dev, 0, "defer");
1582 else
1583 ep0start(dev, UDCCS0_IPR, "defer/IPR");
1584 }
1585
1586 /* expect at least one data or status stage irq */
1587 return;
1588
1589 } else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA))
1590 == (UDCCS0_OPR|UDCCS0_SA))) {
1591 unsigned i;
1592
1593 /* pxa210/250 erratum 131 for B0/B1 says RNE lies.
1594 * still observed on a pxa255 a0.
1595 */
1596 DBG(DBG_VERBOSE, "e131\n");
1597 nuke(ep, -EPROTO);
1598
1599 /* read SETUP data, but don't trust it too much */
1600 for (i = 0; i < 8; i++)
1601 u.raw [i] = (u8) UDDR0;
1602 if ((u.r.bRequestType & USB_RECIP_MASK)
1603 > USB_RECIP_OTHER)
1604 goto stall;
1605 if (u.word [0] == 0 && u.word [1] == 0)
1606 goto stall;
1607 goto got_setup;
1608 } else {
1609 /* some random early IRQ:
1610 * - we acked FST
1611 * - IPR cleared
1612 * - OPR got set, without SA (likely status stage)
1613 */
1614 UDCCS0 = udccs0 & (UDCCS0_SA|UDCCS0_OPR);
1615 }
1616 break;
1617 case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */
1618 if (udccs0 & UDCCS0_OPR) {
1619 UDCCS0 = UDCCS0_OPR|UDCCS0_FTF;
1620 DBG(DBG_VERBOSE, "ep0in premature status\n");
1621 if (req)
1622 done(ep, req, 0);
1623 ep0_idle(dev);
1624 } else /* irq was IPR clearing */ {
1625 if (req) {
1626 /* this IN packet might finish the request */
1627 (void) write_ep0_fifo(ep, req);
1628 } /* else IN token before response was written */
1629 }
1630 break;
1631 case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */
1632 if (udccs0 & UDCCS0_OPR) {
1633 if (req) {
1634 /* this OUT packet might finish the request */
1635 if (read_ep0_fifo(ep, req))
1636 done(ep, req, 0);
1637 /* else more OUT packets expected */
1638 } /* else OUT token before read was issued */
1639 } else /* irq was IPR clearing */ {
1640 DBG(DBG_VERBOSE, "ep0out premature status\n");
1641 if (req)
1642 done(ep, req, 0);
1643 ep0_idle(dev);
1644 }
1645 break;
1646 case EP0_END_XFER:
1647 if (req)
1648 done(ep, req, 0);
1649 /* ack control-IN status (maybe in-zlp was skipped)
1650 * also appears after some config change events.
1651 */
1652 if (udccs0 & UDCCS0_OPR)
1653 UDCCS0 = UDCCS0_OPR;
1654 ep0_idle(dev);
1655 break;
1656 case EP0_STALL:
1657 UDCCS0 = UDCCS0_FST;
1658 break;
1659 }
1660 USIR0 = USIR0_IR0;
1661 }
1662
1663 static void handle_ep(struct pxa2xx_ep *ep)
1664 {
1665 struct pxa2xx_request *req;
1666 int is_in = ep->bEndpointAddress & USB_DIR_IN;
1667 int completed;
1668 u32 udccs, tmp;
1669
1670 do {
1671 completed = 0;
1672 if (likely (!list_empty(&ep->queue)))
1673 req = list_entry(ep->queue.next,
1674 struct pxa2xx_request, queue);
1675 else
1676 req = NULL;
1677
1678 // TODO check FST handling
1679
1680 udccs = *ep->reg_udccs;
1681 if (unlikely(is_in)) { /* irq from TPC, SST, or (ISO) TUR */
1682 tmp = UDCCS_BI_TUR;
1683 if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1684 tmp |= UDCCS_BI_SST;
1685 tmp &= udccs;
1686 if (likely (tmp))
1687 *ep->reg_udccs = tmp;
1688 if (req && likely ((udccs & UDCCS_BI_TFS) != 0))
1689 completed = write_fifo(ep, req);
1690
1691 } else { /* irq from RPC (or for ISO, ROF) */
1692 if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1693 tmp = UDCCS_BO_SST | UDCCS_BO_DME;
1694 else
1695 tmp = UDCCS_IO_ROF | UDCCS_IO_DME;
1696 tmp &= udccs;
1697 if (likely(tmp))
1698 *ep->reg_udccs = tmp;
1699
1700 /* fifos can hold packets, ready for reading... */
1701 if (likely(req)) {
1702 completed = read_fifo(ep, req);
1703 } else
1704 pio_irq_disable (ep->bEndpointAddress);
1705 }
1706 ep->pio_irqs++;
1707 } while (completed);
1708 }
1709
1710 /*
1711 * pxa2xx_udc_irq - interrupt handler
1712 *
1713 * avoid delays in ep0 processing. the control handshaking isn't always
1714 * under software control (pxa250c0 and the pxa255 are better), and delays
1715 * could cause usb protocol errors.
1716 */
1717 static irqreturn_t
1718 pxa2xx_udc_irq(int irq, void *_dev)
1719 {
1720 struct pxa2xx_udc *dev = _dev;
1721 int handled;
1722
1723 dev->stats.irqs++;
1724 do {
1725 u32 udccr = UDCCR;
1726
1727 handled = 0;
1728
1729 /* SUSpend Interrupt Request */
1730 if (unlikely(udccr & UDCCR_SUSIR)) {
1731 udc_ack_int_UDCCR(UDCCR_SUSIR);
1732 handled = 1;
1733 DBG(DBG_VERBOSE, "USB suspend%s\n", is_vbus_present()
1734 ? "" : "+disconnect");
1735
1736 if (!is_vbus_present())
1737 stop_activity(dev, dev->driver);
1738 else if (dev->gadget.speed != USB_SPEED_UNKNOWN
1739 && dev->driver
1740 && dev->driver->suspend)
1741 dev->driver->suspend(&dev->gadget);
1742 ep0_idle (dev);
1743 }
1744
1745 /* RESume Interrupt Request */
1746 if (unlikely(udccr & UDCCR_RESIR)) {
1747 udc_ack_int_UDCCR(UDCCR_RESIR);
1748 handled = 1;
1749 DBG(DBG_VERBOSE, "USB resume\n");
1750
1751 if (dev->gadget.speed != USB_SPEED_UNKNOWN
1752 && dev->driver
1753 && dev->driver->resume
1754 && is_vbus_present())
1755 dev->driver->resume(&dev->gadget);
1756 }
1757
1758 /* ReSeT Interrupt Request - USB reset */
1759 if (unlikely(udccr & UDCCR_RSTIR)) {
1760 udc_ack_int_UDCCR(UDCCR_RSTIR);
1761 handled = 1;
1762
1763 if ((UDCCR & UDCCR_UDA) == 0) {
1764 DBG(DBG_VERBOSE, "USB reset start\n");
1765
1766 /* reset driver and endpoints,
1767 * in case that's not yet done
1768 */
1769 stop_activity (dev, dev->driver);
1770
1771 } else {
1772 DBG(DBG_VERBOSE, "USB reset end\n");
1773 dev->gadget.speed = USB_SPEED_FULL;
1774 memset(&dev->stats, 0, sizeof dev->stats);
1775 /* driver and endpoints are still reset */
1776 }
1777
1778 } else {
1779 u32 usir0 = USIR0 & ~UICR0;
1780 u32 usir1 = USIR1 & ~UICR1;
1781 int i;
1782
1783 if (unlikely (!usir0 && !usir1))
1784 continue;
1785
1786 DBG(DBG_VERY_NOISY, "irq %02x.%02x\n", usir1, usir0);
1787
1788 /* control traffic */
1789 if (usir0 & USIR0_IR0) {
1790 dev->ep[0].pio_irqs++;
1791 handle_ep0(dev);
1792 handled = 1;
1793 }
1794
1795 /* endpoint data transfers */
1796 for (i = 0; i < 8; i++) {
1797 u32 tmp = 1 << i;
1798
1799 if (i && (usir0 & tmp)) {
1800 handle_ep(&dev->ep[i]);
1801 USIR0 |= tmp;
1802 handled = 1;
1803 }
1804 if (usir1 & tmp) {
1805 handle_ep(&dev->ep[i+8]);
1806 USIR1 |= tmp;
1807 handled = 1;
1808 }
1809 }
1810 }
1811
1812 /* we could also ask for 1 msec SOF (SIR) interrupts */
1813
1814 } while (handled);
1815 return IRQ_HANDLED;
1816 }
1817
1818 /*-------------------------------------------------------------------------*/
1819
1820 static void nop_release (struct device *dev)
1821 {
1822 DMSG("%s %s\n", __func__, dev->bus_id);
1823 }
1824
1825 /* this uses load-time allocation and initialization (instead of
1826 * doing it at run-time) to save code, eliminate fault paths, and
1827 * be more obviously correct.
1828 */
1829 static struct pxa2xx_udc memory = {
1830 .gadget = {
1831 .ops = &pxa2xx_udc_ops,
1832 .ep0 = &memory.ep[0].ep,
1833 .name = driver_name,
1834 .dev = {
1835 .bus_id = "gadget",
1836 .release = nop_release,
1837 },
1838 },
1839
1840 /* control endpoint */
1841 .ep[0] = {
1842 .ep = {
1843 .name = ep0name,
1844 .ops = &pxa2xx_ep_ops,
1845 .maxpacket = EP0_FIFO_SIZE,
1846 },
1847 .dev = &memory,
1848 .reg_udccs = &UDCCS0,
1849 .reg_uddr = &UDDR0,
1850 },
1851
1852 /* first group of endpoints */
1853 .ep[1] = {
1854 .ep = {
1855 .name = "ep1in-bulk",
1856 .ops = &pxa2xx_ep_ops,
1857 .maxpacket = BULK_FIFO_SIZE,
1858 },
1859 .dev = &memory,
1860 .fifo_size = BULK_FIFO_SIZE,
1861 .bEndpointAddress = USB_DIR_IN | 1,
1862 .bmAttributes = USB_ENDPOINT_XFER_BULK,
1863 .reg_udccs = &UDCCS1,
1864 .reg_uddr = &UDDR1,
1865 },
1866 .ep[2] = {
1867 .ep = {
1868 .name = "ep2out-bulk",
1869 .ops = &pxa2xx_ep_ops,
1870 .maxpacket = BULK_FIFO_SIZE,
1871 },
1872 .dev = &memory,
1873 .fifo_size = BULK_FIFO_SIZE,
1874 .bEndpointAddress = 2,
1875 .bmAttributes = USB_ENDPOINT_XFER_BULK,
1876 .reg_udccs = &UDCCS2,
1877 .reg_ubcr = &UBCR2,
1878 .reg_uddr = &UDDR2,
1879 },
1880 #ifndef CONFIG_USB_PXA2XX_SMALL
1881 .ep[3] = {
1882 .ep = {
1883 .name = "ep3in-iso",
1884 .ops = &pxa2xx_ep_ops,
1885 .maxpacket = ISO_FIFO_SIZE,
1886 },
1887 .dev = &memory,
1888 .fifo_size = ISO_FIFO_SIZE,
1889 .bEndpointAddress = USB_DIR_IN | 3,
1890 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
1891 .reg_udccs = &UDCCS3,
1892 .reg_uddr = &UDDR3,
1893 },
1894 .ep[4] = {
1895 .ep = {
1896 .name = "ep4out-iso",
1897 .ops = &pxa2xx_ep_ops,
1898 .maxpacket = ISO_FIFO_SIZE,
1899 },
1900 .dev = &memory,
1901 .fifo_size = ISO_FIFO_SIZE,
1902 .bEndpointAddress = 4,
1903 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
1904 .reg_udccs = &UDCCS4,
1905 .reg_ubcr = &UBCR4,
1906 .reg_uddr = &UDDR4,
1907 },
1908 .ep[5] = {
1909 .ep = {
1910 .name = "ep5in-int",
1911 .ops = &pxa2xx_ep_ops,
1912 .maxpacket = INT_FIFO_SIZE,
1913 },
1914 .dev = &memory,
1915 .fifo_size = INT_FIFO_SIZE,
1916 .bEndpointAddress = USB_DIR_IN | 5,
1917 .bmAttributes = USB_ENDPOINT_XFER_INT,
1918 .reg_udccs = &UDCCS5,
1919 .reg_uddr = &UDDR5,
1920 },
1921
1922 /* second group of endpoints */
1923 .ep[6] = {
1924 .ep = {
1925 .name = "ep6in-bulk",
1926 .ops = &pxa2xx_ep_ops,
1927 .maxpacket = BULK_FIFO_SIZE,
1928 },
1929 .dev = &memory,
1930 .fifo_size = BULK_FIFO_SIZE,
1931 .bEndpointAddress = USB_DIR_IN | 6,
1932 .bmAttributes = USB_ENDPOINT_XFER_BULK,
1933 .reg_udccs = &UDCCS6,
1934 .reg_uddr = &UDDR6,
1935 },
1936 .ep[7] = {
1937 .ep = {
1938 .name = "ep7out-bulk",
1939 .ops = &pxa2xx_ep_ops,
1940 .maxpacket = BULK_FIFO_SIZE,
1941 },
1942 .dev = &memory,
1943 .fifo_size = BULK_FIFO_SIZE,
1944 .bEndpointAddress = 7,
1945 .bmAttributes = USB_ENDPOINT_XFER_BULK,
1946 .reg_udccs = &UDCCS7,
1947 .reg_ubcr = &UBCR7,
1948 .reg_uddr = &UDDR7,
1949 },
1950 .ep[8] = {
1951 .ep = {
1952 .name = "ep8in-iso",
1953 .ops = &pxa2xx_ep_ops,
1954 .maxpacket = ISO_FIFO_SIZE,
1955 },
1956 .dev = &memory,
1957 .fifo_size = ISO_FIFO_SIZE,
1958 .bEndpointAddress = USB_DIR_IN | 8,
1959 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
1960 .reg_udccs = &UDCCS8,
1961 .reg_uddr = &UDDR8,
1962 },
1963 .ep[9] = {
1964 .ep = {
1965 .name = "ep9out-iso",
1966 .ops = &pxa2xx_ep_ops,
1967 .maxpacket = ISO_FIFO_SIZE,
1968 },
1969 .dev = &memory,
1970 .fifo_size = ISO_FIFO_SIZE,
1971 .bEndpointAddress = 9,
1972 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
1973 .reg_udccs = &UDCCS9,
1974 .reg_ubcr = &UBCR9,
1975 .reg_uddr = &UDDR9,
1976 },
1977 .ep[10] = {
1978 .ep = {
1979 .name = "ep10in-int",
1980 .ops = &pxa2xx_ep_ops,
1981 .maxpacket = INT_FIFO_SIZE,
1982 },
1983 .dev = &memory,
1984 .fifo_size = INT_FIFO_SIZE,
1985 .bEndpointAddress = USB_DIR_IN | 10,
1986 .bmAttributes = USB_ENDPOINT_XFER_INT,
1987 .reg_udccs = &UDCCS10,
1988 .reg_uddr = &UDDR10,
1989 },
1990
1991 /* third group of endpoints */
1992 .ep[11] = {
1993 .ep = {
1994 .name = "ep11in-bulk",
1995 .ops = &pxa2xx_ep_ops,
1996 .maxpacket = BULK_FIFO_SIZE,
1997 },
1998 .dev = &memory,
1999 .fifo_size = BULK_FIFO_SIZE,
2000 .bEndpointAddress = USB_DIR_IN | 11,
2001 .bmAttributes = USB_ENDPOINT_XFER_BULK,
2002 .reg_udccs = &UDCCS11,
2003 .reg_uddr = &UDDR11,
2004 },
2005 .ep[12] = {
2006 .ep = {
2007 .name = "ep12out-bulk",
2008 .ops = &pxa2xx_ep_ops,
2009 .maxpacket = BULK_FIFO_SIZE,
2010 },
2011 .dev = &memory,
2012 .fifo_size = BULK_FIFO_SIZE,
2013 .bEndpointAddress = 12,
2014 .bmAttributes = USB_ENDPOINT_XFER_BULK,
2015 .reg_udccs = &UDCCS12,
2016 .reg_ubcr = &UBCR12,
2017 .reg_uddr = &UDDR12,
2018 },
2019 .ep[13] = {
2020 .ep = {
2021 .name = "ep13in-iso",
2022 .ops = &pxa2xx_ep_ops,
2023 .maxpacket = ISO_FIFO_SIZE,
2024 },
2025 .dev = &memory,
2026 .fifo_size = ISO_FIFO_SIZE,
2027 .bEndpointAddress = USB_DIR_IN | 13,
2028 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
2029 .reg_udccs = &UDCCS13,
2030 .reg_uddr = &UDDR13,
2031 },
2032 .ep[14] = {
2033 .ep = {
2034 .name = "ep14out-iso",
2035 .ops = &pxa2xx_ep_ops,
2036 .maxpacket = ISO_FIFO_SIZE,
2037 },
2038 .dev = &memory,
2039 .fifo_size = ISO_FIFO_SIZE,
2040 .bEndpointAddress = 14,
2041 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
2042 .reg_udccs = &UDCCS14,
2043 .reg_ubcr = &UBCR14,
2044 .reg_uddr = &UDDR14,
2045 },
2046 .ep[15] = {
2047 .ep = {
2048 .name = "ep15in-int",
2049 .ops = &pxa2xx_ep_ops,
2050 .maxpacket = INT_FIFO_SIZE,
2051 },
2052 .dev = &memory,
2053 .fifo_size = INT_FIFO_SIZE,
2054 .bEndpointAddress = USB_DIR_IN | 15,
2055 .bmAttributes = USB_ENDPOINT_XFER_INT,
2056 .reg_udccs = &UDCCS15,
2057 .reg_uddr = &UDDR15,
2058 },
2059 #endif /* !CONFIG_USB_PXA2XX_SMALL */
2060 };
2061
2062 #define CP15R0_VENDOR_MASK 0xffffe000
2063
2064 #if defined(CONFIG_ARCH_PXA)
2065 #define CP15R0_XSCALE_VALUE 0x69052000 /* intel/arm/xscale */
2066
2067 #elif defined(CONFIG_ARCH_IXP4XX)
2068 #define CP15R0_XSCALE_VALUE 0x69054000 /* intel/arm/ixp4xx */
2069
2070 #endif
2071
2072 #define CP15R0_PROD_MASK 0x000003f0
2073 #define PXA25x 0x00000100 /* and PXA26x */
2074 #define PXA210 0x00000120
2075
2076 #define CP15R0_REV_MASK 0x0000000f
2077
2078 #define CP15R0_PRODREV_MASK (CP15R0_PROD_MASK | CP15R0_REV_MASK)
2079
2080 #define PXA255_A0 0x00000106 /* or PXA260_B1 */
2081 #define PXA250_C0 0x00000105 /* or PXA26x_B0 */
2082 #define PXA250_B2 0x00000104
2083 #define PXA250_B1 0x00000103 /* or PXA260_A0 */
2084 #define PXA250_B0 0x00000102
2085 #define PXA250_A1 0x00000101
2086 #define PXA250_A0 0x00000100
2087
2088 #define PXA210_C0 0x00000125
2089 #define PXA210_B2 0x00000124
2090 #define PXA210_B1 0x00000123
2091 #define PXA210_B0 0x00000122
2092 #define IXP425_A0 0x000001c1
2093 #define IXP425_B0 0x000001f1
2094 #define IXP465_AD 0x00000200
2095
2096 /*
2097 * probe - binds to the platform device
2098 */
2099 static int __init pxa2xx_udc_probe(struct platform_device *pdev)
2100 {
2101 struct pxa2xx_udc *dev = &memory;
2102 int retval, vbus_irq, irq;
2103 u32 chiprev;
2104
2105 /* insist on Intel/ARM/XScale */
2106 asm("mrc%? p15, 0, %0, c0, c0" : "=r" (chiprev));
2107 if ((chiprev & CP15R0_VENDOR_MASK) != CP15R0_XSCALE_VALUE) {
2108 pr_err("%s: not XScale!\n", driver_name);
2109 return -ENODEV;
2110 }
2111
2112 /* trigger chiprev-specific logic */
2113 switch (chiprev & CP15R0_PRODREV_MASK) {
2114 #if defined(CONFIG_ARCH_PXA)
2115 case PXA255_A0:
2116 dev->has_cfr = 1;
2117 break;
2118 case PXA250_A0:
2119 case PXA250_A1:
2120 /* A0/A1 "not released"; ep 13, 15 unusable */
2121 /* fall through */
2122 case PXA250_B2: case PXA210_B2:
2123 case PXA250_B1: case PXA210_B1:
2124 case PXA250_B0: case PXA210_B0:
2125 /* OUT-DMA is broken ... */
2126 /* fall through */
2127 case PXA250_C0: case PXA210_C0:
2128 break;
2129 #elif defined(CONFIG_ARCH_IXP4XX)
2130 case IXP425_A0:
2131 case IXP425_B0:
2132 case IXP465_AD:
2133 dev->has_cfr = 1;
2134 break;
2135 #endif
2136 default:
2137 pr_err("%s: unrecognized processor: %08x\n",
2138 driver_name, chiprev);
2139 /* iop3xx, ixp4xx, ... */
2140 return -ENODEV;
2141 }
2142
2143 irq = platform_get_irq(pdev, 0);
2144 if (irq < 0)
2145 return -ENODEV;
2146
2147 dev->clk = clk_get(&pdev->dev, "UDCCLK");
2148 if (IS_ERR(dev->clk)) {
2149 retval = PTR_ERR(dev->clk);
2150 goto err_clk;
2151 }
2152
2153 pr_debug("%s: IRQ %d%s%s\n", driver_name, irq,
2154 dev->has_cfr ? "" : " (!cfr)",
2155 SIZE_STR "(pio)"
2156 );
2157
2158 /* other non-static parts of init */
2159 dev->dev = &pdev->dev;
2160 dev->mach = pdev->dev.platform_data;
2161
2162 if (dev->mach->gpio_vbus) {
2163 if ((retval = gpio_request(dev->mach->gpio_vbus,
2164 "pxa2xx_udc GPIO VBUS"))) {
2165 dev_dbg(&pdev->dev,
2166 "can't get vbus gpio %d, err: %d\n",
2167 dev->mach->gpio_vbus, retval);
2168 goto err_gpio_vbus;
2169 }
2170 gpio_direction_input(dev->mach->gpio_vbus);
2171 vbus_irq = gpio_to_irq(dev->mach->gpio_vbus);
2172 } else
2173 vbus_irq = 0;
2174
2175 if (dev->mach->gpio_pullup) {
2176 if ((retval = gpio_request(dev->mach->gpio_pullup,
2177 "pca2xx_udc GPIO PULLUP"))) {
2178 dev_dbg(&pdev->dev,
2179 "can't get pullup gpio %d, err: %d\n",
2180 dev->mach->gpio_pullup, retval);
2181 goto err_gpio_pullup;
2182 }
2183 gpio_direction_output(dev->mach->gpio_pullup, 0);
2184 }
2185
2186 init_timer(&dev->timer);
2187 dev->timer.function = udc_watchdog;
2188 dev->timer.data = (unsigned long) dev;
2189
2190 device_initialize(&dev->gadget.dev);
2191 dev->gadget.dev.parent = &pdev->dev;
2192 dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
2193
2194 the_controller = dev;
2195 platform_set_drvdata(pdev, dev);
2196
2197 udc_disable(dev);
2198 udc_reinit(dev);
2199
2200 dev->vbus = is_vbus_present();
2201
2202 /* irq setup after old hardware state is cleaned up */
2203 retval = request_irq(irq, pxa2xx_udc_irq,
2204 IRQF_DISABLED, driver_name, dev);
2205 if (retval != 0) {
2206 pr_err("%s: can't get irq %d, err %d\n",
2207 driver_name, irq, retval);
2208 goto err_irq1;
2209 }
2210 dev->got_irq = 1;
2211
2212 #ifdef CONFIG_ARCH_LUBBOCK
2213 if (machine_is_lubbock()) {
2214 retval = request_irq(LUBBOCK_USB_DISC_IRQ,
2215 lubbock_vbus_irq,
2216 IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
2217 driver_name, dev);
2218 if (retval != 0) {
2219 pr_err("%s: can't get irq %i, err %d\n",
2220 driver_name, LUBBOCK_USB_DISC_IRQ, retval);
2221 lubbock_fail0:
2222 goto err_irq_lub;
2223 }
2224 retval = request_irq(LUBBOCK_USB_IRQ,
2225 lubbock_vbus_irq,
2226 IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
2227 driver_name, dev);
2228 if (retval != 0) {
2229 pr_err("%s: can't get irq %i, err %d\n",
2230 driver_name, LUBBOCK_USB_IRQ, retval);
2231 free_irq(LUBBOCK_USB_DISC_IRQ, dev);
2232 goto lubbock_fail0;
2233 }
2234 } else
2235 #endif
2236 if (vbus_irq) {
2237 retval = request_irq(vbus_irq, udc_vbus_irq,
2238 IRQF_DISABLED | IRQF_SAMPLE_RANDOM |
2239 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
2240 driver_name, dev);
2241 if (retval != 0) {
2242 pr_err("%s: can't get irq %i, err %d\n",
2243 driver_name, vbus_irq, retval);
2244 goto err_vbus_irq;
2245 }
2246 }
2247 create_debug_files(dev);
2248
2249 return 0;
2250
2251 err_vbus_irq:
2252 #ifdef CONFIG_ARCH_LUBBOCK
2253 free_irq(LUBBOCK_USB_DISC_IRQ, dev);
2254 err_irq_lub:
2255 #endif
2256 free_irq(irq, dev);
2257 err_irq1:
2258 if (dev->mach->gpio_pullup)
2259 gpio_free(dev->mach->gpio_pullup);
2260 err_gpio_pullup:
2261 if (dev->mach->gpio_vbus)
2262 gpio_free(dev->mach->gpio_vbus);
2263 err_gpio_vbus:
2264 clk_put(dev->clk);
2265 err_clk:
2266 return retval;
2267 }
2268
2269 static void pxa2xx_udc_shutdown(struct platform_device *_dev)
2270 {
2271 pullup_off();
2272 }
2273
2274 static int __exit pxa2xx_udc_remove(struct platform_device *pdev)
2275 {
2276 struct pxa2xx_udc *dev = platform_get_drvdata(pdev);
2277
2278 if (dev->driver)
2279 return -EBUSY;
2280
2281 dev->pullup = 0;
2282 pullup(dev);
2283
2284 remove_debug_files(dev);
2285
2286 if (dev->got_irq) {
2287 free_irq(platform_get_irq(pdev, 0), dev);
2288 dev->got_irq = 0;
2289 }
2290 #ifdef CONFIG_ARCH_LUBBOCK
2291 if (machine_is_lubbock()) {
2292 free_irq(LUBBOCK_USB_DISC_IRQ, dev);
2293 free_irq(LUBBOCK_USB_IRQ, dev);
2294 }
2295 #endif
2296 if (dev->mach->gpio_vbus) {
2297 free_irq(gpio_to_irq(dev->mach->gpio_vbus), dev);
2298 gpio_free(dev->mach->gpio_vbus);
2299 }
2300 if (dev->mach->gpio_pullup)
2301 gpio_free(dev->mach->gpio_pullup);
2302
2303 clk_put(dev->clk);
2304
2305 platform_set_drvdata(pdev, NULL);
2306 the_controller = NULL;
2307 return 0;
2308 }
2309
2310 /*-------------------------------------------------------------------------*/
2311
2312 #ifdef CONFIG_PM
2313
2314 /* USB suspend (controlled by the host) and system suspend (controlled
2315 * by the PXA) don't necessarily work well together. If USB is active,
2316 * the 48 MHz clock is required; so the system can't enter 33 MHz idle
2317 * mode, or any deeper PM saving state.
2318 *
2319 * For now, we punt and forcibly disconnect from the USB host when PXA
2320 * enters any suspend state. While we're disconnected, we always disable
2321 * the 48MHz USB clock ... allowing PXA sleep and/or 33 MHz idle states.
2322 * Boards without software pullup control shouldn't use those states.
2323 * VBUS IRQs should probably be ignored so that the PXA device just acts
2324 * "dead" to USB hosts until system resume.
2325 */
2326 static int pxa2xx_udc_suspend(struct platform_device *dev, pm_message_t state)
2327 {
2328 struct pxa2xx_udc *udc = platform_get_drvdata(dev);
2329 unsigned long flags;
2330
2331 if (!udc->mach->gpio_pullup && !udc->mach->udc_command)
2332 WARN("USB host won't detect disconnect!\n");
2333 udc->suspended = 1;
2334
2335 local_irq_save(flags);
2336 pullup(udc);
2337 local_irq_restore(flags);
2338
2339 return 0;
2340 }
2341
2342 static int pxa2xx_udc_resume(struct platform_device *dev)
2343 {
2344 struct pxa2xx_udc *udc = platform_get_drvdata(dev);
2345 unsigned long flags;
2346
2347 udc->suspended = 0;
2348 local_irq_save(flags);
2349 pullup(udc);
2350 local_irq_restore(flags);
2351
2352 return 0;
2353 }
2354
2355 #else
2356 #define pxa2xx_udc_suspend NULL
2357 #define pxa2xx_udc_resume NULL
2358 #endif
2359
2360 /*-------------------------------------------------------------------------*/
2361
2362 static struct platform_driver udc_driver = {
2363 .shutdown = pxa2xx_udc_shutdown,
2364 .remove = __exit_p(pxa2xx_udc_remove),
2365 .suspend = pxa2xx_udc_suspend,
2366 .resume = pxa2xx_udc_resume,
2367 .driver = {
2368 .owner = THIS_MODULE,
2369 .name = "pxa2xx-udc",
2370 },
2371 };
2372
2373 static int __init udc_init(void)
2374 {
2375 pr_info("%s: version %s\n", driver_name, DRIVER_VERSION);
2376 return platform_driver_probe(&udc_driver, pxa2xx_udc_probe);
2377 }
2378 module_init(udc_init);
2379
2380 static void __exit udc_exit(void)
2381 {
2382 platform_driver_unregister(&udc_driver);
2383 }
2384 module_exit(udc_exit);
2385
2386 MODULE_DESCRIPTION(DRIVER_DESC);
2387 MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
2388 MODULE_LICENSE("GPL");
2389 MODULE_ALIAS("platform:pxa2xx-udc");
AMDTP streaming driver for the Linux FireWire stack (Juju)