arch/mips/sibyte/sb1250/irq.c

   1 /*
   2  * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  */
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/linkage.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/smp.h>
  24 #include <linux/mm.h>
  25 #include <linux/slab.h>
  26 #include <linux/kernel_stat.h>
  27
  28 #include <asm/errno.h>
  29 #include <asm/signal.h>
  30 #include <asm/system.h>
  31 #include <asm/io.h>
  32
  33 #include <asm/sibyte/sb1250_regs.h>
  34 #include <asm/sibyte/sb1250_int.h>
  35 #include <asm/sibyte/sb1250_uart.h>
  36 #include <asm/sibyte/sb1250_scd.h>
  37 #include <asm/sibyte/sb1250.h>
  38
  39 /*
  40  * These are the routines that handle all the low level interrupt stuff.
  41  * Actions handled here are: initialization of the interrupt map, requesting of
  42  * interrupt lines by handlers, dispatching if interrupts to handlers, probing
  43  * for interrupt lines
  44  */
  45
  46
  47 #define shutdown_sb1250_irq     disable_sb1250_irq
  48 static void end_sb1250_irq(unsigned int irq);
  49 static void enable_sb1250_irq(unsigned int irq);
  50 static void disable_sb1250_irq(unsigned int irq);
  51 static unsigned int startup_sb1250_irq(unsigned int irq);
  52 static void ack_sb1250_irq(unsigned int irq);
  53 #ifdef CONFIG_SMP
  54 static void sb1250_set_affinity(unsigned int irq, cpumask_t mask);
  55 #endif
  56
  57 #ifdef CONFIG_SIBYTE_HAS_LDT
  58 extern unsigned long ldt_eoi_space;
  59 #endif
  60
  61 #ifdef CONFIG_KGDB
  62 static int kgdb_irq;
  63
  64 /* Default to UART1 */
  65 int kgdb_port = 1;
  66 #ifdef CONFIG_SIBYTE_SB1250_DUART
  67 extern char sb1250_duart_present[];
  68 #endif
  69 #endif
  70
  71 static struct irq_chip sb1250_irq_type = {
  72         .typename = "SB1250-IMR",
  73         .startup = startup_sb1250_irq,
  74         .shutdown = shutdown_sb1250_irq,
  75         .enable = enable_sb1250_irq,
  76         .disable = disable_sb1250_irq,
  77         .ack = ack_sb1250_irq,
  78         .end = end_sb1250_irq,
  79 #ifdef CONFIG_SMP
  80         .set_affinity = sb1250_set_affinity
  81 #endif
  82 };
  83
  84 /* Store the CPU id (not the logical number) */
  85 int sb1250_irq_owner[SB1250_NR_IRQS];
  86
  87 DEFINE_SPINLOCK(sb1250_imr_lock);
  88
  89 void sb1250_mask_irq(int cpu, int irq)
  90 {
  91         unsigned long flags;
  92         u64 cur_ints;
  93
  94         spin_lock_irqsave(&sb1250_imr_lock, flags);
  95         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
  96                                         R_IMR_INTERRUPT_MASK));
  97         cur_ints |= (((u64) 1) << irq);
  98         ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
  99                                         R_IMR_INTERRUPT_MASK));
 100         spin_unlock_irqrestore(&sb1250_imr_lock, flags);
 101 }
 102
 103 void sb1250_unmask_irq(int cpu, int irq)
 104 {
 105         unsigned long flags;
 106         u64 cur_ints;
 107
 108         spin_lock_irqsave(&sb1250_imr_lock, flags);
 109         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
 110                                         R_IMR_INTERRUPT_MASK));
 111         cur_ints &= ~(((u64) 1) << irq);
 112         ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
 113                                         R_IMR_INTERRUPT_MASK));
 114         spin_unlock_irqrestore(&sb1250_imr_lock, flags);
 115 }
 116
 117 #ifdef CONFIG_SMP
 118 static void sb1250_set_affinity(unsigned int irq, cpumask_t mask)
 119 {
 120         int i = 0, old_cpu, cpu, int_on;
 121         u64 cur_ints;
 122         struct irq_desc *desc = irq_desc + irq;
 123         unsigned long flags;
 124
 125         i = first_cpu(mask);
 126
 127         if (cpus_weight(mask) > 1) {
 128                 printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
 129                 return;
 130         }
 131
 132         /* Convert logical CPU to physical CPU */
 133         cpu = cpu_logical_map(i);
 134
 135         /* Protect against other affinity changers and IMR manipulation */
 136         spin_lock_irqsave(&desc->lock, flags);
 137         spin_lock(&sb1250_imr_lock);
 138
 139         /* Swizzle each CPU's IMR (but leave the IP selection alone) */
 140         old_cpu = sb1250_irq_owner[irq];
 141         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
 142                                         R_IMR_INTERRUPT_MASK));
 143         int_on = !(cur_ints & (((u64) 1) << irq));
 144         if (int_on) {
 145                 /* If it was on, mask it */
 146                 cur_ints |= (((u64) 1) << irq);
 147                 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
 148                                         R_IMR_INTERRUPT_MASK));
 149         }
 150         sb1250_irq_owner[irq] = cpu;
 151         if (int_on) {
 152                 /* unmask for the new CPU */
 153                 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
 154                                         R_IMR_INTERRUPT_MASK));
 155                 cur_ints &= ~(((u64) 1) << irq);
 156                 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
 157                                         R_IMR_INTERRUPT_MASK));
 158         }
 159         spin_unlock(&sb1250_imr_lock);
 160         spin_unlock_irqrestore(&desc->lock, flags);
 161 }
 162 #endif
 163
 164 /*****************************************************************************/
 165
 166 static unsigned int startup_sb1250_irq(unsigned int irq)
 167 {
 168         sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
 169
 170         return 0;               /* never anything pending */
 171 }
 172
 173
 174 static void disable_sb1250_irq(unsigned int irq)
 175 {
 176         sb1250_mask_irq(sb1250_irq_owner[irq], irq);
 177 }
 178
 179 static void enable_sb1250_irq(unsigned int irq)
 180 {
 181         sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
 182 }
 183
 184
 185 static void ack_sb1250_irq(unsigned int irq)
 186 {
 187 #ifdef CONFIG_SIBYTE_HAS_LDT
 188         u64 pending;
 189
 190         /*
 191          * If the interrupt was an HT interrupt, now is the time to
 192          * clear it.  NOTE: we assume the HT bridge was set up to
 193          * deliver the interrupts to all CPUs (which makes affinity
 194          * changing easier for us)
 195          */
 196         pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
 197                                                     R_IMR_LDT_INTERRUPT)));
 198         pending &= ((u64)1 << (irq));
 199         if (pending) {
 200                 int i;
 201                 for (i=0; i<NR_CPUS; i++) {
 202                         int cpu;
 203 #ifdef CONFIG_SMP
 204                         cpu = cpu_logical_map(i);
 205 #else
 206                         cpu = i;
 207 #endif
 208                         /*
 209                          * Clear for all CPUs so an affinity switch
 210                          * doesn't find an old status
 211                          */
 212                         __raw_writeq(pending,
 213                                      IOADDR(A_IMR_REGISTER(cpu,
 214                                                 R_IMR_LDT_INTERRUPT_CLR)));
 215                 }
 216
 217                 /*
 218                  * Generate EOI.  For Pass 1 parts, EOI is a nop.  For
 219                  * Pass 2, the LDT world may be edge-triggered, but
 220                  * this EOI shouldn't hurt.  If they are
 221                  * level-sensitive, the EOI is required.
 222                  */
 223                 *(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0;
 224         }
 225 #endif
 226         sb1250_mask_irq(sb1250_irq_owner[irq], irq);
 227 }
 228
 229
 230 static void end_sb1250_irq(unsigned int irq)
 231 {
 232         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
 233                 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
 234         }
 235 }
 236
 237
 238 void __init init_sb1250_irqs(void)
 239 {
 240         int i;
 241
 242         for (i = 0; i < NR_IRQS; i++) {
 243                 irq_desc[i].status = IRQ_DISABLED;
 244                 irq_desc[i].action = 0;
 245                 irq_desc[i].depth = 1;
 246                 if (i < SB1250_NR_IRQS) {
 247                         irq_desc[i].chip = &sb1250_irq_type;
 248                         sb1250_irq_owner[i] = 0;
 249                 } else {
 250                         irq_desc[i].chip = &no_irq_chip;
 251                 }
 252         }
 253 }
 254
 255
 256 static irqreturn_t  sb1250_dummy_handler(int irq, void *dev_id)
 257 {
 258         return IRQ_NONE;
 259 }
 260
 261 static struct irqaction sb1250_dummy_action = {
 262         .handler = sb1250_dummy_handler,
 263         .flags   = 0,
 264         .mask    = CPU_MASK_NONE,
 265         .name    = "sb1250-private",
 266         .next    = NULL,
 267         .dev_id  = 0
 268 };
 269
 270 int sb1250_steal_irq(int irq)
 271 {
 272         struct irq_desc *desc = irq_desc + irq;
 273         unsigned long flags;
 274         int retval = 0;
 275
 276         if (irq >= SB1250_NR_IRQS)
 277                 return -EINVAL;
 278
 279         spin_lock_irqsave(&desc->lock,flags);
 280         /* Don't allow sharing at all for these */
 281         if (desc->action != NULL)
 282                 retval = -EBUSY;
 283         else {
 284                 desc->action = &sb1250_dummy_action;
 285                 desc->depth = 0;
 286         }
 287         spin_unlock_irqrestore(&desc->lock,flags);
 288         return 0;
 289 }
 290
 291 /*
 292  *  arch_init_irq is called early in the boot sequence from init/main.c via
 293  *  init_IRQ.  It is responsible for setting up the interrupt mapper and
 294  *  installing the handler that will be responsible for dispatching interrupts
 295  *  to the "right" place.
 296  */
 297 /*
 298  * For now, map all interrupts to IP[2].  We could save
 299  * some cycles by parceling out system interrupts to different
 300  * IP lines, but keep it simple for bringup.  We'll also direct
 301  * all interrupts to a single CPU; we should probably route
 302  * PCI and LDT to one cpu and everything else to the other
 303  * to balance the load a bit.
 304  *
 305  * On the second cpu, everything is set to IP5, which is
 306  * ignored, EXCEPT the mailbox interrupt.  That one is
 307  * set to IP[2] so it is handled.  This is needed so we
 308  * can do cross-cpu function calls, as requred by SMP
 309  */
 310
 311 #define IMR_IP2_VAL     K_INT_MAP_I0
 312 #define IMR_IP3_VAL     K_INT_MAP_I1
 313 #define IMR_IP4_VAL     K_INT_MAP_I2
 314 #define IMR_IP5_VAL     K_INT_MAP_I3
 315 #define IMR_IP6_VAL     K_INT_MAP_I4
 316
 317 void __init arch_init_irq(void)
 318 {
 319
 320         unsigned int i;
 321         u64 tmp;
 322         unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
 323                 STATUSF_IP1 | STATUSF_IP0;
 324
 325         /* Default everything to IP2 */
 326         for (i = 0; i < SB1250_NR_IRQS; i++) {  /* was I0 */
 327                 __raw_writeq(IMR_IP2_VAL,
 328                              IOADDR(A_IMR_REGISTER(0,
 329                                                    R_IMR_INTERRUPT_MAP_BASE) +
 330                                     (i << 3)));
 331                 __raw_writeq(IMR_IP2_VAL,
 332                              IOADDR(A_IMR_REGISTER(1,
 333                                                    R_IMR_INTERRUPT_MAP_BASE) +
 334                                     (i << 3)));
 335         }
 336
 337         init_sb1250_irqs();
 338
 339         /*
 340          * Map the high 16 bits of the mailbox registers to IP[3], for
 341          * inter-cpu messages
 342          */
 343         /* Was I1 */
 344         __raw_writeq(IMR_IP3_VAL,
 345                      IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
 346                             (K_INT_MBOX_0 << 3)));
 347         __raw_writeq(IMR_IP3_VAL,
 348                      IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
 349                             (K_INT_MBOX_0 << 3)));
 350
 351         /* Clear the mailboxes.  The firmware may leave them dirty */
 352         __raw_writeq(0xffffffffffffffffULL,
 353                      IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
 354         __raw_writeq(0xffffffffffffffffULL,
 355                      IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
 356
 357         /* Mask everything except the mailbox registers for both cpus */
 358         tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
 359         __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
 360         __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
 361
 362         sb1250_steal_irq(K_INT_MBOX_0);
 363
 364         /*
 365          * Note that the timer interrupts are also mapped, but this is
 366          * done in sb1250_time_init().  Also, the profiling driver
 367          * does its own management of IP7.
 368          */
 369
 370 #ifdef CONFIG_KGDB
 371         imask |= STATUSF_IP6;
 372 #endif
 373         /* Enable necessary IPs, disable the rest */
 374         change_c0_status(ST0_IM, imask);
 375
 376 #ifdef CONFIG_KGDB
 377         if (kgdb_flag) {
 378                 kgdb_irq = K_INT_UART_0 + kgdb_port;
 379
 380 #ifdef CONFIG_SIBYTE_SB1250_DUART
 381                 sb1250_duart_present[kgdb_port] = 0;
 382 #endif
 383                 /* Setup uart 1 settings, mapper */
 384                 __raw_writeq(M_DUART_IMR_BRK,
 385                              IOADDR(A_DUART_IMRREG(kgdb_port)));
 386
 387                 sb1250_steal_irq(kgdb_irq);
 388                 __raw_writeq(IMR_IP6_VAL,
 389                              IOADDR(A_IMR_REGISTER(0,
 390                                                    R_IMR_INTERRUPT_MAP_BASE) +
 391                                     (kgdb_irq << 3)));
 392                 sb1250_unmask_irq(0, kgdb_irq);
 393         }
 394 #endif
 395 }
 396
 397 #ifdef CONFIG_KGDB
 398
 399 #include <linux/delay.h>
 400
 401 #define duart_out(reg, val)     csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
 402 #define duart_in(reg)           csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
 403
 404 static void sb1250_kgdb_interrupt(void)
 405 {
 406         /*
 407          * Clear break-change status (allow some time for the remote
 408          * host to stop the break, since we would see another
 409          * interrupt on the end-of-break too)
 410          */
 411         kstat_this_cpu.irqs[kgdb_irq]++;
 412         mdelay(500);
 413         duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
 414                                 M_DUART_RX_EN | M_DUART_TX_EN);
 415         set_async_breakpoint(&get_irq_regs()->cp0_epc);
 416 }
 417
 418 #endif  /* CONFIG_KGDB */
 419
 420 extern void sb1250_timer_interrupt(void);
 421 extern void sb1250_mailbox_interrupt(void);
 422
 423 asmlinkage void plat_irq_dispatch(void)
 424 {
 425         unsigned int pending;
 426
 427 #ifdef CONFIG_SIBYTE_SB1250_PROF
 428         /* Set compare to count to silence count/compare timer interrupts */
 429         write_c0_compare(read_c0_count());
 430 #endif
 431
 432         /*
 433          * What a pain. We have to be really careful saving the upper 32 bits
 434          * of any * register across function calls if we don't want them
 435          * trashed--since were running in -o32, the calling routing never saves
 436          * the full 64 bits of a register across a function call.  Being the
 437          * interrupt handler, we're guaranteed that interrupts are disabled
 438          * during this code so we don't have to worry about random interrupts
 439          * blasting the high 32 bits.
 440          */
 441
 442         pending = read_c0_cause() & read_c0_status();
 443
 444 #ifdef CONFIG_SIBYTE_SB1250_PROF
 445         if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */
 446                 sbprof_cpu_intr();
 447         else
 448 #endif
 449
 450         if (pending & CAUSEF_IP4)
 451                 sb1250_timer_interrupt();
 452
 453 #ifdef CONFIG_SMP
 454         else if (pending & CAUSEF_IP3)
 455                 sb1250_mailbox_interrupt();
 456 #endif
 457
 458 #ifdef CONFIG_KGDB
 459         else if (pending & CAUSEF_IP6)                  /* KGDB (uart 1) */
 460                 sb1250_kgdb_interrupt();
 461 #endif
 462
 463         else if (pending & CAUSEF_IP2) {
 464                 unsigned long long mask;
 465
 466                 /*
 467                  * Default...we've hit an IP[2] interrupt, which means we've
 468                  * got to check the 1250 interrupt registers to figure out what
 469                  * to do.  Need to detect which CPU we're on, now that
 470                  * smp_affinity is supported.
 471                  */
 472                 mask = __raw_readq(IOADDR(A_IMR_REGISTER(smp_processor_id(),
 473                                               R_IMR_INTERRUPT_STATUS_BASE)));
 474                 if (mask)
 475                         do_IRQ(fls64(mask) - 1);
 476                 else
 477                         spurious_interrupt();
 478         } else
 479                 spurious_interrupt();
 480 }