[MIPS] Cleanup unnecessary <asm/ptrace.h> inclusions.
[firewire-audio.git] / arch / mips / kernel / irq-msc01.c
blob650a80ca37418f1e0399f683520c9ab54887ccd3
1 /*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
7 * Copyright (c) 2004 MIPS Inc
8 * Author: chris@mips.com
10 * Copyright (C) 2004, 06 Ralf Baechle <ralf@linux-mips.org>
12 #include <linux/module.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/sched.h>
16 #include <linux/kernel_stat.h>
17 #include <asm/io.h>
18 #include <asm/irq.h>
19 #include <asm/msc01_ic.h>
21 static unsigned long _icctrl_msc;
22 #define MSC01_IC_REG_BASE _icctrl_msc
24 #define MSCIC_WRITE(reg, data) do { *(volatile u32 *)(reg) = data; } while (0)
25 #define MSCIC_READ(reg, data) do { data = *(volatile u32 *)(reg); } while (0)
27 static unsigned int irq_base;
29 /* mask off an interrupt */
30 static inline void mask_msc_irq(unsigned int irq)
32 if (irq < (irq_base + 32))
33 MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base));
34 else
35 MSCIC_WRITE(MSC01_IC_DISH, 1<<(irq - irq_base - 32));
38 /* unmask an interrupt */
39 static inline void unmask_msc_irq(unsigned int irq)
41 if (irq < (irq_base + 32))
42 MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base));
43 else
44 MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32));
48 * Enables the IRQ on SOC-it
50 static void enable_msc_irq(unsigned int irq)
52 unmask_msc_irq(irq);
56 * Initialize the IRQ on SOC-it
58 static unsigned int startup_msc_irq(unsigned int irq)
60 unmask_msc_irq(irq);
61 return 0;
65 * Disables the IRQ on SOC-it
67 static void disable_msc_irq(unsigned int irq)
69 mask_msc_irq(irq);
73 * Masks and ACKs an IRQ
75 static void level_mask_and_ack_msc_irq(unsigned int irq)
77 mask_msc_irq(irq);
78 if (!cpu_has_veic)
79 MSCIC_WRITE(MSC01_IC_EOI, 0);
80 #ifdef CONFIG_MIPS_MT_SMTC
81 /* This actually needs to be a call into platform code */
82 if (irq_hwmask[irq] & ST0_IM)
83 set_c0_status(irq_hwmask[irq] & ST0_IM);
84 #endif /* CONFIG_MIPS_MT_SMTC */
88 * Masks and ACKs an IRQ
90 static void edge_mask_and_ack_msc_irq(unsigned int irq)
92 mask_msc_irq(irq);
93 if (!cpu_has_veic)
94 MSCIC_WRITE(MSC01_IC_EOI, 0);
95 else {
96 u32 r;
97 MSCIC_READ(MSC01_IC_SUP+irq*8, r);
98 MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT);
99 MSCIC_WRITE(MSC01_IC_SUP+irq*8, r);
101 #ifdef CONFIG_MIPS_MT_SMTC
102 if (irq_hwmask[irq] & ST0_IM)
103 set_c0_status(irq_hwmask[irq] & ST0_IM);
104 #endif /* CONFIG_MIPS_MT_SMTC */
108 * End IRQ processing
110 static void end_msc_irq(unsigned int irq)
112 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
113 unmask_msc_irq(irq);
117 * Interrupt handler for interrupts coming from SOC-it.
119 void ll_msc_irq(void)
121 unsigned int irq;
123 /* read the interrupt vector register */
124 MSCIC_READ(MSC01_IC_VEC, irq);
125 if (irq < 64)
126 do_IRQ(irq + irq_base);
127 else {
128 /* Ignore spurious interrupt */
132 void
133 msc_bind_eic_interrupt (unsigned int irq, unsigned int set)
135 MSCIC_WRITE(MSC01_IC_RAMW,
136 (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF));
139 #define shutdown_msc_irq disable_msc_irq
141 struct irq_chip msc_levelirq_type = {
142 .typename = "SOC-it-Level",
143 .startup = startup_msc_irq,
144 .shutdown = shutdown_msc_irq,
145 .enable = enable_msc_irq,
146 .disable = disable_msc_irq,
147 .ack = level_mask_and_ack_msc_irq,
148 .end = end_msc_irq,
151 struct irq_chip msc_edgeirq_type = {
152 .typename = "SOC-it-Edge",
153 .startup =startup_msc_irq,
154 .shutdown = shutdown_msc_irq,
155 .enable = enable_msc_irq,
156 .disable = disable_msc_irq,
157 .ack = edge_mask_and_ack_msc_irq,
158 .end = end_msc_irq,
162 void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq)
164 extern void (*board_bind_eic_interrupt)(unsigned int irq, unsigned int regset);
166 _icctrl_msc = (unsigned long) ioremap (MIPS_MSC01_IC_REG_BASE, 0x40000);
168 /* Reset interrupt controller - initialises all registers to 0 */
169 MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);
171 board_bind_eic_interrupt = &msc_bind_eic_interrupt;
173 for (; nirq >= 0; nirq--, imp++) {
174 int n = imp->im_irq;
176 switch (imp->im_type) {
177 case MSC01_IRQ_EDGE:
178 irq_desc[base+n].chip = &msc_edgeirq_type;
179 if (cpu_has_veic)
180 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
181 else
182 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
183 break;
184 case MSC01_IRQ_LEVEL:
185 irq_desc[base+n].chip = &msc_levelirq_type;
186 if (cpu_has_veic)
187 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
188 else
189 MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl);
193 irq_base = base;
195 MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */