arch/mips/cobalt/irq.c

   1 /*
   2  * IRQ vector handles
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle
   9  */
  10 #include <linux/kernel.h>
  11 #include <linux/init.h>
  12 #include <linux/irq.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/pci.h>
  15
  16 #include <asm/i8259.h>
  17 #include <asm/irq_cpu.h>
  18 #include <asm/gt64120.h>
  19
  20 #include <asm/mach-cobalt/cobalt.h>
  21
  22 /*
  23  * We have two types of interrupts that we handle, ones that come in through
  24  * the CPU interrupt lines, and ones that come in on the via chip. The CPU
  25  * mappings are:
  26  *
  27  *    16   - Software interrupt 0 (unused)      IE_SW0
  28  *    17   - Software interrupt 1 (unused)      IE_SW1
  29  *    18   - Galileo chip (timer)               IE_IRQ0
  30  *    19   - Tulip 0 + NCR SCSI                 IE_IRQ1
  31  *    20   - Tulip 1                            IE_IRQ2
  32  *    21   - 16550 UART                         IE_IRQ3
  33  *    22   - VIA southbridge PIC                IE_IRQ4
  34  *    23   - unused                             IE_IRQ5
  35  *
  36  * The VIA chip is a master/slave 8259 setup and has the following interrupts:
  37  *
  38  *     8  - RTC
  39  *     9  - PCI
  40  *    14  - IDE0
  41  *    15  - IDE1
  42  */
  43
  44 static inline void galileo_irq(void)
  45 {
  46         unsigned int mask, pending, devfn;
  47
  48         mask = GALILEO_INL(GT_INTRMASK_OFS);
  49         pending = GALILEO_INL(GT_INTRCAUSE_OFS) & mask;
  50
  51         if (pending & GALILEO_INTR_T0EXP) {
  52
  53                 GALILEO_OUTL(~GALILEO_INTR_T0EXP, GT_INTRCAUSE_OFS);
  54                 do_IRQ(COBALT_GALILEO_IRQ);
  55
  56         } else if (pending & GALILEO_INTR_RETRY_CTR) {
  57
  58                 devfn = GALILEO_INL(GT_PCI0_CFGADDR_OFS) >> 8;
  59                 GALILEO_OUTL(~GALILEO_INTR_RETRY_CTR, GT_INTRCAUSE_OFS);
  60                 printk(KERN_WARNING "Galileo: PCI retry count exceeded (%02x.%u)\n",
  61                         PCI_SLOT(devfn), PCI_FUNC(devfn));
  62
  63         } else {
  64
  65                 GALILEO_OUTL(mask & ~pending, GT_INTRMASK_OFS);
  66                 printk(KERN_WARNING "Galileo: masking unexpected interrupt %08x\n", pending);
  67         }
  68 }
  69
  70 static inline void via_pic_irq(void)
  71 {
  72         int irq;
  73
  74         irq = i8259_irq();
  75         if (irq >= 0)
  76                 do_IRQ(irq);
  77 }
  78
  79 asmlinkage void plat_irq_dispatch(void)
  80 {
  81         unsigned pending = read_c0_status() & read_c0_cause();
  82
  83         if (pending & CAUSEF_IP2)               /* COBALT_GALILEO_IRQ (18) */
  84                 galileo_irq();
  85         else if (pending & CAUSEF_IP6)          /* COBALT_VIA_IRQ (22) */
  86                 via_pic_irq();
  87         else if (pending & CAUSEF_IP3)          /* COBALT_ETH0_IRQ (19) */
  88                 do_IRQ(COBALT_CPU_IRQ + 3);
  89         else if (pending & CAUSEF_IP4)          /* COBALT_ETH1_IRQ (20) */
  90                 do_IRQ(COBALT_CPU_IRQ + 4);
  91         else if (pending & CAUSEF_IP5)          /* COBALT_SERIAL_IRQ (21) */
  92                 do_IRQ(COBALT_CPU_IRQ + 5);
  93         else if (pending & CAUSEF_IP7)          /* IRQ 23 */
  94                 do_IRQ(COBALT_CPU_IRQ + 7);
  95 }
  96
  97 static struct irqaction irq_via = {
  98         no_action, 0, { { 0, } }, "cascade", NULL, NULL
  99 };
 100
 101 void __init arch_init_irq(void)
 102 {
 103         /*
 104          * Mask all Galileo interrupts. The Galileo
 105          * handler is set in cobalt_timer_setup()
 106          */
 107         GALILEO_OUTL(0, GT_INTRMASK_OFS);
 108
 109         init_i8259_irqs();                              /*  0 ... 15 */
 110         mips_cpu_irq_init(COBALT_CPU_IRQ);              /* 16 ... 23 */
 111
 112         /*
 113          * Mask all cpu interrupts
 114          *  (except IE4, we already masked those at VIA level)
 115          */
 116         change_c0_status(ST0_IM, IE_IRQ4);
 117
 118         setup_irq(COBALT_VIA_IRQ, &irq_via);
 119 }