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sky2: PCI irq issues
[firewire-audio.git] / drivers / net / sky2.c
blobcc1c8d13845f99bcca52c546e94420fe0f10ba7e
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/netdevice.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/pci.h>
33 #include <linux/ip.h>
34 #include <net/ip.h>
35 #include <linux/tcp.h>
36 #include <linux/in.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/debugfs.h>
42 #include <linux/mii.h>
43
44 #include <asm/irq.h>
45
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
48 #endif
49
50 #include "sky2.h"
51
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.22"
54 #define PFX DRV_NAME " "
55
56 /*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3.
60 */
61
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
66
67 #define TX_RING_SIZE 512
68 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
69 #define TX_MIN_PENDING 64
70 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
71
72 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
73 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
74 #define TX_WATCHDOG (5 * HZ)
75 #define NAPI_WEIGHT 64
76 #define PHY_RETRIES 1000
77
78 #define SKY2_EEPROM_MAGIC 0x9955aabb
79
80
81 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
82
83 static const u32 default_msg =
84 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
85 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
86 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
87
88 static int debug = -1; /* defaults above */
89 module_param(debug, int, 0);
90 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
91
92 static int copybreak __read_mostly = 128;
93 module_param(copybreak, int, 0);
94 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
95
96 static int disable_msi = 0;
97 module_param(disable_msi, int, 0);
98 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
99
100 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
140 { 0 }
141 };
142
143 MODULE_DEVICE_TABLE(pci, sky2_id_table);
144
145 /* Avoid conditionals by using array */
146 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
147 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
148 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
149
150 static void sky2_set_multicast(struct net_device *dev);
151
152 /* Access to PHY via serial interconnect */
153 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
154 {
155 int i;
156
157 gma_write16(hw, port, GM_SMI_DATA, val);
158 gma_write16(hw, port, GM_SMI_CTRL,
159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
160
161 for (i = 0; i < PHY_RETRIES; i++) {
162 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
163 if (ctrl == 0xffff)
164 goto io_error;
165
166 if (!(ctrl & GM_SMI_CT_BUSY))
167 return 0;
168
169 udelay(10);
170 }
171
172 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
173 return -ETIMEDOUT;
174
175 io_error:
176 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
177 return -EIO;
178 }
179
180 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
181 {
182 int i;
183
184 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
185 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
186
187 for (i = 0; i < PHY_RETRIES; i++) {
188 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
189 if (ctrl == 0xffff)
190 goto io_error;
191
192 if (ctrl & GM_SMI_CT_RD_VAL) {
193 *val = gma_read16(hw, port, GM_SMI_DATA);
194 return 0;
195 }
196
197 udelay(10);
198 }
199
200 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
201 return -ETIMEDOUT;
202 io_error:
203 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
204 return -EIO;
205 }
206
207 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
208 {
209 u16 v;
210 __gm_phy_read(hw, port, reg, &v);
211 return v;
212 }
213
214
215 static void sky2_power_on(struct sky2_hw *hw)
216 {
217 /* switch power to VCC (WA for VAUX problem) */
218 sky2_write8(hw, B0_POWER_CTRL,
219 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
220
221 /* disable Core Clock Division, */
222 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
223
224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
225 /* enable bits are inverted */
226 sky2_write8(hw, B2_Y2_CLK_GATE,
227 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
228 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
229 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
230 else
231 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
232
233 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
234 u32 reg;
235
236 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
237
238 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
239 /* set all bits to 0 except bits 15..12 and 8 */
240 reg &= P_ASPM_CONTROL_MSK;
241 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
242
243 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
244 /* set all bits to 0 except bits 28 & 27 */
245 reg &= P_CTL_TIM_VMAIN_AV_MSK;
246 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
247
248 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
249
250 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
251 reg = sky2_read32(hw, B2_GP_IO);
252 reg |= GLB_GPIO_STAT_RACE_DIS;
253 sky2_write32(hw, B2_GP_IO, reg);
254
255 sky2_read32(hw, B2_GP_IO);
256 }
257 }
258
259 static void sky2_power_aux(struct sky2_hw *hw)
260 {
261 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
262 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
263 else
264 /* enable bits are inverted */
265 sky2_write8(hw, B2_Y2_CLK_GATE,
266 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
267 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
268 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
269
270 /* switch power to VAUX */
271 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
272 sky2_write8(hw, B0_POWER_CTRL,
273 (PC_VAUX_ENA | PC_VCC_ENA |
274 PC_VAUX_ON | PC_VCC_OFF));
275 }
276
277 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
278 {
279 u16 reg;
280
281 /* disable all GMAC IRQ's */
282 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
283
284 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
285 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
286 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
287 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
288
289 reg = gma_read16(hw, port, GM_RX_CTRL);
290 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
291 gma_write16(hw, port, GM_RX_CTRL, reg);
292 }
293
294 /* flow control to advertise bits */
295 static const u16 copper_fc_adv[] = {
296 [FC_NONE] = 0,
297 [FC_TX] = PHY_M_AN_ASP,
298 [FC_RX] = PHY_M_AN_PC,
299 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
300 };
301
302 /* flow control to advertise bits when using 1000BaseX */
303 static const u16 fiber_fc_adv[] = {
304 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
305 [FC_TX] = PHY_M_P_ASYM_MD_X,
306 [FC_RX] = PHY_M_P_SYM_MD_X,
307 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
308 };
309
310 /* flow control to GMA disable bits */
311 static const u16 gm_fc_disable[] = {
312 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
313 [FC_TX] = GM_GPCR_FC_RX_DIS,
314 [FC_RX] = GM_GPCR_FC_TX_DIS,
315 [FC_BOTH] = 0,
316 };
317
318
319 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
320 {
321 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
322 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
323
324 if (sky2->autoneg == AUTONEG_ENABLE &&
325 !(hw->flags & SKY2_HW_NEWER_PHY)) {
326 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
327
328 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
329 PHY_M_EC_MAC_S_MSK);
330 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
331
332 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
333 if (hw->chip_id == CHIP_ID_YUKON_EC)
334 /* set downshift counter to 3x and enable downshift */
335 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
336 else
337 /* set master & slave downshift counter to 1x */
338 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
339
340 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
341 }
342
343 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
344 if (sky2_is_copper(hw)) {
345 if (!(hw->flags & SKY2_HW_GIGABIT)) {
346 /* enable automatic crossover */
347 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
348
349 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
350 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
351 u16 spec;
352
353 /* Enable Class A driver for FE+ A0 */
354 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
355 spec |= PHY_M_FESC_SEL_CL_A;
356 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
357 }
358 } else {
359 /* disable energy detect */
360 ctrl &= ~PHY_M_PC_EN_DET_MSK;
361
362 /* enable automatic crossover */
363 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
364
365 /* downshift on PHY 88E1112 and 88E1149 is changed */
366 if (sky2->autoneg == AUTONEG_ENABLE
367 && (hw->flags & SKY2_HW_NEWER_PHY)) {
368 /* set downshift counter to 3x and enable downshift */
369 ctrl &= ~PHY_M_PC_DSC_MSK;
370 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
371 }
372 }
373 } else {
374 /* workaround for deviation #4.88 (CRC errors) */
375 /* disable Automatic Crossover */
376
377 ctrl &= ~PHY_M_PC_MDIX_MSK;
378 }
379
380 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
381
382 /* special setup for PHY 88E1112 Fiber */
383 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
384 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
385
386 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
387 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
388 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
389 ctrl &= ~PHY_M_MAC_MD_MSK;
390 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
391 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
392
393 if (hw->pmd_type == 'P') {
394 /* select page 1 to access Fiber registers */
395 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
396
397 /* for SFP-module set SIGDET polarity to low */
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl |= PHY_M_FIB_SIGD_POL;
400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
401 }
402
403 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
404 }
405
406 ctrl = PHY_CT_RESET;
407 ct1000 = 0;
408 adv = PHY_AN_CSMA;
409 reg = 0;
410
411 if (sky2->autoneg == AUTONEG_ENABLE) {
412 if (sky2_is_copper(hw)) {
413 if (sky2->advertising & ADVERTISED_1000baseT_Full)
414 ct1000 |= PHY_M_1000C_AFD;
415 if (sky2->advertising & ADVERTISED_1000baseT_Half)
416 ct1000 |= PHY_M_1000C_AHD;
417 if (sky2->advertising & ADVERTISED_100baseT_Full)
418 adv |= PHY_M_AN_100_FD;
419 if (sky2->advertising & ADVERTISED_100baseT_Half)
420 adv |= PHY_M_AN_100_HD;
421 if (sky2->advertising & ADVERTISED_10baseT_Full)
422 adv |= PHY_M_AN_10_FD;
423 if (sky2->advertising & ADVERTISED_10baseT_Half)
424 adv |= PHY_M_AN_10_HD;
425
426 adv |= copper_fc_adv[sky2->flow_mode];
427 } else { /* special defines for FIBER (88E1040S only) */
428 if (sky2->advertising & ADVERTISED_1000baseT_Full)
429 adv |= PHY_M_AN_1000X_AFD;
430 if (sky2->advertising & ADVERTISED_1000baseT_Half)
431 adv |= PHY_M_AN_1000X_AHD;
432
433 adv |= fiber_fc_adv[sky2->flow_mode];
434 }
435
436 /* Restart Auto-negotiation */
437 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
438 } else {
439 /* forced speed/duplex settings */
440 ct1000 = PHY_M_1000C_MSE;
441
442 /* Disable auto update for duplex flow control and speed */
443 reg |= GM_GPCR_AU_ALL_DIS;
444
445 switch (sky2->speed) {
446 case SPEED_1000:
447 ctrl |= PHY_CT_SP1000;
448 reg |= GM_GPCR_SPEED_1000;
449 break;
450 case SPEED_100:
451 ctrl |= PHY_CT_SP100;
452 reg |= GM_GPCR_SPEED_100;
453 break;
454 }
455
456 if (sky2->duplex == DUPLEX_FULL) {
457 reg |= GM_GPCR_DUP_FULL;
458 ctrl |= PHY_CT_DUP_MD;
459 } else if (sky2->speed < SPEED_1000)
460 sky2->flow_mode = FC_NONE;
461
462
463 reg |= gm_fc_disable[sky2->flow_mode];
464
465 /* Forward pause packets to GMAC? */
466 if (sky2->flow_mode & FC_RX)
467 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
468 else
469 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
470 }
471
472 gma_write16(hw, port, GM_GP_CTRL, reg);
473
474 if (hw->flags & SKY2_HW_GIGABIT)
475 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
476
477 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
478 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
479
480 /* Setup Phy LED's */
481 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
482 ledover = 0;
483
484 switch (hw->chip_id) {
485 case CHIP_ID_YUKON_FE:
486 /* on 88E3082 these bits are at 11..9 (shifted left) */
487 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
488
489 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
490
491 /* delete ACT LED control bits */
492 ctrl &= ~PHY_M_FELP_LED1_MSK;
493 /* change ACT LED control to blink mode */
494 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
495 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
496 break;
497
498 case CHIP_ID_YUKON_FE_P:
499 /* Enable Link Partner Next Page */
500 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
501 ctrl |= PHY_M_PC_ENA_LIP_NP;
502
503 /* disable Energy Detect and enable scrambler */
504 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
505 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
506
507 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
508 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
509 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
510 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
511
512 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
513 break;
514
515 case CHIP_ID_YUKON_XL:
516 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
517
518 /* select page 3 to access LED control register */
519 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
520
521 /* set LED Function Control register */
522 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
523 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
524 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
525 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
526 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
527
528 /* set Polarity Control register */
529 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
530 (PHY_M_POLC_LS1_P_MIX(4) |
531 PHY_M_POLC_IS0_P_MIX(4) |
532 PHY_M_POLC_LOS_CTRL(2) |
533 PHY_M_POLC_INIT_CTRL(2) |
534 PHY_M_POLC_STA1_CTRL(2) |
535 PHY_M_POLC_STA0_CTRL(2)));
536
537 /* restore page register */
538 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
539 break;
540
541 case CHIP_ID_YUKON_EC_U:
542 case CHIP_ID_YUKON_EX:
543 case CHIP_ID_YUKON_SUPR:
544 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
545
546 /* select page 3 to access LED control register */
547 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
548
549 /* set LED Function Control register */
550 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
551 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
552 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
553 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
554 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
555
556 /* set Blink Rate in LED Timer Control Register */
557 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
558 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
559 /* restore page register */
560 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
561 break;
562
563 default:
564 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
565 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
566
567 /* turn off the Rx LED (LED_RX) */
568 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
569 }
570
571 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
572 /* apply fixes in PHY AFE */
573 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
574
575 /* increase differential signal amplitude in 10BASE-T */
576 gm_phy_write(hw, port, 0x18, 0xaa99);
577 gm_phy_write(hw, port, 0x17, 0x2011);
578
579 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
580 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
581 gm_phy_write(hw, port, 0x18, 0xa204);
582 gm_phy_write(hw, port, 0x17, 0x2002);
583 }
584
585 /* set page register to 0 */
586 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
587 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
588 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
589 /* apply workaround for integrated resistors calibration */
590 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
591 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
592 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
593 hw->chip_id < CHIP_ID_YUKON_SUPR) {
594 /* no effect on Yukon-XL */
595 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
596
597 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
598 /* turn on 100 Mbps LED (LED_LINK100) */
599 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
600 }
601
602 if (ledover)
603 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
604
605 }
606
607 /* Enable phy interrupt on auto-negotiation complete (or link up) */
608 if (sky2->autoneg == AUTONEG_ENABLE)
609 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
610 else
611 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
612 }
613
614 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
615 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
616
617 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
618 {
619 u32 reg1;
620
621 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
622 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
623 reg1 &= ~phy_power[port];
624
625 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
626 reg1 |= coma_mode[port];
627
628 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
629 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
630 sky2_pci_read32(hw, PCI_DEV_REG1);
631
632 if (hw->chip_id == CHIP_ID_YUKON_FE)
633 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
634 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
635 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
636 }
637
638 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
639 {
640 u32 reg1;
641 u16 ctrl;
642
643 /* release GPHY Control reset */
644 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
645
646 /* release GMAC reset */
647 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
648
649 if (hw->flags & SKY2_HW_NEWER_PHY) {
650 /* select page 2 to access MAC control register */
651 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
652
653 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
654 /* allow GMII Power Down */
655 ctrl &= ~PHY_M_MAC_GMIF_PUP;
656 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
657
658 /* set page register back to 0 */
659 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
660 }
661
662 /* setup General Purpose Control Register */
663 gma_write16(hw, port, GM_GP_CTRL,
664 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
665
666 if (hw->chip_id != CHIP_ID_YUKON_EC) {
667 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
668 /* select page 2 to access MAC control register */
669 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
670
671 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
672 /* enable Power Down */
673 ctrl |= PHY_M_PC_POW_D_ENA;
674 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
675
676 /* set page register back to 0 */
677 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
678 }
679
680 /* set IEEE compatible Power Down Mode (dev. #4.99) */
681 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
682 }
683
684 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
685 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
686 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
687 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
688 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
689 }
690
691 /* Force a renegotiation */
692 static void sky2_phy_reinit(struct sky2_port *sky2)
693 {
694 spin_lock_bh(&sky2->phy_lock);
695 sky2_phy_init(sky2->hw, sky2->port);
696 spin_unlock_bh(&sky2->phy_lock);
697 }
698
699 /* Put device in state to listen for Wake On Lan */
700 static void sky2_wol_init(struct sky2_port *sky2)
701 {
702 struct sky2_hw *hw = sky2->hw;
703 unsigned port = sky2->port;
704 enum flow_control save_mode;
705 u16 ctrl;
706 u32 reg1;
707
708 /* Bring hardware out of reset */
709 sky2_write16(hw, B0_CTST, CS_RST_CLR);
710 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
711
712 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
713 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
714
715 /* Force to 10/100
716 * sky2_reset will re-enable on resume
717 */
718 save_mode = sky2->flow_mode;
719 ctrl = sky2->advertising;
720
721 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
722 sky2->flow_mode = FC_NONE;
723
724 spin_lock_bh(&sky2->phy_lock);
725 sky2_phy_power_up(hw, port);
726 sky2_phy_init(hw, port);
727 spin_unlock_bh(&sky2->phy_lock);
728
729 sky2->flow_mode = save_mode;
730 sky2->advertising = ctrl;
731
732 /* Set GMAC to no flow control and auto update for speed/duplex */
733 gma_write16(hw, port, GM_GP_CTRL,
734 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
735 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
736
737 /* Set WOL address */
738 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
739 sky2->netdev->dev_addr, ETH_ALEN);
740
741 /* Turn on appropriate WOL control bits */
742 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
743 ctrl = 0;
744 if (sky2->wol & WAKE_PHY)
745 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
746 else
747 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
748
749 if (sky2->wol & WAKE_MAGIC)
750 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
751 else
752 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
753
754 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
755 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
756
757 /* Turn on legacy PCI-Express PME mode */
758 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
759 reg1 |= PCI_Y2_PME_LEGACY;
760 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
761
762 /* block receiver */
763 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
764
765 }
766
767 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
768 {
769 struct net_device *dev = hw->dev[port];
770
771 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
772 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
773 hw->chip_id == CHIP_ID_YUKON_FE_P ||
774 hw->chip_id == CHIP_ID_YUKON_SUPR) {
775 /* Yukon-Extreme B0 and further Extreme devices */
776 /* enable Store & Forward mode for TX */
777
778 if (dev->mtu <= ETH_DATA_LEN)
779 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
780 TX_JUMBO_DIS | TX_STFW_ENA);
781
782 else
783 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
784 TX_JUMBO_ENA| TX_STFW_ENA);
785 } else {
786 if (dev->mtu <= ETH_DATA_LEN)
787 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
788 else {
789 /* set Tx GMAC FIFO Almost Empty Threshold */
790 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
791 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
792
793 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
794
795 /* Can't do offload because of lack of store/forward */
796 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
797 }
798 }
799 }
800
801 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
802 {
803 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
804 u16 reg;
805 u32 rx_reg;
806 int i;
807 const u8 *addr = hw->dev[port]->dev_addr;
808
809 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
810 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
811
812 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
813
814 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
815 /* WA DEV_472 -- looks like crossed wires on port 2 */
816 /* clear GMAC 1 Control reset */
817 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
818 do {
819 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
820 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
821 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
822 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
823 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
824 }
825
826 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
827
828 /* Enable Transmit FIFO Underrun */
829 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
830
831 spin_lock_bh(&sky2->phy_lock);
832 sky2_phy_power_up(hw, port);
833 sky2_phy_init(hw, port);
834 spin_unlock_bh(&sky2->phy_lock);
835
836 /* MIB clear */
837 reg = gma_read16(hw, port, GM_PHY_ADDR);
838 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
839
840 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
841 gma_read16(hw, port, i);
842 gma_write16(hw, port, GM_PHY_ADDR, reg);
843
844 /* transmit control */
845 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
846
847 /* receive control reg: unicast + multicast + no FCS */
848 gma_write16(hw, port, GM_RX_CTRL,
849 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
850
851 /* transmit flow control */
852 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
853
854 /* transmit parameter */
855 gma_write16(hw, port, GM_TX_PARAM,
856 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
857 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
858 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
859 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
860
861 /* serial mode register */
862 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
863 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
864
865 if (hw->dev[port]->mtu > ETH_DATA_LEN)
866 reg |= GM_SMOD_JUMBO_ENA;
867
868 gma_write16(hw, port, GM_SERIAL_MODE, reg);
869
870 /* virtual address for data */
871 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
872
873 /* physical address: used for pause frames */
874 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
875
876 /* ignore counter overflows */
877 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
878 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
879 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
880
881 /* Configure Rx MAC FIFO */
882 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
883 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
884 if (hw->chip_id == CHIP_ID_YUKON_EX ||
885 hw->chip_id == CHIP_ID_YUKON_FE_P)
886 rx_reg |= GMF_RX_OVER_ON;
887
888 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
889
890 if (hw->chip_id == CHIP_ID_YUKON_XL) {
891 /* Hardware errata - clear flush mask */
892 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
893 } else {
894 /* Flush Rx MAC FIFO on any flow control or error */
895 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
896 }
897
898 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
899 reg = RX_GMF_FL_THR_DEF + 1;
900 /* Another magic mystery workaround from sk98lin */
901 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
902 hw->chip_rev == CHIP_REV_YU_FE2_A0)
903 reg = 0x178;
904 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
905
906 /* Configure Tx MAC FIFO */
907 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
908 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
909
910 /* On chips without ram buffer, pause is controled by MAC level */
911 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
912 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
913 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
914
915 sky2_set_tx_stfwd(hw, port);
916 }
917
918 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
919 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
920 /* disable dynamic watermark */
921 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
922 reg &= ~TX_DYN_WM_ENA;
923 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
924 }
925 }
926
927 /* Assign Ram Buffer allocation to queue */
928 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
929 {
930 u32 end;
931
932 /* convert from K bytes to qwords used for hw register */
933 start *= 1024/8;
934 space *= 1024/8;
935 end = start + space - 1;
936
937 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
938 sky2_write32(hw, RB_ADDR(q, RB_START), start);
939 sky2_write32(hw, RB_ADDR(q, RB_END), end);
940 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
941 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
942
943 if (q == Q_R1 || q == Q_R2) {
944 u32 tp = space - space/4;
945
946 /* On receive queue's set the thresholds
947 * give receiver priority when > 3/4 full
948 * send pause when down to 2K
949 */
950 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
951 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
952
953 tp = space - 2048/8;
954 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
955 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
956 } else {
957 /* Enable store & forward on Tx queue's because
958 * Tx FIFO is only 1K on Yukon
959 */
960 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
961 }
962
963 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
964 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
965 }
966
967 /* Setup Bus Memory Interface */
968 static void sky2_qset(struct sky2_hw *hw, u16 q)
969 {
970 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
971 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
972 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
973 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
974 }
975
976 /* Setup prefetch unit registers. This is the interface between
977 * hardware and driver list elements
978 */
979 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
980 u64 addr, u32 last)
981 {
982 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
983 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
984 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
985 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
986 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
987 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
988
989 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
990 }
991
992 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
993 {
994 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
995
996 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
997 le->ctrl = 0;
998 return le;
999 }
1000
1001 static void tx_init(struct sky2_port *sky2)
1002 {
1003 struct sky2_tx_le *le;
1004
1005 sky2->tx_prod = sky2->tx_cons = 0;
1006 sky2->tx_tcpsum = 0;
1007 sky2->tx_last_mss = 0;
1008
1009 le = get_tx_le(sky2);
1010 le->addr = 0;
1011 le->opcode = OP_ADDR64 | HW_OWNER;
1012 }
1013
1014 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
1015 struct sky2_tx_le *le)
1016 {
1017 return sky2->tx_ring + (le - sky2->tx_le);
1018 }
1019
1020 /* Update chip's next pointer */
1021 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1022 {
1023 /* Make sure write' to descriptors are complete before we tell hardware */
1024 wmb();
1025 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1026
1027 /* Synchronize I/O on since next processor may write to tail */
1028 mmiowb();
1029 }
1030
1031
1032 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1033 {
1034 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1035 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1036 le->ctrl = 0;
1037 return le;
1038 }
1039
1040 /* Build description to hardware for one receive segment */
1041 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1042 dma_addr_t map, unsigned len)
1043 {
1044 struct sky2_rx_le *le;
1045
1046 if (sizeof(dma_addr_t) > sizeof(u32)) {
1047 le = sky2_next_rx(sky2);
1048 le->addr = cpu_to_le32(upper_32_bits(map));
1049 le->opcode = OP_ADDR64 | HW_OWNER;
1050 }
1051
1052 le = sky2_next_rx(sky2);
1053 le->addr = cpu_to_le32((u32) map);
1054 le->length = cpu_to_le16(len);
1055 le->opcode = op | HW_OWNER;
1056 }
1057
1058 /* Build description to hardware for one possibly fragmented skb */
1059 static void sky2_rx_submit(struct sky2_port *sky2,
1060 const struct rx_ring_info *re)
1061 {
1062 int i;
1063
1064 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1065
1066 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1067 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1068 }
1069
1070
1071 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1072 unsigned size)
1073 {
1074 struct sk_buff *skb = re->skb;
1075 int i;
1076
1077 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1078 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1079 return -EIO;
1080
1081 pci_unmap_len_set(re, data_size, size);
1082
1083 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1084 re->frag_addr[i] = pci_map_page(pdev,
1085 skb_shinfo(skb)->frags[i].page,
1086 skb_shinfo(skb)->frags[i].page_offset,
1087 skb_shinfo(skb)->frags[i].size,
1088 PCI_DMA_FROMDEVICE);
1089 return 0;
1090 }
1091
1092 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1093 {
1094 struct sk_buff *skb = re->skb;
1095 int i;
1096
1097 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1098 PCI_DMA_FROMDEVICE);
1099
1100 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1101 pci_unmap_page(pdev, re->frag_addr[i],
1102 skb_shinfo(skb)->frags[i].size,
1103 PCI_DMA_FROMDEVICE);
1104 }
1105
1106 /* Tell chip where to start receive checksum.
1107 * Actually has two checksums, but set both same to avoid possible byte
1108 * order problems.
1109 */
1110 static void rx_set_checksum(struct sky2_port *sky2)
1111 {
1112 struct sky2_rx_le *le = sky2_next_rx(sky2);
1113
1114 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1115 le->ctrl = 0;
1116 le->opcode = OP_TCPSTART | HW_OWNER;
1117
1118 sky2_write32(sky2->hw,
1119 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1120 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1121 }
1122
1123 /*
1124 * The RX Stop command will not work for Yukon-2 if the BMU does not
1125 * reach the end of packet and since we can't make sure that we have
1126 * incoming data, we must reset the BMU while it is not doing a DMA
1127 * transfer. Since it is possible that the RX path is still active,
1128 * the RX RAM buffer will be stopped first, so any possible incoming
1129 * data will not trigger a DMA. After the RAM buffer is stopped, the
1130 * BMU is polled until any DMA in progress is ended and only then it
1131 * will be reset.
1132 */
1133 static void sky2_rx_stop(struct sky2_port *sky2)
1134 {
1135 struct sky2_hw *hw = sky2->hw;
1136 unsigned rxq = rxqaddr[sky2->port];
1137 int i;
1138
1139 /* disable the RAM Buffer receive queue */
1140 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1141
1142 for (i = 0; i < 0xffff; i++)
1143 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1144 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1145 goto stopped;
1146
1147 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1148 sky2->netdev->name);
1149 stopped:
1150 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1151
1152 /* reset the Rx prefetch unit */
1153 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1154
1155 /* Reset the RAM Buffer receive queue */
1156 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_RST_SET);
1157
1158 /* Reset Rx MAC FIFO */
1159 sky2_write8(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), GMF_RST_SET);
1160
1161 sky2_read8(hw, B0_CTST);
1162 }
1163
1164 /* Clean out receive buffer area, assumes receiver hardware stopped */
1165 static void sky2_rx_clean(struct sky2_port *sky2)
1166 {
1167 unsigned i;
1168
1169 memset(sky2->rx_le, 0, RX_LE_BYTES);
1170 for (i = 0; i < sky2->rx_pending; i++) {
1171 struct rx_ring_info *re = sky2->rx_ring + i;
1172
1173 if (re->skb) {
1174 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1175 kfree_skb(re->skb);
1176 re->skb = NULL;
1177 }
1178 }
1179 }
1180
1181 /* Basic MII support */
1182 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1183 {
1184 struct mii_ioctl_data *data = if_mii(ifr);
1185 struct sky2_port *sky2 = netdev_priv(dev);
1186 struct sky2_hw *hw = sky2->hw;
1187 int err = -EOPNOTSUPP;
1188
1189 if (!netif_running(dev))
1190 return -ENODEV; /* Phy still in reset */
1191
1192 switch (cmd) {
1193 case SIOCGMIIPHY:
1194 data->phy_id = PHY_ADDR_MARV;
1195
1196 /* fallthru */
1197 case SIOCGMIIREG: {
1198 u16 val = 0;
1199
1200 spin_lock_bh(&sky2->phy_lock);
1201 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1202 spin_unlock_bh(&sky2->phy_lock);
1203
1204 data->val_out = val;
1205 break;
1206 }
1207
1208 case SIOCSMIIREG:
1209 if (!capable(CAP_NET_ADMIN))
1210 return -EPERM;
1211
1212 spin_lock_bh(&sky2->phy_lock);
1213 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1214 data->val_in);
1215 spin_unlock_bh(&sky2->phy_lock);
1216 break;
1217 }
1218 return err;
1219 }
1220
1221 #ifdef SKY2_VLAN_TAG_USED
1222 static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
1223 {
1224 if (onoff) {
1225 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1226 RX_VLAN_STRIP_ON);
1227 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1228 TX_VLAN_TAG_ON);
1229 } else {
1230 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1231 RX_VLAN_STRIP_OFF);
1232 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1233 TX_VLAN_TAG_OFF);
1234 }
1235 }
1236
1237 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1238 {
1239 struct sky2_port *sky2 = netdev_priv(dev);
1240 struct sky2_hw *hw = sky2->hw;
1241 u16 port = sky2->port;
1242
1243 netif_tx_lock_bh(dev);
1244 napi_disable(&hw->napi);
1245
1246 sky2->vlgrp = grp;
1247 sky2_set_vlan_mode(hw, port, grp != NULL);
1248
1249 sky2_read32(hw, B0_Y2_SP_LISR);
1250 napi_enable(&hw->napi);
1251 netif_tx_unlock_bh(dev);
1252 }
1253 #endif
1254
1255 /*
1256 * Allocate an skb for receiving. If the MTU is large enough
1257 * make the skb non-linear with a fragment list of pages.
1258 */
1259 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1260 {
1261 struct sk_buff *skb;
1262 int i;
1263
1264 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1265 unsigned char *start;
1266 /*
1267 * Workaround for a bug in FIFO that cause hang
1268 * if the FIFO if the receive buffer is not 64 byte aligned.
1269 * The buffer returned from netdev_alloc_skb is
1270 * aligned except if slab debugging is enabled.
1271 */
1272 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
1273 if (!skb)
1274 goto nomem;
1275 start = PTR_ALIGN(skb->data, 8);
1276 skb_reserve(skb, start - skb->data);
1277 } else {
1278 skb = netdev_alloc_skb(sky2->netdev,
1279 sky2->rx_data_size + NET_IP_ALIGN);
1280 if (!skb)
1281 goto nomem;
1282 skb_reserve(skb, NET_IP_ALIGN);
1283 }
1284
1285 for (i = 0; i < sky2->rx_nfrags; i++) {
1286 struct page *page = alloc_page(GFP_ATOMIC);
1287
1288 if (!page)
1289 goto free_partial;
1290 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1291 }
1292
1293 return skb;
1294 free_partial:
1295 kfree_skb(skb);
1296 nomem:
1297 return NULL;
1298 }
1299
1300 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1301 {
1302 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1303 }
1304
1305 /*
1306 * Allocate and setup receiver buffer pool.
1307 * Normal case this ends up creating one list element for skb
1308 * in the receive ring. Worst case if using large MTU and each
1309 * allocation falls on a different 64 bit region, that results
1310 * in 6 list elements per ring entry.
1311 * One element is used for checksum enable/disable, and one
1312 * extra to avoid wrap.
1313 */
1314 static int sky2_rx_start(struct sky2_port *sky2)
1315 {
1316 struct sky2_hw *hw = sky2->hw;
1317 struct rx_ring_info *re;
1318 unsigned rxq = rxqaddr[sky2->port];
1319 unsigned i, size, thresh;
1320
1321 sky2->rx_put = sky2->rx_next = 0;
1322 sky2_qset(hw, rxq);
1323
1324 /* On PCI express lowering the watermark gives better performance */
1325 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1326 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1327
1328 /* These chips have no ram buffer?
1329 * MAC Rx RAM Read is controlled by hardware */
1330 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1331 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1332 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1333 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1334
1335 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1336
1337 if (!(hw->flags & SKY2_HW_NEW_LE))
1338 rx_set_checksum(sky2);
1339
1340 /* Space needed for frame data + headers rounded up */
1341 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1342
1343 /* Stopping point for hardware truncation */
1344 thresh = (size - 8) / sizeof(u32);
1345
1346 sky2->rx_nfrags = size >> PAGE_SHIFT;
1347 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1348
1349 /* Compute residue after pages */
1350 size -= sky2->rx_nfrags << PAGE_SHIFT;
1351
1352 /* Optimize to handle small packets and headers */
1353 if (size < copybreak)
1354 size = copybreak;
1355 if (size < ETH_HLEN)
1356 size = ETH_HLEN;
1357
1358 sky2->rx_data_size = size;
1359
1360 /* Fill Rx ring */
1361 for (i = 0; i < sky2->rx_pending; i++) {
1362 re = sky2->rx_ring + i;
1363
1364 re->skb = sky2_rx_alloc(sky2);
1365 if (!re->skb)
1366 goto nomem;
1367
1368 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1369 dev_kfree_skb(re->skb);
1370 re->skb = NULL;
1371 goto nomem;
1372 }
1373
1374 sky2_rx_submit(sky2, re);
1375 }
1376
1377 /*
1378 * The receiver hangs if it receives frames larger than the
1379 * packet buffer. As a workaround, truncate oversize frames, but
1380 * the register is limited to 9 bits, so if you do frames > 2052
1381 * you better get the MTU right!
1382 */
1383 if (thresh > 0x1ff)
1384 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1385 else {
1386 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1387 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1388 }
1389
1390 /* Tell chip about available buffers */
1391 sky2_rx_update(sky2, rxq);
1392 return 0;
1393 nomem:
1394 sky2_rx_clean(sky2);
1395 return -ENOMEM;
1396 }
1397
1398 /* Bring up network interface. */
1399 static int sky2_up(struct net_device *dev)
1400 {
1401 struct sky2_port *sky2 = netdev_priv(dev);
1402 struct sky2_hw *hw = sky2->hw;
1403 unsigned port = sky2->port;
1404 u32 imask, ramsize;
1405 int cap, err = -ENOMEM;
1406 struct net_device *otherdev = hw->dev[sky2->port^1];
1407
1408 /*
1409 * On dual port PCI-X card, there is an problem where status
1410 * can be received out of order due to split transactions
1411 */
1412 if (otherdev && netif_running(otherdev) &&
1413 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1414 u16 cmd;
1415
1416 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1417 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1418 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1419
1420 }
1421
1422 netif_carrier_off(dev);
1423
1424 /* must be power of 2 */
1425 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1426 TX_RING_SIZE *
1427 sizeof(struct sky2_tx_le),
1428 &sky2->tx_le_map);
1429 if (!sky2->tx_le)
1430 goto err_out;
1431
1432 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1433 GFP_KERNEL);
1434 if (!sky2->tx_ring)
1435 goto err_out;
1436
1437 tx_init(sky2);
1438
1439 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1440 &sky2->rx_le_map);
1441 if (!sky2->rx_le)
1442 goto err_out;
1443 memset(sky2->rx_le, 0, RX_LE_BYTES);
1444
1445 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1446 GFP_KERNEL);
1447 if (!sky2->rx_ring)
1448 goto err_out;
1449
1450 sky2_mac_init(hw, port);
1451
1452 /* Register is number of 4K blocks on internal RAM buffer. */
1453 ramsize = sky2_read8(hw, B2_E_0) * 4;
1454 if (ramsize > 0) {
1455 u32 rxspace;
1456
1457 hw->flags |= SKY2_HW_RAM_BUFFER;
1458 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1459 if (ramsize < 16)
1460 rxspace = ramsize / 2;
1461 else
1462 rxspace = 8 + (2*(ramsize - 16))/3;
1463
1464 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1465 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1466
1467 /* Make sure SyncQ is disabled */
1468 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1469 RB_RST_SET);
1470 }
1471
1472 sky2_qset(hw, txqaddr[port]);
1473
1474 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1475 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1476 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1477
1478 /* Set almost empty threshold */
1479 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1480 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1481 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1482
1483 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1484 TX_RING_SIZE - 1);
1485
1486 #ifdef SKY2_VLAN_TAG_USED
1487 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1488 #endif
1489
1490 err = sky2_rx_start(sky2);
1491 if (err)
1492 goto err_out;
1493
1494 /* Enable interrupts from phy/mac for port */
1495 imask = sky2_read32(hw, B0_IMSK);
1496 imask |= portirq_msk[port];
1497 sky2_write32(hw, B0_IMSK, imask);
1498 sky2_read32(hw, B0_IMSK);
1499
1500 sky2_set_multicast(dev);
1501
1502 if (netif_msg_ifup(sky2))
1503 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1504 return 0;
1505
1506 err_out:
1507 if (sky2->rx_le) {
1508 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1509 sky2->rx_le, sky2->rx_le_map);
1510 sky2->rx_le = NULL;
1511 }
1512 if (sky2->tx_le) {
1513 pci_free_consistent(hw->pdev,
1514 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1515 sky2->tx_le, sky2->tx_le_map);
1516 sky2->tx_le = NULL;
1517 }
1518 kfree(sky2->tx_ring);
1519 kfree(sky2->rx_ring);
1520
1521 sky2->tx_ring = NULL;
1522 sky2->rx_ring = NULL;
1523 return err;
1524 }
1525
1526 /* Modular subtraction in ring */
1527 static inline int tx_dist(unsigned tail, unsigned head)
1528 {
1529 return (head - tail) & (TX_RING_SIZE - 1);
1530 }
1531
1532 /* Number of list elements available for next tx */
1533 static inline int tx_avail(const struct sky2_port *sky2)
1534 {
1535 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1536 }
1537
1538 /* Estimate of number of transmit list elements required */
1539 static unsigned tx_le_req(const struct sk_buff *skb)
1540 {
1541 unsigned count;
1542
1543 count = sizeof(dma_addr_t) / sizeof(u32);
1544 count += skb_shinfo(skb)->nr_frags * count;
1545
1546 if (skb_is_gso(skb))
1547 ++count;
1548
1549 if (skb->ip_summed == CHECKSUM_PARTIAL)
1550 ++count;
1551
1552 return count;
1553 }
1554
1555 /*
1556 * Put one packet in ring for transmit.
1557 * A single packet can generate multiple list elements, and
1558 * the number of ring elements will probably be less than the number
1559 * of list elements used.
1560 */
1561 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1562 {
1563 struct sky2_port *sky2 = netdev_priv(dev);
1564 struct sky2_hw *hw = sky2->hw;
1565 struct sky2_tx_le *le = NULL;
1566 struct tx_ring_info *re;
1567 unsigned i, len, first_slot;
1568 dma_addr_t mapping;
1569 u16 mss;
1570 u8 ctrl;
1571
1572 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1573 return NETDEV_TX_BUSY;
1574
1575 len = skb_headlen(skb);
1576 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1577
1578 if (pci_dma_mapping_error(hw->pdev, mapping))
1579 goto mapping_error;
1580
1581 first_slot = sky2->tx_prod;
1582 if (unlikely(netif_msg_tx_queued(sky2)))
1583 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1584 dev->name, first_slot, skb->len);
1585
1586 /* Send high bits if needed */
1587 if (sizeof(dma_addr_t) > sizeof(u32)) {
1588 le = get_tx_le(sky2);
1589 le->addr = cpu_to_le32(upper_32_bits(mapping));
1590 le->opcode = OP_ADDR64 | HW_OWNER;
1591 }
1592
1593 /* Check for TCP Segmentation Offload */
1594 mss = skb_shinfo(skb)->gso_size;
1595 if (mss != 0) {
1596
1597 if (!(hw->flags & SKY2_HW_NEW_LE))
1598 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1599
1600 if (mss != sky2->tx_last_mss) {
1601 le = get_tx_le(sky2);
1602 le->addr = cpu_to_le32(mss);
1603
1604 if (hw->flags & SKY2_HW_NEW_LE)
1605 le->opcode = OP_MSS | HW_OWNER;
1606 else
1607 le->opcode = OP_LRGLEN | HW_OWNER;
1608 sky2->tx_last_mss = mss;
1609 }
1610 }
1611
1612 ctrl = 0;
1613 #ifdef SKY2_VLAN_TAG_USED
1614 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1615 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1616 if (!le) {
1617 le = get_tx_le(sky2);
1618 le->addr = 0;
1619 le->opcode = OP_VLAN|HW_OWNER;
1620 } else
1621 le->opcode |= OP_VLAN;
1622 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1623 ctrl |= INS_VLAN;
1624 }
1625 #endif
1626
1627 /* Handle TCP checksum offload */
1628 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1629 /* On Yukon EX (some versions) encoding change. */
1630 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1631 ctrl |= CALSUM; /* auto checksum */
1632 else {
1633 const unsigned offset = skb_transport_offset(skb);
1634 u32 tcpsum;
1635
1636 tcpsum = offset << 16; /* sum start */
1637 tcpsum |= offset + skb->csum_offset; /* sum write */
1638
1639 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1640 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1641 ctrl |= UDPTCP;
1642
1643 if (tcpsum != sky2->tx_tcpsum) {
1644 sky2->tx_tcpsum = tcpsum;
1645
1646 le = get_tx_le(sky2);
1647 le->addr = cpu_to_le32(tcpsum);
1648 le->length = 0; /* initial checksum value */
1649 le->ctrl = 1; /* one packet */
1650 le->opcode = OP_TCPLISW | HW_OWNER;
1651 }
1652 }
1653 }
1654
1655 le = get_tx_le(sky2);
1656 le->addr = cpu_to_le32((u32) mapping);
1657 le->length = cpu_to_le16(len);
1658 le->ctrl = ctrl;
1659 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1660
1661 re = tx_le_re(sky2, le);
1662 re->skb = skb;
1663 pci_unmap_addr_set(re, mapaddr, mapping);
1664 pci_unmap_len_set(re, maplen, len);
1665
1666 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1667 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1668
1669 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1670 frag->size, PCI_DMA_TODEVICE);
1671
1672 if (pci_dma_mapping_error(hw->pdev, mapping))
1673 goto mapping_unwind;
1674
1675 if (sizeof(dma_addr_t) > sizeof(u32)) {
1676 le = get_tx_le(sky2);
1677 le->addr = cpu_to_le32(upper_32_bits(mapping));
1678 le->ctrl = 0;
1679 le->opcode = OP_ADDR64 | HW_OWNER;
1680 }
1681
1682 le = get_tx_le(sky2);
1683 le->addr = cpu_to_le32((u32) mapping);
1684 le->length = cpu_to_le16(frag->size);
1685 le->ctrl = ctrl;
1686 le->opcode = OP_BUFFER | HW_OWNER;
1687
1688 re = tx_le_re(sky2, le);
1689 re->skb = skb;
1690 pci_unmap_addr_set(re, mapaddr, mapping);
1691 pci_unmap_len_set(re, maplen, frag->size);
1692 }
1693
1694 le->ctrl |= EOP;
1695
1696 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1697 netif_stop_queue(dev);
1698
1699 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1700
1701 return NETDEV_TX_OK;
1702
1703 mapping_unwind:
1704 for (i = first_slot; i != sky2->tx_prod; i = RING_NEXT(i, TX_RING_SIZE)) {
1705 le = sky2->tx_le + i;
1706 re = sky2->tx_ring + i;
1707
1708 switch(le->opcode & ~HW_OWNER) {
1709 case OP_LARGESEND:
1710 case OP_PACKET:
1711 pci_unmap_single(hw->pdev,
1712 pci_unmap_addr(re, mapaddr),
1713 pci_unmap_len(re, maplen),
1714 PCI_DMA_TODEVICE);
1715 break;
1716 case OP_BUFFER:
1717 pci_unmap_page(hw->pdev, pci_unmap_addr(re, mapaddr),
1718 pci_unmap_len(re, maplen),
1719 PCI_DMA_TODEVICE);
1720 break;
1721 }
1722 }
1723
1724 sky2->tx_prod = first_slot;
1725 mapping_error:
1726 if (net_ratelimit())
1727 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1728 dev_kfree_skb(skb);
1729 return NETDEV_TX_OK;
1730 }
1731
1732 /*
1733 * Free ring elements from starting at tx_cons until "done"
1734 *
1735 * NB: the hardware will tell us about partial completion of multi-part
1736 * buffers so make sure not to free skb to early.
1737 */
1738 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1739 {
1740 struct net_device *dev = sky2->netdev;
1741 struct pci_dev *pdev = sky2->hw->pdev;
1742 unsigned idx;
1743
1744 BUG_ON(done >= TX_RING_SIZE);
1745
1746 for (idx = sky2->tx_cons; idx != done;
1747 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1748 struct sky2_tx_le *le = sky2->tx_le + idx;
1749 struct tx_ring_info *re = sky2->tx_ring + idx;
1750
1751 switch(le->opcode & ~HW_OWNER) {
1752 case OP_LARGESEND:
1753 case OP_PACKET:
1754 pci_unmap_single(pdev,
1755 pci_unmap_addr(re, mapaddr),
1756 pci_unmap_len(re, maplen),
1757 PCI_DMA_TODEVICE);
1758 break;
1759 case OP_BUFFER:
1760 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1761 pci_unmap_len(re, maplen),
1762 PCI_DMA_TODEVICE);
1763 break;
1764 }
1765
1766 if (le->ctrl & EOP) {
1767 if (unlikely(netif_msg_tx_done(sky2)))
1768 printk(KERN_DEBUG "%s: tx done %u\n",
1769 dev->name, idx);
1770
1771 dev->stats.tx_packets++;
1772 dev->stats.tx_bytes += re->skb->len;
1773
1774 dev_kfree_skb_any(re->skb);
1775 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1776 }
1777 }
1778
1779 sky2->tx_cons = idx;
1780 smp_mb();
1781
1782 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1783 netif_wake_queue(dev);
1784 }
1785
1786 /* Cleanup all untransmitted buffers, assume transmitter not running */
1787 static void sky2_tx_clean(struct net_device *dev)
1788 {
1789 struct sky2_port *sky2 = netdev_priv(dev);
1790
1791 netif_tx_lock_bh(dev);
1792 sky2_tx_complete(sky2, sky2->tx_prod);
1793 netif_tx_unlock_bh(dev);
1794 }
1795
1796 /* Network shutdown */
1797 static int sky2_down(struct net_device *dev)
1798 {
1799 struct sky2_port *sky2 = netdev_priv(dev);
1800 struct sky2_hw *hw = sky2->hw;
1801 unsigned port = sky2->port;
1802 u16 ctrl;
1803 u32 imask;
1804
1805 /* Never really got started! */
1806 if (!sky2->tx_le)
1807 return 0;
1808
1809 if (netif_msg_ifdown(sky2))
1810 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1811
1812 /* Disable port IRQ */
1813 imask = sky2_read32(hw, B0_IMSK);
1814 imask &= ~portirq_msk[port];
1815 sky2_write32(hw, B0_IMSK, imask);
1816 sky2_read32(hw, B0_IMSK);
1817
1818 synchronize_irq(hw->pdev->irq);
1819
1820 /* Force flow control off */
1821 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1822
1823 /* Stop transmitter */
1824 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1825 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1826
1827 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1828 RB_RST_SET | RB_DIS_OP_MD);
1829
1830 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1831 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1832 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1833
1834 /* Make sure no packets are pending */
1835 napi_synchronize(&hw->napi);
1836
1837 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1838
1839 /* Workaround shared GMAC reset */
1840 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1841 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1842 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1843
1844 /* Disable Force Sync bit and Enable Alloc bit */
1845 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1846 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1847
1848 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1849 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1850 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1851
1852 /* Reset the PCI FIFO of the async Tx queue */
1853 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1854 BMU_RST_SET | BMU_FIFO_RST);
1855
1856 /* Reset the Tx prefetch units */
1857 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1858 PREF_UNIT_RST_SET);
1859
1860 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1861
1862 sky2_rx_stop(sky2);
1863
1864 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1865 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1866
1867 sky2_phy_power_down(hw, port);
1868
1869 /* turn off LED's */
1870 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1871
1872 sky2_tx_clean(dev);
1873 sky2_rx_clean(sky2);
1874
1875 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1876 sky2->rx_le, sky2->rx_le_map);
1877 kfree(sky2->rx_ring);
1878
1879 pci_free_consistent(hw->pdev,
1880 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1881 sky2->tx_le, sky2->tx_le_map);
1882 kfree(sky2->tx_ring);
1883
1884 sky2->tx_le = NULL;
1885 sky2->rx_le = NULL;
1886
1887 sky2->rx_ring = NULL;
1888 sky2->tx_ring = NULL;
1889
1890 return 0;
1891 }
1892
1893 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1894 {
1895 if (hw->flags & SKY2_HW_FIBRE_PHY)
1896 return SPEED_1000;
1897
1898 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1899 if (aux & PHY_M_PS_SPEED_100)
1900 return SPEED_100;
1901 else
1902 return SPEED_10;
1903 }
1904
1905 switch (aux & PHY_M_PS_SPEED_MSK) {
1906 case PHY_M_PS_SPEED_1000:
1907 return SPEED_1000;
1908 case PHY_M_PS_SPEED_100:
1909 return SPEED_100;
1910 default:
1911 return SPEED_10;
1912 }
1913 }
1914
1915 static void sky2_link_up(struct sky2_port *sky2)
1916 {
1917 struct sky2_hw *hw = sky2->hw;
1918 unsigned port = sky2->port;
1919 u16 reg;
1920 static const char *fc_name[] = {
1921 [FC_NONE] = "none",
1922 [FC_TX] = "tx",
1923 [FC_RX] = "rx",
1924 [FC_BOTH] = "both",
1925 };
1926
1927 /* enable Rx/Tx */
1928 reg = gma_read16(hw, port, GM_GP_CTRL);
1929 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1930 gma_write16(hw, port, GM_GP_CTRL, reg);
1931
1932 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1933
1934 netif_carrier_on(sky2->netdev);
1935
1936 mod_timer(&hw->watchdog_timer, jiffies + 1);
1937
1938 /* Turn on link LED */
1939 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1940 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1941
1942 if (netif_msg_link(sky2))
1943 printk(KERN_INFO PFX
1944 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1945 sky2->netdev->name, sky2->speed,
1946 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1947 fc_name[sky2->flow_status]);
1948 }
1949
1950 static void sky2_link_down(struct sky2_port *sky2)
1951 {
1952 struct sky2_hw *hw = sky2->hw;
1953 unsigned port = sky2->port;
1954 u16 reg;
1955
1956 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1957
1958 reg = gma_read16(hw, port, GM_GP_CTRL);
1959 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1960 gma_write16(hw, port, GM_GP_CTRL, reg);
1961
1962 netif_carrier_off(sky2->netdev);
1963
1964 /* Turn on link LED */
1965 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1966
1967 if (netif_msg_link(sky2))
1968 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1969
1970 sky2_phy_init(hw, port);
1971 }
1972
1973 static enum flow_control sky2_flow(int rx, int tx)
1974 {
1975 if (rx)
1976 return tx ? FC_BOTH : FC_RX;
1977 else
1978 return tx ? FC_TX : FC_NONE;
1979 }
1980
1981 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1982 {
1983 struct sky2_hw *hw = sky2->hw;
1984 unsigned port = sky2->port;
1985 u16 advert, lpa;
1986
1987 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1988 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1989 if (lpa & PHY_M_AN_RF) {
1990 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1991 return -1;
1992 }
1993
1994 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1995 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1996 sky2->netdev->name);
1997 return -1;
1998 }
1999
2000 sky2->speed = sky2_phy_speed(hw, aux);
2001 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2002
2003 /* Since the pause result bits seem to in different positions on
2004 * different chips. look at registers.
2005 */
2006 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2007 /* Shift for bits in fiber PHY */
2008 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2009 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2010
2011 if (advert & ADVERTISE_1000XPAUSE)
2012 advert |= ADVERTISE_PAUSE_CAP;
2013 if (advert & ADVERTISE_1000XPSE_ASYM)
2014 advert |= ADVERTISE_PAUSE_ASYM;
2015 if (lpa & LPA_1000XPAUSE)
2016 lpa |= LPA_PAUSE_CAP;
2017 if (lpa & LPA_1000XPAUSE_ASYM)
2018 lpa |= LPA_PAUSE_ASYM;
2019 }
2020
2021 sky2->flow_status = FC_NONE;
2022 if (advert & ADVERTISE_PAUSE_CAP) {
2023 if (lpa & LPA_PAUSE_CAP)
2024 sky2->flow_status = FC_BOTH;
2025 else if (advert & ADVERTISE_PAUSE_ASYM)
2026 sky2->flow_status = FC_RX;
2027 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2028 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2029 sky2->flow_status = FC_TX;
2030 }
2031
2032 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
2033 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2034 sky2->flow_status = FC_NONE;
2035
2036 if (sky2->flow_status & FC_TX)
2037 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2038 else
2039 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2040
2041 return 0;
2042 }
2043
2044 /* Interrupt from PHY */
2045 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2046 {
2047 struct net_device *dev = hw->dev[port];
2048 struct sky2_port *sky2 = netdev_priv(dev);
2049 u16 istatus, phystat;
2050
2051 if (!netif_running(dev))
2052 return;
2053
2054 spin_lock(&sky2->phy_lock);
2055 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2056 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2057
2058 if (netif_msg_intr(sky2))
2059 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2060 sky2->netdev->name, istatus, phystat);
2061
2062 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
2063 if (sky2_autoneg_done(sky2, phystat) == 0)
2064 sky2_link_up(sky2);
2065 goto out;
2066 }
2067
2068 if (istatus & PHY_M_IS_LSP_CHANGE)
2069 sky2->speed = sky2_phy_speed(hw, phystat);
2070
2071 if (istatus & PHY_M_IS_DUP_CHANGE)
2072 sky2->duplex =
2073 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2074
2075 if (istatus & PHY_M_IS_LST_CHANGE) {
2076 if (phystat & PHY_M_PS_LINK_UP)
2077 sky2_link_up(sky2);
2078 else
2079 sky2_link_down(sky2);
2080 }
2081 out:
2082 spin_unlock(&sky2->phy_lock);
2083 }
2084
2085 /* Transmit timeout is only called if we are running, carrier is up
2086 * and tx queue is full (stopped).
2087 */
2088 static void sky2_tx_timeout(struct net_device *dev)
2089 {
2090 struct sky2_port *sky2 = netdev_priv(dev);
2091 struct sky2_hw *hw = sky2->hw;
2092
2093 if (netif_msg_timer(sky2))
2094 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2095
2096 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
2097 dev->name, sky2->tx_cons, sky2->tx_prod,
2098 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2099 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2100
2101 /* can't restart safely under softirq */
2102 schedule_work(&hw->restart_work);
2103 }
2104
2105 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2106 {
2107 struct sky2_port *sky2 = netdev_priv(dev);
2108 struct sky2_hw *hw = sky2->hw;
2109 unsigned port = sky2->port;
2110 int err;
2111 u16 ctl, mode;
2112 u32 imask;
2113
2114 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2115 return -EINVAL;
2116
2117 if (new_mtu > ETH_DATA_LEN &&
2118 (hw->chip_id == CHIP_ID_YUKON_FE ||
2119 hw->chip_id == CHIP_ID_YUKON_FE_P))
2120 return -EINVAL;
2121
2122 if (!netif_running(dev)) {
2123 dev->mtu = new_mtu;
2124 return 0;
2125 }
2126
2127 imask = sky2_read32(hw, B0_IMSK);
2128 sky2_write32(hw, B0_IMSK, 0);
2129
2130 dev->trans_start = jiffies; /* prevent tx timeout */
2131 netif_stop_queue(dev);
2132 napi_disable(&hw->napi);
2133
2134 synchronize_irq(hw->pdev->irq);
2135
2136 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2137 sky2_set_tx_stfwd(hw, port);
2138
2139 ctl = gma_read16(hw, port, GM_GP_CTRL);
2140 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2141 sky2_rx_stop(sky2);
2142 sky2_rx_clean(sky2);
2143
2144 dev->mtu = new_mtu;
2145
2146 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2147 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2148
2149 if (dev->mtu > ETH_DATA_LEN)
2150 mode |= GM_SMOD_JUMBO_ENA;
2151
2152 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2153
2154 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2155
2156 err = sky2_rx_start(sky2);
2157 sky2_write32(hw, B0_IMSK, imask);
2158
2159 sky2_read32(hw, B0_Y2_SP_LISR);
2160 napi_enable(&hw->napi);
2161
2162 if (err)
2163 dev_close(dev);
2164 else {
2165 gma_write16(hw, port, GM_GP_CTRL, ctl);
2166
2167 netif_wake_queue(dev);
2168 }
2169
2170 return err;
2171 }
2172
2173 /* For small just reuse existing skb for next receive */
2174 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2175 const struct rx_ring_info *re,
2176 unsigned length)
2177 {
2178 struct sk_buff *skb;
2179
2180 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2181 if (likely(skb)) {
2182 skb_reserve(skb, 2);
2183 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2184 length, PCI_DMA_FROMDEVICE);
2185 skb_copy_from_linear_data(re->skb, skb->data, length);
2186 skb->ip_summed = re->skb->ip_summed;
2187 skb->csum = re->skb->csum;
2188 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2189 length, PCI_DMA_FROMDEVICE);
2190 re->skb->ip_summed = CHECKSUM_NONE;
2191 skb_put(skb, length);
2192 }
2193 return skb;
2194 }
2195
2196 /* Adjust length of skb with fragments to match received data */
2197 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2198 unsigned int length)
2199 {
2200 int i, num_frags;
2201 unsigned int size;
2202
2203 /* put header into skb */
2204 size = min(length, hdr_space);
2205 skb->tail += size;
2206 skb->len += size;
2207 length -= size;
2208
2209 num_frags = skb_shinfo(skb)->nr_frags;
2210 for (i = 0; i < num_frags; i++) {
2211 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2212
2213 if (length == 0) {
2214 /* don't need this page */
2215 __free_page(frag->page);
2216 --skb_shinfo(skb)->nr_frags;
2217 } else {
2218 size = min(length, (unsigned) PAGE_SIZE);
2219
2220 frag->size = size;
2221 skb->data_len += size;
2222 skb->truesize += size;
2223 skb->len += size;
2224 length -= size;
2225 }
2226 }
2227 }
2228
2229 /* Normal packet - take skb from ring element and put in a new one */
2230 static struct sk_buff *receive_new(struct sky2_port *sky2,
2231 struct rx_ring_info *re,
2232 unsigned int length)
2233 {
2234 struct sk_buff *skb, *nskb;
2235 unsigned hdr_space = sky2->rx_data_size;
2236
2237 /* Don't be tricky about reusing pages (yet) */
2238 nskb = sky2_rx_alloc(sky2);
2239 if (unlikely(!nskb))
2240 return NULL;
2241
2242 skb = re->skb;
2243 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2244
2245 prefetch(skb->data);
2246 re->skb = nskb;
2247 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2248 dev_kfree_skb(nskb);
2249 re->skb = skb;
2250 return NULL;
2251 }
2252
2253 if (skb_shinfo(skb)->nr_frags)
2254 skb_put_frags(skb, hdr_space, length);
2255 else
2256 skb_put(skb, length);
2257 return skb;
2258 }
2259
2260 /*
2261 * Receive one packet.
2262 * For larger packets, get new buffer.
2263 */
2264 static struct sk_buff *sky2_receive(struct net_device *dev,
2265 u16 length, u32 status)
2266 {
2267 struct sky2_port *sky2 = netdev_priv(dev);
2268 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2269 struct sk_buff *skb = NULL;
2270 u16 count = (status & GMR_FS_LEN) >> 16;
2271
2272 #ifdef SKY2_VLAN_TAG_USED
2273 /* Account for vlan tag */
2274 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2275 count -= VLAN_HLEN;
2276 #endif
2277
2278 if (unlikely(netif_msg_rx_status(sky2)))
2279 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2280 dev->name, sky2->rx_next, status, length);
2281
2282 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2283 prefetch(sky2->rx_ring + sky2->rx_next);
2284
2285 /* This chip has hardware problems that generates bogus status.
2286 * So do only marginal checking and expect higher level protocols
2287 * to handle crap frames.
2288 */
2289 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2290 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2291 length != count)
2292 goto okay;
2293
2294 if (status & GMR_FS_ANY_ERR)
2295 goto error;
2296
2297 if (!(status & GMR_FS_RX_OK))
2298 goto resubmit;
2299
2300 /* if length reported by DMA does not match PHY, packet was truncated */
2301 if (length != count)
2302 goto len_error;
2303
2304 okay:
2305 if (length < copybreak)
2306 skb = receive_copy(sky2, re, length);
2307 else
2308 skb = receive_new(sky2, re, length);
2309 resubmit:
2310 sky2_rx_submit(sky2, re);
2311
2312 return skb;
2313
2314 len_error:
2315 /* Truncation of overlength packets
2316 causes PHY length to not match MAC length */
2317 ++dev->stats.rx_length_errors;
2318 if (netif_msg_rx_err(sky2) && net_ratelimit())
2319 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2320 dev->name, status, length);
2321 goto resubmit;
2322
2323 error:
2324 ++dev->stats.rx_errors;
2325 if (status & GMR_FS_RX_FF_OV) {
2326 dev->stats.rx_over_errors++;
2327 goto resubmit;
2328 }
2329
2330 if (netif_msg_rx_err(sky2) && net_ratelimit())
2331 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2332 dev->name, status, length);
2333
2334 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2335 dev->stats.rx_length_errors++;
2336 if (status & GMR_FS_FRAGMENT)
2337 dev->stats.rx_frame_errors++;
2338 if (status & GMR_FS_CRC_ERR)
2339 dev->stats.rx_crc_errors++;
2340
2341 goto resubmit;
2342 }
2343
2344 /* Transmit complete */
2345 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2346 {
2347 struct sky2_port *sky2 = netdev_priv(dev);
2348
2349 if (netif_running(dev)) {
2350 netif_tx_lock(dev);
2351 sky2_tx_complete(sky2, last);
2352 netif_tx_unlock(dev);
2353 }
2354 }
2355
2356 /* Process status response ring */
2357 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2358 {
2359 int work_done = 0;
2360 unsigned rx[2] = { 0, 0 };
2361
2362 rmb();
2363 do {
2364 struct sky2_port *sky2;
2365 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2366 unsigned port;
2367 struct net_device *dev;
2368 struct sk_buff *skb;
2369 u32 status;
2370 u16 length;
2371 u8 opcode = le->opcode;
2372
2373 if (!(opcode & HW_OWNER))
2374 break;
2375
2376 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2377
2378 port = le->css & CSS_LINK_BIT;
2379 dev = hw->dev[port];
2380 sky2 = netdev_priv(dev);
2381 length = le16_to_cpu(le->length);
2382 status = le32_to_cpu(le->status);
2383
2384 le->opcode = 0;
2385 switch (opcode & ~HW_OWNER) {
2386 case OP_RXSTAT:
2387 ++rx[port];
2388 skb = sky2_receive(dev, length, status);
2389 if (unlikely(!skb)) {
2390 dev->stats.rx_dropped++;
2391 break;
2392 }
2393
2394 /* This chip reports checksum status differently */
2395 if (hw->flags & SKY2_HW_NEW_LE) {
2396 if (sky2->rx_csum &&
2397 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2398 (le->css & CSS_TCPUDPCSOK))
2399 skb->ip_summed = CHECKSUM_UNNECESSARY;
2400 else
2401 skb->ip_summed = CHECKSUM_NONE;
2402 }
2403
2404 skb->protocol = eth_type_trans(skb, dev);
2405 dev->stats.rx_packets++;
2406 dev->stats.rx_bytes += skb->len;
2407 dev->last_rx = jiffies;
2408
2409 #ifdef SKY2_VLAN_TAG_USED
2410 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2411 vlan_hwaccel_receive_skb(skb,
2412 sky2->vlgrp,
2413 be16_to_cpu(sky2->rx_tag));
2414 } else
2415 #endif
2416 netif_receive_skb(skb);
2417
2418 /* Stop after net poll weight */
2419 if (++work_done >= to_do)
2420 goto exit_loop;
2421 break;
2422
2423 #ifdef SKY2_VLAN_TAG_USED
2424 case OP_RXVLAN:
2425 sky2->rx_tag = length;
2426 break;
2427
2428 case OP_RXCHKSVLAN:
2429 sky2->rx_tag = length;
2430 /* fall through */
2431 #endif
2432 case OP_RXCHKS:
2433 if (!sky2->rx_csum)
2434 break;
2435
2436 /* If this happens then driver assuming wrong format */
2437 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2438 if (net_ratelimit())
2439 printk(KERN_NOTICE "%s: unexpected"
2440 " checksum status\n",
2441 dev->name);
2442 break;
2443 }
2444
2445 /* Both checksum counters are programmed to start at
2446 * the same offset, so unless there is a problem they
2447 * should match. This failure is an early indication that
2448 * hardware receive checksumming won't work.
2449 */
2450 if (likely(status >> 16 == (status & 0xffff))) {
2451 skb = sky2->rx_ring[sky2->rx_next].skb;
2452 skb->ip_summed = CHECKSUM_COMPLETE;
2453 skb->csum = status & 0xffff;
2454 } else {
2455 printk(KERN_NOTICE PFX "%s: hardware receive "
2456 "checksum problem (status = %#x)\n",
2457 dev->name, status);
2458 sky2->rx_csum = 0;
2459 sky2_write32(sky2->hw,
2460 Q_ADDR(rxqaddr[port], Q_CSR),
2461 BMU_DIS_RX_CHKSUM);
2462 }
2463 break;
2464
2465 case OP_TXINDEXLE:
2466 /* TX index reports status for both ports */
2467 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2468 sky2_tx_done(hw->dev[0], status & 0xfff);
2469 if (hw->dev[1])
2470 sky2_tx_done(hw->dev[1],
2471 ((status >> 24) & 0xff)
2472 | (u16)(length & 0xf) << 8);
2473 break;
2474
2475 default:
2476 if (net_ratelimit())
2477 printk(KERN_WARNING PFX
2478 "unknown status opcode 0x%x\n", opcode);
2479 }
2480 } while (hw->st_idx != idx);
2481
2482 /* Fully processed status ring so clear irq */
2483 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2484
2485 exit_loop:
2486 if (rx[0])
2487 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
2488
2489 if (rx[1])
2490 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
2491
2492 return work_done;
2493 }
2494
2495 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2496 {
2497 struct net_device *dev = hw->dev[port];
2498
2499 if (net_ratelimit())
2500 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2501 dev->name, status);
2502
2503 if (status & Y2_IS_PAR_RD1) {
2504 if (net_ratelimit())
2505 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2506 dev->name);
2507 /* Clear IRQ */
2508 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2509 }
2510
2511 if (status & Y2_IS_PAR_WR1) {
2512 if (net_ratelimit())
2513 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2514 dev->name);
2515
2516 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2517 }
2518
2519 if (status & Y2_IS_PAR_MAC1) {
2520 if (net_ratelimit())
2521 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2522 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2523 }
2524
2525 if (status & Y2_IS_PAR_RX1) {
2526 if (net_ratelimit())
2527 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2528 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2529 }
2530
2531 if (status & Y2_IS_TCP_TXA1) {
2532 if (net_ratelimit())
2533 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2534 dev->name);
2535 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2536 }
2537 }
2538
2539 static void sky2_hw_intr(struct sky2_hw *hw)
2540 {
2541 struct pci_dev *pdev = hw->pdev;
2542 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2543 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2544
2545 status &= hwmsk;
2546
2547 if (status & Y2_IS_TIST_OV)
2548 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2549
2550 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2551 u16 pci_err;
2552
2553 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2554 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2555 if (net_ratelimit())
2556 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2557 pci_err);
2558
2559 sky2_pci_write16(hw, PCI_STATUS,
2560 pci_err | PCI_STATUS_ERROR_BITS);
2561 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2562 }
2563
2564 if (status & Y2_IS_PCI_EXP) {
2565 /* PCI-Express uncorrectable Error occurred */
2566 u32 err;
2567
2568 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2569 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2570 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2571 0xfffffffful);
2572 if (net_ratelimit())
2573 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2574
2575 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2576 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2577 }
2578
2579 if (status & Y2_HWE_L1_MASK)
2580 sky2_hw_error(hw, 0, status);
2581 status >>= 8;
2582 if (status & Y2_HWE_L1_MASK)
2583 sky2_hw_error(hw, 1, status);
2584 }
2585
2586 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2587 {
2588 struct net_device *dev = hw->dev[port];
2589 struct sky2_port *sky2 = netdev_priv(dev);
2590 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2591
2592 if (netif_msg_intr(sky2))
2593 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2594 dev->name, status);
2595
2596 if (status & GM_IS_RX_CO_OV)
2597 gma_read16(hw, port, GM_RX_IRQ_SRC);
2598
2599 if (status & GM_IS_TX_CO_OV)
2600 gma_read16(hw, port, GM_TX_IRQ_SRC);
2601
2602 if (status & GM_IS_RX_FF_OR) {
2603 ++dev->stats.rx_fifo_errors;
2604 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2605 }
2606
2607 if (status & GM_IS_TX_FF_UR) {
2608 ++dev->stats.tx_fifo_errors;
2609 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2610 }
2611 }
2612
2613 /* This should never happen it is a bug. */
2614 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2615 u16 q, unsigned ring_size)
2616 {
2617 struct net_device *dev = hw->dev[port];
2618 struct sky2_port *sky2 = netdev_priv(dev);
2619 unsigned idx;
2620 const u64 *le = (q == Q_R1 || q == Q_R2)
2621 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2622
2623 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2624 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2625 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2626 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2627
2628 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2629 }
2630
2631 static int sky2_rx_hung(struct net_device *dev)
2632 {
2633 struct sky2_port *sky2 = netdev_priv(dev);
2634 struct sky2_hw *hw = sky2->hw;
2635 unsigned port = sky2->port;
2636 unsigned rxq = rxqaddr[port];
2637 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2638 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2639 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2640 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2641
2642 /* If idle and MAC or PCI is stuck */
2643 if (sky2->check.last == dev->last_rx &&
2644 ((mac_rp == sky2->check.mac_rp &&
2645 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2646 /* Check if the PCI RX hang */
2647 (fifo_rp == sky2->check.fifo_rp &&
2648 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2649 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2650 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2651 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2652 return 1;
2653 } else {
2654 sky2->check.last = dev->last_rx;
2655 sky2->check.mac_rp = mac_rp;
2656 sky2->check.mac_lev = mac_lev;
2657 sky2->check.fifo_rp = fifo_rp;
2658 sky2->check.fifo_lev = fifo_lev;
2659 return 0;
2660 }
2661 }
2662
2663 static void sky2_watchdog(unsigned long arg)
2664 {
2665 struct sky2_hw *hw = (struct sky2_hw *) arg;
2666
2667 /* Check for lost IRQ once a second */
2668 if (sky2_read32(hw, B0_ISRC)) {
2669 napi_schedule(&hw->napi);
2670 } else {
2671 int i, active = 0;
2672
2673 for (i = 0; i < hw->ports; i++) {
2674 struct net_device *dev = hw->dev[i];
2675 if (!netif_running(dev))
2676 continue;
2677 ++active;
2678
2679 /* For chips with Rx FIFO, check if stuck */
2680 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2681 sky2_rx_hung(dev)) {
2682 pr_info(PFX "%s: receiver hang detected\n",
2683 dev->name);
2684 schedule_work(&hw->restart_work);
2685 return;
2686 }
2687 }
2688
2689 if (active == 0)
2690 return;
2691 }
2692
2693 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2694 }
2695
2696 /* Hardware/software error handling */
2697 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2698 {
2699 if (net_ratelimit())
2700 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2701
2702 if (status & Y2_IS_HW_ERR)
2703 sky2_hw_intr(hw);
2704
2705 if (status & Y2_IS_IRQ_MAC1)
2706 sky2_mac_intr(hw, 0);
2707
2708 if (status & Y2_IS_IRQ_MAC2)
2709 sky2_mac_intr(hw, 1);
2710
2711 if (status & Y2_IS_CHK_RX1)
2712 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2713
2714 if (status & Y2_IS_CHK_RX2)
2715 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2716
2717 if (status & Y2_IS_CHK_TXA1)
2718 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2719
2720 if (status & Y2_IS_CHK_TXA2)
2721 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2722 }
2723
2724 static int sky2_poll(struct napi_struct *napi, int work_limit)
2725 {
2726 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2727 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2728 int work_done = 0;
2729 u16 idx;
2730
2731 if (unlikely(status & Y2_IS_ERROR))
2732 sky2_err_intr(hw, status);
2733
2734 if (status & Y2_IS_IRQ_PHY1)
2735 sky2_phy_intr(hw, 0);
2736
2737 if (status & Y2_IS_IRQ_PHY2)
2738 sky2_phy_intr(hw, 1);
2739
2740 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2741 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2742
2743 if (work_done >= work_limit)
2744 goto done;
2745 }
2746
2747 napi_complete(napi);
2748 sky2_read32(hw, B0_Y2_SP_LISR);
2749 done:
2750
2751 return work_done;
2752 }
2753
2754 static irqreturn_t sky2_intr(int irq, void *dev_id)
2755 {
2756 struct sky2_hw *hw = dev_id;
2757 u32 status;
2758
2759 /* Reading this mask interrupts as side effect */
2760 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2761 if (status == 0 || status == ~0)
2762 return IRQ_NONE;
2763
2764 prefetch(&hw->st_le[hw->st_idx]);
2765
2766 napi_schedule(&hw->napi);
2767
2768 return IRQ_HANDLED;
2769 }
2770
2771 #ifdef CONFIG_NET_POLL_CONTROLLER
2772 static void sky2_netpoll(struct net_device *dev)
2773 {
2774 struct sky2_port *sky2 = netdev_priv(dev);
2775
2776 napi_schedule(&sky2->hw->napi);
2777 }
2778 #endif
2779
2780 /* Chip internal frequency for clock calculations */
2781 static u32 sky2_mhz(const struct sky2_hw *hw)
2782 {
2783 switch (hw->chip_id) {
2784 case CHIP_ID_YUKON_EC:
2785 case CHIP_ID_YUKON_EC_U:
2786 case CHIP_ID_YUKON_EX:
2787 case CHIP_ID_YUKON_SUPR:
2788 case CHIP_ID_YUKON_UL_2:
2789 return 125;
2790
2791 case CHIP_ID_YUKON_FE:
2792 return 100;
2793
2794 case CHIP_ID_YUKON_FE_P:
2795 return 50;
2796
2797 case CHIP_ID_YUKON_XL:
2798 return 156;
2799
2800 default:
2801 BUG();
2802 }
2803 }
2804
2805 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2806 {
2807 return sky2_mhz(hw) * us;
2808 }
2809
2810 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2811 {
2812 return clk / sky2_mhz(hw);
2813 }
2814
2815
2816 static int __devinit sky2_init(struct sky2_hw *hw)
2817 {
2818 u8 t8;
2819
2820 /* Enable all clocks and check for bad PCI access */
2821 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2822
2823 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2824
2825 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2826 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2827
2828 switch(hw->chip_id) {
2829 case CHIP_ID_YUKON_XL:
2830 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2831 break;
2832
2833 case CHIP_ID_YUKON_EC_U:
2834 hw->flags = SKY2_HW_GIGABIT
2835 | SKY2_HW_NEWER_PHY
2836 | SKY2_HW_ADV_POWER_CTL;
2837 break;
2838
2839 case CHIP_ID_YUKON_EX:
2840 hw->flags = SKY2_HW_GIGABIT
2841 | SKY2_HW_NEWER_PHY
2842 | SKY2_HW_NEW_LE
2843 | SKY2_HW_ADV_POWER_CTL;
2844
2845 /* New transmit checksum */
2846 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2847 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2848 break;
2849
2850 case CHIP_ID_YUKON_EC:
2851 /* This rev is really old, and requires untested workarounds */
2852 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2853 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2854 return -EOPNOTSUPP;
2855 }
2856 hw->flags = SKY2_HW_GIGABIT;
2857 break;
2858
2859 case CHIP_ID_YUKON_FE:
2860 break;
2861
2862 case CHIP_ID_YUKON_FE_P:
2863 hw->flags = SKY2_HW_NEWER_PHY
2864 | SKY2_HW_NEW_LE
2865 | SKY2_HW_AUTO_TX_SUM
2866 | SKY2_HW_ADV_POWER_CTL;
2867 break;
2868
2869 case CHIP_ID_YUKON_SUPR:
2870 hw->flags = SKY2_HW_GIGABIT
2871 | SKY2_HW_NEWER_PHY
2872 | SKY2_HW_NEW_LE
2873 | SKY2_HW_AUTO_TX_SUM
2874 | SKY2_HW_ADV_POWER_CTL;
2875 break;
2876
2877 case CHIP_ID_YUKON_UL_2:
2878 hw->flags = SKY2_HW_GIGABIT
2879 | SKY2_HW_ADV_POWER_CTL;
2880 break;
2881
2882 default:
2883 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2884 hw->chip_id);
2885 return -EOPNOTSUPP;
2886 }
2887
2888 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2889 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2890 hw->flags |= SKY2_HW_FIBRE_PHY;
2891
2892 hw->ports = 1;
2893 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2894 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2895 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2896 ++hw->ports;
2897 }
2898
2899 return 0;
2900 }
2901
2902 static void sky2_reset(struct sky2_hw *hw)
2903 {
2904 struct pci_dev *pdev = hw->pdev;
2905 u16 status;
2906 int i, cap;
2907 u32 hwe_mask = Y2_HWE_ALL_MASK;
2908
2909 /* disable ASF */
2910 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2911 status = sky2_read16(hw, HCU_CCSR);
2912 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2913 HCU_CCSR_UC_STATE_MSK);
2914 sky2_write16(hw, HCU_CCSR, status);
2915 } else
2916 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2917 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2918
2919 /* do a SW reset */
2920 sky2_write8(hw, B0_CTST, CS_RST_SET);
2921 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2922
2923 /* allow writes to PCI config */
2924 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2925
2926 /* clear PCI errors, if any */
2927 status = sky2_pci_read16(hw, PCI_STATUS);
2928 status |= PCI_STATUS_ERROR_BITS;
2929 sky2_pci_write16(hw, PCI_STATUS, status);
2930
2931 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2932
2933 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2934 if (cap) {
2935 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2936 0xfffffffful);
2937
2938 /* If error bit is stuck on ignore it */
2939 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2940 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
2941 else
2942 hwe_mask |= Y2_IS_PCI_EXP;
2943 }
2944
2945 sky2_power_on(hw);
2946 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2947
2948 for (i = 0; i < hw->ports; i++) {
2949 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2950 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2951
2952 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2953 hw->chip_id == CHIP_ID_YUKON_SUPR)
2954 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2955 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2956 | GMC_BYP_RETR_ON);
2957 }
2958
2959 /* Clear I2C IRQ noise */
2960 sky2_write32(hw, B2_I2C_IRQ, 1);
2961
2962 /* turn off hardware timer (unused) */
2963 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2964 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2965
2966 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2967
2968 /* Turn off descriptor polling */
2969 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2970
2971 /* Turn off receive timestamp */
2972 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2973 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2974
2975 /* enable the Tx Arbiters */
2976 for (i = 0; i < hw->ports; i++)
2977 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2978
2979 /* Initialize ram interface */
2980 for (i = 0; i < hw->ports; i++) {
2981 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2982
2983 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2984 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2985 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2986 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2987 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2988 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2989 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2990 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2991 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2992 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2993 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2994 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2995 }
2996
2997 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
2998
2999 for (i = 0; i < hw->ports; i++)
3000 sky2_gmac_reset(hw, i);
3001
3002 memset(hw->st_le, 0, STATUS_LE_BYTES);
3003 hw->st_idx = 0;
3004
3005 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3006 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3007
3008 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3009 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3010
3011 /* Set the list last index */
3012 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
3013
3014 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3015 sky2_write8(hw, STAT_FIFO_WM, 16);
3016
3017 /* set Status-FIFO ISR watermark */
3018 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3019 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3020 else
3021 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3022
3023 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3024 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3025 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3026
3027 /* enable status unit */
3028 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3029
3030 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3031 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3032 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3033 }
3034
3035 static void sky2_restart(struct work_struct *work)
3036 {
3037 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3038 struct net_device *dev;
3039 int i, err;
3040
3041 rtnl_lock();
3042 for (i = 0; i < hw->ports; i++) {
3043 dev = hw->dev[i];
3044 if (netif_running(dev))
3045 sky2_down(dev);
3046 }
3047
3048 napi_disable(&hw->napi);
3049 sky2_write32(hw, B0_IMSK, 0);
3050 sky2_reset(hw);
3051 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3052 napi_enable(&hw->napi);
3053
3054 for (i = 0; i < hw->ports; i++) {
3055 dev = hw->dev[i];
3056 if (netif_running(dev)) {
3057 err = sky2_up(dev);
3058 if (err) {
3059 printk(KERN_INFO PFX "%s: could not restart %d\n",
3060 dev->name, err);
3061 dev_close(dev);
3062 }
3063 }
3064 }
3065
3066 rtnl_unlock();
3067 }
3068
3069 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3070 {
3071 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3072 }
3073
3074 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3075 {
3076 const struct sky2_port *sky2 = netdev_priv(dev);
3077
3078 wol->supported = sky2_wol_supported(sky2->hw);
3079 wol->wolopts = sky2->wol;
3080 }
3081
3082 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3083 {
3084 struct sky2_port *sky2 = netdev_priv(dev);
3085 struct sky2_hw *hw = sky2->hw;
3086
3087 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw))
3088 || !device_can_wakeup(&hw->pdev->dev))
3089 return -EOPNOTSUPP;
3090
3091 sky2->wol = wol->wolopts;
3092
3093 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3094 hw->chip_id == CHIP_ID_YUKON_EX ||
3095 hw->chip_id == CHIP_ID_YUKON_FE_P)
3096 sky2_write32(hw, B0_CTST, sky2->wol
3097 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3098
3099 device_set_wakeup_enable(&hw->pdev->dev, sky2->wol);
3100
3101 if (!netif_running(dev))
3102 sky2_wol_init(sky2);
3103 return 0;
3104 }
3105
3106 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3107 {
3108 if (sky2_is_copper(hw)) {
3109 u32 modes = SUPPORTED_10baseT_Half
3110 | SUPPORTED_10baseT_Full
3111 | SUPPORTED_100baseT_Half
3112 | SUPPORTED_100baseT_Full
3113 | SUPPORTED_Autoneg | SUPPORTED_TP;
3114
3115 if (hw->flags & SKY2_HW_GIGABIT)
3116 modes |= SUPPORTED_1000baseT_Half
3117 | SUPPORTED_1000baseT_Full;
3118 return modes;
3119 } else
3120 return SUPPORTED_1000baseT_Half
3121 | SUPPORTED_1000baseT_Full
3122 | SUPPORTED_Autoneg
3123 | SUPPORTED_FIBRE;
3124 }
3125
3126 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3127 {
3128 struct sky2_port *sky2 = netdev_priv(dev);
3129 struct sky2_hw *hw = sky2->hw;
3130
3131 ecmd->transceiver = XCVR_INTERNAL;
3132 ecmd->supported = sky2_supported_modes(hw);
3133 ecmd->phy_address = PHY_ADDR_MARV;
3134 if (sky2_is_copper(hw)) {
3135 ecmd->port = PORT_TP;
3136 ecmd->speed = sky2->speed;
3137 } else {
3138 ecmd->speed = SPEED_1000;
3139 ecmd->port = PORT_FIBRE;
3140 }
3141
3142 ecmd->advertising = sky2->advertising;
3143 ecmd->autoneg = sky2->autoneg;
3144 ecmd->duplex = sky2->duplex;
3145 return 0;
3146 }
3147
3148 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3149 {
3150 struct sky2_port *sky2 = netdev_priv(dev);
3151 const struct sky2_hw *hw = sky2->hw;
3152 u32 supported = sky2_supported_modes(hw);
3153
3154 if (ecmd->autoneg == AUTONEG_ENABLE) {
3155 ecmd->advertising = supported;
3156 sky2->duplex = -1;
3157 sky2->speed = -1;
3158 } else {
3159 u32 setting;
3160
3161 switch (ecmd->speed) {
3162 case SPEED_1000:
3163 if (ecmd->duplex == DUPLEX_FULL)
3164 setting = SUPPORTED_1000baseT_Full;
3165 else if (ecmd->duplex == DUPLEX_HALF)
3166 setting = SUPPORTED_1000baseT_Half;
3167 else
3168 return -EINVAL;
3169 break;
3170 case SPEED_100:
3171 if (ecmd->duplex == DUPLEX_FULL)
3172 setting = SUPPORTED_100baseT_Full;
3173 else if (ecmd->duplex == DUPLEX_HALF)
3174 setting = SUPPORTED_100baseT_Half;
3175 else
3176 return -EINVAL;
3177 break;
3178
3179 case SPEED_10:
3180 if (ecmd->duplex == DUPLEX_FULL)
3181 setting = SUPPORTED_10baseT_Full;
3182 else if (ecmd->duplex == DUPLEX_HALF)
3183 setting = SUPPORTED_10baseT_Half;
3184 else
3185 return -EINVAL;
3186 break;
3187 default:
3188 return -EINVAL;
3189 }
3190
3191 if ((setting & supported) == 0)
3192 return -EINVAL;
3193
3194 sky2->speed = ecmd->speed;
3195 sky2->duplex = ecmd->duplex;
3196 }
3197
3198 sky2->autoneg = ecmd->autoneg;
3199 sky2->advertising = ecmd->advertising;
3200
3201 if (netif_running(dev)) {
3202 sky2_phy_reinit(sky2);
3203 sky2_set_multicast(dev);
3204 }
3205
3206 return 0;
3207 }
3208
3209 static void sky2_get_drvinfo(struct net_device *dev,
3210 struct ethtool_drvinfo *info)
3211 {
3212 struct sky2_port *sky2 = netdev_priv(dev);
3213
3214 strcpy(info->driver, DRV_NAME);
3215 strcpy(info->version, DRV_VERSION);
3216 strcpy(info->fw_version, "N/A");
3217 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3218 }
3219
3220 static const struct sky2_stat {
3221 char name[ETH_GSTRING_LEN];
3222 u16 offset;
3223 } sky2_stats[] = {
3224 { "tx_bytes", GM_TXO_OK_HI },
3225 { "rx_bytes", GM_RXO_OK_HI },
3226 { "tx_broadcast", GM_TXF_BC_OK },
3227 { "rx_broadcast", GM_RXF_BC_OK },
3228 { "tx_multicast", GM_TXF_MC_OK },
3229 { "rx_multicast", GM_RXF_MC_OK },
3230 { "tx_unicast", GM_TXF_UC_OK },
3231 { "rx_unicast", GM_RXF_UC_OK },
3232 { "tx_mac_pause", GM_TXF_MPAUSE },
3233 { "rx_mac_pause", GM_RXF_MPAUSE },
3234 { "collisions", GM_TXF_COL },
3235 { "late_collision",GM_TXF_LAT_COL },
3236 { "aborted", GM_TXF_ABO_COL },
3237 { "single_collisions", GM_TXF_SNG_COL },
3238 { "multi_collisions", GM_TXF_MUL_COL },
3239
3240 { "rx_short", GM_RXF_SHT },
3241 { "rx_runt", GM_RXE_FRAG },
3242 { "rx_64_byte_packets", GM_RXF_64B },
3243 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3244 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3245 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3246 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3247 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3248 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3249 { "rx_too_long", GM_RXF_LNG_ERR },
3250 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3251 { "rx_jabber", GM_RXF_JAB_PKT },
3252 { "rx_fcs_error", GM_RXF_FCS_ERR },
3253
3254 { "tx_64_byte_packets", GM_TXF_64B },
3255 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3256 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3257 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3258 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3259 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3260 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3261 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3262 };
3263
3264 static u32 sky2_get_rx_csum(struct net_device *dev)
3265 {
3266 struct sky2_port *sky2 = netdev_priv(dev);
3267
3268 return sky2->rx_csum;
3269 }
3270
3271 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3272 {
3273 struct sky2_port *sky2 = netdev_priv(dev);
3274
3275 sky2->rx_csum = data;
3276
3277 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3278 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3279
3280 return 0;
3281 }
3282
3283 static u32 sky2_get_msglevel(struct net_device *netdev)
3284 {
3285 struct sky2_port *sky2 = netdev_priv(netdev);
3286 return sky2->msg_enable;
3287 }
3288
3289 static int sky2_nway_reset(struct net_device *dev)
3290 {
3291 struct sky2_port *sky2 = netdev_priv(dev);
3292
3293 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
3294 return -EINVAL;
3295
3296 sky2_phy_reinit(sky2);
3297 sky2_set_multicast(dev);
3298
3299 return 0;
3300 }
3301
3302 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3303 {
3304 struct sky2_hw *hw = sky2->hw;
3305 unsigned port = sky2->port;
3306 int i;
3307
3308 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3309 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3310 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3311 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3312
3313 for (i = 2; i < count; i++)
3314 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3315 }
3316
3317 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3318 {
3319 struct sky2_port *sky2 = netdev_priv(netdev);
3320 sky2->msg_enable = value;
3321 }
3322
3323 static int sky2_get_sset_count(struct net_device *dev, int sset)
3324 {
3325 switch (sset) {
3326 case ETH_SS_STATS:
3327 return ARRAY_SIZE(sky2_stats);
3328 default:
3329 return -EOPNOTSUPP;
3330 }
3331 }
3332
3333 static void sky2_get_ethtool_stats(struct net_device *dev,
3334 struct ethtool_stats *stats, u64 * data)
3335 {
3336 struct sky2_port *sky2 = netdev_priv(dev);
3337
3338 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3339 }
3340
3341 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3342 {
3343 int i;
3344
3345 switch (stringset) {
3346 case ETH_SS_STATS:
3347 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3348 memcpy(data + i * ETH_GSTRING_LEN,
3349 sky2_stats[i].name, ETH_GSTRING_LEN);
3350 break;
3351 }
3352 }
3353
3354 static int sky2_set_mac_address(struct net_device *dev, void *p)
3355 {
3356 struct sky2_port *sky2 = netdev_priv(dev);
3357 struct sky2_hw *hw = sky2->hw;
3358 unsigned port = sky2->port;
3359 const struct sockaddr *addr = p;
3360
3361 if (!is_valid_ether_addr(addr->sa_data))
3362 return -EADDRNOTAVAIL;
3363
3364 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3365 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3366 dev->dev_addr, ETH_ALEN);
3367 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3368 dev->dev_addr, ETH_ALEN);
3369
3370 /* virtual address for data */
3371 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3372
3373 /* physical address: used for pause frames */
3374 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3375
3376 return 0;
3377 }
3378
3379 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3380 {
3381 u32 bit;
3382
3383 bit = ether_crc(ETH_ALEN, addr) & 63;
3384 filter[bit >> 3] |= 1 << (bit & 7);
3385 }
3386
3387 static void sky2_set_multicast(struct net_device *dev)
3388 {
3389 struct sky2_port *sky2 = netdev_priv(dev);
3390 struct sky2_hw *hw = sky2->hw;
3391 unsigned port = sky2->port;
3392 struct dev_mc_list *list = dev->mc_list;
3393 u16 reg;
3394 u8 filter[8];
3395 int rx_pause;
3396 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3397
3398 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3399 memset(filter, 0, sizeof(filter));
3400
3401 reg = gma_read16(hw, port, GM_RX_CTRL);
3402 reg |= GM_RXCR_UCF_ENA;
3403
3404 if (dev->flags & IFF_PROMISC) /* promiscuous */
3405 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3406 else if (dev->flags & IFF_ALLMULTI)
3407 memset(filter, 0xff, sizeof(filter));
3408 else if (dev->mc_count == 0 && !rx_pause)
3409 reg &= ~GM_RXCR_MCF_ENA;
3410 else {
3411 int i;
3412 reg |= GM_RXCR_MCF_ENA;
3413
3414 if (rx_pause)
3415 sky2_add_filter(filter, pause_mc_addr);
3416
3417 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3418 sky2_add_filter(filter, list->dmi_addr);
3419 }
3420
3421 gma_write16(hw, port, GM_MC_ADDR_H1,
3422 (u16) filter[0] | ((u16) filter[1] << 8));
3423 gma_write16(hw, port, GM_MC_ADDR_H2,
3424 (u16) filter[2] | ((u16) filter[3] << 8));
3425 gma_write16(hw, port, GM_MC_ADDR_H3,
3426 (u16) filter[4] | ((u16) filter[5] << 8));
3427 gma_write16(hw, port, GM_MC_ADDR_H4,
3428 (u16) filter[6] | ((u16) filter[7] << 8));
3429
3430 gma_write16(hw, port, GM_RX_CTRL, reg);
3431 }
3432
3433 /* Can have one global because blinking is controlled by
3434 * ethtool and that is always under RTNL mutex
3435 */
3436 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3437 {
3438 struct sky2_hw *hw = sky2->hw;
3439 unsigned port = sky2->port;
3440
3441 spin_lock_bh(&sky2->phy_lock);
3442 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3443 hw->chip_id == CHIP_ID_YUKON_EX ||
3444 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3445 u16 pg;
3446 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3447 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3448
3449 switch (mode) {
3450 case MO_LED_OFF:
3451 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3452 PHY_M_LEDC_LOS_CTRL(8) |
3453 PHY_M_LEDC_INIT_CTRL(8) |
3454 PHY_M_LEDC_STA1_CTRL(8) |
3455 PHY_M_LEDC_STA0_CTRL(8));
3456 break;
3457 case MO_LED_ON:
3458 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3459 PHY_M_LEDC_LOS_CTRL(9) |
3460 PHY_M_LEDC_INIT_CTRL(9) |
3461 PHY_M_LEDC_STA1_CTRL(9) |
3462 PHY_M_LEDC_STA0_CTRL(9));
3463 break;
3464 case MO_LED_BLINK:
3465 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3466 PHY_M_LEDC_LOS_CTRL(0xa) |
3467 PHY_M_LEDC_INIT_CTRL(0xa) |
3468 PHY_M_LEDC_STA1_CTRL(0xa) |
3469 PHY_M_LEDC_STA0_CTRL(0xa));
3470 break;
3471 case MO_LED_NORM:
3472 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3473 PHY_M_LEDC_LOS_CTRL(1) |
3474 PHY_M_LEDC_INIT_CTRL(8) |
3475 PHY_M_LEDC_STA1_CTRL(7) |
3476 PHY_M_LEDC_STA0_CTRL(7));
3477 }
3478
3479 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3480 } else
3481 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3482 PHY_M_LED_MO_DUP(mode) |
3483 PHY_M_LED_MO_10(mode) |
3484 PHY_M_LED_MO_100(mode) |
3485 PHY_M_LED_MO_1000(mode) |
3486 PHY_M_LED_MO_RX(mode) |
3487 PHY_M_LED_MO_TX(mode));
3488
3489 spin_unlock_bh(&sky2->phy_lock);
3490 }
3491
3492 /* blink LED's for finding board */
3493 static int sky2_phys_id(struct net_device *dev, u32 data)
3494 {
3495 struct sky2_port *sky2 = netdev_priv(dev);
3496 unsigned int i;
3497
3498 if (data == 0)
3499 data = UINT_MAX;
3500
3501 for (i = 0; i < data; i++) {
3502 sky2_led(sky2, MO_LED_ON);
3503 if (msleep_interruptible(500))
3504 break;
3505 sky2_led(sky2, MO_LED_OFF);
3506 if (msleep_interruptible(500))
3507 break;
3508 }
3509 sky2_led(sky2, MO_LED_NORM);
3510
3511 return 0;
3512 }
3513
3514 static void sky2_get_pauseparam(struct net_device *dev,
3515 struct ethtool_pauseparam *ecmd)
3516 {
3517 struct sky2_port *sky2 = netdev_priv(dev);
3518
3519 switch (sky2->flow_mode) {
3520 case FC_NONE:
3521 ecmd->tx_pause = ecmd->rx_pause = 0;
3522 break;
3523 case FC_TX:
3524 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3525 break;
3526 case FC_RX:
3527 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3528 break;
3529 case FC_BOTH:
3530 ecmd->tx_pause = ecmd->rx_pause = 1;
3531 }
3532
3533 ecmd->autoneg = sky2->autoneg;
3534 }
3535
3536 static int sky2_set_pauseparam(struct net_device *dev,
3537 struct ethtool_pauseparam *ecmd)
3538 {
3539 struct sky2_port *sky2 = netdev_priv(dev);
3540
3541 sky2->autoneg = ecmd->autoneg;
3542 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3543
3544 if (netif_running(dev))
3545 sky2_phy_reinit(sky2);
3546
3547 return 0;
3548 }
3549
3550 static int sky2_get_coalesce(struct net_device *dev,
3551 struct ethtool_coalesce *ecmd)
3552 {
3553 struct sky2_port *sky2 = netdev_priv(dev);
3554 struct sky2_hw *hw = sky2->hw;
3555
3556 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3557 ecmd->tx_coalesce_usecs = 0;
3558 else {
3559 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3560 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3561 }
3562 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3563
3564 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3565 ecmd->rx_coalesce_usecs = 0;
3566 else {
3567 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3568 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3569 }
3570 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3571
3572 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3573 ecmd->rx_coalesce_usecs_irq = 0;
3574 else {
3575 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3576 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3577 }
3578
3579 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3580
3581 return 0;
3582 }
3583
3584 /* Note: this affect both ports */
3585 static int sky2_set_coalesce(struct net_device *dev,
3586 struct ethtool_coalesce *ecmd)
3587 {
3588 struct sky2_port *sky2 = netdev_priv(dev);
3589 struct sky2_hw *hw = sky2->hw;
3590 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3591
3592 if (ecmd->tx_coalesce_usecs > tmax ||
3593 ecmd->rx_coalesce_usecs > tmax ||
3594 ecmd->rx_coalesce_usecs_irq > tmax)
3595 return -EINVAL;
3596
3597 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3598 return -EINVAL;
3599 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3600 return -EINVAL;
3601 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3602 return -EINVAL;
3603
3604 if (ecmd->tx_coalesce_usecs == 0)
3605 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3606 else {
3607 sky2_write32(hw, STAT_TX_TIMER_INI,
3608 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3609 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3610 }
3611 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3612
3613 if (ecmd->rx_coalesce_usecs == 0)
3614 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3615 else {
3616 sky2_write32(hw, STAT_LEV_TIMER_INI,
3617 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3618 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3619 }
3620 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3621
3622 if (ecmd->rx_coalesce_usecs_irq == 0)
3623 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3624 else {
3625 sky2_write32(hw, STAT_ISR_TIMER_INI,
3626 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3627 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3628 }
3629 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3630 return 0;
3631 }
3632
3633 static void sky2_get_ringparam(struct net_device *dev,
3634 struct ethtool_ringparam *ering)
3635 {
3636 struct sky2_port *sky2 = netdev_priv(dev);
3637
3638 ering->rx_max_pending = RX_MAX_PENDING;
3639 ering->rx_mini_max_pending = 0;
3640 ering->rx_jumbo_max_pending = 0;
3641 ering->tx_max_pending = TX_RING_SIZE - 1;
3642
3643 ering->rx_pending = sky2->rx_pending;
3644 ering->rx_mini_pending = 0;
3645 ering->rx_jumbo_pending = 0;
3646 ering->tx_pending = sky2->tx_pending;
3647 }
3648
3649 static int sky2_set_ringparam(struct net_device *dev,
3650 struct ethtool_ringparam *ering)
3651 {
3652 struct sky2_port *sky2 = netdev_priv(dev);
3653 int err = 0;
3654
3655 if (ering->rx_pending > RX_MAX_PENDING ||
3656 ering->rx_pending < 8 ||
3657 ering->tx_pending < MAX_SKB_TX_LE ||
3658 ering->tx_pending > TX_RING_SIZE - 1)
3659 return -EINVAL;
3660
3661 if (netif_running(dev))
3662 sky2_down(dev);
3663
3664 sky2->rx_pending = ering->rx_pending;
3665 sky2->tx_pending = ering->tx_pending;
3666
3667 if (netif_running(dev)) {
3668 err = sky2_up(dev);
3669 if (err)
3670 dev_close(dev);
3671 }
3672
3673 return err;
3674 }
3675
3676 static int sky2_get_regs_len(struct net_device *dev)
3677 {
3678 return 0x4000;
3679 }
3680
3681 /*
3682 * Returns copy of control register region
3683 * Note: ethtool_get_regs always provides full size (16k) buffer
3684 */
3685 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3686 void *p)
3687 {
3688 const struct sky2_port *sky2 = netdev_priv(dev);
3689 const void __iomem *io = sky2->hw->regs;
3690 unsigned int b;
3691
3692 regs->version = 1;
3693
3694 for (b = 0; b < 128; b++) {
3695 /* This complicated switch statement is to make sure and
3696 * only access regions that are unreserved.
3697 * Some blocks are only valid on dual port cards.
3698 * and block 3 has some special diagnostic registers that
3699 * are poison.
3700 */
3701 switch (b) {
3702 case 3:
3703 /* skip diagnostic ram region */
3704 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3705 break;
3706
3707 /* dual port cards only */
3708 case 5: /* Tx Arbiter 2 */
3709 case 9: /* RX2 */
3710 case 14 ... 15: /* TX2 */
3711 case 17: case 19: /* Ram Buffer 2 */
3712 case 22 ... 23: /* Tx Ram Buffer 2 */
3713 case 25: /* Rx MAC Fifo 1 */
3714 case 27: /* Tx MAC Fifo 2 */
3715 case 31: /* GPHY 2 */
3716 case 40 ... 47: /* Pattern Ram 2 */
3717 case 52: case 54: /* TCP Segmentation 2 */
3718 case 112 ... 116: /* GMAC 2 */
3719 if (sky2->hw->ports == 1)
3720 goto reserved;
3721 /* fall through */
3722 case 0: /* Control */
3723 case 2: /* Mac address */
3724 case 4: /* Tx Arbiter 1 */
3725 case 7: /* PCI express reg */
3726 case 8: /* RX1 */
3727 case 12 ... 13: /* TX1 */
3728 case 16: case 18:/* Rx Ram Buffer 1 */
3729 case 20 ... 21: /* Tx Ram Buffer 1 */
3730 case 24: /* Rx MAC Fifo 1 */
3731 case 26: /* Tx MAC Fifo 1 */
3732 case 28 ... 29: /* Descriptor and status unit */
3733 case 30: /* GPHY 1*/
3734 case 32 ... 39: /* Pattern Ram 1 */
3735 case 48: case 50: /* TCP Segmentation 1 */
3736 case 56 ... 60: /* PCI space */
3737 case 80 ... 84: /* GMAC 1 */
3738 memcpy_fromio(p, io, 128);
3739 break;
3740 default:
3741 reserved:
3742 memset(p, 0, 128);
3743 }
3744
3745 p += 128;
3746 io += 128;
3747 }
3748 }
3749
3750 /* In order to do Jumbo packets on these chips, need to turn off the
3751 * transmit store/forward. Therefore checksum offload won't work.
3752 */
3753 static int no_tx_offload(struct net_device *dev)
3754 {
3755 const struct sky2_port *sky2 = netdev_priv(dev);
3756 const struct sky2_hw *hw = sky2->hw;
3757
3758 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3759 }
3760
3761 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3762 {
3763 if (data && no_tx_offload(dev))
3764 return -EINVAL;
3765
3766 return ethtool_op_set_tx_csum(dev, data);
3767 }
3768
3769
3770 static int sky2_set_tso(struct net_device *dev, u32 data)
3771 {
3772 if (data && no_tx_offload(dev))
3773 return -EINVAL;
3774
3775 return ethtool_op_set_tso(dev, data);
3776 }
3777
3778 static int sky2_get_eeprom_len(struct net_device *dev)
3779 {
3780 struct sky2_port *sky2 = netdev_priv(dev);
3781 struct sky2_hw *hw = sky2->hw;
3782 u16 reg2;
3783
3784 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3785 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3786 }
3787
3788 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
3789 {
3790 unsigned long start = jiffies;
3791
3792 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3793 /* Can take up to 10.6 ms for write */
3794 if (time_after(jiffies, start + HZ/4)) {
3795 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3796 return -ETIMEDOUT;
3797 }
3798 mdelay(1);
3799 }
3800
3801 return 0;
3802 }
3803
3804 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3805 u16 offset, size_t length)
3806 {
3807 int rc = 0;
3808
3809 while (length > 0) {
3810 u32 val;
3811
3812 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3813 rc = sky2_vpd_wait(hw, cap, 0);
3814 if (rc)
3815 break;
3816
3817 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3818
3819 memcpy(data, &val, min(sizeof(val), length));
3820 offset += sizeof(u32);
3821 data += sizeof(u32);
3822 length -= sizeof(u32);
3823 }
3824
3825 return rc;
3826 }
3827
3828 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
3829 u16 offset, unsigned int length)
3830 {
3831 unsigned int i;
3832 int rc = 0;
3833
3834 for (i = 0; i < length; i += sizeof(u32)) {
3835 u32 val = *(u32 *)(data + i);
3836
3837 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3838 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3839
3840 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
3841 if (rc)
3842 break;
3843 }
3844 return rc;
3845 }
3846
3847 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3848 u8 *data)
3849 {
3850 struct sky2_port *sky2 = netdev_priv(dev);
3851 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3852
3853 if (!cap)
3854 return -EINVAL;
3855
3856 eeprom->magic = SKY2_EEPROM_MAGIC;
3857
3858 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
3859 }
3860
3861 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3862 u8 *data)
3863 {
3864 struct sky2_port *sky2 = netdev_priv(dev);
3865 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3866
3867 if (!cap)
3868 return -EINVAL;
3869
3870 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3871 return -EINVAL;
3872
3873 /* Partial writes not supported */
3874 if ((eeprom->offset & 3) || (eeprom->len & 3))
3875 return -EINVAL;
3876
3877 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
3878 }
3879
3880
3881 static const struct ethtool_ops sky2_ethtool_ops = {
3882 .get_settings = sky2_get_settings,
3883 .set_settings = sky2_set_settings,
3884 .get_drvinfo = sky2_get_drvinfo,
3885 .get_wol = sky2_get_wol,
3886 .set_wol = sky2_set_wol,
3887 .get_msglevel = sky2_get_msglevel,
3888 .set_msglevel = sky2_set_msglevel,
3889 .nway_reset = sky2_nway_reset,
3890 .get_regs_len = sky2_get_regs_len,
3891 .get_regs = sky2_get_regs,
3892 .get_link = ethtool_op_get_link,
3893 .get_eeprom_len = sky2_get_eeprom_len,
3894 .get_eeprom = sky2_get_eeprom,
3895 .set_eeprom = sky2_set_eeprom,
3896 .set_sg = ethtool_op_set_sg,
3897 .set_tx_csum = sky2_set_tx_csum,
3898 .set_tso = sky2_set_tso,
3899 .get_rx_csum = sky2_get_rx_csum,
3900 .set_rx_csum = sky2_set_rx_csum,
3901 .get_strings = sky2_get_strings,
3902 .get_coalesce = sky2_get_coalesce,
3903 .set_coalesce = sky2_set_coalesce,
3904 .get_ringparam = sky2_get_ringparam,
3905 .set_ringparam = sky2_set_ringparam,
3906 .get_pauseparam = sky2_get_pauseparam,
3907 .set_pauseparam = sky2_set_pauseparam,
3908 .phys_id = sky2_phys_id,
3909 .get_sset_count = sky2_get_sset_count,
3910 .get_ethtool_stats = sky2_get_ethtool_stats,
3911 };
3912
3913 #ifdef CONFIG_SKY2_DEBUG
3914
3915 static struct dentry *sky2_debug;
3916
3917
3918 /*
3919 * Read and parse the first part of Vital Product Data
3920 */
3921 #define VPD_SIZE 128
3922 #define VPD_MAGIC 0x82
3923
3924 static const struct vpd_tag {
3925 char tag[2];
3926 char *label;
3927 } vpd_tags[] = {
3928 { "PN", "Part Number" },
3929 { "EC", "Engineering Level" },
3930 { "MN", "Manufacturer" },
3931 { "SN", "Serial Number" },
3932 { "YA", "Asset Tag" },
3933 { "VL", "First Error Log Message" },
3934 { "VF", "Second Error Log Message" },
3935 { "VB", "Boot Agent ROM Configuration" },
3936 { "VE", "EFI UNDI Configuration" },
3937 };
3938
3939 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
3940 {
3941 size_t vpd_size;
3942 loff_t offs;
3943 u8 len;
3944 unsigned char *buf;
3945 u16 reg2;
3946
3947 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3948 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3949
3950 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
3951 buf = kmalloc(vpd_size, GFP_KERNEL);
3952 if (!buf) {
3953 seq_puts(seq, "no memory!\n");
3954 return;
3955 }
3956
3957 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
3958 seq_puts(seq, "VPD read failed\n");
3959 goto out;
3960 }
3961
3962 if (buf[0] != VPD_MAGIC) {
3963 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
3964 goto out;
3965 }
3966 len = buf[1];
3967 if (len == 0 || len > vpd_size - 4) {
3968 seq_printf(seq, "Invalid id length: %d\n", len);
3969 goto out;
3970 }
3971
3972 seq_printf(seq, "%.*s\n", len, buf + 3);
3973 offs = len + 3;
3974
3975 while (offs < vpd_size - 4) {
3976 int i;
3977
3978 if (!memcmp("RW", buf + offs, 2)) /* end marker */
3979 break;
3980 len = buf[offs + 2];
3981 if (offs + len + 3 >= vpd_size)
3982 break;
3983
3984 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
3985 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
3986 seq_printf(seq, " %s: %.*s\n",
3987 vpd_tags[i].label, len, buf + offs + 3);
3988 break;
3989 }
3990 }
3991 offs += len + 3;
3992 }
3993 out:
3994 kfree(buf);
3995 }
3996
3997 static int sky2_debug_show(struct seq_file *seq, void *v)
3998 {
3999 struct net_device *dev = seq->private;
4000 const struct sky2_port *sky2 = netdev_priv(dev);
4001 struct sky2_hw *hw = sky2->hw;
4002 unsigned port = sky2->port;
4003 unsigned idx, last;
4004 int sop;
4005
4006 sky2_show_vpd(seq, hw);
4007
4008 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4009 sky2_read32(hw, B0_ISRC),
4010 sky2_read32(hw, B0_IMSK),
4011 sky2_read32(hw, B0_Y2_SP_ICR));
4012
4013 if (!netif_running(dev)) {
4014 seq_printf(seq, "network not running\n");
4015 return 0;
4016 }
4017
4018 napi_disable(&hw->napi);
4019 last = sky2_read16(hw, STAT_PUT_IDX);
4020
4021 if (hw->st_idx == last)
4022 seq_puts(seq, "Status ring (empty)\n");
4023 else {
4024 seq_puts(seq, "Status ring\n");
4025 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4026 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4027 const struct sky2_status_le *le = hw->st_le + idx;
4028 seq_printf(seq, "[%d] %#x %d %#x\n",
4029 idx, le->opcode, le->length, le->status);
4030 }
4031 seq_puts(seq, "\n");
4032 }
4033
4034 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4035 sky2->tx_cons, sky2->tx_prod,
4036 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4037 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4038
4039 /* Dump contents of tx ring */
4040 sop = 1;
4041 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
4042 idx = RING_NEXT(idx, TX_RING_SIZE)) {
4043 const struct sky2_tx_le *le = sky2->tx_le + idx;
4044 u32 a = le32_to_cpu(le->addr);
4045
4046 if (sop)
4047 seq_printf(seq, "%u:", idx);
4048 sop = 0;
4049
4050 switch(le->opcode & ~HW_OWNER) {
4051 case OP_ADDR64:
4052 seq_printf(seq, " %#x:", a);
4053 break;
4054 case OP_LRGLEN:
4055 seq_printf(seq, " mtu=%d", a);
4056 break;
4057 case OP_VLAN:
4058 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4059 break;
4060 case OP_TCPLISW:
4061 seq_printf(seq, " csum=%#x", a);
4062 break;
4063 case OP_LARGESEND:
4064 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4065 break;
4066 case OP_PACKET:
4067 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4068 break;
4069 case OP_BUFFER:
4070 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4071 break;
4072 default:
4073 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4074 a, le16_to_cpu(le->length));
4075 }
4076
4077 if (le->ctrl & EOP) {
4078 seq_putc(seq, '\n');
4079 sop = 1;
4080 }
4081 }
4082
4083 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4084 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4085 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4086 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4087
4088 sky2_read32(hw, B0_Y2_SP_LISR);
4089 napi_enable(&hw->napi);
4090 return 0;
4091 }
4092
4093 static int sky2_debug_open(struct inode *inode, struct file *file)
4094 {
4095 return single_open(file, sky2_debug_show, inode->i_private);
4096 }
4097
4098 static const struct file_operations sky2_debug_fops = {
4099 .owner = THIS_MODULE,
4100 .open = sky2_debug_open,
4101 .read = seq_read,
4102 .llseek = seq_lseek,
4103 .release = single_release,
4104 };
4105
4106 /*
4107 * Use network device events to create/remove/rename
4108 * debugfs file entries
4109 */
4110 static int sky2_device_event(struct notifier_block *unused,
4111 unsigned long event, void *ptr)
4112 {
4113 struct net_device *dev = ptr;
4114 struct sky2_port *sky2 = netdev_priv(dev);
4115
4116 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
4117 return NOTIFY_DONE;
4118
4119 switch(event) {
4120 case NETDEV_CHANGENAME:
4121 if (sky2->debugfs) {
4122 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4123 sky2_debug, dev->name);
4124 }
4125 break;
4126
4127 case NETDEV_GOING_DOWN:
4128 if (sky2->debugfs) {
4129 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4130 dev->name);
4131 debugfs_remove(sky2->debugfs);
4132 sky2->debugfs = NULL;
4133 }
4134 break;
4135
4136 case NETDEV_UP:
4137 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4138 sky2_debug, dev,
4139 &sky2_debug_fops);
4140 if (IS_ERR(sky2->debugfs))
4141 sky2->debugfs = NULL;
4142 }
4143
4144 return NOTIFY_DONE;
4145 }
4146
4147 static struct notifier_block sky2_notifier = {
4148 .notifier_call = sky2_device_event,
4149 };
4150
4151
4152 static __init void sky2_debug_init(void)
4153 {
4154 struct dentry *ent;
4155
4156 ent = debugfs_create_dir("sky2", NULL);
4157 if (!ent || IS_ERR(ent))
4158 return;
4159
4160 sky2_debug = ent;
4161 register_netdevice_notifier(&sky2_notifier);
4162 }
4163
4164 static __exit void sky2_debug_cleanup(void)
4165 {
4166 if (sky2_debug) {
4167 unregister_netdevice_notifier(&sky2_notifier);
4168 debugfs_remove(sky2_debug);
4169 sky2_debug = NULL;
4170 }
4171 }
4172
4173 #else
4174 #define sky2_debug_init()
4175 #define sky2_debug_cleanup()
4176 #endif
4177
4178 /* Two copies of network device operations to handle special case of
4179 not allowing netpoll on second port */
4180 static const struct net_device_ops sky2_netdev_ops[2] = {
4181 {
4182 .ndo_open = sky2_up,
4183 .ndo_stop = sky2_down,
4184 .ndo_start_xmit = sky2_xmit_frame,
4185 .ndo_do_ioctl = sky2_ioctl,
4186 .ndo_validate_addr = eth_validate_addr,
4187 .ndo_set_mac_address = sky2_set_mac_address,
4188 .ndo_set_multicast_list = sky2_set_multicast,
4189 .ndo_change_mtu = sky2_change_mtu,
4190 .ndo_tx_timeout = sky2_tx_timeout,
4191 #ifdef SKY2_VLAN_TAG_USED
4192 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4193 #endif
4194 #ifdef CONFIG_NET_POLL_CONTROLLER
4195 .ndo_poll_controller = sky2_netpoll,
4196 #endif
4197 },
4198 {
4199 .ndo_open = sky2_up,
4200 .ndo_stop = sky2_down,
4201 .ndo_start_xmit = sky2_xmit_frame,
4202 .ndo_do_ioctl = sky2_ioctl,
4203 .ndo_validate_addr = eth_validate_addr,
4204 .ndo_set_mac_address = sky2_set_mac_address,
4205 .ndo_set_multicast_list = sky2_set_multicast,
4206 .ndo_change_mtu = sky2_change_mtu,
4207 .ndo_tx_timeout = sky2_tx_timeout,
4208 #ifdef SKY2_VLAN_TAG_USED
4209 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4210 #endif
4211 },
4212 };
4213
4214 /* Initialize network device */
4215 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4216 unsigned port,
4217 int highmem, int wol)
4218 {
4219 struct sky2_port *sky2;
4220 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4221
4222 if (!dev) {
4223 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4224 return NULL;
4225 }
4226
4227 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4228 dev->irq = hw->pdev->irq;
4229 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4230 dev->watchdog_timeo = TX_WATCHDOG;
4231 dev->netdev_ops = &sky2_netdev_ops[port];
4232
4233 sky2 = netdev_priv(dev);
4234 sky2->netdev = dev;
4235 sky2->hw = hw;
4236 sky2->msg_enable = netif_msg_init(debug, default_msg);
4237
4238 /* Auto speed and flow control */
4239 sky2->autoneg = AUTONEG_ENABLE;
4240 sky2->flow_mode = FC_BOTH;
4241
4242 sky2->duplex = -1;
4243 sky2->speed = -1;
4244 sky2->advertising = sky2_supported_modes(hw);
4245 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
4246 sky2->wol = wol;
4247
4248 spin_lock_init(&sky2->phy_lock);
4249 sky2->tx_pending = TX_DEF_PENDING;
4250 sky2->rx_pending = RX_DEF_PENDING;
4251
4252 hw->dev[port] = dev;
4253
4254 sky2->port = port;
4255
4256 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4257 if (highmem)
4258 dev->features |= NETIF_F_HIGHDMA;
4259
4260 #ifdef SKY2_VLAN_TAG_USED
4261 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4262 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4263 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4264 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4265 }
4266 #endif
4267
4268 /* read the mac address */
4269 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4270 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4271
4272 return dev;
4273 }
4274
4275 static void __devinit sky2_show_addr(struct net_device *dev)
4276 {
4277 const struct sky2_port *sky2 = netdev_priv(dev);
4278
4279 if (netif_msg_probe(sky2))
4280 printk(KERN_INFO PFX "%s: addr %pM\n",
4281 dev->name, dev->dev_addr);
4282 }
4283
4284 /* Handle software interrupt used during MSI test */
4285 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4286 {
4287 struct sky2_hw *hw = dev_id;
4288 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4289
4290 if (status == 0)
4291 return IRQ_NONE;
4292
4293 if (status & Y2_IS_IRQ_SW) {
4294 hw->flags |= SKY2_HW_USE_MSI;
4295 wake_up(&hw->msi_wait);
4296 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4297 }
4298 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4299
4300 return IRQ_HANDLED;
4301 }
4302
4303 /* Test interrupt path by forcing a a software IRQ */
4304 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4305 {
4306 struct pci_dev *pdev = hw->pdev;
4307 int err;
4308
4309 init_waitqueue_head (&hw->msi_wait);
4310
4311 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4312
4313 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4314 if (err) {
4315 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4316 return err;
4317 }
4318
4319 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4320 sky2_read8(hw, B0_CTST);
4321
4322 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4323
4324 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4325 /* MSI test failed, go back to INTx mode */
4326 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4327 "switching to INTx mode.\n");
4328
4329 err = -EOPNOTSUPP;
4330 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4331 }
4332
4333 sky2_write32(hw, B0_IMSK, 0);
4334 sky2_read32(hw, B0_IMSK);
4335
4336 free_irq(pdev->irq, hw);
4337
4338 return err;
4339 }
4340
4341 /* This driver supports yukon2 chipset only */
4342 static const char *sky2_name(u8 chipid, char *buf, int sz)
4343 {
4344 const char *name[] = {
4345 "XL", /* 0xb3 */
4346 "EC Ultra", /* 0xb4 */
4347 "Extreme", /* 0xb5 */
4348 "EC", /* 0xb6 */
4349 "FE", /* 0xb7 */
4350 "FE+", /* 0xb8 */
4351 "Supreme", /* 0xb9 */
4352 "UL 2", /* 0xba */
4353 };
4354
4355 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
4356 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4357 else
4358 snprintf(buf, sz, "(chip %#x)", chipid);
4359 return buf;
4360 }
4361
4362 static int __devinit sky2_probe(struct pci_dev *pdev,
4363 const struct pci_device_id *ent)
4364 {
4365 struct net_device *dev;
4366 struct sky2_hw *hw;
4367 int err, using_dac = 0, wol_default;
4368 u32 reg;
4369 char buf1[16];
4370
4371 err = pci_enable_device(pdev);
4372 if (err) {
4373 dev_err(&pdev->dev, "cannot enable PCI device\n");
4374 goto err_out;
4375 }
4376
4377 /* Get configuration information
4378 * Note: only regular PCI config access once to test for HW issues
4379 * other PCI access through shared memory for speed and to
4380 * avoid MMCONFIG problems.
4381 */
4382 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4383 if (err) {
4384 dev_err(&pdev->dev, "PCI read config failed\n");
4385 goto err_out;
4386 }
4387
4388 if (~reg == 0) {
4389 dev_err(&pdev->dev, "PCI configuration read error\n");
4390 goto err_out;
4391 }
4392
4393 err = pci_request_regions(pdev, DRV_NAME);
4394 if (err) {
4395 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4396 goto err_out_disable;
4397 }
4398
4399 pci_set_master(pdev);
4400
4401 if (sizeof(dma_addr_t) > sizeof(u32) &&
4402 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4403 using_dac = 1;
4404 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4405 if (err < 0) {
4406 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4407 "for consistent allocations\n");
4408 goto err_out_free_regions;
4409 }
4410 } else {
4411 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4412 if (err) {
4413 dev_err(&pdev->dev, "no usable DMA configuration\n");
4414 goto err_out_free_regions;
4415 }
4416 }
4417
4418
4419 #ifdef __BIG_ENDIAN
4420 /* The sk98lin vendor driver uses hardware byte swapping but
4421 * this driver uses software swapping.
4422 */
4423 reg &= ~PCI_REV_DESC;
4424 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4425 if (err) {
4426 dev_err(&pdev->dev, "PCI write config failed\n");
4427 goto err_out_free_regions;
4428 }
4429 #endif
4430
4431 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4432
4433 err = -ENOMEM;
4434 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
4435 if (!hw) {
4436 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4437 goto err_out_free_regions;
4438 }
4439
4440 hw->pdev = pdev;
4441
4442 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4443 if (!hw->regs) {
4444 dev_err(&pdev->dev, "cannot map device registers\n");
4445 goto err_out_free_hw;
4446 }
4447
4448 /* ring for status responses */
4449 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4450 if (!hw->st_le)
4451 goto err_out_iounmap;
4452
4453 err = sky2_init(hw);
4454 if (err)
4455 goto err_out_iounmap;
4456
4457 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4458 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4459
4460 sky2_reset(hw);
4461
4462 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4463 if (!dev) {
4464 err = -ENOMEM;
4465 goto err_out_free_pci;
4466 }
4467
4468 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4469 err = sky2_test_msi(hw);
4470 if (err == -EOPNOTSUPP)
4471 pci_disable_msi(pdev);
4472 else if (err)
4473 goto err_out_free_netdev;
4474 }
4475
4476 err = register_netdev(dev);
4477 if (err) {
4478 dev_err(&pdev->dev, "cannot register net device\n");
4479 goto err_out_free_netdev;
4480 }
4481
4482 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4483
4484 err = request_irq(pdev->irq, sky2_intr,
4485 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4486 dev->name, hw);
4487 if (err) {
4488 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4489 goto err_out_unregister;
4490 }
4491 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4492 napi_enable(&hw->napi);
4493
4494 sky2_show_addr(dev);
4495
4496 if (hw->ports > 1) {
4497 struct net_device *dev1;
4498
4499 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4500 if (!dev1)
4501 dev_warn(&pdev->dev, "allocation for second device failed\n");
4502 else if ((err = register_netdev(dev1))) {
4503 dev_warn(&pdev->dev,
4504 "register of second port failed (%d)\n", err);
4505 hw->dev[1] = NULL;
4506 free_netdev(dev1);
4507 } else
4508 sky2_show_addr(dev1);
4509 }
4510
4511 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4512 INIT_WORK(&hw->restart_work, sky2_restart);
4513
4514 pci_set_drvdata(pdev, hw);
4515
4516 return 0;
4517
4518 err_out_unregister:
4519 if (hw->flags & SKY2_HW_USE_MSI)
4520 pci_disable_msi(pdev);
4521 unregister_netdev(dev);
4522 err_out_free_netdev:
4523 free_netdev(dev);
4524 err_out_free_pci:
4525 sky2_write8(hw, B0_CTST, CS_RST_SET);
4526 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4527 err_out_iounmap:
4528 iounmap(hw->regs);
4529 err_out_free_hw:
4530 kfree(hw);
4531 err_out_free_regions:
4532 pci_release_regions(pdev);
4533 err_out_disable:
4534 pci_disable_device(pdev);
4535 err_out:
4536 pci_set_drvdata(pdev, NULL);
4537 return err;
4538 }
4539
4540 static void __devexit sky2_remove(struct pci_dev *pdev)
4541 {
4542 struct sky2_hw *hw = pci_get_drvdata(pdev);
4543 int i;
4544
4545 if (!hw)
4546 return;
4547
4548 del_timer_sync(&hw->watchdog_timer);
4549 cancel_work_sync(&hw->restart_work);
4550
4551 for (i = hw->ports-1; i >= 0; --i)
4552 unregister_netdev(hw->dev[i]);
4553
4554 sky2_write32(hw, B0_IMSK, 0);
4555
4556 sky2_power_aux(hw);
4557
4558 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4559 sky2_write8(hw, B0_CTST, CS_RST_SET);
4560 sky2_read8(hw, B0_CTST);
4561
4562 free_irq(pdev->irq, hw);
4563 if (hw->flags & SKY2_HW_USE_MSI)
4564 pci_disable_msi(pdev);
4565 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4566 pci_release_regions(pdev);
4567 pci_disable_device(pdev);
4568
4569 for (i = hw->ports-1; i >= 0; --i)
4570 free_netdev(hw->dev[i]);
4571
4572 iounmap(hw->regs);
4573 kfree(hw);
4574
4575 pci_set_drvdata(pdev, NULL);
4576 }
4577
4578 #ifdef CONFIG_PM
4579 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4580 {
4581 struct sky2_hw *hw = pci_get_drvdata(pdev);
4582 int i, wol = 0;
4583
4584 if (!hw)
4585 return 0;
4586
4587 del_timer_sync(&hw->watchdog_timer);
4588 cancel_work_sync(&hw->restart_work);
4589
4590 for (i = 0; i < hw->ports; i++) {
4591 struct net_device *dev = hw->dev[i];
4592 struct sky2_port *sky2 = netdev_priv(dev);
4593
4594 netif_device_detach(dev);
4595 if (netif_running(dev))
4596 sky2_down(dev);
4597
4598 if (sky2->wol)
4599 sky2_wol_init(sky2);
4600
4601 wol |= sky2->wol;
4602 }
4603
4604 sky2_write32(hw, B0_IMSK, 0);
4605 napi_disable(&hw->napi);
4606 sky2_power_aux(hw);
4607
4608 pci_save_state(pdev);
4609 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4610 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4611
4612 return 0;
4613 }
4614
4615 static int sky2_resume(struct pci_dev *pdev)
4616 {
4617 struct sky2_hw *hw = pci_get_drvdata(pdev);
4618 int i, err;
4619
4620 if (!hw)
4621 return 0;
4622
4623 err = pci_set_power_state(pdev, PCI_D0);
4624 if (err)
4625 goto out;
4626
4627 err = pci_restore_state(pdev);
4628 if (err)
4629 goto out;
4630
4631 pci_enable_wake(pdev, PCI_D0, 0);
4632
4633 /* Re-enable all clocks */
4634 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4635 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4636 hw->chip_id == CHIP_ID_YUKON_FE_P)
4637 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4638
4639 sky2_reset(hw);
4640 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4641 napi_enable(&hw->napi);
4642
4643 for (i = 0; i < hw->ports; i++) {
4644 struct net_device *dev = hw->dev[i];
4645
4646 netif_device_attach(dev);
4647 if (netif_running(dev)) {
4648 err = sky2_up(dev);
4649 if (err) {
4650 printk(KERN_ERR PFX "%s: could not up: %d\n",
4651 dev->name, err);
4652 rtnl_lock();
4653 dev_close(dev);
4654 rtnl_unlock();
4655 goto out;
4656 }
4657 }
4658 }
4659
4660 return 0;
4661 out:
4662 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4663 pci_disable_device(pdev);
4664 return err;
4665 }
4666 #endif
4667
4668 static void sky2_shutdown(struct pci_dev *pdev)
4669 {
4670 struct sky2_hw *hw = pci_get_drvdata(pdev);
4671 int i, wol = 0;
4672
4673 if (!hw)
4674 return;
4675
4676 del_timer_sync(&hw->watchdog_timer);
4677
4678 for (i = 0; i < hw->ports; i++) {
4679 struct net_device *dev = hw->dev[i];
4680 struct sky2_port *sky2 = netdev_priv(dev);
4681
4682 if (sky2->wol) {
4683 wol = 1;
4684 sky2_wol_init(sky2);
4685 }
4686 }
4687
4688 if (wol)
4689 sky2_power_aux(hw);
4690
4691 pci_enable_wake(pdev, PCI_D3hot, wol);
4692 pci_enable_wake(pdev, PCI_D3cold, wol);
4693
4694 pci_disable_device(pdev);
4695 pci_set_power_state(pdev, PCI_D3hot);
4696 }
4697
4698 static struct pci_driver sky2_driver = {
4699 .name = DRV_NAME,
4700 .id_table = sky2_id_table,
4701 .probe = sky2_probe,
4702 .remove = __devexit_p(sky2_remove),
4703 #ifdef CONFIG_PM
4704 .suspend = sky2_suspend,
4705 .resume = sky2_resume,
4706 #endif
4707 .shutdown = sky2_shutdown,
4708 };
4709
4710 static int __init sky2_init_module(void)
4711 {
4712 pr_info(PFX "driver version " DRV_VERSION "\n");
4713
4714 sky2_debug_init();
4715 return pci_register_driver(&sky2_driver);
4716 }
4717
4718 static void __exit sky2_cleanup_module(void)
4719 {
4720 pci_unregister_driver(&sky2_driver);
4721 sky2_debug_cleanup();
4722 }
4723
4724 module_init(sky2_init_module);
4725 module_exit(sky2_cleanup_module);
4726
4727 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4728 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4729 MODULE_LICENSE("GPL");
4730 MODULE_VERSION(DRV_VERSION);
AMDTP streaming driver for the Linux FireWire stack (Juju)