arch/x86/kernel/setup_64.c

   1 /*
   2  *  Copyright (C) 1995  Linus Torvalds
   3  */
   4
   5 /*
   6  * This file handles the architecture-dependent parts of initialization
   7  */
   8
   9 #include <linux/errno.h>
  10 #include <linux/sched.h>
  11 #include <linux/kernel.h>
  12 #include <linux/mm.h>
  13 #include <linux/stddef.h>
  14 #include <linux/unistd.h>
  15 #include <linux/ptrace.h>
  16 #include <linux/slab.h>
  17 #include <linux/user.h>
  18 #include <linux/screen_info.h>
  19 #include <linux/ioport.h>
  20 #include <linux/delay.h>
  21 #include <linux/init.h>
  22 #include <linux/initrd.h>
  23 #include <linux/highmem.h>
  24 #include <linux/bootmem.h>
  25 #include <linux/module.h>
  26 #include <asm/processor.h>
  27 #include <linux/console.h>
  28 #include <linux/seq_file.h>
  29 #include <linux/crash_dump.h>
  30 #include <linux/root_dev.h>
  31 #include <linux/pci.h>
  32 #include <linux/efi.h>
  33 #include <linux/acpi.h>
  34 #include <linux/kallsyms.h>
  35 #include <linux/edd.h>
  36 #include <linux/iscsi_ibft.h>
  37 #include <linux/mmzone.h>
  38 #include <linux/kexec.h>
  39 #include <linux/cpufreq.h>
  40 #include <linux/dmi.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/ctype.h>
  43 #include <linux/uaccess.h>
  44 #include <linux/init_ohci1394_dma.h>
  45
  46 #include <asm/mtrr.h>
  47 #include <asm/uaccess.h>
  48 #include <asm/system.h>
  49 #include <asm/vsyscall.h>
  50 #include <asm/io.h>
  51 #include <asm/smp.h>
  52 #include <asm/msr.h>
  53 #include <asm/desc.h>
  54 #include <video/edid.h>
  55 #include <asm/e820.h>
  56 #include <asm/dma.h>
  57 #include <asm/gart.h>
  58 #include <asm/mpspec.h>
  59 #include <asm/mmu_context.h>
  60 #include <asm/proto.h>
  61 #include <asm/setup.h>
  62 #include <asm/numa.h>
  63 #include <asm/sections.h>
  64 #include <asm/dmi.h>
  65 #include <asm/cacheflush.h>
  66 #include <asm/mce.h>
  67 #include <asm/ds.h>
  68 #include <asm/topology.h>
  69 #include <asm/trampoline.h>
  70
  71 #include <mach_apic.h>
  72 #ifdef CONFIG_PARAVIRT
  73 #include <asm/paravirt.h>
  74 #else
  75 #define ARCH_SETUP
  76 #endif
  77
  78 /*
  79  * Machine setup..
  80  */
  81
  82 struct cpuinfo_x86 boot_cpu_data __read_mostly;
  83 EXPORT_SYMBOL(boot_cpu_data);
  84
  85 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
  86
  87 unsigned long mmu_cr4_features;
  88
  89 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
  90 int bootloader_type;
  91
  92 unsigned long saved_video_mode;
  93
  94 int force_mwait __cpuinitdata;
  95
  96 /*
  97  * Early DMI memory
  98  */
  99 int dmi_alloc_index;
 100 char dmi_alloc_data[DMI_MAX_DATA];
 101
 102 /*
 103  * Setup options
 104  */
 105 struct screen_info screen_info;
 106 EXPORT_SYMBOL(screen_info);
 107 struct sys_desc_table_struct {
 108         unsigned short length;
 109         unsigned char table[0];
 110 };
 111
 112 struct edid_info edid_info;
 113 EXPORT_SYMBOL_GPL(edid_info);
 114
 115 extern int root_mountflags;
 116
 117 char __initdata command_line[COMMAND_LINE_SIZE];
 118
 119 struct resource standard_io_resources[] = {
 120         { .name = "dma1", .start = 0x00, .end = 0x1f,
 121                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 122         { .name = "pic1", .start = 0x20, .end = 0x21,
 123                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 124         { .name = "timer0", .start = 0x40, .end = 0x43,
 125                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 126         { .name = "timer1", .start = 0x50, .end = 0x53,
 127                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 128         { .name = "keyboard", .start = 0x60, .end = 0x6f,
 129                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 130         { .name = "dma page reg", .start = 0x80, .end = 0x8f,
 131                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 132         { .name = "pic2", .start = 0xa0, .end = 0xa1,
 133                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 134         { .name = "dma2", .start = 0xc0, .end = 0xdf,
 135                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 136         { .name = "fpu", .start = 0xf0, .end = 0xff,
 137                 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
 138 };
 139
 140 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
 141
 142 static struct resource data_resource = {
 143         .name = "Kernel data",
 144         .start = 0,
 145         .end = 0,
 146         .flags = IORESOURCE_RAM,
 147 };
 148 static struct resource code_resource = {
 149         .name = "Kernel code",
 150         .start = 0,
 151         .end = 0,
 152         .flags = IORESOURCE_RAM,
 153 };
 154 static struct resource bss_resource = {
 155         .name = "Kernel bss",
 156         .start = 0,
 157         .end = 0,
 158         .flags = IORESOURCE_RAM,
 159 };
 160
 161 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
 162
 163 #ifdef CONFIG_PROC_VMCORE
 164 /* elfcorehdr= specifies the location of elf core header
 165  * stored by the crashed kernel. This option will be passed
 166  * by kexec loader to the capture kernel.
 167  */
 168 static int __init setup_elfcorehdr(char *arg)
 169 {
 170         char *end;
 171         if (!arg)
 172                 return -EINVAL;
 173         elfcorehdr_addr = memparse(arg, &end);
 174         return end > arg ? 0 : -EINVAL;
 175 }
 176 early_param("elfcorehdr", setup_elfcorehdr);
 177 #endif
 178
 179 #ifndef CONFIG_NUMA
 180 static void __init
 181 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
 182 {
 183         unsigned long bootmap_size, bootmap;
 184
 185         bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
 186         bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size,
 187                                  PAGE_SIZE);
 188         if (bootmap == -1L)
 189                 panic("Cannot find bootmem map of size %ld\n", bootmap_size);
 190         bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
 191         e820_register_active_regions(0, start_pfn, end_pfn);
 192         free_bootmem_with_active_regions(0, end_pfn);
 193         reserve_bootmem(bootmap, bootmap_size, BOOTMEM_DEFAULT);
 194 }
 195 #endif
 196
 197 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
 198 struct edd edd;
 199 #ifdef CONFIG_EDD_MODULE
 200 EXPORT_SYMBOL(edd);
 201 #endif
 202 /**
 203  * copy_edd() - Copy the BIOS EDD information
 204  *              from boot_params into a safe place.
 205  *
 206  */
 207 static inline void copy_edd(void)
 208 {
 209      memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
 210             sizeof(edd.mbr_signature));
 211      memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
 212      edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
 213      edd.edd_info_nr = boot_params.eddbuf_entries;
 214 }
 215 #else
 216 static inline void copy_edd(void)
 217 {
 218 }
 219 #endif
 220
 221 #ifdef CONFIG_KEXEC
 222 static void __init reserve_crashkernel(void)
 223 {
 224         unsigned long long total_mem;
 225         unsigned long long crash_size, crash_base;
 226         int ret;
 227
 228         total_mem = ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
 229
 230         ret = parse_crashkernel(boot_command_line, total_mem,
 231                         &crash_size, &crash_base);
 232         if (ret == 0 && crash_size) {
 233                 if (crash_base <= 0) {
 234                         printk(KERN_INFO "crashkernel reservation failed - "
 235                                         "you have to specify a base address\n");
 236                         return;
 237                 }
 238
 239                 if (reserve_bootmem(crash_base, crash_size,
 240                                         BOOTMEM_EXCLUSIVE) < 0) {
 241                         printk(KERN_INFO "crashkernel reservation failed - "
 242                                         "memory is in use\n");
 243                         return;
 244                 }
 245
 246                 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
 247                                 "for crashkernel (System RAM: %ldMB)\n",
 248                                 (unsigned long)(crash_size >> 20),
 249                                 (unsigned long)(crash_base >> 20),
 250                                 (unsigned long)(total_mem >> 20));
 251                 crashk_res.start = crash_base;
 252                 crashk_res.end   = crash_base + crash_size - 1;
 253                 insert_resource(&iomem_resource, &crashk_res);
 254         }
 255 }
 256 #else
 257 static inline void __init reserve_crashkernel(void)
 258 {}
 259 #endif
 260
 261 /* Overridden in paravirt.c if CONFIG_PARAVIRT */
 262 void __attribute__((weak)) __init memory_setup(void)
 263 {
 264        machine_specific_memory_setup();
 265 }
 266
 267 /*
 268  * setup_arch - architecture-specific boot-time initializations
 269  *
 270  * Note: On x86_64, fixmaps are ready for use even before this is called.
 271  */
 272 void __init setup_arch(char **cmdline_p)
 273 {
 274         unsigned i;
 275
 276         printk(KERN_INFO "Command line: %s\n", boot_command_line);
 277
 278         ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
 279         screen_info = boot_params.screen_info;
 280         edid_info = boot_params.edid_info;
 281         saved_video_mode = boot_params.hdr.vid_mode;
 282         bootloader_type = boot_params.hdr.type_of_loader;
 283
 284 #ifdef CONFIG_BLK_DEV_RAM
 285         rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
 286         rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
 287         rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
 288 #endif
 289 #ifdef CONFIG_EFI
 290         if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
 291                      "EL64", 4))
 292                 efi_enabled = 1;
 293 #endif
 294
 295         ARCH_SETUP
 296
 297         memory_setup();
 298         copy_edd();
 299
 300         if (!boot_params.hdr.root_flags)
 301                 root_mountflags &= ~MS_RDONLY;
 302         init_mm.start_code = (unsigned long) &_text;
 303         init_mm.end_code = (unsigned long) &_etext;
 304         init_mm.end_data = (unsigned long) &_edata;
 305         init_mm.brk = (unsigned long) &_end;
 306
 307         code_resource.start = virt_to_phys(&_text);
 308         code_resource.end = virt_to_phys(&_etext)-1;
 309         data_resource.start = virt_to_phys(&_etext);
 310         data_resource.end = virt_to_phys(&_edata)-1;
 311         bss_resource.start = virt_to_phys(&__bss_start);
 312         bss_resource.end = virt_to_phys(&__bss_stop)-1;
 313
 314         early_identify_cpu(&boot_cpu_data);
 315
 316         strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
 317         *cmdline_p = command_line;
 318
 319         parse_early_param();
 320
 321 #ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
 322         if (init_ohci1394_dma_early)
 323                 init_ohci1394_dma_on_all_controllers();
 324 #endif
 325
 326         finish_e820_parsing();
 327
 328         /* after parse_early_param, so could debug it */
 329         insert_resource(&iomem_resource, &code_resource);
 330         insert_resource(&iomem_resource, &data_resource);
 331         insert_resource(&iomem_resource, &bss_resource);
 332
 333         early_gart_iommu_check();
 334
 335         e820_register_active_regions(0, 0, -1UL);
 336         /*
 337          * partially used pages are not usable - thus
 338          * we are rounding upwards:
 339          */
 340         end_pfn = e820_end_of_ram();
 341         /* update e820 for memory not covered by WB MTRRs */
 342         mtrr_bp_init();
 343         if (mtrr_trim_uncached_memory(end_pfn)) {
 344                 e820_register_active_regions(0, 0, -1UL);
 345                 end_pfn = e820_end_of_ram();
 346         }
 347
 348         num_physpages = end_pfn;
 349
 350         check_efer();
 351
 352         max_pfn_mapped = init_memory_mapping(0, (max_pfn_mapped << PAGE_SHIFT));
 353         if (efi_enabled)
 354                 efi_init();
 355
 356         vsmp_init();
 357
 358         dmi_scan_machine();
 359
 360         io_delay_init();
 361
 362 #ifdef CONFIG_SMP
 363         /* setup to use the early static init tables during kernel startup */
 364         x86_cpu_to_apicid_early_ptr = (void *)x86_cpu_to_apicid_init;
 365         x86_bios_cpu_apicid_early_ptr = (void *)x86_bios_cpu_apicid_init;
 366 #ifdef CONFIG_NUMA
 367         x86_cpu_to_node_map_early_ptr = (void *)x86_cpu_to_node_map_init;
 368 #endif
 369 #endif
 370
 371 #ifdef CONFIG_ACPI
 372         /*
 373          * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
 374          * Call this early for SRAT node setup.
 375          */
 376         acpi_boot_table_init();
 377 #endif
 378
 379         /* How many end-of-memory variables you have, grandma! */
 380         max_low_pfn = end_pfn;
 381         max_pfn = end_pfn;
 382         high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
 383
 384         /* Remove active ranges so rediscovery with NUMA-awareness happens */
 385         remove_all_active_ranges();
 386
 387 #ifdef CONFIG_ACPI_NUMA
 388         /*
 389          * Parse SRAT to discover nodes.
 390          */
 391         acpi_numa_init();
 392 #endif
 393
 394 #ifdef CONFIG_NUMA
 395         numa_initmem_init(0, end_pfn);
 396 #else
 397         contig_initmem_init(0, end_pfn);
 398 #endif
 399
 400         early_res_to_bootmem();
 401
 402         dma32_reserve_bootmem();
 403
 404 #ifdef CONFIG_ACPI_SLEEP
 405         /*
 406          * Reserve low memory region for sleep support.
 407          */
 408        acpi_reserve_bootmem();
 409 #endif
 410
 411         if (efi_enabled)
 412                 efi_reserve_bootmem();
 413
 414        /*
 415         * Find and reserve possible boot-time SMP configuration:
 416         */
 417         find_smp_config();
 418 #ifdef CONFIG_BLK_DEV_INITRD
 419         if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
 420                 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
 421                 unsigned long ramdisk_size  = boot_params.hdr.ramdisk_size;
 422                 unsigned long ramdisk_end   = ramdisk_image + ramdisk_size;
 423                 unsigned long end_of_mem    = end_pfn << PAGE_SHIFT;
 424
 425                 if (ramdisk_end <= end_of_mem) {
 426                         /*
 427                          * don't need to reserve again, already reserved early
 428                          * in x86_64_start_kernel, and early_res_to_bootmem
 429                          * convert that to reserved in bootmem
 430                          */
 431                         initrd_start = ramdisk_image + PAGE_OFFSET;
 432                         initrd_end = initrd_start+ramdisk_size;
 433                 } else {
 434                         free_bootmem(ramdisk_image, ramdisk_size);
 435                         printk(KERN_ERR "initrd extends beyond end of memory "
 436                                "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
 437                                ramdisk_end, end_of_mem);
 438                         initrd_start = 0;
 439                 }
 440         }
 441 #endif
 442         reserve_crashkernel();
 443
 444         reserve_ibft_region();
 445
 446         paging_init();
 447         map_vsyscall();
 448
 449         early_quirks();
 450
 451 #ifdef CONFIG_ACPI
 452         /*
 453          * Read APIC and some other early information from ACPI tables.
 454          */
 455         acpi_boot_init();
 456 #endif
 457
 458         init_cpu_to_node();
 459
 460         /*
 461          * get boot-time SMP configuration:
 462          */
 463         if (smp_found_config)
 464                 get_smp_config();
 465         init_apic_mappings();
 466         ioapic_init_mappings();
 467
 468         /*
 469          * We trust e820 completely. No explicit ROM probing in memory.
 470          */
 471         e820_reserve_resources();
 472         e820_mark_nosave_regions();
 473
 474         /* request I/O space for devices used on all i[345]86 PCs */
 475         for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
 476                 request_resource(&ioport_resource, &standard_io_resources[i]);
 477
 478         e820_setup_gap();
 479
 480 #ifdef CONFIG_VT
 481 #if defined(CONFIG_VGA_CONSOLE)
 482         if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
 483                 conswitchp = &vga_con;
 484 #elif defined(CONFIG_DUMMY_CONSOLE)
 485         conswitchp = &dummy_con;
 486 #endif
 487 #endif
 488 }
 489
 490 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
 491 {
 492         unsigned int *v;
 493
 494         if (c->extended_cpuid_level < 0x80000004)
 495                 return 0;
 496
 497         v = (unsigned int *) c->x86_model_id;
 498         cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
 499         cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
 500         cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
 501         c->x86_model_id[48] = 0;
 502         return 1;
 503 }
 504
 505
 506 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
 507 {
 508         unsigned int n, dummy, eax, ebx, ecx, edx;
 509
 510         n = c->extended_cpuid_level;
 511
 512         if (n >= 0x80000005) {
 513                 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
 514                 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
 515                        "D cache %dK (%d bytes/line)\n",
 516                        edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
 517                 c->x86_cache_size = (ecx>>24) + (edx>>24);
 518                 /* On K8 L1 TLB is inclusive, so don't count it */
 519                 c->x86_tlbsize = 0;
 520         }
 521
 522         if (n >= 0x80000006) {
 523                 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
 524                 ecx = cpuid_ecx(0x80000006);
 525                 c->x86_cache_size = ecx >> 16;
 526                 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
 527
 528                 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
 529                 c->x86_cache_size, ecx & 0xFF);
 530         }
 531         if (n >= 0x80000008) {
 532                 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
 533                 c->x86_virt_bits = (eax >> 8) & 0xff;
 534                 c->x86_phys_bits = eax & 0xff;
 535         }
 536 }
 537
 538 #ifdef CONFIG_NUMA
 539 static int __cpuinit nearby_node(int apicid)
 540 {
 541         int i, node;
 542
 543         for (i = apicid - 1; i >= 0; i--) {
 544                 node = apicid_to_node[i];
 545                 if (node != NUMA_NO_NODE && node_online(node))
 546                         return node;
 547         }
 548         for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
 549                 node = apicid_to_node[i];
 550                 if (node != NUMA_NO_NODE && node_online(node))
 551                         return node;
 552         }
 553         return first_node(node_online_map); /* Shouldn't happen */
 554 }
 555 #endif
 556
 557 /*
 558  * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
 559  * Assumes number of cores is a power of two.
 560  */
 561 static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
 562 {
 563 #ifdef CONFIG_SMP
 564         unsigned bits;
 565 #ifdef CONFIG_NUMA
 566         int cpu = smp_processor_id();
 567         int node = 0;
 568         unsigned apicid = hard_smp_processor_id();
 569 #endif
 570         bits = c->x86_coreid_bits;
 571
 572         /* Low order bits define the core id (index of core in socket) */
 573         c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
 574         /* Convert the initial APIC ID into the socket ID */
 575         c->phys_proc_id = c->initial_apicid >> bits;
 576
 577 #ifdef CONFIG_NUMA
 578         node = c->phys_proc_id;
 579         if (apicid_to_node[apicid] != NUMA_NO_NODE)
 580                 node = apicid_to_node[apicid];
 581         if (!node_online(node)) {
 582                 /* Two possibilities here:
 583                    - The CPU is missing memory and no node was created.
 584                    In that case try picking one from a nearby CPU
 585                    - The APIC IDs differ from the HyperTransport node IDs
 586                    which the K8 northbridge parsing fills in.
 587                    Assume they are all increased by a constant offset,
 588                    but in the same order as the HT nodeids.
 589                    If that doesn't result in a usable node fall back to the
 590                    path for the previous case.  */
 591
 592                 int ht_nodeid = c->initial_apicid;
 593
 594                 if (ht_nodeid >= 0 &&
 595                     apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
 596                         node = apicid_to_node[ht_nodeid];
 597                 /* Pick a nearby node */
 598                 if (!node_online(node))
 599                         node = nearby_node(apicid);
 600         }
 601         numa_set_node(cpu, node);
 602
 603         printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
 604 #endif
 605 #endif
 606 }
 607
 608 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
 609 {
 610 #ifdef CONFIG_SMP
 611         unsigned bits, ecx;
 612
 613         /* Multi core CPU? */
 614         if (c->extended_cpuid_level < 0x80000008)
 615                 return;
 616
 617         ecx = cpuid_ecx(0x80000008);
 618
 619         c->x86_max_cores = (ecx & 0xff) + 1;
 620
 621         /* CPU telling us the core id bits shift? */
 622         bits = (ecx >> 12) & 0xF;
 623
 624         /* Otherwise recompute */
 625         if (bits == 0) {
 626                 while ((1 << bits) < c->x86_max_cores)
 627                         bits++;
 628         }
 629
 630         c->x86_coreid_bits = bits;
 631
 632 #endif
 633 }
 634
 635 #define ENABLE_C1E_MASK         0x18000000
 636 #define CPUID_PROCESSOR_SIGNATURE       1
 637 #define CPUID_XFAM              0x0ff00000
 638 #define CPUID_XFAM_K8           0x00000000
 639 #define CPUID_XFAM_10H          0x00100000
 640 #define CPUID_XFAM_11H          0x00200000
 641 #define CPUID_XMOD              0x000f0000
 642 #define CPUID_XMOD_REV_F        0x00040000
 643
 644 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
 645 static __cpuinit int amd_apic_timer_broken(void)
 646 {
 647         u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
 648
 649         switch (eax & CPUID_XFAM) {
 650         case CPUID_XFAM_K8:
 651                 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
 652                         break;
 653         case CPUID_XFAM_10H:
 654         case CPUID_XFAM_11H:
 655                 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
 656                 if (lo & ENABLE_C1E_MASK)
 657                         return 1;
 658                 break;
 659         default:
 660                 /* err on the side of caution */
 661                 return 1;
 662         }
 663         return 0;
 664 }
 665
 666 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
 667 {
 668         early_init_amd_mc(c);
 669
 670         /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
 671         if (c->x86_power & (1<<8))
 672                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 673 }
 674
 675 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 676 {
 677         unsigned level;
 678
 679 #ifdef CONFIG_SMP
 680         unsigned long value;
 681
 682         /*
 683          * Disable TLB flush filter by setting HWCR.FFDIS on K8
 684          * bit 6 of msr C001_0015
 685          *
 686          * Errata 63 for SH-B3 steppings
 687          * Errata 122 for all steppings (F+ have it disabled by default)
 688          */
 689         if (c->x86 == 15) {
 690                 rdmsrl(MSR_K8_HWCR, value);
 691                 value |= 1 << 6;
 692                 wrmsrl(MSR_K8_HWCR, value);
 693         }
 694 #endif
 695
 696         /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
 697            3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
 698         clear_cpu_cap(c, 0*32+31);
 699
 700         /* On C+ stepping K8 rep microcode works well for copy/memset */
 701         level = cpuid_eax(1);
 702         if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
 703                              level >= 0x0f58))
 704                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 705         if (c->x86 == 0x10 || c->x86 == 0x11)
 706                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 707
 708         /* Enable workaround for FXSAVE leak */
 709         if (c->x86 >= 6)
 710                 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
 711
 712         level = get_model_name(c);
 713         if (!level) {
 714                 switch (c->x86) {
 715                 case 15:
 716                         /* Should distinguish Models here, but this is only
 717                            a fallback anyways. */
 718                         strcpy(c->x86_model_id, "Hammer");
 719                         break;
 720                 }
 721         }
 722         display_cacheinfo(c);
 723
 724         /* Multi core CPU? */
 725         if (c->extended_cpuid_level >= 0x80000008)
 726                 amd_detect_cmp(c);
 727
 728         if (c->extended_cpuid_level >= 0x80000006 &&
 729                 (cpuid_edx(0x80000006) & 0xf000))
 730                 num_cache_leaves = 4;
 731         else
 732                 num_cache_leaves = 3;
 733
 734         if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
 735                 set_cpu_cap(c, X86_FEATURE_K8);
 736
 737         /* MFENCE stops RDTSC speculation */
 738         set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
 739
 740         if (amd_apic_timer_broken())
 741                 disable_apic_timer = 1;
 742
 743         if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
 744                 unsigned long long tseg;
 745
 746                 /*
 747                  * Split up direct mapping around the TSEG SMM area.
 748                  * Don't do it for gbpages because there seems very little
 749                  * benefit in doing so.
 750                  */
 751                 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg) &&
 752                 (tseg >> PMD_SHIFT) < (max_pfn_mapped >> (PMD_SHIFT-PAGE_SHIFT)))
 753                         set_memory_4k((unsigned long)__va(tseg), 1);
 754         }
 755 }
 756
 757 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
 758 {
 759 #ifdef CONFIG_SMP
 760         u32 eax, ebx, ecx, edx;
 761         int index_msb, core_bits;
 762
 763         cpuid(1, &eax, &ebx, &ecx, &edx);
 764
 765
 766         if (!cpu_has(c, X86_FEATURE_HT))
 767                 return;
 768         if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
 769                 goto out;
 770
 771         smp_num_siblings = (ebx & 0xff0000) >> 16;
 772
 773         if (smp_num_siblings == 1) {
 774                 printk(KERN_INFO  "CPU: Hyper-Threading is disabled\n");
 775         } else if (smp_num_siblings > 1) {
 776
 777                 if (smp_num_siblings > NR_CPUS) {
 778                         printk(KERN_WARNING "CPU: Unsupported number of "
 779                                "siblings %d", smp_num_siblings);
 780                         smp_num_siblings = 1;
 781                         return;
 782                 }
 783
 784                 index_msb = get_count_order(smp_num_siblings);
 785                 c->phys_proc_id = phys_pkg_id(index_msb);
 786
 787                 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
 788
 789                 index_msb = get_count_order(smp_num_siblings);
 790
 791                 core_bits = get_count_order(c->x86_max_cores);
 792
 793                 c->cpu_core_id = phys_pkg_id(index_msb) &
 794                                                ((1 << core_bits) - 1);
 795         }
 796 out:
 797         if ((c->x86_max_cores * smp_num_siblings) > 1) {
 798                 printk(KERN_INFO  "CPU: Physical Processor ID: %d\n",
 799                        c->phys_proc_id);
 800                 printk(KERN_INFO  "CPU: Processor Core ID: %d\n",
 801                        c->cpu_core_id);
 802         }
 803
 804 #endif
 805 }
 806
 807 /*
 808  * find out the number of processor cores on the die
 809  */
 810 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
 811 {
 812         unsigned int eax, t;
 813
 814         if (c->cpuid_level < 4)
 815                 return 1;
 816
 817         cpuid_count(4, 0, &eax, &t, &t, &t);
 818
 819         if (eax & 0x1f)
 820                 return ((eax >> 26) + 1);
 821         else
 822                 return 1;
 823 }
 824
 825 static void __cpuinit srat_detect_node(void)
 826 {
 827 #ifdef CONFIG_NUMA
 828         unsigned node;
 829         int cpu = smp_processor_id();
 830         int apicid = hard_smp_processor_id();
 831
 832         /* Don't do the funky fallback heuristics the AMD version employs
 833            for now. */
 834         node = apicid_to_node[apicid];
 835         if (node == NUMA_NO_NODE || !node_online(node))
 836                 node = first_node(node_online_map);
 837         numa_set_node(cpu, node);
 838
 839         printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
 840 #endif
 841 }
 842
 843 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
 844 {
 845         if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
 846             (c->x86 == 0x6 && c->x86_model >= 0x0e))
 847                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 848 }
 849
 850 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 851 {
 852         /* Cache sizes */
 853         unsigned n;
 854
 855         init_intel_cacheinfo(c);
 856         if (c->cpuid_level > 9) {
 857                 unsigned eax = cpuid_eax(10);
 858                 /* Check for version and the number of counters */
 859                 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
 860                         set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
 861         }
 862
 863         if (cpu_has_ds) {
 864                 unsigned int l1, l2;
 865                 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
 866                 if (!(l1 & (1<<11)))
 867                         set_cpu_cap(c, X86_FEATURE_BTS);
 868                 if (!(l1 & (1<<12)))
 869                         set_cpu_cap(c, X86_FEATURE_PEBS);
 870         }
 871
 872
 873         if (cpu_has_bts)
 874                 ds_init_intel(c);
 875
 876         n = c->extended_cpuid_level;
 877         if (n >= 0x80000008) {
 878                 unsigned eax = cpuid_eax(0x80000008);
 879                 c->x86_virt_bits = (eax >> 8) & 0xff;
 880                 c->x86_phys_bits = eax & 0xff;
 881                 /* CPUID workaround for Intel 0F34 CPU */
 882                 if (c->x86_vendor == X86_VENDOR_INTEL &&
 883                     c->x86 == 0xF && c->x86_model == 0x3 &&
 884                     c->x86_mask == 0x4)
 885                         c->x86_phys_bits = 36;
 886         }
 887
 888         if (c->x86 == 15)
 889                 c->x86_cache_alignment = c->x86_clflush_size * 2;
 890         if (c->x86 == 6)
 891                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 892         set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
 893         c->x86_max_cores = intel_num_cpu_cores(c);
 894
 895         srat_detect_node();
 896 }
 897
 898 static void __cpuinit early_init_centaur(struct cpuinfo_x86 *c)
 899 {
 900         if (c->x86 == 0x6 && c->x86_model >= 0xf)
 901                 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
 902 }
 903
 904 static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
 905 {
 906         /* Cache sizes */
 907         unsigned n;
 908
 909         n = c->extended_cpuid_level;
 910         if (n >= 0x80000008) {
 911                 unsigned eax = cpuid_eax(0x80000008);
 912                 c->x86_virt_bits = (eax >> 8) & 0xff;
 913                 c->x86_phys_bits = eax & 0xff;
 914         }
 915
 916         if (c->x86 == 0x6 && c->x86_model >= 0xf) {
 917                 c->x86_cache_alignment = c->x86_clflush_size * 2;
 918                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 919                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 920         }
 921         set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
 922 }
 923
 924 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
 925 {
 926         char *v = c->x86_vendor_id;
 927
 928         if (!strcmp(v, "AuthenticAMD"))
 929                 c->x86_vendor = X86_VENDOR_AMD;
 930         else if (!strcmp(v, "GenuineIntel"))
 931                 c->x86_vendor = X86_VENDOR_INTEL;
 932         else if (!strcmp(v, "CentaurHauls"))
 933                 c->x86_vendor = X86_VENDOR_CENTAUR;
 934         else
 935                 c->x86_vendor = X86_VENDOR_UNKNOWN;
 936 }
 937
 938 /* Do some early cpuid on the boot CPU to get some parameter that are
 939    needed before check_bugs. Everything advanced is in identify_cpu
 940    below. */
 941 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
 942 {
 943         u32 tfms, xlvl;
 944
 945         c->loops_per_jiffy = loops_per_jiffy;
 946         c->x86_cache_size = -1;
 947         c->x86_vendor = X86_VENDOR_UNKNOWN;
 948         c->x86_model = c->x86_mask = 0; /* So far unknown... */
 949         c->x86_vendor_id[0] = '\0'; /* Unset */
 950         c->x86_model_id[0] = '\0';  /* Unset */
 951         c->x86_clflush_size = 64;
 952         c->x86_cache_alignment = c->x86_clflush_size;
 953         c->x86_max_cores = 1;
 954         c->x86_coreid_bits = 0;
 955         c->extended_cpuid_level = 0;
 956         memset(&c->x86_capability, 0, sizeof c->x86_capability);
 957
 958         /* Get vendor name */
 959         cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
 960               (unsigned int *)&c->x86_vendor_id[0],
 961               (unsigned int *)&c->x86_vendor_id[8],
 962               (unsigned int *)&c->x86_vendor_id[4]);
 963
 964         get_cpu_vendor(c);
 965
 966         /* Initialize the standard set of capabilities */
 967         /* Note that the vendor-specific code below might override */
 968
 969         /* Intel-defined flags: level 0x00000001 */
 970         if (c->cpuid_level >= 0x00000001) {
 971                 __u32 misc;
 972                 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
 973                       &c->x86_capability[0]);
 974                 c->x86 = (tfms >> 8) & 0xf;
 975                 c->x86_model = (tfms >> 4) & 0xf;
 976                 c->x86_mask = tfms & 0xf;
 977                 if (c->x86 == 0xf)
 978                         c->x86 += (tfms >> 20) & 0xff;
 979                 if (c->x86 >= 0x6)
 980                         c->x86_model += ((tfms >> 16) & 0xF) << 4;
 981                 if (test_cpu_cap(c, X86_FEATURE_CLFLSH))
 982                         c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
 983         } else {
 984                 /* Have CPUID level 0 only - unheard of */
 985                 c->x86 = 4;
 986         }
 987
 988         c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xff;
 989 #ifdef CONFIG_SMP
 990         c->phys_proc_id = c->initial_apicid;
 991 #endif
 992         /* AMD-defined flags: level 0x80000001 */
 993         xlvl = cpuid_eax(0x80000000);
 994         c->extended_cpuid_level = xlvl;
 995         if ((xlvl & 0xffff0000) == 0x80000000) {
 996                 if (xlvl >= 0x80000001) {
 997                         c->x86_capability[1] = cpuid_edx(0x80000001);
 998                         c->x86_capability[6] = cpuid_ecx(0x80000001);
 999                 }
1000                 if (xlvl >= 0x80000004)
1001                         get_model_name(c); /* Default name */
1002         }
1003
1004         /* Transmeta-defined flags: level 0x80860001 */
1005         xlvl = cpuid_eax(0x80860000);
1006         if ((xlvl & 0xffff0000) == 0x80860000) {
1007                 /* Don't set x86_cpuid_level here for now to not confuse. */
1008                 if (xlvl >= 0x80860001)
1009                         c->x86_capability[2] = cpuid_edx(0x80860001);
1010         }
1011
1012         c->extended_cpuid_level = cpuid_eax(0x80000000);
1013         if (c->extended_cpuid_level >= 0x80000007)
1014                 c->x86_power = cpuid_edx(0x80000007);
1015
1016
1017         clear_cpu_cap(c, X86_FEATURE_PAT);
1018
1019         switch (c->x86_vendor) {
1020         case X86_VENDOR_AMD:
1021                 early_init_amd(c);
1022                 if (c->x86 >= 0xf && c->x86 <= 0x11)
1023                         set_cpu_cap(c, X86_FEATURE_PAT);
1024                 break;
1025         case X86_VENDOR_INTEL:
1026                 early_init_intel(c);
1027                 if (c->x86 == 0xF || (c->x86 == 6 && c->x86_model >= 15))
1028                         set_cpu_cap(c, X86_FEATURE_PAT);
1029                 break;
1030         case X86_VENDOR_CENTAUR:
1031                 early_init_centaur(c);
1032                 break;
1033         }
1034
1035 }
1036
1037 /*
1038  * This does the hard work of actually picking apart the CPU stuff...
1039  */
1040 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
1041 {
1042         int i;
1043
1044         early_identify_cpu(c);
1045
1046         init_scattered_cpuid_features(c);
1047
1048         c->apicid = phys_pkg_id(0);
1049
1050         /*
1051          * Vendor-specific initialization.  In this section we
1052          * canonicalize the feature flags, meaning if there are
1053          * features a certain CPU supports which CPUID doesn't
1054          * tell us, CPUID claiming incorrect flags, or other bugs,
1055          * we handle them here.
1056          *
1057          * At the end of this section, c->x86_capability better
1058          * indicate the features this CPU genuinely supports!
1059          */
1060         switch (c->x86_vendor) {
1061         case X86_VENDOR_AMD:
1062                 init_amd(c);
1063                 break;
1064
1065         case X86_VENDOR_INTEL:
1066                 init_intel(c);
1067                 break;
1068
1069         case X86_VENDOR_CENTAUR:
1070                 init_centaur(c);
1071                 break;
1072
1073         case X86_VENDOR_UNKNOWN:
1074         default:
1075                 display_cacheinfo(c);
1076                 break;
1077         }
1078
1079         detect_ht(c);
1080
1081         /*
1082          * On SMP, boot_cpu_data holds the common feature set between
1083          * all CPUs; so make sure that we indicate which features are
1084          * common between the CPUs.  The first time this routine gets
1085          * executed, c == &boot_cpu_data.
1086          */
1087         if (c != &boot_cpu_data) {
1088                 /* AND the already accumulated flags with these */
1089                 for (i = 0; i < NCAPINTS; i++)
1090                         boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1091         }
1092
1093         /* Clear all flags overriden by options */
1094         for (i = 0; i < NCAPINTS; i++)
1095                 c->x86_capability[i] &= ~cleared_cpu_caps[i];
1096
1097 #ifdef CONFIG_X86_MCE
1098         mcheck_init(c);
1099 #endif
1100         select_idle_routine(c);
1101
1102 #ifdef CONFIG_NUMA
1103         numa_add_cpu(smp_processor_id());
1104 #endif
1105
1106 }
1107
1108 void __cpuinit identify_boot_cpu(void)
1109 {
1110         identify_cpu(&boot_cpu_data);
1111 }
1112
1113 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
1114 {
1115         BUG_ON(c == &boot_cpu_data);
1116         identify_cpu(c);
1117         mtrr_ap_init();
1118 }
1119
1120 static __init int setup_noclflush(char *arg)
1121 {
1122         setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
1123         return 1;
1124 }
1125 __setup("noclflush", setup_noclflush);
1126
1127 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1128 {
1129         if (c->x86_model_id[0])
1130                 printk(KERN_CONT "%s", c->x86_model_id);
1131
1132         if (c->x86_mask || c->cpuid_level >= 0)
1133                 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1134         else
1135                 printk(KERN_CONT "\n");
1136 }
1137
1138 static __init int setup_disablecpuid(char *arg)
1139 {
1140         int bit;
1141         if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1142                 setup_clear_cpu_cap(bit);
1143         else
1144                 return 0;
1145         return 1;
1146 }
1147 __setup("clearcpuid=", setup_disablecpuid);