drivers/i2c/busses/i2c-piix4.c

   1 /*
   2     piix4.c - Part of lm_sensors, Linux kernel modules for hardware
   3               monitoring
   4     Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
   5     Philip Edelbrock <phil@netroedge.com>
   6
   7     This program is free software; you can redistribute it and/or modify
   8     it under the terms of the GNU General Public License as published by
   9     the Free Software Foundation; either version 2 of the License, or
  10     (at your option) any later version.
  11
  12     This program is distributed in the hope that it will be useful,
  13     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15     GNU General Public License for more details.
  16
  17     You should have received a copy of the GNU General Public License
  18     along with this program; if not, write to the Free Software
  19     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20 */
  21
  22 /*
  23    Supports:
  24         Intel PIIX4, 440MX
  25         Serverworks OSB4, CSB5, CSB6, HT-1000
  26         ATI IXP200, IXP300, IXP400, SB600
  27         SMSC Victory66
  28
  29    Note: we assume there can only be one device, with one SMBus interface.
  30 */
  31
  32 #include <linux/module.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/pci.h>
  35 #include <linux/kernel.h>
  36 #include <linux/delay.h>
  37 #include <linux/stddef.h>
  38 #include <linux/ioport.h>
  39 #include <linux/i2c.h>
  40 #include <linux/init.h>
  41 #include <linux/apm_bios.h>
  42 #include <linux/dmi.h>
  43 #include <asm/io.h>
  44
  45
  46 struct sd {
  47         const unsigned short mfr;
  48         const unsigned short dev;
  49         const unsigned char fn;
  50         const char *name;
  51 };
  52
  53 /* PIIX4 SMBus address offsets */
  54 #define SMBHSTSTS       (0 + piix4_smba)
  55 #define SMBHSLVSTS      (1 + piix4_smba)
  56 #define SMBHSTCNT       (2 + piix4_smba)
  57 #define SMBHSTCMD       (3 + piix4_smba)
  58 #define SMBHSTADD       (4 + piix4_smba)
  59 #define SMBHSTDAT0      (5 + piix4_smba)
  60 #define SMBHSTDAT1      (6 + piix4_smba)
  61 #define SMBBLKDAT       (7 + piix4_smba)
  62 #define SMBSLVCNT       (8 + piix4_smba)
  63 #define SMBSHDWCMD      (9 + piix4_smba)
  64 #define SMBSLVEVT       (0xA + piix4_smba)
  65 #define SMBSLVDAT       (0xC + piix4_smba)
  66
  67 /* count for request_region */
  68 #define SMBIOSIZE       8
  69
  70 /* PCI Address Constants */
  71 #define SMBBA           0x090
  72 #define SMBHSTCFG       0x0D2
  73 #define SMBSLVC         0x0D3
  74 #define SMBSHDW1        0x0D4
  75 #define SMBSHDW2        0x0D5
  76 #define SMBREV          0x0D6
  77
  78 /* Other settings */
  79 #define MAX_TIMEOUT     500
  80 #define  ENABLE_INT9    0
  81
  82 /* PIIX4 constants */
  83 #define PIIX4_QUICK             0x00
  84 #define PIIX4_BYTE              0x04
  85 #define PIIX4_BYTE_DATA         0x08
  86 #define PIIX4_WORD_DATA         0x0C
  87 #define PIIX4_BLOCK_DATA        0x14
  88
  89 /* insmod parameters */
  90
  91 /* If force is set to anything different from 0, we forcibly enable the
  92    PIIX4. DANGEROUS! */
  93 static int force;
  94 module_param (force, int, 0);
  95 MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!");
  96
  97 /* If force_addr is set to anything different from 0, we forcibly enable
  98    the PIIX4 at the given address. VERY DANGEROUS! */
  99 static int force_addr;
 100 module_param (force_addr, int, 0);
 101 MODULE_PARM_DESC(force_addr,
 102                  "Forcibly enable the PIIX4 at the given address. "
 103                  "EXTREMELY DANGEROUS!");
 104
 105 static int piix4_transaction(void);
 106
 107 static unsigned short piix4_smba;
 108 static struct pci_driver piix4_driver;
 109 static struct i2c_adapter piix4_adapter;
 110
 111 static struct dmi_system_id __devinitdata piix4_dmi_table[] = {
 112         {
 113                 .ident = "IBM",
 114                 .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), },
 115         },
 116         { },
 117 };
 118
 119 static int __devinit piix4_setup(struct pci_dev *PIIX4_dev,
 120                                 const struct pci_device_id *id)
 121 {
 122         unsigned char temp;
 123
 124         /* match up the function */
 125         if (PCI_FUNC(PIIX4_dev->devfn) != id->driver_data)
 126                 return -ENODEV;
 127
 128         dev_info(&PIIX4_dev->dev, "Found %s device\n", pci_name(PIIX4_dev));
 129
 130         /* Don't access SMBus on IBM systems which get corrupted eeproms */
 131         if (dmi_check_system(piix4_dmi_table) &&
 132                         PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) {
 133                 dev_err(&PIIX4_dev->dev, "IBM system detected; this module "
 134                         "may corrupt your serial eeprom! Refusing to load "
 135                         "module!\n");
 136                 return -EPERM;
 137         }
 138
 139         /* Determine the address of the SMBus areas */
 140         if (force_addr) {
 141                 piix4_smba = force_addr & 0xfff0;
 142                 force = 0;
 143         } else {
 144                 pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba);
 145                 piix4_smba &= 0xfff0;
 146                 if(piix4_smba == 0) {
 147                         dev_err(&PIIX4_dev->dev, "SMB base address "
 148                                 "uninitialized - upgrade BIOS or use "
 149                                 "force_addr=0xaddr\n");
 150                         return -ENODEV;
 151                 }
 152         }
 153
 154         if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
 155                 dev_err(&PIIX4_dev->dev, "SMB region 0x%x already in use!\n",
 156                         piix4_smba);
 157                 return -ENODEV;
 158         }
 159
 160         pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp);
 161
 162         /* If force_addr is set, we program the new address here. Just to make
 163            sure, we disable the PIIX4 first. */
 164         if (force_addr) {
 165                 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe);
 166                 pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba);
 167                 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01);
 168                 dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to "
 169                         "new address %04x!\n", piix4_smba);
 170         } else if ((temp & 1) == 0) {
 171                 if (force) {
 172                         /* This should never need to be done, but has been
 173                          * noted that many Dell machines have the SMBus
 174                          * interface on the PIIX4 disabled!? NOTE: This assumes
 175                          * I/O space and other allocations WERE done by the
 176                          * Bios!  Don't complain if your hardware does weird
 177                          * things after enabling this. :') Check for Bios
 178                          * updates before resorting to this.
 179                          */
 180                         pci_write_config_byte(PIIX4_dev, SMBHSTCFG,
 181                                               temp | 1);
 182                         dev_printk(KERN_NOTICE, &PIIX4_dev->dev,
 183                                 "WARNING: SMBus interface has been "
 184                                 "FORCEFULLY ENABLED!\n");
 185                 } else {
 186                         dev_err(&PIIX4_dev->dev,
 187                                 "Host SMBus controller not enabled!\n");
 188                         release_region(piix4_smba, SMBIOSIZE);
 189                         piix4_smba = 0;
 190                         return -ENODEV;
 191                 }
 192         }
 193
 194         if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2))
 195                 dev_dbg(&PIIX4_dev->dev, "Using Interrupt 9 for SMBus.\n");
 196         else if ((temp & 0x0E) == 0)
 197                 dev_dbg(&PIIX4_dev->dev, "Using Interrupt SMI# for SMBus.\n");
 198         else
 199                 dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration "
 200                         "(or code out of date)!\n");
 201
 202         pci_read_config_byte(PIIX4_dev, SMBREV, &temp);
 203         dev_dbg(&PIIX4_dev->dev, "SMBREV = 0x%X\n", temp);
 204         dev_dbg(&PIIX4_dev->dev, "SMBA = 0x%X\n", piix4_smba);
 205
 206         return 0;
 207 }
 208
 209 /* Another internally used function */
 210 static int piix4_transaction(void)
 211 {
 212         int temp;
 213         int result = 0;
 214         int timeout = 0;
 215
 216         dev_dbg(&piix4_adapter.dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
 217                 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
 218                 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
 219                 inb_p(SMBHSTDAT1));
 220
 221         /* Make sure the SMBus host is ready to start transmitting */
 222         if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
 223                 dev_dbg(&piix4_adapter.dev, "SMBus busy (%02x). "
 224                         "Resetting...\n", temp);
 225                 outb_p(temp, SMBHSTSTS);
 226                 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
 227                         dev_err(&piix4_adapter.dev, "Failed! (%02x)\n", temp);
 228                         return -1;
 229                 } else {
 230                         dev_dbg(&piix4_adapter.dev, "Successfull!\n");
 231                 }
 232         }
 233
 234         /* start the transaction by setting bit 6 */
 235         outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT);
 236
 237         /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */
 238         do {
 239                 msleep(1);
 240                 temp = inb_p(SMBHSTSTS);
 241         } while ((temp & 0x01) && (timeout++ < MAX_TIMEOUT));
 242
 243         /* If the SMBus is still busy, we give up */
 244         if (timeout >= MAX_TIMEOUT) {
 245                 dev_err(&piix4_adapter.dev, "SMBus Timeout!\n");
 246                 result = -1;
 247         }
 248
 249         if (temp & 0x10) {
 250                 result = -1;
 251                 dev_err(&piix4_adapter.dev, "Error: Failed bus transaction\n");
 252         }
 253
 254         if (temp & 0x08) {
 255                 result = -1;
 256                 dev_dbg(&piix4_adapter.dev, "Bus collision! SMBus may be "
 257                         "locked until next hard reset. (sorry!)\n");
 258                 /* Clock stops and slave is stuck in mid-transmission */
 259         }
 260
 261         if (temp & 0x04) {
 262                 result = -1;
 263                 dev_dbg(&piix4_adapter.dev, "Error: no response!\n");
 264         }
 265
 266         if (inb_p(SMBHSTSTS) != 0x00)
 267                 outb_p(inb(SMBHSTSTS), SMBHSTSTS);
 268
 269         if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
 270                 dev_err(&piix4_adapter.dev, "Failed reset at end of "
 271                         "transaction (%02x)\n", temp);
 272         }
 273         dev_dbg(&piix4_adapter.dev, "Transaction (post): CNT=%02x, CMD=%02x, "
 274                 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
 275                 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
 276                 inb_p(SMBHSTDAT1));
 277         return result;
 278 }
 279
 280 /* Return -1 on error. */
 281 static s32 piix4_access(struct i2c_adapter * adap, u16 addr,
 282                  unsigned short flags, char read_write,
 283                  u8 command, int size, union i2c_smbus_data * data)
 284 {
 285         int i, len;
 286
 287         switch (size) {
 288         case I2C_SMBUS_PROC_CALL:
 289                 dev_err(&adap->dev, "I2C_SMBUS_PROC_CALL not supported!\n");
 290                 return -1;
 291         case I2C_SMBUS_QUICK:
 292                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 293                        SMBHSTADD);
 294                 size = PIIX4_QUICK;
 295                 break;
 296         case I2C_SMBUS_BYTE:
 297                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 298                        SMBHSTADD);
 299                 if (read_write == I2C_SMBUS_WRITE)
 300                         outb_p(command, SMBHSTCMD);
 301                 size = PIIX4_BYTE;
 302                 break;
 303         case I2C_SMBUS_BYTE_DATA:
 304                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 305                        SMBHSTADD);
 306                 outb_p(command, SMBHSTCMD);
 307                 if (read_write == I2C_SMBUS_WRITE)
 308                         outb_p(data->byte, SMBHSTDAT0);
 309                 size = PIIX4_BYTE_DATA;
 310                 break;
 311         case I2C_SMBUS_WORD_DATA:
 312                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 313                        SMBHSTADD);
 314                 outb_p(command, SMBHSTCMD);
 315                 if (read_write == I2C_SMBUS_WRITE) {
 316                         outb_p(data->word & 0xff, SMBHSTDAT0);
 317                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
 318                 }
 319                 size = PIIX4_WORD_DATA;
 320                 break;
 321         case I2C_SMBUS_BLOCK_DATA:
 322                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 323                        SMBHSTADD);
 324                 outb_p(command, SMBHSTCMD);
 325                 if (read_write == I2C_SMBUS_WRITE) {
 326                         len = data->block[0];
 327                         if (len < 0)
 328                                 len = 0;
 329                         if (len > 32)
 330                                 len = 32;
 331                         outb_p(len, SMBHSTDAT0);
 332                         i = inb_p(SMBHSTCNT);   /* Reset SMBBLKDAT */
 333                         for (i = 1; i <= len; i++)
 334                                 outb_p(data->block[i], SMBBLKDAT);
 335                 }
 336                 size = PIIX4_BLOCK_DATA;
 337                 break;
 338         }
 339
 340         outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT);
 341
 342         if (piix4_transaction())        /* Error in transaction */
 343                 return -1;
 344
 345         if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK))
 346                 return 0;
 347
 348
 349         switch (size) {
 350         case PIIX4_BYTE:        /* Where is the result put? I assume here it is in
 351                                    SMBHSTDAT0 but it might just as well be in the
 352                                    SMBHSTCMD. No clue in the docs */
 353
 354                 data->byte = inb_p(SMBHSTDAT0);
 355                 break;
 356         case PIIX4_BYTE_DATA:
 357                 data->byte = inb_p(SMBHSTDAT0);
 358                 break;
 359         case PIIX4_WORD_DATA:
 360                 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
 361                 break;
 362         case PIIX4_BLOCK_DATA:
 363                 data->block[0] = inb_p(SMBHSTDAT0);
 364                 i = inb_p(SMBHSTCNT);   /* Reset SMBBLKDAT */
 365                 for (i = 1; i <= data->block[0]; i++)
 366                         data->block[i] = inb_p(SMBBLKDAT);
 367                 break;
 368         }
 369         return 0;
 370 }
 371
 372 static u32 piix4_func(struct i2c_adapter *adapter)
 373 {
 374         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 375             I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 376             I2C_FUNC_SMBUS_BLOCK_DATA;
 377 }
 378
 379 static const struct i2c_algorithm smbus_algorithm = {
 380         .smbus_xfer     = piix4_access,
 381         .functionality  = piix4_func,
 382 };
 383
 384 static struct i2c_adapter piix4_adapter = {
 385         .owner          = THIS_MODULE,
 386         .id             = I2C_HW_SMBUS_PIIX4,
 387         .class          = I2C_CLASS_HWMON,
 388         .algo           = &smbus_algorithm,
 389 };
 390
 391 static struct pci_device_id piix4_ids[] = {
 392         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3),
 393           .driver_data = 3 },
 394         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS),
 395           .driver_data = 0 },
 396         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS),
 397           .driver_data = 0 },
 398         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS),
 399           .driver_data = 0 },
 400         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SMBUS),
 401           .driver_data = 0 },
 402         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4),
 403           .driver_data = 0 },
 404         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5),
 405           .driver_data = 0 },
 406         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6),
 407           .driver_data = 0 },
 408         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB),
 409           .driver_data = 0 },
 410         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3),
 411           .driver_data = 3 },
 412         { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3),
 413           .driver_data = 0 },
 414         { 0, }
 415 };
 416
 417 MODULE_DEVICE_TABLE (pci, piix4_ids);
 418
 419 static int __devinit piix4_probe(struct pci_dev *dev,
 420                                 const struct pci_device_id *id)
 421 {
 422         int retval;
 423
 424         retval = piix4_setup(dev, id);
 425         if (retval)
 426                 return retval;
 427
 428         /* set up the sysfs linkage to our parent device */
 429         piix4_adapter.dev.parent = &dev->dev;
 430
 431         snprintf(piix4_adapter.name, sizeof(piix4_adapter.name),
 432                 "SMBus PIIX4 adapter at %04x", piix4_smba);
 433
 434         if ((retval = i2c_add_adapter(&piix4_adapter))) {
 435                 dev_err(&dev->dev, "Couldn't register adapter!\n");
 436                 release_region(piix4_smba, SMBIOSIZE);
 437                 piix4_smba = 0;
 438         }
 439
 440         return retval;
 441 }
 442
 443 static void __devexit piix4_remove(struct pci_dev *dev)
 444 {
 445         if (piix4_smba) {
 446                 i2c_del_adapter(&piix4_adapter);
 447                 release_region(piix4_smba, SMBIOSIZE);
 448                 piix4_smba = 0;
 449         }
 450 }
 451
 452 static struct pci_driver piix4_driver = {
 453         .name           = "piix4_smbus",
 454         .id_table       = piix4_ids,
 455         .probe          = piix4_probe,
 456         .remove         = __devexit_p(piix4_remove),
 457 };
 458
 459 static int __init i2c_piix4_init(void)
 460 {
 461         return pci_register_driver(&piix4_driver);
 462 }
 463
 464 static void __exit i2c_piix4_exit(void)
 465 {
 466         pci_unregister_driver(&piix4_driver);
 467 }
 468
 469 MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and "
 470                 "Philip Edelbrock <phil@netroedge.com>");
 471 MODULE_DESCRIPTION("PIIX4 SMBus driver");
 472 MODULE_LICENSE("GPL");
 473
 474 module_init(i2c_piix4_init);
 475 module_exit(i2c_piix4_exit);