?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
tridentfb: fix console freeze when switching from X11
[firewire-audio.git] / drivers / video / tridentfb.c
blobda4b464cbdba45fed1481488218d4e1d27187408
1 /*
2 * Frame buffer driver for Trident TGUI, Blade and Image series
3 *
4 * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro>
5 *
6 *
7 * CREDITS:(in order of appearance)
8 * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
9 * Special thanks ;) to Mattia Crivellini <tia@mclink.it>
10 * much inspired by the XFree86 4.x Trident driver sources
11 * by Alan Hourihane the FreeVGA project
12 * Francesco Salvestrini <salvestrini@users.sf.net> XP support,
13 * code, suggestions
14 * TODO:
15 * timing value tweaking so it looks good on every monitor in every mode
16 */
17
18 #include <linux/module.h>
19 #include <linux/fb.h>
20 #include <linux/init.h>
21 #include <linux/pci.h>
22
23 #include <linux/delay.h>
24 #include <video/vga.h>
25 #include <video/trident.h>
26
27 struct tridentfb_par {
28 void __iomem *io_virt; /* iospace virtual memory address */
29 u32 pseudo_pal[16];
30 int chip_id;
31 int flatpanel;
32 void (*init_accel) (struct tridentfb_par *, int, int);
33 void (*wait_engine) (struct tridentfb_par *);
34 void (*fill_rect)
35 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
36 void (*copy_rect)
37 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
38 unsigned char eng_oper; /* engine operation... */
39 };
40
41 static struct fb_ops tridentfb_ops;
42
43 static struct fb_fix_screeninfo tridentfb_fix = {
44 .id = "Trident",
45 .type = FB_TYPE_PACKED_PIXELS,
46 .ypanstep = 1,
47 .visual = FB_VISUAL_PSEUDOCOLOR,
48 .accel = FB_ACCEL_NONE,
49 };
50
51 /* defaults which are normally overriden by user values */
52
53 /* video mode */
54 static char *mode_option __devinitdata = "640x480-8@60";
55 static int bpp __devinitdata = 8;
56
57 static int noaccel __devinitdata;
58
59 static int center;
60 static int stretch;
61
62 static int fp __devinitdata;
63 static int crt __devinitdata;
64
65 static int memsize __devinitdata;
66 static int memdiff __devinitdata;
67 static int nativex;
68
69 module_param(mode_option, charp, 0);
70 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
71 module_param_named(mode, mode_option, charp, 0);
72 MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
73 module_param(bpp, int, 0);
74 module_param(center, int, 0);
75 module_param(stretch, int, 0);
76 module_param(noaccel, int, 0);
77 module_param(memsize, int, 0);
78 module_param(memdiff, int, 0);
79 module_param(nativex, int, 0);
80 module_param(fp, int, 0);
81 MODULE_PARM_DESC(fp, "Define if flatpanel is connected");
82 module_param(crt, int, 0);
83 MODULE_PARM_DESC(crt, "Define if CRT is connected");
84
85 static inline int is_oldclock(int id)
86 {
87 return (id == TGUI9440) ||
88 (id == TGUI9660) ||
89 (id == CYBER9320);
90 }
91
92 static inline int is_oldprotect(int id)
93 {
94 return is_oldclock(id) ||
95 (id == PROVIDIA9685) ||
96 (id == CYBER9382) ||
97 (id == CYBER9385);
98 }
99
100 static inline int is_blade(int id)
101 {
102 return (id == BLADE3D) ||
103 (id == CYBERBLADEE4) ||
104 (id == CYBERBLADEi7) ||
105 (id == CYBERBLADEi7D) ||
106 (id == CYBERBLADEi1) ||
107 (id == CYBERBLADEi1D) ||
108 (id == CYBERBLADEAi1) ||
109 (id == CYBERBLADEAi1D);
110 }
111
112 static inline int is_xp(int id)
113 {
114 return (id == CYBERBLADEXPAi1) ||
115 (id == CYBERBLADEXPm8) ||
116 (id == CYBERBLADEXPm16);
117 }
118
119 static inline int is3Dchip(int id)
120 {
121 return is_blade(id) || is_xp(id) ||
122 (id == CYBER9397) || (id == CYBER9397DVD) ||
123 (id == CYBER9520) || (id == CYBER9525DVD) ||
124 (id == IMAGE975) || (id == IMAGE985);
125 }
126
127 static inline int iscyber(int id)
128 {
129 switch (id) {
130 case CYBER9388:
131 case CYBER9382:
132 case CYBER9385:
133 case CYBER9397:
134 case CYBER9397DVD:
135 case CYBER9520:
136 case CYBER9525DVD:
137 case CYBERBLADEE4:
138 case CYBERBLADEi7D:
139 case CYBERBLADEi1:
140 case CYBERBLADEi1D:
141 case CYBERBLADEAi1:
142 case CYBERBLADEAi1D:
143 case CYBERBLADEXPAi1:
144 return 1;
145
146 case CYBER9320:
147 case CYBERBLADEi7: /* VIA MPV4 integrated version */
148 default:
149 /* case CYBERBLDAEXPm8: Strange */
150 /* case CYBERBLDAEXPm16: Strange */
151 return 0;
152 }
153 }
154
155 static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
156 {
157 fb_writeb(val, p->io_virt + reg);
158 }
159
160 static inline u8 t_inb(struct tridentfb_par *p, u16 reg)
161 {
162 return fb_readb(p->io_virt + reg);
163 }
164
165 static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
166 {
167 fb_writel(v, par->io_virt + r);
168 }
169
170 static inline u32 readmmr(struct tridentfb_par *par, u16 r)
171 {
172 return fb_readl(par->io_virt + r);
173 }
174
175 /*
176 * Blade specific acceleration.
177 */
178
179 #define point(x, y) ((y) << 16 | (x))
180
181 static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp)
182 {
183 int v1 = (pitch >> 3) << 20;
184 int tmp = bpp == 24 ? 2 : (bpp >> 4);
185 int v2 = v1 | (tmp << 29);
186
187 writemmr(par, 0x21C0, v2);
188 writemmr(par, 0x21C4, v2);
189 writemmr(par, 0x21B8, v2);
190 writemmr(par, 0x21BC, v2);
191 writemmr(par, 0x21D0, v1);
192 writemmr(par, 0x21D4, v1);
193 writemmr(par, 0x21C8, v1);
194 writemmr(par, 0x21CC, v1);
195 writemmr(par, 0x216C, 0);
196 }
197
198 static void blade_wait_engine(struct tridentfb_par *par)
199 {
200 while (readmmr(par, STATUS) & 0xFA800000)
201 cpu_relax();
202 }
203
204 static void blade_fill_rect(struct tridentfb_par *par,
205 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
206 {
207 writemmr(par, COLOR, c);
208 writemmr(par, ROP, rop ? ROP_X : ROP_S);
209 writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
210
211 writemmr(par, DST1, point(x, y));
212 writemmr(par, DST2, point(x + w - 1, y + h - 1));
213 }
214
215 static void blade_copy_rect(struct tridentfb_par *par,
216 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
217 {
218 int direction = 2;
219 u32 s1 = point(x1, y1);
220 u32 s2 = point(x1 + w - 1, y1 + h - 1);
221 u32 d1 = point(x2, y2);
222 u32 d2 = point(x2 + w - 1, y2 + h - 1);
223
224 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
225 direction = 0;
226
227 writemmr(par, ROP, ROP_S);
228 writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
229
230 writemmr(par, SRC1, direction ? s2 : s1);
231 writemmr(par, SRC2, direction ? s1 : s2);
232 writemmr(par, DST1, direction ? d2 : d1);
233 writemmr(par, DST2, direction ? d1 : d2);
234 }
235
236 /*
237 * BladeXP specific acceleration functions
238 */
239
240 static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp)
241 {
242 unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
243 int v1 = pitch << (bpp == 24 ? 20 : (18 + x));
244
245 switch (pitch << (bpp >> 3)) {
246 case 8192:
247 case 512:
248 x |= 0x00;
249 break;
250 case 1024:
251 x |= 0x04;
252 break;
253 case 2048:
254 x |= 0x08;
255 break;
256 case 4096:
257 x |= 0x0C;
258 break;
259 }
260
261 t_outb(par, x, 0x2125);
262
263 par->eng_oper = x | 0x40;
264
265 writemmr(par, 0x2154, v1);
266 writemmr(par, 0x2150, v1);
267 t_outb(par, 3, 0x2126);
268 }
269
270 static void xp_wait_engine(struct tridentfb_par *par)
271 {
272 int count = 0;
273 int timeout = 0;
274
275 while (t_inb(par, STATUS) & 0x80) {
276 count++;
277 if (count == 10000000) {
278 /* Timeout */
279 count = 9990000;
280 timeout++;
281 if (timeout == 8) {
282 /* Reset engine */
283 t_outb(par, 0x00, STATUS);
284 return;
285 }
286 }
287 cpu_relax();
288 }
289 }
290
291 static void xp_fill_rect(struct tridentfb_par *par,
292 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
293 {
294 writemmr(par, 0x2127, ROP_P);
295 writemmr(par, 0x2158, c);
296 writemmr(par, DRAWFL, 0x4000);
297 writemmr(par, OLDDIM, point(h, w));
298 writemmr(par, OLDDST, point(y, x));
299 t_outb(par, 0x01, OLDCMD);
300 t_outb(par, par->eng_oper, 0x2125);
301 }
302
303 static void xp_copy_rect(struct tridentfb_par *par,
304 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
305 {
306 u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
307 int direction = 0x0004;
308
309 if ((x1 < x2) && (y1 == y2)) {
310 direction |= 0x0200;
311 x1_tmp = x1 + w - 1;
312 x2_tmp = x2 + w - 1;
313 } else {
314 x1_tmp = x1;
315 x2_tmp = x2;
316 }
317
318 if (y1 < y2) {
319 direction |= 0x0100;
320 y1_tmp = y1 + h - 1;
321 y2_tmp = y2 + h - 1;
322 } else {
323 y1_tmp = y1;
324 y2_tmp = y2;
325 }
326
327 writemmr(par, DRAWFL, direction);
328 t_outb(par, ROP_S, 0x2127);
329 writemmr(par, OLDSRC, point(y1_tmp, x1_tmp));
330 writemmr(par, OLDDST, point(y2_tmp, x2_tmp));
331 writemmr(par, OLDDIM, point(h, w));
332 t_outb(par, 0x01, OLDCMD);
333 }
334
335 /*
336 * Image specific acceleration functions
337 */
338 static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp)
339 {
340 int tmp = bpp == 24 ? 2: (bpp >> 4);
341
342 writemmr(par, 0x2120, 0xF0000000);
343 writemmr(par, 0x2120, 0x40000000 | tmp);
344 writemmr(par, 0x2120, 0x80000000);
345 writemmr(par, 0x2144, 0x00000000);
346 writemmr(par, 0x2148, 0x00000000);
347 writemmr(par, 0x2150, 0x00000000);
348 writemmr(par, 0x2154, 0x00000000);
349 writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch);
350 writemmr(par, 0x216C, 0x00000000);
351 writemmr(par, 0x2170, 0x00000000);
352 writemmr(par, 0x217C, 0x00000000);
353 writemmr(par, 0x2120, 0x10000000);
354 writemmr(par, 0x2130, (2047 << 16) | 2047);
355 }
356
357 static void image_wait_engine(struct tridentfb_par *par)
358 {
359 while (readmmr(par, 0x2164) & 0xF0000000)
360 cpu_relax();
361 }
362
363 static void image_fill_rect(struct tridentfb_par *par,
364 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
365 {
366 writemmr(par, 0x2120, 0x80000000);
367 writemmr(par, 0x2120, 0x90000000 | ROP_S);
368
369 writemmr(par, 0x2144, c);
370
371 writemmr(par, DST1, point(x, y));
372 writemmr(par, DST2, point(x + w - 1, y + h - 1));
373
374 writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
375 }
376
377 static void image_copy_rect(struct tridentfb_par *par,
378 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
379 {
380 int direction = 0x4;
381 u32 s1 = point(x1, y1);
382 u32 s2 = point(x1 + w - 1, y1 + h - 1);
383 u32 d1 = point(x2, y2);
384 u32 d2 = point(x2 + w - 1, y2 + h - 1);
385
386 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
387 direction = 0;
388
389 writemmr(par, 0x2120, 0x80000000);
390 writemmr(par, 0x2120, 0x90000000 | ROP_S);
391
392 writemmr(par, SRC1, direction ? s2 : s1);
393 writemmr(par, SRC2, direction ? s1 : s2);
394 writemmr(par, DST1, direction ? d2 : d1);
395 writemmr(par, DST2, direction ? d1 : d2);
396 writemmr(par, 0x2124,
397 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
398 }
399
400 /*
401 * TGUI 9440/96XX acceleration
402 */
403
404 static void tgui_init_accel(struct tridentfb_par *par, int pitch, int bpp)
405 {
406 unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
407
408 /* disable clipping */
409 writemmr(par, 0x2148, 0);
410 writemmr(par, 0x214C, point(4095, 2047));
411
412 switch ((pitch * bpp) / 8) {
413 case 8192:
414 case 512:
415 x |= 0x00;
416 break;
417 case 1024:
418 x |= 0x04;
419 break;
420 case 2048:
421 x |= 0x08;
422 break;
423 case 4096:
424 x |= 0x0C;
425 break;
426 }
427
428 fb_writew(x, par->io_virt + 0x2122);
429 }
430
431 static void tgui_fill_rect(struct tridentfb_par *par,
432 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
433 {
434 t_outb(par, ROP_P, 0x2127);
435 writemmr(par, OLDCLR, c);
436 writemmr(par, DRAWFL, 0x4020);
437 writemmr(par, OLDDIM, point(w - 1, h - 1));
438 writemmr(par, OLDDST, point(x, y));
439 t_outb(par, 1, OLDCMD);
440 }
441
442 static void tgui_copy_rect(struct tridentfb_par *par,
443 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
444 {
445 int flags = 0;
446 u16 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
447
448 if ((x1 < x2) && (y1 == y2)) {
449 flags |= 0x0200;
450 x1_tmp = x1 + w - 1;
451 x2_tmp = x2 + w - 1;
452 } else {
453 x1_tmp = x1;
454 x2_tmp = x2;
455 }
456
457 if (y1 < y2) {
458 flags |= 0x0100;
459 y1_tmp = y1 + h - 1;
460 y2_tmp = y2 + h - 1;
461 } else {
462 y1_tmp = y1;
463 y2_tmp = y2;
464 }
465
466 writemmr(par, DRAWFL, 0x4 | flags);
467 t_outb(par, ROP_S, 0x2127);
468 writemmr(par, OLDSRC, point(x1_tmp, y1_tmp));
469 writemmr(par, OLDDST, point(x2_tmp, y2_tmp));
470 writemmr(par, OLDDIM, point(w - 1, h - 1));
471 t_outb(par, 1, OLDCMD);
472 }
473
474 /*
475 * Accel functions called by the upper layers
476 */
477 #ifdef CONFIG_FB_TRIDENT_ACCEL
478 static void tridentfb_fillrect(struct fb_info *info,
479 const struct fb_fillrect *fr)
480 {
481 struct tridentfb_par *par = info->par;
482 int col;
483
484 if (info->flags & FBINFO_HWACCEL_DISABLED) {
485 cfb_fillrect(info, fr);
486 return;
487 }
488 if (info->var.bits_per_pixel == 8) {
489 col = fr->color;
490 col |= col << 8;
491 col |= col << 16;
492 } else
493 col = ((u32 *)(info->pseudo_palette))[fr->color];
494
495 par->wait_engine(par);
496 par->fill_rect(par, fr->dx, fr->dy, fr->width,
497 fr->height, col, fr->rop);
498 }
499
500 static void tridentfb_copyarea(struct fb_info *info,
501 const struct fb_copyarea *ca)
502 {
503 struct tridentfb_par *par = info->par;
504
505 if (info->flags & FBINFO_HWACCEL_DISABLED) {
506 cfb_copyarea(info, ca);
507 return;
508 }
509 par->wait_engine(par);
510 par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy,
511 ca->width, ca->height);
512 }
513
514 static int tridentfb_sync(struct fb_info *info)
515 {
516 struct tridentfb_par *par = info->par;
517
518 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
519 par->wait_engine(par);
520 return 0;
521 }
522 #else
523 #define tridentfb_fillrect cfb_fillrect
524 #define tridentfb_copyarea cfb_copyarea
525 #endif /* CONFIG_FB_TRIDENT_ACCEL */
526
527 /*
528 * Hardware access functions
529 */
530
531 static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
532 {
533 return vga_mm_rcrt(par->io_virt, reg);
534 }
535
536 static inline void write3X4(struct tridentfb_par *par, int reg,
537 unsigned char val)
538 {
539 vga_mm_wcrt(par->io_virt, reg, val);
540 }
541
542 static inline unsigned char read3CE(struct tridentfb_par *par,
543 unsigned char reg)
544 {
545 return vga_mm_rgfx(par->io_virt, reg);
546 }
547
548 static inline void writeAttr(struct tridentfb_par *par, int reg,
549 unsigned char val)
550 {
551 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
552 vga_mm_wattr(par->io_virt, reg, val);
553 }
554
555 static inline void write3CE(struct tridentfb_par *par, int reg,
556 unsigned char val)
557 {
558 vga_mm_wgfx(par->io_virt, reg, val);
559 }
560
561 static void enable_mmio(struct tridentfb_par *par)
562 {
563 /* Goto New Mode */
564 vga_io_rseq(0x0B);
565
566 /* Unprotect registers */
567 vga_io_wseq(NewMode1, 0x80);
568 if (!is_oldprotect(par->chip_id))
569 vga_io_wseq(Protection, 0x92);
570
571 /* Enable MMIO */
572 outb(PCIReg, 0x3D4);
573 outb(inb(0x3D5) | 0x01, 0x3D5);
574 }
575
576 static void disable_mmio(struct tridentfb_par *par)
577 {
578 /* Goto New Mode */
579 vga_mm_rseq(par->io_virt, 0x0B);
580
581 /* Unprotect registers */
582 vga_mm_wseq(par->io_virt, NewMode1, 0x80);
583 if (!is_oldprotect(par->chip_id))
584 vga_mm_wseq(par->io_virt, Protection, 0x92);
585
586 /* Disable MMIO */
587 t_outb(par, PCIReg, 0x3D4);
588 t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);
589 }
590
591 static inline void crtc_unlock(struct tridentfb_par *par)
592 {
593 write3X4(par, VGA_CRTC_V_SYNC_END,
594 read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F);
595 }
596
597 /* Return flat panel's maximum x resolution */
598 static int __devinit get_nativex(struct tridentfb_par *par)
599 {
600 int x, y, tmp;
601
602 if (nativex)
603 return nativex;
604
605 tmp = (read3CE(par, VertStretch) >> 4) & 3;
606
607 switch (tmp) {
608 case 0:
609 x = 1280; y = 1024;
610 break;
611 case 2:
612 x = 1024; y = 768;
613 break;
614 case 3:
615 x = 800; y = 600;
616 break;
617 case 4:
618 x = 1400; y = 1050;
619 break;
620 case 1:
621 default:
622 x = 640; y = 480;
623 break;
624 }
625
626 output("%dx%d flat panel found\n", x, y);
627 return x;
628 }
629
630 /* Set pitch */
631 static inline void set_lwidth(struct tridentfb_par *par, int width)
632 {
633 write3X4(par, VGA_CRTC_OFFSET, width & 0xFF);
634 write3X4(par, AddColReg,
635 (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
636 }
637
638 /* For resolutions smaller than FP resolution stretch */
639 static void screen_stretch(struct tridentfb_par *par)
640 {
641 if (par->chip_id != CYBERBLADEXPAi1)
642 write3CE(par, BiosReg, 0);
643 else
644 write3CE(par, BiosReg, 8);
645 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1);
646 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1);
647 }
648
649 /* For resolutions smaller than FP resolution center */
650 static inline void screen_center(struct tridentfb_par *par)
651 {
652 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80);
653 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80);
654 }
655
656 /* Address of first shown pixel in display memory */
657 static void set_screen_start(struct tridentfb_par *par, int base)
658 {
659 u8 tmp;
660 write3X4(par, VGA_CRTC_START_LO, base & 0xFF);
661 write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8);
662 tmp = read3X4(par, CRTCModuleTest) & 0xDF;
663 write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
664 tmp = read3X4(par, CRTHiOrd) & 0xF8;
665 write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));
666 }
667
668 /* Set dotclock frequency */
669 static void set_vclk(struct tridentfb_par *par, unsigned long freq)
670 {
671 int m, n, k;
672 unsigned long fi, d, di;
673 unsigned char best_m = 0, best_n = 0, best_k = 0;
674 unsigned char hi, lo;
675
676 d = 20000;
677 for (k = 1; k >= 0; k--)
678 for (m = 0; m < 32; m++) {
679 n = 2 * (m + 2) - 8;
680 for (n = (n < 0 ? 0 : n); n < 122; n++) {
681 fi = ((14318l * (n + 8)) / (m + 2)) >> k;
682 di = abs(fi - freq);
683 if (di <= d) {
684 d = di;
685 best_n = n;
686 best_m = m;
687 best_k = k;
688 }
689 if (fi > freq)
690 break;
691 }
692 }
693
694 if (is_oldclock(par->chip_id)) {
695 lo = best_n | (best_m << 7);
696 hi = (best_m >> 1) | (best_k << 4);
697 } else {
698 lo = best_n;
699 hi = best_m | (best_k << 6);
700 }
701
702 if (is3Dchip(par->chip_id)) {
703 vga_mm_wseq(par->io_virt, ClockHigh, hi);
704 vga_mm_wseq(par->io_virt, ClockLow, lo);
705 } else {
706 t_outb(par, lo, 0x43C8);
707 t_outb(par, hi, 0x43C9);
708 }
709 debug("VCLK = %X %X\n", hi, lo);
710 }
711
712 /* Set number of lines for flat panels*/
713 static void set_number_of_lines(struct tridentfb_par *par, int lines)
714 {
715 int tmp = read3CE(par, CyberEnhance) & 0x8F;
716 if (lines > 1024)
717 tmp |= 0x50;
718 else if (lines > 768)
719 tmp |= 0x30;
720 else if (lines > 600)
721 tmp |= 0x20;
722 else if (lines > 480)
723 tmp |= 0x10;
724 write3CE(par, CyberEnhance, tmp);
725 }
726
727 /*
728 * If we see that FP is active we assume we have one.
729 * Otherwise we have a CRT display. User can override.
730 */
731 static int __devinit is_flatpanel(struct tridentfb_par *par)
732 {
733 if (fp)
734 return 1;
735 if (crt || !iscyber(par->chip_id))
736 return 0;
737 return (read3CE(par, FPConfig) & 0x10) ? 1 : 0;
738 }
739
740 /* Try detecting the video memory size */
741 static unsigned int __devinit get_memsize(struct tridentfb_par *par)
742 {
743 unsigned char tmp, tmp2;
744 unsigned int k;
745
746 /* If memory size provided by user */
747 if (memsize)
748 k = memsize * Kb;
749 else
750 switch (par->chip_id) {
751 case CYBER9525DVD:
752 k = 2560 * Kb;
753 break;
754 default:
755 tmp = read3X4(par, SPR) & 0x0F;
756 switch (tmp) {
757
758 case 0x01:
759 k = 512 * Kb;
760 break;
761 case 0x02:
762 k = 6 * Mb; /* XP */
763 break;
764 case 0x03:
765 k = 1 * Mb;
766 break;
767 case 0x04:
768 k = 8 * Mb;
769 break;
770 case 0x06:
771 k = 10 * Mb; /* XP */
772 break;
773 case 0x07:
774 k = 2 * Mb;
775 break;
776 case 0x08:
777 k = 12 * Mb; /* XP */
778 break;
779 case 0x0A:
780 k = 14 * Mb; /* XP */
781 break;
782 case 0x0C:
783 k = 16 * Mb; /* XP */
784 break;
785 case 0x0E: /* XP */
786
787 tmp2 = vga_mm_rseq(par->io_virt, 0xC1);
788 switch (tmp2) {
789 case 0x00:
790 k = 20 * Mb;
791 break;
792 case 0x01:
793 k = 24 * Mb;
794 break;
795 case 0x10:
796 k = 28 * Mb;
797 break;
798 case 0x11:
799 k = 32 * Mb;
800 break;
801 default:
802 k = 1 * Mb;
803 break;
804 }
805 break;
806
807 case 0x0F:
808 k = 4 * Mb;
809 break;
810 default:
811 k = 1 * Mb;
812 break;
813 }
814 }
815
816 k -= memdiff * Kb;
817 output("framebuffer size = %d Kb\n", k / Kb);
818 return k;
819 }
820
821 /* See if we can handle the video mode described in var */
822 static int tridentfb_check_var(struct fb_var_screeninfo *var,
823 struct fb_info *info)
824 {
825 struct tridentfb_par *par = info->par;
826 int bpp = var->bits_per_pixel;
827 int line_length;
828 int ramdac = 230000; /* 230MHz for most 3D chips */
829 debug("enter\n");
830
831 /* check color depth */
832 if (bpp == 24)
833 bpp = var->bits_per_pixel = 32;
834 if (bpp != 8 && bpp != 16 && bpp != 32)
835 return -EINVAL;
836 if (par->chip_id == TGUI9440 && bpp == 32)
837 return -EINVAL;
838 /* check whether resolution fits on panel and in memory */
839 if (par->flatpanel && nativex && var->xres > nativex)
840 return -EINVAL;
841 /* various resolution checks */
842 var->xres = (var->xres + 7) & ~0x7;
843 if (var->xres > var->xres_virtual)
844 var->xres_virtual = var->xres;
845 if (var->yres > var->yres_virtual)
846 var->yres_virtual = var->yres;
847 if (var->xres_virtual > 4095 || var->yres > 2048)
848 return -EINVAL;
849 /* prevent from position overflow for acceleration */
850 if (var->yres_virtual > 0xffff)
851 return -EINVAL;
852 line_length = var->xres_virtual * bpp / 8;
853
854 if (!is3Dchip(par->chip_id) &&
855 !(info->flags & FBINFO_HWACCEL_DISABLED)) {
856 /* acceleration requires line length to be power of 2 */
857 if (line_length <= 512)
858 var->xres_virtual = 512 * 8 / bpp;
859 else if (line_length <= 1024)
860 var->xres_virtual = 1024 * 8 / bpp;
861 else if (line_length <= 2048)
862 var->xres_virtual = 2048 * 8 / bpp;
863 else if (line_length <= 4096)
864 var->xres_virtual = 4096 * 8 / bpp;
865 else if (line_length <= 8192)
866 var->xres_virtual = 8192 * 8 / bpp;
867 else
868 return -EINVAL;
869
870 line_length = var->xres_virtual * bpp / 8;
871 }
872
873 if (var->yres > var->yres_virtual)
874 var->yres_virtual = var->yres;
875 if (line_length * var->yres_virtual > info->fix.smem_len)
876 return -EINVAL;
877
878 switch (bpp) {
879 case 8:
880 var->red.offset = 0;
881 var->green.offset = 0;
882 var->blue.offset = 0;
883 var->red.length = 6;
884 var->green.length = 6;
885 var->blue.length = 6;
886 break;
887 case 16:
888 var->red.offset = 11;
889 var->green.offset = 5;
890 var->blue.offset = 0;
891 var->red.length = 5;
892 var->green.length = 6;
893 var->blue.length = 5;
894 break;
895 case 32:
896 var->red.offset = 16;
897 var->green.offset = 8;
898 var->blue.offset = 0;
899 var->red.length = 8;
900 var->green.length = 8;
901 var->blue.length = 8;
902 break;
903 default:
904 return -EINVAL;
905 }
906
907 if (is_xp(par->chip_id))
908 ramdac = 350000;
909
910 switch (par->chip_id) {
911 case TGUI9440:
912 ramdac = (bpp >= 16) ? 45000 : 90000;
913 break;
914 case CYBER9320:
915 case TGUI9660:
916 ramdac = 135000;
917 break;
918 case PROVIDIA9685:
919 case CYBER9388:
920 case CYBER9382:
921 case CYBER9385:
922 ramdac = 170000;
923 break;
924 }
925
926 /* The clock is doubled for 32 bpp */
927 if (bpp == 32)
928 ramdac /= 2;
929
930 if (PICOS2KHZ(var->pixclock) > ramdac)
931 return -EINVAL;
932
933 debug("exit\n");
934
935 return 0;
936
937 }
938
939 /* Pan the display */
940 static int tridentfb_pan_display(struct fb_var_screeninfo *var,
941 struct fb_info *info)
942 {
943 struct tridentfb_par *par = info->par;
944 unsigned int offset;
945
946 debug("enter\n");
947 offset = (var->xoffset + (var->yoffset * var->xres_virtual))
948 * var->bits_per_pixel / 32;
949 info->var.xoffset = var->xoffset;
950 info->var.yoffset = var->yoffset;
951 set_screen_start(par, offset);
952 debug("exit\n");
953 return 0;
954 }
955
956 static inline void shadowmode_on(struct tridentfb_par *par)
957 {
958 write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81);
959 }
960
961 static inline void shadowmode_off(struct tridentfb_par *par)
962 {
963 write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E);
964 }
965
966 /* Set the hardware to the requested video mode */
967 static int tridentfb_set_par(struct fb_info *info)
968 {
969 struct tridentfb_par *par = info->par;
970 u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
971 u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
972 struct fb_var_screeninfo *var = &info->var;
973 int bpp = var->bits_per_pixel;
974 unsigned char tmp;
975 unsigned long vclk;
976
977 debug("enter\n");
978 hdispend = var->xres / 8 - 1;
979 hsyncstart = (var->xres + var->right_margin) / 8;
980 hsyncend = (var->xres + var->right_margin + var->hsync_len) / 8;
981 htotal = (var->xres + var->left_margin + var->right_margin +
982 var->hsync_len) / 8 - 5;
983 hblankstart = hdispend + 1;
984 hblankend = htotal + 3;
985
986 vdispend = var->yres - 1;
987 vsyncstart = var->yres + var->lower_margin;
988 vsyncend = vsyncstart + var->vsync_len;
989 vtotal = var->upper_margin + vsyncend - 2;
990 vblankstart = vdispend + 1;
991 vblankend = vtotal;
992
993 if (info->var.vmode & FB_VMODE_INTERLACED) {
994 vtotal /= 2;
995 vdispend /= 2;
996 vsyncstart /= 2;
997 vsyncend /= 2;
998 vblankstart /= 2;
999 vblankend /= 2;
1000 }
1001
1002 enable_mmio(par);
1003 crtc_unlock(par);
1004 write3CE(par, CyberControl, 8);
1005 tmp = 0xEB;
1006 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
1007 tmp &= ~0x40;
1008 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
1009 tmp &= ~0x80;
1010
1011 if (par->flatpanel && var->xres < nativex) {
1012 /*
1013 * on flat panels with native size larger
1014 * than requested resolution decide whether
1015 * we stretch or center
1016 */
1017 t_outb(par, tmp | 0xC0, VGA_MIS_W);
1018
1019 shadowmode_on(par);
1020
1021 if (center)
1022 screen_center(par);
1023 else if (stretch)
1024 screen_stretch(par);
1025
1026 } else {
1027 t_outb(par, tmp, VGA_MIS_W);
1028 write3CE(par, CyberControl, 8);
1029 }
1030
1031 /* vertical timing values */
1032 write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF);
1033 write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF);
1034 write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF);
1035 write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F));
1036 write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF);
1037 write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF);
1038
1039 /* horizontal timing values */
1040 write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF);
1041 write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF);
1042 write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF);
1043 write3X4(par, VGA_CRTC_H_SYNC_END,
1044 (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
1045 write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF);
1046 write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F);
1047
1048 /* higher bits of vertical timing values */
1049 tmp = 0x10;
1050 if (vtotal & 0x100) tmp |= 0x01;
1051 if (vdispend & 0x100) tmp |= 0x02;
1052 if (vsyncstart & 0x100) tmp |= 0x04;
1053 if (vblankstart & 0x100) tmp |= 0x08;
1054
1055 if (vtotal & 0x200) tmp |= 0x20;
1056 if (vdispend & 0x200) tmp |= 0x40;
1057 if (vsyncstart & 0x200) tmp |= 0x80;
1058 write3X4(par, VGA_CRTC_OVERFLOW, tmp);
1059
1060 tmp = read3X4(par, CRTHiOrd) & 0x07;
1061 tmp |= 0x08; /* line compare bit 10 */
1062 if (vtotal & 0x400) tmp |= 0x80;
1063 if (vblankstart & 0x400) tmp |= 0x40;
1064 if (vsyncstart & 0x400) tmp |= 0x20;
1065 if (vdispend & 0x400) tmp |= 0x10;
1066 write3X4(par, CRTHiOrd, tmp);
1067
1068 tmp = (htotal >> 8) & 0x01;
1069 tmp |= (hdispend >> 7) & 0x02;
1070 tmp |= (hsyncstart >> 5) & 0x08;
1071 tmp |= (hblankstart >> 4) & 0x10;
1072 write3X4(par, HorizOverflow, tmp);
1073
1074 tmp = 0x40;
1075 if (vblankstart & 0x200) tmp |= 0x20;
1076 //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
1077 write3X4(par, VGA_CRTC_MAX_SCAN, tmp);
1078
1079 write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF);
1080 write3X4(par, VGA_CRTC_PRESET_ROW, 0);
1081 write3X4(par, VGA_CRTC_MODE, 0xC3);
1082
1083 write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
1084
1085 tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
1086 /* enable access extended memory */
1087 write3X4(par, CRTCModuleTest, tmp);
1088 tmp = read3CE(par, MiscIntContReg) & ~0x4;
1089 if (info->var.vmode & FB_VMODE_INTERLACED)
1090 tmp |= 0x4;
1091 write3CE(par, MiscIntContReg, tmp);
1092
1093 /* enable GE for text acceleration */
1094 write3X4(par, GraphEngReg, 0x80);
1095
1096 switch (bpp) {
1097 case 8:
1098 tmp = 0x00;
1099 break;
1100 case 16:
1101 tmp = 0x05;
1102 break;
1103 case 24:
1104 tmp = 0x29;
1105 break;
1106 case 32:
1107 tmp = 0x09;
1108 break;
1109 }
1110
1111 write3X4(par, PixelBusReg, tmp);
1112
1113 tmp = read3X4(par, DRAMControl);
1114 if (!is_oldprotect(par->chip_id))
1115 tmp |= 0x10;
1116 if (iscyber(par->chip_id))
1117 tmp |= 0x20;
1118 write3X4(par, DRAMControl, tmp); /* both IO, linear enable */
1119
1120 write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
1121 if (!is_xp(par->chip_id))
1122 write3X4(par, Performance, read3X4(par, Performance) | 0x10);
1123 /* MMIO & PCI read and write burst enable */
1124 if (par->chip_id != TGUI9440 && par->chip_id != IMAGE975)
1125 write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06);
1126
1127 vga_mm_wseq(par->io_virt, 0, 3);
1128 vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */
1129 /* enable 4 maps because needed in chain4 mode */
1130 vga_mm_wseq(par->io_virt, 2, 0x0F);
1131 vga_mm_wseq(par->io_virt, 3, 0);
1132 vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */
1133
1134 /* convert from picoseconds to kHz */
1135 vclk = PICOS2KHZ(info->var.pixclock);
1136
1137 /* divide clock by 2 if 32bpp chain4 mode display and CPU path */
1138 tmp = read3CE(par, MiscExtFunc) & 0xF0;
1139 if (bpp == 32 || (par->chip_id == TGUI9440 && bpp == 16)) {
1140 tmp |= 8;
1141 vclk *= 2;
1142 }
1143 set_vclk(par, vclk);
1144 write3CE(par, MiscExtFunc, tmp | 0x12);
1145 write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */
1146 write3CE(par, 0x6, 0x05); /* graphics mode */
1147 write3CE(par, 0x7, 0x0F); /* planes? */
1148
1149 /* graphics mode and support 256 color modes */
1150 writeAttr(par, 0x10, 0x41);
1151 writeAttr(par, 0x12, 0x0F); /* planes */
1152 writeAttr(par, 0x13, 0); /* horizontal pel panning */
1153
1154 /* colors */
1155 for (tmp = 0; tmp < 0x10; tmp++)
1156 writeAttr(par, tmp, tmp);
1157 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
1158 t_outb(par, 0x20, VGA_ATT_W); /* enable attr */
1159
1160 switch (bpp) {
1161 case 8:
1162 tmp = 0;
1163 break;
1164 case 16:
1165 tmp = 0x30;
1166 break;
1167 case 24:
1168 case 32:
1169 tmp = 0xD0;
1170 break;
1171 }
1172
1173 t_inb(par, VGA_PEL_IW);
1174 t_inb(par, VGA_PEL_MSK);
1175 t_inb(par, VGA_PEL_MSK);
1176 t_inb(par, VGA_PEL_MSK);
1177 t_inb(par, VGA_PEL_MSK);
1178 t_outb(par, tmp, VGA_PEL_MSK);
1179 t_inb(par, VGA_PEL_IW);
1180
1181 if (par->flatpanel)
1182 set_number_of_lines(par, info->var.yres);
1183 info->fix.line_length = info->var.xres_virtual * bpp / 8;
1184 set_lwidth(par, info->fix.line_length / 8);
1185
1186 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1187 par->init_accel(par, info->var.xres_virtual, bpp);
1188
1189 info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1190 info->cmap.len = (bpp == 8) ? 256 : 16;
1191 debug("exit\n");
1192 return 0;
1193 }
1194
1195 /* Set one color register */
1196 static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1197 unsigned blue, unsigned transp,
1198 struct fb_info *info)
1199 {
1200 int bpp = info->var.bits_per_pixel;
1201 struct tridentfb_par *par = info->par;
1202
1203 if (regno >= info->cmap.len)
1204 return 1;
1205
1206 if (bpp == 8) {
1207 t_outb(par, 0xFF, VGA_PEL_MSK);
1208 t_outb(par, regno, VGA_PEL_IW);
1209
1210 t_outb(par, red >> 10, VGA_PEL_D);
1211 t_outb(par, green >> 10, VGA_PEL_D);
1212 t_outb(par, blue >> 10, VGA_PEL_D);
1213
1214 } else if (regno < 16) {
1215 if (bpp == 16) { /* RGB 565 */
1216 u32 col;
1217
1218 col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
1219 ((blue & 0xF800) >> 11);
1220 col |= col << 16;
1221 ((u32 *)(info->pseudo_palette))[regno] = col;
1222 } else if (bpp == 32) /* ARGB 8888 */
1223 ((u32 *)info->pseudo_palette)[regno] =
1224 ((transp & 0xFF00) << 16) |
1225 ((red & 0xFF00) << 8) |
1226 ((green & 0xFF00)) |
1227 ((blue & 0xFF00) >> 8);
1228 }
1229
1230 /* debug("exit\n"); */
1231 return 0;
1232 }
1233
1234 /* Try blanking the screen. For flat panels it does nothing */
1235 static int tridentfb_blank(int blank_mode, struct fb_info *info)
1236 {
1237 unsigned char PMCont, DPMSCont;
1238 struct tridentfb_par *par = info->par;
1239
1240 debug("enter\n");
1241 if (par->flatpanel)
1242 return 0;
1243 t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */
1244 PMCont = t_inb(par, 0x83C6) & 0xFC;
1245 DPMSCont = read3CE(par, PowerStatus) & 0xFC;
1246 switch (blank_mode) {
1247 case FB_BLANK_UNBLANK:
1248 /* Screen: On, HSync: On, VSync: On */
1249 case FB_BLANK_NORMAL:
1250 /* Screen: Off, HSync: On, VSync: On */
1251 PMCont |= 0x03;
1252 DPMSCont |= 0x00;
1253 break;
1254 case FB_BLANK_HSYNC_SUSPEND:
1255 /* Screen: Off, HSync: Off, VSync: On */
1256 PMCont |= 0x02;
1257 DPMSCont |= 0x01;
1258 break;
1259 case FB_BLANK_VSYNC_SUSPEND:
1260 /* Screen: Off, HSync: On, VSync: Off */
1261 PMCont |= 0x02;
1262 DPMSCont |= 0x02;
1263 break;
1264 case FB_BLANK_POWERDOWN:
1265 /* Screen: Off, HSync: Off, VSync: Off */
1266 PMCont |= 0x00;
1267 DPMSCont |= 0x03;
1268 break;
1269 }
1270
1271 write3CE(par, PowerStatus, DPMSCont);
1272 t_outb(par, 4, 0x83C8);
1273 t_outb(par, PMCont, 0x83C6);
1274
1275 debug("exit\n");
1276
1277 /* let fbcon do a softblank for us */
1278 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1279 }
1280
1281 static struct fb_ops tridentfb_ops = {
1282 .owner = THIS_MODULE,
1283 .fb_setcolreg = tridentfb_setcolreg,
1284 .fb_pan_display = tridentfb_pan_display,
1285 .fb_blank = tridentfb_blank,
1286 .fb_check_var = tridentfb_check_var,
1287 .fb_set_par = tridentfb_set_par,
1288 .fb_fillrect = tridentfb_fillrect,
1289 .fb_copyarea = tridentfb_copyarea,
1290 .fb_imageblit = cfb_imageblit,
1291 #ifdef CONFIG_FB_TRIDENT_ACCEL
1292 .fb_sync = tridentfb_sync,
1293 #endif
1294 };
1295
1296 static int __devinit trident_pci_probe(struct pci_dev *dev,
1297 const struct pci_device_id *id)
1298 {
1299 int err;
1300 unsigned char revision;
1301 struct fb_info *info;
1302 struct tridentfb_par *default_par;
1303 int chip3D;
1304 int chip_id;
1305
1306 err = pci_enable_device(dev);
1307 if (err)
1308 return err;
1309
1310 info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev);
1311 if (!info)
1312 return -ENOMEM;
1313 default_par = info->par;
1314
1315 chip_id = id->device;
1316
1317 if (chip_id == CYBERBLADEi1)
1318 output("*** Please do use cyblafb, Cyberblade/i1 support "
1319 "will soon be removed from tridentfb!\n");
1320
1321 #ifndef CONFIG_FB_TRIDENT_ACCEL
1322 noaccel = 1;
1323 #endif
1324
1325 /* If PCI id is 0x9660 then further detect chip type */
1326
1327 if (chip_id == TGUI9660) {
1328 revision = vga_io_rseq(RevisionID);
1329
1330 switch (revision) {
1331 case 0x21:
1332 chip_id = PROVIDIA9685;
1333 break;
1334 case 0x22:
1335 case 0x23:
1336 chip_id = CYBER9397;
1337 break;
1338 case 0x2A:
1339 chip_id = CYBER9397DVD;
1340 break;
1341 case 0x30:
1342 case 0x33:
1343 case 0x34:
1344 case 0x35:
1345 case 0x38:
1346 case 0x3A:
1347 case 0xB3:
1348 chip_id = CYBER9385;
1349 break;
1350 case 0x40 ... 0x43:
1351 chip_id = CYBER9382;
1352 break;
1353 case 0x4A:
1354 chip_id = CYBER9388;
1355 break;
1356 default:
1357 break;
1358 }
1359 }
1360
1361 chip3D = is3Dchip(chip_id);
1362
1363 if (is_xp(chip_id)) {
1364 default_par->init_accel = xp_init_accel;
1365 default_par->wait_engine = xp_wait_engine;
1366 default_par->fill_rect = xp_fill_rect;
1367 default_par->copy_rect = xp_copy_rect;
1368 tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADEXP;
1369 } else if (is_blade(chip_id)) {
1370 default_par->init_accel = blade_init_accel;
1371 default_par->wait_engine = blade_wait_engine;
1372 default_par->fill_rect = blade_fill_rect;
1373 default_par->copy_rect = blade_copy_rect;
1374 tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADE3D;
1375 } else if (chip3D) { /* 3DImage family left */
1376 default_par->init_accel = image_init_accel;
1377 default_par->wait_engine = image_wait_engine;
1378 default_par->fill_rect = image_fill_rect;
1379 default_par->copy_rect = image_copy_rect;
1380 tridentfb_fix.accel = FB_ACCEL_TRIDENT_3DIMAGE;
1381 } else { /* TGUI 9440/96XX family */
1382 default_par->init_accel = tgui_init_accel;
1383 default_par->wait_engine = xp_wait_engine;
1384 default_par->fill_rect = tgui_fill_rect;
1385 default_par->copy_rect = tgui_copy_rect;
1386 tridentfb_fix.accel = FB_ACCEL_TRIDENT_TGUI;
1387 }
1388
1389 default_par->chip_id = chip_id;
1390
1391 /* setup MMIO region */
1392 tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
1393 tridentfb_fix.mmio_len = pci_resource_len(dev, 1);
1394
1395 if (!request_mem_region(tridentfb_fix.mmio_start,
1396 tridentfb_fix.mmio_len, "tridentfb")) {
1397 debug("request_region failed!\n");
1398 framebuffer_release(info);
1399 return -1;
1400 }
1401
1402 default_par->io_virt = ioremap_nocache(tridentfb_fix.mmio_start,
1403 tridentfb_fix.mmio_len);
1404
1405 if (!default_par->io_virt) {
1406 debug("ioremap failed\n");
1407 err = -1;
1408 goto out_unmap1;
1409 }
1410
1411 enable_mmio(default_par);
1412
1413 /* setup framebuffer memory */
1414 tridentfb_fix.smem_start = pci_resource_start(dev, 0);
1415 tridentfb_fix.smem_len = get_memsize(default_par);
1416
1417 if (!request_mem_region(tridentfb_fix.smem_start,
1418 tridentfb_fix.smem_len, "tridentfb")) {
1419 debug("request_mem_region failed!\n");
1420 disable_mmio(info->par);
1421 err = -1;
1422 goto out_unmap1;
1423 }
1424
1425 info->screen_base = ioremap_nocache(tridentfb_fix.smem_start,
1426 tridentfb_fix.smem_len);
1427
1428 if (!info->screen_base) {
1429 debug("ioremap failed\n");
1430 err = -1;
1431 goto out_unmap2;
1432 }
1433
1434 default_par->flatpanel = is_flatpanel(default_par);
1435
1436 if (default_par->flatpanel)
1437 nativex = get_nativex(default_par);
1438
1439 info->fix = tridentfb_fix;
1440 info->fbops = &tridentfb_ops;
1441 info->pseudo_palette = default_par->pseudo_pal;
1442
1443 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1444 if (!noaccel && default_par->init_accel) {
1445 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1446 info->flags |= FBINFO_HWACCEL_COPYAREA;
1447 info->flags |= FBINFO_HWACCEL_FILLRECT;
1448 } else
1449 info->flags |= FBINFO_HWACCEL_DISABLED;
1450
1451 if (!fb_find_mode(&info->var, info,
1452 mode_option, NULL, 0, NULL, bpp)) {
1453 err = -EINVAL;
1454 goto out_unmap2;
1455 }
1456 err = fb_alloc_cmap(&info->cmap, 256, 0);
1457 if (err < 0)
1458 goto out_unmap2;
1459
1460 info->var.activate |= FB_ACTIVATE_NOW;
1461 info->device = &dev->dev;
1462 if (register_framebuffer(info) < 0) {
1463 printk(KERN_ERR "tridentfb: could not register framebuffer\n");
1464 fb_dealloc_cmap(&info->cmap);
1465 err = -EINVAL;
1466 goto out_unmap2;
1467 }
1468 output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
1469 info->node, info->fix.id, info->var.xres,
1470 info->var.yres, info->var.bits_per_pixel);
1471
1472 pci_set_drvdata(dev, info);
1473 return 0;
1474
1475 out_unmap2:
1476 if (info->screen_base)
1477 iounmap(info->screen_base);
1478 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1479 disable_mmio(info->par);
1480 out_unmap1:
1481 if (default_par->io_virt)
1482 iounmap(default_par->io_virt);
1483 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1484 framebuffer_release(info);
1485 return err;
1486 }
1487
1488 static void __devexit trident_pci_remove(struct pci_dev *dev)
1489 {
1490 struct fb_info *info = pci_get_drvdata(dev);
1491 struct tridentfb_par *par = info->par;
1492
1493 unregister_framebuffer(info);
1494 iounmap(par->io_virt);
1495 iounmap(info->screen_base);
1496 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1497 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1498 pci_set_drvdata(dev, NULL);
1499 framebuffer_release(info);
1500 }
1501
1502 /* List of boards that we are trying to support */
1503 static struct pci_device_id trident_devices[] = {
1504 {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1505 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1506 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1507 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1508 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1509 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1510 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1511 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1512 {PCI_VENDOR_ID_TRIDENT, TGUI9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1513 {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1514 {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1515 {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1516 {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1517 {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1518 {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1519 {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1520 {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1521 {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1522 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1523 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1524 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1525 {0,}
1526 };
1527
1528 MODULE_DEVICE_TABLE(pci, trident_devices);
1529
1530 static struct pci_driver tridentfb_pci_driver = {
1531 .name = "tridentfb",
1532 .id_table = trident_devices,
1533 .probe = trident_pci_probe,
1534 .remove = __devexit_p(trident_pci_remove)
1535 };
1536
1537 /*
1538 * Parse user specified options (`video=trident:')
1539 * example:
1540 * video=trident:800x600,bpp=16,noaccel
1541 */
1542 #ifndef MODULE
1543 static int __init tridentfb_setup(char *options)
1544 {
1545 char *opt;
1546 if (!options || !*options)
1547 return 0;
1548 while ((opt = strsep(&options, ",")) != NULL) {
1549 if (!*opt)
1550 continue;
1551 if (!strncmp(opt, "noaccel", 7))
1552 noaccel = 1;
1553 else if (!strncmp(opt, "fp", 2))
1554 fp = 1;
1555 else if (!strncmp(opt, "crt", 3))
1556 fp = 0;
1557 else if (!strncmp(opt, "bpp=", 4))
1558 bpp = simple_strtoul(opt + 4, NULL, 0);
1559 else if (!strncmp(opt, "center", 6))
1560 center = 1;
1561 else if (!strncmp(opt, "stretch", 7))
1562 stretch = 1;
1563 else if (!strncmp(opt, "memsize=", 8))
1564 memsize = simple_strtoul(opt + 8, NULL, 0);
1565 else if (!strncmp(opt, "memdiff=", 8))
1566 memdiff = simple_strtoul(opt + 8, NULL, 0);
1567 else if (!strncmp(opt, "nativex=", 8))
1568 nativex = simple_strtoul(opt + 8, NULL, 0);
1569 else
1570 mode_option = opt;
1571 }
1572 return 0;
1573 }
1574 #endif
1575
1576 static int __init tridentfb_init(void)
1577 {
1578 #ifndef MODULE
1579 char *option = NULL;
1580
1581 if (fb_get_options("tridentfb", &option))
1582 return -ENODEV;
1583 tridentfb_setup(option);
1584 #endif
1585 return pci_register_driver(&tridentfb_pci_driver);
1586 }
1587
1588 static void __exit tridentfb_exit(void)
1589 {
1590 pci_unregister_driver(&tridentfb_pci_driver);
1591 }
1592
1593 module_init(tridentfb_init);
1594 module_exit(tridentfb_exit);
1595
1596 MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
1597 MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
1598 MODULE_LICENSE("GPL");
1599
AMDTP streaming driver for the Linux FireWire stack (Juju)