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iwlwifi: proper monitor support
[firewire-audio.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
bloba793cd11f73806163143e468825c0812ff84fd79
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/version.h>
30 #include <linux/init.h>
31 #include <linux/pci.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/delay.h>
34 #include <linux/skbuff.h>
35 #include <linux/netdevice.h>
36 #include <linux/wireless.h>
37 #include <linux/firmware.h>
38 #include <linux/etherdevice.h>
39 #include <asm/unaligned.h>
40 #include <net/mac80211.h>
41
42 #include "iwl-3945.h"
43 #include "iwl-helpers.h"
44 #include "iwl-3945-rs.h"
45
46 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
47 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
48 IWL_RATE_##r##M_IEEE, \
49 IWL_RATE_##ip##M_INDEX, \
50 IWL_RATE_##in##M_INDEX, \
51 IWL_RATE_##rp##M_INDEX, \
52 IWL_RATE_##rn##M_INDEX, \
53 IWL_RATE_##pp##M_INDEX, \
54 IWL_RATE_##np##M_INDEX, \
55 IWL_RATE_##r##M_INDEX_TABLE, \
56 IWL_RATE_##ip##M_INDEX_TABLE }
57
58 /*
59 * Parameter order:
60 * rate, prev rate, next rate, prev tgg rate, next tgg rate
61 *
62 * If there isn't a valid next or previous rate then INV is used which
63 * maps to IWL_RATE_INVALID
64 *
65 */
66 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT] = {
67 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
68 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
69 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
70 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
71 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
72 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
73 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
74 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
75 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
76 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
77 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
78 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
79 };
80
81 /* 1 = enable the iwl3945_disable_events() function */
82 #define IWL_EVT_DISABLE (0)
83 #define IWL_EVT_DISABLE_SIZE (1532/32)
84
85 /**
86 * iwl3945_disable_events - Disable selected events in uCode event log
87 *
88 * Disable an event by writing "1"s into "disable"
89 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
90 * Default values of 0 enable uCode events to be logged.
91 * Use for only special debugging. This function is just a placeholder as-is,
92 * you'll need to provide the special bits! ...
93 * ... and set IWL_EVT_DISABLE to 1. */
94 void iwl3945_disable_events(struct iwl3945_priv *priv)
95 {
96 int ret;
97 int i;
98 u32 base; /* SRAM address of event log header */
99 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
100 u32 array_size; /* # of u32 entries in array */
101 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
102 0x00000000, /* 31 - 0 Event id numbers */
103 0x00000000, /* 63 - 32 */
104 0x00000000, /* 95 - 64 */
105 0x00000000, /* 127 - 96 */
106 0x00000000, /* 159 - 128 */
107 0x00000000, /* 191 - 160 */
108 0x00000000, /* 223 - 192 */
109 0x00000000, /* 255 - 224 */
110 0x00000000, /* 287 - 256 */
111 0x00000000, /* 319 - 288 */
112 0x00000000, /* 351 - 320 */
113 0x00000000, /* 383 - 352 */
114 0x00000000, /* 415 - 384 */
115 0x00000000, /* 447 - 416 */
116 0x00000000, /* 479 - 448 */
117 0x00000000, /* 511 - 480 */
118 0x00000000, /* 543 - 512 */
119 0x00000000, /* 575 - 544 */
120 0x00000000, /* 607 - 576 */
121 0x00000000, /* 639 - 608 */
122 0x00000000, /* 671 - 640 */
123 0x00000000, /* 703 - 672 */
124 0x00000000, /* 735 - 704 */
125 0x00000000, /* 767 - 736 */
126 0x00000000, /* 799 - 768 */
127 0x00000000, /* 831 - 800 */
128 0x00000000, /* 863 - 832 */
129 0x00000000, /* 895 - 864 */
130 0x00000000, /* 927 - 896 */
131 0x00000000, /* 959 - 928 */
132 0x00000000, /* 991 - 960 */
133 0x00000000, /* 1023 - 992 */
134 0x00000000, /* 1055 - 1024 */
135 0x00000000, /* 1087 - 1056 */
136 0x00000000, /* 1119 - 1088 */
137 0x00000000, /* 1151 - 1120 */
138 0x00000000, /* 1183 - 1152 */
139 0x00000000, /* 1215 - 1184 */
140 0x00000000, /* 1247 - 1216 */
141 0x00000000, /* 1279 - 1248 */
142 0x00000000, /* 1311 - 1280 */
143 0x00000000, /* 1343 - 1312 */
144 0x00000000, /* 1375 - 1344 */
145 0x00000000, /* 1407 - 1376 */
146 0x00000000, /* 1439 - 1408 */
147 0x00000000, /* 1471 - 1440 */
148 0x00000000, /* 1503 - 1472 */
149 };
150
151 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
152 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
153 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
154 return;
155 }
156
157 ret = iwl3945_grab_nic_access(priv);
158 if (ret) {
159 IWL_WARNING("Can not read from adapter at this time.\n");
160 return;
161 }
162
163 disable_ptr = iwl3945_read_targ_mem(priv, base + (4 * sizeof(u32)));
164 array_size = iwl3945_read_targ_mem(priv, base + (5 * sizeof(u32)));
165 iwl3945_release_nic_access(priv);
166
167 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
168 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
169 disable_ptr);
170 ret = iwl3945_grab_nic_access(priv);
171 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
172 iwl3945_write_targ_mem(priv,
173 disable_ptr + (i * sizeof(u32)),
174 evt_disable[i]);
175
176 iwl3945_release_nic_access(priv);
177 } else {
178 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
179 IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n");
180 IWL_DEBUG_INFO(" in SRAM at 0x%x, size %d u32s\n",
181 disable_ptr, array_size);
182 }
183
184 }
185
186 /**
187 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
188 * @priv: eeprom and antenna fields are used to determine antenna flags
189 *
190 * priv->eeprom is used to determine if antenna AUX/MAIN are reversed
191 * priv->antenna specifies the antenna diversity mode:
192 *
193 * IWL_ANTENNA_DIVERISTY - NIC selects best antenna by itself
194 * IWL_ANTENNA_MAIN - Force MAIN antenna
195 * IWL_ANTENNA_AUX - Force AUX antenna
196 */
197 __le32 iwl3945_get_antenna_flags(const struct iwl3945_priv *priv)
198 {
199 switch (priv->antenna) {
200 case IWL_ANTENNA_DIVERSITY:
201 return 0;
202
203 case IWL_ANTENNA_MAIN:
204 if (priv->eeprom.antenna_switch_type)
205 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
206 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
207
208 case IWL_ANTENNA_AUX:
209 if (priv->eeprom.antenna_switch_type)
210 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
211 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
212 }
213
214 /* bad antenna selector value */
215 IWL_ERROR("Bad antenna selector value (0x%x)\n", priv->antenna);
216 return 0; /* "diversity" is default if error */
217 }
218
219 /*****************************************************************************
220 *
221 * Intel PRO/Wireless 3945ABG/BG Network Connection
222 *
223 * RX handler implementations
224 *
225 * Used by iwl-base.c
226 *
227 *****************************************************************************/
228
229 void iwl3945_hw_rx_statistics(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
230 {
231 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
232 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
233 (int)sizeof(struct iwl3945_notif_statistics),
234 le32_to_cpu(pkt->len));
235
236 memcpy(&priv->statistics, pkt->u.raw, sizeof(priv->statistics));
237
238 priv->last_statistics_time = jiffies;
239 }
240
241 void iwl3945_add_radiotap(struct iwl3945_priv *priv, struct sk_buff *skb,
242 struct iwl3945_rx_frame_hdr *rx_hdr,
243 struct ieee80211_rx_status *stats)
244 {
245 /* First cache any information we need before we overwrite
246 * the information provided in the skb from the hardware */
247 s8 signal = stats->ssi;
248 s8 noise = 0;
249 int rate = stats->rate;
250 u64 tsf = stats->mactime;
251 __le16 phy_flags_hw = rx_hdr->phy_flags;
252
253 struct iwl3945_rt_rx_hdr {
254 struct ieee80211_radiotap_header rt_hdr;
255 __le64 rt_tsf; /* TSF */
256 u8 rt_flags; /* radiotap packet flags */
257 u8 rt_rate; /* rate in 500kb/s */
258 __le16 rt_channelMHz; /* channel in MHz */
259 __le16 rt_chbitmask; /* channel bitfield */
260 s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
261 s8 rt_dbmnoise;
262 u8 rt_antenna; /* antenna number */
263 } __attribute__ ((packed)) *iwl3945_rt;
264
265 if (skb_headroom(skb) < sizeof(*iwl3945_rt)) {
266 if (net_ratelimit())
267 printk(KERN_ERR "not enough headroom [%d] for "
268 "radiotap head [%d]\n",
269 skb_headroom(skb), sizeof(*iwl3945_rt));
270 return;
271 }
272
273 /* put radiotap header in front of 802.11 header and data */
274 iwl3945_rt = (void *)skb_push(skb, sizeof(*iwl3945_rt));
275
276 /* initialise radiotap header */
277 iwl3945_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
278 iwl3945_rt->rt_hdr.it_pad = 0;
279
280 /* total header + data */
281 put_unaligned(cpu_to_le16(sizeof(*iwl3945_rt)),
282 &iwl3945_rt->rt_hdr.it_len);
283
284 /* Indicate all the fields we add to the radiotap header */
285 put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
286 (1 << IEEE80211_RADIOTAP_FLAGS) |
287 (1 << IEEE80211_RADIOTAP_RATE) |
288 (1 << IEEE80211_RADIOTAP_CHANNEL) |
289 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
290 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
291 (1 << IEEE80211_RADIOTAP_ANTENNA)),
292 &iwl3945_rt->rt_hdr.it_present);
293
294 /* Zero the flags, we'll add to them as we go */
295 iwl3945_rt->rt_flags = 0;
296
297 put_unaligned(cpu_to_le64(tsf), &iwl3945_rt->rt_tsf);
298
299 iwl3945_rt->rt_dbmsignal = signal;
300 iwl3945_rt->rt_dbmnoise = noise;
301
302 /* Convert the channel frequency and set the flags */
303 put_unaligned(cpu_to_le16(stats->freq), &iwl3945_rt->rt_channelMHz);
304 if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
305 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
306 IEEE80211_CHAN_5GHZ),
307 &iwl3945_rt->rt_chbitmask);
308 else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
309 put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
310 IEEE80211_CHAN_2GHZ),
311 &iwl3945_rt->rt_chbitmask);
312 else /* 802.11g */
313 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
314 IEEE80211_CHAN_2GHZ),
315 &iwl3945_rt->rt_chbitmask);
316
317 rate = iwl3945_rate_index_from_plcp(rate);
318 if (rate == -1)
319 iwl3945_rt->rt_rate = 0;
320 else
321 iwl3945_rt->rt_rate = iwl3945_rates[rate].ieee;
322
323 /* antenna number */
324 iwl3945_rt->rt_antenna =
325 le16_to_cpu(phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
326
327 /* set the preamble flag if we have it */
328 if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
329 iwl3945_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
330
331 stats->flag |= RX_FLAG_RADIOTAP;
332 }
333
334 static void iwl3945_handle_data_packet(struct iwl3945_priv *priv, int is_data,
335 struct iwl3945_rx_mem_buffer *rxb,
336 struct ieee80211_rx_status *stats)
337 {
338 struct ieee80211_hdr *hdr;
339 struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
340 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
341 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
342 short len = le16_to_cpu(rx_hdr->len);
343
344 /* We received data from the HW, so stop the watchdog */
345 if (unlikely((len + IWL_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
346 IWL_DEBUG_DROP("Corruption detected!\n");
347 return;
348 }
349
350 /* We only process data packets if the interface is open */
351 if (unlikely(!priv->is_open)) {
352 IWL_DEBUG_DROP_LIMIT
353 ("Dropping packet while interface is not open.\n");
354 return;
355 }
356
357 skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
358 /* Set the size of the skb to the size of the frame */
359 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
360
361 hdr = (void *)rxb->skb->data;
362
363 if (iwl3945_param_hwcrypto)
364 iwl3945_set_decrypted_flag(priv, rxb->skb,
365 le32_to_cpu(rx_end->status), stats);
366
367 if (priv->add_radiotap)
368 iwl3945_add_radiotap(priv, rxb->skb, rx_hdr, stats);
369
370 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
371 rxb->skb = NULL;
372 }
373
374 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
375
376 static void iwl3945_rx_reply_rx(struct iwl3945_priv *priv,
377 struct iwl3945_rx_mem_buffer *rxb)
378 {
379 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
380 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
381 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
382 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
383 struct ieee80211_hdr *header;
384 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
385 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
386 struct ieee80211_rx_status stats = {
387 .mactime = le64_to_cpu(rx_end->timestamp),
388 .freq = ieee80211chan2mhz(le16_to_cpu(rx_hdr->channel)),
389 .channel = le16_to_cpu(rx_hdr->channel),
390 .phymode = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
391 MODE_IEEE80211G : MODE_IEEE80211A,
392 .antenna = 0,
393 .rate = rx_hdr->rate,
394 .flag = 0,
395 };
396 u8 network_packet;
397 int snr;
398
399 if ((unlikely(rx_stats->phy_count > 20))) {
400 IWL_DEBUG_DROP
401 ("dsp size out of range [0,20]: "
402 "%d/n", rx_stats->phy_count);
403 return;
404 }
405
406 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
407 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
408 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
409 return;
410 }
411
412 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
413 iwl3945_handle_data_packet(priv, 1, rxb, &stats);
414 return;
415 }
416
417 /* Convert 3945's rssi indicator to dBm */
418 stats.ssi = rx_stats->rssi - IWL_RSSI_OFFSET;
419
420 /* Set default noise value to -127 */
421 if (priv->last_rx_noise == 0)
422 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
423
424 /* 3945 provides noise info for OFDM frames only.
425 * sig_avg and noise_diff are measured by the 3945's digital signal
426 * processor (DSP), and indicate linear levels of signal level and
427 * distortion/noise within the packet preamble after
428 * automatic gain control (AGC). sig_avg should stay fairly
429 * constant if the radio's AGC is working well.
430 * Since these values are linear (not dB or dBm), linear
431 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
432 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
433 * to obtain noise level in dBm.
434 * Calculate stats.signal (quality indicator in %) based on SNR. */
435 if (rx_stats_noise_diff) {
436 snr = rx_stats_sig_avg / rx_stats_noise_diff;
437 stats.noise = stats.ssi - iwl3945_calc_db_from_ratio(snr);
438 stats.signal = iwl3945_calc_sig_qual(stats.ssi, stats.noise);
439
440 /* If noise info not available, calculate signal quality indicator (%)
441 * using just the dBm signal level. */
442 } else {
443 stats.noise = priv->last_rx_noise;
444 stats.signal = iwl3945_calc_sig_qual(stats.ssi, 0);
445 }
446
447
448 IWL_DEBUG_STATS("Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
449 stats.ssi, stats.noise, stats.signal,
450 rx_stats_sig_avg, rx_stats_noise_diff);
451
452 stats.freq = ieee80211chan2mhz(stats.channel);
453
454 /* can be covered by iwl3945_report_frame() in most cases */
455 /* IWL_DEBUG_RX("RX status: 0x%08X\n", rx_end->status); */
456
457 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
458
459 network_packet = iwl3945_is_network_packet(priv, header);
460
461 #ifdef CONFIG_IWL3945_DEBUG
462 if (iwl3945_debug_level & IWL_DL_STATS && net_ratelimit())
463 IWL_DEBUG_STATS
464 ("[%c] %d RSSI: %d Signal: %u, Noise: %u, Rate: %u\n",
465 network_packet ? '*' : ' ',
466 stats.channel, stats.ssi, stats.ssi,
467 stats.ssi, stats.rate);
468
469 if (iwl3945_debug_level & (IWL_DL_RX))
470 /* Set "1" to report good data frames in groups of 100 */
471 iwl3945_report_frame(priv, pkt, header, 1);
472 #endif
473
474 if (network_packet) {
475 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
476 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
477 priv->last_rx_rssi = stats.ssi;
478 priv->last_rx_noise = stats.noise;
479 }
480
481 switch (le16_to_cpu(header->frame_control) & IEEE80211_FCTL_FTYPE) {
482 case IEEE80211_FTYPE_MGMT:
483 switch (le16_to_cpu(header->frame_control) &
484 IEEE80211_FCTL_STYPE) {
485 case IEEE80211_STYPE_PROBE_RESP:
486 case IEEE80211_STYPE_BEACON:{
487 /* If this is a beacon or probe response for
488 * our network then cache the beacon
489 * timestamp */
490 if ((((priv->iw_mode == IEEE80211_IF_TYPE_STA)
491 && !compare_ether_addr(header->addr2,
492 priv->bssid)) ||
493 ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
494 && !compare_ether_addr(header->addr3,
495 priv->bssid)))) {
496 struct ieee80211_mgmt *mgmt =
497 (struct ieee80211_mgmt *)header;
498 __le32 *pos;
499 pos =
500 (__le32 *) & mgmt->u.beacon.
501 timestamp;
502 priv->timestamp0 = le32_to_cpu(pos[0]);
503 priv->timestamp1 = le32_to_cpu(pos[1]);
504 priv->beacon_int = le16_to_cpu(
505 mgmt->u.beacon.beacon_int);
506 if (priv->call_post_assoc_from_beacon &&
507 (priv->iw_mode ==
508 IEEE80211_IF_TYPE_STA))
509 queue_work(priv->workqueue,
510 &priv->post_associate.work);
511
512 priv->call_post_assoc_from_beacon = 0;
513 }
514
515 break;
516 }
517
518 case IEEE80211_STYPE_ACTION:
519 /* TODO: Parse 802.11h frames for CSA... */
520 break;
521
522 /*
523 * TODO: There is no callback function from upper
524 * stack to inform us when associated status. this
525 * work around to sniff assoc_resp management frame
526 * and finish the association process.
527 */
528 case IEEE80211_STYPE_ASSOC_RESP:
529 case IEEE80211_STYPE_REASSOC_RESP:{
530 struct ieee80211_mgmt *mgnt =
531 (struct ieee80211_mgmt *)header;
532
533 /* We have just associated, give some
534 * time for the 4-way handshake if
535 * any. Don't start scan too early. */
536 priv->next_scan_jiffies = jiffies +
537 IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
538
539 priv->assoc_id = (~((1 << 15) | (1 << 14)) &
540 le16_to_cpu(mgnt->u.
541 assoc_resp.aid));
542 priv->assoc_capability =
543 le16_to_cpu(mgnt->u.assoc_resp.capab_info);
544 if (priv->beacon_int)
545 queue_work(priv->workqueue,
546 &priv->post_associate.work);
547 else
548 priv->call_post_assoc_from_beacon = 1;
549 break;
550 }
551
552 case IEEE80211_STYPE_PROBE_REQ:{
553 DECLARE_MAC_BUF(mac1);
554 DECLARE_MAC_BUF(mac2);
555 DECLARE_MAC_BUF(mac3);
556 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
557 IWL_DEBUG_DROP
558 ("Dropping (non network): %s"
559 ", %s, %s\n",
560 print_mac(mac1, header->addr1),
561 print_mac(mac2, header->addr2),
562 print_mac(mac3, header->addr3));
563 return;
564 }
565 }
566
567 iwl3945_handle_data_packet(priv, 0, rxb, &stats);
568 break;
569
570 case IEEE80211_FTYPE_CTL:
571 break;
572
573 case IEEE80211_FTYPE_DATA: {
574 DECLARE_MAC_BUF(mac1);
575 DECLARE_MAC_BUF(mac2);
576 DECLARE_MAC_BUF(mac3);
577
578 if (unlikely(iwl3945_is_duplicate_packet(priv, header)))
579 IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
580 print_mac(mac1, header->addr1),
581 print_mac(mac2, header->addr2),
582 print_mac(mac3, header->addr3));
583 else
584 iwl3945_handle_data_packet(priv, 1, rxb, &stats);
585 break;
586 }
587 }
588 }
589
590 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl3945_priv *priv, void *ptr,
591 dma_addr_t addr, u16 len)
592 {
593 int count;
594 u32 pad;
595 struct iwl3945_tfd_frame *tfd = (struct iwl3945_tfd_frame *)ptr;
596
597 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
598 pad = TFD_CTL_PAD_GET(le32_to_cpu(tfd->control_flags));
599
600 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
601 IWL_ERROR("Error can not send more than %d chunks\n",
602 NUM_TFD_CHUNKS);
603 return -EINVAL;
604 }
605
606 tfd->pa[count].addr = cpu_to_le32(addr);
607 tfd->pa[count].len = cpu_to_le32(len);
608
609 count++;
610
611 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
612 TFD_CTL_PAD_SET(pad));
613
614 return 0;
615 }
616
617 /**
618 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
619 *
620 * Does NOT advance any indexes
621 */
622 int iwl3945_hw_txq_free_tfd(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
623 {
624 struct iwl3945_tfd_frame *bd_tmp = (struct iwl3945_tfd_frame *)&txq->bd[0];
625 struct iwl3945_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
626 struct pci_dev *dev = priv->pci_dev;
627 int i;
628 int counter;
629
630 /* classify bd */
631 if (txq->q.id == IWL_CMD_QUEUE_NUM)
632 /* nothing to cleanup after for host commands */
633 return 0;
634
635 /* sanity check */
636 counter = TFD_CTL_COUNT_GET(le32_to_cpu(bd->control_flags));
637 if (counter > NUM_TFD_CHUNKS) {
638 IWL_ERROR("Too many chunks: %i\n", counter);
639 /* @todo issue fatal error, it is quite serious situation */
640 return 0;
641 }
642
643 /* unmap chunks if any */
644
645 for (i = 1; i < counter; i++) {
646 pci_unmap_single(dev, le32_to_cpu(bd->pa[i].addr),
647 le32_to_cpu(bd->pa[i].len), PCI_DMA_TODEVICE);
648 if (txq->txb[txq->q.read_ptr].skb[0]) {
649 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
650 if (txq->txb[txq->q.read_ptr].skb[0]) {
651 /* Can be called from interrupt context */
652 dev_kfree_skb_any(skb);
653 txq->txb[txq->q.read_ptr].skb[0] = NULL;
654 }
655 }
656 }
657 return 0;
658 }
659
660 u8 iwl3945_hw_find_station(struct iwl3945_priv *priv, const u8 *addr)
661 {
662 int i;
663 int ret = IWL_INVALID_STATION;
664 unsigned long flags;
665 DECLARE_MAC_BUF(mac);
666
667 spin_lock_irqsave(&priv->sta_lock, flags);
668 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
669 if ((priv->stations[i].used) &&
670 (!compare_ether_addr
671 (priv->stations[i].sta.sta.addr, addr))) {
672 ret = i;
673 goto out;
674 }
675
676 IWL_DEBUG_INFO("can not find STA %s (total %d)\n",
677 print_mac(mac, addr), priv->num_stations);
678 out:
679 spin_unlock_irqrestore(&priv->sta_lock, flags);
680 return ret;
681 }
682
683 /**
684 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
685 *
686 */
687 void iwl3945_hw_build_tx_cmd_rate(struct iwl3945_priv *priv,
688 struct iwl3945_cmd *cmd,
689 struct ieee80211_tx_control *ctrl,
690 struct ieee80211_hdr *hdr, int sta_id, int tx_id)
691 {
692 unsigned long flags;
693 u16 rate_index = min(ctrl->tx_rate & 0xffff, IWL_RATE_COUNT - 1);
694 u16 rate_mask;
695 int rate;
696 u8 rts_retry_limit;
697 u8 data_retry_limit;
698 __le32 tx_flags;
699 u16 fc = le16_to_cpu(hdr->frame_control);
700
701 rate = iwl3945_rates[rate_index].plcp;
702 tx_flags = cmd->cmd.tx.tx_flags;
703
704 /* We need to figure out how to get the sta->supp_rates while
705 * in this running context; perhaps encoding into ctrl->tx_rate? */
706 rate_mask = IWL_RATES_MASK;
707
708 spin_lock_irqsave(&priv->sta_lock, flags);
709
710 priv->stations[sta_id].current_rate.rate_n_flags = rate;
711
712 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
713 (sta_id != IWL3945_BROADCAST_ID) &&
714 (sta_id != IWL_MULTICAST_ID))
715 priv->stations[IWL_STA_ID].current_rate.rate_n_flags = rate;
716
717 spin_unlock_irqrestore(&priv->sta_lock, flags);
718
719 if (tx_id >= IWL_CMD_QUEUE_NUM)
720 rts_retry_limit = 3;
721 else
722 rts_retry_limit = 7;
723
724 if (ieee80211_is_probe_response(fc)) {
725 data_retry_limit = 3;
726 if (data_retry_limit < rts_retry_limit)
727 rts_retry_limit = data_retry_limit;
728 } else
729 data_retry_limit = IWL_DEFAULT_TX_RETRY;
730
731 if (priv->data_retry_limit != -1)
732 data_retry_limit = priv->data_retry_limit;
733
734 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
735 switch (fc & IEEE80211_FCTL_STYPE) {
736 case IEEE80211_STYPE_AUTH:
737 case IEEE80211_STYPE_DEAUTH:
738 case IEEE80211_STYPE_ASSOC_REQ:
739 case IEEE80211_STYPE_REASSOC_REQ:
740 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
741 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
742 tx_flags |= TX_CMD_FLG_CTS_MSK;
743 }
744 break;
745 default:
746 break;
747 }
748 }
749
750 cmd->cmd.tx.rts_retry_limit = rts_retry_limit;
751 cmd->cmd.tx.data_retry_limit = data_retry_limit;
752 cmd->cmd.tx.rate = rate;
753 cmd->cmd.tx.tx_flags = tx_flags;
754
755 /* OFDM */
756 cmd->cmd.tx.supp_rates[0] =
757 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
758
759 /* CCK */
760 cmd->cmd.tx.supp_rates[1] = (rate_mask & 0xF);
761
762 IWL_DEBUG_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
763 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
764 cmd->cmd.tx.rate, le32_to_cpu(cmd->cmd.tx.tx_flags),
765 cmd->cmd.tx.supp_rates[1], cmd->cmd.tx.supp_rates[0]);
766 }
767
768 u8 iwl3945_sync_sta(struct iwl3945_priv *priv, int sta_id, u16 tx_rate, u8 flags)
769 {
770 unsigned long flags_spin;
771 struct iwl3945_station_entry *station;
772
773 if (sta_id == IWL_INVALID_STATION)
774 return IWL_INVALID_STATION;
775
776 spin_lock_irqsave(&priv->sta_lock, flags_spin);
777 station = &priv->stations[sta_id];
778
779 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
780 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
781 station->current_rate.rate_n_flags = tx_rate;
782 station->sta.mode = STA_CONTROL_MODIFY_MSK;
783
784 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
785
786 iwl3945_send_add_station(priv, &station->sta, flags);
787 IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n",
788 sta_id, tx_rate);
789 return sta_id;
790 }
791
792 static int iwl3945_nic_set_pwr_src(struct iwl3945_priv *priv, int pwr_max)
793 {
794 int rc;
795 unsigned long flags;
796
797 spin_lock_irqsave(&priv->lock, flags);
798 rc = iwl3945_grab_nic_access(priv);
799 if (rc) {
800 spin_unlock_irqrestore(&priv->lock, flags);
801 return rc;
802 }
803
804 if (!pwr_max) {
805 u32 val;
806
807 rc = pci_read_config_dword(priv->pci_dev,
808 PCI_POWER_SOURCE, &val);
809 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
810 iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
811 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
812 ~APMG_PS_CTRL_MSK_PWR_SRC);
813 iwl3945_release_nic_access(priv);
814
815 iwl3945_poll_bit(priv, CSR_GPIO_IN,
816 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
817 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
818 } else
819 iwl3945_release_nic_access(priv);
820 } else {
821 iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
822 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
823 ~APMG_PS_CTRL_MSK_PWR_SRC);
824
825 iwl3945_release_nic_access(priv);
826 iwl3945_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
827 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
828 }
829 spin_unlock_irqrestore(&priv->lock, flags);
830
831 return rc;
832 }
833
834 static int iwl3945_rx_init(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
835 {
836 int rc;
837 unsigned long flags;
838
839 spin_lock_irqsave(&priv->lock, flags);
840 rc = iwl3945_grab_nic_access(priv);
841 if (rc) {
842 spin_unlock_irqrestore(&priv->lock, flags);
843 return rc;
844 }
845
846 iwl3945_write_direct32(priv, FH_RCSR_RBD_BASE(0), rxq->dma_addr);
847 iwl3945_write_direct32(priv, FH_RCSR_RPTR_ADDR(0),
848 priv->hw_setting.shared_phys +
849 offsetof(struct iwl3945_shared, rx_read_ptr[0]));
850 iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), 0);
851 iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0),
852 ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
853 ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
854 ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
855 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
856 (RX_QUEUE_SIZE_LOG << ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
857 ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
858 (1 << ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
859 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
860
861 /* fake read to flush all prev I/O */
862 iwl3945_read_direct32(priv, FH_RSSR_CTRL);
863
864 iwl3945_release_nic_access(priv);
865 spin_unlock_irqrestore(&priv->lock, flags);
866
867 return 0;
868 }
869
870 static int iwl3945_tx_reset(struct iwl3945_priv *priv)
871 {
872 int rc;
873 unsigned long flags;
874
875 spin_lock_irqsave(&priv->lock, flags);
876 rc = iwl3945_grab_nic_access(priv);
877 if (rc) {
878 spin_unlock_irqrestore(&priv->lock, flags);
879 return rc;
880 }
881
882 /* bypass mode */
883 iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
884
885 /* RA 0 is active */
886 iwl3945_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
887
888 /* all 6 fifo are active */
889 iwl3945_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
890
891 iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
892 iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
893 iwl3945_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
894 iwl3945_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
895
896 iwl3945_write_direct32(priv, FH_TSSR_CBB_BASE,
897 priv->hw_setting.shared_phys);
898
899 iwl3945_write_direct32(priv, FH_TSSR_MSG_CONFIG,
900 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
901 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
902 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
903 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
904 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
905 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
906 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
907
908 iwl3945_release_nic_access(priv);
909 spin_unlock_irqrestore(&priv->lock, flags);
910
911 return 0;
912 }
913
914 /**
915 * iwl3945_txq_ctx_reset - Reset TX queue context
916 *
917 * Destroys all DMA structures and initialize them again
918 */
919 static int iwl3945_txq_ctx_reset(struct iwl3945_priv *priv)
920 {
921 int rc;
922 int txq_id, slots_num;
923
924 iwl3945_hw_txq_ctx_free(priv);
925
926 /* Tx CMD queue */
927 rc = iwl3945_tx_reset(priv);
928 if (rc)
929 goto error;
930
931 /* Tx queue(s) */
932 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
933 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
934 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
935 rc = iwl3945_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
936 txq_id);
937 if (rc) {
938 IWL_ERROR("Tx %d queue init failed\n", txq_id);
939 goto error;
940 }
941 }
942
943 return rc;
944
945 error:
946 iwl3945_hw_txq_ctx_free(priv);
947 return rc;
948 }
949
950 int iwl3945_hw_nic_init(struct iwl3945_priv *priv)
951 {
952 u8 rev_id;
953 int rc;
954 unsigned long flags;
955 struct iwl3945_rx_queue *rxq = &priv->rxq;
956
957 iwl3945_power_init_handle(priv);
958
959 spin_lock_irqsave(&priv->lock, flags);
960 iwl3945_set_bit(priv, CSR_ANA_PLL_CFG, (1 << 24));
961 iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
962 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
963
964 iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
965 rc = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
966 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
967 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
968 if (rc < 0) {
969 spin_unlock_irqrestore(&priv->lock, flags);
970 IWL_DEBUG_INFO("Failed to init the card\n");
971 return rc;
972 }
973
974 rc = iwl3945_grab_nic_access(priv);
975 if (rc) {
976 spin_unlock_irqrestore(&priv->lock, flags);
977 return rc;
978 }
979 iwl3945_write_prph(priv, APMG_CLK_EN_REG,
980 APMG_CLK_VAL_DMA_CLK_RQT |
981 APMG_CLK_VAL_BSM_CLK_RQT);
982 udelay(20);
983 iwl3945_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
984 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
985 iwl3945_release_nic_access(priv);
986 spin_unlock_irqrestore(&priv->lock, flags);
987
988 /* Determine HW type */
989 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
990 if (rc)
991 return rc;
992 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
993
994 iwl3945_nic_set_pwr_src(priv, 1);
995 spin_lock_irqsave(&priv->lock, flags);
996
997 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
998 IWL_DEBUG_INFO("RTP type \n");
999 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1000 IWL_DEBUG_INFO("ALM-MB type\n");
1001 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1002 CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MB);
1003 } else {
1004 IWL_DEBUG_INFO("ALM-MM type\n");
1005 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1006 CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MM);
1007 }
1008
1009 spin_unlock_irqrestore(&priv->lock, flags);
1010
1011 /* Initialize the EEPROM */
1012 rc = iwl3945_eeprom_init(priv);
1013 if (rc)
1014 return rc;
1015
1016 spin_lock_irqsave(&priv->lock, flags);
1017 if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom.sku_cap) {
1018 IWL_DEBUG_INFO("SKU OP mode is mrc\n");
1019 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1020 CSR_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1021 } else
1022 IWL_DEBUG_INFO("SKU OP mode is basic\n");
1023
1024 if ((priv->eeprom.board_revision & 0xF0) == 0xD0) {
1025 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1026 priv->eeprom.board_revision);
1027 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1028 CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1029 } else {
1030 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1031 priv->eeprom.board_revision);
1032 iwl3945_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1033 CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1034 }
1035
1036 if (priv->eeprom.almgor_m_version <= 1) {
1037 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1038 CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1039 IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
1040 priv->eeprom.almgor_m_version);
1041 } else {
1042 IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
1043 priv->eeprom.almgor_m_version);
1044 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1045 CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1046 }
1047 spin_unlock_irqrestore(&priv->lock, flags);
1048
1049 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1050 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
1051
1052 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1053 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
1054
1055 /* Allocate the RX queue, or reset if it is already allocated */
1056 if (!rxq->bd) {
1057 rc = iwl3945_rx_queue_alloc(priv);
1058 if (rc) {
1059 IWL_ERROR("Unable to initialize Rx queue\n");
1060 return -ENOMEM;
1061 }
1062 } else
1063 iwl3945_rx_queue_reset(priv, rxq);
1064
1065 iwl3945_rx_replenish(priv);
1066
1067 iwl3945_rx_init(priv, rxq);
1068
1069 spin_lock_irqsave(&priv->lock, flags);
1070
1071 /* Look at using this instead:
1072 rxq->need_update = 1;
1073 iwl3945_rx_queue_update_write_ptr(priv, rxq);
1074 */
1075
1076 rc = iwl3945_grab_nic_access(priv);
1077 if (rc) {
1078 spin_unlock_irqrestore(&priv->lock, flags);
1079 return rc;
1080 }
1081 iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), rxq->write & ~7);
1082 iwl3945_release_nic_access(priv);
1083
1084 spin_unlock_irqrestore(&priv->lock, flags);
1085
1086 rc = iwl3945_txq_ctx_reset(priv);
1087 if (rc)
1088 return rc;
1089
1090 set_bit(STATUS_INIT, &priv->status);
1091
1092 return 0;
1093 }
1094
1095 /**
1096 * iwl3945_hw_txq_ctx_free - Free TXQ Context
1097 *
1098 * Destroy all TX DMA queues and structures
1099 */
1100 void iwl3945_hw_txq_ctx_free(struct iwl3945_priv *priv)
1101 {
1102 int txq_id;
1103
1104 /* Tx queues */
1105 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
1106 iwl3945_tx_queue_free(priv, &priv->txq[txq_id]);
1107 }
1108
1109 void iwl3945_hw_txq_ctx_stop(struct iwl3945_priv *priv)
1110 {
1111 int queue;
1112 unsigned long flags;
1113
1114 spin_lock_irqsave(&priv->lock, flags);
1115 if (iwl3945_grab_nic_access(priv)) {
1116 spin_unlock_irqrestore(&priv->lock, flags);
1117 iwl3945_hw_txq_ctx_free(priv);
1118 return;
1119 }
1120
1121 /* stop SCD */
1122 iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0);
1123
1124 /* reset TFD queues */
1125 for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) {
1126 iwl3945_write_direct32(priv, FH_TCSR_CONFIG(queue), 0x0);
1127 iwl3945_poll_direct_bit(priv, FH_TSSR_TX_STATUS,
1128 ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(queue),
1129 1000);
1130 }
1131
1132 iwl3945_release_nic_access(priv);
1133 spin_unlock_irqrestore(&priv->lock, flags);
1134
1135 iwl3945_hw_txq_ctx_free(priv);
1136 }
1137
1138 int iwl3945_hw_nic_stop_master(struct iwl3945_priv *priv)
1139 {
1140 int rc = 0;
1141 u32 reg_val;
1142 unsigned long flags;
1143
1144 spin_lock_irqsave(&priv->lock, flags);
1145
1146 /* set stop master bit */
1147 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
1148
1149 reg_val = iwl3945_read32(priv, CSR_GP_CNTRL);
1150
1151 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
1152 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
1153 IWL_DEBUG_INFO("Card in power save, master is already "
1154 "stopped\n");
1155 else {
1156 rc = iwl3945_poll_bit(priv, CSR_RESET,
1157 CSR_RESET_REG_FLAG_MASTER_DISABLED,
1158 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
1159 if (rc < 0) {
1160 spin_unlock_irqrestore(&priv->lock, flags);
1161 return rc;
1162 }
1163 }
1164
1165 spin_unlock_irqrestore(&priv->lock, flags);
1166 IWL_DEBUG_INFO("stop master\n");
1167
1168 return rc;
1169 }
1170
1171 int iwl3945_hw_nic_reset(struct iwl3945_priv *priv)
1172 {
1173 int rc;
1174 unsigned long flags;
1175
1176 iwl3945_hw_nic_stop_master(priv);
1177
1178 spin_lock_irqsave(&priv->lock, flags);
1179
1180 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1181
1182 rc = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
1183 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1184 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1185
1186 rc = iwl3945_grab_nic_access(priv);
1187 if (!rc) {
1188 iwl3945_write_prph(priv, APMG_CLK_CTRL_REG,
1189 APMG_CLK_VAL_BSM_CLK_RQT);
1190
1191 udelay(10);
1192
1193 iwl3945_set_bit(priv, CSR_GP_CNTRL,
1194 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1195
1196 iwl3945_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1197 iwl3945_write_prph(priv, APMG_RTC_INT_STT_REG,
1198 0xFFFFFFFF);
1199
1200 /* enable DMA */
1201 iwl3945_write_prph(priv, APMG_CLK_EN_REG,
1202 APMG_CLK_VAL_DMA_CLK_RQT |
1203 APMG_CLK_VAL_BSM_CLK_RQT);
1204 udelay(10);
1205
1206 iwl3945_set_bits_prph(priv, APMG_PS_CTRL_REG,
1207 APMG_PS_CTRL_VAL_RESET_REQ);
1208 udelay(5);
1209 iwl3945_clear_bits_prph(priv, APMG_PS_CTRL_REG,
1210 APMG_PS_CTRL_VAL_RESET_REQ);
1211 iwl3945_release_nic_access(priv);
1212 }
1213
1214 /* Clear the 'host command active' bit... */
1215 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1216
1217 wake_up_interruptible(&priv->wait_command_queue);
1218 spin_unlock_irqrestore(&priv->lock, flags);
1219
1220 return rc;
1221 }
1222
1223 /**
1224 * iwl3945_hw_reg_adjust_power_by_temp
1225 * return index delta into power gain settings table
1226 */
1227 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1228 {
1229 return (new_reading - old_reading) * (-11) / 100;
1230 }
1231
1232 /**
1233 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1234 */
1235 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1236 {
1237 return (((temperature < -260) || (temperature > 25)) ? 1 : 0);
1238 }
1239
1240 int iwl3945_hw_get_temperature(struct iwl3945_priv *priv)
1241 {
1242 return iwl3945_read32(priv, CSR_UCODE_DRV_GP2);
1243 }
1244
1245 /**
1246 * iwl3945_hw_reg_txpower_get_temperature
1247 * get the current temperature by reading from NIC
1248 */
1249 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl3945_priv *priv)
1250 {
1251 int temperature;
1252
1253 temperature = iwl3945_hw_get_temperature(priv);
1254
1255 /* driver's okay range is -260 to +25.
1256 * human readable okay range is 0 to +285 */
1257 IWL_DEBUG_INFO("Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1258
1259 /* handle insane temp reading */
1260 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1261 IWL_ERROR("Error bad temperature value %d\n", temperature);
1262
1263 /* if really really hot(?),
1264 * substitute the 3rd band/group's temp measured at factory */
1265 if (priv->last_temperature > 100)
1266 temperature = priv->eeprom.groups[2].temperature;
1267 else /* else use most recent "sane" value from driver */
1268 temperature = priv->last_temperature;
1269 }
1270
1271 return temperature; /* raw, not "human readable" */
1272 }
1273
1274 /* Adjust Txpower only if temperature variance is greater than threshold.
1275 *
1276 * Both are lower than older versions' 9 degrees */
1277 #define IWL_TEMPERATURE_LIMIT_TIMER 6
1278
1279 /**
1280 * is_temp_calib_needed - determines if new calibration is needed
1281 *
1282 * records new temperature in tx_mgr->temperature.
1283 * replaces tx_mgr->last_temperature *only* if calib needed
1284 * (assumes caller will actually do the calibration!). */
1285 static int is_temp_calib_needed(struct iwl3945_priv *priv)
1286 {
1287 int temp_diff;
1288
1289 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1290 temp_diff = priv->temperature - priv->last_temperature;
1291
1292 /* get absolute value */
1293 if (temp_diff < 0) {
1294 IWL_DEBUG_POWER("Getting cooler, delta %d,\n", temp_diff);
1295 temp_diff = -temp_diff;
1296 } else if (temp_diff == 0)
1297 IWL_DEBUG_POWER("Same temp,\n");
1298 else
1299 IWL_DEBUG_POWER("Getting warmer, delta %d,\n", temp_diff);
1300
1301 /* if we don't need calibration, *don't* update last_temperature */
1302 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1303 IWL_DEBUG_POWER("Timed thermal calib not needed\n");
1304 return 0;
1305 }
1306
1307 IWL_DEBUG_POWER("Timed thermal calib needed\n");
1308
1309 /* assume that caller will actually do calib ...
1310 * update the "last temperature" value */
1311 priv->last_temperature = priv->temperature;
1312 return 1;
1313 }
1314
1315 #define IWL_MAX_GAIN_ENTRIES 78
1316 #define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1317 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1318
1319 /* radio and DSP power table, each step is 1/2 dB.
1320 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1321 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1322 {
1323 {251, 127}, /* 2.4 GHz, highest power */
1324 {251, 127},
1325 {251, 127},
1326 {251, 127},
1327 {251, 125},
1328 {251, 110},
1329 {251, 105},
1330 {251, 98},
1331 {187, 125},
1332 {187, 115},
1333 {187, 108},
1334 {187, 99},
1335 {243, 119},
1336 {243, 111},
1337 {243, 105},
1338 {243, 97},
1339 {243, 92},
1340 {211, 106},
1341 {211, 100},
1342 {179, 120},
1343 {179, 113},
1344 {179, 107},
1345 {147, 125},
1346 {147, 119},
1347 {147, 112},
1348 {147, 106},
1349 {147, 101},
1350 {147, 97},
1351 {147, 91},
1352 {115, 107},
1353 {235, 121},
1354 {235, 115},
1355 {235, 109},
1356 {203, 127},
1357 {203, 121},
1358 {203, 115},
1359 {203, 108},
1360 {203, 102},
1361 {203, 96},
1362 {203, 92},
1363 {171, 110},
1364 {171, 104},
1365 {171, 98},
1366 {139, 116},
1367 {227, 125},
1368 {227, 119},
1369 {227, 113},
1370 {227, 107},
1371 {227, 101},
1372 {227, 96},
1373 {195, 113},
1374 {195, 106},
1375 {195, 102},
1376 {195, 95},
1377 {163, 113},
1378 {163, 106},
1379 {163, 102},
1380 {163, 95},
1381 {131, 113},
1382 {131, 106},
1383 {131, 102},
1384 {131, 95},
1385 {99, 113},
1386 {99, 106},
1387 {99, 102},
1388 {99, 95},
1389 {67, 113},
1390 {67, 106},
1391 {67, 102},
1392 {67, 95},
1393 {35, 113},
1394 {35, 106},
1395 {35, 102},
1396 {35, 95},
1397 {3, 113},
1398 {3, 106},
1399 {3, 102},
1400 {3, 95} }, /* 2.4 GHz, lowest power */
1401 {
1402 {251, 127}, /* 5.x GHz, highest power */
1403 {251, 120},
1404 {251, 114},
1405 {219, 119},
1406 {219, 101},
1407 {187, 113},
1408 {187, 102},
1409 {155, 114},
1410 {155, 103},
1411 {123, 117},
1412 {123, 107},
1413 {123, 99},
1414 {123, 92},
1415 {91, 108},
1416 {59, 125},
1417 {59, 118},
1418 {59, 109},
1419 {59, 102},
1420 {59, 96},
1421 {59, 90},
1422 {27, 104},
1423 {27, 98},
1424 {27, 92},
1425 {115, 118},
1426 {115, 111},
1427 {115, 104},
1428 {83, 126},
1429 {83, 121},
1430 {83, 113},
1431 {83, 105},
1432 {83, 99},
1433 {51, 118},
1434 {51, 111},
1435 {51, 104},
1436 {51, 98},
1437 {19, 116},
1438 {19, 109},
1439 {19, 102},
1440 {19, 98},
1441 {19, 93},
1442 {171, 113},
1443 {171, 107},
1444 {171, 99},
1445 {139, 120},
1446 {139, 113},
1447 {139, 107},
1448 {139, 99},
1449 {107, 120},
1450 {107, 113},
1451 {107, 107},
1452 {107, 99},
1453 {75, 120},
1454 {75, 113},
1455 {75, 107},
1456 {75, 99},
1457 {43, 120},
1458 {43, 113},
1459 {43, 107},
1460 {43, 99},
1461 {11, 120},
1462 {11, 113},
1463 {11, 107},
1464 {11, 99},
1465 {131, 107},
1466 {131, 99},
1467 {99, 120},
1468 {99, 113},
1469 {99, 107},
1470 {99, 99},
1471 {67, 120},
1472 {67, 113},
1473 {67, 107},
1474 {67, 99},
1475 {35, 120},
1476 {35, 113},
1477 {35, 107},
1478 {35, 99},
1479 {3, 120} } /* 5.x GHz, lowest power */
1480 };
1481
1482 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1483 {
1484 if (index < 0)
1485 return 0;
1486 if (index >= IWL_MAX_GAIN_ENTRIES)
1487 return IWL_MAX_GAIN_ENTRIES - 1;
1488 return (u8) index;
1489 }
1490
1491 /* Kick off thermal recalibration check every 60 seconds */
1492 #define REG_RECALIB_PERIOD (60)
1493
1494 /**
1495 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1496 *
1497 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1498 * or 6 Mbit (OFDM) rates.
1499 */
1500 static void iwl3945_hw_reg_set_scan_power(struct iwl3945_priv *priv, u32 scan_tbl_index,
1501 s32 rate_index, const s8 *clip_pwrs,
1502 struct iwl3945_channel_info *ch_info,
1503 int band_index)
1504 {
1505 struct iwl3945_scan_power_info *scan_power_info;
1506 s8 power;
1507 u8 power_index;
1508
1509 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1510
1511 /* use this channel group's 6Mbit clipping/saturation pwr,
1512 * but cap at regulatory scan power restriction (set during init
1513 * based on eeprom channel data) for this channel. */
1514 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1515
1516 /* further limit to user's max power preference.
1517 * FIXME: Other spectrum management power limitations do not
1518 * seem to apply?? */
1519 power = min(power, priv->user_txpower_limit);
1520 scan_power_info->requested_power = power;
1521
1522 /* find difference between new scan *power* and current "normal"
1523 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1524 * current "normal" temperature-compensated Tx power *index* for
1525 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1526 * *index*. */
1527 power_index = ch_info->power_info[rate_index].power_table_index
1528 - (power - ch_info->power_info
1529 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1530
1531 /* store reference index that we use when adjusting *all* scan
1532 * powers. So we can accommodate user (all channel) or spectrum
1533 * management (single channel) power changes "between" temperature
1534 * feedback compensation procedures.
1535 * don't force fit this reference index into gain table; it may be a
1536 * negative number. This will help avoid errors when we're at
1537 * the lower bounds (highest gains, for warmest temperatures)
1538 * of the table. */
1539
1540 /* don't exceed table bounds for "real" setting */
1541 power_index = iwl3945_hw_reg_fix_power_index(power_index);
1542
1543 scan_power_info->power_table_index = power_index;
1544 scan_power_info->tpc.tx_gain =
1545 power_gain_table[band_index][power_index].tx_gain;
1546 scan_power_info->tpc.dsp_atten =
1547 power_gain_table[band_index][power_index].dsp_atten;
1548 }
1549
1550 /**
1551 * iwl3945_hw_reg_send_txpower - fill in Tx Power command with gain settings
1552 *
1553 * Configures power settings for all rates for the current channel,
1554 * using values from channel info struct, and send to NIC
1555 */
1556 int iwl3945_hw_reg_send_txpower(struct iwl3945_priv *priv)
1557 {
1558 int rate_idx, i;
1559 const struct iwl3945_channel_info *ch_info = NULL;
1560 struct iwl3945_txpowertable_cmd txpower = {
1561 .channel = priv->active_rxon.channel,
1562 };
1563
1564 txpower.band = (priv->phymode == MODE_IEEE80211A) ? 0 : 1;
1565 ch_info = iwl3945_get_channel_info(priv,
1566 priv->phymode,
1567 le16_to_cpu(priv->active_rxon.channel));
1568 if (!ch_info) {
1569 IWL_ERROR
1570 ("Failed to get channel info for channel %d [%d]\n",
1571 le16_to_cpu(priv->active_rxon.channel), priv->phymode);
1572 return -EINVAL;
1573 }
1574
1575 if (!is_channel_valid(ch_info)) {
1576 IWL_DEBUG_POWER("Not calling TX_PWR_TABLE_CMD on "
1577 "non-Tx channel.\n");
1578 return 0;
1579 }
1580
1581 /* fill cmd with power settings for all rates for current channel */
1582 /* Fill OFDM rate */
1583 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1584 rate_idx <= IWL_LAST_OFDM_RATE; rate_idx++, i++) {
1585
1586 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1587 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1588
1589 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1590 le16_to_cpu(txpower.channel),
1591 txpower.band,
1592 txpower.power[i].tpc.tx_gain,
1593 txpower.power[i].tpc.dsp_atten,
1594 txpower.power[i].rate);
1595 }
1596 /* Fill CCK rates */
1597 for (rate_idx = IWL_FIRST_CCK_RATE;
1598 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1599 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1600 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1601
1602 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1603 le16_to_cpu(txpower.channel),
1604 txpower.band,
1605 txpower.power[i].tpc.tx_gain,
1606 txpower.power[i].tpc.dsp_atten,
1607 txpower.power[i].rate);
1608 }
1609
1610 return iwl3945_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1611 sizeof(struct iwl3945_txpowertable_cmd), &txpower);
1612
1613 }
1614
1615 /**
1616 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1617 * @ch_info: Channel to update. Uses power_info.requested_power.
1618 *
1619 * Replace requested_power and base_power_index ch_info fields for
1620 * one channel.
1621 *
1622 * Called if user or spectrum management changes power preferences.
1623 * Takes into account h/w and modulation limitations (clip power).
1624 *
1625 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1626 *
1627 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1628 * properly fill out the scan powers, and actual h/w gain settings,
1629 * and send changes to NIC
1630 */
1631 static int iwl3945_hw_reg_set_new_power(struct iwl3945_priv *priv,
1632 struct iwl3945_channel_info *ch_info)
1633 {
1634 struct iwl3945_channel_power_info *power_info;
1635 int power_changed = 0;
1636 int i;
1637 const s8 *clip_pwrs;
1638 int power;
1639
1640 /* Get this chnlgrp's rate-to-max/clip-powers table */
1641 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
1642
1643 /* Get this channel's rate-to-current-power settings table */
1644 power_info = ch_info->power_info;
1645
1646 /* update OFDM Txpower settings */
1647 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1648 i++, ++power_info) {
1649 int delta_idx;
1650
1651 /* limit new power to be no more than h/w capability */
1652 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1653 if (power == power_info->requested_power)
1654 continue;
1655
1656 /* find difference between old and new requested powers,
1657 * update base (non-temp-compensated) power index */
1658 delta_idx = (power - power_info->requested_power) * 2;
1659 power_info->base_power_index -= delta_idx;
1660
1661 /* save new requested power value */
1662 power_info->requested_power = power;
1663
1664 power_changed = 1;
1665 }
1666
1667 /* update CCK Txpower settings, based on OFDM 12M setting ...
1668 * ... all CCK power settings for a given channel are the *same*. */
1669 if (power_changed) {
1670 power =
1671 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1672 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1673
1674 /* do all CCK rates' iwl3945_channel_power_info structures */
1675 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1676 power_info->requested_power = power;
1677 power_info->base_power_index =
1678 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1679 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1680 ++power_info;
1681 }
1682 }
1683
1684 return 0;
1685 }
1686
1687 /**
1688 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1689 *
1690 * NOTE: Returned power limit may be less (but not more) than requested,
1691 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1692 * (no consideration for h/w clipping limitations).
1693 */
1694 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl3945_channel_info *ch_info)
1695 {
1696 s8 max_power;
1697
1698 #if 0
1699 /* if we're using TGd limits, use lower of TGd or EEPROM */
1700 if (ch_info->tgd_data.max_power != 0)
1701 max_power = min(ch_info->tgd_data.max_power,
1702 ch_info->eeprom.max_power_avg);
1703
1704 /* else just use EEPROM limits */
1705 else
1706 #endif
1707 max_power = ch_info->eeprom.max_power_avg;
1708
1709 return min(max_power, ch_info->max_power_avg);
1710 }
1711
1712 /**
1713 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1714 *
1715 * Compensate txpower settings of *all* channels for temperature.
1716 * This only accounts for the difference between current temperature
1717 * and the factory calibration temperatures, and bases the new settings
1718 * on the channel's base_power_index.
1719 *
1720 * If RxOn is "associated", this sends the new Txpower to NIC!
1721 */
1722 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl3945_priv *priv)
1723 {
1724 struct iwl3945_channel_info *ch_info = NULL;
1725 int delta_index;
1726 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1727 u8 a_band;
1728 u8 rate_index;
1729 u8 scan_tbl_index;
1730 u8 i;
1731 int ref_temp;
1732 int temperature = priv->temperature;
1733
1734 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1735 for (i = 0; i < priv->channel_count; i++) {
1736 ch_info = &priv->channel_info[i];
1737 a_band = is_channel_a_band(ch_info);
1738
1739 /* Get this chnlgrp's factory calibration temperature */
1740 ref_temp = (s16)priv->eeprom.groups[ch_info->group_index].
1741 temperature;
1742
1743 /* get power index adjustment based on curr and factory
1744 * temps */
1745 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1746 ref_temp);
1747
1748 /* set tx power value for all rates, OFDM and CCK */
1749 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1750 rate_index++) {
1751 int power_idx =
1752 ch_info->power_info[rate_index].base_power_index;
1753
1754 /* temperature compensate */
1755 power_idx += delta_index;
1756
1757 /* stay within table range */
1758 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1759 ch_info->power_info[rate_index].
1760 power_table_index = (u8) power_idx;
1761 ch_info->power_info[rate_index].tpc =
1762 power_gain_table[a_band][power_idx];
1763 }
1764
1765 /* Get this chnlgrp's rate-to-max/clip-powers table */
1766 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
1767
1768 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1769 for (scan_tbl_index = 0;
1770 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1771 s32 actual_index = (scan_tbl_index == 0) ?
1772 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1773 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1774 actual_index, clip_pwrs,
1775 ch_info, a_band);
1776 }
1777 }
1778
1779 /* send Txpower command for current channel to ucode */
1780 return iwl3945_hw_reg_send_txpower(priv);
1781 }
1782
1783 int iwl3945_hw_reg_set_txpower(struct iwl3945_priv *priv, s8 power)
1784 {
1785 struct iwl3945_channel_info *ch_info;
1786 s8 max_power;
1787 u8 a_band;
1788 u8 i;
1789
1790 if (priv->user_txpower_limit == power) {
1791 IWL_DEBUG_POWER("Requested Tx power same as current "
1792 "limit: %ddBm.\n", power);
1793 return 0;
1794 }
1795
1796 IWL_DEBUG_POWER("Setting upper limit clamp to %ddBm.\n", power);
1797 priv->user_txpower_limit = power;
1798
1799 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1800
1801 for (i = 0; i < priv->channel_count; i++) {
1802 ch_info = &priv->channel_info[i];
1803 a_band = is_channel_a_band(ch_info);
1804
1805 /* find minimum power of all user and regulatory constraints
1806 * (does not consider h/w clipping limitations) */
1807 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1808 max_power = min(power, max_power);
1809 if (max_power != ch_info->curr_txpow) {
1810 ch_info->curr_txpow = max_power;
1811
1812 /* this considers the h/w clipping limitations */
1813 iwl3945_hw_reg_set_new_power(priv, ch_info);
1814 }
1815 }
1816
1817 /* update txpower settings for all channels,
1818 * send to NIC if associated. */
1819 is_temp_calib_needed(priv);
1820 iwl3945_hw_reg_comp_txpower_temp(priv);
1821
1822 return 0;
1823 }
1824
1825 /* will add 3945 channel switch cmd handling later */
1826 int iwl3945_hw_channel_switch(struct iwl3945_priv *priv, u16 channel)
1827 {
1828 return 0;
1829 }
1830
1831 /**
1832 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1833 *
1834 * -- reset periodic timer
1835 * -- see if temp has changed enough to warrant re-calibration ... if so:
1836 * -- correct coeffs for temp (can reset temp timer)
1837 * -- save this temp as "last",
1838 * -- send new set of gain settings to NIC
1839 * NOTE: This should continue working, even when we're not associated,
1840 * so we can keep our internal table of scan powers current. */
1841 void iwl3945_reg_txpower_periodic(struct iwl3945_priv *priv)
1842 {
1843 /* This will kick in the "brute force"
1844 * iwl3945_hw_reg_comp_txpower_temp() below */
1845 if (!is_temp_calib_needed(priv))
1846 goto reschedule;
1847
1848 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1849 * This is based *only* on current temperature,
1850 * ignoring any previous power measurements */
1851 iwl3945_hw_reg_comp_txpower_temp(priv);
1852
1853 reschedule:
1854 queue_delayed_work(priv->workqueue,
1855 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
1856 }
1857
1858 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
1859 {
1860 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv,
1861 thermal_periodic.work);
1862
1863 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1864 return;
1865
1866 mutex_lock(&priv->mutex);
1867 iwl3945_reg_txpower_periodic(priv);
1868 mutex_unlock(&priv->mutex);
1869 }
1870
1871 /**
1872 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
1873 * for the channel.
1874 *
1875 * This function is used when initializing channel-info structs.
1876 *
1877 * NOTE: These channel groups do *NOT* match the bands above!
1878 * These channel groups are based on factory-tested channels;
1879 * on A-band, EEPROM's "group frequency" entries represent the top
1880 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
1881 */
1882 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl3945_priv *priv,
1883 const struct iwl3945_channel_info *ch_info)
1884 {
1885 struct iwl3945_eeprom_txpower_group *ch_grp = &priv->eeprom.groups[0];
1886 u8 group;
1887 u16 group_index = 0; /* based on factory calib frequencies */
1888 u8 grp_channel;
1889
1890 /* Find the group index for the channel ... don't use index 1(?) */
1891 if (is_channel_a_band(ch_info)) {
1892 for (group = 1; group < 5; group++) {
1893 grp_channel = ch_grp[group].group_channel;
1894 if (ch_info->channel <= grp_channel) {
1895 group_index = group;
1896 break;
1897 }
1898 }
1899 /* group 4 has a few channels *above* its factory cal freq */
1900 if (group == 5)
1901 group_index = 4;
1902 } else
1903 group_index = 0; /* 2.4 GHz, group 0 */
1904
1905 IWL_DEBUG_POWER("Chnl %d mapped to grp %d\n", ch_info->channel,
1906 group_index);
1907 return group_index;
1908 }
1909
1910 /**
1911 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
1912 *
1913 * Interpolate to get nominal (i.e. at factory calibration temperature) index
1914 * into radio/DSP gain settings table for requested power.
1915 */
1916 static int iwl3945_hw_reg_get_matched_power_index(struct iwl3945_priv *priv,
1917 s8 requested_power,
1918 s32 setting_index, s32 *new_index)
1919 {
1920 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
1921 s32 index0, index1;
1922 s32 power = 2 * requested_power;
1923 s32 i;
1924 const struct iwl3945_eeprom_txpower_sample *samples;
1925 s32 gains0, gains1;
1926 s32 res;
1927 s32 denominator;
1928
1929 chnl_grp = &priv->eeprom.groups[setting_index];
1930 samples = chnl_grp->samples;
1931 for (i = 0; i < 5; i++) {
1932 if (power == samples[i].power) {
1933 *new_index = samples[i].gain_index;
1934 return 0;
1935 }
1936 }
1937
1938 if (power > samples[1].power) {
1939 index0 = 0;
1940 index1 = 1;
1941 } else if (power > samples[2].power) {
1942 index0 = 1;
1943 index1 = 2;
1944 } else if (power > samples[3].power) {
1945 index0 = 2;
1946 index1 = 3;
1947 } else {
1948 index0 = 3;
1949 index1 = 4;
1950 }
1951
1952 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
1953 if (denominator == 0)
1954 return -EINVAL;
1955 gains0 = (s32) samples[index0].gain_index * (1 << 19);
1956 gains1 = (s32) samples[index1].gain_index * (1 << 19);
1957 res = gains0 + (gains1 - gains0) *
1958 ((s32) power - (s32) samples[index0].power) / denominator +
1959 (1 << 18);
1960 *new_index = res >> 19;
1961 return 0;
1962 }
1963
1964 static void iwl3945_hw_reg_init_channel_groups(struct iwl3945_priv *priv)
1965 {
1966 u32 i;
1967 s32 rate_index;
1968 const struct iwl3945_eeprom_txpower_group *group;
1969
1970 IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n");
1971
1972 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
1973 s8 *clip_pwrs; /* table of power levels for each rate */
1974 s8 satur_pwr; /* saturation power for each chnl group */
1975 group = &priv->eeprom.groups[i];
1976
1977 /* sanity check on factory saturation power value */
1978 if (group->saturation_power < 40) {
1979 IWL_WARNING("Error: saturation power is %d, "
1980 "less than minimum expected 40\n",
1981 group->saturation_power);
1982 return;
1983 }
1984
1985 /*
1986 * Derive requested power levels for each rate, based on
1987 * hardware capabilities (saturation power for band).
1988 * Basic value is 3dB down from saturation, with further
1989 * power reductions for highest 3 data rates. These
1990 * backoffs provide headroom for high rate modulation
1991 * power peaks, without too much distortion (clipping).
1992 */
1993 /* we'll fill in this array with h/w max power levels */
1994 clip_pwrs = (s8 *) priv->clip_groups[i].clip_powers;
1995
1996 /* divide factory saturation power by 2 to find -3dB level */
1997 satur_pwr = (s8) (group->saturation_power >> 1);
1998
1999 /* fill in channel group's nominal powers for each rate */
2000 for (rate_index = 0;
2001 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2002 switch (rate_index) {
2003 case IWL_RATE_36M_INDEX_TABLE:
2004 if (i == 0) /* B/G */
2005 *clip_pwrs = satur_pwr;
2006 else /* A */
2007 *clip_pwrs = satur_pwr - 5;
2008 break;
2009 case IWL_RATE_48M_INDEX_TABLE:
2010 if (i == 0)
2011 *clip_pwrs = satur_pwr - 7;
2012 else
2013 *clip_pwrs = satur_pwr - 10;
2014 break;
2015 case IWL_RATE_54M_INDEX_TABLE:
2016 if (i == 0)
2017 *clip_pwrs = satur_pwr - 9;
2018 else
2019 *clip_pwrs = satur_pwr - 12;
2020 break;
2021 default:
2022 *clip_pwrs = satur_pwr;
2023 break;
2024 }
2025 }
2026 }
2027 }
2028
2029 /**
2030 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2031 *
2032 * Second pass (during init) to set up priv->channel_info
2033 *
2034 * Set up Tx-power settings in our channel info database for each VALID
2035 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2036 * and current temperature.
2037 *
2038 * Since this is based on current temperature (at init time), these values may
2039 * not be valid for very long, but it gives us a starting/default point,
2040 * and allows us to active (i.e. using Tx) scan.
2041 *
2042 * This does *not* write values to NIC, just sets up our internal table.
2043 */
2044 int iwl3945_txpower_set_from_eeprom(struct iwl3945_priv *priv)
2045 {
2046 struct iwl3945_channel_info *ch_info = NULL;
2047 struct iwl3945_channel_power_info *pwr_info;
2048 int delta_index;
2049 u8 rate_index;
2050 u8 scan_tbl_index;
2051 const s8 *clip_pwrs; /* array of power levels for each rate */
2052 u8 gain, dsp_atten;
2053 s8 power;
2054 u8 pwr_index, base_pwr_index, a_band;
2055 u8 i;
2056 int temperature;
2057
2058 /* save temperature reference,
2059 * so we can determine next time to calibrate */
2060 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2061 priv->last_temperature = temperature;
2062
2063 iwl3945_hw_reg_init_channel_groups(priv);
2064
2065 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2066 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2067 i++, ch_info++) {
2068 a_band = is_channel_a_band(ch_info);
2069 if (!is_channel_valid(ch_info))
2070 continue;
2071
2072 /* find this channel's channel group (*not* "band") index */
2073 ch_info->group_index =
2074 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2075
2076 /* Get this chnlgrp's rate->max/clip-powers table */
2077 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
2078
2079 /* calculate power index *adjustment* value according to
2080 * diff between current temperature and factory temperature */
2081 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2082 priv->eeprom.groups[ch_info->group_index].
2083 temperature);
2084
2085 IWL_DEBUG_POWER("Delta index for channel %d: %d [%d]\n",
2086 ch_info->channel, delta_index, temperature +
2087 IWL_TEMP_CONVERT);
2088
2089 /* set tx power value for all OFDM rates */
2090 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2091 rate_index++) {
2092 s32 power_idx;
2093 int rc;
2094
2095 /* use channel group's clip-power table,
2096 * but don't exceed channel's max power */
2097 s8 pwr = min(ch_info->max_power_avg,
2098 clip_pwrs[rate_index]);
2099
2100 pwr_info = &ch_info->power_info[rate_index];
2101
2102 /* get base (i.e. at factory-measured temperature)
2103 * power table index for this rate's power */
2104 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2105 ch_info->group_index,
2106 &power_idx);
2107 if (rc) {
2108 IWL_ERROR("Invalid power index\n");
2109 return rc;
2110 }
2111 pwr_info->base_power_index = (u8) power_idx;
2112
2113 /* temperature compensate */
2114 power_idx += delta_index;
2115
2116 /* stay within range of gain table */
2117 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2118
2119 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2120 pwr_info->requested_power = pwr;
2121 pwr_info->power_table_index = (u8) power_idx;
2122 pwr_info->tpc.tx_gain =
2123 power_gain_table[a_band][power_idx].tx_gain;
2124 pwr_info->tpc.dsp_atten =
2125 power_gain_table[a_band][power_idx].dsp_atten;
2126 }
2127
2128 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2129 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2130 power = pwr_info->requested_power +
2131 IWL_CCK_FROM_OFDM_POWER_DIFF;
2132 pwr_index = pwr_info->power_table_index +
2133 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2134 base_pwr_index = pwr_info->base_power_index +
2135 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2136
2137 /* stay within table range */
2138 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2139 gain = power_gain_table[a_band][pwr_index].tx_gain;
2140 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2141
2142 /* fill each CCK rate's iwl3945_channel_power_info structure
2143 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2144 * NOTE: CCK rates start at end of OFDM rates! */
2145 for (rate_index = 0;
2146 rate_index < IWL_CCK_RATES; rate_index++) {
2147 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2148 pwr_info->requested_power = power;
2149 pwr_info->power_table_index = pwr_index;
2150 pwr_info->base_power_index = base_pwr_index;
2151 pwr_info->tpc.tx_gain = gain;
2152 pwr_info->tpc.dsp_atten = dsp_atten;
2153 }
2154
2155 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2156 for (scan_tbl_index = 0;
2157 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2158 s32 actual_index = (scan_tbl_index == 0) ?
2159 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2160 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2161 actual_index, clip_pwrs, ch_info, a_band);
2162 }
2163 }
2164
2165 return 0;
2166 }
2167
2168 int iwl3945_hw_rxq_stop(struct iwl3945_priv *priv)
2169 {
2170 int rc;
2171 unsigned long flags;
2172
2173 spin_lock_irqsave(&priv->lock, flags);
2174 rc = iwl3945_grab_nic_access(priv);
2175 if (rc) {
2176 spin_unlock_irqrestore(&priv->lock, flags);
2177 return rc;
2178 }
2179
2180 iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0), 0);
2181 rc = iwl3945_poll_direct_bit(priv, FH_RSSR_STATUS, (1 << 24), 1000);
2182 if (rc < 0)
2183 IWL_ERROR("Can't stop Rx DMA.\n");
2184
2185 iwl3945_release_nic_access(priv);
2186 spin_unlock_irqrestore(&priv->lock, flags);
2187
2188 return 0;
2189 }
2190
2191 int iwl3945_hw_tx_queue_init(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
2192 {
2193 int rc;
2194 unsigned long flags;
2195 int txq_id = txq->q.id;
2196
2197 struct iwl3945_shared *shared_data = priv->hw_setting.shared_virt;
2198
2199 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2200
2201 spin_lock_irqsave(&priv->lock, flags);
2202 rc = iwl3945_grab_nic_access(priv);
2203 if (rc) {
2204 spin_unlock_irqrestore(&priv->lock, flags);
2205 return rc;
2206 }
2207 iwl3945_write_direct32(priv, FH_CBCC_CTRL(txq_id), 0);
2208 iwl3945_write_direct32(priv, FH_CBCC_BASE(txq_id), 0);
2209
2210 iwl3945_write_direct32(priv, FH_TCSR_CONFIG(txq_id),
2211 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2212 ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2213 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2214 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2215 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2216 iwl3945_release_nic_access(priv);
2217
2218 /* fake read to flush all prev. writes */
2219 iwl3945_read32(priv, FH_TSSR_CBB_BASE);
2220 spin_unlock_irqrestore(&priv->lock, flags);
2221
2222 return 0;
2223 }
2224
2225 int iwl3945_hw_get_rx_read(struct iwl3945_priv *priv)
2226 {
2227 struct iwl3945_shared *shared_data = priv->hw_setting.shared_virt;
2228
2229 return le32_to_cpu(shared_data->rx_read_ptr[0]);
2230 }
2231
2232 /**
2233 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2234 */
2235 int iwl3945_init_hw_rate_table(struct iwl3945_priv *priv)
2236 {
2237 int rc, i, index, prev_index;
2238 struct iwl3945_rate_scaling_cmd rate_cmd = {
2239 .reserved = {0, 0, 0},
2240 };
2241 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2242
2243 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2244 index = iwl3945_rates[i].table_rs_index;
2245
2246 table[index].rate_n_flags =
2247 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2248 table[index].try_cnt = priv->retry_rate;
2249 prev_index = iwl3945_get_prev_ieee_rate(i);
2250 table[index].next_rate_index = iwl3945_rates[prev_index].table_rs_index;
2251 }
2252
2253 switch (priv->phymode) {
2254 case MODE_IEEE80211A:
2255 IWL_DEBUG_RATE("Select A mode rate scale\n");
2256 /* If one of the following CCK rates is used,
2257 * have it fall back to the 6M OFDM rate */
2258 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++)
2259 table[i].next_rate_index = iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2260
2261 /* Don't fall back to CCK rates */
2262 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index = IWL_RATE_9M_INDEX_TABLE;
2263
2264 /* Don't drop out of OFDM rates */
2265 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2266 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2267 break;
2268
2269 case MODE_IEEE80211B:
2270 IWL_DEBUG_RATE("Select B mode rate scale\n");
2271 /* If an OFDM rate is used, have it fall back to the
2272 * 1M CCK rates */
2273 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE; i++)
2274 table[i].next_rate_index = iwl3945_rates[IWL_FIRST_CCK_RATE].table_rs_index;
2275
2276 /* CCK shouldn't fall back to OFDM... */
2277 table[IWL_RATE_11M_INDEX_TABLE].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2278 break;
2279
2280 default:
2281 IWL_DEBUG_RATE("Select G mode rate scale\n");
2282 break;
2283 }
2284
2285 /* Update the rate scaling for control frame Tx */
2286 rate_cmd.table_id = 0;
2287 rc = iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2288 &rate_cmd);
2289 if (rc)
2290 return rc;
2291
2292 /* Update the rate scaling for data frame Tx */
2293 rate_cmd.table_id = 1;
2294 return iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2295 &rate_cmd);
2296 }
2297
2298 /* Called when initializing driver */
2299 int iwl3945_hw_set_hw_setting(struct iwl3945_priv *priv)
2300 {
2301 memset((void *)&priv->hw_setting, 0,
2302 sizeof(struct iwl3945_driver_hw_info));
2303
2304 priv->hw_setting.shared_virt =
2305 pci_alloc_consistent(priv->pci_dev,
2306 sizeof(struct iwl3945_shared),
2307 &priv->hw_setting.shared_phys);
2308
2309 if (!priv->hw_setting.shared_virt) {
2310 IWL_ERROR("failed to allocate pci memory\n");
2311 mutex_unlock(&priv->mutex);
2312 return -ENOMEM;
2313 }
2314
2315 priv->hw_setting.ac_queue_count = AC_NUM;
2316 priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE;
2317 priv->hw_setting.max_pkt_size = 2342;
2318 priv->hw_setting.tx_cmd_len = sizeof(struct iwl3945_tx_cmd);
2319 priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
2320 priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
2321 priv->hw_setting.max_stations = IWL3945_STATION_COUNT;
2322 priv->hw_setting.bcast_sta_id = IWL3945_BROADCAST_ID;
2323 return 0;
2324 }
2325
2326 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl3945_priv *priv,
2327 struct iwl3945_frame *frame, u8 rate)
2328 {
2329 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2330 unsigned int frame_size;
2331
2332 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2333 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2334
2335 tx_beacon_cmd->tx.sta_id = IWL3945_BROADCAST_ID;
2336 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2337
2338 frame_size = iwl3945_fill_beacon_frame(priv,
2339 tx_beacon_cmd->frame,
2340 iwl3945_broadcast_addr,
2341 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2342
2343 BUG_ON(frame_size > MAX_MPDU_SIZE);
2344 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2345
2346 tx_beacon_cmd->tx.rate = rate;
2347 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2348 TX_CMD_FLG_TSF_MSK);
2349
2350 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2351 tx_beacon_cmd->tx.supp_rates[0] =
2352 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2353
2354 tx_beacon_cmd->tx.supp_rates[1] =
2355 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2356
2357 return (sizeof(struct iwl3945_tx_beacon_cmd) + frame_size);
2358 }
2359
2360 void iwl3945_hw_rx_handler_setup(struct iwl3945_priv *priv)
2361 {
2362 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2363 }
2364
2365 void iwl3945_hw_setup_deferred_work(struct iwl3945_priv *priv)
2366 {
2367 INIT_DELAYED_WORK(&priv->thermal_periodic,
2368 iwl3945_bg_reg_txpower_periodic);
2369 }
2370
2371 void iwl3945_hw_cancel_deferred_work(struct iwl3945_priv *priv)
2372 {
2373 cancel_delayed_work(&priv->thermal_periodic);
2374 }
2375
2376 struct pci_device_id iwl3945_hw_card_ids[] = {
2377 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4222)},
2378 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4227)},
2379 {0}
2380 };
2381
2382 /*
2383 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2384 * embedded controller) as EEPROM reader; each read is a series of pulses
2385 * to/from the EEPROM chip, not a single event, so even reads could conflict
2386 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2387 * simply claims ownership, which should be safe when this function is called
2388 * (i.e. before loading uCode!).
2389 */
2390 inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
2391 {
2392 _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2393 return 0;
2394 }
2395
2396 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
AMDTP streaming driver for the Linux FireWire stack (Juju)