?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
firewire: core: check for 1394a compliant IRM, fix inaccessibility of Sony camcorder
[firewire-audio.git] / drivers / net / smc91x.h
blob8d2772cc42f2ba5e174e501de81c966c6cd97474
1 /*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 .
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
27 .
28 . Authors
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@fluxnic.net>
32 .
33 ---------------------------------------------------------------------------*/
34 #ifndef _SMC91X_H_
35 #define _SMC91X_H_
36
37 #include <linux/smc91x.h>
38
39 /*
40 * Define your architecture specific bus configuration parameters here.
41 */
42
43 #if defined(CONFIG_ARCH_LUBBOCK) ||\
44 defined(CONFIG_MACH_MAINSTONE) ||\
45 defined(CONFIG_MACH_ZYLONITE) ||\
46 defined(CONFIG_MACH_LITTLETON) ||\
47 defined(CONFIG_MACH_ZYLONITE2) ||\
48 defined(CONFIG_ARCH_VIPER) ||\
49 defined(CONFIG_MACH_STARGATE2)
50
51 #include <asm/mach-types.h>
52
53 /* Now the bus width is specified in the platform data
54 * pretend here to support all I/O access types
55 */
56 #define SMC_CAN_USE_8BIT 1
57 #define SMC_CAN_USE_16BIT 1
58 #define SMC_CAN_USE_32BIT 1
59 #define SMC_NOWAIT 1
60
61 #define SMC_IO_SHIFT (lp->io_shift)
62
63 #define SMC_inb(a, r) readb((a) + (r))
64 #define SMC_inw(a, r) readw((a) + (r))
65 #define SMC_inl(a, r) readl((a) + (r))
66 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
67 #define SMC_outl(v, a, r) writel(v, (a) + (r))
68 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
69 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
70 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
71 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
72 #define SMC_IRQ_FLAGS (-1) /* from resource */
73
74 /* We actually can't write halfwords properly if not word aligned */
75 static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg)
76 {
77 if ((machine_is_mainstone() || machine_is_stargate2()) && reg & 2) {
78 unsigned int v = val << 16;
79 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
80 writel(v, ioaddr + (reg & ~2));
81 } else {
82 writew(val, ioaddr + reg);
83 }
84 }
85
86 #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
87
88 /* We can only do 16-bit reads and writes in the static memory space. */
89 #define SMC_CAN_USE_8BIT 0
90 #define SMC_CAN_USE_16BIT 1
91 #define SMC_CAN_USE_32BIT 0
92 #define SMC_NOWAIT 1
93
94 #define SMC_IO_SHIFT 0
95
96 #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
97 #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
98 #define SMC_insw(a, r, p, l) \
99 do { \
100 unsigned long __port = (a) + (r); \
101 u16 *__p = (u16 *)(p); \
102 int __l = (l); \
103 insw(__port, __p, __l); \
104 while (__l > 0) { \
105 *__p = swab16(*__p); \
106 __p++; \
107 __l--; \
108 } \
109 } while (0)
110 #define SMC_outsw(a, r, p, l) \
111 do { \
112 unsigned long __port = (a) + (r); \
113 u16 *__p = (u16 *)(p); \
114 int __l = (l); \
115 while (__l > 0) { \
116 /* Believe it or not, the swab isn't needed. */ \
117 outw( /* swab16 */ (*__p++), __port); \
118 __l--; \
119 } \
120 } while (0)
121 #define SMC_IRQ_FLAGS (0)
122
123 #elif defined(CONFIG_SA1100_PLEB)
124 /* We can only do 16-bit reads and writes in the static memory space. */
125 #define SMC_CAN_USE_8BIT 1
126 #define SMC_CAN_USE_16BIT 1
127 #define SMC_CAN_USE_32BIT 0
128 #define SMC_IO_SHIFT 0
129 #define SMC_NOWAIT 1
130
131 #define SMC_inb(a, r) readb((a) + (r))
132 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
133 #define SMC_inw(a, r) readw((a) + (r))
134 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
135 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
136 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
137 #define SMC_outw(v, a, r) writew(v, (a) + (r))
138 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
139
140 #define SMC_IRQ_FLAGS (-1)
141
142 #elif defined(CONFIG_SA1100_ASSABET)
143
144 #include <mach/neponset.h>
145
146 /* We can only do 8-bit reads and writes in the static memory space. */
147 #define SMC_CAN_USE_8BIT 1
148 #define SMC_CAN_USE_16BIT 0
149 #define SMC_CAN_USE_32BIT 0
150 #define SMC_NOWAIT 1
151
152 /* The first two address lines aren't connected... */
153 #define SMC_IO_SHIFT 2
154
155 #define SMC_inb(a, r) readb((a) + (r))
156 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
157 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
158 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
159 #define SMC_IRQ_FLAGS (-1) /* from resource */
160
161 #elif defined(CONFIG_MACH_LOGICPD_PXA270) || \
162 defined(CONFIG_MACH_NOMADIK_8815NHK)
163
164 #define SMC_CAN_USE_8BIT 0
165 #define SMC_CAN_USE_16BIT 1
166 #define SMC_CAN_USE_32BIT 0
167 #define SMC_IO_SHIFT 0
168 #define SMC_NOWAIT 1
169
170 #define SMC_inw(a, r) readw((a) + (r))
171 #define SMC_outw(v, a, r) writew(v, (a) + (r))
172 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
173 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
174
175 #elif defined(CONFIG_ARCH_INNOKOM) || \
176 defined(CONFIG_ARCH_PXA_IDP) || \
177 defined(CONFIG_ARCH_RAMSES) || \
178 defined(CONFIG_ARCH_PCM027)
179
180 #define SMC_CAN_USE_8BIT 1
181 #define SMC_CAN_USE_16BIT 1
182 #define SMC_CAN_USE_32BIT 1
183 #define SMC_IO_SHIFT 0
184 #define SMC_NOWAIT 1
185 #define SMC_USE_PXA_DMA 1
186
187 #define SMC_inb(a, r) readb((a) + (r))
188 #define SMC_inw(a, r) readw((a) + (r))
189 #define SMC_inl(a, r) readl((a) + (r))
190 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
191 #define SMC_outl(v, a, r) writel(v, (a) + (r))
192 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
193 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
194 #define SMC_IRQ_FLAGS (-1) /* from resource */
195
196 /* We actually can't write halfwords properly if not word aligned */
197 static inline void
198 SMC_outw(u16 val, void __iomem *ioaddr, int reg)
199 {
200 if (reg & 2) {
201 unsigned int v = val << 16;
202 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
203 writel(v, ioaddr + (reg & ~2));
204 } else {
205 writew(val, ioaddr + reg);
206 }
207 }
208
209 #elif defined(CONFIG_SH_SH4202_MICRODEV)
210
211 #define SMC_CAN_USE_8BIT 0
212 #define SMC_CAN_USE_16BIT 1
213 #define SMC_CAN_USE_32BIT 0
214
215 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
216 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
217 #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
218 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
219 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
220 #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
221 #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
222 #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
223 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
224 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
225
226 #define SMC_IRQ_FLAGS (0)
227
228 #elif defined(CONFIG_M32R)
229
230 #define SMC_CAN_USE_8BIT 0
231 #define SMC_CAN_USE_16BIT 1
232 #define SMC_CAN_USE_32BIT 0
233
234 #define SMC_inb(a, r) inb(((u32)a) + (r))
235 #define SMC_inw(a, r) inw(((u32)a) + (r))
236 #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
237 #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
238 #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
239 #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
240
241 #define SMC_IRQ_FLAGS (0)
242
243 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
244 #define RPC_LSB_DEFAULT RPC_LED_100_10
245
246 #elif defined(CONFIG_MACH_LPD79520) || \
247 defined(CONFIG_MACH_LPD7A400) || \
248 defined(CONFIG_MACH_LPD7A404)
249
250 /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
251 * way that the CPU handles chip selects and the way that the SMC chip
252 * expects the chip select to operate. Refer to
253 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
254 * IOBARRIER is a byte, in order that we read the least-common
255 * denominator. It would be wasteful to read 32 bits from an 8-bit
256 * accessible region.
257 *
258 * There is no explicit protection against interrupts intervening
259 * between the writew and the IOBARRIER. In SMC ISR there is a
260 * preamble that performs an IOBARRIER in the extremely unlikely event
261 * that the driver interrupts itself between a writew to the chip an
262 * the IOBARRIER that follows *and* the cache is large enough that the
263 * first off-chip access while handing the interrupt is to the SMC
264 * chip. Other devices in the same address space as the SMC chip must
265 * be aware of the potential for trouble and perform a similar
266 * IOBARRIER on entry to their ISR.
267 */
268
269 #include <mach/constants.h> /* IOBARRIER_VIRT */
270
271 #define SMC_CAN_USE_8BIT 0
272 #define SMC_CAN_USE_16BIT 1
273 #define SMC_CAN_USE_32BIT 0
274 #define SMC_NOWAIT 0
275 #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
276
277 #define SMC_inw(a,r)\
278 ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
279 #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
280
281 #define SMC_insw LPD7_SMC_insw
282 static inline void LPD7_SMC_insw (unsigned char* a, int r,
283 unsigned char* p, int l)
284 {
285 unsigned short* ps = (unsigned short*) p;
286 while (l-- > 0) {
287 *ps++ = readw (a + r);
288 LPD7X_IOBARRIER;
289 }
290 }
291
292 #define SMC_outsw LPD7_SMC_outsw
293 static inline void LPD7_SMC_outsw (unsigned char* a, int r,
294 unsigned char* p, int l)
295 {
296 unsigned short* ps = (unsigned short*) p;
297 while (l-- > 0) {
298 writew (*ps++, a + r);
299 LPD7X_IOBARRIER;
300 }
301 }
302
303 #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
304
305 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
306 #define RPC_LSB_DEFAULT RPC_LED_100_10
307
308 #elif defined(CONFIG_ARCH_VERSATILE)
309
310 #define SMC_CAN_USE_8BIT 1
311 #define SMC_CAN_USE_16BIT 1
312 #define SMC_CAN_USE_32BIT 1
313 #define SMC_NOWAIT 1
314
315 #define SMC_inb(a, r) readb((a) + (r))
316 #define SMC_inw(a, r) readw((a) + (r))
317 #define SMC_inl(a, r) readl((a) + (r))
318 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
319 #define SMC_outw(v, a, r) writew(v, (a) + (r))
320 #define SMC_outl(v, a, r) writel(v, (a) + (r))
321 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
322 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
323 #define SMC_IRQ_FLAGS (-1) /* from resource */
324
325 #elif defined(CONFIG_MN10300)
326
327 /*
328 * MN10300/AM33 configuration
329 */
330
331 #include <unit/smc91111.h>
332
333 #elif defined(CONFIG_ARCH_MSM)
334
335 #define SMC_CAN_USE_8BIT 0
336 #define SMC_CAN_USE_16BIT 1
337 #define SMC_CAN_USE_32BIT 0
338 #define SMC_NOWAIT 1
339
340 #define SMC_inw(a, r) readw((a) + (r))
341 #define SMC_outw(v, a, r) writew(v, (a) + (r))
342 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
343 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
344
345 #define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH
346
347 #elif defined(CONFIG_COLDFIRE)
348
349 #define SMC_CAN_USE_8BIT 0
350 #define SMC_CAN_USE_16BIT 1
351 #define SMC_CAN_USE_32BIT 0
352 #define SMC_NOWAIT 1
353
354 static inline void mcf_insw(void *a, unsigned char *p, int l)
355 {
356 u16 *wp = (u16 *) p;
357 while (l-- > 0)
358 *wp++ = readw(a);
359 }
360
361 static inline void mcf_outsw(void *a, unsigned char *p, int l)
362 {
363 u16 *wp = (u16 *) p;
364 while (l-- > 0)
365 writew(*wp++, a);
366 }
367
368 #define SMC_inw(a, r) _swapw(readw((a) + (r)))
369 #define SMC_outw(v, a, r) writew(_swapw(v), (a) + (r))
370 #define SMC_insw(a, r, p, l) mcf_insw(a + r, p, l)
371 #define SMC_outsw(a, r, p, l) mcf_outsw(a + r, p, l)
372
373 #define SMC_IRQ_FLAGS (IRQF_DISABLED)
374
375 #else
376
377 /*
378 * Default configuration
379 */
380
381 #define SMC_CAN_USE_8BIT 1
382 #define SMC_CAN_USE_16BIT 1
383 #define SMC_CAN_USE_32BIT 1
384 #define SMC_NOWAIT 1
385
386 #define SMC_IO_SHIFT (lp->io_shift)
387
388 #define SMC_inb(a, r) readb((a) + (r))
389 #define SMC_inw(a, r) readw((a) + (r))
390 #define SMC_inl(a, r) readl((a) + (r))
391 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
392 #define SMC_outw(v, a, r) writew(v, (a) + (r))
393 #define SMC_outl(v, a, r) writel(v, (a) + (r))
394 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
395 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
396 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
397 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
398
399 #define RPC_LSA_DEFAULT RPC_LED_100_10
400 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
401
402 #endif
403
404
405 /* store this information for the driver.. */
406 struct smc_local {
407 /*
408 * If I have to wait until memory is available to send a
409 * packet, I will store the skbuff here, until I get the
410 * desired memory. Then, I'll send it out and free it.
411 */
412 struct sk_buff *pending_tx_skb;
413 struct tasklet_struct tx_task;
414
415 /* version/revision of the SMC91x chip */
416 int version;
417
418 /* Contains the current active transmission mode */
419 int tcr_cur_mode;
420
421 /* Contains the current active receive mode */
422 int rcr_cur_mode;
423
424 /* Contains the current active receive/phy mode */
425 int rpc_cur_mode;
426 int ctl_rfduplx;
427 int ctl_rspeed;
428
429 u32 msg_enable;
430 u32 phy_type;
431 struct mii_if_info mii;
432
433 /* work queue */
434 struct work_struct phy_configure;
435 struct net_device *dev;
436 int work_pending;
437
438 spinlock_t lock;
439
440 #ifdef CONFIG_ARCH_PXA
441 /* DMA needs the physical address of the chip */
442 u_long physaddr;
443 struct device *device;
444 #endif
445 void __iomem *base;
446 void __iomem *datacs;
447
448 /* the low address lines on some platforms aren't connected... */
449 int io_shift;
450
451 struct smc91x_platdata cfg;
452 };
453
454 #define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT)
455 #define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT)
456 #define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT)
457
458 #ifdef CONFIG_ARCH_PXA
459 /*
460 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
461 * always happening in irq context so no need to worry about races. TX is
462 * different and probably not worth it for that reason, and not as critical
463 * as RX which can overrun memory and lose packets.
464 */
465 #include <linux/dma-mapping.h>
466 #include <mach/dma.h>
467
468 #ifdef SMC_insl
469 #undef SMC_insl
470 #define SMC_insl(a, r, p, l) \
471 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
472 static inline void
473 smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
474 u_char *buf, int len)
475 {
476 u_long physaddr = lp->physaddr;
477 dma_addr_t dmabuf;
478
479 /* fallback if no DMA available */
480 if (dma == (unsigned char)-1) {
481 readsl(ioaddr + reg, buf, len);
482 return;
483 }
484
485 /* 64 bit alignment is required for memory to memory DMA */
486 if ((long)buf & 4) {
487 *((u32 *)buf) = SMC_inl(ioaddr, reg);
488 buf += 4;
489 len--;
490 }
491
492 len *= 4;
493 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
494 DCSR(dma) = DCSR_NODESC;
495 DTADR(dma) = dmabuf;
496 DSADR(dma) = physaddr + reg;
497 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
498 DCMD_WIDTH4 | (DCMD_LENGTH & len));
499 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
500 while (!(DCSR(dma) & DCSR_STOPSTATE))
501 cpu_relax();
502 DCSR(dma) = 0;
503 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
504 }
505 #endif
506
507 #ifdef SMC_insw
508 #undef SMC_insw
509 #define SMC_insw(a, r, p, l) \
510 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
511 static inline void
512 smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
513 u_char *buf, int len)
514 {
515 u_long physaddr = lp->physaddr;
516 dma_addr_t dmabuf;
517
518 /* fallback if no DMA available */
519 if (dma == (unsigned char)-1) {
520 readsw(ioaddr + reg, buf, len);
521 return;
522 }
523
524 /* 64 bit alignment is required for memory to memory DMA */
525 while ((long)buf & 6) {
526 *((u16 *)buf) = SMC_inw(ioaddr, reg);
527 buf += 2;
528 len--;
529 }
530
531 len *= 2;
532 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
533 DCSR(dma) = DCSR_NODESC;
534 DTADR(dma) = dmabuf;
535 DSADR(dma) = physaddr + reg;
536 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
537 DCMD_WIDTH2 | (DCMD_LENGTH & len));
538 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
539 while (!(DCSR(dma) & DCSR_STOPSTATE))
540 cpu_relax();
541 DCSR(dma) = 0;
542 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
543 }
544 #endif
545
546 static void
547 smc_pxa_dma_irq(int dma, void *dummy)
548 {
549 DCSR(dma) = 0;
550 }
551 #endif /* CONFIG_ARCH_PXA */
552
553
554 /*
555 * Everything a particular hardware setup needs should have been defined
556 * at this point. Add stubs for the undefined cases, mainly to avoid
557 * compilation warnings since they'll be optimized away, or to prevent buggy
558 * use of them.
559 */
560
561 #if ! SMC_CAN_USE_32BIT
562 #define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
563 #define SMC_outl(x, ioaddr, reg) BUG()
564 #define SMC_insl(a, r, p, l) BUG()
565 #define SMC_outsl(a, r, p, l) BUG()
566 #endif
567
568 #if !defined(SMC_insl) || !defined(SMC_outsl)
569 #define SMC_insl(a, r, p, l) BUG()
570 #define SMC_outsl(a, r, p, l) BUG()
571 #endif
572
573 #if ! SMC_CAN_USE_16BIT
574
575 /*
576 * Any 16-bit access is performed with two 8-bit accesses if the hardware
577 * can't do it directly. Most registers are 16-bit so those are mandatory.
578 */
579 #define SMC_outw(x, ioaddr, reg) \
580 do { \
581 unsigned int __val16 = (x); \
582 SMC_outb( __val16, ioaddr, reg ); \
583 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
584 } while (0)
585 #define SMC_inw(ioaddr, reg) \
586 ({ \
587 unsigned int __val16; \
588 __val16 = SMC_inb( ioaddr, reg ); \
589 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
590 __val16; \
591 })
592
593 #define SMC_insw(a, r, p, l) BUG()
594 #define SMC_outsw(a, r, p, l) BUG()
595
596 #endif
597
598 #if !defined(SMC_insw) || !defined(SMC_outsw)
599 #define SMC_insw(a, r, p, l) BUG()
600 #define SMC_outsw(a, r, p, l) BUG()
601 #endif
602
603 #if ! SMC_CAN_USE_8BIT
604 #define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
605 #define SMC_outb(x, ioaddr, reg) BUG()
606 #define SMC_insb(a, r, p, l) BUG()
607 #define SMC_outsb(a, r, p, l) BUG()
608 #endif
609
610 #if !defined(SMC_insb) || !defined(SMC_outsb)
611 #define SMC_insb(a, r, p, l) BUG()
612 #define SMC_outsb(a, r, p, l) BUG()
613 #endif
614
615 #ifndef SMC_CAN_USE_DATACS
616 #define SMC_CAN_USE_DATACS 0
617 #endif
618
619 #ifndef SMC_IO_SHIFT
620 #define SMC_IO_SHIFT 0
621 #endif
622
623 #ifndef SMC_IRQ_FLAGS
624 #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
625 #endif
626
627 #ifndef SMC_INTERRUPT_PREAMBLE
628 #define SMC_INTERRUPT_PREAMBLE
629 #endif
630
631
632 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
633 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
634 #define SMC_DATA_EXTENT (4)
635
636 /*
637 . Bank Select Register:
638 .
639 . yyyy yyyy 0000 00xx
640 . xx = bank number
641 . yyyy yyyy = 0x33, for identification purposes.
642 */
643 #define BANK_SELECT (14 << SMC_IO_SHIFT)
644
645
646 // Transmit Control Register
647 /* BANK 0 */
648 #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
649 #define TCR_ENABLE 0x0001 // When 1 we can transmit
650 #define TCR_LOOP 0x0002 // Controls output pin LBK
651 #define TCR_FORCOL 0x0004 // When 1 will force a collision
652 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
653 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
654 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
655 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
656 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
657 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
658 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
659
660 #define TCR_CLEAR 0 /* do NOTHING */
661 /* the default settings for the TCR register : */
662 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
663
664
665 // EPH Status Register
666 /* BANK 0 */
667 #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
668 #define ES_TX_SUC 0x0001 // Last TX was successful
669 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
670 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
671 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
672 #define ES_16COL 0x0010 // 16 Collisions Reached
673 #define ES_SQET 0x0020 // Signal Quality Error Test
674 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
675 #define ES_TXDEFR 0x0080 // Transmit Deferred
676 #define ES_LATCOL 0x0200 // Late collision detected on last tx
677 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
678 #define ES_EXC_DEF 0x0800 // Excessive Deferral
679 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
680 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
681 #define ES_TXUNRN 0x8000 // Tx Underrun
682
683
684 // Receive Control Register
685 /* BANK 0 */
686 #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
687 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
688 #define RCR_PRMS 0x0002 // Enable promiscuous mode
689 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
690 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
691 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
692 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
693 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
694 #define RCR_SOFTRST 0x8000 // resets the chip
695
696 /* the normal settings for the RCR register : */
697 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
698 #define RCR_CLEAR 0x0 // set it to a base state
699
700
701 // Counter Register
702 /* BANK 0 */
703 #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
704
705
706 // Memory Information Register
707 /* BANK 0 */
708 #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
709
710
711 // Receive/Phy Control Register
712 /* BANK 0 */
713 #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
714 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
715 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
716 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
717 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
718 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
719
720 #ifndef RPC_LSA_DEFAULT
721 #define RPC_LSA_DEFAULT RPC_LED_100
722 #endif
723 #ifndef RPC_LSB_DEFAULT
724 #define RPC_LSB_DEFAULT RPC_LED_FD
725 #endif
726
727 #define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX)
728
729
730 /* Bank 0 0x0C is reserved */
731
732 // Bank Select Register
733 /* All Banks */
734 #define BSR_REG 0x000E
735
736
737 // Configuration Reg
738 /* BANK 1 */
739 #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
740 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
741 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
742 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
743 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
744
745 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
746 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
747
748
749 // Base Address Register
750 /* BANK 1 */
751 #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
752
753
754 // Individual Address Registers
755 /* BANK 1 */
756 #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
757 #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
758 #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
759
760
761 // General Purpose Register
762 /* BANK 1 */
763 #define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
764
765
766 // Control Register
767 /* BANK 1 */
768 #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
769 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
770 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
771 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
772 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
773 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
774 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
775 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
776 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
777
778
779 // MMU Command Register
780 /* BANK 2 */
781 #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
782 #define MC_BUSY 1 // When 1 the last release has not completed
783 #define MC_NOP (0<<5) // No Op
784 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
785 #define MC_RESET (2<<5) // Reset MMU to initial state
786 #define MC_REMOVE (3<<5) // Remove the current rx packet
787 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
788 #define MC_FREEPKT (5<<5) // Release packet in PNR register
789 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
790 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
791
792
793 // Packet Number Register
794 /* BANK 2 */
795 #define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
796
797
798 // Allocation Result Register
799 /* BANK 2 */
800 #define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
801 #define AR_FAILED 0x80 // Alocation Failed
802
803
804 // TX FIFO Ports Register
805 /* BANK 2 */
806 #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
807 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
808
809 // RX FIFO Ports Register
810 /* BANK 2 */
811 #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
812 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
813
814 #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
815
816 // Pointer Register
817 /* BANK 2 */
818 #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
819 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
820 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
821 #define PTR_READ 0x2000 // When 1 the operation is a read
822
823
824 // Data Register
825 /* BANK 2 */
826 #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
827
828
829 // Interrupt Status/Acknowledge Register
830 /* BANK 2 */
831 #define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
832
833
834 // Interrupt Mask Register
835 /* BANK 2 */
836 #define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
837 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
838 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
839 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
840 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
841 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
842 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
843 #define IM_TX_INT 0x02 // Transmit Interrupt
844 #define IM_RCV_INT 0x01 // Receive Interrupt
845
846
847 // Multicast Table Registers
848 /* BANK 3 */
849 #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
850 #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
851 #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
852 #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
853
854
855 // Management Interface Register (MII)
856 /* BANK 3 */
857 #define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
858 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
859 #define MII_MDOE 0x0008 // MII Output Enable
860 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
861 #define MII_MDI 0x0002 // MII Input, pin MDI
862 #define MII_MDO 0x0001 // MII Output, pin MDO
863
864
865 // Revision Register
866 /* BANK 3 */
867 /* ( hi: chip id low: rev # ) */
868 #define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
869
870
871 // Early RCV Register
872 /* BANK 3 */
873 /* this is NOT on SMC9192 */
874 #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
875 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
876 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
877
878
879 // External Register
880 /* BANK 7 */
881 #define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
882
883
884 #define CHIP_9192 3
885 #define CHIP_9194 4
886 #define CHIP_9195 5
887 #define CHIP_9196 6
888 #define CHIP_91100 7
889 #define CHIP_91100FD 8
890 #define CHIP_91111FD 9
891
892 static const char * chip_ids[ 16 ] = {
893 NULL, NULL, NULL,
894 /* 3 */ "SMC91C90/91C92",
895 /* 4 */ "SMC91C94",
896 /* 5 */ "SMC91C95",
897 /* 6 */ "SMC91C96",
898 /* 7 */ "SMC91C100",
899 /* 8 */ "SMC91C100FD",
900 /* 9 */ "SMC91C11xFD",
901 NULL, NULL, NULL,
902 NULL, NULL, NULL};
903
904
905 /*
906 . Receive status bits
907 */
908 #define RS_ALGNERR 0x8000
909 #define RS_BRODCAST 0x4000
910 #define RS_BADCRC 0x2000
911 #define RS_ODDFRAME 0x1000
912 #define RS_TOOLONG 0x0800
913 #define RS_TOOSHORT 0x0400
914 #define RS_MULTICAST 0x0001
915 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
916
917
918 /*
919 * PHY IDs
920 * LAN83C183 == LAN91C111 Internal PHY
921 */
922 #define PHY_LAN83C183 0x0016f840
923 #define PHY_LAN83C180 0x02821c50
924
925 /*
926 * PHY Register Addresses (LAN91C111 Internal PHY)
927 *
928 * Generic PHY registers can be found in <linux/mii.h>
929 *
930 * These phy registers are specific to our on-board phy.
931 */
932
933 // PHY Configuration Register 1
934 #define PHY_CFG1_REG 0x10
935 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
936 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
937 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
938 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
939 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
940 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
941 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
942 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
943 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
944 #define PHY_CFG1_TLVL_MASK 0x003C
945 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
946
947
948 // PHY Configuration Register 2
949 #define PHY_CFG2_REG 0x11
950 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
951 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
952 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
953 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
954
955 // PHY Status Output (and Interrupt status) Register
956 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
957 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
958 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
959 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
960 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
961 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
962 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
963 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
964 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
965 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
966 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
967
968 // PHY Interrupt/Status Mask Register
969 #define PHY_MASK_REG 0x13 // Interrupt Mask
970 // Uses the same bit definitions as PHY_INT_REG
971
972
973 /*
974 * SMC91C96 ethernet config and status registers.
975 * These are in the "attribute" space.
976 */
977 #define ECOR 0x8000
978 #define ECOR_RESET 0x80
979 #define ECOR_LEVEL_IRQ 0x40
980 #define ECOR_WR_ATTRIB 0x04
981 #define ECOR_ENABLE 0x01
982
983 #define ECSR 0x8002
984 #define ECSR_IOIS8 0x20
985 #define ECSR_PWRDWN 0x04
986 #define ECSR_INT 0x02
987
988 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
989
990
991 /*
992 * Macros to abstract register access according to the data bus
993 * capabilities. Please use those and not the in/out primitives.
994 * Note: the following macros do *not* select the bank -- this must
995 * be done separately as needed in the main code. The SMC_REG() macro
996 * only uses the bank argument for debugging purposes (when enabled).
997 *
998 * Note: despite inline functions being safer, everything leading to this
999 * should preferably be macros to let BUG() display the line number in
1000 * the core source code since we're interested in the top call site
1001 * not in any inline function location.
1002 */
1003
1004 #if SMC_DEBUG > 0
1005 #define SMC_REG(lp, reg, bank) \
1006 ({ \
1007 int __b = SMC_CURRENT_BANK(lp); \
1008 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
1009 printk( "%s: bank reg screwed (0x%04x)\n", \
1010 CARDNAME, __b ); \
1011 BUG(); \
1012 } \
1013 reg<<SMC_IO_SHIFT; \
1014 })
1015 #else
1016 #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)
1017 #endif
1018
1019 /*
1020 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
1021 * aligned to a 32 bit boundary. I tell you that does exist!
1022 * Fortunately the affected register accesses can be easily worked around
1023 * since we can write zeroes to the preceeding 16 bits without adverse
1024 * effects and use a 32-bit access.
1025 *
1026 * Enforce it on any 32-bit capable setup for now.
1027 */
1028 #define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp)
1029
1030 #define SMC_GET_PN(lp) \
1031 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
1032 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
1033
1034 #define SMC_SET_PN(lp, x) \
1035 do { \
1036 if (SMC_MUST_ALIGN_WRITE(lp)) \
1037 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
1038 else if (SMC_8BIT(lp)) \
1039 SMC_outb(x, ioaddr, PN_REG(lp)); \
1040 else \
1041 SMC_outw(x, ioaddr, PN_REG(lp)); \
1042 } while (0)
1043
1044 #define SMC_GET_AR(lp) \
1045 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
1046 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
1047
1048 #define SMC_GET_TXFIFO(lp) \
1049 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
1050 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
1051
1052 #define SMC_GET_RXFIFO(lp) \
1053 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
1054 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
1055
1056 #define SMC_GET_INT(lp) \
1057 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
1058 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
1059
1060 #define SMC_ACK_INT(lp, x) \
1061 do { \
1062 if (SMC_8BIT(lp)) \
1063 SMC_outb(x, ioaddr, INT_REG(lp)); \
1064 else { \
1065 unsigned long __flags; \
1066 int __mask; \
1067 local_irq_save(__flags); \
1068 __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
1069 SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \
1070 local_irq_restore(__flags); \
1071 } \
1072 } while (0)
1073
1074 #define SMC_GET_INT_MASK(lp) \
1075 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
1076 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
1077
1078 #define SMC_SET_INT_MASK(lp, x) \
1079 do { \
1080 if (SMC_8BIT(lp)) \
1081 SMC_outb(x, ioaddr, IM_REG(lp)); \
1082 else \
1083 SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \
1084 } while (0)
1085
1086 #define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
1087
1088 #define SMC_SELECT_BANK(lp, x) \
1089 do { \
1090 if (SMC_MUST_ALIGN_WRITE(lp)) \
1091 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
1092 else \
1093 SMC_outw(x, ioaddr, BANK_SELECT); \
1094 } while (0)
1095
1096 #define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
1097
1098 #define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp))
1099
1100 #define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
1101
1102 #define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp))
1103
1104 #define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
1105
1106 #define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
1107
1108 #define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp))
1109
1110 #define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
1111
1112 #define SMC_GET_GP(lp) SMC_inw(ioaddr, GP_REG(lp))
1113
1114 #define SMC_SET_GP(lp, x) \
1115 do { \
1116 if (SMC_MUST_ALIGN_WRITE(lp)) \
1117 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1)); \
1118 else \
1119 SMC_outw(x, ioaddr, GP_REG(lp)); \
1120 } while (0)
1121
1122 #define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp))
1123
1124 #define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
1125
1126 #define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp))
1127
1128 #define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
1129
1130 #define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
1131
1132 #define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
1133
1134 #define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
1135
1136 #define SMC_SET_PTR(lp, x) \
1137 do { \
1138 if (SMC_MUST_ALIGN_WRITE(lp)) \
1139 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
1140 else \
1141 SMC_outw(x, ioaddr, PTR_REG(lp)); \
1142 } while (0)
1143
1144 #define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
1145
1146 #define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
1147
1148 #define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp))
1149
1150 #define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
1151
1152 #define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp))
1153
1154 #define SMC_SET_RPC(lp, x) \
1155 do { \
1156 if (SMC_MUST_ALIGN_WRITE(lp)) \
1157 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
1158 else \
1159 SMC_outw(x, ioaddr, RPC_REG(lp)); \
1160 } while (0)
1161
1162 #define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
1163
1164 #define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp))
1165
1166 #ifndef SMC_GET_MAC_ADDR
1167 #define SMC_GET_MAC_ADDR(lp, addr) \
1168 do { \
1169 unsigned int __v; \
1170 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
1171 addr[0] = __v; addr[1] = __v >> 8; \
1172 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
1173 addr[2] = __v; addr[3] = __v >> 8; \
1174 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
1175 addr[4] = __v; addr[5] = __v >> 8; \
1176 } while (0)
1177 #endif
1178
1179 #define SMC_SET_MAC_ADDR(lp, addr) \
1180 do { \
1181 SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1182 SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1183 SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1184 } while (0)
1185
1186 #define SMC_SET_MCAST(lp, x) \
1187 do { \
1188 const unsigned char *mt = (x); \
1189 SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1190 SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1191 SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1192 SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1193 } while (0)
1194
1195 #define SMC_PUT_PKT_HDR(lp, status, length) \
1196 do { \
1197 if (SMC_32BIT(lp)) \
1198 SMC_outl((status) | (length)<<16, ioaddr, \
1199 DATA_REG(lp)); \
1200 else { \
1201 SMC_outw(status, ioaddr, DATA_REG(lp)); \
1202 SMC_outw(length, ioaddr, DATA_REG(lp)); \
1203 } \
1204 } while (0)
1205
1206 #define SMC_GET_PKT_HDR(lp, status, length) \
1207 do { \
1208 if (SMC_32BIT(lp)) { \
1209 unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1210 (status) = __val & 0xffff; \
1211 (length) = __val >> 16; \
1212 } else { \
1213 (status) = SMC_inw(ioaddr, DATA_REG(lp)); \
1214 (length) = SMC_inw(ioaddr, DATA_REG(lp)); \
1215 } \
1216 } while (0)
1217
1218 #define SMC_PUSH_DATA(lp, p, l) \
1219 do { \
1220 if (SMC_32BIT(lp)) { \
1221 void *__ptr = (p); \
1222 int __len = (l); \
1223 void __iomem *__ioaddr = ioaddr; \
1224 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1225 __len -= 2; \
1226 SMC_outw(*(u16 *)__ptr, ioaddr, \
1227 DATA_REG(lp)); \
1228 __ptr += 2; \
1229 } \
1230 if (SMC_CAN_USE_DATACS && lp->datacs) \
1231 __ioaddr = lp->datacs; \
1232 SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1233 if (__len & 2) { \
1234 __ptr += (__len & ~3); \
1235 SMC_outw(*((u16 *)__ptr), ioaddr, \
1236 DATA_REG(lp)); \
1237 } \
1238 } else if (SMC_16BIT(lp)) \
1239 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1240 else if (SMC_8BIT(lp)) \
1241 SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
1242 } while (0)
1243
1244 #define SMC_PULL_DATA(lp, p, l) \
1245 do { \
1246 if (SMC_32BIT(lp)) { \
1247 void *__ptr = (p); \
1248 int __len = (l); \
1249 void __iomem *__ioaddr = ioaddr; \
1250 if ((unsigned long)__ptr & 2) { \
1251 /* \
1252 * We want 32bit alignment here. \
1253 * Since some buses perform a full \
1254 * 32bit fetch even for 16bit data \
1255 * we can't use SMC_inw() here. \
1256 * Back both source (on-chip) and \
1257 * destination pointers of 2 bytes. \
1258 * This is possible since the call to \
1259 * SMC_GET_PKT_HDR() already advanced \
1260 * the source pointer of 4 bytes, and \
1261 * the skb_reserve(skb, 2) advanced \
1262 * the destination pointer of 2 bytes. \
1263 */ \
1264 __ptr -= 2; \
1265 __len += 2; \
1266 SMC_SET_PTR(lp, \
1267 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1268 } \
1269 if (SMC_CAN_USE_DATACS && lp->datacs) \
1270 __ioaddr = lp->datacs; \
1271 __len += 2; \
1272 SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1273 } else if (SMC_16BIT(lp)) \
1274 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1275 else if (SMC_8BIT(lp)) \
1276 SMC_insb(ioaddr, DATA_REG(lp), p, l); \
1277 } while (0)
1278
1279 #endif /* _SMC91X_H_ */
AMDTP streaming driver for the Linux FireWire stack (Juju)