?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
firewire: core: check for 1394a compliant IRM, fix inaccessibility of Sony camcorder
[firewire-audio.git] / drivers / net / igb / igb_ethtool.c
blobf2ebf927e4bc0d2b6ab21285f9c54ebd0937829f
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* ethtool support for igb */
29
30 #include <linux/vmalloc.h>
31 #include <linux/netdevice.h>
32 #include <linux/pci.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/if_ether.h>
36 #include <linux/ethtool.h>
37 #include <linux/sched.h>
38 #include <linux/slab.h>
39
40 #include "igb.h"
41
42 struct igb_stats {
43 char stat_string[ETH_GSTRING_LEN];
44 int sizeof_stat;
45 int stat_offset;
46 };
47
48 #define IGB_STAT(_name, _stat) { \
49 .stat_string = _name, \
50 .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \
51 .stat_offset = offsetof(struct igb_adapter, _stat) \
52 }
53 static const struct igb_stats igb_gstrings_stats[] = {
54 IGB_STAT("rx_packets", stats.gprc),
55 IGB_STAT("tx_packets", stats.gptc),
56 IGB_STAT("rx_bytes", stats.gorc),
57 IGB_STAT("tx_bytes", stats.gotc),
58 IGB_STAT("rx_broadcast", stats.bprc),
59 IGB_STAT("tx_broadcast", stats.bptc),
60 IGB_STAT("rx_multicast", stats.mprc),
61 IGB_STAT("tx_multicast", stats.mptc),
62 IGB_STAT("multicast", stats.mprc),
63 IGB_STAT("collisions", stats.colc),
64 IGB_STAT("rx_crc_errors", stats.crcerrs),
65 IGB_STAT("rx_no_buffer_count", stats.rnbc),
66 IGB_STAT("rx_missed_errors", stats.mpc),
67 IGB_STAT("tx_aborted_errors", stats.ecol),
68 IGB_STAT("tx_carrier_errors", stats.tncrs),
69 IGB_STAT("tx_window_errors", stats.latecol),
70 IGB_STAT("tx_abort_late_coll", stats.latecol),
71 IGB_STAT("tx_deferred_ok", stats.dc),
72 IGB_STAT("tx_single_coll_ok", stats.scc),
73 IGB_STAT("tx_multi_coll_ok", stats.mcc),
74 IGB_STAT("tx_timeout_count", tx_timeout_count),
75 IGB_STAT("rx_long_length_errors", stats.roc),
76 IGB_STAT("rx_short_length_errors", stats.ruc),
77 IGB_STAT("rx_align_errors", stats.algnerrc),
78 IGB_STAT("tx_tcp_seg_good", stats.tsctc),
79 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc),
80 IGB_STAT("rx_flow_control_xon", stats.xonrxc),
81 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc),
82 IGB_STAT("tx_flow_control_xon", stats.xontxc),
83 IGB_STAT("tx_flow_control_xoff", stats.xofftxc),
84 IGB_STAT("rx_long_byte_count", stats.gorc),
85 IGB_STAT("tx_dma_out_of_sync", stats.doosync),
86 IGB_STAT("tx_smbus", stats.mgptc),
87 IGB_STAT("rx_smbus", stats.mgprc),
88 IGB_STAT("dropped_smbus", stats.mgpdc),
89 };
90
91 #define IGB_NETDEV_STAT(_net_stat) { \
92 .stat_string = __stringify(_net_stat), \
93 .sizeof_stat = FIELD_SIZEOF(struct net_device_stats, _net_stat), \
94 .stat_offset = offsetof(struct net_device_stats, _net_stat) \
95 }
96 static const struct igb_stats igb_gstrings_net_stats[] = {
97 IGB_NETDEV_STAT(rx_errors),
98 IGB_NETDEV_STAT(tx_errors),
99 IGB_NETDEV_STAT(tx_dropped),
100 IGB_NETDEV_STAT(rx_length_errors),
101 IGB_NETDEV_STAT(rx_over_errors),
102 IGB_NETDEV_STAT(rx_frame_errors),
103 IGB_NETDEV_STAT(rx_fifo_errors),
104 IGB_NETDEV_STAT(tx_fifo_errors),
105 IGB_NETDEV_STAT(tx_heartbeat_errors)
106 };
107
108 #define IGB_GLOBAL_STATS_LEN \
109 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats))
110 #define IGB_NETDEV_STATS_LEN \
111 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats))
112 #define IGB_RX_QUEUE_STATS_LEN \
113 (sizeof(struct igb_rx_queue_stats) / sizeof(u64))
114 #define IGB_TX_QUEUE_STATS_LEN \
115 (sizeof(struct igb_tx_queue_stats) / sizeof(u64))
116 #define IGB_QUEUE_STATS_LEN \
117 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
118 IGB_RX_QUEUE_STATS_LEN) + \
119 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
120 IGB_TX_QUEUE_STATS_LEN))
121 #define IGB_STATS_LEN \
122 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN)
123
124 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
125 "Register test (offline)", "Eeprom test (offline)",
126 "Interrupt test (offline)", "Loopback test (offline)",
127 "Link test (on/offline)"
128 };
129 #define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN)
130
131 static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
132 {
133 struct igb_adapter *adapter = netdev_priv(netdev);
134 struct e1000_hw *hw = &adapter->hw;
135 u32 status;
136
137 if (hw->phy.media_type == e1000_media_type_copper) {
138
139 ecmd->supported = (SUPPORTED_10baseT_Half |
140 SUPPORTED_10baseT_Full |
141 SUPPORTED_100baseT_Half |
142 SUPPORTED_100baseT_Full |
143 SUPPORTED_1000baseT_Full|
144 SUPPORTED_Autoneg |
145 SUPPORTED_TP);
146 ecmd->advertising = ADVERTISED_TP;
147
148 if (hw->mac.autoneg == 1) {
149 ecmd->advertising |= ADVERTISED_Autoneg;
150 /* the e1000 autoneg seems to match ethtool nicely */
151 ecmd->advertising |= hw->phy.autoneg_advertised;
152 }
153
154 ecmd->port = PORT_TP;
155 ecmd->phy_address = hw->phy.addr;
156 } else {
157 ecmd->supported = (SUPPORTED_1000baseT_Full |
158 SUPPORTED_FIBRE |
159 SUPPORTED_Autoneg);
160
161 ecmd->advertising = (ADVERTISED_1000baseT_Full |
162 ADVERTISED_FIBRE |
163 ADVERTISED_Autoneg);
164
165 ecmd->port = PORT_FIBRE;
166 }
167
168 ecmd->transceiver = XCVR_INTERNAL;
169
170 status = rd32(E1000_STATUS);
171
172 if (status & E1000_STATUS_LU) {
173
174 if ((status & E1000_STATUS_SPEED_1000) ||
175 hw->phy.media_type != e1000_media_type_copper)
176 ecmd->speed = SPEED_1000;
177 else if (status & E1000_STATUS_SPEED_100)
178 ecmd->speed = SPEED_100;
179 else
180 ecmd->speed = SPEED_10;
181
182 if ((status & E1000_STATUS_FD) ||
183 hw->phy.media_type != e1000_media_type_copper)
184 ecmd->duplex = DUPLEX_FULL;
185 else
186 ecmd->duplex = DUPLEX_HALF;
187 } else {
188 ecmd->speed = -1;
189 ecmd->duplex = -1;
190 }
191
192 ecmd->autoneg = hw->mac.autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
193 return 0;
194 }
195
196 static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
197 {
198 struct igb_adapter *adapter = netdev_priv(netdev);
199 struct e1000_hw *hw = &adapter->hw;
200
201 /* When SoL/IDER sessions are active, autoneg/speed/duplex
202 * cannot be changed */
203 if (igb_check_reset_block(hw)) {
204 dev_err(&adapter->pdev->dev, "Cannot change link "
205 "characteristics when SoL/IDER is active.\n");
206 return -EINVAL;
207 }
208
209 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
210 msleep(1);
211
212 if (ecmd->autoneg == AUTONEG_ENABLE) {
213 hw->mac.autoneg = 1;
214 hw->phy.autoneg_advertised = ecmd->advertising |
215 ADVERTISED_TP |
216 ADVERTISED_Autoneg;
217 ecmd->advertising = hw->phy.autoneg_advertised;
218 if (adapter->fc_autoneg)
219 hw->fc.requested_mode = e1000_fc_default;
220 } else {
221 if (igb_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
222 clear_bit(__IGB_RESETTING, &adapter->state);
223 return -EINVAL;
224 }
225 }
226
227 /* reset the link */
228 if (netif_running(adapter->netdev)) {
229 igb_down(adapter);
230 igb_up(adapter);
231 } else
232 igb_reset(adapter);
233
234 clear_bit(__IGB_RESETTING, &adapter->state);
235 return 0;
236 }
237
238 static u32 igb_get_link(struct net_device *netdev)
239 {
240 struct igb_adapter *adapter = netdev_priv(netdev);
241 struct e1000_mac_info *mac = &adapter->hw.mac;
242
243 /*
244 * If the link is not reported up to netdev, interrupts are disabled,
245 * and so the physical link state may have changed since we last
246 * looked. Set get_link_status to make sure that the true link
247 * state is interrogated, rather than pulling a cached and possibly
248 * stale link state from the driver.
249 */
250 if (!netif_carrier_ok(netdev))
251 mac->get_link_status = 1;
252
253 return igb_has_link(adapter);
254 }
255
256 static void igb_get_pauseparam(struct net_device *netdev,
257 struct ethtool_pauseparam *pause)
258 {
259 struct igb_adapter *adapter = netdev_priv(netdev);
260 struct e1000_hw *hw = &adapter->hw;
261
262 pause->autoneg =
263 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
264
265 if (hw->fc.current_mode == e1000_fc_rx_pause)
266 pause->rx_pause = 1;
267 else if (hw->fc.current_mode == e1000_fc_tx_pause)
268 pause->tx_pause = 1;
269 else if (hw->fc.current_mode == e1000_fc_full) {
270 pause->rx_pause = 1;
271 pause->tx_pause = 1;
272 }
273 }
274
275 static int igb_set_pauseparam(struct net_device *netdev,
276 struct ethtool_pauseparam *pause)
277 {
278 struct igb_adapter *adapter = netdev_priv(netdev);
279 struct e1000_hw *hw = &adapter->hw;
280 int retval = 0;
281
282 adapter->fc_autoneg = pause->autoneg;
283
284 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
285 msleep(1);
286
287 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
288 hw->fc.requested_mode = e1000_fc_default;
289 if (netif_running(adapter->netdev)) {
290 igb_down(adapter);
291 igb_up(adapter);
292 } else {
293 igb_reset(adapter);
294 }
295 } else {
296 if (pause->rx_pause && pause->tx_pause)
297 hw->fc.requested_mode = e1000_fc_full;
298 else if (pause->rx_pause && !pause->tx_pause)
299 hw->fc.requested_mode = e1000_fc_rx_pause;
300 else if (!pause->rx_pause && pause->tx_pause)
301 hw->fc.requested_mode = e1000_fc_tx_pause;
302 else if (!pause->rx_pause && !pause->tx_pause)
303 hw->fc.requested_mode = e1000_fc_none;
304
305 hw->fc.current_mode = hw->fc.requested_mode;
306
307 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
308 igb_force_mac_fc(hw) : igb_setup_link(hw));
309 }
310
311 clear_bit(__IGB_RESETTING, &adapter->state);
312 return retval;
313 }
314
315 static u32 igb_get_rx_csum(struct net_device *netdev)
316 {
317 struct igb_adapter *adapter = netdev_priv(netdev);
318 return !!(adapter->rx_ring[0]->flags & IGB_RING_FLAG_RX_CSUM);
319 }
320
321 static int igb_set_rx_csum(struct net_device *netdev, u32 data)
322 {
323 struct igb_adapter *adapter = netdev_priv(netdev);
324 int i;
325
326 for (i = 0; i < adapter->num_rx_queues; i++) {
327 if (data)
328 adapter->rx_ring[i]->flags |= IGB_RING_FLAG_RX_CSUM;
329 else
330 adapter->rx_ring[i]->flags &= ~IGB_RING_FLAG_RX_CSUM;
331 }
332
333 return 0;
334 }
335
336 static u32 igb_get_tx_csum(struct net_device *netdev)
337 {
338 return (netdev->features & NETIF_F_IP_CSUM) != 0;
339 }
340
341 static int igb_set_tx_csum(struct net_device *netdev, u32 data)
342 {
343 struct igb_adapter *adapter = netdev_priv(netdev);
344
345 if (data) {
346 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
347 if (adapter->hw.mac.type >= e1000_82576)
348 netdev->features |= NETIF_F_SCTP_CSUM;
349 } else {
350 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
351 NETIF_F_SCTP_CSUM);
352 }
353
354 return 0;
355 }
356
357 static int igb_set_tso(struct net_device *netdev, u32 data)
358 {
359 struct igb_adapter *adapter = netdev_priv(netdev);
360
361 if (data) {
362 netdev->features |= NETIF_F_TSO;
363 netdev->features |= NETIF_F_TSO6;
364 } else {
365 netdev->features &= ~NETIF_F_TSO;
366 netdev->features &= ~NETIF_F_TSO6;
367 }
368
369 dev_info(&adapter->pdev->dev, "TSO is %s\n",
370 data ? "Enabled" : "Disabled");
371 return 0;
372 }
373
374 static u32 igb_get_msglevel(struct net_device *netdev)
375 {
376 struct igb_adapter *adapter = netdev_priv(netdev);
377 return adapter->msg_enable;
378 }
379
380 static void igb_set_msglevel(struct net_device *netdev, u32 data)
381 {
382 struct igb_adapter *adapter = netdev_priv(netdev);
383 adapter->msg_enable = data;
384 }
385
386 static int igb_get_regs_len(struct net_device *netdev)
387 {
388 #define IGB_REGS_LEN 551
389 return IGB_REGS_LEN * sizeof(u32);
390 }
391
392 static void igb_get_regs(struct net_device *netdev,
393 struct ethtool_regs *regs, void *p)
394 {
395 struct igb_adapter *adapter = netdev_priv(netdev);
396 struct e1000_hw *hw = &adapter->hw;
397 u32 *regs_buff = p;
398 u8 i;
399
400 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
401
402 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
403
404 /* General Registers */
405 regs_buff[0] = rd32(E1000_CTRL);
406 regs_buff[1] = rd32(E1000_STATUS);
407 regs_buff[2] = rd32(E1000_CTRL_EXT);
408 regs_buff[3] = rd32(E1000_MDIC);
409 regs_buff[4] = rd32(E1000_SCTL);
410 regs_buff[5] = rd32(E1000_CONNSW);
411 regs_buff[6] = rd32(E1000_VET);
412 regs_buff[7] = rd32(E1000_LEDCTL);
413 regs_buff[8] = rd32(E1000_PBA);
414 regs_buff[9] = rd32(E1000_PBS);
415 regs_buff[10] = rd32(E1000_FRTIMER);
416 regs_buff[11] = rd32(E1000_TCPTIMER);
417
418 /* NVM Register */
419 regs_buff[12] = rd32(E1000_EECD);
420
421 /* Interrupt */
422 /* Reading EICS for EICR because they read the
423 * same but EICS does not clear on read */
424 regs_buff[13] = rd32(E1000_EICS);
425 regs_buff[14] = rd32(E1000_EICS);
426 regs_buff[15] = rd32(E1000_EIMS);
427 regs_buff[16] = rd32(E1000_EIMC);
428 regs_buff[17] = rd32(E1000_EIAC);
429 regs_buff[18] = rd32(E1000_EIAM);
430 /* Reading ICS for ICR because they read the
431 * same but ICS does not clear on read */
432 regs_buff[19] = rd32(E1000_ICS);
433 regs_buff[20] = rd32(E1000_ICS);
434 regs_buff[21] = rd32(E1000_IMS);
435 regs_buff[22] = rd32(E1000_IMC);
436 regs_buff[23] = rd32(E1000_IAC);
437 regs_buff[24] = rd32(E1000_IAM);
438 regs_buff[25] = rd32(E1000_IMIRVP);
439
440 /* Flow Control */
441 regs_buff[26] = rd32(E1000_FCAL);
442 regs_buff[27] = rd32(E1000_FCAH);
443 regs_buff[28] = rd32(E1000_FCTTV);
444 regs_buff[29] = rd32(E1000_FCRTL);
445 regs_buff[30] = rd32(E1000_FCRTH);
446 regs_buff[31] = rd32(E1000_FCRTV);
447
448 /* Receive */
449 regs_buff[32] = rd32(E1000_RCTL);
450 regs_buff[33] = rd32(E1000_RXCSUM);
451 regs_buff[34] = rd32(E1000_RLPML);
452 regs_buff[35] = rd32(E1000_RFCTL);
453 regs_buff[36] = rd32(E1000_MRQC);
454 regs_buff[37] = rd32(E1000_VT_CTL);
455
456 /* Transmit */
457 regs_buff[38] = rd32(E1000_TCTL);
458 regs_buff[39] = rd32(E1000_TCTL_EXT);
459 regs_buff[40] = rd32(E1000_TIPG);
460 regs_buff[41] = rd32(E1000_DTXCTL);
461
462 /* Wake Up */
463 regs_buff[42] = rd32(E1000_WUC);
464 regs_buff[43] = rd32(E1000_WUFC);
465 regs_buff[44] = rd32(E1000_WUS);
466 regs_buff[45] = rd32(E1000_IPAV);
467 regs_buff[46] = rd32(E1000_WUPL);
468
469 /* MAC */
470 regs_buff[47] = rd32(E1000_PCS_CFG0);
471 regs_buff[48] = rd32(E1000_PCS_LCTL);
472 regs_buff[49] = rd32(E1000_PCS_LSTAT);
473 regs_buff[50] = rd32(E1000_PCS_ANADV);
474 regs_buff[51] = rd32(E1000_PCS_LPAB);
475 regs_buff[52] = rd32(E1000_PCS_NPTX);
476 regs_buff[53] = rd32(E1000_PCS_LPABNP);
477
478 /* Statistics */
479 regs_buff[54] = adapter->stats.crcerrs;
480 regs_buff[55] = adapter->stats.algnerrc;
481 regs_buff[56] = adapter->stats.symerrs;
482 regs_buff[57] = adapter->stats.rxerrc;
483 regs_buff[58] = adapter->stats.mpc;
484 regs_buff[59] = adapter->stats.scc;
485 regs_buff[60] = adapter->stats.ecol;
486 regs_buff[61] = adapter->stats.mcc;
487 regs_buff[62] = adapter->stats.latecol;
488 regs_buff[63] = adapter->stats.colc;
489 regs_buff[64] = adapter->stats.dc;
490 regs_buff[65] = adapter->stats.tncrs;
491 regs_buff[66] = adapter->stats.sec;
492 regs_buff[67] = adapter->stats.htdpmc;
493 regs_buff[68] = adapter->stats.rlec;
494 regs_buff[69] = adapter->stats.xonrxc;
495 regs_buff[70] = adapter->stats.xontxc;
496 regs_buff[71] = adapter->stats.xoffrxc;
497 regs_buff[72] = adapter->stats.xofftxc;
498 regs_buff[73] = adapter->stats.fcruc;
499 regs_buff[74] = adapter->stats.prc64;
500 regs_buff[75] = adapter->stats.prc127;
501 regs_buff[76] = adapter->stats.prc255;
502 regs_buff[77] = adapter->stats.prc511;
503 regs_buff[78] = adapter->stats.prc1023;
504 regs_buff[79] = adapter->stats.prc1522;
505 regs_buff[80] = adapter->stats.gprc;
506 regs_buff[81] = adapter->stats.bprc;
507 regs_buff[82] = adapter->stats.mprc;
508 regs_buff[83] = adapter->stats.gptc;
509 regs_buff[84] = adapter->stats.gorc;
510 regs_buff[86] = adapter->stats.gotc;
511 regs_buff[88] = adapter->stats.rnbc;
512 regs_buff[89] = adapter->stats.ruc;
513 regs_buff[90] = adapter->stats.rfc;
514 regs_buff[91] = adapter->stats.roc;
515 regs_buff[92] = adapter->stats.rjc;
516 regs_buff[93] = adapter->stats.mgprc;
517 regs_buff[94] = adapter->stats.mgpdc;
518 regs_buff[95] = adapter->stats.mgptc;
519 regs_buff[96] = adapter->stats.tor;
520 regs_buff[98] = adapter->stats.tot;
521 regs_buff[100] = adapter->stats.tpr;
522 regs_buff[101] = adapter->stats.tpt;
523 regs_buff[102] = adapter->stats.ptc64;
524 regs_buff[103] = adapter->stats.ptc127;
525 regs_buff[104] = adapter->stats.ptc255;
526 regs_buff[105] = adapter->stats.ptc511;
527 regs_buff[106] = adapter->stats.ptc1023;
528 regs_buff[107] = adapter->stats.ptc1522;
529 regs_buff[108] = adapter->stats.mptc;
530 regs_buff[109] = adapter->stats.bptc;
531 regs_buff[110] = adapter->stats.tsctc;
532 regs_buff[111] = adapter->stats.iac;
533 regs_buff[112] = adapter->stats.rpthc;
534 regs_buff[113] = adapter->stats.hgptc;
535 regs_buff[114] = adapter->stats.hgorc;
536 regs_buff[116] = adapter->stats.hgotc;
537 regs_buff[118] = adapter->stats.lenerrs;
538 regs_buff[119] = adapter->stats.scvpc;
539 regs_buff[120] = adapter->stats.hrmpc;
540
541 for (i = 0; i < 4; i++)
542 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
543 for (i = 0; i < 4; i++)
544 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i));
545 for (i = 0; i < 4; i++)
546 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
547 for (i = 0; i < 4; i++)
548 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
549 for (i = 0; i < 4; i++)
550 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
551 for (i = 0; i < 4; i++)
552 regs_buff[141 + i] = rd32(E1000_RDH(i));
553 for (i = 0; i < 4; i++)
554 regs_buff[145 + i] = rd32(E1000_RDT(i));
555 for (i = 0; i < 4; i++)
556 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
557
558 for (i = 0; i < 10; i++)
559 regs_buff[153 + i] = rd32(E1000_EITR(i));
560 for (i = 0; i < 8; i++)
561 regs_buff[163 + i] = rd32(E1000_IMIR(i));
562 for (i = 0; i < 8; i++)
563 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
564 for (i = 0; i < 16; i++)
565 regs_buff[179 + i] = rd32(E1000_RAL(i));
566 for (i = 0; i < 16; i++)
567 regs_buff[195 + i] = rd32(E1000_RAH(i));
568
569 for (i = 0; i < 4; i++)
570 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
571 for (i = 0; i < 4; i++)
572 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
573 for (i = 0; i < 4; i++)
574 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
575 for (i = 0; i < 4; i++)
576 regs_buff[223 + i] = rd32(E1000_TDH(i));
577 for (i = 0; i < 4; i++)
578 regs_buff[227 + i] = rd32(E1000_TDT(i));
579 for (i = 0; i < 4; i++)
580 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
581 for (i = 0; i < 4; i++)
582 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
583 for (i = 0; i < 4; i++)
584 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
585 for (i = 0; i < 4; i++)
586 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
587
588 for (i = 0; i < 4; i++)
589 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
590 for (i = 0; i < 4; i++)
591 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
592 for (i = 0; i < 32; i++)
593 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
594 for (i = 0; i < 128; i++)
595 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
596 for (i = 0; i < 128; i++)
597 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
598 for (i = 0; i < 4; i++)
599 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
600
601 regs_buff[547] = rd32(E1000_TDFH);
602 regs_buff[548] = rd32(E1000_TDFT);
603 regs_buff[549] = rd32(E1000_TDFHS);
604 regs_buff[550] = rd32(E1000_TDFPC);
605
606 }
607
608 static int igb_get_eeprom_len(struct net_device *netdev)
609 {
610 struct igb_adapter *adapter = netdev_priv(netdev);
611 return adapter->hw.nvm.word_size * 2;
612 }
613
614 static int igb_get_eeprom(struct net_device *netdev,
615 struct ethtool_eeprom *eeprom, u8 *bytes)
616 {
617 struct igb_adapter *adapter = netdev_priv(netdev);
618 struct e1000_hw *hw = &adapter->hw;
619 u16 *eeprom_buff;
620 int first_word, last_word;
621 int ret_val = 0;
622 u16 i;
623
624 if (eeprom->len == 0)
625 return -EINVAL;
626
627 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
628
629 first_word = eeprom->offset >> 1;
630 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
631
632 eeprom_buff = kmalloc(sizeof(u16) *
633 (last_word - first_word + 1), GFP_KERNEL);
634 if (!eeprom_buff)
635 return -ENOMEM;
636
637 if (hw->nvm.type == e1000_nvm_eeprom_spi)
638 ret_val = hw->nvm.ops.read(hw, first_word,
639 last_word - first_word + 1,
640 eeprom_buff);
641 else {
642 for (i = 0; i < last_word - first_word + 1; i++) {
643 ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
644 &eeprom_buff[i]);
645 if (ret_val)
646 break;
647 }
648 }
649
650 /* Device's eeprom is always little-endian, word addressable */
651 for (i = 0; i < last_word - first_word + 1; i++)
652 le16_to_cpus(&eeprom_buff[i]);
653
654 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
655 eeprom->len);
656 kfree(eeprom_buff);
657
658 return ret_val;
659 }
660
661 static int igb_set_eeprom(struct net_device *netdev,
662 struct ethtool_eeprom *eeprom, u8 *bytes)
663 {
664 struct igb_adapter *adapter = netdev_priv(netdev);
665 struct e1000_hw *hw = &adapter->hw;
666 u16 *eeprom_buff;
667 void *ptr;
668 int max_len, first_word, last_word, ret_val = 0;
669 u16 i;
670
671 if (eeprom->len == 0)
672 return -EOPNOTSUPP;
673
674 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
675 return -EFAULT;
676
677 max_len = hw->nvm.word_size * 2;
678
679 first_word = eeprom->offset >> 1;
680 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
681 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
682 if (!eeprom_buff)
683 return -ENOMEM;
684
685 ptr = (void *)eeprom_buff;
686
687 if (eeprom->offset & 1) {
688 /* need read/modify/write of first changed EEPROM word */
689 /* only the second byte of the word is being modified */
690 ret_val = hw->nvm.ops.read(hw, first_word, 1,
691 &eeprom_buff[0]);
692 ptr++;
693 }
694 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
695 /* need read/modify/write of last changed EEPROM word */
696 /* only the first byte of the word is being modified */
697 ret_val = hw->nvm.ops.read(hw, last_word, 1,
698 &eeprom_buff[last_word - first_word]);
699 }
700
701 /* Device's eeprom is always little-endian, word addressable */
702 for (i = 0; i < last_word - first_word + 1; i++)
703 le16_to_cpus(&eeprom_buff[i]);
704
705 memcpy(ptr, bytes, eeprom->len);
706
707 for (i = 0; i < last_word - first_word + 1; i++)
708 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
709
710 ret_val = hw->nvm.ops.write(hw, first_word,
711 last_word - first_word + 1, eeprom_buff);
712
713 /* Update the checksum over the first part of the EEPROM if needed
714 * and flush shadow RAM for 82573 controllers */
715 if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
716 igb_update_nvm_checksum(hw);
717
718 kfree(eeprom_buff);
719 return ret_val;
720 }
721
722 static void igb_get_drvinfo(struct net_device *netdev,
723 struct ethtool_drvinfo *drvinfo)
724 {
725 struct igb_adapter *adapter = netdev_priv(netdev);
726 char firmware_version[32];
727 u16 eeprom_data;
728
729 strncpy(drvinfo->driver, igb_driver_name, 32);
730 strncpy(drvinfo->version, igb_driver_version, 32);
731
732 /* EEPROM image version # is reported as firmware version # for
733 * 82575 controllers */
734 adapter->hw.nvm.ops.read(&adapter->hw, 5, 1, &eeprom_data);
735 sprintf(firmware_version, "%d.%d-%d",
736 (eeprom_data & 0xF000) >> 12,
737 (eeprom_data & 0x0FF0) >> 4,
738 eeprom_data & 0x000F);
739
740 strncpy(drvinfo->fw_version, firmware_version, 32);
741 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
742 drvinfo->n_stats = IGB_STATS_LEN;
743 drvinfo->testinfo_len = IGB_TEST_LEN;
744 drvinfo->regdump_len = igb_get_regs_len(netdev);
745 drvinfo->eedump_len = igb_get_eeprom_len(netdev);
746 }
747
748 static void igb_get_ringparam(struct net_device *netdev,
749 struct ethtool_ringparam *ring)
750 {
751 struct igb_adapter *adapter = netdev_priv(netdev);
752
753 ring->rx_max_pending = IGB_MAX_RXD;
754 ring->tx_max_pending = IGB_MAX_TXD;
755 ring->rx_mini_max_pending = 0;
756 ring->rx_jumbo_max_pending = 0;
757 ring->rx_pending = adapter->rx_ring_count;
758 ring->tx_pending = adapter->tx_ring_count;
759 ring->rx_mini_pending = 0;
760 ring->rx_jumbo_pending = 0;
761 }
762
763 static int igb_set_ringparam(struct net_device *netdev,
764 struct ethtool_ringparam *ring)
765 {
766 struct igb_adapter *adapter = netdev_priv(netdev);
767 struct igb_ring *temp_ring;
768 int i, err = 0;
769 u16 new_rx_count, new_tx_count;
770
771 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
772 return -EINVAL;
773
774 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD);
775 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD);
776 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
777
778 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD);
779 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD);
780 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
781
782 if ((new_tx_count == adapter->tx_ring_count) &&
783 (new_rx_count == adapter->rx_ring_count)) {
784 /* nothing to do */
785 return 0;
786 }
787
788 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
789 msleep(1);
790
791 if (!netif_running(adapter->netdev)) {
792 for (i = 0; i < adapter->num_tx_queues; i++)
793 adapter->tx_ring[i]->count = new_tx_count;
794 for (i = 0; i < adapter->num_rx_queues; i++)
795 adapter->rx_ring[i]->count = new_rx_count;
796 adapter->tx_ring_count = new_tx_count;
797 adapter->rx_ring_count = new_rx_count;
798 goto clear_reset;
799 }
800
801 if (adapter->num_tx_queues > adapter->num_rx_queues)
802 temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring));
803 else
804 temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring));
805
806 if (!temp_ring) {
807 err = -ENOMEM;
808 goto clear_reset;
809 }
810
811 igb_down(adapter);
812
813 /*
814 * We can't just free everything and then setup again,
815 * because the ISRs in MSI-X mode get passed pointers
816 * to the tx and rx ring structs.
817 */
818 if (new_tx_count != adapter->tx_ring_count) {
819 for (i = 0; i < adapter->num_tx_queues; i++) {
820 memcpy(&temp_ring[i], adapter->tx_ring[i],
821 sizeof(struct igb_ring));
822
823 temp_ring[i].count = new_tx_count;
824 err = igb_setup_tx_resources(&temp_ring[i]);
825 if (err) {
826 while (i) {
827 i--;
828 igb_free_tx_resources(&temp_ring[i]);
829 }
830 goto err_setup;
831 }
832 }
833
834 for (i = 0; i < adapter->num_tx_queues; i++) {
835 igb_free_tx_resources(adapter->tx_ring[i]);
836
837 memcpy(adapter->tx_ring[i], &temp_ring[i],
838 sizeof(struct igb_ring));
839 }
840
841 adapter->tx_ring_count = new_tx_count;
842 }
843
844 if (new_rx_count != adapter->rx_ring_count) {
845 for (i = 0; i < adapter->num_rx_queues; i++) {
846 memcpy(&temp_ring[i], adapter->rx_ring[i],
847 sizeof(struct igb_ring));
848
849 temp_ring[i].count = new_rx_count;
850 err = igb_setup_rx_resources(&temp_ring[i]);
851 if (err) {
852 while (i) {
853 i--;
854 igb_free_rx_resources(&temp_ring[i]);
855 }
856 goto err_setup;
857 }
858
859 }
860
861 for (i = 0; i < adapter->num_rx_queues; i++) {
862 igb_free_rx_resources(adapter->rx_ring[i]);
863
864 memcpy(adapter->rx_ring[i], &temp_ring[i],
865 sizeof(struct igb_ring));
866 }
867
868 adapter->rx_ring_count = new_rx_count;
869 }
870 err_setup:
871 igb_up(adapter);
872 vfree(temp_ring);
873 clear_reset:
874 clear_bit(__IGB_RESETTING, &adapter->state);
875 return err;
876 }
877
878 /* ethtool register test data */
879 struct igb_reg_test {
880 u16 reg;
881 u16 reg_offset;
882 u16 array_len;
883 u16 test_type;
884 u32 mask;
885 u32 write;
886 };
887
888 /* In the hardware, registers are laid out either singly, in arrays
889 * spaced 0x100 bytes apart, or in contiguous tables. We assume
890 * most tests take place on arrays or single registers (handled
891 * as a single-element array) and special-case the tables.
892 * Table tests are always pattern tests.
893 *
894 * We also make provision for some required setup steps by specifying
895 * registers to be written without any read-back testing.
896 */
897
898 #define PATTERN_TEST 1
899 #define SET_READ_TEST 2
900 #define WRITE_NO_TEST 3
901 #define TABLE32_TEST 4
902 #define TABLE64_TEST_LO 5
903 #define TABLE64_TEST_HI 6
904
905 /* i350 reg test */
906 static struct igb_reg_test reg_test_i350[] = {
907 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
908 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
909 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
910 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 },
911 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
912 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
913 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
914 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
915 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
916 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
917 /* RDH is read-only for i350, only test RDT. */
918 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
919 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
920 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
921 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
922 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
923 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
924 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
925 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
926 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
927 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
928 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
929 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
930 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
931 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
932 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
933 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
934 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
935 { E1000_RA, 0, 16, TABLE64_TEST_LO,
936 0xFFFFFFFF, 0xFFFFFFFF },
937 { E1000_RA, 0, 16, TABLE64_TEST_HI,
938 0xC3FFFFFF, 0xFFFFFFFF },
939 { E1000_RA2, 0, 16, TABLE64_TEST_LO,
940 0xFFFFFFFF, 0xFFFFFFFF },
941 { E1000_RA2, 0, 16, TABLE64_TEST_HI,
942 0xC3FFFFFF, 0xFFFFFFFF },
943 { E1000_MTA, 0, 128, TABLE32_TEST,
944 0xFFFFFFFF, 0xFFFFFFFF },
945 { 0, 0, 0, 0 }
946 };
947
948 /* 82580 reg test */
949 static struct igb_reg_test reg_test_82580[] = {
950 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
951 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
952 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
953 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
954 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
955 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
956 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
957 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
958 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
959 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
960 /* RDH is read-only for 82580, only test RDT. */
961 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
962 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
963 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
964 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
965 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
966 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
967 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
968 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
969 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
970 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
971 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
972 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
973 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
974 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
975 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
976 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
977 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
978 { E1000_RA, 0, 16, TABLE64_TEST_LO,
979 0xFFFFFFFF, 0xFFFFFFFF },
980 { E1000_RA, 0, 16, TABLE64_TEST_HI,
981 0x83FFFFFF, 0xFFFFFFFF },
982 { E1000_RA2, 0, 8, TABLE64_TEST_LO,
983 0xFFFFFFFF, 0xFFFFFFFF },
984 { E1000_RA2, 0, 8, TABLE64_TEST_HI,
985 0x83FFFFFF, 0xFFFFFFFF },
986 { E1000_MTA, 0, 128, TABLE32_TEST,
987 0xFFFFFFFF, 0xFFFFFFFF },
988 { 0, 0, 0, 0 }
989 };
990
991 /* 82576 reg test */
992 static struct igb_reg_test reg_test_82576[] = {
993 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
994 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
995 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
996 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
997 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
998 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
999 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1000 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1001 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1002 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1003 /* Enable all RX queues before testing. */
1004 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
1005 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
1006 /* RDH is read-only for 82576, only test RDT. */
1007 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1008 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1009 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1010 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 },
1011 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1012 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1013 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1014 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1015 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1016 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1017 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1018 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1019 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1020 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1021 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1022 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1023 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1024 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1025 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1026 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1027 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1028 { E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1029 { 0, 0, 0, 0 }
1030 };
1031
1032 /* 82575 register test */
1033 static struct igb_reg_test reg_test_82575[] = {
1034 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1035 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1036 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1037 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1038 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1039 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1040 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1041 /* Enable all four RX queues before testing. */
1042 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
1043 /* RDH is read-only for 82575, only test RDT. */
1044 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1045 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1046 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1047 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1048 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1049 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1050 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1051 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1052 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1053 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
1054 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
1055 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1056 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
1057 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1058 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
1059 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1060 { 0, 0, 0, 0 }
1061 };
1062
1063 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
1064 int reg, u32 mask, u32 write)
1065 {
1066 struct e1000_hw *hw = &adapter->hw;
1067 u32 pat, val;
1068 static const u32 _test[] =
1069 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1070 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
1071 wr32(reg, (_test[pat] & write));
1072 val = rd32(reg);
1073 if (val != (_test[pat] & write & mask)) {
1074 dev_err(&adapter->pdev->dev, "pattern test reg %04X "
1075 "failed: got 0x%08X expected 0x%08X\n",
1076 reg, val, (_test[pat] & write & mask));
1077 *data = reg;
1078 return 1;
1079 }
1080 }
1081
1082 return 0;
1083 }
1084
1085 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
1086 int reg, u32 mask, u32 write)
1087 {
1088 struct e1000_hw *hw = &adapter->hw;
1089 u32 val;
1090 wr32(reg, write & mask);
1091 val = rd32(reg);
1092 if ((write & mask) != (val & mask)) {
1093 dev_err(&adapter->pdev->dev, "set/check reg %04X test failed:"
1094 " got 0x%08X expected 0x%08X\n", reg,
1095 (val & mask), (write & mask));
1096 *data = reg;
1097 return 1;
1098 }
1099
1100 return 0;
1101 }
1102
1103 #define REG_PATTERN_TEST(reg, mask, write) \
1104 do { \
1105 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1106 return 1; \
1107 } while (0)
1108
1109 #define REG_SET_AND_CHECK(reg, mask, write) \
1110 do { \
1111 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1112 return 1; \
1113 } while (0)
1114
1115 static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1116 {
1117 struct e1000_hw *hw = &adapter->hw;
1118 struct igb_reg_test *test;
1119 u32 value, before, after;
1120 u32 i, toggle;
1121
1122 switch (adapter->hw.mac.type) {
1123 case e1000_i350:
1124 test = reg_test_i350;
1125 toggle = 0x7FEFF3FF;
1126 break;
1127 case e1000_82580:
1128 test = reg_test_82580;
1129 toggle = 0x7FEFF3FF;
1130 break;
1131 case e1000_82576:
1132 test = reg_test_82576;
1133 toggle = 0x7FFFF3FF;
1134 break;
1135 default:
1136 test = reg_test_82575;
1137 toggle = 0x7FFFF3FF;
1138 break;
1139 }
1140
1141 /* Because the status register is such a special case,
1142 * we handle it separately from the rest of the register
1143 * tests. Some bits are read-only, some toggle, and some
1144 * are writable on newer MACs.
1145 */
1146 before = rd32(E1000_STATUS);
1147 value = (rd32(E1000_STATUS) & toggle);
1148 wr32(E1000_STATUS, toggle);
1149 after = rd32(E1000_STATUS) & toggle;
1150 if (value != after) {
1151 dev_err(&adapter->pdev->dev, "failed STATUS register test "
1152 "got: 0x%08X expected: 0x%08X\n", after, value);
1153 *data = 1;
1154 return 1;
1155 }
1156 /* restore previous status */
1157 wr32(E1000_STATUS, before);
1158
1159 /* Perform the remainder of the register test, looping through
1160 * the test table until we either fail or reach the null entry.
1161 */
1162 while (test->reg) {
1163 for (i = 0; i < test->array_len; i++) {
1164 switch (test->test_type) {
1165 case PATTERN_TEST:
1166 REG_PATTERN_TEST(test->reg +
1167 (i * test->reg_offset),
1168 test->mask,
1169 test->write);
1170 break;
1171 case SET_READ_TEST:
1172 REG_SET_AND_CHECK(test->reg +
1173 (i * test->reg_offset),
1174 test->mask,
1175 test->write);
1176 break;
1177 case WRITE_NO_TEST:
1178 writel(test->write,
1179 (adapter->hw.hw_addr + test->reg)
1180 + (i * test->reg_offset));
1181 break;
1182 case TABLE32_TEST:
1183 REG_PATTERN_TEST(test->reg + (i * 4),
1184 test->mask,
1185 test->write);
1186 break;
1187 case TABLE64_TEST_LO:
1188 REG_PATTERN_TEST(test->reg + (i * 8),
1189 test->mask,
1190 test->write);
1191 break;
1192 case TABLE64_TEST_HI:
1193 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1194 test->mask,
1195 test->write);
1196 break;
1197 }
1198 }
1199 test++;
1200 }
1201
1202 *data = 0;
1203 return 0;
1204 }
1205
1206 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1207 {
1208 u16 temp;
1209 u16 checksum = 0;
1210 u16 i;
1211
1212 *data = 0;
1213 /* Read and add up the contents of the EEPROM */
1214 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1215 if ((adapter->hw.nvm.ops.read(&adapter->hw, i, 1, &temp)) < 0) {
1216 *data = 1;
1217 break;
1218 }
1219 checksum += temp;
1220 }
1221
1222 /* If Checksum is not Correct return error else test passed */
1223 if ((checksum != (u16) NVM_SUM) && !(*data))
1224 *data = 2;
1225
1226 return *data;
1227 }
1228
1229 static irqreturn_t igb_test_intr(int irq, void *data)
1230 {
1231 struct igb_adapter *adapter = (struct igb_adapter *) data;
1232 struct e1000_hw *hw = &adapter->hw;
1233
1234 adapter->test_icr |= rd32(E1000_ICR);
1235
1236 return IRQ_HANDLED;
1237 }
1238
1239 static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1240 {
1241 struct e1000_hw *hw = &adapter->hw;
1242 struct net_device *netdev = adapter->netdev;
1243 u32 mask, ics_mask, i = 0, shared_int = true;
1244 u32 irq = adapter->pdev->irq;
1245
1246 *data = 0;
1247
1248 /* Hook up test interrupt handler just for this test */
1249 if (adapter->msix_entries) {
1250 if (request_irq(adapter->msix_entries[0].vector,
1251 igb_test_intr, 0, netdev->name, adapter)) {
1252 *data = 1;
1253 return -1;
1254 }
1255 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
1256 shared_int = false;
1257 if (request_irq(irq,
1258 igb_test_intr, 0, netdev->name, adapter)) {
1259 *data = 1;
1260 return -1;
1261 }
1262 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED,
1263 netdev->name, adapter)) {
1264 shared_int = false;
1265 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED,
1266 netdev->name, adapter)) {
1267 *data = 1;
1268 return -1;
1269 }
1270 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1271 (shared_int ? "shared" : "unshared"));
1272
1273 /* Disable all the interrupts */
1274 wr32(E1000_IMC, ~0);
1275 msleep(10);
1276
1277 /* Define all writable bits for ICS */
1278 switch (hw->mac.type) {
1279 case e1000_82575:
1280 ics_mask = 0x37F47EDD;
1281 break;
1282 case e1000_82576:
1283 ics_mask = 0x77D4FBFD;
1284 break;
1285 case e1000_82580:
1286 ics_mask = 0x77DCFED5;
1287 break;
1288 case e1000_i350:
1289 ics_mask = 0x77DCFED5;
1290 break;
1291 default:
1292 ics_mask = 0x7FFFFFFF;
1293 break;
1294 }
1295
1296 /* Test each interrupt */
1297 for (; i < 31; i++) {
1298 /* Interrupt to test */
1299 mask = 1 << i;
1300
1301 if (!(mask & ics_mask))
1302 continue;
1303
1304 if (!shared_int) {
1305 /* Disable the interrupt to be reported in
1306 * the cause register and then force the same
1307 * interrupt and see if one gets posted. If
1308 * an interrupt was posted to the bus, the
1309 * test failed.
1310 */
1311 adapter->test_icr = 0;
1312
1313 /* Flush any pending interrupts */
1314 wr32(E1000_ICR, ~0);
1315
1316 wr32(E1000_IMC, mask);
1317 wr32(E1000_ICS, mask);
1318 msleep(10);
1319
1320 if (adapter->test_icr & mask) {
1321 *data = 3;
1322 break;
1323 }
1324 }
1325
1326 /* Enable the interrupt to be reported in
1327 * the cause register and then force the same
1328 * interrupt and see if one gets posted. If
1329 * an interrupt was not posted to the bus, the
1330 * test failed.
1331 */
1332 adapter->test_icr = 0;
1333
1334 /* Flush any pending interrupts */
1335 wr32(E1000_ICR, ~0);
1336
1337 wr32(E1000_IMS, mask);
1338 wr32(E1000_ICS, mask);
1339 msleep(10);
1340
1341 if (!(adapter->test_icr & mask)) {
1342 *data = 4;
1343 break;
1344 }
1345
1346 if (!shared_int) {
1347 /* Disable the other interrupts to be reported in
1348 * the cause register and then force the other
1349 * interrupts and see if any get posted. If
1350 * an interrupt was posted to the bus, the
1351 * test failed.
1352 */
1353 adapter->test_icr = 0;
1354
1355 /* Flush any pending interrupts */
1356 wr32(E1000_ICR, ~0);
1357
1358 wr32(E1000_IMC, ~mask);
1359 wr32(E1000_ICS, ~mask);
1360 msleep(10);
1361
1362 if (adapter->test_icr & mask) {
1363 *data = 5;
1364 break;
1365 }
1366 }
1367 }
1368
1369 /* Disable all the interrupts */
1370 wr32(E1000_IMC, ~0);
1371 msleep(10);
1372
1373 /* Unhook test interrupt handler */
1374 if (adapter->msix_entries)
1375 free_irq(adapter->msix_entries[0].vector, adapter);
1376 else
1377 free_irq(irq, adapter);
1378
1379 return *data;
1380 }
1381
1382 static void igb_free_desc_rings(struct igb_adapter *adapter)
1383 {
1384 igb_free_tx_resources(&adapter->test_tx_ring);
1385 igb_free_rx_resources(&adapter->test_rx_ring);
1386 }
1387
1388 static int igb_setup_desc_rings(struct igb_adapter *adapter)
1389 {
1390 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1391 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1392 struct e1000_hw *hw = &adapter->hw;
1393 int ret_val;
1394
1395 /* Setup Tx descriptor ring and Tx buffers */
1396 tx_ring->count = IGB_DEFAULT_TXD;
1397 tx_ring->dev = &adapter->pdev->dev;
1398 tx_ring->netdev = adapter->netdev;
1399 tx_ring->reg_idx = adapter->vfs_allocated_count;
1400
1401 if (igb_setup_tx_resources(tx_ring)) {
1402 ret_val = 1;
1403 goto err_nomem;
1404 }
1405
1406 igb_setup_tctl(adapter);
1407 igb_configure_tx_ring(adapter, tx_ring);
1408
1409 /* Setup Rx descriptor ring and Rx buffers */
1410 rx_ring->count = IGB_DEFAULT_RXD;
1411 rx_ring->dev = &adapter->pdev->dev;
1412 rx_ring->netdev = adapter->netdev;
1413 rx_ring->rx_buffer_len = IGB_RXBUFFER_2048;
1414 rx_ring->reg_idx = adapter->vfs_allocated_count;
1415
1416 if (igb_setup_rx_resources(rx_ring)) {
1417 ret_val = 3;
1418 goto err_nomem;
1419 }
1420
1421 /* set the default queue to queue 0 of PF */
1422 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3);
1423
1424 /* enable receive ring */
1425 igb_setup_rctl(adapter);
1426 igb_configure_rx_ring(adapter, rx_ring);
1427
1428 igb_alloc_rx_buffers_adv(rx_ring, igb_desc_unused(rx_ring));
1429
1430 return 0;
1431
1432 err_nomem:
1433 igb_free_desc_rings(adapter);
1434 return ret_val;
1435 }
1436
1437 static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1438 {
1439 struct e1000_hw *hw = &adapter->hw;
1440
1441 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1442 igb_write_phy_reg(hw, 29, 0x001F);
1443 igb_write_phy_reg(hw, 30, 0x8FFC);
1444 igb_write_phy_reg(hw, 29, 0x001A);
1445 igb_write_phy_reg(hw, 30, 0x8FF0);
1446 }
1447
1448 static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1449 {
1450 struct e1000_hw *hw = &adapter->hw;
1451 u32 ctrl_reg = 0;
1452
1453 hw->mac.autoneg = false;
1454
1455 if (hw->phy.type == e1000_phy_m88) {
1456 /* Auto-MDI/MDIX Off */
1457 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1458 /* reset to update Auto-MDI/MDIX */
1459 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1460 /* autoneg off */
1461 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1462 } else if (hw->phy.type == e1000_phy_82580) {
1463 /* enable MII loopback */
1464 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041);
1465 }
1466
1467 ctrl_reg = rd32(E1000_CTRL);
1468
1469 /* force 1000, set loopback */
1470 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1471
1472 /* Now set up the MAC to the same speed/duplex as the PHY. */
1473 ctrl_reg = rd32(E1000_CTRL);
1474 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1475 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1476 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1477 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1478 E1000_CTRL_FD | /* Force Duplex to FULL */
1479 E1000_CTRL_SLU); /* Set link up enable bit */
1480
1481 if (hw->phy.type == e1000_phy_m88)
1482 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1483
1484 wr32(E1000_CTRL, ctrl_reg);
1485
1486 /* Disable the receiver on the PHY so when a cable is plugged in, the
1487 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1488 */
1489 if (hw->phy.type == e1000_phy_m88)
1490 igb_phy_disable_receiver(adapter);
1491
1492 udelay(500);
1493
1494 return 0;
1495 }
1496
1497 static int igb_set_phy_loopback(struct igb_adapter *adapter)
1498 {
1499 return igb_integrated_phy_loopback(adapter);
1500 }
1501
1502 static int igb_setup_loopback_test(struct igb_adapter *adapter)
1503 {
1504 struct e1000_hw *hw = &adapter->hw;
1505 u32 reg;
1506
1507 reg = rd32(E1000_CTRL_EXT);
1508
1509 /* use CTRL_EXT to identify link type as SGMII can appear as copper */
1510 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) {
1511 reg = rd32(E1000_RCTL);
1512 reg |= E1000_RCTL_LBM_TCVR;
1513 wr32(E1000_RCTL, reg);
1514
1515 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1516
1517 reg = rd32(E1000_CTRL);
1518 reg &= ~(E1000_CTRL_RFCE |
1519 E1000_CTRL_TFCE |
1520 E1000_CTRL_LRST);
1521 reg |= E1000_CTRL_SLU |
1522 E1000_CTRL_FD;
1523 wr32(E1000_CTRL, reg);
1524
1525 /* Unset switch control to serdes energy detect */
1526 reg = rd32(E1000_CONNSW);
1527 reg &= ~E1000_CONNSW_ENRGSRC;
1528 wr32(E1000_CONNSW, reg);
1529
1530 /* Set PCS register for forced speed */
1531 reg = rd32(E1000_PCS_LCTL);
1532 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
1533 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1534 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1535 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1536 E1000_PCS_LCTL_FSD | /* Force Speed */
1537 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1538 wr32(E1000_PCS_LCTL, reg);
1539
1540 return 0;
1541 }
1542
1543 return igb_set_phy_loopback(adapter);
1544 }
1545
1546 static void igb_loopback_cleanup(struct igb_adapter *adapter)
1547 {
1548 struct e1000_hw *hw = &adapter->hw;
1549 u32 rctl;
1550 u16 phy_reg;
1551
1552 rctl = rd32(E1000_RCTL);
1553 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1554 wr32(E1000_RCTL, rctl);
1555
1556 hw->mac.autoneg = true;
1557 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1558 if (phy_reg & MII_CR_LOOPBACK) {
1559 phy_reg &= ~MII_CR_LOOPBACK;
1560 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
1561 igb_phy_sw_reset(hw);
1562 }
1563 }
1564
1565 static void igb_create_lbtest_frame(struct sk_buff *skb,
1566 unsigned int frame_size)
1567 {
1568 memset(skb->data, 0xFF, frame_size);
1569 frame_size /= 2;
1570 memset(&skb->data[frame_size], 0xAA, frame_size - 1);
1571 memset(&skb->data[frame_size + 10], 0xBE, 1);
1572 memset(&skb->data[frame_size + 12], 0xAF, 1);
1573 }
1574
1575 static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1576 {
1577 frame_size /= 2;
1578 if (*(skb->data + 3) == 0xFF) {
1579 if ((*(skb->data + frame_size + 10) == 0xBE) &&
1580 (*(skb->data + frame_size + 12) == 0xAF)) {
1581 return 0;
1582 }
1583 }
1584 return 13;
1585 }
1586
1587 static int igb_clean_test_rings(struct igb_ring *rx_ring,
1588 struct igb_ring *tx_ring,
1589 unsigned int size)
1590 {
1591 union e1000_adv_rx_desc *rx_desc;
1592 struct igb_buffer *buffer_info;
1593 int rx_ntc, tx_ntc, count = 0;
1594 u32 staterr;
1595
1596 /* initialize next to clean and descriptor values */
1597 rx_ntc = rx_ring->next_to_clean;
1598 tx_ntc = tx_ring->next_to_clean;
1599 rx_desc = E1000_RX_DESC_ADV(*rx_ring, rx_ntc);
1600 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1601
1602 while (staterr & E1000_RXD_STAT_DD) {
1603 /* check rx buffer */
1604 buffer_info = &rx_ring->buffer_info[rx_ntc];
1605
1606 /* unmap rx buffer, will be remapped by alloc_rx_buffers */
1607 dma_unmap_single(rx_ring->dev,
1608 buffer_info->dma,
1609 rx_ring->rx_buffer_len,
1610 DMA_FROM_DEVICE);
1611 buffer_info->dma = 0;
1612
1613 /* verify contents of skb */
1614 if (!igb_check_lbtest_frame(buffer_info->skb, size))
1615 count++;
1616
1617 /* unmap buffer on tx side */
1618 buffer_info = &tx_ring->buffer_info[tx_ntc];
1619 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
1620
1621 /* increment rx/tx next to clean counters */
1622 rx_ntc++;
1623 if (rx_ntc == rx_ring->count)
1624 rx_ntc = 0;
1625 tx_ntc++;
1626 if (tx_ntc == tx_ring->count)
1627 tx_ntc = 0;
1628
1629 /* fetch next descriptor */
1630 rx_desc = E1000_RX_DESC_ADV(*rx_ring, rx_ntc);
1631 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1632 }
1633
1634 /* re-map buffers to ring, store next to clean values */
1635 igb_alloc_rx_buffers_adv(rx_ring, count);
1636 rx_ring->next_to_clean = rx_ntc;
1637 tx_ring->next_to_clean = tx_ntc;
1638
1639 return count;
1640 }
1641
1642 static int igb_run_loopback_test(struct igb_adapter *adapter)
1643 {
1644 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1645 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1646 int i, j, lc, good_cnt, ret_val = 0;
1647 unsigned int size = 1024;
1648 netdev_tx_t tx_ret_val;
1649 struct sk_buff *skb;
1650
1651 /* allocate test skb */
1652 skb = alloc_skb(size, GFP_KERNEL);
1653 if (!skb)
1654 return 11;
1655
1656 /* place data into test skb */
1657 igb_create_lbtest_frame(skb, size);
1658 skb_put(skb, size);
1659
1660 /*
1661 * Calculate the loop count based on the largest descriptor ring
1662 * The idea is to wrap the largest ring a number of times using 64
1663 * send/receive pairs during each loop
1664 */
1665
1666 if (rx_ring->count <= tx_ring->count)
1667 lc = ((tx_ring->count / 64) * 2) + 1;
1668 else
1669 lc = ((rx_ring->count / 64) * 2) + 1;
1670
1671 for (j = 0; j <= lc; j++) { /* loop count loop */
1672 /* reset count of good packets */
1673 good_cnt = 0;
1674
1675 /* place 64 packets on the transmit queue*/
1676 for (i = 0; i < 64; i++) {
1677 skb_get(skb);
1678 tx_ret_val = igb_xmit_frame_ring_adv(skb, tx_ring);
1679 if (tx_ret_val == NETDEV_TX_OK)
1680 good_cnt++;
1681 }
1682
1683 if (good_cnt != 64) {
1684 ret_val = 12;
1685 break;
1686 }
1687
1688 /* allow 200 milliseconds for packets to go from tx to rx */
1689 msleep(200);
1690
1691 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size);
1692 if (good_cnt != 64) {
1693 ret_val = 13;
1694 break;
1695 }
1696 } /* end loop count loop */
1697
1698 /* free the original skb */
1699 kfree_skb(skb);
1700
1701 return ret_val;
1702 }
1703
1704 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1705 {
1706 /* PHY loopback cannot be performed if SoL/IDER
1707 * sessions are active */
1708 if (igb_check_reset_block(&adapter->hw)) {
1709 dev_err(&adapter->pdev->dev,
1710 "Cannot do PHY loopback test "
1711 "when SoL/IDER is active.\n");
1712 *data = 0;
1713 goto out;
1714 }
1715 *data = igb_setup_desc_rings(adapter);
1716 if (*data)
1717 goto out;
1718 *data = igb_setup_loopback_test(adapter);
1719 if (*data)
1720 goto err_loopback;
1721 *data = igb_run_loopback_test(adapter);
1722 igb_loopback_cleanup(adapter);
1723
1724 err_loopback:
1725 igb_free_desc_rings(adapter);
1726 out:
1727 return *data;
1728 }
1729
1730 static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1731 {
1732 struct e1000_hw *hw = &adapter->hw;
1733 *data = 0;
1734 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1735 int i = 0;
1736 hw->mac.serdes_has_link = false;
1737
1738 /* On some blade server designs, link establishment
1739 * could take as long as 2-3 minutes */
1740 do {
1741 hw->mac.ops.check_for_link(&adapter->hw);
1742 if (hw->mac.serdes_has_link)
1743 return *data;
1744 msleep(20);
1745 } while (i++ < 3750);
1746
1747 *data = 1;
1748 } else {
1749 hw->mac.ops.check_for_link(&adapter->hw);
1750 if (hw->mac.autoneg)
1751 msleep(4000);
1752
1753 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU))
1754 *data = 1;
1755 }
1756 return *data;
1757 }
1758
1759 static void igb_diag_test(struct net_device *netdev,
1760 struct ethtool_test *eth_test, u64 *data)
1761 {
1762 struct igb_adapter *adapter = netdev_priv(netdev);
1763 u16 autoneg_advertised;
1764 u8 forced_speed_duplex, autoneg;
1765 bool if_running = netif_running(netdev);
1766
1767 set_bit(__IGB_TESTING, &adapter->state);
1768 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1769 /* Offline tests */
1770
1771 /* save speed, duplex, autoneg settings */
1772 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1773 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1774 autoneg = adapter->hw.mac.autoneg;
1775
1776 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1777
1778 /* power up link for link test */
1779 igb_power_up_link(adapter);
1780
1781 /* Link test performed before hardware reset so autoneg doesn't
1782 * interfere with test result */
1783 if (igb_link_test(adapter, &data[4]))
1784 eth_test->flags |= ETH_TEST_FL_FAILED;
1785
1786 if (if_running)
1787 /* indicate we're in test mode */
1788 dev_close(netdev);
1789 else
1790 igb_reset(adapter);
1791
1792 if (igb_reg_test(adapter, &data[0]))
1793 eth_test->flags |= ETH_TEST_FL_FAILED;
1794
1795 igb_reset(adapter);
1796 if (igb_eeprom_test(adapter, &data[1]))
1797 eth_test->flags |= ETH_TEST_FL_FAILED;
1798
1799 igb_reset(adapter);
1800 if (igb_intr_test(adapter, &data[2]))
1801 eth_test->flags |= ETH_TEST_FL_FAILED;
1802
1803 igb_reset(adapter);
1804 /* power up link for loopback test */
1805 igb_power_up_link(adapter);
1806 if (igb_loopback_test(adapter, &data[3]))
1807 eth_test->flags |= ETH_TEST_FL_FAILED;
1808
1809 /* restore speed, duplex, autoneg settings */
1810 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
1811 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
1812 adapter->hw.mac.autoneg = autoneg;
1813
1814 /* force this routine to wait until autoneg complete/timeout */
1815 adapter->hw.phy.autoneg_wait_to_complete = true;
1816 igb_reset(adapter);
1817 adapter->hw.phy.autoneg_wait_to_complete = false;
1818
1819 clear_bit(__IGB_TESTING, &adapter->state);
1820 if (if_running)
1821 dev_open(netdev);
1822 } else {
1823 dev_info(&adapter->pdev->dev, "online testing starting\n");
1824
1825 /* PHY is powered down when interface is down */
1826 if (!netif_carrier_ok(netdev)) {
1827 data[4] = 0;
1828 } else {
1829 if (igb_link_test(adapter, &data[4]))
1830 eth_test->flags |= ETH_TEST_FL_FAILED;
1831 }
1832
1833 /* Online tests aren't run; pass by default */
1834 data[0] = 0;
1835 data[1] = 0;
1836 data[2] = 0;
1837 data[3] = 0;
1838
1839 clear_bit(__IGB_TESTING, &adapter->state);
1840 }
1841 msleep_interruptible(4 * 1000);
1842 }
1843
1844 static int igb_wol_exclusion(struct igb_adapter *adapter,
1845 struct ethtool_wolinfo *wol)
1846 {
1847 struct e1000_hw *hw = &adapter->hw;
1848 int retval = 1; /* fail by default */
1849
1850 switch (hw->device_id) {
1851 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1852 /* WoL not supported */
1853 wol->supported = 0;
1854 break;
1855 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1856 case E1000_DEV_ID_82576_FIBER:
1857 case E1000_DEV_ID_82576_SERDES:
1858 /* Wake events not supported on port B */
1859 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {
1860 wol->supported = 0;
1861 break;
1862 }
1863 /* return success for non excluded adapter ports */
1864 retval = 0;
1865 break;
1866 case E1000_DEV_ID_82576_QUAD_COPPER:
1867 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
1868 /* quad port adapters only support WoL on port A */
1869 if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) {
1870 wol->supported = 0;
1871 break;
1872 }
1873 /* return success for non excluded adapter ports */
1874 retval = 0;
1875 break;
1876 default:
1877 /* dual port cards only support WoL on port A from now on
1878 * unless it was enabled in the eeprom for port B
1879 * so exclude FUNC_1 ports from having WoL enabled */
1880 if ((rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) &&
1881 !adapter->eeprom_wol) {
1882 wol->supported = 0;
1883 break;
1884 }
1885
1886 retval = 0;
1887 }
1888
1889 return retval;
1890 }
1891
1892 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1893 {
1894 struct igb_adapter *adapter = netdev_priv(netdev);
1895
1896 wol->supported = WAKE_UCAST | WAKE_MCAST |
1897 WAKE_BCAST | WAKE_MAGIC |
1898 WAKE_PHY;
1899 wol->wolopts = 0;
1900
1901 /* this function will set ->supported = 0 and return 1 if wol is not
1902 * supported by this hardware */
1903 if (igb_wol_exclusion(adapter, wol) ||
1904 !device_can_wakeup(&adapter->pdev->dev))
1905 return;
1906
1907 /* apply any specific unsupported masks here */
1908 switch (adapter->hw.device_id) {
1909 default:
1910 break;
1911 }
1912
1913 if (adapter->wol & E1000_WUFC_EX)
1914 wol->wolopts |= WAKE_UCAST;
1915 if (adapter->wol & E1000_WUFC_MC)
1916 wol->wolopts |= WAKE_MCAST;
1917 if (adapter->wol & E1000_WUFC_BC)
1918 wol->wolopts |= WAKE_BCAST;
1919 if (adapter->wol & E1000_WUFC_MAG)
1920 wol->wolopts |= WAKE_MAGIC;
1921 if (adapter->wol & E1000_WUFC_LNKC)
1922 wol->wolopts |= WAKE_PHY;
1923 }
1924
1925 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1926 {
1927 struct igb_adapter *adapter = netdev_priv(netdev);
1928
1929 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
1930 return -EOPNOTSUPP;
1931
1932 if (igb_wol_exclusion(adapter, wol) ||
1933 !device_can_wakeup(&adapter->pdev->dev))
1934 return wol->wolopts ? -EOPNOTSUPP : 0;
1935
1936 /* these settings will always override what we currently have */
1937 adapter->wol = 0;
1938
1939 if (wol->wolopts & WAKE_UCAST)
1940 adapter->wol |= E1000_WUFC_EX;
1941 if (wol->wolopts & WAKE_MCAST)
1942 adapter->wol |= E1000_WUFC_MC;
1943 if (wol->wolopts & WAKE_BCAST)
1944 adapter->wol |= E1000_WUFC_BC;
1945 if (wol->wolopts & WAKE_MAGIC)
1946 adapter->wol |= E1000_WUFC_MAG;
1947 if (wol->wolopts & WAKE_PHY)
1948 adapter->wol |= E1000_WUFC_LNKC;
1949 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1950
1951 return 0;
1952 }
1953
1954 /* bit defines for adapter->led_status */
1955 #define IGB_LED_ON 0
1956
1957 static int igb_phys_id(struct net_device *netdev, u32 data)
1958 {
1959 struct igb_adapter *adapter = netdev_priv(netdev);
1960 struct e1000_hw *hw = &adapter->hw;
1961 unsigned long timeout;
1962
1963 timeout = data * 1000;
1964
1965 /*
1966 * msleep_interruptable only accepts unsigned int so we are limited
1967 * in how long a duration we can wait
1968 */
1969 if (!timeout || timeout > UINT_MAX)
1970 timeout = UINT_MAX;
1971
1972 igb_blink_led(hw);
1973 msleep_interruptible(timeout);
1974
1975 igb_led_off(hw);
1976 clear_bit(IGB_LED_ON, &adapter->led_status);
1977 igb_cleanup_led(hw);
1978
1979 return 0;
1980 }
1981
1982 static int igb_set_coalesce(struct net_device *netdev,
1983 struct ethtool_coalesce *ec)
1984 {
1985 struct igb_adapter *adapter = netdev_priv(netdev);
1986 int i;
1987
1988 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1989 ((ec->rx_coalesce_usecs > 3) &&
1990 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1991 (ec->rx_coalesce_usecs == 2))
1992 return -EINVAL;
1993
1994 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1995 ((ec->tx_coalesce_usecs > 3) &&
1996 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1997 (ec->tx_coalesce_usecs == 2))
1998 return -EINVAL;
1999
2000 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)
2001 return -EINVAL;
2002
2003 /* convert to rate of irq's per second */
2004 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)
2005 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2006 else
2007 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2008
2009 /* convert to rate of irq's per second */
2010 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS)
2011 adapter->tx_itr_setting = adapter->rx_itr_setting;
2012 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3)
2013 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2014 else
2015 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2016
2017 for (i = 0; i < adapter->num_q_vectors; i++) {
2018 struct igb_q_vector *q_vector = adapter->q_vector[i];
2019 if (q_vector->rx_ring)
2020 q_vector->itr_val = adapter->rx_itr_setting;
2021 else
2022 q_vector->itr_val = adapter->tx_itr_setting;
2023 if (q_vector->itr_val && q_vector->itr_val <= 3)
2024 q_vector->itr_val = IGB_START_ITR;
2025 q_vector->set_itr = 1;
2026 }
2027
2028 return 0;
2029 }
2030
2031 static int igb_get_coalesce(struct net_device *netdev,
2032 struct ethtool_coalesce *ec)
2033 {
2034 struct igb_adapter *adapter = netdev_priv(netdev);
2035
2036 if (adapter->rx_itr_setting <= 3)
2037 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2038 else
2039 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2040
2041 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) {
2042 if (adapter->tx_itr_setting <= 3)
2043 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2044 else
2045 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2046 }
2047
2048 return 0;
2049 }
2050
2051 static int igb_nway_reset(struct net_device *netdev)
2052 {
2053 struct igb_adapter *adapter = netdev_priv(netdev);
2054 if (netif_running(netdev))
2055 igb_reinit_locked(adapter);
2056 return 0;
2057 }
2058
2059 static int igb_get_sset_count(struct net_device *netdev, int sset)
2060 {
2061 switch (sset) {
2062 case ETH_SS_STATS:
2063 return IGB_STATS_LEN;
2064 case ETH_SS_TEST:
2065 return IGB_TEST_LEN;
2066 default:
2067 return -ENOTSUPP;
2068 }
2069 }
2070
2071 static void igb_get_ethtool_stats(struct net_device *netdev,
2072 struct ethtool_stats *stats, u64 *data)
2073 {
2074 struct igb_adapter *adapter = netdev_priv(netdev);
2075 struct net_device_stats *net_stats = &netdev->stats;
2076 u64 *queue_stat;
2077 int i, j, k;
2078 char *p;
2079
2080 igb_update_stats(adapter);
2081
2082 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2083 p = (char *)adapter + igb_gstrings_stats[i].stat_offset;
2084 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
2085 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2086 }
2087 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) {
2088 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset;
2089 data[i] = (igb_gstrings_net_stats[j].sizeof_stat ==
2090 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2091 }
2092 for (j = 0; j < adapter->num_tx_queues; j++) {
2093 queue_stat = (u64 *)&adapter->tx_ring[j]->tx_stats;
2094 for (k = 0; k < IGB_TX_QUEUE_STATS_LEN; k++, i++)
2095 data[i] = queue_stat[k];
2096 }
2097 for (j = 0; j < adapter->num_rx_queues; j++) {
2098 queue_stat = (u64 *)&adapter->rx_ring[j]->rx_stats;
2099 for (k = 0; k < IGB_RX_QUEUE_STATS_LEN; k++, i++)
2100 data[i] = queue_stat[k];
2101 }
2102 }
2103
2104 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2105 {
2106 struct igb_adapter *adapter = netdev_priv(netdev);
2107 u8 *p = data;
2108 int i;
2109
2110 switch (stringset) {
2111 case ETH_SS_TEST:
2112 memcpy(data, *igb_gstrings_test,
2113 IGB_TEST_LEN*ETH_GSTRING_LEN);
2114 break;
2115 case ETH_SS_STATS:
2116 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2117 memcpy(p, igb_gstrings_stats[i].stat_string,
2118 ETH_GSTRING_LEN);
2119 p += ETH_GSTRING_LEN;
2120 }
2121 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) {
2122 memcpy(p, igb_gstrings_net_stats[i].stat_string,
2123 ETH_GSTRING_LEN);
2124 p += ETH_GSTRING_LEN;
2125 }
2126 for (i = 0; i < adapter->num_tx_queues; i++) {
2127 sprintf(p, "tx_queue_%u_packets", i);
2128 p += ETH_GSTRING_LEN;
2129 sprintf(p, "tx_queue_%u_bytes", i);
2130 p += ETH_GSTRING_LEN;
2131 sprintf(p, "tx_queue_%u_restart", i);
2132 p += ETH_GSTRING_LEN;
2133 }
2134 for (i = 0; i < adapter->num_rx_queues; i++) {
2135 sprintf(p, "rx_queue_%u_packets", i);
2136 p += ETH_GSTRING_LEN;
2137 sprintf(p, "rx_queue_%u_bytes", i);
2138 p += ETH_GSTRING_LEN;
2139 sprintf(p, "rx_queue_%u_drops", i);
2140 p += ETH_GSTRING_LEN;
2141 sprintf(p, "rx_queue_%u_csum_err", i);
2142 p += ETH_GSTRING_LEN;
2143 sprintf(p, "rx_queue_%u_alloc_failed", i);
2144 p += ETH_GSTRING_LEN;
2145 }
2146 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2147 break;
2148 }
2149 }
2150
2151 static const struct ethtool_ops igb_ethtool_ops = {
2152 .get_settings = igb_get_settings,
2153 .set_settings = igb_set_settings,
2154 .get_drvinfo = igb_get_drvinfo,
2155 .get_regs_len = igb_get_regs_len,
2156 .get_regs = igb_get_regs,
2157 .get_wol = igb_get_wol,
2158 .set_wol = igb_set_wol,
2159 .get_msglevel = igb_get_msglevel,
2160 .set_msglevel = igb_set_msglevel,
2161 .nway_reset = igb_nway_reset,
2162 .get_link = igb_get_link,
2163 .get_eeprom_len = igb_get_eeprom_len,
2164 .get_eeprom = igb_get_eeprom,
2165 .set_eeprom = igb_set_eeprom,
2166 .get_ringparam = igb_get_ringparam,
2167 .set_ringparam = igb_set_ringparam,
2168 .get_pauseparam = igb_get_pauseparam,
2169 .set_pauseparam = igb_set_pauseparam,
2170 .get_rx_csum = igb_get_rx_csum,
2171 .set_rx_csum = igb_set_rx_csum,
2172 .get_tx_csum = igb_get_tx_csum,
2173 .set_tx_csum = igb_set_tx_csum,
2174 .get_sg = ethtool_op_get_sg,
2175 .set_sg = ethtool_op_set_sg,
2176 .get_tso = ethtool_op_get_tso,
2177 .set_tso = igb_set_tso,
2178 .self_test = igb_diag_test,
2179 .get_strings = igb_get_strings,
2180 .phys_id = igb_phys_id,
2181 .get_sset_count = igb_get_sset_count,
2182 .get_ethtool_stats = igb_get_ethtool_stats,
2183 .get_coalesce = igb_get_coalesce,
2184 .set_coalesce = igb_set_coalesce,
2185 };
2186
2187 void igb_set_ethtool_ops(struct net_device *netdev)
2188 {
2189 SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
2190 }
AMDTP streaming driver for the Linux FireWire stack (Juju)