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firewire: core: check for 1394a compliant IRM, fix inaccessibility of Sony camcorder
[firewire-audio.git] / drivers / net / bnx2.c
blob188e356c30a30e005a69eaf05997ea57fdae880e
1 /* bnx2.c: Broadcom NX2 network driver.
2 *
3 * Copyright (c) 2004-2010 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16
17 #include <linux/kernel.h>
18 #include <linux/timer.h>
19 #include <linux/errno.h>
20 #include <linux/ioport.h>
21 #include <linux/slab.h>
22 #include <linux/vmalloc.h>
23 #include <linux/interrupt.h>
24 #include <linux/pci.h>
25 #include <linux/init.h>
26 #include <linux/netdevice.h>
27 #include <linux/etherdevice.h>
28 #include <linux/skbuff.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/bitops.h>
31 #include <asm/io.h>
32 #include <asm/irq.h>
33 #include <linux/delay.h>
34 #include <asm/byteorder.h>
35 #include <asm/page.h>
36 #include <linux/time.h>
37 #include <linux/ethtool.h>
38 #include <linux/mii.h>
39 #include <linux/if_vlan.h>
40 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
41 #define BCM_VLAN 1
42 #endif
43 #include <net/ip.h>
44 #include <net/tcp.h>
45 #include <net/checksum.h>
46 #include <linux/workqueue.h>
47 #include <linux/crc32.h>
48 #include <linux/prefetch.h>
49 #include <linux/cache.h>
50 #include <linux/firmware.h>
51 #include <linux/log2.h>
52
53 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
54 #define BCM_CNIC 1
55 #include "cnic_if.h"
56 #endif
57 #include "bnx2.h"
58 #include "bnx2_fw.h"
59
60 #define DRV_MODULE_NAME "bnx2"
61 #define DRV_MODULE_VERSION "2.0.15"
62 #define DRV_MODULE_RELDATE "May 4, 2010"
63 #define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-5.0.0.j6.fw"
64 #define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-5.0.0.j3.fw"
65 #define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-5.0.0.j15.fw"
66 #define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-5.0.0.j10.fw"
67 #define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-5.0.0.j10.fw"
68
69 #define RUN_AT(x) (jiffies + (x))
70
71 /* Time in jiffies before concluding the transmitter is hung. */
72 #define TX_TIMEOUT (5*HZ)
73
74 static char version[] __devinitdata =
75 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
76
77 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
78 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
79 MODULE_LICENSE("GPL");
80 MODULE_VERSION(DRV_MODULE_VERSION);
81 MODULE_FIRMWARE(FW_MIPS_FILE_06);
82 MODULE_FIRMWARE(FW_RV2P_FILE_06);
83 MODULE_FIRMWARE(FW_MIPS_FILE_09);
84 MODULE_FIRMWARE(FW_RV2P_FILE_09);
85 MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax);
86
87 static int disable_msi = 0;
88
89 module_param(disable_msi, int, 0);
90 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
91
92 typedef enum {
93 BCM5706 = 0,
94 NC370T,
95 NC370I,
96 BCM5706S,
97 NC370F,
98 BCM5708,
99 BCM5708S,
100 BCM5709,
101 BCM5709S,
102 BCM5716,
103 BCM5716S,
104 } board_t;
105
106 /* indexed by board_t, above */
107 static struct {
108 char *name;
109 } board_info[] __devinitdata = {
110 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
111 { "HP NC370T Multifunction Gigabit Server Adapter" },
112 { "HP NC370i Multifunction Gigabit Server Adapter" },
113 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
114 { "HP NC370F Multifunction Gigabit Server Adapter" },
115 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
116 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
117 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
118 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
119 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
120 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
121 };
122
123 static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
124 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
125 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
126 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
127 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
128 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
130 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
132 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
133 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
134 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
136 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
138 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
140 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
142 { PCI_VENDOR_ID_BROADCOM, 0x163b,
143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
144 { PCI_VENDOR_ID_BROADCOM, 0x163c,
145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
146 { 0, }
147 };
148
149 static const struct flash_spec flash_table[] =
150 {
151 #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
152 #define NONBUFFERED_FLAGS (BNX2_NV_WREN)
153 /* Slow EEPROM */
154 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
155 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
156 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
157 "EEPROM - slow"},
158 /* Expansion entry 0001 */
159 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
160 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
161 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
162 "Entry 0001"},
163 /* Saifun SA25F010 (non-buffered flash) */
164 /* strap, cfg1, & write1 need updates */
165 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
166 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
167 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
168 "Non-buffered flash (128kB)"},
169 /* Saifun SA25F020 (non-buffered flash) */
170 /* strap, cfg1, & write1 need updates */
171 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
172 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
173 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
174 "Non-buffered flash (256kB)"},
175 /* Expansion entry 0100 */
176 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
177 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
178 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
179 "Entry 0100"},
180 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
181 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
182 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
183 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
184 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
185 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
186 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
187 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
188 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
189 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
190 /* Saifun SA25F005 (non-buffered flash) */
191 /* strap, cfg1, & write1 need updates */
192 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
194 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
195 "Non-buffered flash (64kB)"},
196 /* Fast EEPROM */
197 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
198 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
199 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
200 "EEPROM - fast"},
201 /* Expansion entry 1001 */
202 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
204 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
205 "Entry 1001"},
206 /* Expansion entry 1010 */
207 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
208 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
209 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
210 "Entry 1010"},
211 /* ATMEL AT45DB011B (buffered flash) */
212 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
213 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
214 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
215 "Buffered flash (128kB)"},
216 /* Expansion entry 1100 */
217 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
218 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
219 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
220 "Entry 1100"},
221 /* Expansion entry 1101 */
222 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
223 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
224 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
225 "Entry 1101"},
226 /* Ateml Expansion entry 1110 */
227 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
228 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
229 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
230 "Entry 1110 (Atmel)"},
231 /* ATMEL AT45DB021B (buffered flash) */
232 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
233 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
234 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
235 "Buffered flash (256kB)"},
236 };
237
238 static const struct flash_spec flash_5709 = {
239 .flags = BNX2_NV_BUFFERED,
240 .page_bits = BCM5709_FLASH_PAGE_BITS,
241 .page_size = BCM5709_FLASH_PAGE_SIZE,
242 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
243 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
244 .name = "5709 Buffered flash (256kB)",
245 };
246
247 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
248
249 static void bnx2_init_napi(struct bnx2 *bp);
250
251 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
252 {
253 u32 diff;
254
255 smp_mb();
256
257 /* The ring uses 256 indices for 255 entries, one of them
258 * needs to be skipped.
259 */
260 diff = txr->tx_prod - txr->tx_cons;
261 if (unlikely(diff >= TX_DESC_CNT)) {
262 diff &= 0xffff;
263 if (diff == TX_DESC_CNT)
264 diff = MAX_TX_DESC_CNT;
265 }
266 return (bp->tx_ring_size - diff);
267 }
268
269 static u32
270 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
271 {
272 u32 val;
273
274 spin_lock_bh(&bp->indirect_lock);
275 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
276 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
277 spin_unlock_bh(&bp->indirect_lock);
278 return val;
279 }
280
281 static void
282 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
283 {
284 spin_lock_bh(&bp->indirect_lock);
285 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
286 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
287 spin_unlock_bh(&bp->indirect_lock);
288 }
289
290 static void
291 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
292 {
293 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
294 }
295
296 static u32
297 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
298 {
299 return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
300 }
301
302 static void
303 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
304 {
305 offset += cid_addr;
306 spin_lock_bh(&bp->indirect_lock);
307 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
308 int i;
309
310 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
311 REG_WR(bp, BNX2_CTX_CTX_CTRL,
312 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
313 for (i = 0; i < 5; i++) {
314 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
315 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
316 break;
317 udelay(5);
318 }
319 } else {
320 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
321 REG_WR(bp, BNX2_CTX_DATA, val);
322 }
323 spin_unlock_bh(&bp->indirect_lock);
324 }
325
326 #ifdef BCM_CNIC
327 static int
328 bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info)
329 {
330 struct bnx2 *bp = netdev_priv(dev);
331 struct drv_ctl_io *io = &info->data.io;
332
333 switch (info->cmd) {
334 case DRV_CTL_IO_WR_CMD:
335 bnx2_reg_wr_ind(bp, io->offset, io->data);
336 break;
337 case DRV_CTL_IO_RD_CMD:
338 io->data = bnx2_reg_rd_ind(bp, io->offset);
339 break;
340 case DRV_CTL_CTX_WR_CMD:
341 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
342 break;
343 default:
344 return -EINVAL;
345 }
346 return 0;
347 }
348
349 static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
350 {
351 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
352 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
353 int sb_id;
354
355 if (bp->flags & BNX2_FLAG_USING_MSIX) {
356 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
357 bnapi->cnic_present = 0;
358 sb_id = bp->irq_nvecs;
359 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
360 } else {
361 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
362 bnapi->cnic_tag = bnapi->last_status_idx;
363 bnapi->cnic_present = 1;
364 sb_id = 0;
365 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
366 }
367
368 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
369 cp->irq_arr[0].status_blk = (void *)
370 ((unsigned long) bnapi->status_blk.msi +
371 (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id));
372 cp->irq_arr[0].status_blk_num = sb_id;
373 cp->num_irq = 1;
374 }
375
376 static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops,
377 void *data)
378 {
379 struct bnx2 *bp = netdev_priv(dev);
380 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
381
382 if (ops == NULL)
383 return -EINVAL;
384
385 if (cp->drv_state & CNIC_DRV_STATE_REGD)
386 return -EBUSY;
387
388 bp->cnic_data = data;
389 rcu_assign_pointer(bp->cnic_ops, ops);
390
391 cp->num_irq = 0;
392 cp->drv_state = CNIC_DRV_STATE_REGD;
393
394 bnx2_setup_cnic_irq_info(bp);
395
396 return 0;
397 }
398
399 static int bnx2_unregister_cnic(struct net_device *dev)
400 {
401 struct bnx2 *bp = netdev_priv(dev);
402 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
403 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
404
405 mutex_lock(&bp->cnic_lock);
406 cp->drv_state = 0;
407 bnapi->cnic_present = 0;
408 rcu_assign_pointer(bp->cnic_ops, NULL);
409 mutex_unlock(&bp->cnic_lock);
410 synchronize_rcu();
411 return 0;
412 }
413
414 struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev)
415 {
416 struct bnx2 *bp = netdev_priv(dev);
417 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
418
419 cp->drv_owner = THIS_MODULE;
420 cp->chip_id = bp->chip_id;
421 cp->pdev = bp->pdev;
422 cp->io_base = bp->regview;
423 cp->drv_ctl = bnx2_drv_ctl;
424 cp->drv_register_cnic = bnx2_register_cnic;
425 cp->drv_unregister_cnic = bnx2_unregister_cnic;
426
427 return cp;
428 }
429 EXPORT_SYMBOL(bnx2_cnic_probe);
430
431 static void
432 bnx2_cnic_stop(struct bnx2 *bp)
433 {
434 struct cnic_ops *c_ops;
435 struct cnic_ctl_info info;
436
437 mutex_lock(&bp->cnic_lock);
438 c_ops = bp->cnic_ops;
439 if (c_ops) {
440 info.cmd = CNIC_CTL_STOP_CMD;
441 c_ops->cnic_ctl(bp->cnic_data, &info);
442 }
443 mutex_unlock(&bp->cnic_lock);
444 }
445
446 static void
447 bnx2_cnic_start(struct bnx2 *bp)
448 {
449 struct cnic_ops *c_ops;
450 struct cnic_ctl_info info;
451
452 mutex_lock(&bp->cnic_lock);
453 c_ops = bp->cnic_ops;
454 if (c_ops) {
455 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
456 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
457
458 bnapi->cnic_tag = bnapi->last_status_idx;
459 }
460 info.cmd = CNIC_CTL_START_CMD;
461 c_ops->cnic_ctl(bp->cnic_data, &info);
462 }
463 mutex_unlock(&bp->cnic_lock);
464 }
465
466 #else
467
468 static void
469 bnx2_cnic_stop(struct bnx2 *bp)
470 {
471 }
472
473 static void
474 bnx2_cnic_start(struct bnx2 *bp)
475 {
476 }
477
478 #endif
479
480 static int
481 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
482 {
483 u32 val1;
484 int i, ret;
485
486 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
487 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
488 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
489
490 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
491 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
492
493 udelay(40);
494 }
495
496 val1 = (bp->phy_addr << 21) | (reg << 16) |
497 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
498 BNX2_EMAC_MDIO_COMM_START_BUSY;
499 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
500
501 for (i = 0; i < 50; i++) {
502 udelay(10);
503
504 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
505 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
506 udelay(5);
507
508 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
509 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
510
511 break;
512 }
513 }
514
515 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
516 *val = 0x0;
517 ret = -EBUSY;
518 }
519 else {
520 *val = val1;
521 ret = 0;
522 }
523
524 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
525 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
526 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
527
528 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
529 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
530
531 udelay(40);
532 }
533
534 return ret;
535 }
536
537 static int
538 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
539 {
540 u32 val1;
541 int i, ret;
542
543 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
544 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
545 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
546
547 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
548 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
549
550 udelay(40);
551 }
552
553 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
554 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
555 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
556 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
557
558 for (i = 0; i < 50; i++) {
559 udelay(10);
560
561 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
562 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
563 udelay(5);
564 break;
565 }
566 }
567
568 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
569 ret = -EBUSY;
570 else
571 ret = 0;
572
573 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
574 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
575 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
576
577 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
578 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
579
580 udelay(40);
581 }
582
583 return ret;
584 }
585
586 static void
587 bnx2_disable_int(struct bnx2 *bp)
588 {
589 int i;
590 struct bnx2_napi *bnapi;
591
592 for (i = 0; i < bp->irq_nvecs; i++) {
593 bnapi = &bp->bnx2_napi[i];
594 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
595 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
596 }
597 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
598 }
599
600 static void
601 bnx2_enable_int(struct bnx2 *bp)
602 {
603 int i;
604 struct bnx2_napi *bnapi;
605
606 for (i = 0; i < bp->irq_nvecs; i++) {
607 bnapi = &bp->bnx2_napi[i];
608
609 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
610 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
611 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
612 bnapi->last_status_idx);
613
614 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
615 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
616 bnapi->last_status_idx);
617 }
618 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
619 }
620
621 static void
622 bnx2_disable_int_sync(struct bnx2 *bp)
623 {
624 int i;
625
626 atomic_inc(&bp->intr_sem);
627 if (!netif_running(bp->dev))
628 return;
629
630 bnx2_disable_int(bp);
631 for (i = 0; i < bp->irq_nvecs; i++)
632 synchronize_irq(bp->irq_tbl[i].vector);
633 }
634
635 static void
636 bnx2_napi_disable(struct bnx2 *bp)
637 {
638 int i;
639
640 for (i = 0; i < bp->irq_nvecs; i++)
641 napi_disable(&bp->bnx2_napi[i].napi);
642 }
643
644 static void
645 bnx2_napi_enable(struct bnx2 *bp)
646 {
647 int i;
648
649 for (i = 0; i < bp->irq_nvecs; i++)
650 napi_enable(&bp->bnx2_napi[i].napi);
651 }
652
653 static void
654 bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic)
655 {
656 if (stop_cnic)
657 bnx2_cnic_stop(bp);
658 if (netif_running(bp->dev)) {
659 bnx2_napi_disable(bp);
660 netif_tx_disable(bp->dev);
661 }
662 bnx2_disable_int_sync(bp);
663 netif_carrier_off(bp->dev); /* prevent tx timeout */
664 }
665
666 static void
667 bnx2_netif_start(struct bnx2 *bp, bool start_cnic)
668 {
669 if (atomic_dec_and_test(&bp->intr_sem)) {
670 if (netif_running(bp->dev)) {
671 netif_tx_wake_all_queues(bp->dev);
672 spin_lock_bh(&bp->phy_lock);
673 if (bp->link_up)
674 netif_carrier_on(bp->dev);
675 spin_unlock_bh(&bp->phy_lock);
676 bnx2_napi_enable(bp);
677 bnx2_enable_int(bp);
678 if (start_cnic)
679 bnx2_cnic_start(bp);
680 }
681 }
682 }
683
684 static void
685 bnx2_free_tx_mem(struct bnx2 *bp)
686 {
687 int i;
688
689 for (i = 0; i < bp->num_tx_rings; i++) {
690 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
691 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
692
693 if (txr->tx_desc_ring) {
694 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
695 txr->tx_desc_ring,
696 txr->tx_desc_mapping);
697 txr->tx_desc_ring = NULL;
698 }
699 kfree(txr->tx_buf_ring);
700 txr->tx_buf_ring = NULL;
701 }
702 }
703
704 static void
705 bnx2_free_rx_mem(struct bnx2 *bp)
706 {
707 int i;
708
709 for (i = 0; i < bp->num_rx_rings; i++) {
710 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
711 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
712 int j;
713
714 for (j = 0; j < bp->rx_max_ring; j++) {
715 if (rxr->rx_desc_ring[j])
716 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
717 rxr->rx_desc_ring[j],
718 rxr->rx_desc_mapping[j]);
719 rxr->rx_desc_ring[j] = NULL;
720 }
721 vfree(rxr->rx_buf_ring);
722 rxr->rx_buf_ring = NULL;
723
724 for (j = 0; j < bp->rx_max_pg_ring; j++) {
725 if (rxr->rx_pg_desc_ring[j])
726 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
727 rxr->rx_pg_desc_ring[j],
728 rxr->rx_pg_desc_mapping[j]);
729 rxr->rx_pg_desc_ring[j] = NULL;
730 }
731 vfree(rxr->rx_pg_ring);
732 rxr->rx_pg_ring = NULL;
733 }
734 }
735
736 static int
737 bnx2_alloc_tx_mem(struct bnx2 *bp)
738 {
739 int i;
740
741 for (i = 0; i < bp->num_tx_rings; i++) {
742 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
743 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
744
745 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
746 if (txr->tx_buf_ring == NULL)
747 return -ENOMEM;
748
749 txr->tx_desc_ring =
750 pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
751 &txr->tx_desc_mapping);
752 if (txr->tx_desc_ring == NULL)
753 return -ENOMEM;
754 }
755 return 0;
756 }
757
758 static int
759 bnx2_alloc_rx_mem(struct bnx2 *bp)
760 {
761 int i;
762
763 for (i = 0; i < bp->num_rx_rings; i++) {
764 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
765 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
766 int j;
767
768 rxr->rx_buf_ring =
769 vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
770 if (rxr->rx_buf_ring == NULL)
771 return -ENOMEM;
772
773 memset(rxr->rx_buf_ring, 0,
774 SW_RXBD_RING_SIZE * bp->rx_max_ring);
775
776 for (j = 0; j < bp->rx_max_ring; j++) {
777 rxr->rx_desc_ring[j] =
778 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
779 &rxr->rx_desc_mapping[j]);
780 if (rxr->rx_desc_ring[j] == NULL)
781 return -ENOMEM;
782
783 }
784
785 if (bp->rx_pg_ring_size) {
786 rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
787 bp->rx_max_pg_ring);
788 if (rxr->rx_pg_ring == NULL)
789 return -ENOMEM;
790
791 memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
792 bp->rx_max_pg_ring);
793 }
794
795 for (j = 0; j < bp->rx_max_pg_ring; j++) {
796 rxr->rx_pg_desc_ring[j] =
797 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
798 &rxr->rx_pg_desc_mapping[j]);
799 if (rxr->rx_pg_desc_ring[j] == NULL)
800 return -ENOMEM;
801
802 }
803 }
804 return 0;
805 }
806
807 static void
808 bnx2_free_mem(struct bnx2 *bp)
809 {
810 int i;
811 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
812
813 bnx2_free_tx_mem(bp);
814 bnx2_free_rx_mem(bp);
815
816 for (i = 0; i < bp->ctx_pages; i++) {
817 if (bp->ctx_blk[i]) {
818 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
819 bp->ctx_blk[i],
820 bp->ctx_blk_mapping[i]);
821 bp->ctx_blk[i] = NULL;
822 }
823 }
824 if (bnapi->status_blk.msi) {
825 pci_free_consistent(bp->pdev, bp->status_stats_size,
826 bnapi->status_blk.msi,
827 bp->status_blk_mapping);
828 bnapi->status_blk.msi = NULL;
829 bp->stats_blk = NULL;
830 }
831 }
832
833 static int
834 bnx2_alloc_mem(struct bnx2 *bp)
835 {
836 int i, status_blk_size, err;
837 struct bnx2_napi *bnapi;
838 void *status_blk;
839
840 /* Combine status and statistics blocks into one allocation. */
841 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
842 if (bp->flags & BNX2_FLAG_MSIX_CAP)
843 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
844 BNX2_SBLK_MSIX_ALIGN_SIZE);
845 bp->status_stats_size = status_blk_size +
846 sizeof(struct statistics_block);
847
848 status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
849 &bp->status_blk_mapping);
850 if (status_blk == NULL)
851 goto alloc_mem_err;
852
853 memset(status_blk, 0, bp->status_stats_size);
854
855 bnapi = &bp->bnx2_napi[0];
856 bnapi->status_blk.msi = status_blk;
857 bnapi->hw_tx_cons_ptr =
858 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
859 bnapi->hw_rx_cons_ptr =
860 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
861 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
862 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
863 struct status_block_msix *sblk;
864
865 bnapi = &bp->bnx2_napi[i];
866
867 sblk = (void *) (status_blk +
868 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
869 bnapi->status_blk.msix = sblk;
870 bnapi->hw_tx_cons_ptr =
871 &sblk->status_tx_quick_consumer_index;
872 bnapi->hw_rx_cons_ptr =
873 &sblk->status_rx_quick_consumer_index;
874 bnapi->int_num = i << 24;
875 }
876 }
877
878 bp->stats_blk = status_blk + status_blk_size;
879
880 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
881
882 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
883 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
884 if (bp->ctx_pages == 0)
885 bp->ctx_pages = 1;
886 for (i = 0; i < bp->ctx_pages; i++) {
887 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
888 BCM_PAGE_SIZE,
889 &bp->ctx_blk_mapping[i]);
890 if (bp->ctx_blk[i] == NULL)
891 goto alloc_mem_err;
892 }
893 }
894
895 err = bnx2_alloc_rx_mem(bp);
896 if (err)
897 goto alloc_mem_err;
898
899 err = bnx2_alloc_tx_mem(bp);
900 if (err)
901 goto alloc_mem_err;
902
903 return 0;
904
905 alloc_mem_err:
906 bnx2_free_mem(bp);
907 return -ENOMEM;
908 }
909
910 static void
911 bnx2_report_fw_link(struct bnx2 *bp)
912 {
913 u32 fw_link_status = 0;
914
915 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
916 return;
917
918 if (bp->link_up) {
919 u32 bmsr;
920
921 switch (bp->line_speed) {
922 case SPEED_10:
923 if (bp->duplex == DUPLEX_HALF)
924 fw_link_status = BNX2_LINK_STATUS_10HALF;
925 else
926 fw_link_status = BNX2_LINK_STATUS_10FULL;
927 break;
928 case SPEED_100:
929 if (bp->duplex == DUPLEX_HALF)
930 fw_link_status = BNX2_LINK_STATUS_100HALF;
931 else
932 fw_link_status = BNX2_LINK_STATUS_100FULL;
933 break;
934 case SPEED_1000:
935 if (bp->duplex == DUPLEX_HALF)
936 fw_link_status = BNX2_LINK_STATUS_1000HALF;
937 else
938 fw_link_status = BNX2_LINK_STATUS_1000FULL;
939 break;
940 case SPEED_2500:
941 if (bp->duplex == DUPLEX_HALF)
942 fw_link_status = BNX2_LINK_STATUS_2500HALF;
943 else
944 fw_link_status = BNX2_LINK_STATUS_2500FULL;
945 break;
946 }
947
948 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
949
950 if (bp->autoneg) {
951 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
952
953 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
954 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
955
956 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
957 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
958 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
959 else
960 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
961 }
962 }
963 else
964 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
965
966 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
967 }
968
969 static char *
970 bnx2_xceiver_str(struct bnx2 *bp)
971 {
972 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
973 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
974 "Copper"));
975 }
976
977 static void
978 bnx2_report_link(struct bnx2 *bp)
979 {
980 if (bp->link_up) {
981 netif_carrier_on(bp->dev);
982 netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex",
983 bnx2_xceiver_str(bp),
984 bp->line_speed,
985 bp->duplex == DUPLEX_FULL ? "full" : "half");
986
987 if (bp->flow_ctrl) {
988 if (bp->flow_ctrl & FLOW_CTRL_RX) {
989 pr_cont(", receive ");
990 if (bp->flow_ctrl & FLOW_CTRL_TX)
991 pr_cont("& transmit ");
992 }
993 else {
994 pr_cont(", transmit ");
995 }
996 pr_cont("flow control ON");
997 }
998 pr_cont("\n");
999 } else {
1000 netif_carrier_off(bp->dev);
1001 netdev_err(bp->dev, "NIC %s Link is Down\n",
1002 bnx2_xceiver_str(bp));
1003 }
1004
1005 bnx2_report_fw_link(bp);
1006 }
1007
1008 static void
1009 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
1010 {
1011 u32 local_adv, remote_adv;
1012
1013 bp->flow_ctrl = 0;
1014 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1015 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1016
1017 if (bp->duplex == DUPLEX_FULL) {
1018 bp->flow_ctrl = bp->req_flow_ctrl;
1019 }
1020 return;
1021 }
1022
1023 if (bp->duplex != DUPLEX_FULL) {
1024 return;
1025 }
1026
1027 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1028 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
1029 u32 val;
1030
1031 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1032 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
1033 bp->flow_ctrl |= FLOW_CTRL_TX;
1034 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
1035 bp->flow_ctrl |= FLOW_CTRL_RX;
1036 return;
1037 }
1038
1039 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1040 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1041
1042 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1043 u32 new_local_adv = 0;
1044 u32 new_remote_adv = 0;
1045
1046 if (local_adv & ADVERTISE_1000XPAUSE)
1047 new_local_adv |= ADVERTISE_PAUSE_CAP;
1048 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1049 new_local_adv |= ADVERTISE_PAUSE_ASYM;
1050 if (remote_adv & ADVERTISE_1000XPAUSE)
1051 new_remote_adv |= ADVERTISE_PAUSE_CAP;
1052 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
1053 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
1054
1055 local_adv = new_local_adv;
1056 remote_adv = new_remote_adv;
1057 }
1058
1059 /* See Table 28B-3 of 802.3ab-1999 spec. */
1060 if (local_adv & ADVERTISE_PAUSE_CAP) {
1061 if(local_adv & ADVERTISE_PAUSE_ASYM) {
1062 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1063 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1064 }
1065 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
1066 bp->flow_ctrl = FLOW_CTRL_RX;
1067 }
1068 }
1069 else {
1070 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1071 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1072 }
1073 }
1074 }
1075 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1076 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
1077 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
1078
1079 bp->flow_ctrl = FLOW_CTRL_TX;
1080 }
1081 }
1082 }
1083
1084 static int
1085 bnx2_5709s_linkup(struct bnx2 *bp)
1086 {
1087 u32 val, speed;
1088
1089 bp->link_up = 1;
1090
1091 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
1092 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
1093 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1094
1095 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
1096 bp->line_speed = bp->req_line_speed;
1097 bp->duplex = bp->req_duplex;
1098 return 0;
1099 }
1100 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
1101 switch (speed) {
1102 case MII_BNX2_GP_TOP_AN_SPEED_10:
1103 bp->line_speed = SPEED_10;
1104 break;
1105 case MII_BNX2_GP_TOP_AN_SPEED_100:
1106 bp->line_speed = SPEED_100;
1107 break;
1108 case MII_BNX2_GP_TOP_AN_SPEED_1G:
1109 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
1110 bp->line_speed = SPEED_1000;
1111 break;
1112 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
1113 bp->line_speed = SPEED_2500;
1114 break;
1115 }
1116 if (val & MII_BNX2_GP_TOP_AN_FD)
1117 bp->duplex = DUPLEX_FULL;
1118 else
1119 bp->duplex = DUPLEX_HALF;
1120 return 0;
1121 }
1122
1123 static int
1124 bnx2_5708s_linkup(struct bnx2 *bp)
1125 {
1126 u32 val;
1127
1128 bp->link_up = 1;
1129 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1130 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
1131 case BCM5708S_1000X_STAT1_SPEED_10:
1132 bp->line_speed = SPEED_10;
1133 break;
1134 case BCM5708S_1000X_STAT1_SPEED_100:
1135 bp->line_speed = SPEED_100;
1136 break;
1137 case BCM5708S_1000X_STAT1_SPEED_1G:
1138 bp->line_speed = SPEED_1000;
1139 break;
1140 case BCM5708S_1000X_STAT1_SPEED_2G5:
1141 bp->line_speed = SPEED_2500;
1142 break;
1143 }
1144 if (val & BCM5708S_1000X_STAT1_FD)
1145 bp->duplex = DUPLEX_FULL;
1146 else
1147 bp->duplex = DUPLEX_HALF;
1148
1149 return 0;
1150 }
1151
1152 static int
1153 bnx2_5706s_linkup(struct bnx2 *bp)
1154 {
1155 u32 bmcr, local_adv, remote_adv, common;
1156
1157 bp->link_up = 1;
1158 bp->line_speed = SPEED_1000;
1159
1160 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1161 if (bmcr & BMCR_FULLDPLX) {
1162 bp->duplex = DUPLEX_FULL;
1163 }
1164 else {
1165 bp->duplex = DUPLEX_HALF;
1166 }
1167
1168 if (!(bmcr & BMCR_ANENABLE)) {
1169 return 0;
1170 }
1171
1172 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1173 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1174
1175 common = local_adv & remote_adv;
1176 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1177
1178 if (common & ADVERTISE_1000XFULL) {
1179 bp->duplex = DUPLEX_FULL;
1180 }
1181 else {
1182 bp->duplex = DUPLEX_HALF;
1183 }
1184 }
1185
1186 return 0;
1187 }
1188
1189 static int
1190 bnx2_copper_linkup(struct bnx2 *bp)
1191 {
1192 u32 bmcr;
1193
1194 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1195 if (bmcr & BMCR_ANENABLE) {
1196 u32 local_adv, remote_adv, common;
1197
1198 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1199 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1200
1201 common = local_adv & (remote_adv >> 2);
1202 if (common & ADVERTISE_1000FULL) {
1203 bp->line_speed = SPEED_1000;
1204 bp->duplex = DUPLEX_FULL;
1205 }
1206 else if (common & ADVERTISE_1000HALF) {
1207 bp->line_speed = SPEED_1000;
1208 bp->duplex = DUPLEX_HALF;
1209 }
1210 else {
1211 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1212 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1213
1214 common = local_adv & remote_adv;
1215 if (common & ADVERTISE_100FULL) {
1216 bp->line_speed = SPEED_100;
1217 bp->duplex = DUPLEX_FULL;
1218 }
1219 else if (common & ADVERTISE_100HALF) {
1220 bp->line_speed = SPEED_100;
1221 bp->duplex = DUPLEX_HALF;
1222 }
1223 else if (common & ADVERTISE_10FULL) {
1224 bp->line_speed = SPEED_10;
1225 bp->duplex = DUPLEX_FULL;
1226 }
1227 else if (common & ADVERTISE_10HALF) {
1228 bp->line_speed = SPEED_10;
1229 bp->duplex = DUPLEX_HALF;
1230 }
1231 else {
1232 bp->line_speed = 0;
1233 bp->link_up = 0;
1234 }
1235 }
1236 }
1237 else {
1238 if (bmcr & BMCR_SPEED100) {
1239 bp->line_speed = SPEED_100;
1240 }
1241 else {
1242 bp->line_speed = SPEED_10;
1243 }
1244 if (bmcr & BMCR_FULLDPLX) {
1245 bp->duplex = DUPLEX_FULL;
1246 }
1247 else {
1248 bp->duplex = DUPLEX_HALF;
1249 }
1250 }
1251
1252 return 0;
1253 }
1254
1255 static void
1256 bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
1257 {
1258 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1259
1260 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1261 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1262 val |= 0x02 << 8;
1263
1264 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1265 u32 lo_water, hi_water;
1266
1267 if (bp->flow_ctrl & FLOW_CTRL_TX)
1268 lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1269 else
1270 lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1271 if (lo_water >= bp->rx_ring_size)
1272 lo_water = 0;
1273
1274 hi_water = min_t(int, bp->rx_ring_size / 4, lo_water + 16);
1275
1276 if (hi_water <= lo_water)
1277 lo_water = 0;
1278
1279 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1280 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1281
1282 if (hi_water > 0xf)
1283 hi_water = 0xf;
1284 else if (hi_water == 0)
1285 lo_water = 0;
1286 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1287 }
1288 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1289 }
1290
1291 static void
1292 bnx2_init_all_rx_contexts(struct bnx2 *bp)
1293 {
1294 int i;
1295 u32 cid;
1296
1297 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1298 if (i == 1)
1299 cid = RX_RSS_CID;
1300 bnx2_init_rx_context(bp, cid);
1301 }
1302 }
1303
1304 static void
1305 bnx2_set_mac_link(struct bnx2 *bp)
1306 {
1307 u32 val;
1308
1309 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1310 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1311 (bp->duplex == DUPLEX_HALF)) {
1312 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1313 }
1314
1315 /* Configure the EMAC mode register. */
1316 val = REG_RD(bp, BNX2_EMAC_MODE);
1317
1318 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1319 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1320 BNX2_EMAC_MODE_25G_MODE);
1321
1322 if (bp->link_up) {
1323 switch (bp->line_speed) {
1324 case SPEED_10:
1325 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1326 val |= BNX2_EMAC_MODE_PORT_MII_10M;
1327 break;
1328 }
1329 /* fall through */
1330 case SPEED_100:
1331 val |= BNX2_EMAC_MODE_PORT_MII;
1332 break;
1333 case SPEED_2500:
1334 val |= BNX2_EMAC_MODE_25G_MODE;
1335 /* fall through */
1336 case SPEED_1000:
1337 val |= BNX2_EMAC_MODE_PORT_GMII;
1338 break;
1339 }
1340 }
1341 else {
1342 val |= BNX2_EMAC_MODE_PORT_GMII;
1343 }
1344
1345 /* Set the MAC to operate in the appropriate duplex mode. */
1346 if (bp->duplex == DUPLEX_HALF)
1347 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1348 REG_WR(bp, BNX2_EMAC_MODE, val);
1349
1350 /* Enable/disable rx PAUSE. */
1351 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1352
1353 if (bp->flow_ctrl & FLOW_CTRL_RX)
1354 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1355 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1356
1357 /* Enable/disable tx PAUSE. */
1358 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1359 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1360
1361 if (bp->flow_ctrl & FLOW_CTRL_TX)
1362 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1363 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1364
1365 /* Acknowledge the interrupt. */
1366 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1367
1368 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1369 bnx2_init_all_rx_contexts(bp);
1370 }
1371
1372 static void
1373 bnx2_enable_bmsr1(struct bnx2 *bp)
1374 {
1375 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1376 (CHIP_NUM(bp) == CHIP_NUM_5709))
1377 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1378 MII_BNX2_BLK_ADDR_GP_STATUS);
1379 }
1380
1381 static void
1382 bnx2_disable_bmsr1(struct bnx2 *bp)
1383 {
1384 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1385 (CHIP_NUM(bp) == CHIP_NUM_5709))
1386 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1387 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1388 }
1389
1390 static int
1391 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1392 {
1393 u32 up1;
1394 int ret = 1;
1395
1396 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1397 return 0;
1398
1399 if (bp->autoneg & AUTONEG_SPEED)
1400 bp->advertising |= ADVERTISED_2500baseX_Full;
1401
1402 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1403 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1404
1405 bnx2_read_phy(bp, bp->mii_up1, &up1);
1406 if (!(up1 & BCM5708S_UP1_2G5)) {
1407 up1 |= BCM5708S_UP1_2G5;
1408 bnx2_write_phy(bp, bp->mii_up1, up1);
1409 ret = 0;
1410 }
1411
1412 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1413 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1414 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1415
1416 return ret;
1417 }
1418
1419 static int
1420 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1421 {
1422 u32 up1;
1423 int ret = 0;
1424
1425 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1426 return 0;
1427
1428 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1429 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1430
1431 bnx2_read_phy(bp, bp->mii_up1, &up1);
1432 if (up1 & BCM5708S_UP1_2G5) {
1433 up1 &= ~BCM5708S_UP1_2G5;
1434 bnx2_write_phy(bp, bp->mii_up1, up1);
1435 ret = 1;
1436 }
1437
1438 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1439 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1440 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1441
1442 return ret;
1443 }
1444
1445 static void
1446 bnx2_enable_forced_2g5(struct bnx2 *bp)
1447 {
1448 u32 bmcr;
1449
1450 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1451 return;
1452
1453 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1454 u32 val;
1455
1456 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1457 MII_BNX2_BLK_ADDR_SERDES_DIG);
1458 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1459 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1460 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1461 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1462
1463 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1464 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1465 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1466
1467 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1468 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1469 bmcr |= BCM5708S_BMCR_FORCE_2500;
1470 } else {
1471 return;
1472 }
1473
1474 if (bp->autoneg & AUTONEG_SPEED) {
1475 bmcr &= ~BMCR_ANENABLE;
1476 if (bp->req_duplex == DUPLEX_FULL)
1477 bmcr |= BMCR_FULLDPLX;
1478 }
1479 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1480 }
1481
1482 static void
1483 bnx2_disable_forced_2g5(struct bnx2 *bp)
1484 {
1485 u32 bmcr;
1486
1487 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1488 return;
1489
1490 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1491 u32 val;
1492
1493 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1494 MII_BNX2_BLK_ADDR_SERDES_DIG);
1495 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1496 val &= ~MII_BNX2_SD_MISC1_FORCE;
1497 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1498
1499 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1500 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1501 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1502
1503 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1504 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1505 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1506 } else {
1507 return;
1508 }
1509
1510 if (bp->autoneg & AUTONEG_SPEED)
1511 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1512 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1513 }
1514
1515 static void
1516 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1517 {
1518 u32 val;
1519
1520 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1521 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1522 if (start)
1523 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1524 else
1525 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1526 }
1527
1528 static int
1529 bnx2_set_link(struct bnx2 *bp)
1530 {
1531 u32 bmsr;
1532 u8 link_up;
1533
1534 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1535 bp->link_up = 1;
1536 return 0;
1537 }
1538
1539 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1540 return 0;
1541
1542 link_up = bp->link_up;
1543
1544 bnx2_enable_bmsr1(bp);
1545 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1546 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1547 bnx2_disable_bmsr1(bp);
1548
1549 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1550 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1551 u32 val, an_dbg;
1552
1553 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1554 bnx2_5706s_force_link_dn(bp, 0);
1555 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1556 }
1557 val = REG_RD(bp, BNX2_EMAC_STATUS);
1558
1559 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1560 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1561 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1562
1563 if ((val & BNX2_EMAC_STATUS_LINK) &&
1564 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1565 bmsr |= BMSR_LSTATUS;
1566 else
1567 bmsr &= ~BMSR_LSTATUS;
1568 }
1569
1570 if (bmsr & BMSR_LSTATUS) {
1571 bp->link_up = 1;
1572
1573 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1574 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1575 bnx2_5706s_linkup(bp);
1576 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1577 bnx2_5708s_linkup(bp);
1578 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1579 bnx2_5709s_linkup(bp);
1580 }
1581 else {
1582 bnx2_copper_linkup(bp);
1583 }
1584 bnx2_resolve_flow_ctrl(bp);
1585 }
1586 else {
1587 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1588 (bp->autoneg & AUTONEG_SPEED))
1589 bnx2_disable_forced_2g5(bp);
1590
1591 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1592 u32 bmcr;
1593
1594 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1595 bmcr |= BMCR_ANENABLE;
1596 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1597
1598 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1599 }
1600 bp->link_up = 0;
1601 }
1602
1603 if (bp->link_up != link_up) {
1604 bnx2_report_link(bp);
1605 }
1606
1607 bnx2_set_mac_link(bp);
1608
1609 return 0;
1610 }
1611
1612 static int
1613 bnx2_reset_phy(struct bnx2 *bp)
1614 {
1615 int i;
1616 u32 reg;
1617
1618 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1619
1620 #define PHY_RESET_MAX_WAIT 100
1621 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1622 udelay(10);
1623
1624 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
1625 if (!(reg & BMCR_RESET)) {
1626 udelay(20);
1627 break;
1628 }
1629 }
1630 if (i == PHY_RESET_MAX_WAIT) {
1631 return -EBUSY;
1632 }
1633 return 0;
1634 }
1635
1636 static u32
1637 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1638 {
1639 u32 adv = 0;
1640
1641 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1642 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1643
1644 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1645 adv = ADVERTISE_1000XPAUSE;
1646 }
1647 else {
1648 adv = ADVERTISE_PAUSE_CAP;
1649 }
1650 }
1651 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1652 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1653 adv = ADVERTISE_1000XPSE_ASYM;
1654 }
1655 else {
1656 adv = ADVERTISE_PAUSE_ASYM;
1657 }
1658 }
1659 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1660 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1661 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1662 }
1663 else {
1664 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1665 }
1666 }
1667 return adv;
1668 }
1669
1670 static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
1671
1672 static int
1673 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1674 __releases(&bp->phy_lock)
1675 __acquires(&bp->phy_lock)
1676 {
1677 u32 speed_arg = 0, pause_adv;
1678
1679 pause_adv = bnx2_phy_get_pause_adv(bp);
1680
1681 if (bp->autoneg & AUTONEG_SPEED) {
1682 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1683 if (bp->advertising & ADVERTISED_10baseT_Half)
1684 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1685 if (bp->advertising & ADVERTISED_10baseT_Full)
1686 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1687 if (bp->advertising & ADVERTISED_100baseT_Half)
1688 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1689 if (bp->advertising & ADVERTISED_100baseT_Full)
1690 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1691 if (bp->advertising & ADVERTISED_1000baseT_Full)
1692 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1693 if (bp->advertising & ADVERTISED_2500baseX_Full)
1694 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1695 } else {
1696 if (bp->req_line_speed == SPEED_2500)
1697 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1698 else if (bp->req_line_speed == SPEED_1000)
1699 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1700 else if (bp->req_line_speed == SPEED_100) {
1701 if (bp->req_duplex == DUPLEX_FULL)
1702 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1703 else
1704 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1705 } else if (bp->req_line_speed == SPEED_10) {
1706 if (bp->req_duplex == DUPLEX_FULL)
1707 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1708 else
1709 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1710 }
1711 }
1712
1713 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1714 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1715 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1716 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1717
1718 if (port == PORT_TP)
1719 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1720 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1721
1722 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1723
1724 spin_unlock_bh(&bp->phy_lock);
1725 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1726 spin_lock_bh(&bp->phy_lock);
1727
1728 return 0;
1729 }
1730
1731 static int
1732 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1733 __releases(&bp->phy_lock)
1734 __acquires(&bp->phy_lock)
1735 {
1736 u32 adv, bmcr;
1737 u32 new_adv = 0;
1738
1739 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1740 return (bnx2_setup_remote_phy(bp, port));
1741
1742 if (!(bp->autoneg & AUTONEG_SPEED)) {
1743 u32 new_bmcr;
1744 int force_link_down = 0;
1745
1746 if (bp->req_line_speed == SPEED_2500) {
1747 if (!bnx2_test_and_enable_2g5(bp))
1748 force_link_down = 1;
1749 } else if (bp->req_line_speed == SPEED_1000) {
1750 if (bnx2_test_and_disable_2g5(bp))
1751 force_link_down = 1;
1752 }
1753 bnx2_read_phy(bp, bp->mii_adv, &adv);
1754 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1755
1756 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1757 new_bmcr = bmcr & ~BMCR_ANENABLE;
1758 new_bmcr |= BMCR_SPEED1000;
1759
1760 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1761 if (bp->req_line_speed == SPEED_2500)
1762 bnx2_enable_forced_2g5(bp);
1763 else if (bp->req_line_speed == SPEED_1000) {
1764 bnx2_disable_forced_2g5(bp);
1765 new_bmcr &= ~0x2000;
1766 }
1767
1768 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1769 if (bp->req_line_speed == SPEED_2500)
1770 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1771 else
1772 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1773 }
1774
1775 if (bp->req_duplex == DUPLEX_FULL) {
1776 adv |= ADVERTISE_1000XFULL;
1777 new_bmcr |= BMCR_FULLDPLX;
1778 }
1779 else {
1780 adv |= ADVERTISE_1000XHALF;
1781 new_bmcr &= ~BMCR_FULLDPLX;
1782 }
1783 if ((new_bmcr != bmcr) || (force_link_down)) {
1784 /* Force a link down visible on the other side */
1785 if (bp->link_up) {
1786 bnx2_write_phy(bp, bp->mii_adv, adv &
1787 ~(ADVERTISE_1000XFULL |
1788 ADVERTISE_1000XHALF));
1789 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1790 BMCR_ANRESTART | BMCR_ANENABLE);
1791
1792 bp->link_up = 0;
1793 netif_carrier_off(bp->dev);
1794 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1795 bnx2_report_link(bp);
1796 }
1797 bnx2_write_phy(bp, bp->mii_adv, adv);
1798 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1799 } else {
1800 bnx2_resolve_flow_ctrl(bp);
1801 bnx2_set_mac_link(bp);
1802 }
1803 return 0;
1804 }
1805
1806 bnx2_test_and_enable_2g5(bp);
1807
1808 if (bp->advertising & ADVERTISED_1000baseT_Full)
1809 new_adv |= ADVERTISE_1000XFULL;
1810
1811 new_adv |= bnx2_phy_get_pause_adv(bp);
1812
1813 bnx2_read_phy(bp, bp->mii_adv, &adv);
1814 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1815
1816 bp->serdes_an_pending = 0;
1817 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1818 /* Force a link down visible on the other side */
1819 if (bp->link_up) {
1820 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1821 spin_unlock_bh(&bp->phy_lock);
1822 msleep(20);
1823 spin_lock_bh(&bp->phy_lock);
1824 }
1825
1826 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1827 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1828 BMCR_ANENABLE);
1829 /* Speed up link-up time when the link partner
1830 * does not autonegotiate which is very common
1831 * in blade servers. Some blade servers use
1832 * IPMI for kerboard input and it's important
1833 * to minimize link disruptions. Autoneg. involves
1834 * exchanging base pages plus 3 next pages and
1835 * normally completes in about 120 msec.
1836 */
1837 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
1838 bp->serdes_an_pending = 1;
1839 mod_timer(&bp->timer, jiffies + bp->current_interval);
1840 } else {
1841 bnx2_resolve_flow_ctrl(bp);
1842 bnx2_set_mac_link(bp);
1843 }
1844
1845 return 0;
1846 }
1847
1848 #define ETHTOOL_ALL_FIBRE_SPEED \
1849 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
1850 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1851 (ADVERTISED_1000baseT_Full)
1852
1853 #define ETHTOOL_ALL_COPPER_SPEED \
1854 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1855 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1856 ADVERTISED_1000baseT_Full)
1857
1858 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1859 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1860
1861 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1862
1863 static void
1864 bnx2_set_default_remote_link(struct bnx2 *bp)
1865 {
1866 u32 link;
1867
1868 if (bp->phy_port == PORT_TP)
1869 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1870 else
1871 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1872
1873 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1874 bp->req_line_speed = 0;
1875 bp->autoneg |= AUTONEG_SPEED;
1876 bp->advertising = ADVERTISED_Autoneg;
1877 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1878 bp->advertising |= ADVERTISED_10baseT_Half;
1879 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1880 bp->advertising |= ADVERTISED_10baseT_Full;
1881 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1882 bp->advertising |= ADVERTISED_100baseT_Half;
1883 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1884 bp->advertising |= ADVERTISED_100baseT_Full;
1885 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1886 bp->advertising |= ADVERTISED_1000baseT_Full;
1887 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1888 bp->advertising |= ADVERTISED_2500baseX_Full;
1889 } else {
1890 bp->autoneg = 0;
1891 bp->advertising = 0;
1892 bp->req_duplex = DUPLEX_FULL;
1893 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1894 bp->req_line_speed = SPEED_10;
1895 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1896 bp->req_duplex = DUPLEX_HALF;
1897 }
1898 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1899 bp->req_line_speed = SPEED_100;
1900 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1901 bp->req_duplex = DUPLEX_HALF;
1902 }
1903 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1904 bp->req_line_speed = SPEED_1000;
1905 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1906 bp->req_line_speed = SPEED_2500;
1907 }
1908 }
1909
1910 static void
1911 bnx2_set_default_link(struct bnx2 *bp)
1912 {
1913 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1914 bnx2_set_default_remote_link(bp);
1915 return;
1916 }
1917
1918 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1919 bp->req_line_speed = 0;
1920 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1921 u32 reg;
1922
1923 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1924
1925 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1926 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1927 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1928 bp->autoneg = 0;
1929 bp->req_line_speed = bp->line_speed = SPEED_1000;
1930 bp->req_duplex = DUPLEX_FULL;
1931 }
1932 } else
1933 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1934 }
1935
1936 static void
1937 bnx2_send_heart_beat(struct bnx2 *bp)
1938 {
1939 u32 msg;
1940 u32 addr;
1941
1942 spin_lock(&bp->indirect_lock);
1943 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1944 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1945 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1946 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1947 spin_unlock(&bp->indirect_lock);
1948 }
1949
1950 static void
1951 bnx2_remote_phy_event(struct bnx2 *bp)
1952 {
1953 u32 msg;
1954 u8 link_up = bp->link_up;
1955 u8 old_port;
1956
1957 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1958
1959 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1960 bnx2_send_heart_beat(bp);
1961
1962 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1963
1964 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1965 bp->link_up = 0;
1966 else {
1967 u32 speed;
1968
1969 bp->link_up = 1;
1970 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1971 bp->duplex = DUPLEX_FULL;
1972 switch (speed) {
1973 case BNX2_LINK_STATUS_10HALF:
1974 bp->duplex = DUPLEX_HALF;
1975 case BNX2_LINK_STATUS_10FULL:
1976 bp->line_speed = SPEED_10;
1977 break;
1978 case BNX2_LINK_STATUS_100HALF:
1979 bp->duplex = DUPLEX_HALF;
1980 case BNX2_LINK_STATUS_100BASE_T4:
1981 case BNX2_LINK_STATUS_100FULL:
1982 bp->line_speed = SPEED_100;
1983 break;
1984 case BNX2_LINK_STATUS_1000HALF:
1985 bp->duplex = DUPLEX_HALF;
1986 case BNX2_LINK_STATUS_1000FULL:
1987 bp->line_speed = SPEED_1000;
1988 break;
1989 case BNX2_LINK_STATUS_2500HALF:
1990 bp->duplex = DUPLEX_HALF;
1991 case BNX2_LINK_STATUS_2500FULL:
1992 bp->line_speed = SPEED_2500;
1993 break;
1994 default:
1995 bp->line_speed = 0;
1996 break;
1997 }
1998
1999 bp->flow_ctrl = 0;
2000 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
2001 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
2002 if (bp->duplex == DUPLEX_FULL)
2003 bp->flow_ctrl = bp->req_flow_ctrl;
2004 } else {
2005 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
2006 bp->flow_ctrl |= FLOW_CTRL_TX;
2007 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
2008 bp->flow_ctrl |= FLOW_CTRL_RX;
2009 }
2010
2011 old_port = bp->phy_port;
2012 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
2013 bp->phy_port = PORT_FIBRE;
2014 else
2015 bp->phy_port = PORT_TP;
2016
2017 if (old_port != bp->phy_port)
2018 bnx2_set_default_link(bp);
2019
2020 }
2021 if (bp->link_up != link_up)
2022 bnx2_report_link(bp);
2023
2024 bnx2_set_mac_link(bp);
2025 }
2026
2027 static int
2028 bnx2_set_remote_link(struct bnx2 *bp)
2029 {
2030 u32 evt_code;
2031
2032 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
2033 switch (evt_code) {
2034 case BNX2_FW_EVT_CODE_LINK_EVENT:
2035 bnx2_remote_phy_event(bp);
2036 break;
2037 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
2038 default:
2039 bnx2_send_heart_beat(bp);
2040 break;
2041 }
2042 return 0;
2043 }
2044
2045 static int
2046 bnx2_setup_copper_phy(struct bnx2 *bp)
2047 __releases(&bp->phy_lock)
2048 __acquires(&bp->phy_lock)
2049 {
2050 u32 bmcr;
2051 u32 new_bmcr;
2052
2053 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
2054
2055 if (bp->autoneg & AUTONEG_SPEED) {
2056 u32 adv_reg, adv1000_reg;
2057 u32 new_adv_reg = 0;
2058 u32 new_adv1000_reg = 0;
2059
2060 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
2061 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
2062 ADVERTISE_PAUSE_ASYM);
2063
2064 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
2065 adv1000_reg &= PHY_ALL_1000_SPEED;
2066
2067 if (bp->advertising & ADVERTISED_10baseT_Half)
2068 new_adv_reg |= ADVERTISE_10HALF;
2069 if (bp->advertising & ADVERTISED_10baseT_Full)
2070 new_adv_reg |= ADVERTISE_10FULL;
2071 if (bp->advertising & ADVERTISED_100baseT_Half)
2072 new_adv_reg |= ADVERTISE_100HALF;
2073 if (bp->advertising & ADVERTISED_100baseT_Full)
2074 new_adv_reg |= ADVERTISE_100FULL;
2075 if (bp->advertising & ADVERTISED_1000baseT_Full)
2076 new_adv1000_reg |= ADVERTISE_1000FULL;
2077
2078 new_adv_reg |= ADVERTISE_CSMA;
2079
2080 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
2081
2082 if ((adv1000_reg != new_adv1000_reg) ||
2083 (adv_reg != new_adv_reg) ||
2084 ((bmcr & BMCR_ANENABLE) == 0)) {
2085
2086 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
2087 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
2088 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
2089 BMCR_ANENABLE);
2090 }
2091 else if (bp->link_up) {
2092 /* Flow ctrl may have changed from auto to forced */
2093 /* or vice-versa. */
2094
2095 bnx2_resolve_flow_ctrl(bp);
2096 bnx2_set_mac_link(bp);
2097 }
2098 return 0;
2099 }
2100
2101 new_bmcr = 0;
2102 if (bp->req_line_speed == SPEED_100) {
2103 new_bmcr |= BMCR_SPEED100;
2104 }
2105 if (bp->req_duplex == DUPLEX_FULL) {
2106 new_bmcr |= BMCR_FULLDPLX;
2107 }
2108 if (new_bmcr != bmcr) {
2109 u32 bmsr;
2110
2111 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2112 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2113
2114 if (bmsr & BMSR_LSTATUS) {
2115 /* Force link down */
2116 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
2117 spin_unlock_bh(&bp->phy_lock);
2118 msleep(50);
2119 spin_lock_bh(&bp->phy_lock);
2120
2121 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2122 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2123 }
2124
2125 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
2126
2127 /* Normally, the new speed is setup after the link has
2128 * gone down and up again. In some cases, link will not go
2129 * down so we need to set up the new speed here.
2130 */
2131 if (bmsr & BMSR_LSTATUS) {
2132 bp->line_speed = bp->req_line_speed;
2133 bp->duplex = bp->req_duplex;
2134 bnx2_resolve_flow_ctrl(bp);
2135 bnx2_set_mac_link(bp);
2136 }
2137 } else {
2138 bnx2_resolve_flow_ctrl(bp);
2139 bnx2_set_mac_link(bp);
2140 }
2141 return 0;
2142 }
2143
2144 static int
2145 bnx2_setup_phy(struct bnx2 *bp, u8 port)
2146 __releases(&bp->phy_lock)
2147 __acquires(&bp->phy_lock)
2148 {
2149 if (bp->loopback == MAC_LOOPBACK)
2150 return 0;
2151
2152 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2153 return (bnx2_setup_serdes_phy(bp, port));
2154 }
2155 else {
2156 return (bnx2_setup_copper_phy(bp));
2157 }
2158 }
2159
2160 static int
2161 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
2162 {
2163 u32 val;
2164
2165 bp->mii_bmcr = MII_BMCR + 0x10;
2166 bp->mii_bmsr = MII_BMSR + 0x10;
2167 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
2168 bp->mii_adv = MII_ADVERTISE + 0x10;
2169 bp->mii_lpa = MII_LPA + 0x10;
2170 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
2171
2172 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2173 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2174
2175 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2176 if (reset_phy)
2177 bnx2_reset_phy(bp);
2178
2179 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2180
2181 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2182 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2183 val |= MII_BNX2_SD_1000XCTL1_FIBER;
2184 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2185
2186 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2187 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2188 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
2189 val |= BCM5708S_UP1_2G5;
2190 else
2191 val &= ~BCM5708S_UP1_2G5;
2192 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2193
2194 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2195 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2196 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2197 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2198
2199 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2200
2201 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2202 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2203 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2204
2205 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2206
2207 return 0;
2208 }
2209
2210 static int
2211 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
2212 {
2213 u32 val;
2214
2215 if (reset_phy)
2216 bnx2_reset_phy(bp);
2217
2218 bp->mii_up1 = BCM5708S_UP1;
2219
2220 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2221 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2222 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2223
2224 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2225 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2226 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2227
2228 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2229 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2230 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2231
2232 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
2233 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2234 val |= BCM5708S_UP1_2G5;
2235 bnx2_write_phy(bp, BCM5708S_UP1, val);
2236 }
2237
2238 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
2239 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2240 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
2241 /* increase tx signal amplitude */
2242 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2243 BCM5708S_BLK_ADDR_TX_MISC);
2244 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2245 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2246 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2247 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2248 }
2249
2250 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2251 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2252
2253 if (val) {
2254 u32 is_backplane;
2255
2256 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
2257 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2258 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2259 BCM5708S_BLK_ADDR_TX_MISC);
2260 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2261 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2262 BCM5708S_BLK_ADDR_DIG);
2263 }
2264 }
2265 return 0;
2266 }
2267
2268 static int
2269 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
2270 {
2271 if (reset_phy)
2272 bnx2_reset_phy(bp);
2273
2274 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2275
2276 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2277 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2278
2279 if (bp->dev->mtu > 1500) {
2280 u32 val;
2281
2282 /* Set extended packet length bit */
2283 bnx2_write_phy(bp, 0x18, 0x7);
2284 bnx2_read_phy(bp, 0x18, &val);
2285 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2286
2287 bnx2_write_phy(bp, 0x1c, 0x6c00);
2288 bnx2_read_phy(bp, 0x1c, &val);
2289 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2290 }
2291 else {
2292 u32 val;
2293
2294 bnx2_write_phy(bp, 0x18, 0x7);
2295 bnx2_read_phy(bp, 0x18, &val);
2296 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2297
2298 bnx2_write_phy(bp, 0x1c, 0x6c00);
2299 bnx2_read_phy(bp, 0x1c, &val);
2300 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2301 }
2302
2303 return 0;
2304 }
2305
2306 static int
2307 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2308 {
2309 u32 val;
2310
2311 if (reset_phy)
2312 bnx2_reset_phy(bp);
2313
2314 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2315 bnx2_write_phy(bp, 0x18, 0x0c00);
2316 bnx2_write_phy(bp, 0x17, 0x000a);
2317 bnx2_write_phy(bp, 0x15, 0x310b);
2318 bnx2_write_phy(bp, 0x17, 0x201f);
2319 bnx2_write_phy(bp, 0x15, 0x9506);
2320 bnx2_write_phy(bp, 0x17, 0x401f);
2321 bnx2_write_phy(bp, 0x15, 0x14e2);
2322 bnx2_write_phy(bp, 0x18, 0x0400);
2323 }
2324
2325 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2326 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2327 MII_BNX2_DSP_EXPAND_REG | 0x8);
2328 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2329 val &= ~(1 << 8);
2330 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2331 }
2332
2333 if (bp->dev->mtu > 1500) {
2334 /* Set extended packet length bit */
2335 bnx2_write_phy(bp, 0x18, 0x7);
2336 bnx2_read_phy(bp, 0x18, &val);
2337 bnx2_write_phy(bp, 0x18, val | 0x4000);
2338
2339 bnx2_read_phy(bp, 0x10, &val);
2340 bnx2_write_phy(bp, 0x10, val | 0x1);
2341 }
2342 else {
2343 bnx2_write_phy(bp, 0x18, 0x7);
2344 bnx2_read_phy(bp, 0x18, &val);
2345 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2346
2347 bnx2_read_phy(bp, 0x10, &val);
2348 bnx2_write_phy(bp, 0x10, val & ~0x1);
2349 }
2350
2351 /* ethernet@wirespeed */
2352 bnx2_write_phy(bp, 0x18, 0x7007);
2353 bnx2_read_phy(bp, 0x18, &val);
2354 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2355 return 0;
2356 }
2357
2358
2359 static int
2360 bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2361 __releases(&bp->phy_lock)
2362 __acquires(&bp->phy_lock)
2363 {
2364 u32 val;
2365 int rc = 0;
2366
2367 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2368 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2369
2370 bp->mii_bmcr = MII_BMCR;
2371 bp->mii_bmsr = MII_BMSR;
2372 bp->mii_bmsr1 = MII_BMSR;
2373 bp->mii_adv = MII_ADVERTISE;
2374 bp->mii_lpa = MII_LPA;
2375
2376 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2377
2378 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2379 goto setup_phy;
2380
2381 bnx2_read_phy(bp, MII_PHYSID1, &val);
2382 bp->phy_id = val << 16;
2383 bnx2_read_phy(bp, MII_PHYSID2, &val);
2384 bp->phy_id |= val & 0xffff;
2385
2386 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2387 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2388 rc = bnx2_init_5706s_phy(bp, reset_phy);
2389 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2390 rc = bnx2_init_5708s_phy(bp, reset_phy);
2391 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2392 rc = bnx2_init_5709s_phy(bp, reset_phy);
2393 }
2394 else {
2395 rc = bnx2_init_copper_phy(bp, reset_phy);
2396 }
2397
2398 setup_phy:
2399 if (!rc)
2400 rc = bnx2_setup_phy(bp, bp->phy_port);
2401
2402 return rc;
2403 }
2404
2405 static int
2406 bnx2_set_mac_loopback(struct bnx2 *bp)
2407 {
2408 u32 mac_mode;
2409
2410 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2411 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2412 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2413 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2414 bp->link_up = 1;
2415 return 0;
2416 }
2417
2418 static int bnx2_test_link(struct bnx2 *);
2419
2420 static int
2421 bnx2_set_phy_loopback(struct bnx2 *bp)
2422 {
2423 u32 mac_mode;
2424 int rc, i;
2425
2426 spin_lock_bh(&bp->phy_lock);
2427 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2428 BMCR_SPEED1000);
2429 spin_unlock_bh(&bp->phy_lock);
2430 if (rc)
2431 return rc;
2432
2433 for (i = 0; i < 10; i++) {
2434 if (bnx2_test_link(bp) == 0)
2435 break;
2436 msleep(100);
2437 }
2438
2439 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2440 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2441 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2442 BNX2_EMAC_MODE_25G_MODE);
2443
2444 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2445 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2446 bp->link_up = 1;
2447 return 0;
2448 }
2449
2450 static int
2451 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2452 {
2453 int i;
2454 u32 val;
2455
2456 bp->fw_wr_seq++;
2457 msg_data |= bp->fw_wr_seq;
2458
2459 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2460
2461 if (!ack)
2462 return 0;
2463
2464 /* wait for an acknowledgement. */
2465 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
2466 msleep(10);
2467
2468 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2469
2470 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2471 break;
2472 }
2473 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2474 return 0;
2475
2476 /* If we timed out, inform the firmware that this is the case. */
2477 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2478 if (!silent)
2479 pr_err("fw sync timeout, reset code = %x\n", msg_data);
2480
2481 msg_data &= ~BNX2_DRV_MSG_CODE;
2482 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2483
2484 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2485
2486 return -EBUSY;
2487 }
2488
2489 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2490 return -EIO;
2491
2492 return 0;
2493 }
2494
2495 static int
2496 bnx2_init_5709_context(struct bnx2 *bp)
2497 {
2498 int i, ret = 0;
2499 u32 val;
2500
2501 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2502 val |= (BCM_PAGE_BITS - 8) << 16;
2503 REG_WR(bp, BNX2_CTX_COMMAND, val);
2504 for (i = 0; i < 10; i++) {
2505 val = REG_RD(bp, BNX2_CTX_COMMAND);
2506 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2507 break;
2508 udelay(2);
2509 }
2510 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2511 return -EBUSY;
2512
2513 for (i = 0; i < bp->ctx_pages; i++) {
2514 int j;
2515
2516 if (bp->ctx_blk[i])
2517 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2518 else
2519 return -ENOMEM;
2520
2521 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2522 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2523 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2524 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2525 (u64) bp->ctx_blk_mapping[i] >> 32);
2526 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2527 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2528 for (j = 0; j < 10; j++) {
2529
2530 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2531 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2532 break;
2533 udelay(5);
2534 }
2535 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2536 ret = -EBUSY;
2537 break;
2538 }
2539 }
2540 return ret;
2541 }
2542
2543 static void
2544 bnx2_init_context(struct bnx2 *bp)
2545 {
2546 u32 vcid;
2547
2548 vcid = 96;
2549 while (vcid) {
2550 u32 vcid_addr, pcid_addr, offset;
2551 int i;
2552
2553 vcid--;
2554
2555 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2556 u32 new_vcid;
2557
2558 vcid_addr = GET_PCID_ADDR(vcid);
2559 if (vcid & 0x8) {
2560 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2561 }
2562 else {
2563 new_vcid = vcid;
2564 }
2565 pcid_addr = GET_PCID_ADDR(new_vcid);
2566 }
2567 else {
2568 vcid_addr = GET_CID_ADDR(vcid);
2569 pcid_addr = vcid_addr;
2570 }
2571
2572 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2573 vcid_addr += (i << PHY_CTX_SHIFT);
2574 pcid_addr += (i << PHY_CTX_SHIFT);
2575
2576 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2577 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2578
2579 /* Zero out the context. */
2580 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2581 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2582 }
2583 }
2584 }
2585
2586 static int
2587 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2588 {
2589 u16 *good_mbuf;
2590 u32 good_mbuf_cnt;
2591 u32 val;
2592
2593 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2594 if (good_mbuf == NULL) {
2595 pr_err("Failed to allocate memory in %s\n", __func__);
2596 return -ENOMEM;
2597 }
2598
2599 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2600 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2601
2602 good_mbuf_cnt = 0;
2603
2604 /* Allocate a bunch of mbufs and save the good ones in an array. */
2605 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2606 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2607 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2608 BNX2_RBUF_COMMAND_ALLOC_REQ);
2609
2610 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2611
2612 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2613
2614 /* The addresses with Bit 9 set are bad memory blocks. */
2615 if (!(val & (1 << 9))) {
2616 good_mbuf[good_mbuf_cnt] = (u16) val;
2617 good_mbuf_cnt++;
2618 }
2619
2620 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2621 }
2622
2623 /* Free the good ones back to the mbuf pool thus discarding
2624 * all the bad ones. */
2625 while (good_mbuf_cnt) {
2626 good_mbuf_cnt--;
2627
2628 val = good_mbuf[good_mbuf_cnt];
2629 val = (val << 9) | val | 1;
2630
2631 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2632 }
2633 kfree(good_mbuf);
2634 return 0;
2635 }
2636
2637 static void
2638 bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
2639 {
2640 u32 val;
2641
2642 val = (mac_addr[0] << 8) | mac_addr[1];
2643
2644 REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2645
2646 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2647 (mac_addr[4] << 8) | mac_addr[5];
2648
2649 REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2650 }
2651
2652 static inline int
2653 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2654 {
2655 dma_addr_t mapping;
2656 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2657 struct rx_bd *rxbd =
2658 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2659 struct page *page = alloc_page(GFP_ATOMIC);
2660
2661 if (!page)
2662 return -ENOMEM;
2663 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2664 PCI_DMA_FROMDEVICE);
2665 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2666 __free_page(page);
2667 return -EIO;
2668 }
2669
2670 rx_pg->page = page;
2671 dma_unmap_addr_set(rx_pg, mapping, mapping);
2672 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2673 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2674 return 0;
2675 }
2676
2677 static void
2678 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2679 {
2680 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2681 struct page *page = rx_pg->page;
2682
2683 if (!page)
2684 return;
2685
2686 pci_unmap_page(bp->pdev, dma_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2687 PCI_DMA_FROMDEVICE);
2688
2689 __free_page(page);
2690 rx_pg->page = NULL;
2691 }
2692
2693 static inline int
2694 bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2695 {
2696 struct sk_buff *skb;
2697 struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
2698 dma_addr_t mapping;
2699 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2700 unsigned long align;
2701
2702 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2703 if (skb == NULL) {
2704 return -ENOMEM;
2705 }
2706
2707 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2708 skb_reserve(skb, BNX2_RX_ALIGN - align);
2709
2710 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2711 PCI_DMA_FROMDEVICE);
2712 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2713 dev_kfree_skb(skb);
2714 return -EIO;
2715 }
2716
2717 rx_buf->skb = skb;
2718 rx_buf->desc = (struct l2_fhdr *) skb->data;
2719 dma_unmap_addr_set(rx_buf, mapping, mapping);
2720
2721 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2722 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2723
2724 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2725
2726 return 0;
2727 }
2728
2729 static int
2730 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2731 {
2732 struct status_block *sblk = bnapi->status_blk.msi;
2733 u32 new_link_state, old_link_state;
2734 int is_set = 1;
2735
2736 new_link_state = sblk->status_attn_bits & event;
2737 old_link_state = sblk->status_attn_bits_ack & event;
2738 if (new_link_state != old_link_state) {
2739 if (new_link_state)
2740 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2741 else
2742 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2743 } else
2744 is_set = 0;
2745
2746 return is_set;
2747 }
2748
2749 static void
2750 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2751 {
2752 spin_lock(&bp->phy_lock);
2753
2754 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2755 bnx2_set_link(bp);
2756 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2757 bnx2_set_remote_link(bp);
2758
2759 spin_unlock(&bp->phy_lock);
2760
2761 }
2762
2763 static inline u16
2764 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2765 {
2766 u16 cons;
2767
2768 /* Tell compiler that status block fields can change. */
2769 barrier();
2770 cons = *bnapi->hw_tx_cons_ptr;
2771 barrier();
2772 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2773 cons++;
2774 return cons;
2775 }
2776
2777 static int
2778 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2779 {
2780 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2781 u16 hw_cons, sw_cons, sw_ring_cons;
2782 int tx_pkt = 0, index;
2783 struct netdev_queue *txq;
2784
2785 index = (bnapi - bp->bnx2_napi);
2786 txq = netdev_get_tx_queue(bp->dev, index);
2787
2788 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2789 sw_cons = txr->tx_cons;
2790
2791 while (sw_cons != hw_cons) {
2792 struct sw_tx_bd *tx_buf;
2793 struct sk_buff *skb;
2794 int i, last;
2795
2796 sw_ring_cons = TX_RING_IDX(sw_cons);
2797
2798 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
2799 skb = tx_buf->skb;
2800
2801 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
2802 prefetch(&skb->end);
2803
2804 /* partial BD completions possible with TSO packets */
2805 if (tx_buf->is_gso) {
2806 u16 last_idx, last_ring_idx;
2807
2808 last_idx = sw_cons + tx_buf->nr_frags + 1;
2809 last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1;
2810 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2811 last_idx++;
2812 }
2813 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2814 break;
2815 }
2816 }
2817
2818 pci_unmap_single(bp->pdev, dma_unmap_addr(tx_buf, mapping),
2819 skb_headlen(skb), PCI_DMA_TODEVICE);
2820
2821 tx_buf->skb = NULL;
2822 last = tx_buf->nr_frags;
2823
2824 for (i = 0; i < last; i++) {
2825 sw_cons = NEXT_TX_BD(sw_cons);
2826
2827 pci_unmap_page(bp->pdev,
2828 dma_unmap_addr(
2829 &txr->tx_buf_ring[TX_RING_IDX(sw_cons)],
2830 mapping),
2831 skb_shinfo(skb)->frags[i].size,
2832 PCI_DMA_TODEVICE);
2833 }
2834
2835 sw_cons = NEXT_TX_BD(sw_cons);
2836
2837 dev_kfree_skb(skb);
2838 tx_pkt++;
2839 if (tx_pkt == budget)
2840 break;
2841
2842 if (hw_cons == sw_cons)
2843 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2844 }
2845
2846 txr->hw_tx_cons = hw_cons;
2847 txr->tx_cons = sw_cons;
2848
2849 /* Need to make the tx_cons update visible to bnx2_start_xmit()
2850 * before checking for netif_tx_queue_stopped(). Without the
2851 * memory barrier, there is a small possibility that bnx2_start_xmit()
2852 * will miss it and cause the queue to be stopped forever.
2853 */
2854 smp_mb();
2855
2856 if (unlikely(netif_tx_queue_stopped(txq)) &&
2857 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
2858 __netif_tx_lock(txq, smp_processor_id());
2859 if ((netif_tx_queue_stopped(txq)) &&
2860 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2861 netif_tx_wake_queue(txq);
2862 __netif_tx_unlock(txq);
2863 }
2864
2865 return tx_pkt;
2866 }
2867
2868 static void
2869 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2870 struct sk_buff *skb, int count)
2871 {
2872 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2873 struct rx_bd *cons_bd, *prod_bd;
2874 int i;
2875 u16 hw_prod, prod;
2876 u16 cons = rxr->rx_pg_cons;
2877
2878 cons_rx_pg = &rxr->rx_pg_ring[cons];
2879
2880 /* The caller was unable to allocate a new page to replace the
2881 * last one in the frags array, so we need to recycle that page
2882 * and then free the skb.
2883 */
2884 if (skb) {
2885 struct page *page;
2886 struct skb_shared_info *shinfo;
2887
2888 shinfo = skb_shinfo(skb);
2889 shinfo->nr_frags--;
2890 page = shinfo->frags[shinfo->nr_frags].page;
2891 shinfo->frags[shinfo->nr_frags].page = NULL;
2892
2893 cons_rx_pg->page = page;
2894 dev_kfree_skb(skb);
2895 }
2896
2897 hw_prod = rxr->rx_pg_prod;
2898
2899 for (i = 0; i < count; i++) {
2900 prod = RX_PG_RING_IDX(hw_prod);
2901
2902 prod_rx_pg = &rxr->rx_pg_ring[prod];
2903 cons_rx_pg = &rxr->rx_pg_ring[cons];
2904 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2905 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2906
2907 if (prod != cons) {
2908 prod_rx_pg->page = cons_rx_pg->page;
2909 cons_rx_pg->page = NULL;
2910 dma_unmap_addr_set(prod_rx_pg, mapping,
2911 dma_unmap_addr(cons_rx_pg, mapping));
2912
2913 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2914 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2915
2916 }
2917 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2918 hw_prod = NEXT_RX_BD(hw_prod);
2919 }
2920 rxr->rx_pg_prod = hw_prod;
2921 rxr->rx_pg_cons = cons;
2922 }
2923
2924 static inline void
2925 bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2926 struct sk_buff *skb, u16 cons, u16 prod)
2927 {
2928 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2929 struct rx_bd *cons_bd, *prod_bd;
2930
2931 cons_rx_buf = &rxr->rx_buf_ring[cons];
2932 prod_rx_buf = &rxr->rx_buf_ring[prod];
2933
2934 pci_dma_sync_single_for_device(bp->pdev,
2935 dma_unmap_addr(cons_rx_buf, mapping),
2936 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2937
2938 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2939
2940 prod_rx_buf->skb = skb;
2941 prod_rx_buf->desc = (struct l2_fhdr *) skb->data;
2942
2943 if (cons == prod)
2944 return;
2945
2946 dma_unmap_addr_set(prod_rx_buf, mapping,
2947 dma_unmap_addr(cons_rx_buf, mapping));
2948
2949 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2950 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2951 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2952 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2953 }
2954
2955 static int
2956 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
2957 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2958 u32 ring_idx)
2959 {
2960 int err;
2961 u16 prod = ring_idx & 0xffff;
2962
2963 err = bnx2_alloc_rx_skb(bp, rxr, prod);
2964 if (unlikely(err)) {
2965 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
2966 if (hdr_len) {
2967 unsigned int raw_len = len + 4;
2968 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2969
2970 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2971 }
2972 return err;
2973 }
2974
2975 skb_reserve(skb, BNX2_RX_OFFSET);
2976 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2977 PCI_DMA_FROMDEVICE);
2978
2979 if (hdr_len == 0) {
2980 skb_put(skb, len);
2981 return 0;
2982 } else {
2983 unsigned int i, frag_len, frag_size, pages;
2984 struct sw_pg *rx_pg;
2985 u16 pg_cons = rxr->rx_pg_cons;
2986 u16 pg_prod = rxr->rx_pg_prod;
2987
2988 frag_size = len + 4 - hdr_len;
2989 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2990 skb_put(skb, hdr_len);
2991
2992 for (i = 0; i < pages; i++) {
2993 dma_addr_t mapping_old;
2994
2995 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2996 if (unlikely(frag_len <= 4)) {
2997 unsigned int tail = 4 - frag_len;
2998
2999 rxr->rx_pg_cons = pg_cons;
3000 rxr->rx_pg_prod = pg_prod;
3001 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
3002 pages - i);
3003 skb->len -= tail;
3004 if (i == 0) {
3005 skb->tail -= tail;
3006 } else {
3007 skb_frag_t *frag =
3008 &skb_shinfo(skb)->frags[i - 1];
3009 frag->size -= tail;
3010 skb->data_len -= tail;
3011 skb->truesize -= tail;
3012 }
3013 return 0;
3014 }
3015 rx_pg = &rxr->rx_pg_ring[pg_cons];
3016
3017 /* Don't unmap yet. If we're unable to allocate a new
3018 * page, we need to recycle the page and the DMA addr.
3019 */
3020 mapping_old = dma_unmap_addr(rx_pg, mapping);
3021 if (i == pages - 1)
3022 frag_len -= 4;
3023
3024 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
3025 rx_pg->page = NULL;
3026
3027 err = bnx2_alloc_rx_page(bp, rxr,
3028 RX_PG_RING_IDX(pg_prod));
3029 if (unlikely(err)) {
3030 rxr->rx_pg_cons = pg_cons;
3031 rxr->rx_pg_prod = pg_prod;
3032 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
3033 pages - i);
3034 return err;
3035 }
3036
3037 pci_unmap_page(bp->pdev, mapping_old,
3038 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3039
3040 frag_size -= frag_len;
3041 skb->data_len += frag_len;
3042 skb->truesize += frag_len;
3043 skb->len += frag_len;
3044
3045 pg_prod = NEXT_RX_BD(pg_prod);
3046 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
3047 }
3048 rxr->rx_pg_prod = pg_prod;
3049 rxr->rx_pg_cons = pg_cons;
3050 }
3051 return 0;
3052 }
3053
3054 static inline u16
3055 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
3056 {
3057 u16 cons;
3058
3059 /* Tell compiler that status block fields can change. */
3060 barrier();
3061 cons = *bnapi->hw_rx_cons_ptr;
3062 barrier();
3063 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
3064 cons++;
3065 return cons;
3066 }
3067
3068 static int
3069 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
3070 {
3071 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3072 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
3073 struct l2_fhdr *rx_hdr;
3074 int rx_pkt = 0, pg_ring_used = 0;
3075 struct pci_dev *pdev = bp->pdev;
3076
3077 hw_cons = bnx2_get_hw_rx_cons(bnapi);
3078 sw_cons = rxr->rx_cons;
3079 sw_prod = rxr->rx_prod;
3080
3081 /* Memory barrier necessary as speculative reads of the rx
3082 * buffer can be ahead of the index in the status block
3083 */
3084 rmb();
3085 while (sw_cons != hw_cons) {
3086 unsigned int len, hdr_len;
3087 u32 status;
3088 struct sw_bd *rx_buf, *next_rx_buf;
3089 struct sk_buff *skb;
3090 dma_addr_t dma_addr;
3091 u16 vtag = 0;
3092 int hw_vlan __maybe_unused = 0;
3093
3094 sw_ring_cons = RX_RING_IDX(sw_cons);
3095 sw_ring_prod = RX_RING_IDX(sw_prod);
3096
3097 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
3098 skb = rx_buf->skb;
3099 prefetchw(skb);
3100
3101 if (!get_dma_ops(&pdev->dev)->sync_single_for_cpu) {
3102 next_rx_buf =
3103 &rxr->rx_buf_ring[
3104 RX_RING_IDX(NEXT_RX_BD(sw_cons))];
3105 prefetch(next_rx_buf->desc);
3106 }
3107 rx_buf->skb = NULL;
3108
3109 dma_addr = dma_unmap_addr(rx_buf, mapping);
3110
3111 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
3112 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
3113 PCI_DMA_FROMDEVICE);
3114
3115 rx_hdr = rx_buf->desc;
3116 len = rx_hdr->l2_fhdr_pkt_len;
3117 status = rx_hdr->l2_fhdr_status;
3118
3119 hdr_len = 0;
3120 if (status & L2_FHDR_STATUS_SPLIT) {
3121 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
3122 pg_ring_used = 1;
3123 } else if (len > bp->rx_jumbo_thresh) {
3124 hdr_len = bp->rx_jumbo_thresh;
3125 pg_ring_used = 1;
3126 }
3127
3128 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
3129 L2_FHDR_ERRORS_PHY_DECODE |
3130 L2_FHDR_ERRORS_ALIGNMENT |
3131 L2_FHDR_ERRORS_TOO_SHORT |
3132 L2_FHDR_ERRORS_GIANT_FRAME))) {
3133
3134 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3135 sw_ring_prod);
3136 if (pg_ring_used) {
3137 int pages;
3138
3139 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
3140
3141 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3142 }
3143 goto next_rx;
3144 }
3145
3146 len -= 4;
3147
3148 if (len <= bp->rx_copy_thresh) {
3149 struct sk_buff *new_skb;
3150
3151 new_skb = netdev_alloc_skb(bp->dev, len + 6);
3152 if (new_skb == NULL) {
3153 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3154 sw_ring_prod);
3155 goto next_rx;
3156 }
3157
3158 /* aligned copy */
3159 skb_copy_from_linear_data_offset(skb,
3160 BNX2_RX_OFFSET - 6,
3161 new_skb->data, len + 6);
3162 skb_reserve(new_skb, 6);
3163 skb_put(new_skb, len);
3164
3165 bnx2_reuse_rx_skb(bp, rxr, skb,
3166 sw_ring_cons, sw_ring_prod);
3167
3168 skb = new_skb;
3169 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
3170 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
3171 goto next_rx;
3172
3173 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
3174 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
3175 vtag = rx_hdr->l2_fhdr_vlan_tag;
3176 #ifdef BCM_VLAN
3177 if (bp->vlgrp)
3178 hw_vlan = 1;
3179 else
3180 #endif
3181 {
3182 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
3183 __skb_push(skb, 4);
3184
3185 memmove(ve, skb->data + 4, ETH_ALEN * 2);
3186 ve->h_vlan_proto = htons(ETH_P_8021Q);
3187 ve->h_vlan_TCI = htons(vtag);
3188 len += 4;
3189 }
3190 }
3191
3192 skb->protocol = eth_type_trans(skb, bp->dev);
3193
3194 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
3195 (ntohs(skb->protocol) != 0x8100)) {
3196
3197 dev_kfree_skb(skb);
3198 goto next_rx;
3199
3200 }
3201
3202 skb->ip_summed = CHECKSUM_NONE;
3203 if (bp->rx_csum &&
3204 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3205 L2_FHDR_STATUS_UDP_DATAGRAM))) {
3206
3207 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3208 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
3209 skb->ip_summed = CHECKSUM_UNNECESSARY;
3210 }
3211
3212 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
3213
3214 #ifdef BCM_VLAN
3215 if (hw_vlan)
3216 vlan_gro_receive(&bnapi->napi, bp->vlgrp, vtag, skb);
3217 else
3218 #endif
3219 napi_gro_receive(&bnapi->napi, skb);
3220
3221 rx_pkt++;
3222
3223 next_rx:
3224 sw_cons = NEXT_RX_BD(sw_cons);
3225 sw_prod = NEXT_RX_BD(sw_prod);
3226
3227 if ((rx_pkt == budget))
3228 break;
3229
3230 /* Refresh hw_cons to see if there is new work */
3231 if (sw_cons == hw_cons) {
3232 hw_cons = bnx2_get_hw_rx_cons(bnapi);
3233 rmb();
3234 }
3235 }
3236 rxr->rx_cons = sw_cons;
3237 rxr->rx_prod = sw_prod;
3238
3239 if (pg_ring_used)
3240 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
3241
3242 REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
3243
3244 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3245
3246 mmiowb();
3247
3248 return rx_pkt;
3249
3250 }
3251
3252 /* MSI ISR - The only difference between this and the INTx ISR
3253 * is that the MSI interrupt is always serviced.
3254 */
3255 static irqreturn_t
3256 bnx2_msi(int irq, void *dev_instance)
3257 {
3258 struct bnx2_napi *bnapi = dev_instance;
3259 struct bnx2 *bp = bnapi->bp;
3260
3261 prefetch(bnapi->status_blk.msi);
3262 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3263 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3264 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3265
3266 /* Return here if interrupt is disabled. */
3267 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3268 return IRQ_HANDLED;
3269
3270 napi_schedule(&bnapi->napi);
3271
3272 return IRQ_HANDLED;
3273 }
3274
3275 static irqreturn_t
3276 bnx2_msi_1shot(int irq, void *dev_instance)
3277 {
3278 struct bnx2_napi *bnapi = dev_instance;
3279 struct bnx2 *bp = bnapi->bp;
3280
3281 prefetch(bnapi->status_blk.msi);
3282
3283 /* Return here if interrupt is disabled. */
3284 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3285 return IRQ_HANDLED;
3286
3287 napi_schedule(&bnapi->napi);
3288
3289 return IRQ_HANDLED;
3290 }
3291
3292 static irqreturn_t
3293 bnx2_interrupt(int irq, void *dev_instance)
3294 {
3295 struct bnx2_napi *bnapi = dev_instance;
3296 struct bnx2 *bp = bnapi->bp;
3297 struct status_block *sblk = bnapi->status_blk.msi;
3298
3299 /* When using INTx, it is possible for the interrupt to arrive
3300 * at the CPU before the status block posted prior to the
3301 * interrupt. Reading a register will flush the status block.
3302 * When using MSI, the MSI message will always complete after
3303 * the status block write.
3304 */
3305 if ((sblk->status_idx == bnapi->last_status_idx) &&
3306 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3307 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
3308 return IRQ_NONE;
3309
3310 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3311 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3312 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3313
3314 /* Read back to deassert IRQ immediately to avoid too many
3315 * spurious interrupts.
3316 */
3317 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3318
3319 /* Return here if interrupt is shared and is disabled. */
3320 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3321 return IRQ_HANDLED;
3322
3323 if (napi_schedule_prep(&bnapi->napi)) {
3324 bnapi->last_status_idx = sblk->status_idx;
3325 __napi_schedule(&bnapi->napi);
3326 }
3327
3328 return IRQ_HANDLED;
3329 }
3330
3331 static inline int
3332 bnx2_has_fast_work(struct bnx2_napi *bnapi)
3333 {
3334 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3335 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3336
3337 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3338 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3339 return 1;
3340 return 0;
3341 }
3342
3343 #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3344 STATUS_ATTN_BITS_TIMER_ABORT)
3345
3346 static inline int
3347 bnx2_has_work(struct bnx2_napi *bnapi)
3348 {
3349 struct status_block *sblk = bnapi->status_blk.msi;
3350
3351 if (bnx2_has_fast_work(bnapi))
3352 return 1;
3353
3354 #ifdef BCM_CNIC
3355 if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx))
3356 return 1;
3357 #endif
3358
3359 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3360 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
3361 return 1;
3362
3363 return 0;
3364 }
3365
3366 static void
3367 bnx2_chk_missed_msi(struct bnx2 *bp)
3368 {
3369 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3370 u32 msi_ctrl;
3371
3372 if (bnx2_has_work(bnapi)) {
3373 msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3374 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3375 return;
3376
3377 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3378 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3379 ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3380 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3381 bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3382 }
3383 }
3384
3385 bp->idle_chk_status_idx = bnapi->last_status_idx;
3386 }
3387
3388 #ifdef BCM_CNIC
3389 static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
3390 {
3391 struct cnic_ops *c_ops;
3392
3393 if (!bnapi->cnic_present)
3394 return;
3395
3396 rcu_read_lock();
3397 c_ops = rcu_dereference(bp->cnic_ops);
3398 if (c_ops)
3399 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
3400 bnapi->status_blk.msi);
3401 rcu_read_unlock();
3402 }
3403 #endif
3404
3405 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3406 {
3407 struct status_block *sblk = bnapi->status_blk.msi;
3408 u32 status_attn_bits = sblk->status_attn_bits;
3409 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3410
3411 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3412 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3413
3414 bnx2_phy_int(bp, bnapi);
3415
3416 /* This is needed to take care of transient status
3417 * during link changes.
3418 */
3419 REG_WR(bp, BNX2_HC_COMMAND,
3420 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3421 REG_RD(bp, BNX2_HC_COMMAND);
3422 }
3423 }
3424
3425 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3426 int work_done, int budget)
3427 {
3428 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3429 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3430
3431 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
3432 bnx2_tx_int(bp, bnapi, 0);
3433
3434 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
3435 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3436
3437 return work_done;
3438 }
3439
3440 static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3441 {
3442 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3443 struct bnx2 *bp = bnapi->bp;
3444 int work_done = 0;
3445 struct status_block_msix *sblk = bnapi->status_blk.msix;
3446
3447 while (1) {
3448 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3449 if (unlikely(work_done >= budget))
3450 break;
3451
3452 bnapi->last_status_idx = sblk->status_idx;
3453 /* status idx must be read before checking for more work. */
3454 rmb();
3455 if (likely(!bnx2_has_fast_work(bnapi))) {
3456
3457 napi_complete(napi);
3458 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3459 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3460 bnapi->last_status_idx);
3461 break;
3462 }
3463 }
3464 return work_done;
3465 }
3466
3467 static int bnx2_poll(struct napi_struct *napi, int budget)
3468 {
3469 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3470 struct bnx2 *bp = bnapi->bp;
3471 int work_done = 0;
3472 struct status_block *sblk = bnapi->status_blk.msi;
3473
3474 while (1) {
3475 bnx2_poll_link(bp, bnapi);
3476
3477 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3478
3479 #ifdef BCM_CNIC
3480 bnx2_poll_cnic(bp, bnapi);
3481 #endif
3482
3483 /* bnapi->last_status_idx is used below to tell the hw how
3484 * much work has been processed, so we must read it before
3485 * checking for more work.
3486 */
3487 bnapi->last_status_idx = sblk->status_idx;
3488
3489 if (unlikely(work_done >= budget))
3490 break;
3491
3492 rmb();
3493 if (likely(!bnx2_has_work(bnapi))) {
3494 napi_complete(napi);
3495 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3496 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3497 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3498 bnapi->last_status_idx);
3499 break;
3500 }
3501 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3502 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3503 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3504 bnapi->last_status_idx);
3505
3506 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3507 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3508 bnapi->last_status_idx);
3509 break;
3510 }
3511 }
3512
3513 return work_done;
3514 }
3515
3516 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
3517 * from set_multicast.
3518 */
3519 static void
3520 bnx2_set_rx_mode(struct net_device *dev)
3521 {
3522 struct bnx2 *bp = netdev_priv(dev);
3523 u32 rx_mode, sort_mode;
3524 struct netdev_hw_addr *ha;
3525 int i;
3526
3527 if (!netif_running(dev))
3528 return;
3529
3530 spin_lock_bh(&bp->phy_lock);
3531
3532 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3533 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3534 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3535 #ifdef BCM_VLAN
3536 if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
3537 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3538 #else
3539 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
3540 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3541 #endif
3542 if (dev->flags & IFF_PROMISC) {
3543 /* Promiscuous mode. */
3544 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3545 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3546 BNX2_RPM_SORT_USER0_PROM_VLAN;
3547 }
3548 else if (dev->flags & IFF_ALLMULTI) {
3549 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3550 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3551 0xffffffff);
3552 }
3553 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3554 }
3555 else {
3556 /* Accept one or more multicast(s). */
3557 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3558 u32 regidx;
3559 u32 bit;
3560 u32 crc;
3561
3562 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3563
3564 netdev_for_each_mc_addr(ha, dev) {
3565 crc = ether_crc_le(ETH_ALEN, ha->addr);
3566 bit = crc & 0xff;
3567 regidx = (bit & 0xe0) >> 5;
3568 bit &= 0x1f;
3569 mc_filter[regidx] |= (1 << bit);
3570 }
3571
3572 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3573 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3574 mc_filter[i]);
3575 }
3576
3577 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3578 }
3579
3580 if (netdev_uc_count(dev) > BNX2_MAX_UNICAST_ADDRESSES) {
3581 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3582 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3583 BNX2_RPM_SORT_USER0_PROM_VLAN;
3584 } else if (!(dev->flags & IFF_PROMISC)) {
3585 /* Add all entries into to the match filter list */
3586 i = 0;
3587 netdev_for_each_uc_addr(ha, dev) {
3588 bnx2_set_mac_addr(bp, ha->addr,
3589 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3590 sort_mode |= (1 <<
3591 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3592 i++;
3593 }
3594
3595 }
3596
3597 if (rx_mode != bp->rx_mode) {
3598 bp->rx_mode = rx_mode;
3599 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3600 }
3601
3602 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3603 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3604 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3605
3606 spin_unlock_bh(&bp->phy_lock);
3607 }
3608
3609 static int __devinit
3610 check_fw_section(const struct firmware *fw,
3611 const struct bnx2_fw_file_section *section,
3612 u32 alignment, bool non_empty)
3613 {
3614 u32 offset = be32_to_cpu(section->offset);
3615 u32 len = be32_to_cpu(section->len);
3616
3617 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
3618 return -EINVAL;
3619 if ((non_empty && len == 0) || len > fw->size - offset ||
3620 len & (alignment - 1))
3621 return -EINVAL;
3622 return 0;
3623 }
3624
3625 static int __devinit
3626 check_mips_fw_entry(const struct firmware *fw,
3627 const struct bnx2_mips_fw_file_entry *entry)
3628 {
3629 if (check_fw_section(fw, &entry->text, 4, true) ||
3630 check_fw_section(fw, &entry->data, 4, false) ||
3631 check_fw_section(fw, &entry->rodata, 4, false))
3632 return -EINVAL;
3633 return 0;
3634 }
3635
3636 static int __devinit
3637 bnx2_request_firmware(struct bnx2 *bp)
3638 {
3639 const char *mips_fw_file, *rv2p_fw_file;
3640 const struct bnx2_mips_fw_file *mips_fw;
3641 const struct bnx2_rv2p_fw_file *rv2p_fw;
3642 int rc;
3643
3644 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3645 mips_fw_file = FW_MIPS_FILE_09;
3646 if ((CHIP_ID(bp) == CHIP_ID_5709_A0) ||
3647 (CHIP_ID(bp) == CHIP_ID_5709_A1))
3648 rv2p_fw_file = FW_RV2P_FILE_09_Ax;
3649 else
3650 rv2p_fw_file = FW_RV2P_FILE_09;
3651 } else {
3652 mips_fw_file = FW_MIPS_FILE_06;
3653 rv2p_fw_file = FW_RV2P_FILE_06;
3654 }
3655
3656 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3657 if (rc) {
3658 pr_err("Can't load firmware file \"%s\"\n", mips_fw_file);
3659 return rc;
3660 }
3661
3662 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3663 if (rc) {
3664 pr_err("Can't load firmware file \"%s\"\n", rv2p_fw_file);
3665 return rc;
3666 }
3667 mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3668 rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3669 if (bp->mips_firmware->size < sizeof(*mips_fw) ||
3670 check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
3671 check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
3672 check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
3673 check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
3674 check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
3675 pr_err("Firmware file \"%s\" is invalid\n", mips_fw_file);
3676 return -EINVAL;
3677 }
3678 if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
3679 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
3680 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
3681 pr_err("Firmware file \"%s\" is invalid\n", rv2p_fw_file);
3682 return -EINVAL;
3683 }
3684
3685 return 0;
3686 }
3687
3688 static u32
3689 rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
3690 {
3691 switch (idx) {
3692 case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
3693 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
3694 rv2p_code |= RV2P_BD_PAGE_SIZE;
3695 break;
3696 }
3697 return rv2p_code;
3698 }
3699
3700 static int
3701 load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3702 const struct bnx2_rv2p_fw_file_entry *fw_entry)
3703 {
3704 u32 rv2p_code_len, file_offset;
3705 __be32 *rv2p_code;
3706 int i;
3707 u32 val, cmd, addr;
3708
3709 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
3710 file_offset = be32_to_cpu(fw_entry->rv2p.offset);
3711
3712 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3713
3714 if (rv2p_proc == RV2P_PROC1) {
3715 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3716 addr = BNX2_RV2P_PROC1_ADDR_CMD;
3717 } else {
3718 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3719 addr = BNX2_RV2P_PROC2_ADDR_CMD;
3720 }
3721
3722 for (i = 0; i < rv2p_code_len; i += 8) {
3723 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
3724 rv2p_code++;
3725 REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
3726 rv2p_code++;
3727
3728 val = (i / 8) | cmd;
3729 REG_WR(bp, addr, val);
3730 }
3731
3732 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3733 for (i = 0; i < 8; i++) {
3734 u32 loc, code;
3735
3736 loc = be32_to_cpu(fw_entry->fixup[i]);
3737 if (loc && ((loc * 4) < rv2p_code_len)) {
3738 code = be32_to_cpu(*(rv2p_code + loc - 1));
3739 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
3740 code = be32_to_cpu(*(rv2p_code + loc));
3741 code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
3742 REG_WR(bp, BNX2_RV2P_INSTR_LOW, code);
3743
3744 val = (loc / 2) | cmd;
3745 REG_WR(bp, addr, val);
3746 }
3747 }
3748
3749 /* Reset the processor, un-stall is done later. */
3750 if (rv2p_proc == RV2P_PROC1) {
3751 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3752 }
3753 else {
3754 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3755 }
3756
3757 return 0;
3758 }
3759
3760 static int
3761 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3762 const struct bnx2_mips_fw_file_entry *fw_entry)
3763 {
3764 u32 addr, len, file_offset;
3765 __be32 *data;
3766 u32 offset;
3767 u32 val;
3768
3769 /* Halt the CPU. */
3770 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3771 val |= cpu_reg->mode_value_halt;
3772 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3773 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3774
3775 /* Load the Text area. */
3776 addr = be32_to_cpu(fw_entry->text.addr);
3777 len = be32_to_cpu(fw_entry->text.len);
3778 file_offset = be32_to_cpu(fw_entry->text.offset);
3779 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3780
3781 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3782 if (len) {
3783 int j;
3784
3785 for (j = 0; j < (len / 4); j++, offset += 4)
3786 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3787 }
3788
3789 /* Load the Data area. */
3790 addr = be32_to_cpu(fw_entry->data.addr);
3791 len = be32_to_cpu(fw_entry->data.len);
3792 file_offset = be32_to_cpu(fw_entry->data.offset);
3793 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3794
3795 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3796 if (len) {
3797 int j;
3798
3799 for (j = 0; j < (len / 4); j++, offset += 4)
3800 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3801 }
3802
3803 /* Load the Read-Only area. */
3804 addr = be32_to_cpu(fw_entry->rodata.addr);
3805 len = be32_to_cpu(fw_entry->rodata.len);
3806 file_offset = be32_to_cpu(fw_entry->rodata.offset);
3807 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3808
3809 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3810 if (len) {
3811 int j;
3812
3813 for (j = 0; j < (len / 4); j++, offset += 4)
3814 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3815 }
3816
3817 /* Clear the pre-fetch instruction. */
3818 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3819
3820 val = be32_to_cpu(fw_entry->start_addr);
3821 bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
3822
3823 /* Start the CPU. */
3824 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3825 val &= ~cpu_reg->mode_value_halt;
3826 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3827 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3828
3829 return 0;
3830 }
3831
3832 static int
3833 bnx2_init_cpus(struct bnx2 *bp)
3834 {
3835 const struct bnx2_mips_fw_file *mips_fw =
3836 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3837 const struct bnx2_rv2p_fw_file *rv2p_fw =
3838 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3839 int rc;
3840
3841 /* Initialize the RV2P processor. */
3842 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3843 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
3844
3845 /* Initialize the RX Processor. */
3846 rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
3847 if (rc)
3848 goto init_cpu_err;
3849
3850 /* Initialize the TX Processor. */
3851 rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
3852 if (rc)
3853 goto init_cpu_err;
3854
3855 /* Initialize the TX Patch-up Processor. */
3856 rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
3857 if (rc)
3858 goto init_cpu_err;
3859
3860 /* Initialize the Completion Processor. */
3861 rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
3862 if (rc)
3863 goto init_cpu_err;
3864
3865 /* Initialize the Command Processor. */
3866 rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
3867
3868 init_cpu_err:
3869 return rc;
3870 }
3871
3872 static int
3873 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3874 {
3875 u16 pmcsr;
3876
3877 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3878
3879 switch (state) {
3880 case PCI_D0: {
3881 u32 val;
3882
3883 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3884 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3885 PCI_PM_CTRL_PME_STATUS);
3886
3887 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3888 /* delay required during transition out of D3hot */
3889 msleep(20);
3890
3891 val = REG_RD(bp, BNX2_EMAC_MODE);
3892 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3893 val &= ~BNX2_EMAC_MODE_MPKT;
3894 REG_WR(bp, BNX2_EMAC_MODE, val);
3895
3896 val = REG_RD(bp, BNX2_RPM_CONFIG);
3897 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3898 REG_WR(bp, BNX2_RPM_CONFIG, val);
3899 break;
3900 }
3901 case PCI_D3hot: {
3902 int i;
3903 u32 val, wol_msg;
3904
3905 if (bp->wol) {
3906 u32 advertising;
3907 u8 autoneg;
3908
3909 autoneg = bp->autoneg;
3910 advertising = bp->advertising;
3911
3912 if (bp->phy_port == PORT_TP) {
3913 bp->autoneg = AUTONEG_SPEED;
3914 bp->advertising = ADVERTISED_10baseT_Half |
3915 ADVERTISED_10baseT_Full |
3916 ADVERTISED_100baseT_Half |
3917 ADVERTISED_100baseT_Full |
3918 ADVERTISED_Autoneg;
3919 }
3920
3921 spin_lock_bh(&bp->phy_lock);
3922 bnx2_setup_phy(bp, bp->phy_port);
3923 spin_unlock_bh(&bp->phy_lock);
3924
3925 bp->autoneg = autoneg;
3926 bp->advertising = advertising;
3927
3928 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3929
3930 val = REG_RD(bp, BNX2_EMAC_MODE);
3931
3932 /* Enable port mode. */
3933 val &= ~BNX2_EMAC_MODE_PORT;
3934 val |= BNX2_EMAC_MODE_MPKT_RCVD |
3935 BNX2_EMAC_MODE_ACPI_RCVD |
3936 BNX2_EMAC_MODE_MPKT;
3937 if (bp->phy_port == PORT_TP)
3938 val |= BNX2_EMAC_MODE_PORT_MII;
3939 else {
3940 val |= BNX2_EMAC_MODE_PORT_GMII;
3941 if (bp->line_speed == SPEED_2500)
3942 val |= BNX2_EMAC_MODE_25G_MODE;
3943 }
3944
3945 REG_WR(bp, BNX2_EMAC_MODE, val);
3946
3947 /* receive all multicast */
3948 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3949 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3950 0xffffffff);
3951 }
3952 REG_WR(bp, BNX2_EMAC_RX_MODE,
3953 BNX2_EMAC_RX_MODE_SORT_MODE);
3954
3955 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3956 BNX2_RPM_SORT_USER0_MC_EN;
3957 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3958 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3959 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3960 BNX2_RPM_SORT_USER0_ENA);
3961
3962 /* Need to enable EMAC and RPM for WOL. */
3963 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3964 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3965 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3966 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3967
3968 val = REG_RD(bp, BNX2_RPM_CONFIG);
3969 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3970 REG_WR(bp, BNX2_RPM_CONFIG, val);
3971
3972 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3973 }
3974 else {
3975 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3976 }
3977
3978 if (!(bp->flags & BNX2_FLAG_NO_WOL))
3979 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3980 1, 0);
3981
3982 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3983 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3984 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3985
3986 if (bp->wol)
3987 pmcsr |= 3;
3988 }
3989 else {
3990 pmcsr |= 3;
3991 }
3992 if (bp->wol) {
3993 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3994 }
3995 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3996 pmcsr);
3997
3998 /* No more memory access after this point until
3999 * device is brought back to D0.
4000 */
4001 udelay(50);
4002 break;
4003 }
4004 default:
4005 return -EINVAL;
4006 }
4007 return 0;
4008 }
4009
4010 static int
4011 bnx2_acquire_nvram_lock(struct bnx2 *bp)
4012 {
4013 u32 val;
4014 int j;
4015
4016 /* Request access to the flash interface. */
4017 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
4018 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4019 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4020 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
4021 break;
4022
4023 udelay(5);
4024 }
4025
4026 if (j >= NVRAM_TIMEOUT_COUNT)
4027 return -EBUSY;
4028
4029 return 0;
4030 }
4031
4032 static int
4033 bnx2_release_nvram_lock(struct bnx2 *bp)
4034 {
4035 int j;
4036 u32 val;
4037
4038 /* Relinquish nvram interface. */
4039 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
4040
4041 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4042 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4043 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
4044 break;
4045
4046 udelay(5);
4047 }
4048
4049 if (j >= NVRAM_TIMEOUT_COUNT)
4050 return -EBUSY;
4051
4052 return 0;
4053 }
4054
4055
4056 static int
4057 bnx2_enable_nvram_write(struct bnx2 *bp)
4058 {
4059 u32 val;
4060
4061 val = REG_RD(bp, BNX2_MISC_CFG);
4062 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
4063
4064 if (bp->flash_info->flags & BNX2_NV_WREN) {
4065 int j;
4066
4067 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4068 REG_WR(bp, BNX2_NVM_COMMAND,
4069 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
4070
4071 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4072 udelay(5);
4073
4074 val = REG_RD(bp, BNX2_NVM_COMMAND);
4075 if (val & BNX2_NVM_COMMAND_DONE)
4076 break;
4077 }
4078
4079 if (j >= NVRAM_TIMEOUT_COUNT)
4080 return -EBUSY;
4081 }
4082 return 0;
4083 }
4084
4085 static void
4086 bnx2_disable_nvram_write(struct bnx2 *bp)
4087 {
4088 u32 val;
4089
4090 val = REG_RD(bp, BNX2_MISC_CFG);
4091 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
4092 }
4093
4094
4095 static void
4096 bnx2_enable_nvram_access(struct bnx2 *bp)
4097 {
4098 u32 val;
4099
4100 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4101 /* Enable both bits, even on read. */
4102 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4103 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
4104 }
4105
4106 static void
4107 bnx2_disable_nvram_access(struct bnx2 *bp)
4108 {
4109 u32 val;
4110
4111 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4112 /* Disable both bits, even after read. */
4113 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4114 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
4115 BNX2_NVM_ACCESS_ENABLE_WR_EN));
4116 }
4117
4118 static int
4119 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
4120 {
4121 u32 cmd;
4122 int j;
4123
4124 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
4125 /* Buffered flash, no erase needed */
4126 return 0;
4127
4128 /* Build an erase command */
4129 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
4130 BNX2_NVM_COMMAND_DOIT;
4131
4132 /* Need to clear DONE bit separately. */
4133 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4134
4135 /* Address of the NVRAM to read from. */
4136 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4137
4138 /* Issue an erase command. */
4139 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4140
4141 /* Wait for completion. */
4142 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4143 u32 val;
4144
4145 udelay(5);
4146
4147 val = REG_RD(bp, BNX2_NVM_COMMAND);
4148 if (val & BNX2_NVM_COMMAND_DONE)
4149 break;
4150 }
4151
4152 if (j >= NVRAM_TIMEOUT_COUNT)
4153 return -EBUSY;
4154
4155 return 0;
4156 }
4157
4158 static int
4159 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
4160 {
4161 u32 cmd;
4162 int j;
4163
4164 /* Build the command word. */
4165 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
4166
4167 /* Calculate an offset of a buffered flash, not needed for 5709. */
4168 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4169 offset = ((offset / bp->flash_info->page_size) <<
4170 bp->flash_info->page_bits) +
4171 (offset % bp->flash_info->page_size);
4172 }
4173
4174 /* Need to clear DONE bit separately. */
4175 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4176
4177 /* Address of the NVRAM to read from. */
4178 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4179
4180 /* Issue a read command. */
4181 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4182
4183 /* Wait for completion. */
4184 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4185 u32 val;
4186
4187 udelay(5);
4188
4189 val = REG_RD(bp, BNX2_NVM_COMMAND);
4190 if (val & BNX2_NVM_COMMAND_DONE) {
4191 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
4192 memcpy(ret_val, &v, 4);
4193 break;
4194 }
4195 }
4196 if (j >= NVRAM_TIMEOUT_COUNT)
4197 return -EBUSY;
4198
4199 return 0;
4200 }
4201
4202
4203 static int
4204 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
4205 {
4206 u32 cmd;
4207 __be32 val32;
4208 int j;
4209
4210 /* Build the command word. */
4211 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
4212
4213 /* Calculate an offset of a buffered flash, not needed for 5709. */
4214 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4215 offset = ((offset / bp->flash_info->page_size) <<
4216 bp->flash_info->page_bits) +
4217 (offset % bp->flash_info->page_size);
4218 }
4219
4220 /* Need to clear DONE bit separately. */
4221 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4222
4223 memcpy(&val32, val, 4);
4224
4225 /* Write the data. */
4226 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
4227
4228 /* Address of the NVRAM to write to. */
4229 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4230
4231 /* Issue the write command. */
4232 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4233
4234 /* Wait for completion. */
4235 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4236 udelay(5);
4237
4238 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
4239 break;
4240 }
4241 if (j >= NVRAM_TIMEOUT_COUNT)
4242 return -EBUSY;
4243
4244 return 0;
4245 }
4246
4247 static int
4248 bnx2_init_nvram(struct bnx2 *bp)
4249 {
4250 u32 val;
4251 int j, entry_count, rc = 0;
4252 const struct flash_spec *flash;
4253
4254 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4255 bp->flash_info = &flash_5709;
4256 goto get_flash_size;
4257 }
4258
4259 /* Determine the selected interface. */
4260 val = REG_RD(bp, BNX2_NVM_CFG1);
4261
4262 entry_count = ARRAY_SIZE(flash_table);
4263
4264 if (val & 0x40000000) {
4265
4266 /* Flash interface has been reconfigured */
4267 for (j = 0, flash = &flash_table[0]; j < entry_count;
4268 j++, flash++) {
4269 if ((val & FLASH_BACKUP_STRAP_MASK) ==
4270 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
4271 bp->flash_info = flash;
4272 break;
4273 }
4274 }
4275 }
4276 else {
4277 u32 mask;
4278 /* Not yet been reconfigured */
4279
4280 if (val & (1 << 23))
4281 mask = FLASH_BACKUP_STRAP_MASK;
4282 else
4283 mask = FLASH_STRAP_MASK;
4284
4285 for (j = 0, flash = &flash_table[0]; j < entry_count;
4286 j++, flash++) {
4287
4288 if ((val & mask) == (flash->strapping & mask)) {
4289 bp->flash_info = flash;
4290
4291 /* Request access to the flash interface. */
4292 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4293 return rc;
4294
4295 /* Enable access to flash interface */
4296 bnx2_enable_nvram_access(bp);
4297
4298 /* Reconfigure the flash interface */
4299 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
4300 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
4301 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
4302 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4303
4304 /* Disable access to flash interface */
4305 bnx2_disable_nvram_access(bp);
4306 bnx2_release_nvram_lock(bp);
4307
4308 break;
4309 }
4310 }
4311 } /* if (val & 0x40000000) */
4312
4313 if (j == entry_count) {
4314 bp->flash_info = NULL;
4315 pr_alert("Unknown flash/EEPROM type\n");
4316 return -ENODEV;
4317 }
4318
4319 get_flash_size:
4320 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
4321 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4322 if (val)
4323 bp->flash_size = val;
4324 else
4325 bp->flash_size = bp->flash_info->total_size;
4326
4327 return rc;
4328 }
4329
4330 static int
4331 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4332 int buf_size)
4333 {
4334 int rc = 0;
4335 u32 cmd_flags, offset32, len32, extra;
4336
4337 if (buf_size == 0)
4338 return 0;
4339
4340 /* Request access to the flash interface. */
4341 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4342 return rc;
4343
4344 /* Enable access to flash interface */
4345 bnx2_enable_nvram_access(bp);
4346
4347 len32 = buf_size;
4348 offset32 = offset;
4349 extra = 0;
4350
4351 cmd_flags = 0;
4352
4353 if (offset32 & 3) {
4354 u8 buf[4];
4355 u32 pre_len;
4356
4357 offset32 &= ~3;
4358 pre_len = 4 - (offset & 3);
4359
4360 if (pre_len >= len32) {
4361 pre_len = len32;
4362 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4363 BNX2_NVM_COMMAND_LAST;
4364 }
4365 else {
4366 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4367 }
4368
4369 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4370
4371 if (rc)
4372 return rc;
4373
4374 memcpy(ret_buf, buf + (offset & 3), pre_len);
4375
4376 offset32 += 4;
4377 ret_buf += pre_len;
4378 len32 -= pre_len;
4379 }
4380 if (len32 & 3) {
4381 extra = 4 - (len32 & 3);
4382 len32 = (len32 + 4) & ~3;
4383 }
4384
4385 if (len32 == 4) {
4386 u8 buf[4];
4387
4388 if (cmd_flags)
4389 cmd_flags = BNX2_NVM_COMMAND_LAST;
4390 else
4391 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4392 BNX2_NVM_COMMAND_LAST;
4393
4394 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4395
4396 memcpy(ret_buf, buf, 4 - extra);
4397 }
4398 else if (len32 > 0) {
4399 u8 buf[4];
4400
4401 /* Read the first word. */
4402 if (cmd_flags)
4403 cmd_flags = 0;
4404 else
4405 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4406
4407 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4408
4409 /* Advance to the next dword. */
4410 offset32 += 4;
4411 ret_buf += 4;
4412 len32 -= 4;
4413
4414 while (len32 > 4 && rc == 0) {
4415 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4416
4417 /* Advance to the next dword. */
4418 offset32 += 4;
4419 ret_buf += 4;
4420 len32 -= 4;
4421 }
4422
4423 if (rc)
4424 return rc;
4425
4426 cmd_flags = BNX2_NVM_COMMAND_LAST;
4427 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4428
4429 memcpy(ret_buf, buf, 4 - extra);
4430 }
4431
4432 /* Disable access to flash interface */
4433 bnx2_disable_nvram_access(bp);
4434
4435 bnx2_release_nvram_lock(bp);
4436
4437 return rc;
4438 }
4439
4440 static int
4441 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4442 int buf_size)
4443 {
4444 u32 written, offset32, len32;
4445 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4446 int rc = 0;
4447 int align_start, align_end;
4448
4449 buf = data_buf;
4450 offset32 = offset;
4451 len32 = buf_size;
4452 align_start = align_end = 0;
4453
4454 if ((align_start = (offset32 & 3))) {
4455 offset32 &= ~3;
4456 len32 += align_start;
4457 if (len32 < 4)
4458 len32 = 4;
4459 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4460 return rc;
4461 }
4462
4463 if (len32 & 3) {
4464 align_end = 4 - (len32 & 3);
4465 len32 += align_end;
4466 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4467 return rc;
4468 }
4469
4470 if (align_start || align_end) {
4471 align_buf = kmalloc(len32, GFP_KERNEL);
4472 if (align_buf == NULL)
4473 return -ENOMEM;
4474 if (align_start) {
4475 memcpy(align_buf, start, 4);
4476 }
4477 if (align_end) {
4478 memcpy(align_buf + len32 - 4, end, 4);
4479 }
4480 memcpy(align_buf + align_start, data_buf, buf_size);
4481 buf = align_buf;
4482 }
4483
4484 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4485 flash_buffer = kmalloc(264, GFP_KERNEL);
4486 if (flash_buffer == NULL) {
4487 rc = -ENOMEM;
4488 goto nvram_write_end;
4489 }
4490 }
4491
4492 written = 0;
4493 while ((written < len32) && (rc == 0)) {
4494 u32 page_start, page_end, data_start, data_end;
4495 u32 addr, cmd_flags;
4496 int i;
4497
4498 /* Find the page_start addr */
4499 page_start = offset32 + written;
4500 page_start -= (page_start % bp->flash_info->page_size);
4501 /* Find the page_end addr */
4502 page_end = page_start + bp->flash_info->page_size;
4503 /* Find the data_start addr */
4504 data_start = (written == 0) ? offset32 : page_start;
4505 /* Find the data_end addr */
4506 data_end = (page_end > offset32 + len32) ?
4507 (offset32 + len32) : page_end;
4508
4509 /* Request access to the flash interface. */
4510 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4511 goto nvram_write_end;
4512
4513 /* Enable access to flash interface */
4514 bnx2_enable_nvram_access(bp);
4515
4516 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4517 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4518 int j;
4519
4520 /* Read the whole page into the buffer
4521 * (non-buffer flash only) */
4522 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4523 if (j == (bp->flash_info->page_size - 4)) {
4524 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4525 }
4526 rc = bnx2_nvram_read_dword(bp,
4527 page_start + j,
4528 &flash_buffer[j],
4529 cmd_flags);
4530
4531 if (rc)
4532 goto nvram_write_end;
4533
4534 cmd_flags = 0;
4535 }
4536 }
4537
4538 /* Enable writes to flash interface (unlock write-protect) */
4539 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4540 goto nvram_write_end;
4541
4542 /* Loop to write back the buffer data from page_start to
4543 * data_start */
4544 i = 0;
4545 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4546 /* Erase the page */
4547 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4548 goto nvram_write_end;
4549
4550 /* Re-enable the write again for the actual write */
4551 bnx2_enable_nvram_write(bp);
4552
4553 for (addr = page_start; addr < data_start;
4554 addr += 4, i += 4) {
4555
4556 rc = bnx2_nvram_write_dword(bp, addr,
4557 &flash_buffer[i], cmd_flags);
4558
4559 if (rc != 0)
4560 goto nvram_write_end;
4561
4562 cmd_flags = 0;
4563 }
4564 }
4565
4566 /* Loop to write the new data from data_start to data_end */
4567 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4568 if ((addr == page_end - 4) ||
4569 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4570 (addr == data_end - 4))) {
4571
4572 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4573 }
4574 rc = bnx2_nvram_write_dword(bp, addr, buf,
4575 cmd_flags);
4576
4577 if (rc != 0)
4578 goto nvram_write_end;
4579
4580 cmd_flags = 0;
4581 buf += 4;
4582 }
4583
4584 /* Loop to write back the buffer data from data_end
4585 * to page_end */
4586 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4587 for (addr = data_end; addr < page_end;
4588 addr += 4, i += 4) {
4589
4590 if (addr == page_end-4) {
4591 cmd_flags = BNX2_NVM_COMMAND_LAST;
4592 }
4593 rc = bnx2_nvram_write_dword(bp, addr,
4594 &flash_buffer[i], cmd_flags);
4595
4596 if (rc != 0)
4597 goto nvram_write_end;
4598
4599 cmd_flags = 0;
4600 }
4601 }
4602
4603 /* Disable writes to flash interface (lock write-protect) */
4604 bnx2_disable_nvram_write(bp);
4605
4606 /* Disable access to flash interface */
4607 bnx2_disable_nvram_access(bp);
4608 bnx2_release_nvram_lock(bp);
4609
4610 /* Increment written */
4611 written += data_end - data_start;
4612 }
4613
4614 nvram_write_end:
4615 kfree(flash_buffer);
4616 kfree(align_buf);
4617 return rc;
4618 }
4619
4620 static void
4621 bnx2_init_fw_cap(struct bnx2 *bp)
4622 {
4623 u32 val, sig = 0;
4624
4625 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4626 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4627
4628 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4629 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4630
4631 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4632 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4633 return;
4634
4635 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4636 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4637 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4638 }
4639
4640 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4641 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4642 u32 link;
4643
4644 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4645
4646 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4647 if (link & BNX2_LINK_STATUS_SERDES_LINK)
4648 bp->phy_port = PORT_FIBRE;
4649 else
4650 bp->phy_port = PORT_TP;
4651
4652 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4653 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4654 }
4655
4656 if (netif_running(bp->dev) && sig)
4657 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4658 }
4659
4660 static void
4661 bnx2_setup_msix_tbl(struct bnx2 *bp)
4662 {
4663 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4664
4665 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4666 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4667 }
4668
4669 static int
4670 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4671 {
4672 u32 val;
4673 int i, rc = 0;
4674 u8 old_port;
4675
4676 /* Wait for the current PCI transaction to complete before
4677 * issuing a reset. */
4678 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4679 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4680 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4681 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4682 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4683 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4684 udelay(5);
4685
4686 /* Wait for the firmware to tell us it is ok to issue a reset. */
4687 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4688
4689 /* Deposit a driver reset signature so the firmware knows that
4690 * this is a soft reset. */
4691 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4692 BNX2_DRV_RESET_SIGNATURE_MAGIC);
4693
4694 /* Do a dummy read to force the chip to complete all current transaction
4695 * before we issue a reset. */
4696 val = REG_RD(bp, BNX2_MISC_ID);
4697
4698 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4699 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4700 REG_RD(bp, BNX2_MISC_COMMAND);
4701 udelay(5);
4702
4703 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4704 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4705
4706 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4707
4708 } else {
4709 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4710 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4711 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4712
4713 /* Chip reset. */
4714 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4715
4716 /* Reading back any register after chip reset will hang the
4717 * bus on 5706 A0 and A1. The msleep below provides plenty
4718 * of margin for write posting.
4719 */
4720 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4721 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4722 msleep(20);
4723
4724 /* Reset takes approximate 30 usec */
4725 for (i = 0; i < 10; i++) {
4726 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4727 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4728 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4729 break;
4730 udelay(10);
4731 }
4732
4733 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4734 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4735 pr_err("Chip reset did not complete\n");
4736 return -EBUSY;
4737 }
4738 }
4739
4740 /* Make sure byte swapping is properly configured. */
4741 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4742 if (val != 0x01020304) {
4743 pr_err("Chip not in correct endian mode\n");
4744 return -ENODEV;
4745 }
4746
4747 /* Wait for the firmware to finish its initialization. */
4748 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4749 if (rc)
4750 return rc;
4751
4752 spin_lock_bh(&bp->phy_lock);
4753 old_port = bp->phy_port;
4754 bnx2_init_fw_cap(bp);
4755 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4756 old_port != bp->phy_port)
4757 bnx2_set_default_remote_link(bp);
4758 spin_unlock_bh(&bp->phy_lock);
4759
4760 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4761 /* Adjust the voltage regular to two steps lower. The default
4762 * of this register is 0x0000000e. */
4763 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4764
4765 /* Remove bad rbuf memory from the free pool. */
4766 rc = bnx2_alloc_bad_rbuf(bp);
4767 }
4768
4769 if (bp->flags & BNX2_FLAG_USING_MSIX) {
4770 bnx2_setup_msix_tbl(bp);
4771 /* Prevent MSIX table reads and write from timing out */
4772 REG_WR(bp, BNX2_MISC_ECO_HW_CTL,
4773 BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN);
4774 }
4775
4776 return rc;
4777 }
4778
4779 static int
4780 bnx2_init_chip(struct bnx2 *bp)
4781 {
4782 u32 val, mtu;
4783 int rc, i;
4784
4785 /* Make sure the interrupt is not active. */
4786 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4787
4788 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4789 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4790 #ifdef __BIG_ENDIAN
4791 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4792 #endif
4793 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4794 DMA_READ_CHANS << 12 |
4795 DMA_WRITE_CHANS << 16;
4796
4797 val |= (0x2 << 20) | (1 << 11);
4798
4799 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4800 val |= (1 << 23);
4801
4802 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4803 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4804 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4805
4806 REG_WR(bp, BNX2_DMA_CONFIG, val);
4807
4808 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4809 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4810 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4811 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4812 }
4813
4814 if (bp->flags & BNX2_FLAG_PCIX) {
4815 u16 val16;
4816
4817 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4818 &val16);
4819 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4820 val16 & ~PCI_X_CMD_ERO);
4821 }
4822
4823 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4824 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4825 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4826 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4827
4828 /* Initialize context mapping and zero out the quick contexts. The
4829 * context block must have already been enabled. */
4830 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4831 rc = bnx2_init_5709_context(bp);
4832 if (rc)
4833 return rc;
4834 } else
4835 bnx2_init_context(bp);
4836
4837 if ((rc = bnx2_init_cpus(bp)) != 0)
4838 return rc;
4839
4840 bnx2_init_nvram(bp);
4841
4842 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
4843
4844 val = REG_RD(bp, BNX2_MQ_CONFIG);
4845 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4846 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4847 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4848 val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
4849 if (CHIP_REV(bp) == CHIP_REV_Ax)
4850 val |= BNX2_MQ_CONFIG_HALT_DIS;
4851 }
4852
4853 REG_WR(bp, BNX2_MQ_CONFIG, val);
4854
4855 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4856 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4857 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4858
4859 val = (BCM_PAGE_BITS - 8) << 24;
4860 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4861
4862 /* Configure page size. */
4863 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4864 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4865 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4866 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4867
4868 val = bp->mac_addr[0] +
4869 (bp->mac_addr[1] << 8) +
4870 (bp->mac_addr[2] << 16) +
4871 bp->mac_addr[3] +
4872 (bp->mac_addr[4] << 8) +
4873 (bp->mac_addr[5] << 16);
4874 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4875
4876 /* Program the MTU. Also include 4 bytes for CRC32. */
4877 mtu = bp->dev->mtu;
4878 val = mtu + ETH_HLEN + ETH_FCS_LEN;
4879 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4880 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4881 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4882
4883 if (mtu < 1500)
4884 mtu = 1500;
4885
4886 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4887 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4888 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4889
4890 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
4891 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4892 bp->bnx2_napi[i].last_status_idx = 0;
4893
4894 bp->idle_chk_status_idx = 0xffff;
4895
4896 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4897
4898 /* Set up how to generate a link change interrupt. */
4899 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4900
4901 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4902 (u64) bp->status_blk_mapping & 0xffffffff);
4903 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4904
4905 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4906 (u64) bp->stats_blk_mapping & 0xffffffff);
4907 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4908 (u64) bp->stats_blk_mapping >> 32);
4909
4910 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4911 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4912
4913 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4914 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4915
4916 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4917 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4918
4919 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4920
4921 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4922
4923 REG_WR(bp, BNX2_HC_COM_TICKS,
4924 (bp->com_ticks_int << 16) | bp->com_ticks);
4925
4926 REG_WR(bp, BNX2_HC_CMD_TICKS,
4927 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4928
4929 if (bp->flags & BNX2_FLAG_BROKEN_STATS)
4930 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4931 else
4932 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4933 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4934
4935 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4936 val = BNX2_HC_CONFIG_COLLECT_STATS;
4937 else {
4938 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4939 BNX2_HC_CONFIG_COLLECT_STATS;
4940 }
4941
4942 if (bp->flags & BNX2_FLAG_USING_MSIX) {
4943 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4944 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4945
4946 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4947 }
4948
4949 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4950 val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM;
4951
4952 REG_WR(bp, BNX2_HC_CONFIG, val);
4953
4954 for (i = 1; i < bp->irq_nvecs; i++) {
4955 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4956 BNX2_HC_SB_CONFIG_1;
4957
4958 REG_WR(bp, base,
4959 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4960 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
4961 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4962
4963 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
4964 (bp->tx_quick_cons_trip_int << 16) |
4965 bp->tx_quick_cons_trip);
4966
4967 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4968 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4969
4970 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4971 (bp->rx_quick_cons_trip_int << 16) |
4972 bp->rx_quick_cons_trip);
4973
4974 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4975 (bp->rx_ticks_int << 16) | bp->rx_ticks);
4976 }
4977
4978 /* Clear internal stats counters. */
4979 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4980
4981 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4982
4983 /* Initialize the receive filter. */
4984 bnx2_set_rx_mode(bp->dev);
4985
4986 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4987 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4988 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4989 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4990 }
4991 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4992 1, 0);
4993
4994 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4995 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4996
4997 udelay(20);
4998
4999 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
5000
5001 return rc;
5002 }
5003
5004 static void
5005 bnx2_clear_ring_states(struct bnx2 *bp)
5006 {
5007 struct bnx2_napi *bnapi;
5008 struct bnx2_tx_ring_info *txr;
5009 struct bnx2_rx_ring_info *rxr;
5010 int i;
5011
5012 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5013 bnapi = &bp->bnx2_napi[i];
5014 txr = &bnapi->tx_ring;
5015 rxr = &bnapi->rx_ring;
5016
5017 txr->tx_cons = 0;
5018 txr->hw_tx_cons = 0;
5019 rxr->rx_prod_bseq = 0;
5020 rxr->rx_prod = 0;
5021 rxr->rx_cons = 0;
5022 rxr->rx_pg_prod = 0;
5023 rxr->rx_pg_cons = 0;
5024 }
5025 }
5026
5027 static void
5028 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
5029 {
5030 u32 val, offset0, offset1, offset2, offset3;
5031 u32 cid_addr = GET_CID_ADDR(cid);
5032
5033 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5034 offset0 = BNX2_L2CTX_TYPE_XI;
5035 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
5036 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
5037 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
5038 } else {
5039 offset0 = BNX2_L2CTX_TYPE;
5040 offset1 = BNX2_L2CTX_CMD_TYPE;
5041 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
5042 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
5043 }
5044 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
5045 bnx2_ctx_wr(bp, cid_addr, offset0, val);
5046
5047 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
5048 bnx2_ctx_wr(bp, cid_addr, offset1, val);
5049
5050 val = (u64) txr->tx_desc_mapping >> 32;
5051 bnx2_ctx_wr(bp, cid_addr, offset2, val);
5052
5053 val = (u64) txr->tx_desc_mapping & 0xffffffff;
5054 bnx2_ctx_wr(bp, cid_addr, offset3, val);
5055 }
5056
5057 static void
5058 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
5059 {
5060 struct tx_bd *txbd;
5061 u32 cid = TX_CID;
5062 struct bnx2_napi *bnapi;
5063 struct bnx2_tx_ring_info *txr;
5064
5065 bnapi = &bp->bnx2_napi[ring_num];
5066 txr = &bnapi->tx_ring;
5067
5068 if (ring_num == 0)
5069 cid = TX_CID;
5070 else
5071 cid = TX_TSS_CID + ring_num - 1;
5072
5073 bp->tx_wake_thresh = bp->tx_ring_size / 2;
5074
5075 txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
5076
5077 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
5078 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
5079
5080 txr->tx_prod = 0;
5081 txr->tx_prod_bseq = 0;
5082
5083 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
5084 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
5085
5086 bnx2_init_tx_context(bp, cid, txr);
5087 }
5088
5089 static void
5090 bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
5091 int num_rings)
5092 {
5093 int i;
5094 struct rx_bd *rxbd;
5095
5096 for (i = 0; i < num_rings; i++) {
5097 int j;
5098
5099 rxbd = &rx_ring[i][0];
5100 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
5101 rxbd->rx_bd_len = buf_size;
5102 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
5103 }
5104 if (i == (num_rings - 1))
5105 j = 0;
5106 else
5107 j = i + 1;
5108 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
5109 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
5110 }
5111 }
5112
5113 static void
5114 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
5115 {
5116 int i;
5117 u16 prod, ring_prod;
5118 u32 cid, rx_cid_addr, val;
5119 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
5120 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5121
5122 if (ring_num == 0)
5123 cid = RX_CID;
5124 else
5125 cid = RX_RSS_CID + ring_num - 1;
5126
5127 rx_cid_addr = GET_CID_ADDR(cid);
5128
5129 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
5130 bp->rx_buf_use_size, bp->rx_max_ring);
5131
5132 bnx2_init_rx_context(bp, cid);
5133
5134 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5135 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
5136 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
5137 }
5138
5139 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
5140 if (bp->rx_pg_ring_size) {
5141 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
5142 rxr->rx_pg_desc_mapping,
5143 PAGE_SIZE, bp->rx_max_pg_ring);
5144 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
5145 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
5146 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
5147 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
5148
5149 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
5150 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
5151
5152 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
5153 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
5154
5155 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5156 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
5157 }
5158
5159 val = (u64) rxr->rx_desc_mapping[0] >> 32;
5160 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
5161
5162 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
5163 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
5164
5165 ring_prod = prod = rxr->rx_pg_prod;
5166 for (i = 0; i < bp->rx_pg_ring_size; i++) {
5167 if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0) {
5168 netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n",
5169 ring_num, i, bp->rx_pg_ring_size);
5170 break;
5171 }
5172 prod = NEXT_RX_BD(prod);
5173 ring_prod = RX_PG_RING_IDX(prod);
5174 }
5175 rxr->rx_pg_prod = prod;
5176
5177 ring_prod = prod = rxr->rx_prod;
5178 for (i = 0; i < bp->rx_ring_size; i++) {
5179 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0) {
5180 netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n",
5181 ring_num, i, bp->rx_ring_size);
5182 break;
5183 }
5184 prod = NEXT_RX_BD(prod);
5185 ring_prod = RX_RING_IDX(prod);
5186 }
5187 rxr->rx_prod = prod;
5188
5189 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
5190 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
5191 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
5192
5193 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
5194 REG_WR16(bp, rxr->rx_bidx_addr, prod);
5195
5196 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
5197 }
5198
5199 static void
5200 bnx2_init_all_rings(struct bnx2 *bp)
5201 {
5202 int i;
5203 u32 val;
5204
5205 bnx2_clear_ring_states(bp);
5206
5207 REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
5208 for (i = 0; i < bp->num_tx_rings; i++)
5209 bnx2_init_tx_ring(bp, i);
5210
5211 if (bp->num_tx_rings > 1)
5212 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
5213 (TX_TSS_CID << 7));
5214
5215 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
5216 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
5217
5218 for (i = 0; i < bp->num_rx_rings; i++)
5219 bnx2_init_rx_ring(bp, i);
5220
5221 if (bp->num_rx_rings > 1) {
5222 u32 tbl_32;
5223 u8 *tbl = (u8 *) &tbl_32;
5224
5225 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
5226 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
5227
5228 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
5229 tbl[i % 4] = i % (bp->num_rx_rings - 1);
5230 if ((i % 4) == 3)
5231 bnx2_reg_wr_ind(bp,
5232 BNX2_RXP_SCRATCH_RSS_TBL + i,
5233 cpu_to_be32(tbl_32));
5234 }
5235
5236 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5237 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
5238
5239 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5240
5241 }
5242 }
5243
5244 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
5245 {
5246 u32 max, num_rings = 1;
5247
5248 while (ring_size > MAX_RX_DESC_CNT) {
5249 ring_size -= MAX_RX_DESC_CNT;
5250 num_rings++;
5251 }
5252 /* round to next power of 2 */
5253 max = max_size;
5254 while ((max & num_rings) == 0)
5255 max >>= 1;
5256
5257 if (num_rings != max)
5258 max <<= 1;
5259
5260 return max;
5261 }
5262
5263 static void
5264 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
5265 {
5266 u32 rx_size, rx_space, jumbo_size;
5267
5268 /* 8 for CRC and VLAN */
5269 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5270
5271 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
5272 sizeof(struct skb_shared_info);
5273
5274 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
5275 bp->rx_pg_ring_size = 0;
5276 bp->rx_max_pg_ring = 0;
5277 bp->rx_max_pg_ring_idx = 0;
5278 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
5279 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5280
5281 jumbo_size = size * pages;
5282 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
5283 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
5284
5285 bp->rx_pg_ring_size = jumbo_size;
5286 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
5287 MAX_RX_PG_RINGS);
5288 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
5289 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
5290 bp->rx_copy_thresh = 0;
5291 }
5292
5293 bp->rx_buf_use_size = rx_size;
5294 /* hw alignment */
5295 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
5296 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5297 bp->rx_ring_size = size;
5298 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
5299 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
5300 }
5301
5302 static void
5303 bnx2_free_tx_skbs(struct bnx2 *bp)
5304 {
5305 int i;
5306
5307 for (i = 0; i < bp->num_tx_rings; i++) {
5308 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5309 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5310 int j;
5311
5312 if (txr->tx_buf_ring == NULL)
5313 continue;
5314
5315 for (j = 0; j < TX_DESC_CNT; ) {
5316 struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
5317 struct sk_buff *skb = tx_buf->skb;
5318 int k, last;
5319
5320 if (skb == NULL) {
5321 j++;
5322 continue;
5323 }
5324
5325 pci_unmap_single(bp->pdev,
5326 dma_unmap_addr(tx_buf, mapping),
5327 skb_headlen(skb),
5328 PCI_DMA_TODEVICE);
5329
5330 tx_buf->skb = NULL;
5331
5332 last = tx_buf->nr_frags;
5333 j++;
5334 for (k = 0; k < last; k++, j++) {
5335 tx_buf = &txr->tx_buf_ring[TX_RING_IDX(j)];
5336 pci_unmap_page(bp->pdev,
5337 dma_unmap_addr(tx_buf, mapping),
5338 skb_shinfo(skb)->frags[k].size,
5339 PCI_DMA_TODEVICE);
5340 }
5341 dev_kfree_skb(skb);
5342 }
5343 }
5344 }
5345
5346 static void
5347 bnx2_free_rx_skbs(struct bnx2 *bp)
5348 {
5349 int i;
5350
5351 for (i = 0; i < bp->num_rx_rings; i++) {
5352 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5353 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5354 int j;
5355
5356 if (rxr->rx_buf_ring == NULL)
5357 return;
5358
5359 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5360 struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5361 struct sk_buff *skb = rx_buf->skb;
5362
5363 if (skb == NULL)
5364 continue;
5365
5366 pci_unmap_single(bp->pdev,
5367 dma_unmap_addr(rx_buf, mapping),
5368 bp->rx_buf_use_size,
5369 PCI_DMA_FROMDEVICE);
5370
5371 rx_buf->skb = NULL;
5372
5373 dev_kfree_skb(skb);
5374 }
5375 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5376 bnx2_free_rx_page(bp, rxr, j);
5377 }
5378 }
5379
5380 static void
5381 bnx2_free_skbs(struct bnx2 *bp)
5382 {
5383 bnx2_free_tx_skbs(bp);
5384 bnx2_free_rx_skbs(bp);
5385 }
5386
5387 static int
5388 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5389 {
5390 int rc;
5391
5392 rc = bnx2_reset_chip(bp, reset_code);
5393 bnx2_free_skbs(bp);
5394 if (rc)
5395 return rc;
5396
5397 if ((rc = bnx2_init_chip(bp)) != 0)
5398 return rc;
5399
5400 bnx2_init_all_rings(bp);
5401 return 0;
5402 }
5403
5404 static int
5405 bnx2_init_nic(struct bnx2 *bp, int reset_phy)
5406 {
5407 int rc;
5408
5409 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5410 return rc;
5411
5412 spin_lock_bh(&bp->phy_lock);
5413 bnx2_init_phy(bp, reset_phy);
5414 bnx2_set_link(bp);
5415 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5416 bnx2_remote_phy_event(bp);
5417 spin_unlock_bh(&bp->phy_lock);
5418 return 0;
5419 }
5420
5421 static int
5422 bnx2_shutdown_chip(struct bnx2 *bp)
5423 {
5424 u32 reset_code;
5425
5426 if (bp->flags & BNX2_FLAG_NO_WOL)
5427 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5428 else if (bp->wol)
5429 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5430 else
5431 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5432
5433 return bnx2_reset_chip(bp, reset_code);
5434 }
5435
5436 static int
5437 bnx2_test_registers(struct bnx2 *bp)
5438 {
5439 int ret;
5440 int i, is_5709;
5441 static const struct {
5442 u16 offset;
5443 u16 flags;
5444 #define BNX2_FL_NOT_5709 1
5445 u32 rw_mask;
5446 u32 ro_mask;
5447 } reg_tbl[] = {
5448 { 0x006c, 0, 0x00000000, 0x0000003f },
5449 { 0x0090, 0, 0xffffffff, 0x00000000 },
5450 { 0x0094, 0, 0x00000000, 0x00000000 },
5451
5452 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5453 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5454 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5455 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5456 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5457 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5458 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5459 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5460 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5461
5462 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5463 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5464 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5465 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5466 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5467 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5468
5469 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5470 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5471 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
5472
5473 { 0x1000, 0, 0x00000000, 0x00000001 },
5474 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
5475
5476 { 0x1408, 0, 0x01c00800, 0x00000000 },
5477 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5478 { 0x14a8, 0, 0x00000000, 0x000001ff },
5479 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
5480 { 0x14b0, 0, 0x00000002, 0x00000001 },
5481 { 0x14b8, 0, 0x00000000, 0x00000000 },
5482 { 0x14c0, 0, 0x00000000, 0x00000009 },
5483 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5484 { 0x14cc, 0, 0x00000000, 0x00000001 },
5485 { 0x14d0, 0, 0xffffffff, 0x00000000 },
5486
5487 { 0x1800, 0, 0x00000000, 0x00000001 },
5488 { 0x1804, 0, 0x00000000, 0x00000003 },
5489
5490 { 0x2800, 0, 0x00000000, 0x00000001 },
5491 { 0x2804, 0, 0x00000000, 0x00003f01 },
5492 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5493 { 0x2810, 0, 0xffff0000, 0x00000000 },
5494 { 0x2814, 0, 0xffff0000, 0x00000000 },
5495 { 0x2818, 0, 0xffff0000, 0x00000000 },
5496 { 0x281c, 0, 0xffff0000, 0x00000000 },
5497 { 0x2834, 0, 0xffffffff, 0x00000000 },
5498 { 0x2840, 0, 0x00000000, 0xffffffff },
5499 { 0x2844, 0, 0x00000000, 0xffffffff },
5500 { 0x2848, 0, 0xffffffff, 0x00000000 },
5501 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5502
5503 { 0x2c00, 0, 0x00000000, 0x00000011 },
5504 { 0x2c04, 0, 0x00000000, 0x00030007 },
5505
5506 { 0x3c00, 0, 0x00000000, 0x00000001 },
5507 { 0x3c04, 0, 0x00000000, 0x00070000 },
5508 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5509 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5510 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5511 { 0x3c14, 0, 0x00000000, 0xffffffff },
5512 { 0x3c18, 0, 0x00000000, 0xffffffff },
5513 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5514 { 0x3c20, 0, 0xffffff00, 0x00000000 },
5515
5516 { 0x5004, 0, 0x00000000, 0x0000007f },
5517 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
5518
5519 { 0x5c00, 0, 0x00000000, 0x00000001 },
5520 { 0x5c04, 0, 0x00000000, 0x0003000f },
5521 { 0x5c08, 0, 0x00000003, 0x00000000 },
5522 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5523 { 0x5c10, 0, 0x00000000, 0xffffffff },
5524 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5525 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5526 { 0x5c88, 0, 0x00000000, 0x00077373 },
5527 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5528
5529 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5530 { 0x680c, 0, 0xffffffff, 0x00000000 },
5531 { 0x6810, 0, 0xffffffff, 0x00000000 },
5532 { 0x6814, 0, 0xffffffff, 0x00000000 },
5533 { 0x6818, 0, 0xffffffff, 0x00000000 },
5534 { 0x681c, 0, 0xffffffff, 0x00000000 },
5535 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5536 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5537 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5538 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5539 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5540 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5541 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5542 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5543 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5544 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5545 { 0x684c, 0, 0xffffffff, 0x00000000 },
5546 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5547 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5548 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5549 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5550 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5551 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5552
5553 { 0xffff, 0, 0x00000000, 0x00000000 },
5554 };
5555
5556 ret = 0;
5557 is_5709 = 0;
5558 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5559 is_5709 = 1;
5560
5561 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5562 u32 offset, rw_mask, ro_mask, save_val, val;
5563 u16 flags = reg_tbl[i].flags;
5564
5565 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5566 continue;
5567
5568 offset = (u32) reg_tbl[i].offset;
5569 rw_mask = reg_tbl[i].rw_mask;
5570 ro_mask = reg_tbl[i].ro_mask;
5571
5572 save_val = readl(bp->regview + offset);
5573
5574 writel(0, bp->regview + offset);
5575
5576 val = readl(bp->regview + offset);
5577 if ((val & rw_mask) != 0) {
5578 goto reg_test_err;
5579 }
5580
5581 if ((val & ro_mask) != (save_val & ro_mask)) {
5582 goto reg_test_err;
5583 }
5584
5585 writel(0xffffffff, bp->regview + offset);
5586
5587 val = readl(bp->regview + offset);
5588 if ((val & rw_mask) != rw_mask) {
5589 goto reg_test_err;
5590 }
5591
5592 if ((val & ro_mask) != (save_val & ro_mask)) {
5593 goto reg_test_err;
5594 }
5595
5596 writel(save_val, bp->regview + offset);
5597 continue;
5598
5599 reg_test_err:
5600 writel(save_val, bp->regview + offset);
5601 ret = -ENODEV;
5602 break;
5603 }
5604 return ret;
5605 }
5606
5607 static int
5608 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5609 {
5610 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5611 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5612 int i;
5613
5614 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5615 u32 offset;
5616
5617 for (offset = 0; offset < size; offset += 4) {
5618
5619 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5620
5621 if (bnx2_reg_rd_ind(bp, start + offset) !=
5622 test_pattern[i]) {
5623 return -ENODEV;
5624 }
5625 }
5626 }
5627 return 0;
5628 }
5629
5630 static int
5631 bnx2_test_memory(struct bnx2 *bp)
5632 {
5633 int ret = 0;
5634 int i;
5635 static struct mem_entry {
5636 u32 offset;
5637 u32 len;
5638 } mem_tbl_5706[] = {
5639 { 0x60000, 0x4000 },
5640 { 0xa0000, 0x3000 },
5641 { 0xe0000, 0x4000 },
5642 { 0x120000, 0x4000 },
5643 { 0x1a0000, 0x4000 },
5644 { 0x160000, 0x4000 },
5645 { 0xffffffff, 0 },
5646 },
5647 mem_tbl_5709[] = {
5648 { 0x60000, 0x4000 },
5649 { 0xa0000, 0x3000 },
5650 { 0xe0000, 0x4000 },
5651 { 0x120000, 0x4000 },
5652 { 0x1a0000, 0x4000 },
5653 { 0xffffffff, 0 },
5654 };
5655 struct mem_entry *mem_tbl;
5656
5657 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5658 mem_tbl = mem_tbl_5709;
5659 else
5660 mem_tbl = mem_tbl_5706;
5661
5662 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5663 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5664 mem_tbl[i].len)) != 0) {
5665 return ret;
5666 }
5667 }
5668
5669 return ret;
5670 }
5671
5672 #define BNX2_MAC_LOOPBACK 0
5673 #define BNX2_PHY_LOOPBACK 1
5674
5675 static int
5676 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5677 {
5678 unsigned int pkt_size, num_pkts, i;
5679 struct sk_buff *skb, *rx_skb;
5680 unsigned char *packet;
5681 u16 rx_start_idx, rx_idx;
5682 dma_addr_t map;
5683 struct tx_bd *txbd;
5684 struct sw_bd *rx_buf;
5685 struct l2_fhdr *rx_hdr;
5686 int ret = -ENODEV;
5687 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5688 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5689 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5690
5691 tx_napi = bnapi;
5692
5693 txr = &tx_napi->tx_ring;
5694 rxr = &bnapi->rx_ring;
5695 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5696 bp->loopback = MAC_LOOPBACK;
5697 bnx2_set_mac_loopback(bp);
5698 }
5699 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5700 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5701 return 0;
5702
5703 bp->loopback = PHY_LOOPBACK;
5704 bnx2_set_phy_loopback(bp);
5705 }
5706 else
5707 return -EINVAL;
5708
5709 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5710 skb = netdev_alloc_skb(bp->dev, pkt_size);
5711 if (!skb)
5712 return -ENOMEM;
5713 packet = skb_put(skb, pkt_size);
5714 memcpy(packet, bp->dev->dev_addr, 6);
5715 memset(packet + 6, 0x0, 8);
5716 for (i = 14; i < pkt_size; i++)
5717 packet[i] = (unsigned char) (i & 0xff);
5718
5719 map = pci_map_single(bp->pdev, skb->data, pkt_size,
5720 PCI_DMA_TODEVICE);
5721 if (pci_dma_mapping_error(bp->pdev, map)) {
5722 dev_kfree_skb(skb);
5723 return -EIO;
5724 }
5725
5726 REG_WR(bp, BNX2_HC_COMMAND,
5727 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5728
5729 REG_RD(bp, BNX2_HC_COMMAND);
5730
5731 udelay(5);
5732 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5733
5734 num_pkts = 0;
5735
5736 txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
5737
5738 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5739 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5740 txbd->tx_bd_mss_nbytes = pkt_size;
5741 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5742
5743 num_pkts++;
5744 txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5745 txr->tx_prod_bseq += pkt_size;
5746
5747 REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5748 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5749
5750 udelay(100);
5751
5752 REG_WR(bp, BNX2_HC_COMMAND,
5753 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5754
5755 REG_RD(bp, BNX2_HC_COMMAND);
5756
5757 udelay(5);
5758
5759 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
5760 dev_kfree_skb(skb);
5761
5762 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
5763 goto loopback_test_done;
5764
5765 rx_idx = bnx2_get_hw_rx_cons(bnapi);
5766 if (rx_idx != rx_start_idx + num_pkts) {
5767 goto loopback_test_done;
5768 }
5769
5770 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
5771 rx_skb = rx_buf->skb;
5772
5773 rx_hdr = rx_buf->desc;
5774 skb_reserve(rx_skb, BNX2_RX_OFFSET);
5775
5776 pci_dma_sync_single_for_cpu(bp->pdev,
5777 dma_unmap_addr(rx_buf, mapping),
5778 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5779
5780 if (rx_hdr->l2_fhdr_status &
5781 (L2_FHDR_ERRORS_BAD_CRC |
5782 L2_FHDR_ERRORS_PHY_DECODE |
5783 L2_FHDR_ERRORS_ALIGNMENT |
5784 L2_FHDR_ERRORS_TOO_SHORT |
5785 L2_FHDR_ERRORS_GIANT_FRAME)) {
5786
5787 goto loopback_test_done;
5788 }
5789
5790 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5791 goto loopback_test_done;
5792 }
5793
5794 for (i = 14; i < pkt_size; i++) {
5795 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5796 goto loopback_test_done;
5797 }
5798 }
5799
5800 ret = 0;
5801
5802 loopback_test_done:
5803 bp->loopback = 0;
5804 return ret;
5805 }
5806
5807 #define BNX2_MAC_LOOPBACK_FAILED 1
5808 #define BNX2_PHY_LOOPBACK_FAILED 2
5809 #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5810 BNX2_PHY_LOOPBACK_FAILED)
5811
5812 static int
5813 bnx2_test_loopback(struct bnx2 *bp)
5814 {
5815 int rc = 0;
5816
5817 if (!netif_running(bp->dev))
5818 return BNX2_LOOPBACK_FAILED;
5819
5820 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5821 spin_lock_bh(&bp->phy_lock);
5822 bnx2_init_phy(bp, 1);
5823 spin_unlock_bh(&bp->phy_lock);
5824 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5825 rc |= BNX2_MAC_LOOPBACK_FAILED;
5826 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5827 rc |= BNX2_PHY_LOOPBACK_FAILED;
5828 return rc;
5829 }
5830
5831 #define NVRAM_SIZE 0x200
5832 #define CRC32_RESIDUAL 0xdebb20e3
5833
5834 static int
5835 bnx2_test_nvram(struct bnx2 *bp)
5836 {
5837 __be32 buf[NVRAM_SIZE / 4];
5838 u8 *data = (u8 *) buf;
5839 int rc = 0;
5840 u32 magic, csum;
5841
5842 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5843 goto test_nvram_done;
5844
5845 magic = be32_to_cpu(buf[0]);
5846 if (magic != 0x669955aa) {
5847 rc = -ENODEV;
5848 goto test_nvram_done;
5849 }
5850
5851 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5852 goto test_nvram_done;
5853
5854 csum = ether_crc_le(0x100, data);
5855 if (csum != CRC32_RESIDUAL) {
5856 rc = -ENODEV;
5857 goto test_nvram_done;
5858 }
5859
5860 csum = ether_crc_le(0x100, data + 0x100);
5861 if (csum != CRC32_RESIDUAL) {
5862 rc = -ENODEV;
5863 }
5864
5865 test_nvram_done:
5866 return rc;
5867 }
5868
5869 static int
5870 bnx2_test_link(struct bnx2 *bp)
5871 {
5872 u32 bmsr;
5873
5874 if (!netif_running(bp->dev))
5875 return -ENODEV;
5876
5877 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5878 if (bp->link_up)
5879 return 0;
5880 return -ENODEV;
5881 }
5882 spin_lock_bh(&bp->phy_lock);
5883 bnx2_enable_bmsr1(bp);
5884 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5885 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5886 bnx2_disable_bmsr1(bp);
5887 spin_unlock_bh(&bp->phy_lock);
5888
5889 if (bmsr & BMSR_LSTATUS) {
5890 return 0;
5891 }
5892 return -ENODEV;
5893 }
5894
5895 static int
5896 bnx2_test_intr(struct bnx2 *bp)
5897 {
5898 int i;
5899 u16 status_idx;
5900
5901 if (!netif_running(bp->dev))
5902 return -ENODEV;
5903
5904 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5905
5906 /* This register is not touched during run-time. */
5907 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5908 REG_RD(bp, BNX2_HC_COMMAND);
5909
5910 for (i = 0; i < 10; i++) {
5911 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5912 status_idx) {
5913
5914 break;
5915 }
5916
5917 msleep_interruptible(10);
5918 }
5919 if (i < 10)
5920 return 0;
5921
5922 return -ENODEV;
5923 }
5924
5925 /* Determining link for parallel detection. */
5926 static int
5927 bnx2_5706_serdes_has_link(struct bnx2 *bp)
5928 {
5929 u32 mode_ctl, an_dbg, exp;
5930
5931 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5932 return 0;
5933
5934 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5935 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5936
5937 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5938 return 0;
5939
5940 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5941 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5942 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5943
5944 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
5945 return 0;
5946
5947 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5948 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5949 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5950
5951 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
5952 return 0;
5953
5954 return 1;
5955 }
5956
5957 static void
5958 bnx2_5706_serdes_timer(struct bnx2 *bp)
5959 {
5960 int check_link = 1;
5961
5962 spin_lock(&bp->phy_lock);
5963 if (bp->serdes_an_pending) {
5964 bp->serdes_an_pending--;
5965 check_link = 0;
5966 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5967 u32 bmcr;
5968
5969 bp->current_interval = BNX2_TIMER_INTERVAL;
5970
5971 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5972
5973 if (bmcr & BMCR_ANENABLE) {
5974 if (bnx2_5706_serdes_has_link(bp)) {
5975 bmcr &= ~BMCR_ANENABLE;
5976 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5977 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5978 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
5979 }
5980 }
5981 }
5982 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
5983 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
5984 u32 phy2;
5985
5986 bnx2_write_phy(bp, 0x17, 0x0f01);
5987 bnx2_read_phy(bp, 0x15, &phy2);
5988 if (phy2 & 0x20) {
5989 u32 bmcr;
5990
5991 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5992 bmcr |= BMCR_ANENABLE;
5993 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5994
5995 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
5996 }
5997 } else
5998 bp->current_interval = BNX2_TIMER_INTERVAL;
5999
6000 if (check_link) {
6001 u32 val;
6002
6003 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
6004 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6005 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6006
6007 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
6008 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
6009 bnx2_5706s_force_link_dn(bp, 1);
6010 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
6011 } else
6012 bnx2_set_link(bp);
6013 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
6014 bnx2_set_link(bp);
6015 }
6016 spin_unlock(&bp->phy_lock);
6017 }
6018
6019 static void
6020 bnx2_5708_serdes_timer(struct bnx2 *bp)
6021 {
6022 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
6023 return;
6024
6025 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
6026 bp->serdes_an_pending = 0;
6027 return;
6028 }
6029
6030 spin_lock(&bp->phy_lock);
6031 if (bp->serdes_an_pending)
6032 bp->serdes_an_pending--;
6033 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
6034 u32 bmcr;
6035
6036 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6037 if (bmcr & BMCR_ANENABLE) {
6038 bnx2_enable_forced_2g5(bp);
6039 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
6040 } else {
6041 bnx2_disable_forced_2g5(bp);
6042 bp->serdes_an_pending = 2;
6043 bp->current_interval = BNX2_TIMER_INTERVAL;
6044 }
6045
6046 } else
6047 bp->current_interval = BNX2_TIMER_INTERVAL;
6048
6049 spin_unlock(&bp->phy_lock);
6050 }
6051
6052 static void
6053 bnx2_timer(unsigned long data)
6054 {
6055 struct bnx2 *bp = (struct bnx2 *) data;
6056
6057 if (!netif_running(bp->dev))
6058 return;
6059
6060 if (atomic_read(&bp->intr_sem) != 0)
6061 goto bnx2_restart_timer;
6062
6063 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
6064 BNX2_FLAG_USING_MSI)
6065 bnx2_chk_missed_msi(bp);
6066
6067 bnx2_send_heart_beat(bp);
6068
6069 bp->stats_blk->stat_FwRxDrop =
6070 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
6071
6072 /* workaround occasional corrupted counters */
6073 if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)
6074 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
6075 BNX2_HC_COMMAND_STATS_NOW);
6076
6077 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6078 if (CHIP_NUM(bp) == CHIP_NUM_5706)
6079 bnx2_5706_serdes_timer(bp);
6080 else
6081 bnx2_5708_serdes_timer(bp);
6082 }
6083
6084 bnx2_restart_timer:
6085 mod_timer(&bp->timer, jiffies + bp->current_interval);
6086 }
6087
6088 static int
6089 bnx2_request_irq(struct bnx2 *bp)
6090 {
6091 unsigned long flags;
6092 struct bnx2_irq *irq;
6093 int rc = 0, i;
6094
6095 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6096 flags = 0;
6097 else
6098 flags = IRQF_SHARED;
6099
6100 for (i = 0; i < bp->irq_nvecs; i++) {
6101 irq = &bp->irq_tbl[i];
6102 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
6103 &bp->bnx2_napi[i]);
6104 if (rc)
6105 break;
6106 irq->requested = 1;
6107 }
6108 return rc;
6109 }
6110
6111 static void
6112 bnx2_free_irq(struct bnx2 *bp)
6113 {
6114 struct bnx2_irq *irq;
6115 int i;
6116
6117 for (i = 0; i < bp->irq_nvecs; i++) {
6118 irq = &bp->irq_tbl[i];
6119 if (irq->requested)
6120 free_irq(irq->vector, &bp->bnx2_napi[i]);
6121 irq->requested = 0;
6122 }
6123 if (bp->flags & BNX2_FLAG_USING_MSI)
6124 pci_disable_msi(bp->pdev);
6125 else if (bp->flags & BNX2_FLAG_USING_MSIX)
6126 pci_disable_msix(bp->pdev);
6127
6128 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
6129 }
6130
6131 static void
6132 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
6133 {
6134 int i, rc;
6135 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
6136 struct net_device *dev = bp->dev;
6137 const int len = sizeof(bp->irq_tbl[0].name);
6138
6139 bnx2_setup_msix_tbl(bp);
6140 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
6141 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
6142 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
6143
6144 /* Need to flush the previous three writes to ensure MSI-X
6145 * is setup properly */
6146 REG_RD(bp, BNX2_PCI_MSIX_CONTROL);
6147
6148 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6149 msix_ent[i].entry = i;
6150 msix_ent[i].vector = 0;
6151 }
6152
6153 rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
6154 if (rc != 0)
6155 return;
6156
6157 bp->irq_nvecs = msix_vecs;
6158 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
6159 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6160 bp->irq_tbl[i].vector = msix_ent[i].vector;
6161 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
6162 bp->irq_tbl[i].handler = bnx2_msi_1shot;
6163 }
6164 }
6165
6166 static void
6167 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
6168 {
6169 int cpus = num_online_cpus();
6170 int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
6171
6172 bp->irq_tbl[0].handler = bnx2_interrupt;
6173 strcpy(bp->irq_tbl[0].name, bp->dev->name);
6174 bp->irq_nvecs = 1;
6175 bp->irq_tbl[0].vector = bp->pdev->irq;
6176
6177 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1)
6178 bnx2_enable_msix(bp, msix_vecs);
6179
6180 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
6181 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6182 if (pci_enable_msi(bp->pdev) == 0) {
6183 bp->flags |= BNX2_FLAG_USING_MSI;
6184 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
6185 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6186 bp->irq_tbl[0].handler = bnx2_msi_1shot;
6187 } else
6188 bp->irq_tbl[0].handler = bnx2_msi;
6189
6190 bp->irq_tbl[0].vector = bp->pdev->irq;
6191 }
6192 }
6193
6194 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
6195 bp->dev->real_num_tx_queues = bp->num_tx_rings;
6196
6197 bp->num_rx_rings = bp->irq_nvecs;
6198 }
6199
6200 /* Called with rtnl_lock */
6201 static int
6202 bnx2_open(struct net_device *dev)
6203 {
6204 struct bnx2 *bp = netdev_priv(dev);
6205 int rc;
6206
6207 netif_carrier_off(dev);
6208
6209 bnx2_set_power_state(bp, PCI_D0);
6210 bnx2_disable_int(bp);
6211
6212 bnx2_setup_int_mode(bp, disable_msi);
6213 bnx2_init_napi(bp);
6214 bnx2_napi_enable(bp);
6215 rc = bnx2_alloc_mem(bp);
6216 if (rc)
6217 goto open_err;
6218
6219 rc = bnx2_request_irq(bp);
6220 if (rc)
6221 goto open_err;
6222
6223 rc = bnx2_init_nic(bp, 1);
6224 if (rc)
6225 goto open_err;
6226
6227 mod_timer(&bp->timer, jiffies + bp->current_interval);
6228
6229 atomic_set(&bp->intr_sem, 0);
6230
6231 memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block));
6232
6233 bnx2_enable_int(bp);
6234
6235 if (bp->flags & BNX2_FLAG_USING_MSI) {
6236 /* Test MSI to make sure it is working
6237 * If MSI test fails, go back to INTx mode
6238 */
6239 if (bnx2_test_intr(bp) != 0) {
6240 netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report this failure to the PCI maintainer and include system chipset information.\n");
6241
6242 bnx2_disable_int(bp);
6243 bnx2_free_irq(bp);
6244
6245 bnx2_setup_int_mode(bp, 1);
6246
6247 rc = bnx2_init_nic(bp, 0);
6248
6249 if (!rc)
6250 rc = bnx2_request_irq(bp);
6251
6252 if (rc) {
6253 del_timer_sync(&bp->timer);
6254 goto open_err;
6255 }
6256 bnx2_enable_int(bp);
6257 }
6258 }
6259 if (bp->flags & BNX2_FLAG_USING_MSI)
6260 netdev_info(dev, "using MSI\n");
6261 else if (bp->flags & BNX2_FLAG_USING_MSIX)
6262 netdev_info(dev, "using MSIX\n");
6263
6264 netif_tx_start_all_queues(dev);
6265
6266 return 0;
6267
6268 open_err:
6269 bnx2_napi_disable(bp);
6270 bnx2_free_skbs(bp);
6271 bnx2_free_irq(bp);
6272 bnx2_free_mem(bp);
6273 return rc;
6274 }
6275
6276 static void
6277 bnx2_reset_task(struct work_struct *work)
6278 {
6279 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
6280
6281 rtnl_lock();
6282 if (!netif_running(bp->dev)) {
6283 rtnl_unlock();
6284 return;
6285 }
6286
6287 bnx2_netif_stop(bp, true);
6288
6289 bnx2_init_nic(bp, 1);
6290
6291 atomic_set(&bp->intr_sem, 1);
6292 bnx2_netif_start(bp, true);
6293 rtnl_unlock();
6294 }
6295
6296 static void
6297 bnx2_dump_state(struct bnx2 *bp)
6298 {
6299 struct net_device *dev = bp->dev;
6300 u32 mcp_p0, mcp_p1;
6301
6302 netdev_err(dev, "DEBUG: intr_sem[%x]\n", atomic_read(&bp->intr_sem));
6303 netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] EMAC_RX_STATUS[%08x]\n",
6304 REG_RD(bp, BNX2_EMAC_TX_STATUS),
6305 REG_RD(bp, BNX2_EMAC_RX_STATUS));
6306 netdev_err(dev, "DEBUG: RPM_MGMT_PKT_CTRL[%08x]\n",
6307 REG_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));
6308 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
6309 mcp_p0 = BNX2_MCP_STATE_P0;
6310 mcp_p1 = BNX2_MCP_STATE_P1;
6311 } else {
6312 mcp_p0 = BNX2_MCP_STATE_P0_5708;
6313 mcp_p1 = BNX2_MCP_STATE_P1_5708;
6314 }
6315 netdev_err(dev, "DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n",
6316 bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1));
6317 netdev_err(dev, "DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n",
6318 REG_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));
6319 if (bp->flags & BNX2_FLAG_USING_MSIX)
6320 netdev_err(dev, "DEBUG: PBA[%08x]\n",
6321 REG_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));
6322 }
6323
6324 static void
6325 bnx2_tx_timeout(struct net_device *dev)
6326 {
6327 struct bnx2 *bp = netdev_priv(dev);
6328
6329 bnx2_dump_state(bp);
6330
6331 /* This allows the netif to be shutdown gracefully before resetting */
6332 schedule_work(&bp->reset_task);
6333 }
6334
6335 #ifdef BCM_VLAN
6336 /* Called with rtnl_lock */
6337 static void
6338 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
6339 {
6340 struct bnx2 *bp = netdev_priv(dev);
6341
6342 if (netif_running(dev))
6343 bnx2_netif_stop(bp, false);
6344
6345 bp->vlgrp = vlgrp;
6346
6347 if (!netif_running(dev))
6348 return;
6349
6350 bnx2_set_rx_mode(dev);
6351 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
6352 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
6353
6354 bnx2_netif_start(bp, false);
6355 }
6356 #endif
6357
6358 /* Called with netif_tx_lock.
6359 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
6360 * netif_wake_queue().
6361 */
6362 static netdev_tx_t
6363 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
6364 {
6365 struct bnx2 *bp = netdev_priv(dev);
6366 dma_addr_t mapping;
6367 struct tx_bd *txbd;
6368 struct sw_tx_bd *tx_buf;
6369 u32 len, vlan_tag_flags, last_frag, mss;
6370 u16 prod, ring_prod;
6371 int i;
6372 struct bnx2_napi *bnapi;
6373 struct bnx2_tx_ring_info *txr;
6374 struct netdev_queue *txq;
6375
6376 /* Determine which tx ring we will be placed on */
6377 i = skb_get_queue_mapping(skb);
6378 bnapi = &bp->bnx2_napi[i];
6379 txr = &bnapi->tx_ring;
6380 txq = netdev_get_tx_queue(dev, i);
6381
6382 if (unlikely(bnx2_tx_avail(bp, txr) <
6383 (skb_shinfo(skb)->nr_frags + 1))) {
6384 netif_tx_stop_queue(txq);
6385 netdev_err(dev, "BUG! Tx ring full when queue awake!\n");
6386
6387 return NETDEV_TX_BUSY;
6388 }
6389 len = skb_headlen(skb);
6390 prod = txr->tx_prod;
6391 ring_prod = TX_RING_IDX(prod);
6392
6393 vlan_tag_flags = 0;
6394 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6395 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6396 }
6397
6398 #ifdef BCM_VLAN
6399 if (bp->vlgrp && vlan_tx_tag_present(skb)) {
6400 vlan_tag_flags |=
6401 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6402 }
6403 #endif
6404 if ((mss = skb_shinfo(skb)->gso_size)) {
6405 u32 tcp_opt_len;
6406 struct iphdr *iph;
6407
6408 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6409
6410 tcp_opt_len = tcp_optlen(skb);
6411
6412 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6413 u32 tcp_off = skb_transport_offset(skb) -
6414 sizeof(struct ipv6hdr) - ETH_HLEN;
6415
6416 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6417 TX_BD_FLAGS_SW_FLAGS;
6418 if (likely(tcp_off == 0))
6419 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6420 else {
6421 tcp_off >>= 3;
6422 vlan_tag_flags |= ((tcp_off & 0x3) <<
6423 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6424 ((tcp_off & 0x10) <<
6425 TX_BD_FLAGS_TCP6_OFF4_SHL);
6426 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6427 }
6428 } else {
6429 iph = ip_hdr(skb);
6430 if (tcp_opt_len || (iph->ihl > 5)) {
6431 vlan_tag_flags |= ((iph->ihl - 5) +
6432 (tcp_opt_len >> 2)) << 8;
6433 }
6434 }
6435 } else
6436 mss = 0;
6437
6438 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6439 if (pci_dma_mapping_error(bp->pdev, mapping)) {
6440 dev_kfree_skb(skb);
6441 return NETDEV_TX_OK;
6442 }
6443
6444 tx_buf = &txr->tx_buf_ring[ring_prod];
6445 tx_buf->skb = skb;
6446 dma_unmap_addr_set(tx_buf, mapping, mapping);
6447
6448 txbd = &txr->tx_desc_ring[ring_prod];
6449
6450 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6451 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6452 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6453 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6454
6455 last_frag = skb_shinfo(skb)->nr_frags;
6456 tx_buf->nr_frags = last_frag;
6457 tx_buf->is_gso = skb_is_gso(skb);
6458
6459 for (i = 0; i < last_frag; i++) {
6460 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6461
6462 prod = NEXT_TX_BD(prod);
6463 ring_prod = TX_RING_IDX(prod);
6464 txbd = &txr->tx_desc_ring[ring_prod];
6465
6466 len = frag->size;
6467 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
6468 len, PCI_DMA_TODEVICE);
6469 if (pci_dma_mapping_error(bp->pdev, mapping))
6470 goto dma_error;
6471 dma_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping,
6472 mapping);
6473
6474 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6475 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6476 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6477 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6478
6479 }
6480 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6481
6482 prod = NEXT_TX_BD(prod);
6483 txr->tx_prod_bseq += skb->len;
6484
6485 REG_WR16(bp, txr->tx_bidx_addr, prod);
6486 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
6487
6488 mmiowb();
6489
6490 txr->tx_prod = prod;
6491
6492 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
6493 netif_tx_stop_queue(txq);
6494 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
6495 netif_tx_wake_queue(txq);
6496 }
6497
6498 return NETDEV_TX_OK;
6499 dma_error:
6500 /* save value of frag that failed */
6501 last_frag = i;
6502
6503 /* start back at beginning and unmap skb */
6504 prod = txr->tx_prod;
6505 ring_prod = TX_RING_IDX(prod);
6506 tx_buf = &txr->tx_buf_ring[ring_prod];
6507 tx_buf->skb = NULL;
6508 pci_unmap_single(bp->pdev, dma_unmap_addr(tx_buf, mapping),
6509 skb_headlen(skb), PCI_DMA_TODEVICE);
6510
6511 /* unmap remaining mapped pages */
6512 for (i = 0; i < last_frag; i++) {
6513 prod = NEXT_TX_BD(prod);
6514 ring_prod = TX_RING_IDX(prod);
6515 tx_buf = &txr->tx_buf_ring[ring_prod];
6516 pci_unmap_page(bp->pdev, dma_unmap_addr(tx_buf, mapping),
6517 skb_shinfo(skb)->frags[i].size,
6518 PCI_DMA_TODEVICE);
6519 }
6520
6521 dev_kfree_skb(skb);
6522 return NETDEV_TX_OK;
6523 }
6524
6525 /* Called with rtnl_lock */
6526 static int
6527 bnx2_close(struct net_device *dev)
6528 {
6529 struct bnx2 *bp = netdev_priv(dev);
6530
6531 cancel_work_sync(&bp->reset_task);
6532
6533 bnx2_disable_int_sync(bp);
6534 bnx2_napi_disable(bp);
6535 del_timer_sync(&bp->timer);
6536 bnx2_shutdown_chip(bp);
6537 bnx2_free_irq(bp);
6538 bnx2_free_skbs(bp);
6539 bnx2_free_mem(bp);
6540 bp->link_up = 0;
6541 netif_carrier_off(bp->dev);
6542 bnx2_set_power_state(bp, PCI_D3hot);
6543 return 0;
6544 }
6545
6546 static void
6547 bnx2_save_stats(struct bnx2 *bp)
6548 {
6549 u32 *hw_stats = (u32 *) bp->stats_blk;
6550 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
6551 int i;
6552
6553 /* The 1st 10 counters are 64-bit counters */
6554 for (i = 0; i < 20; i += 2) {
6555 u32 hi;
6556 u64 lo;
6557
6558 hi = temp_stats[i] + hw_stats[i];
6559 lo = (u64) temp_stats[i + 1] + (u64) hw_stats[i + 1];
6560 if (lo > 0xffffffff)
6561 hi++;
6562 temp_stats[i] = hi;
6563 temp_stats[i + 1] = lo & 0xffffffff;
6564 }
6565
6566 for ( ; i < sizeof(struct statistics_block) / 4; i++)
6567 temp_stats[i] += hw_stats[i];
6568 }
6569
6570 #define GET_64BIT_NET_STATS64(ctr) \
6571 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
6572 (unsigned long) (ctr##_lo)
6573
6574 #define GET_64BIT_NET_STATS32(ctr) \
6575 (ctr##_lo)
6576
6577 #if (BITS_PER_LONG == 64)
6578 #define GET_64BIT_NET_STATS(ctr) \
6579 GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \
6580 GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr)
6581 #else
6582 #define GET_64BIT_NET_STATS(ctr) \
6583 GET_64BIT_NET_STATS32(bp->stats_blk->ctr) + \
6584 GET_64BIT_NET_STATS32(bp->temp_stats_blk->ctr)
6585 #endif
6586
6587 #define GET_32BIT_NET_STATS(ctr) \
6588 (unsigned long) (bp->stats_blk->ctr + \
6589 bp->temp_stats_blk->ctr)
6590
6591 static struct net_device_stats *
6592 bnx2_get_stats(struct net_device *dev)
6593 {
6594 struct bnx2 *bp = netdev_priv(dev);
6595 struct net_device_stats *net_stats = &dev->stats;
6596
6597 if (bp->stats_blk == NULL) {
6598 return net_stats;
6599 }
6600 net_stats->rx_packets =
6601 GET_64BIT_NET_STATS(stat_IfHCInUcastPkts) +
6602 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts) +
6603 GET_64BIT_NET_STATS(stat_IfHCInBroadcastPkts);
6604
6605 net_stats->tx_packets =
6606 GET_64BIT_NET_STATS(stat_IfHCOutUcastPkts) +
6607 GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts) +
6608 GET_64BIT_NET_STATS(stat_IfHCOutBroadcastPkts);
6609
6610 net_stats->rx_bytes =
6611 GET_64BIT_NET_STATS(stat_IfHCInOctets);
6612
6613 net_stats->tx_bytes =
6614 GET_64BIT_NET_STATS(stat_IfHCOutOctets);
6615
6616 net_stats->multicast =
6617 GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts);
6618
6619 net_stats->collisions =
6620 GET_32BIT_NET_STATS(stat_EtherStatsCollisions);
6621
6622 net_stats->rx_length_errors =
6623 GET_32BIT_NET_STATS(stat_EtherStatsUndersizePkts) +
6624 GET_32BIT_NET_STATS(stat_EtherStatsOverrsizePkts);
6625
6626 net_stats->rx_over_errors =
6627 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6628 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards);
6629
6630 net_stats->rx_frame_errors =
6631 GET_32BIT_NET_STATS(stat_Dot3StatsAlignmentErrors);
6632
6633 net_stats->rx_crc_errors =
6634 GET_32BIT_NET_STATS(stat_Dot3StatsFCSErrors);
6635
6636 net_stats->rx_errors = net_stats->rx_length_errors +
6637 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6638 net_stats->rx_crc_errors;
6639
6640 net_stats->tx_aborted_errors =
6641 GET_32BIT_NET_STATS(stat_Dot3StatsExcessiveCollisions) +
6642 GET_32BIT_NET_STATS(stat_Dot3StatsLateCollisions);
6643
6644 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6645 (CHIP_ID(bp) == CHIP_ID_5708_A0))
6646 net_stats->tx_carrier_errors = 0;
6647 else {
6648 net_stats->tx_carrier_errors =
6649 GET_32BIT_NET_STATS(stat_Dot3StatsCarrierSenseErrors);
6650 }
6651
6652 net_stats->tx_errors =
6653 GET_32BIT_NET_STATS(stat_emac_tx_stat_dot3statsinternalmactransmiterrors) +
6654 net_stats->tx_aborted_errors +
6655 net_stats->tx_carrier_errors;
6656
6657 net_stats->rx_missed_errors =
6658 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6659 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards) +
6660 GET_32BIT_NET_STATS(stat_FwRxDrop);
6661
6662 return net_stats;
6663 }
6664
6665 /* All ethtool functions called with rtnl_lock */
6666
6667 static int
6668 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6669 {
6670 struct bnx2 *bp = netdev_priv(dev);
6671 int support_serdes = 0, support_copper = 0;
6672
6673 cmd->supported = SUPPORTED_Autoneg;
6674 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6675 support_serdes = 1;
6676 support_copper = 1;
6677 } else if (bp->phy_port == PORT_FIBRE)
6678 support_serdes = 1;
6679 else
6680 support_copper = 1;
6681
6682 if (support_serdes) {
6683 cmd->supported |= SUPPORTED_1000baseT_Full |
6684 SUPPORTED_FIBRE;
6685 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6686 cmd->supported |= SUPPORTED_2500baseX_Full;
6687
6688 }
6689 if (support_copper) {
6690 cmd->supported |= SUPPORTED_10baseT_Half |
6691 SUPPORTED_10baseT_Full |
6692 SUPPORTED_100baseT_Half |
6693 SUPPORTED_100baseT_Full |
6694 SUPPORTED_1000baseT_Full |
6695 SUPPORTED_TP;
6696
6697 }
6698
6699 spin_lock_bh(&bp->phy_lock);
6700 cmd->port = bp->phy_port;
6701 cmd->advertising = bp->advertising;
6702
6703 if (bp->autoneg & AUTONEG_SPEED) {
6704 cmd->autoneg = AUTONEG_ENABLE;
6705 }
6706 else {
6707 cmd->autoneg = AUTONEG_DISABLE;
6708 }
6709
6710 if (netif_carrier_ok(dev)) {
6711 cmd->speed = bp->line_speed;
6712 cmd->duplex = bp->duplex;
6713 }
6714 else {
6715 cmd->speed = -1;
6716 cmd->duplex = -1;
6717 }
6718 spin_unlock_bh(&bp->phy_lock);
6719
6720 cmd->transceiver = XCVR_INTERNAL;
6721 cmd->phy_address = bp->phy_addr;
6722
6723 return 0;
6724 }
6725
6726 static int
6727 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6728 {
6729 struct bnx2 *bp = netdev_priv(dev);
6730 u8 autoneg = bp->autoneg;
6731 u8 req_duplex = bp->req_duplex;
6732 u16 req_line_speed = bp->req_line_speed;
6733 u32 advertising = bp->advertising;
6734 int err = -EINVAL;
6735
6736 spin_lock_bh(&bp->phy_lock);
6737
6738 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6739 goto err_out_unlock;
6740
6741 if (cmd->port != bp->phy_port &&
6742 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6743 goto err_out_unlock;
6744
6745 /* If device is down, we can store the settings only if the user
6746 * is setting the currently active port.
6747 */
6748 if (!netif_running(dev) && cmd->port != bp->phy_port)
6749 goto err_out_unlock;
6750
6751 if (cmd->autoneg == AUTONEG_ENABLE) {
6752 autoneg |= AUTONEG_SPEED;
6753
6754 advertising = cmd->advertising;
6755 if (cmd->port == PORT_TP) {
6756 advertising &= ETHTOOL_ALL_COPPER_SPEED;
6757 if (!advertising)
6758 advertising = ETHTOOL_ALL_COPPER_SPEED;
6759 } else {
6760 advertising &= ETHTOOL_ALL_FIBRE_SPEED;
6761 if (!advertising)
6762 advertising = ETHTOOL_ALL_FIBRE_SPEED;
6763 }
6764 advertising |= ADVERTISED_Autoneg;
6765 }
6766 else {
6767 if (cmd->port == PORT_FIBRE) {
6768 if ((cmd->speed != SPEED_1000 &&
6769 cmd->speed != SPEED_2500) ||
6770 (cmd->duplex != DUPLEX_FULL))
6771 goto err_out_unlock;
6772
6773 if (cmd->speed == SPEED_2500 &&
6774 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
6775 goto err_out_unlock;
6776 }
6777 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6778 goto err_out_unlock;
6779
6780 autoneg &= ~AUTONEG_SPEED;
6781 req_line_speed = cmd->speed;
6782 req_duplex = cmd->duplex;
6783 advertising = 0;
6784 }
6785
6786 bp->autoneg = autoneg;
6787 bp->advertising = advertising;
6788 bp->req_line_speed = req_line_speed;
6789 bp->req_duplex = req_duplex;
6790
6791 err = 0;
6792 /* If device is down, the new settings will be picked up when it is
6793 * brought up.
6794 */
6795 if (netif_running(dev))
6796 err = bnx2_setup_phy(bp, cmd->port);
6797
6798 err_out_unlock:
6799 spin_unlock_bh(&bp->phy_lock);
6800
6801 return err;
6802 }
6803
6804 static void
6805 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6806 {
6807 struct bnx2 *bp = netdev_priv(dev);
6808
6809 strcpy(info->driver, DRV_MODULE_NAME);
6810 strcpy(info->version, DRV_MODULE_VERSION);
6811 strcpy(info->bus_info, pci_name(bp->pdev));
6812 strcpy(info->fw_version, bp->fw_version);
6813 }
6814
6815 #define BNX2_REGDUMP_LEN (32 * 1024)
6816
6817 static int
6818 bnx2_get_regs_len(struct net_device *dev)
6819 {
6820 return BNX2_REGDUMP_LEN;
6821 }
6822
6823 static void
6824 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6825 {
6826 u32 *p = _p, i, offset;
6827 u8 *orig_p = _p;
6828 struct bnx2 *bp = netdev_priv(dev);
6829 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6830 0x0800, 0x0880, 0x0c00, 0x0c10,
6831 0x0c30, 0x0d08, 0x1000, 0x101c,
6832 0x1040, 0x1048, 0x1080, 0x10a4,
6833 0x1400, 0x1490, 0x1498, 0x14f0,
6834 0x1500, 0x155c, 0x1580, 0x15dc,
6835 0x1600, 0x1658, 0x1680, 0x16d8,
6836 0x1800, 0x1820, 0x1840, 0x1854,
6837 0x1880, 0x1894, 0x1900, 0x1984,
6838 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6839 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6840 0x2000, 0x2030, 0x23c0, 0x2400,
6841 0x2800, 0x2820, 0x2830, 0x2850,
6842 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6843 0x3c00, 0x3c94, 0x4000, 0x4010,
6844 0x4080, 0x4090, 0x43c0, 0x4458,
6845 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6846 0x4fc0, 0x5010, 0x53c0, 0x5444,
6847 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6848 0x5fc0, 0x6000, 0x6400, 0x6428,
6849 0x6800, 0x6848, 0x684c, 0x6860,
6850 0x6888, 0x6910, 0x8000 };
6851
6852 regs->version = 0;
6853
6854 memset(p, 0, BNX2_REGDUMP_LEN);
6855
6856 if (!netif_running(bp->dev))
6857 return;
6858
6859 i = 0;
6860 offset = reg_boundaries[0];
6861 p += offset;
6862 while (offset < BNX2_REGDUMP_LEN) {
6863 *p++ = REG_RD(bp, offset);
6864 offset += 4;
6865 if (offset == reg_boundaries[i + 1]) {
6866 offset = reg_boundaries[i + 2];
6867 p = (u32 *) (orig_p + offset);
6868 i += 2;
6869 }
6870 }
6871 }
6872
6873 static void
6874 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6875 {
6876 struct bnx2 *bp = netdev_priv(dev);
6877
6878 if (bp->flags & BNX2_FLAG_NO_WOL) {
6879 wol->supported = 0;
6880 wol->wolopts = 0;
6881 }
6882 else {
6883 wol->supported = WAKE_MAGIC;
6884 if (bp->wol)
6885 wol->wolopts = WAKE_MAGIC;
6886 else
6887 wol->wolopts = 0;
6888 }
6889 memset(&wol->sopass, 0, sizeof(wol->sopass));
6890 }
6891
6892 static int
6893 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6894 {
6895 struct bnx2 *bp = netdev_priv(dev);
6896
6897 if (wol->wolopts & ~WAKE_MAGIC)
6898 return -EINVAL;
6899
6900 if (wol->wolopts & WAKE_MAGIC) {
6901 if (bp->flags & BNX2_FLAG_NO_WOL)
6902 return -EINVAL;
6903
6904 bp->wol = 1;
6905 }
6906 else {
6907 bp->wol = 0;
6908 }
6909 return 0;
6910 }
6911
6912 static int
6913 bnx2_nway_reset(struct net_device *dev)
6914 {
6915 struct bnx2 *bp = netdev_priv(dev);
6916 u32 bmcr;
6917
6918 if (!netif_running(dev))
6919 return -EAGAIN;
6920
6921 if (!(bp->autoneg & AUTONEG_SPEED)) {
6922 return -EINVAL;
6923 }
6924
6925 spin_lock_bh(&bp->phy_lock);
6926
6927 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6928 int rc;
6929
6930 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6931 spin_unlock_bh(&bp->phy_lock);
6932 return rc;
6933 }
6934
6935 /* Force a link down visible on the other side */
6936 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6937 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
6938 spin_unlock_bh(&bp->phy_lock);
6939
6940 msleep(20);
6941
6942 spin_lock_bh(&bp->phy_lock);
6943
6944 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
6945 bp->serdes_an_pending = 1;
6946 mod_timer(&bp->timer, jiffies + bp->current_interval);
6947 }
6948
6949 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6950 bmcr &= ~BMCR_LOOPBACK;
6951 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
6952
6953 spin_unlock_bh(&bp->phy_lock);
6954
6955 return 0;
6956 }
6957
6958 static u32
6959 bnx2_get_link(struct net_device *dev)
6960 {
6961 struct bnx2 *bp = netdev_priv(dev);
6962
6963 return bp->link_up;
6964 }
6965
6966 static int
6967 bnx2_get_eeprom_len(struct net_device *dev)
6968 {
6969 struct bnx2 *bp = netdev_priv(dev);
6970
6971 if (bp->flash_info == NULL)
6972 return 0;
6973
6974 return (int) bp->flash_size;
6975 }
6976
6977 static int
6978 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6979 u8 *eebuf)
6980 {
6981 struct bnx2 *bp = netdev_priv(dev);
6982 int rc;
6983
6984 if (!netif_running(dev))
6985 return -EAGAIN;
6986
6987 /* parameters already validated in ethtool_get_eeprom */
6988
6989 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6990
6991 return rc;
6992 }
6993
6994 static int
6995 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6996 u8 *eebuf)
6997 {
6998 struct bnx2 *bp = netdev_priv(dev);
6999 int rc;
7000
7001 if (!netif_running(dev))
7002 return -EAGAIN;
7003
7004 /* parameters already validated in ethtool_set_eeprom */
7005
7006 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
7007
7008 return rc;
7009 }
7010
7011 static int
7012 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7013 {
7014 struct bnx2 *bp = netdev_priv(dev);
7015
7016 memset(coal, 0, sizeof(struct ethtool_coalesce));
7017
7018 coal->rx_coalesce_usecs = bp->rx_ticks;
7019 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
7020 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
7021 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
7022
7023 coal->tx_coalesce_usecs = bp->tx_ticks;
7024 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
7025 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
7026 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
7027
7028 coal->stats_block_coalesce_usecs = bp->stats_ticks;
7029
7030 return 0;
7031 }
7032
7033 static int
7034 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7035 {
7036 struct bnx2 *bp = netdev_priv(dev);
7037
7038 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
7039 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
7040
7041 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
7042 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
7043
7044 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
7045 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
7046
7047 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
7048 if (bp->rx_quick_cons_trip_int > 0xff)
7049 bp->rx_quick_cons_trip_int = 0xff;
7050
7051 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
7052 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
7053
7054 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
7055 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
7056
7057 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
7058 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
7059
7060 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
7061 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
7062 0xff;
7063
7064 bp->stats_ticks = coal->stats_block_coalesce_usecs;
7065 if (bp->flags & BNX2_FLAG_BROKEN_STATS) {
7066 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
7067 bp->stats_ticks = USEC_PER_SEC;
7068 }
7069 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
7070 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7071 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7072
7073 if (netif_running(bp->dev)) {
7074 bnx2_netif_stop(bp, true);
7075 bnx2_init_nic(bp, 0);
7076 bnx2_netif_start(bp, true);
7077 }
7078
7079 return 0;
7080 }
7081
7082 static void
7083 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7084 {
7085 struct bnx2 *bp = netdev_priv(dev);
7086
7087 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
7088 ering->rx_mini_max_pending = 0;
7089 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
7090
7091 ering->rx_pending = bp->rx_ring_size;
7092 ering->rx_mini_pending = 0;
7093 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
7094
7095 ering->tx_max_pending = MAX_TX_DESC_CNT;
7096 ering->tx_pending = bp->tx_ring_size;
7097 }
7098
7099 static int
7100 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
7101 {
7102 if (netif_running(bp->dev)) {
7103 /* Reset will erase chipset stats; save them */
7104 bnx2_save_stats(bp);
7105
7106 bnx2_netif_stop(bp, true);
7107 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
7108 bnx2_free_skbs(bp);
7109 bnx2_free_mem(bp);
7110 }
7111
7112 bnx2_set_rx_ring_size(bp, rx);
7113 bp->tx_ring_size = tx;
7114
7115 if (netif_running(bp->dev)) {
7116 int rc;
7117
7118 rc = bnx2_alloc_mem(bp);
7119 if (!rc)
7120 rc = bnx2_init_nic(bp, 0);
7121
7122 if (rc) {
7123 bnx2_napi_enable(bp);
7124 dev_close(bp->dev);
7125 return rc;
7126 }
7127 #ifdef BCM_CNIC
7128 mutex_lock(&bp->cnic_lock);
7129 /* Let cnic know about the new status block. */
7130 if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD)
7131 bnx2_setup_cnic_irq_info(bp);
7132 mutex_unlock(&bp->cnic_lock);
7133 #endif
7134 bnx2_netif_start(bp, true);
7135 }
7136 return 0;
7137 }
7138
7139 static int
7140 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7141 {
7142 struct bnx2 *bp = netdev_priv(dev);
7143 int rc;
7144
7145 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
7146 (ering->tx_pending > MAX_TX_DESC_CNT) ||
7147 (ering->tx_pending <= MAX_SKB_FRAGS)) {
7148
7149 return -EINVAL;
7150 }
7151 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
7152 return rc;
7153 }
7154
7155 static void
7156 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7157 {
7158 struct bnx2 *bp = netdev_priv(dev);
7159
7160 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
7161 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
7162 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
7163 }
7164
7165 static int
7166 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7167 {
7168 struct bnx2 *bp = netdev_priv(dev);
7169
7170 bp->req_flow_ctrl = 0;
7171 if (epause->rx_pause)
7172 bp->req_flow_ctrl |= FLOW_CTRL_RX;
7173 if (epause->tx_pause)
7174 bp->req_flow_ctrl |= FLOW_CTRL_TX;
7175
7176 if (epause->autoneg) {
7177 bp->autoneg |= AUTONEG_FLOW_CTRL;
7178 }
7179 else {
7180 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
7181 }
7182
7183 if (netif_running(dev)) {
7184 spin_lock_bh(&bp->phy_lock);
7185 bnx2_setup_phy(bp, bp->phy_port);
7186 spin_unlock_bh(&bp->phy_lock);
7187 }
7188
7189 return 0;
7190 }
7191
7192 static u32
7193 bnx2_get_rx_csum(struct net_device *dev)
7194 {
7195 struct bnx2 *bp = netdev_priv(dev);
7196
7197 return bp->rx_csum;
7198 }
7199
7200 static int
7201 bnx2_set_rx_csum(struct net_device *dev, u32 data)
7202 {
7203 struct bnx2 *bp = netdev_priv(dev);
7204
7205 bp->rx_csum = data;
7206 return 0;
7207 }
7208
7209 static int
7210 bnx2_set_tso(struct net_device *dev, u32 data)
7211 {
7212 struct bnx2 *bp = netdev_priv(dev);
7213
7214 if (data) {
7215 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
7216 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7217 dev->features |= NETIF_F_TSO6;
7218 } else
7219 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
7220 NETIF_F_TSO_ECN);
7221 return 0;
7222 }
7223
7224 static struct {
7225 char string[ETH_GSTRING_LEN];
7226 } bnx2_stats_str_arr[] = {
7227 { "rx_bytes" },
7228 { "rx_error_bytes" },
7229 { "tx_bytes" },
7230 { "tx_error_bytes" },
7231 { "rx_ucast_packets" },
7232 { "rx_mcast_packets" },
7233 { "rx_bcast_packets" },
7234 { "tx_ucast_packets" },
7235 { "tx_mcast_packets" },
7236 { "tx_bcast_packets" },
7237 { "tx_mac_errors" },
7238 { "tx_carrier_errors" },
7239 { "rx_crc_errors" },
7240 { "rx_align_errors" },
7241 { "tx_single_collisions" },
7242 { "tx_multi_collisions" },
7243 { "tx_deferred" },
7244 { "tx_excess_collisions" },
7245 { "tx_late_collisions" },
7246 { "tx_total_collisions" },
7247 { "rx_fragments" },
7248 { "rx_jabbers" },
7249 { "rx_undersize_packets" },
7250 { "rx_oversize_packets" },
7251 { "rx_64_byte_packets" },
7252 { "rx_65_to_127_byte_packets" },
7253 { "rx_128_to_255_byte_packets" },
7254 { "rx_256_to_511_byte_packets" },
7255 { "rx_512_to_1023_byte_packets" },
7256 { "rx_1024_to_1522_byte_packets" },
7257 { "rx_1523_to_9022_byte_packets" },
7258 { "tx_64_byte_packets" },
7259 { "tx_65_to_127_byte_packets" },
7260 { "tx_128_to_255_byte_packets" },
7261 { "tx_256_to_511_byte_packets" },
7262 { "tx_512_to_1023_byte_packets" },
7263 { "tx_1024_to_1522_byte_packets" },
7264 { "tx_1523_to_9022_byte_packets" },
7265 { "rx_xon_frames" },
7266 { "rx_xoff_frames" },
7267 { "tx_xon_frames" },
7268 { "tx_xoff_frames" },
7269 { "rx_mac_ctrl_frames" },
7270 { "rx_filtered_packets" },
7271 { "rx_ftq_discards" },
7272 { "rx_discards" },
7273 { "rx_fw_discards" },
7274 };
7275
7276 #define BNX2_NUM_STATS (sizeof(bnx2_stats_str_arr)/\
7277 sizeof(bnx2_stats_str_arr[0]))
7278
7279 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
7280
7281 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
7282 STATS_OFFSET32(stat_IfHCInOctets_hi),
7283 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
7284 STATS_OFFSET32(stat_IfHCOutOctets_hi),
7285 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
7286 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
7287 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
7288 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
7289 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
7290 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
7291 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
7292 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
7293 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
7294 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
7295 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
7296 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
7297 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
7298 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
7299 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
7300 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
7301 STATS_OFFSET32(stat_EtherStatsCollisions),
7302 STATS_OFFSET32(stat_EtherStatsFragments),
7303 STATS_OFFSET32(stat_EtherStatsJabbers),
7304 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
7305 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
7306 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
7307 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
7308 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
7309 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
7310 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
7311 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
7312 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
7313 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
7314 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
7315 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
7316 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
7317 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
7318 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
7319 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
7320 STATS_OFFSET32(stat_XonPauseFramesReceived),
7321 STATS_OFFSET32(stat_XoffPauseFramesReceived),
7322 STATS_OFFSET32(stat_OutXonSent),
7323 STATS_OFFSET32(stat_OutXoffSent),
7324 STATS_OFFSET32(stat_MacControlFramesReceived),
7325 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
7326 STATS_OFFSET32(stat_IfInFTQDiscards),
7327 STATS_OFFSET32(stat_IfInMBUFDiscards),
7328 STATS_OFFSET32(stat_FwRxDrop),
7329 };
7330
7331 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
7332 * skipped because of errata.
7333 */
7334 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
7335 8,0,8,8,8,8,8,8,8,8,
7336 4,0,4,4,4,4,4,4,4,4,
7337 4,4,4,4,4,4,4,4,4,4,
7338 4,4,4,4,4,4,4,4,4,4,
7339 4,4,4,4,4,4,4,
7340 };
7341
7342 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
7343 8,0,8,8,8,8,8,8,8,8,
7344 4,4,4,4,4,4,4,4,4,4,
7345 4,4,4,4,4,4,4,4,4,4,
7346 4,4,4,4,4,4,4,4,4,4,
7347 4,4,4,4,4,4,4,
7348 };
7349
7350 #define BNX2_NUM_TESTS 6
7351
7352 static struct {
7353 char string[ETH_GSTRING_LEN];
7354 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
7355 { "register_test (offline)" },
7356 { "memory_test (offline)" },
7357 { "loopback_test (offline)" },
7358 { "nvram_test (online)" },
7359 { "interrupt_test (online)" },
7360 { "link_test (online)" },
7361 };
7362
7363 static int
7364 bnx2_get_sset_count(struct net_device *dev, int sset)
7365 {
7366 switch (sset) {
7367 case ETH_SS_TEST:
7368 return BNX2_NUM_TESTS;
7369 case ETH_SS_STATS:
7370 return BNX2_NUM_STATS;
7371 default:
7372 return -EOPNOTSUPP;
7373 }
7374 }
7375
7376 static void
7377 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
7378 {
7379 struct bnx2 *bp = netdev_priv(dev);
7380
7381 bnx2_set_power_state(bp, PCI_D0);
7382
7383 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
7384 if (etest->flags & ETH_TEST_FL_OFFLINE) {
7385 int i;
7386
7387 bnx2_netif_stop(bp, true);
7388 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
7389 bnx2_free_skbs(bp);
7390
7391 if (bnx2_test_registers(bp) != 0) {
7392 buf[0] = 1;
7393 etest->flags |= ETH_TEST_FL_FAILED;
7394 }
7395 if (bnx2_test_memory(bp) != 0) {
7396 buf[1] = 1;
7397 etest->flags |= ETH_TEST_FL_FAILED;
7398 }
7399 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
7400 etest->flags |= ETH_TEST_FL_FAILED;
7401
7402 if (!netif_running(bp->dev))
7403 bnx2_shutdown_chip(bp);
7404 else {
7405 bnx2_init_nic(bp, 1);
7406 bnx2_netif_start(bp, true);
7407 }
7408
7409 /* wait for link up */
7410 for (i = 0; i < 7; i++) {
7411 if (bp->link_up)
7412 break;
7413 msleep_interruptible(1000);
7414 }
7415 }
7416
7417 if (bnx2_test_nvram(bp) != 0) {
7418 buf[3] = 1;
7419 etest->flags |= ETH_TEST_FL_FAILED;
7420 }
7421 if (bnx2_test_intr(bp) != 0) {
7422 buf[4] = 1;
7423 etest->flags |= ETH_TEST_FL_FAILED;
7424 }
7425
7426 if (bnx2_test_link(bp) != 0) {
7427 buf[5] = 1;
7428 etest->flags |= ETH_TEST_FL_FAILED;
7429
7430 }
7431 if (!netif_running(bp->dev))
7432 bnx2_set_power_state(bp, PCI_D3hot);
7433 }
7434
7435 static void
7436 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7437 {
7438 switch (stringset) {
7439 case ETH_SS_STATS:
7440 memcpy(buf, bnx2_stats_str_arr,
7441 sizeof(bnx2_stats_str_arr));
7442 break;
7443 case ETH_SS_TEST:
7444 memcpy(buf, bnx2_tests_str_arr,
7445 sizeof(bnx2_tests_str_arr));
7446 break;
7447 }
7448 }
7449
7450 static void
7451 bnx2_get_ethtool_stats(struct net_device *dev,
7452 struct ethtool_stats *stats, u64 *buf)
7453 {
7454 struct bnx2 *bp = netdev_priv(dev);
7455 int i;
7456 u32 *hw_stats = (u32 *) bp->stats_blk;
7457 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
7458 u8 *stats_len_arr = NULL;
7459
7460 if (hw_stats == NULL) {
7461 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7462 return;
7463 }
7464
7465 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7466 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7467 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7468 (CHIP_ID(bp) == CHIP_ID_5708_A0))
7469 stats_len_arr = bnx2_5706_stats_len_arr;
7470 else
7471 stats_len_arr = bnx2_5708_stats_len_arr;
7472
7473 for (i = 0; i < BNX2_NUM_STATS; i++) {
7474 unsigned long offset;
7475
7476 if (stats_len_arr[i] == 0) {
7477 /* skip this counter */
7478 buf[i] = 0;
7479 continue;
7480 }
7481
7482 offset = bnx2_stats_offset_arr[i];
7483 if (stats_len_arr[i] == 4) {
7484 /* 4-byte counter */
7485 buf[i] = (u64) *(hw_stats + offset) +
7486 *(temp_stats + offset);
7487 continue;
7488 }
7489 /* 8-byte counter */
7490 buf[i] = (((u64) *(hw_stats + offset)) << 32) +
7491 *(hw_stats + offset + 1) +
7492 (((u64) *(temp_stats + offset)) << 32) +
7493 *(temp_stats + offset + 1);
7494 }
7495 }
7496
7497 static int
7498 bnx2_phys_id(struct net_device *dev, u32 data)
7499 {
7500 struct bnx2 *bp = netdev_priv(dev);
7501 int i;
7502 u32 save;
7503
7504 bnx2_set_power_state(bp, PCI_D0);
7505
7506 if (data == 0)
7507 data = 2;
7508
7509 save = REG_RD(bp, BNX2_MISC_CFG);
7510 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7511
7512 for (i = 0; i < (data * 2); i++) {
7513 if ((i % 2) == 0) {
7514 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7515 }
7516 else {
7517 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7518 BNX2_EMAC_LED_1000MB_OVERRIDE |
7519 BNX2_EMAC_LED_100MB_OVERRIDE |
7520 BNX2_EMAC_LED_10MB_OVERRIDE |
7521 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7522 BNX2_EMAC_LED_TRAFFIC);
7523 }
7524 msleep_interruptible(500);
7525 if (signal_pending(current))
7526 break;
7527 }
7528 REG_WR(bp, BNX2_EMAC_LED, 0);
7529 REG_WR(bp, BNX2_MISC_CFG, save);
7530
7531 if (!netif_running(dev))
7532 bnx2_set_power_state(bp, PCI_D3hot);
7533
7534 return 0;
7535 }
7536
7537 static int
7538 bnx2_set_tx_csum(struct net_device *dev, u32 data)
7539 {
7540 struct bnx2 *bp = netdev_priv(dev);
7541
7542 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7543 return (ethtool_op_set_tx_ipv6_csum(dev, data));
7544 else
7545 return (ethtool_op_set_tx_csum(dev, data));
7546 }
7547
7548 static const struct ethtool_ops bnx2_ethtool_ops = {
7549 .get_settings = bnx2_get_settings,
7550 .set_settings = bnx2_set_settings,
7551 .get_drvinfo = bnx2_get_drvinfo,
7552 .get_regs_len = bnx2_get_regs_len,
7553 .get_regs = bnx2_get_regs,
7554 .get_wol = bnx2_get_wol,
7555 .set_wol = bnx2_set_wol,
7556 .nway_reset = bnx2_nway_reset,
7557 .get_link = bnx2_get_link,
7558 .get_eeprom_len = bnx2_get_eeprom_len,
7559 .get_eeprom = bnx2_get_eeprom,
7560 .set_eeprom = bnx2_set_eeprom,
7561 .get_coalesce = bnx2_get_coalesce,
7562 .set_coalesce = bnx2_set_coalesce,
7563 .get_ringparam = bnx2_get_ringparam,
7564 .set_ringparam = bnx2_set_ringparam,
7565 .get_pauseparam = bnx2_get_pauseparam,
7566 .set_pauseparam = bnx2_set_pauseparam,
7567 .get_rx_csum = bnx2_get_rx_csum,
7568 .set_rx_csum = bnx2_set_rx_csum,
7569 .set_tx_csum = bnx2_set_tx_csum,
7570 .set_sg = ethtool_op_set_sg,
7571 .set_tso = bnx2_set_tso,
7572 .self_test = bnx2_self_test,
7573 .get_strings = bnx2_get_strings,
7574 .phys_id = bnx2_phys_id,
7575 .get_ethtool_stats = bnx2_get_ethtool_stats,
7576 .get_sset_count = bnx2_get_sset_count,
7577 };
7578
7579 /* Called with rtnl_lock */
7580 static int
7581 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7582 {
7583 struct mii_ioctl_data *data = if_mii(ifr);
7584 struct bnx2 *bp = netdev_priv(dev);
7585 int err;
7586
7587 switch(cmd) {
7588 case SIOCGMIIPHY:
7589 data->phy_id = bp->phy_addr;
7590
7591 /* fallthru */
7592 case SIOCGMIIREG: {
7593 u32 mii_regval;
7594
7595 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7596 return -EOPNOTSUPP;
7597
7598 if (!netif_running(dev))
7599 return -EAGAIN;
7600
7601 spin_lock_bh(&bp->phy_lock);
7602 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
7603 spin_unlock_bh(&bp->phy_lock);
7604
7605 data->val_out = mii_regval;
7606
7607 return err;
7608 }
7609
7610 case SIOCSMIIREG:
7611 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7612 return -EOPNOTSUPP;
7613
7614 if (!netif_running(dev))
7615 return -EAGAIN;
7616
7617 spin_lock_bh(&bp->phy_lock);
7618 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
7619 spin_unlock_bh(&bp->phy_lock);
7620
7621 return err;
7622
7623 default:
7624 /* do nothing */
7625 break;
7626 }
7627 return -EOPNOTSUPP;
7628 }
7629
7630 /* Called with rtnl_lock */
7631 static int
7632 bnx2_change_mac_addr(struct net_device *dev, void *p)
7633 {
7634 struct sockaddr *addr = p;
7635 struct bnx2 *bp = netdev_priv(dev);
7636
7637 if (!is_valid_ether_addr(addr->sa_data))
7638 return -EINVAL;
7639
7640 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7641 if (netif_running(dev))
7642 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
7643
7644 return 0;
7645 }
7646
7647 /* Called with rtnl_lock */
7648 static int
7649 bnx2_change_mtu(struct net_device *dev, int new_mtu)
7650 {
7651 struct bnx2 *bp = netdev_priv(dev);
7652
7653 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7654 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7655 return -EINVAL;
7656
7657 dev->mtu = new_mtu;
7658 return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
7659 }
7660
7661 #ifdef CONFIG_NET_POLL_CONTROLLER
7662 static void
7663 poll_bnx2(struct net_device *dev)
7664 {
7665 struct bnx2 *bp = netdev_priv(dev);
7666 int i;
7667
7668 for (i = 0; i < bp->irq_nvecs; i++) {
7669 struct bnx2_irq *irq = &bp->irq_tbl[i];
7670
7671 disable_irq(irq->vector);
7672 irq->handler(irq->vector, &bp->bnx2_napi[i]);
7673 enable_irq(irq->vector);
7674 }
7675 }
7676 #endif
7677
7678 static void __devinit
7679 bnx2_get_5709_media(struct bnx2 *bp)
7680 {
7681 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7682 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7683 u32 strap;
7684
7685 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7686 return;
7687 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
7688 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7689 return;
7690 }
7691
7692 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7693 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7694 else
7695 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7696
7697 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7698 switch (strap) {
7699 case 0x4:
7700 case 0x5:
7701 case 0x6:
7702 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7703 return;
7704 }
7705 } else {
7706 switch (strap) {
7707 case 0x1:
7708 case 0x2:
7709 case 0x4:
7710 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7711 return;
7712 }
7713 }
7714 }
7715
7716 static void __devinit
7717 bnx2_get_pci_speed(struct bnx2 *bp)
7718 {
7719 u32 reg;
7720
7721 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7722 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7723 u32 clkreg;
7724
7725 bp->flags |= BNX2_FLAG_PCIX;
7726
7727 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7728
7729 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7730 switch (clkreg) {
7731 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7732 bp->bus_speed_mhz = 133;
7733 break;
7734
7735 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7736 bp->bus_speed_mhz = 100;
7737 break;
7738
7739 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7740 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7741 bp->bus_speed_mhz = 66;
7742 break;
7743
7744 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7745 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7746 bp->bus_speed_mhz = 50;
7747 break;
7748
7749 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7750 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7751 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7752 bp->bus_speed_mhz = 33;
7753 break;
7754 }
7755 }
7756 else {
7757 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7758 bp->bus_speed_mhz = 66;
7759 else
7760 bp->bus_speed_mhz = 33;
7761 }
7762
7763 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
7764 bp->flags |= BNX2_FLAG_PCI_32BIT;
7765
7766 }
7767
7768 static void __devinit
7769 bnx2_read_vpd_fw_ver(struct bnx2 *bp)
7770 {
7771 int rc, i, j;
7772 u8 *data;
7773 unsigned int block_end, rosize, len;
7774
7775 #define BNX2_VPD_NVRAM_OFFSET 0x300
7776 #define BNX2_VPD_LEN 128
7777 #define BNX2_MAX_VER_SLEN 30
7778
7779 data = kmalloc(256, GFP_KERNEL);
7780 if (!data)
7781 return;
7782
7783 rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data + BNX2_VPD_LEN,
7784 BNX2_VPD_LEN);
7785 if (rc)
7786 goto vpd_done;
7787
7788 for (i = 0; i < BNX2_VPD_LEN; i += 4) {
7789 data[i] = data[i + BNX2_VPD_LEN + 3];
7790 data[i + 1] = data[i + BNX2_VPD_LEN + 2];
7791 data[i + 2] = data[i + BNX2_VPD_LEN + 1];
7792 data[i + 3] = data[i + BNX2_VPD_LEN];
7793 }
7794
7795 i = pci_vpd_find_tag(data, 0, BNX2_VPD_LEN, PCI_VPD_LRDT_RO_DATA);
7796 if (i < 0)
7797 goto vpd_done;
7798
7799 rosize = pci_vpd_lrdt_size(&data[i]);
7800 i += PCI_VPD_LRDT_TAG_SIZE;
7801 block_end = i + rosize;
7802
7803 if (block_end > BNX2_VPD_LEN)
7804 goto vpd_done;
7805
7806 j = pci_vpd_find_info_keyword(data, i, rosize,
7807 PCI_VPD_RO_KEYWORD_MFR_ID);
7808 if (j < 0)
7809 goto vpd_done;
7810
7811 len = pci_vpd_info_field_size(&data[j]);
7812
7813 j += PCI_VPD_INFO_FLD_HDR_SIZE;
7814 if (j + len > block_end || len != 4 ||
7815 memcmp(&data[j], "1028", 4))
7816 goto vpd_done;
7817
7818 j = pci_vpd_find_info_keyword(data, i, rosize,
7819 PCI_VPD_RO_KEYWORD_VENDOR0);
7820 if (j < 0)
7821 goto vpd_done;
7822
7823 len = pci_vpd_info_field_size(&data[j]);
7824
7825 j += PCI_VPD_INFO_FLD_HDR_SIZE;
7826 if (j + len > block_end || len > BNX2_MAX_VER_SLEN)
7827 goto vpd_done;
7828
7829 memcpy(bp->fw_version, &data[j], len);
7830 bp->fw_version[len] = ' ';
7831
7832 vpd_done:
7833 kfree(data);
7834 }
7835
7836 static int __devinit
7837 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7838 {
7839 struct bnx2 *bp;
7840 unsigned long mem_len;
7841 int rc, i, j;
7842 u32 reg;
7843 u64 dma_mask, persist_dma_mask;
7844
7845 SET_NETDEV_DEV(dev, &pdev->dev);
7846 bp = netdev_priv(dev);
7847
7848 bp->flags = 0;
7849 bp->phy_flags = 0;
7850
7851 bp->temp_stats_blk =
7852 kzalloc(sizeof(struct statistics_block), GFP_KERNEL);
7853
7854 if (bp->temp_stats_blk == NULL) {
7855 rc = -ENOMEM;
7856 goto err_out;
7857 }
7858
7859 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7860 rc = pci_enable_device(pdev);
7861 if (rc) {
7862 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
7863 goto err_out;
7864 }
7865
7866 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7867 dev_err(&pdev->dev,
7868 "Cannot find PCI device base address, aborting\n");
7869 rc = -ENODEV;
7870 goto err_out_disable;
7871 }
7872
7873 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7874 if (rc) {
7875 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
7876 goto err_out_disable;
7877 }
7878
7879 pci_set_master(pdev);
7880 pci_save_state(pdev);
7881
7882 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7883 if (bp->pm_cap == 0) {
7884 dev_err(&pdev->dev,
7885 "Cannot find power management capability, aborting\n");
7886 rc = -EIO;
7887 goto err_out_release;
7888 }
7889
7890 bp->dev = dev;
7891 bp->pdev = pdev;
7892
7893 spin_lock_init(&bp->phy_lock);
7894 spin_lock_init(&bp->indirect_lock);
7895 #ifdef BCM_CNIC
7896 mutex_init(&bp->cnic_lock);
7897 #endif
7898 INIT_WORK(&bp->reset_task, bnx2_reset_task);
7899
7900 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
7901 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS + 1);
7902 dev->mem_end = dev->mem_start + mem_len;
7903 dev->irq = pdev->irq;
7904
7905 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7906
7907 if (!bp->regview) {
7908 dev_err(&pdev->dev, "Cannot map register space, aborting\n");
7909 rc = -ENOMEM;
7910 goto err_out_release;
7911 }
7912
7913 /* Configure byte swap and enable write to the reg_window registers.
7914 * Rely on CPU to do target byte swapping on big endian systems
7915 * The chip's target access swapping will not swap all accesses
7916 */
7917 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7918 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7919 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7920
7921 bnx2_set_power_state(bp, PCI_D0);
7922
7923 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7924
7925 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7926 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7927 dev_err(&pdev->dev,
7928 "Cannot find PCIE capability, aborting\n");
7929 rc = -EIO;
7930 goto err_out_unmap;
7931 }
7932 bp->flags |= BNX2_FLAG_PCIE;
7933 if (CHIP_REV(bp) == CHIP_REV_Ax)
7934 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
7935 } else {
7936 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7937 if (bp->pcix_cap == 0) {
7938 dev_err(&pdev->dev,
7939 "Cannot find PCIX capability, aborting\n");
7940 rc = -EIO;
7941 goto err_out_unmap;
7942 }
7943 bp->flags |= BNX2_FLAG_BROKEN_STATS;
7944 }
7945
7946 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7947 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
7948 bp->flags |= BNX2_FLAG_MSIX_CAP;
7949 }
7950
7951 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7952 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
7953 bp->flags |= BNX2_FLAG_MSI_CAP;
7954 }
7955
7956 /* 5708 cannot support DMA addresses > 40-bit. */
7957 if (CHIP_NUM(bp) == CHIP_NUM_5708)
7958 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
7959 else
7960 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
7961
7962 /* Configure DMA attributes. */
7963 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7964 dev->features |= NETIF_F_HIGHDMA;
7965 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7966 if (rc) {
7967 dev_err(&pdev->dev,
7968 "pci_set_consistent_dma_mask failed, aborting\n");
7969 goto err_out_unmap;
7970 }
7971 } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
7972 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
7973 goto err_out_unmap;
7974 }
7975
7976 if (!(bp->flags & BNX2_FLAG_PCIE))
7977 bnx2_get_pci_speed(bp);
7978
7979 /* 5706A0 may falsely detect SERR and PERR. */
7980 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7981 reg = REG_RD(bp, PCI_COMMAND);
7982 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7983 REG_WR(bp, PCI_COMMAND, reg);
7984 }
7985 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
7986 !(bp->flags & BNX2_FLAG_PCIX)) {
7987
7988 dev_err(&pdev->dev,
7989 "5706 A1 can only be used in a PCIX bus, aborting\n");
7990 goto err_out_unmap;
7991 }
7992
7993 bnx2_init_nvram(bp);
7994
7995 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
7996
7997 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
7998 BNX2_SHM_HDR_SIGNATURE_SIG) {
7999 u32 off = PCI_FUNC(pdev->devfn) << 2;
8000
8001 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
8002 } else
8003 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
8004
8005 /* Get the permanent MAC address. First we need to make sure the
8006 * firmware is actually running.
8007 */
8008 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
8009
8010 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
8011 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
8012 dev_err(&pdev->dev, "Firmware not running, aborting\n");
8013 rc = -ENODEV;
8014 goto err_out_unmap;
8015 }
8016
8017 bnx2_read_vpd_fw_ver(bp);
8018
8019 j = strlen(bp->fw_version);
8020 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
8021 for (i = 0; i < 3 && j < 24; i++) {
8022 u8 num, k, skip0;
8023
8024 if (i == 0) {
8025 bp->fw_version[j++] = 'b';
8026 bp->fw_version[j++] = 'c';
8027 bp->fw_version[j++] = ' ';
8028 }
8029 num = (u8) (reg >> (24 - (i * 8)));
8030 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
8031 if (num >= k || !skip0 || k == 1) {
8032 bp->fw_version[j++] = (num / k) + '0';
8033 skip0 = 0;
8034 }
8035 }
8036 if (i != 2)
8037 bp->fw_version[j++] = '.';
8038 }
8039 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
8040 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
8041 bp->wol = 1;
8042
8043 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
8044 bp->flags |= BNX2_FLAG_ASF_ENABLE;
8045
8046 for (i = 0; i < 30; i++) {
8047 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
8048 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
8049 break;
8050 msleep(10);
8051 }
8052 }
8053 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
8054 reg &= BNX2_CONDITION_MFW_RUN_MASK;
8055 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
8056 reg != BNX2_CONDITION_MFW_RUN_NONE) {
8057 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
8058
8059 if (j < 32)
8060 bp->fw_version[j++] = ' ';
8061 for (i = 0; i < 3 && j < 28; i++) {
8062 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
8063 reg = swab32(reg);
8064 memcpy(&bp->fw_version[j], &reg, 4);
8065 j += 4;
8066 }
8067 }
8068
8069 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
8070 bp->mac_addr[0] = (u8) (reg >> 8);
8071 bp->mac_addr[1] = (u8) reg;
8072
8073 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
8074 bp->mac_addr[2] = (u8) (reg >> 24);
8075 bp->mac_addr[3] = (u8) (reg >> 16);
8076 bp->mac_addr[4] = (u8) (reg >> 8);
8077 bp->mac_addr[5] = (u8) reg;
8078
8079 bp->tx_ring_size = MAX_TX_DESC_CNT;
8080 bnx2_set_rx_ring_size(bp, 255);
8081
8082 bp->rx_csum = 1;
8083
8084 bp->tx_quick_cons_trip_int = 2;
8085 bp->tx_quick_cons_trip = 20;
8086 bp->tx_ticks_int = 18;
8087 bp->tx_ticks = 80;
8088
8089 bp->rx_quick_cons_trip_int = 2;
8090 bp->rx_quick_cons_trip = 12;
8091 bp->rx_ticks_int = 18;
8092 bp->rx_ticks = 18;
8093
8094 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
8095
8096 bp->current_interval = BNX2_TIMER_INTERVAL;
8097
8098 bp->phy_addr = 1;
8099
8100 /* Disable WOL support if we are running on a SERDES chip. */
8101 if (CHIP_NUM(bp) == CHIP_NUM_5709)
8102 bnx2_get_5709_media(bp);
8103 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
8104 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
8105
8106 bp->phy_port = PORT_TP;
8107 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
8108 bp->phy_port = PORT_FIBRE;
8109 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
8110 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
8111 bp->flags |= BNX2_FLAG_NO_WOL;
8112 bp->wol = 0;
8113 }
8114 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
8115 /* Don't do parallel detect on this board because of
8116 * some board problems. The link will not go down
8117 * if we do parallel detect.
8118 */
8119 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
8120 pdev->subsystem_device == 0x310c)
8121 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
8122 } else {
8123 bp->phy_addr = 2;
8124 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
8125 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
8126 }
8127 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
8128 CHIP_NUM(bp) == CHIP_NUM_5708)
8129 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
8130 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
8131 (CHIP_REV(bp) == CHIP_REV_Ax ||
8132 CHIP_REV(bp) == CHIP_REV_Bx))
8133 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
8134
8135 bnx2_init_fw_cap(bp);
8136
8137 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
8138 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
8139 (CHIP_ID(bp) == CHIP_ID_5708_B1) ||
8140 !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
8141 bp->flags |= BNX2_FLAG_NO_WOL;
8142 bp->wol = 0;
8143 }
8144
8145 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
8146 bp->tx_quick_cons_trip_int =
8147 bp->tx_quick_cons_trip;
8148 bp->tx_ticks_int = bp->tx_ticks;
8149 bp->rx_quick_cons_trip_int =
8150 bp->rx_quick_cons_trip;
8151 bp->rx_ticks_int = bp->rx_ticks;
8152 bp->comp_prod_trip_int = bp->comp_prod_trip;
8153 bp->com_ticks_int = bp->com_ticks;
8154 bp->cmd_ticks_int = bp->cmd_ticks;
8155 }
8156
8157 /* Disable MSI on 5706 if AMD 8132 bridge is found.
8158 *
8159 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
8160 * with byte enables disabled on the unused 32-bit word. This is legal
8161 * but causes problems on the AMD 8132 which will eventually stop
8162 * responding after a while.
8163 *
8164 * AMD believes this incompatibility is unique to the 5706, and
8165 * prefers to locally disable MSI rather than globally disabling it.
8166 */
8167 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
8168 struct pci_dev *amd_8132 = NULL;
8169
8170 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
8171 PCI_DEVICE_ID_AMD_8132_BRIDGE,
8172 amd_8132))) {
8173
8174 if (amd_8132->revision >= 0x10 &&
8175 amd_8132->revision <= 0x13) {
8176 disable_msi = 1;
8177 pci_dev_put(amd_8132);
8178 break;
8179 }
8180 }
8181 }
8182
8183 bnx2_set_default_link(bp);
8184 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
8185
8186 init_timer(&bp->timer);
8187 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
8188 bp->timer.data = (unsigned long) bp;
8189 bp->timer.function = bnx2_timer;
8190
8191 return 0;
8192
8193 err_out_unmap:
8194 if (bp->regview) {
8195 iounmap(bp->regview);
8196 bp->regview = NULL;
8197 }
8198
8199 err_out_release:
8200 pci_release_regions(pdev);
8201
8202 err_out_disable:
8203 pci_disable_device(pdev);
8204 pci_set_drvdata(pdev, NULL);
8205
8206 err_out:
8207 return rc;
8208 }
8209
8210 static char * __devinit
8211 bnx2_bus_string(struct bnx2 *bp, char *str)
8212 {
8213 char *s = str;
8214
8215 if (bp->flags & BNX2_FLAG_PCIE) {
8216 s += sprintf(s, "PCI Express");
8217 } else {
8218 s += sprintf(s, "PCI");
8219 if (bp->flags & BNX2_FLAG_PCIX)
8220 s += sprintf(s, "-X");
8221 if (bp->flags & BNX2_FLAG_PCI_32BIT)
8222 s += sprintf(s, " 32-bit");
8223 else
8224 s += sprintf(s, " 64-bit");
8225 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
8226 }
8227 return str;
8228 }
8229
8230 static void __devinit
8231 bnx2_init_napi(struct bnx2 *bp)
8232 {
8233 int i;
8234
8235 for (i = 0; i < bp->irq_nvecs; i++) {
8236 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
8237 int (*poll)(struct napi_struct *, int);
8238
8239 if (i == 0)
8240 poll = bnx2_poll;
8241 else
8242 poll = bnx2_poll_msix;
8243
8244 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
8245 bnapi->bp = bp;
8246 }
8247 }
8248
8249 static const struct net_device_ops bnx2_netdev_ops = {
8250 .ndo_open = bnx2_open,
8251 .ndo_start_xmit = bnx2_start_xmit,
8252 .ndo_stop = bnx2_close,
8253 .ndo_get_stats = bnx2_get_stats,
8254 .ndo_set_rx_mode = bnx2_set_rx_mode,
8255 .ndo_do_ioctl = bnx2_ioctl,
8256 .ndo_validate_addr = eth_validate_addr,
8257 .ndo_set_mac_address = bnx2_change_mac_addr,
8258 .ndo_change_mtu = bnx2_change_mtu,
8259 .ndo_tx_timeout = bnx2_tx_timeout,
8260 #ifdef BCM_VLAN
8261 .ndo_vlan_rx_register = bnx2_vlan_rx_register,
8262 #endif
8263 #ifdef CONFIG_NET_POLL_CONTROLLER
8264 .ndo_poll_controller = poll_bnx2,
8265 #endif
8266 };
8267
8268 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
8269 {
8270 #ifdef BCM_VLAN
8271 dev->vlan_features |= flags;
8272 #endif
8273 }
8274
8275 static int __devinit
8276 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8277 {
8278 static int version_printed = 0;
8279 struct net_device *dev = NULL;
8280 struct bnx2 *bp;
8281 int rc;
8282 char str[40];
8283
8284 if (version_printed++ == 0)
8285 pr_info("%s", version);
8286
8287 /* dev zeroed in init_etherdev */
8288 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
8289
8290 if (!dev)
8291 return -ENOMEM;
8292
8293 rc = bnx2_init_board(pdev, dev);
8294 if (rc < 0) {
8295 free_netdev(dev);
8296 return rc;
8297 }
8298
8299 dev->netdev_ops = &bnx2_netdev_ops;
8300 dev->watchdog_timeo = TX_TIMEOUT;
8301 dev->ethtool_ops = &bnx2_ethtool_ops;
8302
8303 bp = netdev_priv(dev);
8304
8305 pci_set_drvdata(pdev, dev);
8306
8307 rc = bnx2_request_firmware(bp);
8308 if (rc)
8309 goto error;
8310
8311 memcpy(dev->dev_addr, bp->mac_addr, 6);
8312 memcpy(dev->perm_addr, bp->mac_addr, 6);
8313
8314 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
8315 vlan_features_add(dev, NETIF_F_IP_CSUM | NETIF_F_SG);
8316 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
8317 dev->features |= NETIF_F_IPV6_CSUM;
8318 vlan_features_add(dev, NETIF_F_IPV6_CSUM);
8319 }
8320 #ifdef BCM_VLAN
8321 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8322 #endif
8323 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
8324 vlan_features_add(dev, NETIF_F_TSO | NETIF_F_TSO_ECN);
8325 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
8326 dev->features |= NETIF_F_TSO6;
8327 vlan_features_add(dev, NETIF_F_TSO6);
8328 }
8329 if ((rc = register_netdev(dev))) {
8330 dev_err(&pdev->dev, "Cannot register net device\n");
8331 goto error;
8332 }
8333
8334 netdev_info(dev, "%s (%c%d) %s found at mem %lx, IRQ %d, node addr %pM\n",
8335 board_info[ent->driver_data].name,
8336 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
8337 ((CHIP_ID(bp) & 0x0ff0) >> 4),
8338 bnx2_bus_string(bp, str),
8339 dev->base_addr,
8340 bp->pdev->irq, dev->dev_addr);
8341
8342 return 0;
8343
8344 error:
8345 if (bp->mips_firmware)
8346 release_firmware(bp->mips_firmware);
8347 if (bp->rv2p_firmware)
8348 release_firmware(bp->rv2p_firmware);
8349
8350 if (bp->regview)
8351 iounmap(bp->regview);
8352 pci_release_regions(pdev);
8353 pci_disable_device(pdev);
8354 pci_set_drvdata(pdev, NULL);
8355 free_netdev(dev);
8356 return rc;
8357 }
8358
8359 static void __devexit
8360 bnx2_remove_one(struct pci_dev *pdev)
8361 {
8362 struct net_device *dev = pci_get_drvdata(pdev);
8363 struct bnx2 *bp = netdev_priv(dev);
8364
8365 flush_scheduled_work();
8366
8367 unregister_netdev(dev);
8368
8369 if (bp->mips_firmware)
8370 release_firmware(bp->mips_firmware);
8371 if (bp->rv2p_firmware)
8372 release_firmware(bp->rv2p_firmware);
8373
8374 if (bp->regview)
8375 iounmap(bp->regview);
8376
8377 kfree(bp->temp_stats_blk);
8378
8379 free_netdev(dev);
8380 pci_release_regions(pdev);
8381 pci_disable_device(pdev);
8382 pci_set_drvdata(pdev, NULL);
8383 }
8384
8385 static int
8386 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
8387 {
8388 struct net_device *dev = pci_get_drvdata(pdev);
8389 struct bnx2 *bp = netdev_priv(dev);
8390
8391 /* PCI register 4 needs to be saved whether netif_running() or not.
8392 * MSI address and data need to be saved if using MSI and
8393 * netif_running().
8394 */
8395 pci_save_state(pdev);
8396 if (!netif_running(dev))
8397 return 0;
8398
8399 flush_scheduled_work();
8400 bnx2_netif_stop(bp, true);
8401 netif_device_detach(dev);
8402 del_timer_sync(&bp->timer);
8403 bnx2_shutdown_chip(bp);
8404 bnx2_free_skbs(bp);
8405 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
8406 return 0;
8407 }
8408
8409 static int
8410 bnx2_resume(struct pci_dev *pdev)
8411 {
8412 struct net_device *dev = pci_get_drvdata(pdev);
8413 struct bnx2 *bp = netdev_priv(dev);
8414
8415 pci_restore_state(pdev);
8416 if (!netif_running(dev))
8417 return 0;
8418
8419 bnx2_set_power_state(bp, PCI_D0);
8420 netif_device_attach(dev);
8421 bnx2_init_nic(bp, 1);
8422 bnx2_netif_start(bp, true);
8423 return 0;
8424 }
8425
8426 /**
8427 * bnx2_io_error_detected - called when PCI error is detected
8428 * @pdev: Pointer to PCI device
8429 * @state: The current pci connection state
8430 *
8431 * This function is called after a PCI bus error affecting
8432 * this device has been detected.
8433 */
8434 static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
8435 pci_channel_state_t state)
8436 {
8437 struct net_device *dev = pci_get_drvdata(pdev);
8438 struct bnx2 *bp = netdev_priv(dev);
8439
8440 rtnl_lock();
8441 netif_device_detach(dev);
8442
8443 if (state == pci_channel_io_perm_failure) {
8444 rtnl_unlock();
8445 return PCI_ERS_RESULT_DISCONNECT;
8446 }
8447
8448 if (netif_running(dev)) {
8449 bnx2_netif_stop(bp, true);
8450 del_timer_sync(&bp->timer);
8451 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
8452 }
8453
8454 pci_disable_device(pdev);
8455 rtnl_unlock();
8456
8457 /* Request a slot slot reset. */
8458 return PCI_ERS_RESULT_NEED_RESET;
8459 }
8460
8461 /**
8462 * bnx2_io_slot_reset - called after the pci bus has been reset.
8463 * @pdev: Pointer to PCI device
8464 *
8465 * Restart the card from scratch, as if from a cold-boot.
8466 */
8467 static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
8468 {
8469 struct net_device *dev = pci_get_drvdata(pdev);
8470 struct bnx2 *bp = netdev_priv(dev);
8471
8472 rtnl_lock();
8473 if (pci_enable_device(pdev)) {
8474 dev_err(&pdev->dev,
8475 "Cannot re-enable PCI device after reset\n");
8476 rtnl_unlock();
8477 return PCI_ERS_RESULT_DISCONNECT;
8478 }
8479 pci_set_master(pdev);
8480 pci_restore_state(pdev);
8481 pci_save_state(pdev);
8482
8483 if (netif_running(dev)) {
8484 bnx2_set_power_state(bp, PCI_D0);
8485 bnx2_init_nic(bp, 1);
8486 }
8487
8488 rtnl_unlock();
8489 return PCI_ERS_RESULT_RECOVERED;
8490 }
8491
8492 /**
8493 * bnx2_io_resume - called when traffic can start flowing again.
8494 * @pdev: Pointer to PCI device
8495 *
8496 * This callback is called when the error recovery driver tells us that
8497 * its OK to resume normal operation.
8498 */
8499 static void bnx2_io_resume(struct pci_dev *pdev)
8500 {
8501 struct net_device *dev = pci_get_drvdata(pdev);
8502 struct bnx2 *bp = netdev_priv(dev);
8503
8504 rtnl_lock();
8505 if (netif_running(dev))
8506 bnx2_netif_start(bp, true);
8507
8508 netif_device_attach(dev);
8509 rtnl_unlock();
8510 }
8511
8512 static struct pci_error_handlers bnx2_err_handler = {
8513 .error_detected = bnx2_io_error_detected,
8514 .slot_reset = bnx2_io_slot_reset,
8515 .resume = bnx2_io_resume,
8516 };
8517
8518 static struct pci_driver bnx2_pci_driver = {
8519 .name = DRV_MODULE_NAME,
8520 .id_table = bnx2_pci_tbl,
8521 .probe = bnx2_init_one,
8522 .remove = __devexit_p(bnx2_remove_one),
8523 .suspend = bnx2_suspend,
8524 .resume = bnx2_resume,
8525 .err_handler = &bnx2_err_handler,
8526 };
8527
8528 static int __init bnx2_init(void)
8529 {
8530 return pci_register_driver(&bnx2_pci_driver);
8531 }
8532
8533 static void __exit bnx2_cleanup(void)
8534 {
8535 pci_unregister_driver(&bnx2_pci_driver);
8536 }
8537
8538 module_init(bnx2_init);
8539 module_exit(bnx2_cleanup);
8540
8541
8542
AMDTP streaming driver for the Linux FireWire stack (Juju)