2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 * Copyright (C) 2010 ST-Ericsson AB.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/device.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/err.h>
19 #include <linux/highmem.h>
20 #include <linux/log2.h>
21 #include <linux/mmc/host.h>
22 #include <linux/amba/bus.h>
23 #include <linux/clk.h>
24 #include <linux/scatterlist.h>
25 #include <linux/gpio.h>
26 #include <linux/amba/mmci.h>
27 #include <linux/regulator/consumer.h>
29 #include <asm/div64.h>
31 #include <asm/sizes.h>
35 #define DRIVER_NAME "mmci-pl18x"
37 static unsigned int fmax
= 515633;
40 * struct variant_data - MMCI variant-specific quirks
41 * @clkreg: default value for MCICLOCK register
42 * @clkreg_enable: enable value for MMCICLOCK register
43 * @datalength_bits: number of bits in the MMCIDATALENGTH register
44 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
45 * is asserted (likewise for RX)
46 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
47 * is asserted (likewise for RX)
51 unsigned int clkreg_enable
;
52 unsigned int datalength_bits
;
53 unsigned int fifosize
;
54 unsigned int fifohalfsize
;
57 static struct variant_data variant_arm
= {
59 .fifohalfsize
= 8 * 4,
60 .datalength_bits
= 16,
63 static struct variant_data variant_u300
= {
65 .fifohalfsize
= 8 * 4,
66 .clkreg_enable
= 1 << 13, /* HWFCEN */
67 .datalength_bits
= 16,
70 static struct variant_data variant_ux500
= {
72 .fifohalfsize
= 8 * 4,
73 .clkreg
= MCI_CLK_ENABLE
,
74 .clkreg_enable
= 1 << 14, /* HWFCEN */
75 .datalength_bits
= 24,
78 * This must be called with host->lock held
80 static void mmci_set_clkreg(struct mmci_host
*host
, unsigned int desired
)
82 struct variant_data
*variant
= host
->variant
;
83 u32 clk
= variant
->clkreg
;
86 if (desired
>= host
->mclk
) {
88 host
->cclk
= host
->mclk
;
90 clk
= host
->mclk
/ (2 * desired
) - 1;
93 host
->cclk
= host
->mclk
/ (2 * (clk
+ 1));
96 clk
|= variant
->clkreg_enable
;
97 clk
|= MCI_CLK_ENABLE
;
98 /* This hasn't proven to be worthwhile */
99 /* clk |= MCI_CLK_PWRSAVE; */
102 if (host
->mmc
->ios
.bus_width
== MMC_BUS_WIDTH_4
)
104 if (host
->mmc
->ios
.bus_width
== MMC_BUS_WIDTH_8
)
105 clk
|= MCI_ST_8BIT_BUS
;
107 writel(clk
, host
->base
+ MMCICLOCK
);
111 mmci_request_end(struct mmci_host
*host
, struct mmc_request
*mrq
)
113 writel(0, host
->base
+ MMCICOMMAND
);
121 mrq
->data
->bytes_xfered
= host
->data_xfered
;
124 * Need to drop the host lock here; mmc_request_done may call
125 * back into the driver...
127 spin_unlock(&host
->lock
);
128 mmc_request_done(host
->mmc
, mrq
);
129 spin_lock(&host
->lock
);
132 static void mmci_stop_data(struct mmci_host
*host
)
134 writel(0, host
->base
+ MMCIDATACTRL
);
135 writel(0, host
->base
+ MMCIMASK1
);
139 static void mmci_init_sg(struct mmci_host
*host
, struct mmc_data
*data
)
141 unsigned int flags
= SG_MITER_ATOMIC
;
143 if (data
->flags
& MMC_DATA_READ
)
144 flags
|= SG_MITER_TO_SG
;
146 flags
|= SG_MITER_FROM_SG
;
148 sg_miter_start(&host
->sg_miter
, data
->sg
, data
->sg_len
, flags
);
151 static void mmci_start_data(struct mmci_host
*host
, struct mmc_data
*data
)
153 struct variant_data
*variant
= host
->variant
;
154 unsigned int datactrl
, timeout
, irqmask
;
155 unsigned long long clks
;
159 dev_dbg(mmc_dev(host
->mmc
), "blksz %04x blks %04x flags %08x\n",
160 data
->blksz
, data
->blocks
, data
->flags
);
163 host
->size
= data
->blksz
* data
->blocks
;
164 host
->data_xfered
= 0;
166 mmci_init_sg(host
, data
);
168 clks
= (unsigned long long)data
->timeout_ns
* host
->cclk
;
169 do_div(clks
, 1000000000UL);
171 timeout
= data
->timeout_clks
+ (unsigned int)clks
;
174 writel(timeout
, base
+ MMCIDATATIMER
);
175 writel(host
->size
, base
+ MMCIDATALENGTH
);
177 blksz_bits
= ffs(data
->blksz
) - 1;
178 BUG_ON(1 << blksz_bits
!= data
->blksz
);
180 datactrl
= MCI_DPSM_ENABLE
| blksz_bits
<< 4;
181 if (data
->flags
& MMC_DATA_READ
) {
182 datactrl
|= MCI_DPSM_DIRECTION
;
183 irqmask
= MCI_RXFIFOHALFFULLMASK
;
186 * If we have less than a FIFOSIZE of bytes to transfer,
187 * trigger a PIO interrupt as soon as any data is available.
189 if (host
->size
< variant
->fifosize
)
190 irqmask
|= MCI_RXDATAAVLBLMASK
;
193 * We don't actually need to include "FIFO empty" here
194 * since its implicit in "FIFO half empty".
196 irqmask
= MCI_TXFIFOHALFEMPTYMASK
;
199 writel(datactrl
, base
+ MMCIDATACTRL
);
200 writel(readl(base
+ MMCIMASK0
) & ~MCI_DATAENDMASK
, base
+ MMCIMASK0
);
201 writel(irqmask
, base
+ MMCIMASK1
);
205 mmci_start_command(struct mmci_host
*host
, struct mmc_command
*cmd
, u32 c
)
207 void __iomem
*base
= host
->base
;
209 dev_dbg(mmc_dev(host
->mmc
), "op %02x arg %08x flags %08x\n",
210 cmd
->opcode
, cmd
->arg
, cmd
->flags
);
212 if (readl(base
+ MMCICOMMAND
) & MCI_CPSM_ENABLE
) {
213 writel(0, base
+ MMCICOMMAND
);
217 c
|= cmd
->opcode
| MCI_CPSM_ENABLE
;
218 if (cmd
->flags
& MMC_RSP_PRESENT
) {
219 if (cmd
->flags
& MMC_RSP_136
)
220 c
|= MCI_CPSM_LONGRSP
;
221 c
|= MCI_CPSM_RESPONSE
;
224 c
|= MCI_CPSM_INTERRUPT
;
228 writel(cmd
->arg
, base
+ MMCIARGUMENT
);
229 writel(c
, base
+ MMCICOMMAND
);
233 mmci_data_irq(struct mmci_host
*host
, struct mmc_data
*data
,
236 if (status
& MCI_DATABLOCKEND
) {
237 host
->data_xfered
+= data
->blksz
;
238 #ifdef CONFIG_ARCH_U300
240 * On the U300 some signal or other is
241 * badly routed so that a data write does
242 * not properly terminate with a MCI_DATAEND
243 * status flag. This quirk will make writes
246 if (data
->flags
& MMC_DATA_WRITE
)
247 status
|= MCI_DATAEND
;
250 if (status
& (MCI_DATACRCFAIL
|MCI_DATATIMEOUT
|MCI_TXUNDERRUN
|MCI_RXOVERRUN
)) {
251 dev_dbg(mmc_dev(host
->mmc
), "MCI ERROR IRQ (status %08x)\n", status
);
252 if (status
& MCI_DATACRCFAIL
)
253 data
->error
= -EILSEQ
;
254 else if (status
& MCI_DATATIMEOUT
)
255 data
->error
= -ETIMEDOUT
;
256 else if (status
& (MCI_TXUNDERRUN
|MCI_RXOVERRUN
))
258 status
|= MCI_DATAEND
;
261 * We hit an error condition. Ensure that any data
262 * partially written to a page is properly coherent.
264 if (data
->flags
& MMC_DATA_READ
) {
265 struct sg_mapping_iter
*sg_miter
= &host
->sg_miter
;
268 local_irq_save(flags
);
269 if (sg_miter_next(sg_miter
)) {
270 flush_dcache_page(sg_miter
->page
);
271 sg_miter_stop(sg_miter
);
273 local_irq_restore(flags
);
276 if (status
& MCI_DATAEND
) {
277 mmci_stop_data(host
);
280 mmci_request_end(host
, data
->mrq
);
282 mmci_start_command(host
, data
->stop
, 0);
288 mmci_cmd_irq(struct mmci_host
*host
, struct mmc_command
*cmd
,
291 void __iomem
*base
= host
->base
;
295 cmd
->resp
[0] = readl(base
+ MMCIRESPONSE0
);
296 cmd
->resp
[1] = readl(base
+ MMCIRESPONSE1
);
297 cmd
->resp
[2] = readl(base
+ MMCIRESPONSE2
);
298 cmd
->resp
[3] = readl(base
+ MMCIRESPONSE3
);
300 if (status
& MCI_CMDTIMEOUT
) {
301 cmd
->error
= -ETIMEDOUT
;
302 } else if (status
& MCI_CMDCRCFAIL
&& cmd
->flags
& MMC_RSP_CRC
) {
303 cmd
->error
= -EILSEQ
;
306 if (!cmd
->data
|| cmd
->error
) {
308 mmci_stop_data(host
);
309 mmci_request_end(host
, cmd
->mrq
);
310 } else if (!(cmd
->data
->flags
& MMC_DATA_READ
)) {
311 mmci_start_data(host
, cmd
->data
);
315 static int mmci_pio_read(struct mmci_host
*host
, char *buffer
, unsigned int remain
)
317 void __iomem
*base
= host
->base
;
320 int host_remain
= host
->size
;
323 int count
= host_remain
- (readl(base
+ MMCIFIFOCNT
) << 2);
331 readsl(base
+ MMCIFIFO
, ptr
, count
>> 2);
335 host_remain
-= count
;
340 status
= readl(base
+ MMCISTATUS
);
341 } while (status
& MCI_RXDATAAVLBL
);
346 static int mmci_pio_write(struct mmci_host
*host
, char *buffer
, unsigned int remain
, u32 status
)
348 struct variant_data
*variant
= host
->variant
;
349 void __iomem
*base
= host
->base
;
353 unsigned int count
, maxcnt
;
355 maxcnt
= status
& MCI_TXFIFOEMPTY
?
356 variant
->fifosize
: variant
->fifohalfsize
;
357 count
= min(remain
, maxcnt
);
359 writesl(base
+ MMCIFIFO
, ptr
, count
>> 2);
367 status
= readl(base
+ MMCISTATUS
);
368 } while (status
& MCI_TXFIFOHALFEMPTY
);
374 * PIO data transfer IRQ handler.
376 static irqreturn_t
mmci_pio_irq(int irq
, void *dev_id
)
378 struct mmci_host
*host
= dev_id
;
379 struct sg_mapping_iter
*sg_miter
= &host
->sg_miter
;
380 struct variant_data
*variant
= host
->variant
;
381 void __iomem
*base
= host
->base
;
385 status
= readl(base
+ MMCISTATUS
);
387 dev_dbg(mmc_dev(host
->mmc
), "irq1 (pio) %08x\n", status
);
389 local_irq_save(flags
);
392 unsigned int remain
, len
;
396 * For write, we only need to test the half-empty flag
397 * here - if the FIFO is completely empty, then by
398 * definition it is more than half empty.
400 * For read, check for data available.
402 if (!(status
& (MCI_TXFIFOHALFEMPTY
|MCI_RXDATAAVLBL
)))
405 if (!sg_miter_next(sg_miter
))
408 buffer
= sg_miter
->addr
;
409 remain
= sg_miter
->length
;
412 if (status
& MCI_RXACTIVE
)
413 len
= mmci_pio_read(host
, buffer
, remain
);
414 if (status
& MCI_TXACTIVE
)
415 len
= mmci_pio_write(host
, buffer
, remain
, status
);
417 sg_miter
->consumed
= len
;
425 if (status
& MCI_RXACTIVE
)
426 flush_dcache_page(sg_miter
->page
);
428 status
= readl(base
+ MMCISTATUS
);
431 sg_miter_stop(sg_miter
);
433 local_irq_restore(flags
);
436 * If we're nearing the end of the read, switch to
437 * "any data available" mode.
439 if (status
& MCI_RXACTIVE
&& host
->size
< variant
->fifosize
)
440 writel(MCI_RXDATAAVLBLMASK
, base
+ MMCIMASK1
);
443 * If we run out of data, disable the data IRQs; this
444 * prevents a race where the FIFO becomes empty before
445 * the chip itself has disabled the data path, and
446 * stops us racing with our data end IRQ.
448 if (host
->size
== 0) {
449 writel(0, base
+ MMCIMASK1
);
450 writel(readl(base
+ MMCIMASK0
) | MCI_DATAENDMASK
, base
+ MMCIMASK0
);
457 * Handle completion of command and data transfers.
459 static irqreturn_t
mmci_irq(int irq
, void *dev_id
)
461 struct mmci_host
*host
= dev_id
;
465 spin_lock(&host
->lock
);
468 struct mmc_command
*cmd
;
469 struct mmc_data
*data
;
471 status
= readl(host
->base
+ MMCISTATUS
);
472 status
&= readl(host
->base
+ MMCIMASK0
);
473 writel(status
, host
->base
+ MMCICLEAR
);
475 dev_dbg(mmc_dev(host
->mmc
), "irq0 (data+cmd) %08x\n", status
);
478 if (status
& (MCI_DATACRCFAIL
|MCI_DATATIMEOUT
|MCI_TXUNDERRUN
|
479 MCI_RXOVERRUN
|MCI_DATAEND
|MCI_DATABLOCKEND
) && data
)
480 mmci_data_irq(host
, data
, status
);
483 if (status
& (MCI_CMDCRCFAIL
|MCI_CMDTIMEOUT
|MCI_CMDSENT
|MCI_CMDRESPEND
) && cmd
)
484 mmci_cmd_irq(host
, cmd
, status
);
489 spin_unlock(&host
->lock
);
491 return IRQ_RETVAL(ret
);
494 static void mmci_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
496 struct mmci_host
*host
= mmc_priv(mmc
);
499 WARN_ON(host
->mrq
!= NULL
);
501 if (mrq
->data
&& !is_power_of_2(mrq
->data
->blksz
)) {
502 dev_err(mmc_dev(mmc
), "unsupported block size (%d bytes)\n",
504 mrq
->cmd
->error
= -EINVAL
;
505 mmc_request_done(mmc
, mrq
);
509 spin_lock_irqsave(&host
->lock
, flags
);
513 if (mrq
->data
&& mrq
->data
->flags
& MMC_DATA_READ
)
514 mmci_start_data(host
, mrq
->data
);
516 mmci_start_command(host
, mrq
->cmd
, 0);
518 spin_unlock_irqrestore(&host
->lock
, flags
);
521 static void mmci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
523 struct mmci_host
*host
= mmc_priv(mmc
);
528 switch (ios
->power_mode
) {
531 ret
= mmc_regulator_set_ocr(mmc
, host
->vcc
, 0);
535 ret
= mmc_regulator_set_ocr(mmc
, host
->vcc
, ios
->vdd
);
537 dev_err(mmc_dev(mmc
), "unable to set OCR\n");
539 * The .set_ios() function in the mmc_host_ops
540 * struct return void, and failing to set the
541 * power should be rare so we print an error
547 if (host
->plat
->vdd_handler
)
548 pwr
|= host
->plat
->vdd_handler(mmc_dev(mmc
), ios
->vdd
,
550 /* The ST version does not have this, fall through to POWER_ON */
551 if (host
->hw_designer
!= AMBA_VENDOR_ST
) {
560 if (ios
->bus_mode
== MMC_BUSMODE_OPENDRAIN
) {
561 if (host
->hw_designer
!= AMBA_VENDOR_ST
)
565 * The ST Micro variant use the ROD bit for something
566 * else and only has OD (Open Drain).
572 spin_lock_irqsave(&host
->lock
, flags
);
574 mmci_set_clkreg(host
, ios
->clock
);
576 if (host
->pwr
!= pwr
) {
578 writel(pwr
, host
->base
+ MMCIPOWER
);
581 spin_unlock_irqrestore(&host
->lock
, flags
);
584 static int mmci_get_ro(struct mmc_host
*mmc
)
586 struct mmci_host
*host
= mmc_priv(mmc
);
588 if (host
->gpio_wp
== -ENOSYS
)
591 return gpio_get_value_cansleep(host
->gpio_wp
);
594 static int mmci_get_cd(struct mmc_host
*mmc
)
596 struct mmci_host
*host
= mmc_priv(mmc
);
597 struct mmci_platform_data
*plat
= host
->plat
;
600 if (host
->gpio_cd
== -ENOSYS
) {
602 return 1; /* Assume always present */
604 status
= plat
->status(mmc_dev(host
->mmc
));
606 status
= !!gpio_get_value_cansleep(host
->gpio_cd
)
610 * Use positive logic throughout - status is zero for no card,
611 * non-zero for card inserted.
616 static irqreturn_t
mmci_cd_irq(int irq
, void *dev_id
)
618 struct mmci_host
*host
= dev_id
;
620 mmc_detect_change(host
->mmc
, msecs_to_jiffies(500));
625 static const struct mmc_host_ops mmci_ops
= {
626 .request
= mmci_request
,
627 .set_ios
= mmci_set_ios
,
628 .get_ro
= mmci_get_ro
,
629 .get_cd
= mmci_get_cd
,
632 static int __devinit
mmci_probe(struct amba_device
*dev
, struct amba_id
*id
)
634 struct mmci_platform_data
*plat
= dev
->dev
.platform_data
;
635 struct variant_data
*variant
= id
->data
;
636 struct mmci_host
*host
;
637 struct mmc_host
*mmc
;
640 /* must have platform data */
646 ret
= amba_request_regions(dev
, DRIVER_NAME
);
650 mmc
= mmc_alloc_host(sizeof(struct mmci_host
), &dev
->dev
);
656 host
= mmc_priv(mmc
);
659 host
->gpio_wp
= -ENOSYS
;
660 host
->gpio_cd
= -ENOSYS
;
661 host
->gpio_cd_irq
= -1;
663 host
->hw_designer
= amba_manf(dev
);
664 host
->hw_revision
= amba_rev(dev
);
665 dev_dbg(mmc_dev(mmc
), "designer ID = 0x%02x\n", host
->hw_designer
);
666 dev_dbg(mmc_dev(mmc
), "revision = 0x%01x\n", host
->hw_revision
);
668 host
->clk
= clk_get(&dev
->dev
, NULL
);
669 if (IS_ERR(host
->clk
)) {
670 ret
= PTR_ERR(host
->clk
);
675 ret
= clk_enable(host
->clk
);
680 host
->variant
= variant
;
681 host
->mclk
= clk_get_rate(host
->clk
);
683 * According to the spec, mclk is max 100 MHz,
684 * so we try to adjust the clock down to this,
687 if (host
->mclk
> 100000000) {
688 ret
= clk_set_rate(host
->clk
, 100000000);
691 host
->mclk
= clk_get_rate(host
->clk
);
692 dev_dbg(mmc_dev(mmc
), "eventual mclk rate: %u Hz\n",
695 host
->base
= ioremap(dev
->res
.start
, resource_size(&dev
->res
));
701 mmc
->ops
= &mmci_ops
;
702 mmc
->f_min
= (host
->mclk
+ 511) / 512;
704 * If the platform data supplies a maximum operating
705 * frequency, this takes precedence. Else, we fall back
706 * to using the module parameter, which has a (low)
707 * default value in case it is not specified. Either
708 * value must not exceed the clock rate into the block,
712 mmc
->f_max
= min(host
->mclk
, plat
->f_max
);
714 mmc
->f_max
= min(host
->mclk
, fmax
);
715 dev_dbg(mmc_dev(mmc
), "clocking block at %u Hz\n", mmc
->f_max
);
717 #ifdef CONFIG_REGULATOR
718 /* If we're using the regulator framework, try to fetch a regulator */
719 host
->vcc
= regulator_get(&dev
->dev
, "vmmc");
720 if (IS_ERR(host
->vcc
))
723 int mask
= mmc_regulator_get_ocrmask(host
->vcc
);
726 dev_err(&dev
->dev
, "error getting OCR mask (%d)\n",
729 host
->mmc
->ocr_avail
= (u32
) mask
;
732 "Provided ocr_mask/setpower will not be used "
733 "(using regulator instead)\n");
737 /* Fall back to platform data if no regulator is found */
738 if (host
->vcc
== NULL
)
739 mmc
->ocr_avail
= plat
->ocr_mask
;
740 mmc
->caps
= plat
->capabilities
;
745 mmc
->max_segs
= NR_SG
;
748 * Since only a certain number of bits are valid in the data length
749 * register, we must ensure that we don't exceed 2^num-1 bytes in a
752 mmc
->max_req_size
= (1 << variant
->datalength_bits
) - 1;
755 * Set the maximum segment size. Since we aren't doing DMA
756 * (yet) we are only limited by the data length register.
758 mmc
->max_seg_size
= mmc
->max_req_size
;
761 * Block size can be up to 2048 bytes, but must be a power of two.
763 mmc
->max_blk_size
= 2048;
766 * No limit on the number of blocks transferred.
768 mmc
->max_blk_count
= mmc
->max_req_size
;
770 spin_lock_init(&host
->lock
);
772 writel(0, host
->base
+ MMCIMASK0
);
773 writel(0, host
->base
+ MMCIMASK1
);
774 writel(0xfff, host
->base
+ MMCICLEAR
);
776 if (gpio_is_valid(plat
->gpio_cd
)) {
777 ret
= gpio_request(plat
->gpio_cd
, DRIVER_NAME
" (cd)");
779 ret
= gpio_direction_input(plat
->gpio_cd
);
781 host
->gpio_cd
= plat
->gpio_cd
;
782 else if (ret
!= -ENOSYS
)
785 ret
= request_any_context_irq(gpio_to_irq(plat
->gpio_cd
),
787 DRIVER_NAME
" (cd)", host
);
789 host
->gpio_cd_irq
= gpio_to_irq(plat
->gpio_cd
);
791 if (gpio_is_valid(plat
->gpio_wp
)) {
792 ret
= gpio_request(plat
->gpio_wp
, DRIVER_NAME
" (wp)");
794 ret
= gpio_direction_input(plat
->gpio_wp
);
796 host
->gpio_wp
= plat
->gpio_wp
;
797 else if (ret
!= -ENOSYS
)
801 if ((host
->plat
->status
|| host
->gpio_cd
!= -ENOSYS
)
802 && host
->gpio_cd_irq
< 0)
803 mmc
->caps
|= MMC_CAP_NEEDS_POLL
;
805 ret
= request_irq(dev
->irq
[0], mmci_irq
, IRQF_SHARED
, DRIVER_NAME
" (cmd)", host
);
809 ret
= request_irq(dev
->irq
[1], mmci_pio_irq
, IRQF_SHARED
, DRIVER_NAME
" (pio)", host
);
813 writel(MCI_IRQENABLE
, host
->base
+ MMCIMASK0
);
815 amba_set_drvdata(dev
, mmc
);
819 dev_info(&dev
->dev
, "%s: MMCI rev %x cfg %02x at 0x%016llx irq %d,%d\n",
820 mmc_hostname(mmc
), amba_rev(dev
), amba_config(dev
),
821 (unsigned long long)dev
->res
.start
, dev
->irq
[0], dev
->irq
[1]);
826 free_irq(dev
->irq
[0], host
);
828 if (host
->gpio_wp
!= -ENOSYS
)
829 gpio_free(host
->gpio_wp
);
831 if (host
->gpio_cd_irq
>= 0)
832 free_irq(host
->gpio_cd_irq
, host
);
833 if (host
->gpio_cd
!= -ENOSYS
)
834 gpio_free(host
->gpio_cd
);
838 clk_disable(host
->clk
);
844 amba_release_regions(dev
);
849 static int __devexit
mmci_remove(struct amba_device
*dev
)
851 struct mmc_host
*mmc
= amba_get_drvdata(dev
);
853 amba_set_drvdata(dev
, NULL
);
856 struct mmci_host
*host
= mmc_priv(mmc
);
858 mmc_remove_host(mmc
);
860 writel(0, host
->base
+ MMCIMASK0
);
861 writel(0, host
->base
+ MMCIMASK1
);
863 writel(0, host
->base
+ MMCICOMMAND
);
864 writel(0, host
->base
+ MMCIDATACTRL
);
866 free_irq(dev
->irq
[0], host
);
867 free_irq(dev
->irq
[1], host
);
869 if (host
->gpio_wp
!= -ENOSYS
)
870 gpio_free(host
->gpio_wp
);
871 if (host
->gpio_cd_irq
>= 0)
872 free_irq(host
->gpio_cd_irq
, host
);
873 if (host
->gpio_cd
!= -ENOSYS
)
874 gpio_free(host
->gpio_cd
);
877 clk_disable(host
->clk
);
881 mmc_regulator_set_ocr(mmc
, host
->vcc
, 0);
882 regulator_put(host
->vcc
);
886 amba_release_regions(dev
);
893 static int mmci_suspend(struct amba_device
*dev
, pm_message_t state
)
895 struct mmc_host
*mmc
= amba_get_drvdata(dev
);
899 struct mmci_host
*host
= mmc_priv(mmc
);
901 ret
= mmc_suspend_host(mmc
);
903 writel(0, host
->base
+ MMCIMASK0
);
909 static int mmci_resume(struct amba_device
*dev
)
911 struct mmc_host
*mmc
= amba_get_drvdata(dev
);
915 struct mmci_host
*host
= mmc_priv(mmc
);
917 writel(MCI_IRQENABLE
, host
->base
+ MMCIMASK0
);
919 ret
= mmc_resume_host(mmc
);
925 #define mmci_suspend NULL
926 #define mmci_resume NULL
929 static struct amba_id mmci_ids
[] = {
933 .data
= &variant_arm
,
938 .data
= &variant_arm
,
940 /* ST Micro variants */
944 .data
= &variant_u300
,
949 .data
= &variant_u300
,
954 .data
= &variant_ux500
,
959 static struct amba_driver mmci_driver
= {
964 .remove
= __devexit_p(mmci_remove
),
965 .suspend
= mmci_suspend
,
966 .resume
= mmci_resume
,
967 .id_table
= mmci_ids
,
970 static int __init
mmci_init(void)
972 return amba_driver_register(&mmci_driver
);
975 static void __exit
mmci_exit(void)
977 amba_driver_unregister(&mmci_driver
);
980 module_init(mmci_init
);
981 module_exit(mmci_exit
);
982 module_param(fmax
, uint
, 0444);
984 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
985 MODULE_LICENSE("GPL");