?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Fix one more case of computing the return EPC after the registers have
[firewire-audio.git] / arch / arm / mach-pxa / corgi_lcd.c
blob370df113dc066433640874481e7d055a931a7f39
1 /*
2 * linux/drivers/video/w100fb.c
3 *
4 * Corgi/Spitz LCD Specific Code
5 *
6 * Copyright (C) 2005 Richard Purdie
7 *
8 * Connectivity:
9 * Corgi - LCD to ATI Imageon w100 (Wallaby)
10 * Spitz - LCD to PXA Framebuffer
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 */
17
18 #include <linux/delay.h>
19 #include <linux/kernel.h>
20 #include <linux/device.h>
21 #include <linux/module.h>
22 #include <asm/arch/akita.h>
23 #include <asm/arch/corgi.h>
24 #include <asm/arch/hardware.h>
25 #include <asm/arch/pxa-regs.h>
26 #include <asm/arch/sharpsl.h>
27 #include <asm/arch/spitz.h>
28 #include <asm/hardware/scoop.h>
29 #include <asm/mach/sharpsl_param.h>
30 #include "generic.h"
31
32 /* Register Addresses */
33 #define RESCTL_ADRS 0x00
34 #define PHACTRL_ADRS 0x01
35 #define DUTYCTRL_ADRS 0x02
36 #define POWERREG0_ADRS 0x03
37 #define POWERREG1_ADRS 0x04
38 #define GPOR3_ADRS 0x05
39 #define PICTRL_ADRS 0x06
40 #define POLCTRL_ADRS 0x07
41
42 /* Resgister Bit Definitions */
43 #define RESCTL_QVGA 0x01
44 #define RESCTL_VGA 0x00
45
46 #define POWER1_VW_ON 0x01 /* VW Supply FET ON */
47 #define POWER1_GVSS_ON 0x02 /* GVSS(-8V) Power Supply ON */
48 #define POWER1_VDD_ON 0x04 /* VDD(8V),SVSS(-4V) Power Supply ON */
49
50 #define POWER1_VW_OFF 0x00 /* VW Supply FET OFF */
51 #define POWER1_GVSS_OFF 0x00 /* GVSS(-8V) Power Supply OFF */
52 #define POWER1_VDD_OFF 0x00 /* VDD(8V),SVSS(-4V) Power Supply OFF */
53
54 #define POWER0_COM_DCLK 0x01 /* COM Voltage DC Bias DAC Serial Data Clock */
55 #define POWER0_COM_DOUT 0x02 /* COM Voltage DC Bias DAC Serial Data Out */
56 #define POWER0_DAC_ON 0x04 /* DAC Power Supply ON */
57 #define POWER0_COM_ON 0x08 /* COM Powewr Supply ON */
58 #define POWER0_VCC5_ON 0x10 /* VCC5 Power Supply ON */
59
60 #define POWER0_DAC_OFF 0x00 /* DAC Power Supply OFF */
61 #define POWER0_COM_OFF 0x00 /* COM Powewr Supply OFF */
62 #define POWER0_VCC5_OFF 0x00 /* VCC5 Power Supply OFF */
63
64 #define PICTRL_INIT_STATE 0x01
65 #define PICTRL_INIOFF 0x02
66 #define PICTRL_POWER_DOWN 0x04
67 #define PICTRL_COM_SIGNAL_OFF 0x08
68 #define PICTRL_DAC_SIGNAL_OFF 0x10
69
70 #define POLCTRL_SYNC_POL_FALL 0x01
71 #define POLCTRL_EN_POL_FALL 0x02
72 #define POLCTRL_DATA_POL_FALL 0x04
73 #define POLCTRL_SYNC_ACT_H 0x08
74 #define POLCTRL_EN_ACT_L 0x10
75
76 #define POLCTRL_SYNC_POL_RISE 0x00
77 #define POLCTRL_EN_POL_RISE 0x00
78 #define POLCTRL_DATA_POL_RISE 0x00
79 #define POLCTRL_SYNC_ACT_L 0x00
80 #define POLCTRL_EN_ACT_H 0x00
81
82 #define PHACTRL_PHASE_MANUAL 0x01
83 #define DEFAULT_PHAD_QVGA (9)
84 #define DEFAULT_COMADJ (125)
85
86 /*
87 * This is only a psuedo I2C interface. We can't use the standard kernel
88 * routines as the interface is write only. We just assume the data is acked...
89 */
90 static void lcdtg_ssp_i2c_send(u8 data)
91 {
92 corgi_ssp_lcdtg_send(POWERREG0_ADRS, data);
93 udelay(10);
94 }
95
96 static void lcdtg_i2c_send_bit(u8 data)
97 {
98 lcdtg_ssp_i2c_send(data);
99 lcdtg_ssp_i2c_send(data | POWER0_COM_DCLK);
100 lcdtg_ssp_i2c_send(data);
101 }
102
103 static void lcdtg_i2c_send_start(u8 base)
104 {
105 lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK | POWER0_COM_DOUT);
106 lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK);
107 lcdtg_ssp_i2c_send(base);
108 }
109
110 static void lcdtg_i2c_send_stop(u8 base)
111 {
112 lcdtg_ssp_i2c_send(base);
113 lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK);
114 lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK | POWER0_COM_DOUT);
115 }
116
117 static void lcdtg_i2c_send_byte(u8 base, u8 data)
118 {
119 int i;
120 for (i = 0; i < 8; i++) {
121 if (data & 0x80)
122 lcdtg_i2c_send_bit(base | POWER0_COM_DOUT);
123 else
124 lcdtg_i2c_send_bit(base);
125 data <<= 1;
126 }
127 }
128
129 static void lcdtg_i2c_wait_ack(u8 base)
130 {
131 lcdtg_i2c_send_bit(base);
132 }
133
134 static void lcdtg_set_common_voltage(u8 base_data, u8 data)
135 {
136 /* Set Common Voltage to M62332FP via I2C */
137 lcdtg_i2c_send_start(base_data);
138 lcdtg_i2c_send_byte(base_data, 0x9c);
139 lcdtg_i2c_wait_ack(base_data);
140 lcdtg_i2c_send_byte(base_data, 0x00);
141 lcdtg_i2c_wait_ack(base_data);
142 lcdtg_i2c_send_byte(base_data, data);
143 lcdtg_i2c_wait_ack(base_data);
144 lcdtg_i2c_send_stop(base_data);
145 }
146
147 /* Set Phase Adjuct */
148 static void lcdtg_set_phadadj(int mode)
149 {
150 int adj;
151 switch(mode) {
152 case 480:
153 case 640:
154 /* Setting for VGA */
155 adj = sharpsl_param.phadadj;
156 if (adj < 0) {
157 adj = PHACTRL_PHASE_MANUAL;
158 } else {
159 adj = ((adj & 0x0f) << 1) | PHACTRL_PHASE_MANUAL;
160 }
161 break;
162 case 240:
163 case 320:
164 default:
165 /* Setting for QVGA */
166 adj = (DEFAULT_PHAD_QVGA << 1) | PHACTRL_PHASE_MANUAL;
167 break;
168 }
169
170 corgi_ssp_lcdtg_send(PHACTRL_ADRS, adj);
171 }
172
173 static int lcd_inited;
174
175 static void lcdtg_hw_init(int mode)
176 {
177 if (!lcd_inited) {
178 int comadj;
179
180 /* Initialize Internal Logic & Port */
181 corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_POWER_DOWN | PICTRL_INIOFF | PICTRL_INIT_STATE
182 | PICTRL_COM_SIGNAL_OFF | PICTRL_DAC_SIGNAL_OFF);
183
184 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_OFF
185 | POWER0_COM_OFF | POWER0_VCC5_OFF);
186
187 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF);
188
189 /* VDD(+8V), SVSS(-4V) ON */
190 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON);
191 mdelay(3);
192
193 /* DAC ON */
194 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON
195 | POWER0_COM_OFF | POWER0_VCC5_OFF);
196
197 /* INIB = H, INI = L */
198 /* PICTL[0] = H , PICTL[1] = PICTL[2] = PICTL[4] = L */
199 corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIT_STATE | PICTRL_COM_SIGNAL_OFF);
200
201 /* Set Common Voltage */
202 comadj = sharpsl_param.comadj;
203 if (comadj < 0)
204 comadj = DEFAULT_COMADJ;
205 lcdtg_set_common_voltage((POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF), comadj);
206
207 /* VCC5 ON, DAC ON */
208 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON |
209 POWER0_COM_OFF | POWER0_VCC5_ON);
210
211 /* GVSS(-8V) ON, VDD ON */
212 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON);
213 mdelay(2);
214
215 /* COM SIGNAL ON (PICTL[3] = L) */
216 corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIT_STATE);
217
218 /* COM ON, DAC ON, VCC5_ON */
219 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON
220 | POWER0_COM_ON | POWER0_VCC5_ON);
221
222 /* VW ON, GVSS ON, VDD ON */
223 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_ON | POWER1_GVSS_ON | POWER1_VDD_ON);
224
225 /* Signals output enable */
226 corgi_ssp_lcdtg_send(PICTRL_ADRS, 0);
227
228 /* Set Phase Adjuct */
229 lcdtg_set_phadadj(mode);
230
231 /* Initialize for Input Signals from ATI */
232 corgi_ssp_lcdtg_send(POLCTRL_ADRS, POLCTRL_SYNC_POL_RISE | POLCTRL_EN_POL_RISE
233 | POLCTRL_DATA_POL_RISE | POLCTRL_SYNC_ACT_L | POLCTRL_EN_ACT_H);
234 udelay(1000);
235
236 lcd_inited=1;
237 } else {
238 lcdtg_set_phadadj(mode);
239 }
240
241 switch(mode) {
242 case 480:
243 case 640:
244 /* Set Lcd Resolution (VGA) */
245 corgi_ssp_lcdtg_send(RESCTL_ADRS, RESCTL_VGA);
246 break;
247 case 240:
248 case 320:
249 default:
250 /* Set Lcd Resolution (QVGA) */
251 corgi_ssp_lcdtg_send(RESCTL_ADRS, RESCTL_QVGA);
252 break;
253 }
254 }
255
256 static void lcdtg_suspend(void)
257 {
258 /* 60Hz x 2 frame = 16.7msec x 2 = 33.4 msec */
259 mdelay(34);
260
261 /* (1)VW OFF */
262 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON);
263
264 /* (2)COM OFF */
265 corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_COM_SIGNAL_OFF);
266 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON);
267
268 /* (3)Set Common Voltage Bias 0V */
269 lcdtg_set_common_voltage(POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON, 0);
270
271 /* (4)GVSS OFF */
272 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON);
273
274 /* (5)VCC5 OFF */
275 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF);
276
277 /* (6)Set PDWN, INIOFF, DACOFF */
278 corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIOFF | PICTRL_DAC_SIGNAL_OFF |
279 PICTRL_POWER_DOWN | PICTRL_COM_SIGNAL_OFF);
280
281 /* (7)DAC OFF */
282 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_OFF | POWER0_COM_OFF | POWER0_VCC5_OFF);
283
284 /* (8)VDD OFF */
285 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF);
286
287 lcd_inited = 0;
288 }
289
290
291 /*
292 * Corgi w100 Frame Buffer Device
293 */
294 #ifdef CONFIG_PXA_SHARP_C7xx
295
296 #include <video/w100fb.h>
297
298 static void w100_lcdtg_suspend(struct w100fb_par *par)
299 {
300 lcdtg_suspend();
301 }
302
303 static void w100_lcdtg_init(struct w100fb_par *par)
304 {
305 lcdtg_hw_init(par->xres);
306 }
307
308
309 static struct w100_tg_info corgi_lcdtg_info = {
310 .change = w100_lcdtg_init,
311 .suspend = w100_lcdtg_suspend,
312 .resume = w100_lcdtg_init,
313 };
314
315 static struct w100_mem_info corgi_fb_mem = {
316 .ext_cntl = 0x00040003,
317 .sdram_mode_reg = 0x00650021,
318 .ext_timing_cntl = 0x10002a4a,
319 .io_cntl = 0x7ff87012,
320 .size = 0x1fffff,
321 };
322
323 static struct w100_gen_regs corgi_fb_regs = {
324 .lcd_format = 0x00000003,
325 .lcdd_cntl1 = 0x01CC0000,
326 .lcdd_cntl2 = 0x0003FFFF,
327 .genlcd_cntl1 = 0x00FFFF0D,
328 .genlcd_cntl2 = 0x003F3003,
329 .genlcd_cntl3 = 0x000102aa,
330 };
331
332 static struct w100_gpio_regs corgi_fb_gpio = {
333 .init_data1 = 0x000000bf,
334 .init_data2 = 0x00000000,
335 .gpio_dir1 = 0x00000000,
336 .gpio_oe1 = 0x03c0feff,
337 .gpio_dir2 = 0x00000000,
338 .gpio_oe2 = 0x00000000,
339 };
340
341 static struct w100_mode corgi_fb_modes[] = {
342 {
343 .xres = 480,
344 .yres = 640,
345 .left_margin = 0x56,
346 .right_margin = 0x55,
347 .upper_margin = 0x03,
348 .lower_margin = 0x00,
349 .crtc_ss = 0x82360056,
350 .crtc_ls = 0xA0280000,
351 .crtc_gs = 0x80280028,
352 .crtc_vpos_gs = 0x02830002,
353 .crtc_rev = 0x00400008,
354 .crtc_dclk = 0xA0000000,
355 .crtc_gclk = 0x8015010F,
356 .crtc_goe = 0x80100110,
357 .crtc_ps1_active = 0x41060010,
358 .pll_freq = 75,
359 .fast_pll_freq = 100,
360 .sysclk_src = CLK_SRC_PLL,
361 .sysclk_divider = 0,
362 .pixclk_src = CLK_SRC_PLL,
363 .pixclk_divider = 2,
364 .pixclk_divider_rotated = 6,
365 },{
366 .xres = 240,
367 .yres = 320,
368 .left_margin = 0x27,
369 .right_margin = 0x2e,
370 .upper_margin = 0x01,
371 .lower_margin = 0x00,
372 .crtc_ss = 0x81170027,
373 .crtc_ls = 0xA0140000,
374 .crtc_gs = 0xC0140014,
375 .crtc_vpos_gs = 0x00010141,
376 .crtc_rev = 0x00400008,
377 .crtc_dclk = 0xA0000000,
378 .crtc_gclk = 0x8015010F,
379 .crtc_goe = 0x80100110,
380 .crtc_ps1_active = 0x41060010,
381 .pll_freq = 0,
382 .fast_pll_freq = 0,
383 .sysclk_src = CLK_SRC_XTAL,
384 .sysclk_divider = 0,
385 .pixclk_src = CLK_SRC_XTAL,
386 .pixclk_divider = 1,
387 .pixclk_divider_rotated = 1,
388 },
389
390 };
391
392 static struct w100fb_mach_info corgi_fb_info = {
393 .tg = &corgi_lcdtg_info,
394 .init_mode = INIT_MODE_ROTATED,
395 .mem = &corgi_fb_mem,
396 .regs = &corgi_fb_regs,
397 .modelist = &corgi_fb_modes[0],
398 .num_modes = 2,
399 .gpio = &corgi_fb_gpio,
400 .xtal_freq = 12500000,
401 .xtal_dbl = 0,
402 };
403
404 static struct resource corgi_fb_resources[] = {
405 [0] = {
406 .start = 0x08000000,
407 .end = 0x08ffffff,
408 .flags = IORESOURCE_MEM,
409 },
410 };
411
412 struct platform_device corgifb_device = {
413 .name = "w100fb",
414 .id = -1,
415 .num_resources = ARRAY_SIZE(corgi_fb_resources),
416 .resource = corgi_fb_resources,
417 .dev = {
418 .platform_data = &corgi_fb_info,
419 .parent = &corgissp_device.dev,
420 },
421
422 };
423 #endif
424
425
426 /*
427 * Spitz PXA Frame Buffer Device
428 */
429 #ifdef CONFIG_PXA_SHARP_Cxx00
430
431 #include <asm/arch/pxafb.h>
432
433 void spitz_lcd_power(int on)
434 {
435 if (on)
436 lcdtg_hw_init(480);
437 else
438 lcdtg_suspend();
439 }
440
441 #endif
442
443
444 /*
445 * Corgi/Spitz Touchscreen to LCD interface
446 */
447 static unsigned long (*get_hsync_time)(struct device *dev);
448
449 static void inline sharpsl_wait_sync(int gpio)
450 {
451 while((GPLR(gpio) & GPIO_bit(gpio)) == 0);
452 while((GPLR(gpio) & GPIO_bit(gpio)) != 0);
453 }
454
455 #ifdef CONFIG_PXA_SHARP_C7xx
456 unsigned long corgi_get_hsync_len(void)
457 {
458 if (!get_hsync_time)
459 get_hsync_time = symbol_get(w100fb_get_hsynclen);
460 if (!get_hsync_time)
461 return 0;
462
463 return get_hsync_time(&corgifb_device.dev);
464 }
465
466 void corgi_put_hsync(void)
467 {
468 if (get_hsync_time)
469 symbol_put(w100fb_get_hsynclen);
470 get_hsync_time = NULL;
471 }
472
473 void corgi_wait_hsync(void)
474 {
475 sharpsl_wait_sync(CORGI_GPIO_HSYNC);
476 }
477 #endif
478
479 #ifdef CONFIG_PXA_SHARP_Cxx00
480 static struct device *spitz_pxafb_dev;
481
482 static int is_pxafb_device(struct device * dev, void * data)
483 {
484 struct platform_device *pdev = container_of(dev, struct platform_device, dev);
485
486 return (strncmp(pdev->name, "pxa2xx-fb", 9) == 0);
487 }
488
489 unsigned long spitz_get_hsync_len(void)
490 {
491 #ifdef CONFIG_FB_PXA
492 if (!spitz_pxafb_dev) {
493 spitz_pxafb_dev = bus_find_device(&platform_bus_type, NULL, NULL, is_pxafb_device);
494 if (!spitz_pxafb_dev)
495 return 0;
496 }
497 if (!get_hsync_time)
498 get_hsync_time = symbol_get(pxafb_get_hsync_time);
499 if (!get_hsync_time)
500 #endif
501 return 0;
502
503 return pxafb_get_hsync_time(spitz_pxafb_dev);
504 }
505
506 void spitz_put_hsync(void)
507 {
508 put_device(spitz_pxafb_dev);
509 if (get_hsync_time)
510 symbol_put(pxafb_get_hsync_time);
511 spitz_pxafb_dev = NULL;
512 get_hsync_time = NULL;
513 }
514
515 void spitz_wait_hsync(void)
516 {
517 sharpsl_wait_sync(SPITZ_GPIO_HSYNC);
518 }
519 #endif
520
521 /*
522 * Corgi/Spitz Backlight Power
523 */
524 #ifdef CONFIG_PXA_SHARP_C7xx
525 void corgi_bl_set_intensity(int intensity)
526 {
527 if (intensity > 0x10)
528 intensity += 0x10;
529
530 /* Bits 0-4 are accessed via the SSP interface */
531 corgi_ssp_blduty_set(intensity & 0x1f);
532
533 /* Bit 5 is via SCOOP */
534 if (intensity & 0x0020)
535 set_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_BACKLIGHT_CONT);
536 else
537 reset_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_BACKLIGHT_CONT);
538 }
539 #endif
540
541
542 #if defined(CONFIG_MACH_SPITZ) || defined(CONFIG_MACH_BORZOI)
543 void spitz_bl_set_intensity(int intensity)
544 {
545 if (intensity > 0x10)
546 intensity += 0x10;
547
548 /* Bits 0-4 are accessed via the SSP interface */
549 corgi_ssp_blduty_set(intensity & 0x1f);
550
551 /* Bit 5 is via SCOOP */
552 if (intensity & 0x0020)
553 reset_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_BACKLIGHT_CONT);
554 else
555 set_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_BACKLIGHT_CONT);
556
557 if (intensity)
558 set_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_BACKLIGHT_ON);
559 else
560 reset_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_BACKLIGHT_ON);
561 }
562 #endif
563
564 #ifdef CONFIG_MACH_AKITA
565 void akita_bl_set_intensity(int intensity)
566 {
567 if (intensity > 0x10)
568 intensity += 0x10;
569
570 /* Bits 0-4 are accessed via the SSP interface */
571 corgi_ssp_blduty_set(intensity & 0x1f);
572
573 /* Bit 5 is via IO-Expander */
574 if (intensity & 0x0020)
575 akita_reset_ioexp(&akitaioexp_device.dev, AKITA_IOEXP_BACKLIGHT_CONT);
576 else
577 akita_set_ioexp(&akitaioexp_device.dev, AKITA_IOEXP_BACKLIGHT_CONT);
578
579 if (intensity)
580 akita_set_ioexp(&akitaioexp_device.dev, AKITA_IOEXP_BACKLIGHT_ON);
581 else
582 akita_reset_ioexp(&akitaioexp_device.dev, AKITA_IOEXP_BACKLIGHT_ON);
583 }
584 #endif
AMDTP streaming driver for the Linux FireWire stack (Juju)