1 ;;; verilog-mode.el --- major mode for editing verilog source in Emacs
3 ;; Copyright (C) 1996-2015 Free Software Foundation, Inc.
5 ;; Author: Michael McNamara <mac@verilog.com>
6 ;; Wilson Snyder <wsnyder@wsnyder.org>
7 ;; http://www.verilog.com
8 ;; http://www.veripool.org
10 ;; Keywords: languages
12 ;; Yoni Rabkin <yoni@rabkins.net> contacted the maintainer of this
13 ;; file on 19/3/2008, and the maintainer agreed that when a bug is
14 ;; filed in the Emacs bug reporting system against this file, a copy
15 ;; of the bug report be sent to the maintainer's email address.
17 ;; This code supports Emacs 21.1 and later
18 ;; And XEmacs 21.1 and later
19 ;; Please do not make changes that break Emacs 21. Thanks!
23 ;; This file is part of GNU Emacs.
25 ;; GNU Emacs is free software: you can redistribute it and/or modify
26 ;; it under the terms of the GNU General Public License as published by
27 ;; the Free Software Foundation, either version 3 of the License, or
28 ;; (at your option) any later version.
30 ;; GNU Emacs is distributed in the hope that it will be useful,
31 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
32 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 ;; GNU General Public License for more details.
35 ;; You should have received a copy of the GNU General Public License
36 ;; along with GNU Emacs. If not, see <http://www.gnu.org/licenses/>.
43 ;; A major mode for editing Verilog and SystemVerilog HDL source code (IEEE
44 ;; 1364-2005 and IEEE 1800-2012 standards). When you have entered Verilog
45 ;; mode, you may get more info by pressing C-h m. You may also get online
46 ;; help describing various functions by: C-h f <Name of function you want
49 ;; KNOWN BUGS / BUG REPORTS
50 ;; =======================
52 ;; SystemVerilog is a rapidly evolving language, and hence this mode is
53 ;; under continuous development. Please report any issues to the issue
56 ;; http://www.veripool.org/verilog-mode
58 ;; Please use verilog-submit-bug-report to submit a report; type C-c
59 ;; C-b to invoke this and as a result we will have a much easier time
60 ;; of reproducing the bug you find, and hence fixing it.
62 ;; INSTALLING THE MODE
63 ;; ===================
65 ;; An older version of this mode may be already installed as a part of
66 ;; your environment, and one method of updating would be to update
67 ;; your Emacs environment. Sometimes this is difficult for local
68 ;; political/control reasons, and hence you can always install a
69 ;; private copy (or even a shared copy) which overrides the system
72 ;; You can get step by step help in installing this file by going to
73 ;; <http://www.verilog.com/emacs_install.html>
75 ;; The short list of installation instructions are: To set up
76 ;; automatic Verilog mode, put this file in your load path, and put
77 ;; the following in code (please un comment it first!) in your
78 ;; .emacs, or in your site's site-load.el
80 ;; (autoload 'verilog-mode "verilog-mode" "Verilog mode" t )
81 ;; (add-to-list 'auto-mode-alist '("\\.[ds]?vh?\\'" . verilog-mode))
83 ;; Be sure to examine at the help for verilog-auto, and the other
84 ;; verilog-auto-* functions for some major coding time savers.
86 ;; If you want to customize Verilog mode to fit your needs better,
87 ;; you may add the below lines (the values of the variables presented
88 ;; here are the defaults). Note also that if you use an Emacs that
89 ;; supports custom, it's probably better to use the custom menu to
90 ;; edit these. If working as a member of a large team these settings
91 ;; should be common across all users (in a site-start file), or set
92 ;; in Local Variables in every file. Otherwise, different people's
93 ;; AUTO expansion may result different whitespace changes.
95 ;; ;; Enable syntax highlighting of **all** languages
96 ;; (global-font-lock-mode t)
98 ;; ;; User customization for Verilog mode
99 ;; (setq verilog-indent-level 3
100 ;; verilog-indent-level-module 3
101 ;; verilog-indent-level-declaration 3
102 ;; verilog-indent-level-behavioral 3
103 ;; verilog-indent-level-directive 1
104 ;; verilog-case-indent 2
105 ;; verilog-auto-newline t
106 ;; verilog-auto-indent-on-newline t
107 ;; verilog-tab-always-indent t
108 ;; verilog-auto-endcomments t
109 ;; verilog-minimum-comment-distance 40
110 ;; verilog-indent-begin-after-if t
111 ;; verilog-auto-lineup 'declarations
112 ;; verilog-highlight-p1800-keywords nil
113 ;; verilog-linter "my_lint_shell_command"
119 ;; See commit history at http://www.veripool.org/verilog-mode.html
120 ;; (This section is required to appease checkdoc.)
125 ;; This variable will always hold the version number of the mode
126 (defconst verilog-mode-version
"2015-08-16-ce03c7a-vpo-GNU"
127 "Version of this Verilog mode.")
128 (defconst verilog-mode-release-emacs t
129 "If non-nil, this version of Verilog mode was released with Emacs itself.")
131 (defun verilog-version ()
132 "Inform caller of the version of this file."
134 (message "Using verilog-mode version %s" verilog-mode-version
))
136 ;; Insure we have certain packages, and deal with it if we don't
137 ;; Be sure to note which Emacs flavor and version added each feature.
139 ;; Provide stuff if we are XEmacs
140 (when (featurep 'xemacs
)
145 (require 'regexp-opt
)
147 ;; Bug in 19.28 through 19.30 skeleton.el, not provided.
154 (defmacro when
(cond &rest body
)
155 (list 'if cond
(cons 'progn body
))))
158 (if (fboundp 'unless
)
160 (defmacro unless
(cond &rest body
)
161 (cons 'if
(cons cond
(cons nil body
)))))
164 (if (fboundp 'store-match-data
)
166 (defmacro store-match-data
(&rest _args
) nil
))
169 (if (fboundp 'char-before
)
171 (defmacro char-before
(&rest _body
)
172 (char-after (1- (point)))))
177 (defsubst point-at-bol
(&optional N
)
178 (save-excursion (beginning-of-line N
) (point))))
183 (defsubst point-at-eol
(&optional N
)
184 (save-excursion (end-of-line N
) (point))))
190 (if (fboundp 'match-string-no-properties
)
192 (defsubst match-string-no-properties
(num &optional string
)
193 "Return string of text matched by last search, without text properties.
194 NUM specifies which parenthesized expression in the last regexp.
195 Value is nil if NUMth pair didn't match, or there were less than NUM pairs.
196 Zero means the entire text matched by the whole regexp or whole string.
197 STRING should be given if the last search was by `string-match' on STRING."
198 (if (match-beginning num
)
202 (match-beginning num
) (match-end num
))))
203 (set-text-properties 0 (length result
) nil result
)
205 (buffer-substring-no-properties (match-beginning num
)
210 (if (and (featurep 'custom
) (fboundp 'custom-declare-variable
))
211 nil
; We've got what we needed
212 ;; We have the old custom-library, hack around it!
213 (defmacro defgroup
(&rest _args
) nil
)
214 (defmacro customize
(&rest _args
)
216 "Sorry, Customize is not available with this version of Emacs"))
217 (defmacro defcustom
(var value doc
&rest _args
)
218 `(defvar ,var
,value
,doc
))
220 (if (fboundp 'defface
)
222 (defmacro defface
(var values doc
&rest _args
)
226 (if (and (featurep 'custom
) (fboundp 'customize-group
))
227 nil
; We've got what we needed
228 ;; We have an intermediate custom-library, hack around it!
229 (defmacro customize-group
(var &rest _args
)
233 (unless (boundp 'inhibit-point-motion-hooks
)
234 (defvar inhibit-point-motion-hooks nil
))
235 (unless (boundp 'deactivate-mark
)
236 (defvar deactivate-mark nil
))
239 ;; OK, do this stuff if we are NOT XEmacs:
240 (unless (featurep 'xemacs
)
241 (unless (fboundp 'region-active-p
)
242 (defmacro region-active-p
()
243 `(and transient-mark-mode mark-active
))))
246 ;; Provide a regular expression optimization routine, using regexp-opt
247 ;; if provided by the user's elisp libraries
249 ;; The below were disabled when GNU Emacs 22 was released;
250 ;; perhaps some still need to be there to support Emacs 21.
251 (if (featurep 'xemacs
)
252 (if (fboundp 'regexp-opt
)
253 ;; regexp-opt is defined, does it take 3 or 2 arguments?
254 (if (fboundp 'function-max-args
)
255 (let ((args (function-max-args `regexp-opt
)))
257 ((eq args
3) ; It takes 3
258 (condition-case nil
; Hide this defun from emacses
259 ; with just a two input regexp
260 (defun verilog-regexp-opt (a b
)
261 "Deal with differing number of required arguments for `regexp-opt'.
262 Call `regexp-opt' on A and B."
266 ((eq args
2) ; It takes 2
267 (defun verilog-regexp-opt (a b
)
268 "Call `regexp-opt' on A and B."
272 ;; We can't tell; assume it takes 2
273 (defun verilog-regexp-opt (a b
)
274 "Call `regexp-opt' on A and B."
277 ;; There is no regexp-opt, provide our own
278 (defun verilog-regexp-opt (strings &optional paren _shy
)
279 (let ((open (if paren
"\\(" "")) (close (if paren
"\\)" "")))
280 (concat open
(mapconcat 'regexp-quote strings
"\\|") close
)))
283 (defalias 'verilog-regexp-opt
'regexp-opt
)))
285 ;; emacs >=22 has looking-back, but older emacs and xemacs don't.
286 ;; This function is lifted directly from emacs's subr.el
287 ;; so that it can be used by xemacs.
288 ;; The idea for this was borrowed from org-mode via this link:
289 ;; https://lists.gnu.org/archive/html/emacs-orgmode/2009-12/msg00032.html
292 ((fboundp 'looking-back
)
293 (defalias 'verilog-looking-back
'looking-back
))
295 (defun verilog-looking-back (regexp limit
&optional greedy
)
296 "Return non-nil if text before point matches regular expression REGEXP.
297 Like `looking-at' except matches before point, and is slower.
298 LIMIT if non-nil speeds up the search by specifying a minimum
299 starting position, to avoid checking matches that would start
302 If GREEDY is non-nil, extend the match backwards as far as
303 possible, stopping when a single additional previous character
304 cannot be part of a match for REGEXP. When the match is
305 extended, its starting position is allowed to occur before
308 As a general recommendation, try to avoid using `looking-back'
309 wherever possible, since it is slow."
310 (let ((start (point))
313 (and (re-search-backward (concat "\\(?:" regexp
"\\)\\=") limit t
)
317 (narrow-to-region (point-min) start
)
318 (while (and (> pos
(point-min))
322 (looking-at (concat "\\(?:" regexp
"\\)\\'"))))
326 (looking-at (concat "\\(?:" regexp
"\\)\\'")))))
327 (not (null pos
)))))))
330 ;; Both xemacs and emacs
332 (require 'diff
) ; diff-command and diff-switches
335 (require 'compile
) ; compilation-error-regexp-alist-alist
338 (unless (fboundp 'buffer-chars-modified-tick
) ; Emacs 22 added
339 (defmacro buffer-chars-modified-tick
() (buffer-modified-tick)))
341 ;; Added in Emacs 24.1
343 (unless (fboundp 'prog-mode
)
344 (define-derived-mode prog-mode fundamental-mode
"Prog"))
348 (defun verilog-regexp-words (a)
349 "Call `regexp-opt' with word delimiters for the words A."
350 (concat "\\<" (verilog-regexp-opt a t
) "\\>")))
351 (defun verilog-regexp-words (a)
352 "Call `regexp-opt' with word delimiters for the words A."
353 ;; The FAQ references this function, so user LISP sometimes calls it
354 (concat "\\<" (verilog-regexp-opt a t
) "\\>"))
356 (defun verilog-easy-menu-filter (menu)
357 "Filter `easy-menu-define' MENU to support new features."
358 (cond ((not (featurep 'xemacs
))
359 menu
) ; GNU Emacs - passthru
360 ;; XEmacs doesn't support :help. Strip it.
361 ;; Recursively filter the a submenu
363 (mapcar 'verilog-easy-menu-filter menu
))
364 ;; Look for [:help "blah"] and remove
366 (let ((i 0) (out []))
367 (while (< i
(length menu
))
368 (if (equal `:help
(aref menu i
))
370 (setq out
(vconcat out
(vector (aref menu i
)))
373 (t menu
))) ; Default - ok
374 ;;(verilog-easy-menu-filter
375 ;; `("Verilog" ("MA" ["SAA" nil :help "Help SAA"] ["SAB" nil :help "Help SAA"])
376 ;; "----" ["MB" nil :help "Help MB"]))
378 (defun verilog-define-abbrev (table name expansion
&optional hook
)
379 "Filter `define-abbrev' TABLE NAME EXPANSION and call HOOK.
380 Provides SYSTEM-FLAG in newer Emacs."
382 (define-abbrev table name expansion hook
0 t
)
384 (define-abbrev table name expansion hook
))))
386 (defun verilog-customize ()
387 "Customize variables and other settings used by Verilog-Mode."
389 (customize-group 'verilog-mode
))
391 (defun verilog-font-customize ()
392 "Customize fonts used by Verilog-Mode."
394 (if (fboundp 'customize-apropos
)
395 (customize-apropos "font-lock-*" 'faces
)))
397 (defun verilog-booleanp (value)
398 "Return t if VALUE is boolean.
399 This implements GNU Emacs 22.1's `booleanp' function in earlier Emacs.
400 This function may be removed when Emacs 21 is no longer supported."
401 (or (equal value t
) (equal value nil
)))
403 (defun verilog-insert-last-command-event ()
404 "Insert the `last-command-event'."
405 (insert (if (featurep 'xemacs
)
406 ;; XEmacs 21.5 doesn't like last-command-event
408 ;; And GNU Emacs 22 has obsoleted last-command-char
409 last-command-event
)))
411 (defvar verilog-no-change-functions nil
412 "True if `after-change-functions' is disabled.
413 Use of `syntax-ppss' may break, as ppss's cache may get corrupted.")
415 (defvar verilog-in-hooks nil
416 "True when within a `verilog-run-hooks' block.")
418 (defmacro verilog-run-hooks
(&rest hooks
)
419 "Run each hook in HOOKS using `run-hooks'.
420 Set `verilog-in-hooks' during this time, to assist AUTO caches."
421 `(let ((verilog-in-hooks t
))
422 (run-hooks ,@hooks
)))
424 (defun verilog-syntax-ppss (&optional pos
)
425 (when verilog-no-change-functions
427 (verilog-scan-cache-flush)
428 ;; else don't let the AUTO code itself get away with flushing the cache,
429 ;; as that'll make things very slow
431 (error "%s: Internal problem; use of syntax-ppss when cache may be corrupt"
432 (verilog-point-text))))
433 (if (fboundp 'syntax-ppss
)
435 (parse-partial-sexp (point-min) (or pos
(point)))))
437 (defgroup verilog-mode nil
438 "Major mode for Verilog source code."
442 ;; (defgroup verilog-mode-fonts nil
443 ;; "Facilitates easy customization fonts used in Verilog source text"
444 ;; :link '(customize-apropos "font-lock-*" 'faces)
445 ;; :group 'verilog-mode)
447 (defgroup verilog-mode-indent nil
448 "Customize indentation and highlighting of Verilog source text."
449 :group
'verilog-mode
)
451 (defgroup verilog-mode-actions nil
452 "Customize actions on Verilog source text."
453 :group
'verilog-mode
)
455 (defgroup verilog-mode-auto nil
456 "Customize AUTO actions when expanding Verilog source text."
457 :group
'verilog-mode
)
459 (defvar verilog-debug nil
460 "Non-nil means enable debug messages for `verilog-mode' internals.")
462 (defvar verilog-warn-fatal nil
463 "Non-nil means `verilog-warn-error' warnings are fatal `error's.")
465 (defcustom verilog-linter
466 "echo 'No verilog-linter set, see \"M-x describe-variable verilog-linter\"'"
467 "Unix program and arguments to call to run a lint checker on Verilog source.
468 Depending on the `verilog-set-compile-command', this may be invoked when
469 you type \\[compile]. When the compile completes, \\[next-error] will take
470 you to the next lint error."
472 :group
'verilog-mode-actions
)
473 ;; We don't mark it safe, as it's used as a shell command
475 (defcustom verilog-coverage
476 "echo 'No verilog-coverage set, see \"M-x describe-variable verilog-coverage\"'"
477 "Program and arguments to use to annotate for coverage Verilog source.
478 Depending on the `verilog-set-compile-command', this may be invoked when
479 you type \\[compile]. When the compile completes, \\[next-error] will take
480 you to the next lint error."
482 :group
'verilog-mode-actions
)
483 ;; We don't mark it safe, as it's used as a shell command
485 (defcustom verilog-simulator
486 "echo 'No verilog-simulator set, see \"M-x describe-variable verilog-simulator\"'"
487 "Program and arguments to use to interpret Verilog source.
488 Depending on the `verilog-set-compile-command', this may be invoked when
489 you type \\[compile]. When the compile completes, \\[next-error] will take
490 you to the next lint error."
492 :group
'verilog-mode-actions
)
493 ;; We don't mark it safe, as it's used as a shell command
495 (defcustom verilog-compiler
496 "echo 'No verilog-compiler set, see \"M-x describe-variable verilog-compiler\"'"
497 "Program and arguments to use to compile Verilog source.
498 Depending on the `verilog-set-compile-command', this may be invoked when
499 you type \\[compile]. When the compile completes, \\[next-error] will take
500 you to the next lint error."
502 :group
'verilog-mode-actions
)
503 ;; We don't mark it safe, as it's used as a shell command
505 (defcustom verilog-preprocessor
506 ;; Very few tools give preprocessed output, so we'll default to Verilog-Perl
507 "vppreproc __FLAGS__ __FILE__"
508 "Program and arguments to use to preprocess Verilog source.
509 This is invoked with `verilog-preprocess', and depending on the
510 `verilog-set-compile-command', may also be invoked when you type
511 \\[compile]. When the compile completes, \\[next-error] will
512 take you to the next lint error."
514 :group
'verilog-mode-actions
)
515 ;; We don't mark it safe, as it's used as a shell command
517 (defvar verilog-preprocess-history nil
518 "History for `verilog-preprocess'.")
520 (defvar verilog-tool
'verilog-linter
521 "Which tool to use for building compiler-command.
522 Either nil, `verilog-linter', `verilog-compiler',
523 `verilog-coverage', `verilog-preprocessor', or `verilog-simulator'.
524 Alternatively use the \"Choose Compilation Action\" menu. See
525 `verilog-set-compile-command' for more information.")
527 (defcustom verilog-highlight-translate-off nil
528 "Non-nil means background-highlight code excluded from translation.
529 That is, all code between \"// synopsys translate_off\" and
530 \"// synopsys translate_on\" is highlighted using a different background color
531 \(face `verilog-font-lock-translate-off-face').
533 Note: This will slow down on-the-fly fontification (and thus editing).
535 Note: Activate the new setting in a Verilog buffer by re-fontifying it (menu
536 entry \"Fontify Buffer\"). XEmacs: turn off and on font locking."
538 :group
'verilog-mode-indent
)
539 ;; Note we don't use :safe, as that would break on Emacsen before 22.0.
540 (put 'verilog-highlight-translate-off
'safe-local-variable
'verilog-booleanp
)
542 (defcustom verilog-auto-lineup
'declarations
543 "Type of statements to lineup across multiple lines.
544 If `all' is selected, then all line ups described below are done.
546 If `declarations', then just declarations are lined up with any
547 preceding declarations, taking into account widths and the like,
548 so or example the code:
555 If `assignment', then assignments are lined up with any preceding
556 assignments, so for example the code
557 a_long_variable <= b + c;
560 a_long_variable <= b + c;
563 In order to speed up editing, large blocks of statements are lined up
564 only when a \\[verilog-pretty-expr] is typed; and large blocks of declarations
565 are lineup only when \\[verilog-pretty-declarations] is typed."
567 :type
'(radio (const :tag
"Line up Assignments and Declarations" all
)
568 (const :tag
"Line up Assignment statements" assignments
)
569 (const :tag
"Line up Declarations" declarations
)
570 (function :tag
"Other"))
571 :group
'verilog-mode-indent
)
572 (put 'verilog-auto-lineup
'safe-local-variable
573 '(lambda (x) (memq x
'(nil all assignments declarations
))))
575 (defcustom verilog-indent-level
3
576 "Indentation of Verilog statements with respect to containing block."
577 :group
'verilog-mode-indent
579 (put 'verilog-indent-level
'safe-local-variable
'integerp
)
581 (defcustom verilog-indent-level-module
3
582 "Indentation of Module level Verilog statements (eg always, initial).
583 Set to 0 to get initial and always statements lined up on the left side of
585 :group
'verilog-mode-indent
587 (put 'verilog-indent-level-module
'safe-local-variable
'integerp
)
589 (defcustom verilog-indent-level-declaration
3
590 "Indentation of declarations with respect to containing block.
591 Set to 0 to get them list right under containing block."
592 :group
'verilog-mode-indent
594 (put 'verilog-indent-level-declaration
'safe-local-variable
'integerp
)
596 (defcustom verilog-indent-declaration-macros nil
597 "How to treat macro expansions in a declaration.
602 If non nil, treat as:
606 :group
'verilog-mode-indent
608 (put 'verilog-indent-declaration-macros
'safe-local-variable
'verilog-booleanp
)
610 (defcustom verilog-indent-lists t
611 "How to treat indenting items in a list.
612 If t (the default), indent as:
613 always @( posedge a or
617 always @( posedge a or
619 :group
'verilog-mode-indent
621 (put 'verilog-indent-lists
'safe-local-variable
'verilog-booleanp
)
623 (defcustom verilog-indent-level-behavioral
3
624 "Absolute indentation of first begin in a task or function block.
625 Set to 0 to get such code to start at the left side of the screen."
626 :group
'verilog-mode-indent
628 (put 'verilog-indent-level-behavioral
'safe-local-variable
'integerp
)
630 (defcustom verilog-indent-level-directive
1
631 "Indentation to add to each level of \\=`ifdef declarations.
632 Set to 0 to have all directives start at the left side of the screen."
633 :group
'verilog-mode-indent
635 (put 'verilog-indent-level-directive
'safe-local-variable
'integerp
)
637 (defcustom verilog-cexp-indent
2
638 "Indentation of Verilog statements split across lines."
639 :group
'verilog-mode-indent
641 (put 'verilog-cexp-indent
'safe-local-variable
'integerp
)
643 (defcustom verilog-case-indent
2
644 "Indentation for case statements."
645 :group
'verilog-mode-indent
647 (put 'verilog-case-indent
'safe-local-variable
'integerp
)
649 (defcustom verilog-auto-newline t
650 "Non-nil means automatically newline after semicolons."
651 :group
'verilog-mode-indent
653 (put 'verilog-auto-newline
'safe-local-variable
'verilog-booleanp
)
655 (defcustom verilog-auto-indent-on-newline t
656 "Non-nil means automatically indent line after newline."
657 :group
'verilog-mode-indent
659 (put 'verilog-auto-indent-on-newline
'safe-local-variable
'verilog-booleanp
)
661 (defcustom verilog-tab-always-indent t
662 "Non-nil means TAB should always re-indent the current line.
663 A nil value means TAB will only reindent when at the beginning of the line."
664 :group
'verilog-mode-indent
666 (put 'verilog-tab-always-indent
'safe-local-variable
'verilog-booleanp
)
668 (defcustom verilog-tab-to-comment nil
669 "Non-nil means TAB moves to the right hand column in preparation for a comment."
670 :group
'verilog-mode-actions
672 (put 'verilog-tab-to-comment
'safe-local-variable
'verilog-booleanp
)
674 (defcustom verilog-indent-begin-after-if t
675 "Non-nil means indent begin statements following if, else, while, etc.
676 Otherwise, line them up."
677 :group
'verilog-mode-indent
679 (put 'verilog-indent-begin-after-if
'safe-local-variable
'verilog-booleanp
)
681 (defcustom verilog-align-ifelse nil
682 "Non-nil means align `else' under matching `if'.
683 Otherwise else is lined up with first character on line holding matching if."
684 :group
'verilog-mode-indent
686 (put 'verilog-align-ifelse
'safe-local-variable
'verilog-booleanp
)
688 (defcustom verilog-minimum-comment-distance
10
689 "Minimum distance (in lines) between begin and end required before a comment.
690 Setting this variable to zero results in every end acquiring a comment; the
691 default avoids too many redundant comments in tight quarters."
692 :group
'verilog-mode-indent
694 (put 'verilog-minimum-comment-distance
'safe-local-variable
'integerp
)
696 (defcustom verilog-highlight-p1800-keywords nil
697 "Non-nil means highlight words newly reserved by IEEE-1800.
698 These will appear in `verilog-font-lock-p1800-face' in order to gently
699 suggest changing where these words are used as variables to something else.
700 A nil value means highlight these words as appropriate for the SystemVerilog
701 IEEE-1800 standard. Note that changing this will require restarting Emacs
702 to see the effect as font color choices are cached by Emacs."
703 :group
'verilog-mode-indent
705 (put 'verilog-highlight-p1800-keywords
'safe-local-variable
'verilog-booleanp
)
707 (defcustom verilog-highlight-grouping-keywords nil
708 "Non-nil means highlight grouping keywords more dramatically.
709 If false, these words are in the `font-lock-type-face'; if True
710 then they are in `verilog-font-lock-grouping-keywords-face'.
711 Some find that special highlighting on these grouping constructs
712 allow the structure of the code to be understood at a glance."
713 :group
'verilog-mode-indent
715 (put 'verilog-highlight-grouping-keywords
'safe-local-variable
'verilog-booleanp
)
717 (defcustom verilog-highlight-modules nil
718 "Non-nil means highlight module statements for `verilog-load-file-at-point'.
719 When true, mousing over module names will allow jumping to the
720 module definition. If false, this is not supported. Setting
721 this is experimental, and may lead to bad performance."
722 :group
'verilog-mode-indent
724 (put 'verilog-highlight-modules
'safe-local-variable
'verilog-booleanp
)
726 (defcustom verilog-highlight-includes t
727 "Non-nil means highlight module statements for `verilog-load-file-at-point'.
728 When true, mousing over include file names will allow jumping to the
729 file referenced. If false, this is not supported."
730 :group
'verilog-mode-indent
732 (put 'verilog-highlight-includes
'safe-local-variable
'verilog-booleanp
)
734 (defcustom verilog-auto-declare-nettype nil
735 "Non-nil specifies the data type to use with `verilog-auto-input' etc.
736 Set this to \"wire\" if the Verilog code uses \"\\=`default_nettype
737 none\". Note using \\=`default_nettype none isn't recommended practice; this
738 mode is experimental."
739 :version
"24.1" ; rev670
740 :group
'verilog-mode-actions
742 (put 'verilog-auto-declare-nettype
'safe-local-variable
`stringp
)
744 (defcustom verilog-auto-wire-type nil
745 "Non-nil specifies the data type to use with `verilog-auto-wire' etc.
746 Set this to \"logic\" for SystemVerilog code, or use `verilog-auto-logic'."
747 :version
"24.1" ; rev673
748 :group
'verilog-mode-actions
750 (put 'verilog-auto-wire-type
'safe-local-variable
`stringp
)
752 (defcustom verilog-auto-endcomments t
753 "Non-nil means insert a comment /* ... */ after 'end's.
754 The name of the function or case will be set between the braces."
755 :group
'verilog-mode-actions
757 (put 'verilog-auto-endcomments
'safe-local-variable
'verilog-booleanp
)
759 (defcustom verilog-auto-delete-trailing-whitespace nil
760 "Non-nil means to `delete-trailing-whitespace' in `verilog-auto'."
761 :version
"24.1" ; rev703
762 :group
'verilog-mode-actions
764 (put 'verilog-auto-delete-trailing-whitespace
'safe-local-variable
'verilog-booleanp
)
766 (defcustom verilog-auto-ignore-concat nil
767 "Non-nil means ignore signals in {...} concatenations for AUTOWIRE etc.
768 This will exclude signals referenced as pin connections in {...}
769 from AUTOWIRE, AUTOOUTPUT and friends. This flag should be set
770 for backward compatibility only and not set in new designs; it
771 may be removed in future versions."
772 :group
'verilog-mode-actions
774 (put 'verilog-auto-ignore-concat
'safe-local-variable
'verilog-booleanp
)
776 (defcustom verilog-auto-read-includes nil
777 "Non-nil means to automatically read includes before AUTOs.
778 This will do a `verilog-read-defines' and `verilog-read-includes' before
779 each AUTO expansion. This makes it easier to embed defines and includes,
780 but can result in very slow reading times if there are many or large
782 :group
'verilog-mode-actions
784 (put 'verilog-auto-read-includes
'safe-local-variable
'verilog-booleanp
)
786 (defcustom verilog-auto-save-policy nil
787 "Non-nil indicates action to take when saving a Verilog buffer with AUTOs.
788 A value of `force' will always do a \\[verilog-auto] automatically if
789 needed on every save. A value of `detect' will do \\[verilog-auto]
790 automatically when it thinks necessary. A value of `ask' will query the
791 user when it thinks updating is needed.
793 You should not rely on the 'ask or 'detect policies, they are safeguards
794 only. They do not detect when AUTOINSTs need to be updated because a
795 sub-module's port list has changed."
796 :group
'verilog-mode-actions
797 :type
'(choice (const nil
) (const ask
) (const detect
) (const force
)))
799 (defcustom verilog-auto-star-expand t
800 "Non-nil means to expand SystemVerilog .* instance ports.
801 They will be expanded in the same way as if there was an AUTOINST in the
802 instantiation. See also `verilog-auto-star' and `verilog-auto-star-save'."
803 :group
'verilog-mode-actions
805 (put 'verilog-auto-star-expand
'safe-local-variable
'verilog-booleanp
)
807 (defcustom verilog-auto-star-save nil
808 "Non-nil means save to disk SystemVerilog .* instance expansions.
809 A nil value indicates direct connections will be removed before saving.
810 Only meaningful to those created due to `verilog-auto-star-expand' being set.
812 Instead of setting this, you may want to use /*AUTOINST*/, which will
814 :group
'verilog-mode-actions
816 (put 'verilog-auto-star-save
'safe-local-variable
'verilog-booleanp
)
818 (defvar verilog-auto-update-tick nil
819 "Modification tick at which autos were last performed.")
821 (defvar verilog-auto-last-file-locals nil
822 "Text from file-local-variables during last evaluation.")
824 (defvar verilog-diff-function
'verilog-diff-report
825 "Function to run when `verilog-diff-auto' detects differences.
826 Function takes three arguments, the original buffer, the
827 difference buffer, and the point in original buffer with the
835 (defvar verilog-error-regexp-added nil
)
837 (defvar verilog-error-regexp-emacs-alist
840 "\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 3)
842 "([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 1 3)
844 ".*\\*[WE],[0-9A-Z]+\\(\[[0-9A-Z_,]+\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)" 2 3)
846 "[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 2)
848 "\\(WARNING\\|ERROR\\|INFO\\)[^:]*: \\([^,]+\\),\\s-+\\(line \\)?\\([0-9]+\\):" 2 4 )
851 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
852 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 2 5)
854 "\\(Error\\|Warning\\).*in file (\\([^ \t]+\\) at line *\\([0-9]+\\))" 2 3)
856 "\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 3)
858 "Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 2)
860 "\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 3)
862 "syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 2)
864 "%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4)
866 "^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 1 2)
868 "List of regexps for Verilog compilers.
869 See `compilation-error-regexp-alist' for the formatting. For Emacs 22+.")
871 (defvar verilog-error-regexp-xemacs-alist
872 ;; Emacs form is '((v-tool "re" 1 2) ...)
873 ;; XEmacs form is '(verilog ("re" 1 2) ...)
874 ;; So we can just map from Emacs to XEmacs
875 (cons 'verilog
(mapcar 'cdr verilog-error-regexp-emacs-alist
))
876 "List of regexps for Verilog compilers.
877 See `compilation-error-regexp-alist-alist' for the formatting. For XEmacs.")
879 (defvar verilog-error-font-lock-keywords
882 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t
)
883 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t
)
885 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 1 bold t
)
886 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 3 bold t
)
887 ;; verilog-IES (nc-verilog)
888 (".*\\*[WE],[0-9A-Z]+\\(\[[0-9A-Z_,]+\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)|" 2 bold t
)
889 (".*\\*[WE],[0-9A-Z]+\\(\[[0-9A-Z_,]+\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)|" 3 bold t
)
890 ;; verilog-surefire-1
891 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 bold t
)
892 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 2 bold t
)
893 ;; verilog-surefire-2
894 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 2 bold t
)
895 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 3 bold t
)
898 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
899 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t
)
901 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
902 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t
)
904 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 bold t
)
905 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 3 bold t
)
907 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t
)
908 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t
)
910 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t
)
911 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 3 bold t
)
913 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 bold t
)
914 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t
)
916 (".*%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 bold t
)
917 (".*%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 4 bold t
)
919 ("^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 1 bold t
)
920 ("^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 2 bold t
)
922 "Keywords to also highlight in Verilog *compilation* buffers.
923 Only used in XEmacs; GNU Emacs uses `verilog-error-regexp-emacs-alist'.")
925 (defcustom verilog-library-flags
'("")
926 "List of standard Verilog arguments to use for /*AUTOINST*/.
927 These arguments are used to find files for `verilog-auto', and match
928 the flags accepted by a standard Verilog-XL simulator.
930 -f filename Reads more `verilog-library-flags' from the filename.
931 +incdir+dir Adds the directory to `verilog-library-directories'.
932 -Idir Adds the directory to `verilog-library-directories'.
933 -y dir Adds the directory to `verilog-library-directories'.
934 +libext+.v Adds the extensions to `verilog-library-extensions'.
935 -v filename Adds the filename to `verilog-library-files'.
937 filename Adds the filename to `verilog-library-files'.
938 This is not recommended, -v is a better choice.
940 You might want these defined in each file; put at the *END* of your file
944 // verilog-library-flags:(\"-y dir -y otherdir\")
947 Verilog-mode attempts to detect changes to this local variable, but they
948 are only insured to be correct when the file is first visited. Thus if you
949 have problems, use \\[find-alternate-file] RET to have these take effect.
951 See also the variables mentioned above."
952 :group
'verilog-mode-auto
953 :type
'(repeat string
))
954 (put 'verilog-library-flags
'safe-local-variable
'listp
)
956 (defcustom verilog-library-directories
'(".")
957 "List of directories when looking for files for /*AUTOINST*/.
958 The directory may be relative to the current file, or absolute.
959 Environment variables are also expanded in the directory names.
960 Having at least the current directory is a good idea.
962 You might want these defined in each file; put at the *END* of your file
966 // verilog-library-directories:(\".\" \"subdir\" \"subdir2\")
969 Verilog-mode attempts to detect changes to this local variable, but they
970 are only insured to be correct when the file is first visited. Thus if you
971 have problems, use \\[find-alternate-file] RET to have these take effect.
973 See also `verilog-library-flags', `verilog-library-files'
974 and `verilog-library-extensions'."
975 :group
'verilog-mode-auto
976 :type
'(repeat file
))
977 (put 'verilog-library-directories
'safe-local-variable
'listp
)
979 (defcustom verilog-library-files
'()
980 "List of files to search for modules.
981 AUTOINST will use this when it needs to resolve a module name.
982 This is a complete path, usually to a technology file with many standard
985 You might want these defined in each file; put at the *END* of your file
989 // verilog-library-files:(\"/some/path/technology.v\" \"/some/path/tech2.v\")
992 Verilog-mode attempts to detect changes to this local variable, but they
993 are only insured to be correct when the file is first visited. Thus if you
994 have problems, use \\[find-alternate-file] RET to have these take effect.
996 See also `verilog-library-flags', `verilog-library-directories'."
997 :group
'verilog-mode-auto
998 :type
'(repeat directory
))
999 (put 'verilog-library-files
'safe-local-variable
'listp
)
1001 (defcustom verilog-library-extensions
'(".v" ".sv")
1002 "List of extensions to use when looking for files for /*AUTOINST*/.
1003 See also `verilog-library-flags', `verilog-library-directories'."
1004 :type
'(repeat string
)
1005 :group
'verilog-mode-auto
)
1006 (put 'verilog-library-extensions
'safe-local-variable
'listp
)
1008 (defcustom verilog-active-low-regexp nil
1009 "If true, treat signals matching this regexp as active low.
1010 This is used for AUTORESET and AUTOTIEOFF. For proper behavior,
1011 you will probably also need `verilog-auto-reset-widths' set."
1012 :group
'verilog-mode-auto
1013 :type
'(choice (const nil
) regexp
))
1014 (put 'verilog-active-low-regexp
'safe-local-variable
'stringp
)
1016 (defcustom verilog-auto-sense-include-inputs nil
1017 "Non-nil means AUTOSENSE should include all inputs.
1018 If nil, only inputs that are NOT output signals in the same block are
1020 :group
'verilog-mode-auto
1022 (put 'verilog-auto-sense-include-inputs
'safe-local-variable
'verilog-booleanp
)
1024 (defcustom verilog-auto-sense-defines-constant nil
1025 "Non-nil means AUTOSENSE should assume all defines represent constants.
1026 When true, the defines will not be included in sensitivity lists. To
1027 maintain compatibility with other sites, this should be set at the bottom
1028 of each Verilog file that requires it, rather than being set globally."
1029 :group
'verilog-mode-auto
1031 (put 'verilog-auto-sense-defines-constant
'safe-local-variable
'verilog-booleanp
)
1033 (defcustom verilog-auto-reset-blocking-in-non t
1034 "Non-nil means AUTORESET will reset blocking statements.
1035 When true, AUTORESET will reset in blocking statements those
1036 signals which were assigned with blocking assignments (=) even in
1037 a block with non-blocking assignments (<=).
1039 If nil, all blocking assigned signals are ignored when any
1040 non-blocking assignment is in the AUTORESET block. This allows
1041 blocking assignments to be used for temporary values and not have
1042 those temporaries reset. See example in `verilog-auto-reset'."
1043 :version
"24.1" ; rev718
1045 :group
'verilog-mode-auto
)
1046 (put 'verilog-auto-reset-blocking-in-non
'safe-local-variable
'verilog-booleanp
)
1048 (defcustom verilog-auto-reset-widths t
1049 "True means AUTORESET should determine the width of signals.
1050 This is then used to set the width of the zero (32'h0 for example). This
1051 is required by some lint tools that aren't smart enough to ignore widths of
1052 the constant zero. This may result in ugly code when parameters determine
1053 the MSB or LSB of a signal inside an AUTORESET.
1055 If nil, AUTORESET uses \"0\" as the constant.
1057 If `unbased', AUTORESET used the unbased unsized literal \"'0\"
1058 as the constant. This setting is strongly recommended for
1059 SystemVerilog designs."
1061 :group
'verilog-mode-auto
)
1062 (put 'verilog-auto-reset-widths
'safe-local-variable
1063 '(lambda (x) (memq x
'(nil t unbased
))))
1065 (defcustom verilog-assignment-delay
""
1066 "Text used for delays in delayed assignments. Add a trailing space if set."
1067 :group
'verilog-mode-auto
1069 (put 'verilog-assignment-delay
'safe-local-variable
'stringp
)
1071 (defcustom verilog-auto-arg-format
'packed
1072 "Formatting to use for AUTOARG signal names.
1073 If `packed', then as many inputs and outputs that fit within
1074 `fill-column' will be put onto one line.
1076 If `single', then a single input or output will be put onto each
1079 :type
'(radio (const :tag
"Line up Assignments and Declarations" packed
)
1080 (const :tag
"Line up Assignment statements" single
))
1081 :group
'verilog-mode-auto
)
1082 (put 'verilog-auto-arg-format
'safe-local-variable
1083 '(lambda (x) (memq x
'(packed single
))))
1085 (defcustom verilog-auto-arg-sort nil
1086 "Non-nil means AUTOARG signal names will be sorted, not in declaration order.
1087 Declaration order is advantageous with order based instantiations
1088 and is the default for backward compatibility. Sorted order
1089 reduces changes when declarations are moved around in a file, and
1090 it's bad practice to rely on order based instantiations anyhow.
1092 See also `verilog-auto-inst-sort'."
1093 :group
'verilog-mode-auto
1095 (put 'verilog-auto-arg-sort
'safe-local-variable
'verilog-booleanp
)
1097 (defcustom verilog-auto-inst-dot-name nil
1098 "Non-nil means when creating ports with AUTOINST, use .name syntax.
1099 This will use \".port\" instead of \".port(port)\" when possible.
1100 This is only legal in SystemVerilog files, and will confuse older
1101 simulators. Setting `verilog-auto-inst-vector' to nil may also
1102 be desirable to increase how often .name will be used."
1103 :group
'verilog-mode-auto
1105 (put 'verilog-auto-inst-dot-name
'safe-local-variable
'verilog-booleanp
)
1107 (defcustom verilog-auto-inst-param-value nil
1108 "Non-nil means AUTOINST will replace parameters with the parameter value.
1109 If nil, leave parameters as symbolic names.
1111 Parameters must be in Verilog 2001 format #(...), and if a parameter is not
1112 listed as such there (as when the default value is acceptable), it will not
1113 be replaced, and will remain symbolic.
1115 For example, imagine a submodule uses parameters to declare the size of its
1116 inputs. This is then used by an upper module:
1118 module InstModule (o,i);
1120 input [WIDTH-1:0] i;
1130 Note even though PARAM=10, the AUTOINST has left the parameter as a
1131 symbolic name. If `verilog-auto-inst-param-value' is set, this will
1140 :group
'verilog-mode-auto
1142 (put 'verilog-auto-inst-param-value
'safe-local-variable
'verilog-booleanp
)
1144 (defcustom verilog-auto-inst-sort nil
1145 "Non-nil means AUTOINST signals will be sorted, not in declaration order.
1146 Also affects AUTOINSTPARAM. Declaration order is the default for
1147 backward compatibility, and as some teams prefer signals that are
1148 declared together to remain together. Sorted order reduces
1149 changes when declarations are moved around in a file.
1151 See also `verilog-auto-arg-sort'."
1152 :version
"24.1" ; rev688
1153 :group
'verilog-mode-auto
1155 (put 'verilog-auto-inst-sort
'safe-local-variable
'verilog-booleanp
)
1157 (defcustom verilog-auto-inst-vector t
1158 "Non-nil means when creating default ports with AUTOINST, use bus subscripts.
1159 If nil, skip the subscript when it matches the entire bus as declared in
1160 the module (AUTOWIRE signals always are subscripted, you must manually
1161 declare the wire to have the subscripts removed.) Setting this to nil may
1162 speed up some simulators, but is less general and harder to read, so avoid."
1163 :group
'verilog-mode-auto
1165 (put 'verilog-auto-inst-vector
'safe-local-variable
'verilog-booleanp
)
1167 (defcustom verilog-auto-inst-template-numbers nil
1168 "If true, when creating templated ports with AUTOINST, add a comment.
1170 If t, the comment will add the line number of the template that
1171 was used for that port declaration. This setting is suggested
1172 only for debugging use, as regular use may cause a large numbers
1175 If `lhs', the comment will show the left hand side of the
1176 AUTO_TEMPLATE rule that is matched. This is less precise than
1177 numbering (t) when multiple rules have the same pin name, but
1178 won't merge conflict."
1179 :group
'verilog-mode-auto
1180 :type
'(choice (const nil
) (const t
) (const lhs
)))
1181 (put 'verilog-auto-inst-template-numbers
'safe-local-variable
1182 '(lambda (x) (memq x
'(nil t lhs
))))
1184 (defcustom verilog-auto-inst-column
40
1185 "Indent-to column number for net name part of AUTOINST created pin."
1186 :group
'verilog-mode-indent
1188 (put 'verilog-auto-inst-column
'safe-local-variable
'integerp
)
1190 (defcustom verilog-auto-inst-interfaced-ports nil
1191 "Non-nil means include interfaced ports in AUTOINST expansions."
1192 :version
"24.3" ; rev773, default change rev815
1193 :group
'verilog-mode-auto
1195 (put 'verilog-auto-inst-interfaced-ports
'safe-local-variable
'verilog-booleanp
)
1197 (defcustom verilog-auto-input-ignore-regexp nil
1198 "If non-nil, when creating AUTOINPUT, ignore signals matching this regexp.
1199 See the \\[verilog-faq] for examples on using this."
1200 :group
'verilog-mode-auto
1201 :type
'(choice (const nil
) regexp
))
1202 (put 'verilog-auto-input-ignore-regexp
'safe-local-variable
'stringp
)
1204 (defcustom verilog-auto-inout-ignore-regexp nil
1205 "If non-nil, when creating AUTOINOUT, ignore signals matching this regexp.
1206 See the \\[verilog-faq] for examples on using this."
1207 :group
'verilog-mode-auto
1208 :type
'(choice (const nil
) regexp
))
1209 (put 'verilog-auto-inout-ignore-regexp
'safe-local-variable
'stringp
)
1211 (defcustom verilog-auto-output-ignore-regexp nil
1212 "If non-nil, when creating AUTOOUTPUT, ignore signals matching this regexp.
1213 See the \\[verilog-faq] for examples on using this."
1214 :group
'verilog-mode-auto
1215 :type
'(choice (const nil
) regexp
))
1216 (put 'verilog-auto-output-ignore-regexp
'safe-local-variable
'stringp
)
1218 (defcustom verilog-auto-template-warn-unused nil
1219 "Non-nil means report warning if an AUTO_TEMPLATE line is not used.
1220 This feature is not supported before Emacs 21.1 or XEmacs 21.4."
1221 :version
"24.3" ; rev787
1222 :group
'verilog-mode-auto
1224 (put 'verilog-auto-template-warn-unused
'safe-local-variable
'verilog-booleanp
)
1226 (defcustom verilog-auto-tieoff-declaration
"wire"
1227 "Data type used for the declaration for AUTOTIEOFF.
1228 If \"wire\" then create a wire, if \"assign\" create an
1229 assignment, else the data type for variable creation."
1230 :version
"24.1" ; rev713
1231 :group
'verilog-mode-auto
1233 (put 'verilog-auto-tieoff-declaration
'safe-local-variable
'stringp
)
1235 (defcustom verilog-auto-tieoff-ignore-regexp nil
1236 "If non-nil, when creating AUTOTIEOFF, ignore signals matching this regexp.
1237 See the \\[verilog-faq] for examples on using this."
1238 :group
'verilog-mode-auto
1239 :type
'(choice (const nil
) regexp
))
1240 (put 'verilog-auto-tieoff-ignore-regexp
'safe-local-variable
'stringp
)
1242 (defcustom verilog-auto-unused-ignore-regexp nil
1243 "If non-nil, when creating AUTOUNUSED, ignore signals matching this regexp.
1244 See the \\[verilog-faq] for examples on using this."
1245 :group
'verilog-mode-auto
1246 :type
'(choice (const nil
) regexp
))
1247 (put 'verilog-auto-unused-ignore-regexp
'safe-local-variable
'stringp
)
1249 (defcustom verilog-case-fold t
1250 "Non-nil means `verilog-mode' regexps should ignore case.
1251 This variable is t for backward compatibility; nil is suggested."
1253 :group
'verilog-mode
1255 (put 'verilog-case-fold
'safe-local-variable
'verilog-booleanp
)
1257 (defcustom verilog-typedef-regexp nil
1258 "If non-nil, regular expression that matches Verilog-2001 typedef names.
1259 For example, \"_t$\" matches typedefs named with _t, as in the C language.
1260 See also `verilog-case-fold'."
1261 :group
'verilog-mode-auto
1262 :type
'(choice (const nil
) regexp
))
1263 (put 'verilog-typedef-regexp
'safe-local-variable
'stringp
)
1265 (defcustom verilog-mode-hook
'verilog-set-compile-command
1266 "Hook run after Verilog mode is loaded."
1268 :group
'verilog-mode
)
1270 (defcustom verilog-auto-hook nil
1271 "Hook run after `verilog-mode' updates AUTOs."
1272 :group
'verilog-mode-auto
1275 (defcustom verilog-before-auto-hook nil
1276 "Hook run before `verilog-mode' updates AUTOs."
1277 :group
'verilog-mode-auto
1280 (defcustom verilog-delete-auto-hook nil
1281 "Hook run after `verilog-mode' deletes AUTOs."
1282 :group
'verilog-mode-auto
1285 (defcustom verilog-before-delete-auto-hook nil
1286 "Hook run before `verilog-mode' deletes AUTOs."
1287 :group
'verilog-mode-auto
1290 (defcustom verilog-getopt-flags-hook nil
1291 "Hook run after `verilog-getopt-flags' determines the Verilog option lists."
1292 :group
'verilog-mode-auto
1295 (defcustom verilog-before-getopt-flags-hook nil
1296 "Hook run before `verilog-getopt-flags' determines the Verilog option lists."
1297 :group
'verilog-mode-auto
1300 (defcustom verilog-before-save-font-hook nil
1301 "Hook run before `verilog-save-font-mods' removes highlighting."
1302 :version
"24.3" ; rev735
1303 :group
'verilog-mode-auto
1306 (defcustom verilog-after-save-font-hook nil
1307 "Hook run after `verilog-save-font-mods' restores highlighting."
1308 :version
"24.3" ; rev735
1309 :group
'verilog-mode-auto
1312 (defvar verilog-imenu-generic-expression
1313 '((nil "^\\s-*\\(\\(m\\(odule\\|acromodule\\)\\)\\|primitive\\)\\s-+\\([a-zA-Z0-9_.:]+\\)" 4)
1314 ("*Vars*" "^\\s-*\\(reg\\|wire\\)\\s-+\\(\\|\\[[^]]+\\]\\s-+\\)\\([A-Za-z0-9_]+\\)" 3))
1315 "Imenu expression for Verilog mode. See `imenu-generic-expression'.")
1318 ;; provide a verilog-header function.
1319 ;; Customization variables:
1321 (defvar verilog-date-scientific-format nil
1322 "If non-nil, dates are written in scientific format (e.g. 1997/09/17).
1323 If nil, in European format (e.g. 17.09.1997). The brain-dead American
1324 format (e.g. 09/17/1997) is not supported.")
1326 (defvar verilog-company nil
1327 "Default name of Company for Verilog header.
1328 If set will become buffer local.")
1329 (make-variable-buffer-local 'verilog-company
)
1331 (defvar verilog-project nil
1332 "Default name of Project for Verilog header.
1333 If set will become buffer local.")
1334 (make-variable-buffer-local 'verilog-project
)
1336 ;;; Keymap and Menu:
1339 (defvar verilog-mode-map
1340 (let ((map (make-sparse-keymap)))
1341 (define-key map
";" 'electric-verilog-semi
)
1342 (define-key map
[(control 59)] 'electric-verilog-semi-with-comment
)
1343 (define-key map
":" 'electric-verilog-colon
)
1344 ;;(define-key map "=" 'electric-verilog-equal)
1345 (define-key map
"`" 'electric-verilog-tick
)
1346 (define-key map
"\t" 'electric-verilog-tab
)
1347 (define-key map
"\r" 'electric-verilog-terminate-line
)
1348 ;; backspace/delete key bindings
1349 (define-key map
[backspace] 'backward-delete-char-untabify)
1350 (unless (boundp 'delete-key-deletes-forward) ; XEmacs variable
1351 (define-key map [delete] 'delete-char)
1352 (define-key map [(meta delete)] 'kill-word))
1353 (define-key map "\M-\C-b" 'electric-verilog-backward-sexp)
1354 (define-key map "\M-\C-f" 'electric-verilog-forward-sexp)
1355 (define-key map "\M-\r" `electric-verilog-terminate-and-indent)
1356 (define-key map "\M-\t" 'verilog-complete-word)
1357 (define-key map "\M-?" 'verilog-show-completions)
1358 ;; Note \C-c and letter are reserved for users
1359 (define-key map "\C-c`" 'verilog-lint-off)
1360 (define-key map "\C-c*" 'verilog-delete-auto-star-implicit)
1361 (define-key map "\C-c?" 'verilog-diff-auto)
1362 (define-key map "\C-c\C-r" 'verilog-label-be)
1363 (define-key map "\C-c\C-i" 'verilog-pretty-declarations)
1364 (define-key map "\C-c=" 'verilog-pretty-expr)
1365 (define-key map "\C-c\C-b" 'verilog-submit-bug-report)
1366 (define-key map "\M-*" 'verilog-star-comment)
1367 (define-key map "\C-c\C-c" 'verilog-comment-region)
1368 (define-key map "\C-c\C-u" 'verilog-uncomment-region)
1369 (when (featurep 'xemacs)
1370 (define-key map [(meta control h)] 'verilog-mark-defun)
1371 (define-key map "\M-\C-a" 'verilog-beg-of-defun)
1372 (define-key map "\M-\C-e" 'verilog-end-of-defun))
1373 (define-key map "\C-c\C-d" 'verilog-goto-defun)
1374 (define-key map "\C-c\C-k" 'verilog-delete-auto)
1375 (define-key map "\C-c\C-a" 'verilog-auto)
1376 (define-key map "\C-c\C-s" 'verilog-auto-save-compile)
1377 (define-key map "\C-c\C-p" 'verilog-preprocess)
1378 (define-key map "\C-c\C-z" 'verilog-inject-auto)
1379 (define-key map "\C-c\C-e" 'verilog-expand-vector)
1380 (define-key map "\C-c\C-h" 'verilog-header)
1382 "Keymap used in Verilog mode.")
1386 verilog-menu verilog-mode-map "Menu for Verilog mode"
1387 (verilog-easy-menu-filter
1389 ("Choose Compilation Action"
1392 (setq verilog-tool nil)
1393 (verilog-set-compile-command))
1395 :selected (equal verilog-tool nil)
1396 :help "When invoking compilation, use compile-command"]
1399 (setq verilog-tool 'verilog-linter)
1400 (verilog-set-compile-command))
1402 :selected (equal verilog-tool `verilog-linter)
1403 :help "When invoking compilation, use lint checker"]
1406 (setq verilog-tool 'verilog-coverage)
1407 (verilog-set-compile-command))
1409 :selected (equal verilog-tool `verilog-coverage)
1410 :help "When invoking compilation, annotate for coverage"]
1413 (setq verilog-tool 'verilog-simulator)
1414 (verilog-set-compile-command))
1416 :selected (equal verilog-tool `verilog-simulator)
1417 :help "When invoking compilation, interpret Verilog source"]
1420 (setq verilog-tool 'verilog-compiler)
1421 (verilog-set-compile-command))
1423 :selected (equal verilog-tool `verilog-compiler)
1424 :help "When invoking compilation, compile Verilog source"]
1427 (setq verilog-tool 'verilog-preprocessor)
1428 (verilog-set-compile-command))
1430 :selected (equal verilog-tool `verilog-preprocessor)
1431 :help "When invoking compilation, preprocess Verilog source, see also `verilog-preprocess'"]
1434 ["Beginning of function" verilog-beg-of-defun
1436 :help "Move backward to the beginning of the current function or procedure"]
1437 ["End of function" verilog-end-of-defun
1439 :help "Move forward to the end of the current function or procedure"]
1440 ["Mark function" verilog-mark-defun
1442 :help "Mark the current Verilog function or procedure"]
1443 ["Goto function/module" verilog-goto-defun
1444 :help "Move to specified Verilog module/task/function"]
1445 ["Move to beginning of block" electric-verilog-backward-sexp
1446 :help "Move backward over one balanced expression"]
1447 ["Move to end of block" electric-verilog-forward-sexp
1448 :help "Move forward over one balanced expression"]
1451 ["Comment Region" verilog-comment-region
1452 :help "Put marked area into a comment"]
1453 ["UnComment Region" verilog-uncomment-region
1454 :help "Uncomment an area commented with Comment Region"]
1455 ["Multi-line comment insert" verilog-star-comment
1456 :help "Insert Verilog /* */ comment at point"]
1457 ["Lint error to comment" verilog-lint-off
1458 :help "Convert a Verilog linter warning line into a disable statement"]
1462 :help "Perform compilation-action (above) on the current buffer"]
1463 ["AUTO, Save, Compile" verilog-auto-save-compile
1464 :help "Recompute AUTOs, save buffer, and compile"]
1465 ["Next Compile Error" next-error
1466 :help "Visit next compilation error message and corresponding source code"]
1467 ["Ignore Lint Warning at point" verilog-lint-off
1468 :help "Convert a Verilog linter warning line into a disable statement"]
1470 ["Line up declarations around point" verilog-pretty-declarations
1471 :help "Line up declarations around point"]
1472 ["Line up equations around point" verilog-pretty-expr
1473 :help "Line up expressions around point"]
1474 ["Redo/insert comments on every end" verilog-label-be
1475 :help "Label matching begin ... end statements"]
1476 ["Expand [x:y] vector line" verilog-expand-vector
1477 :help "Take a signal vector on the current line and expand it to multiple lines"]
1478 ["Insert begin-end block" verilog-insert-block
1479 :help "Insert begin ... end"]
1480 ["Complete word" verilog-complete-word
1481 :help "Complete word at point"]
1483 ["Recompute AUTOs" verilog-auto
1484 :help "Expand AUTO meta-comment statements"]
1485 ["Kill AUTOs" verilog-delete-auto
1486 :help "Remove AUTO expansions"]
1487 ["Diff AUTOs" verilog-diff-auto
1488 :help "Show differences in AUTO expansions"]
1489 ["Inject AUTOs" verilog-inject-auto
1490 :help "Inject AUTOs into legacy non-AUTO buffer"]
1492 ["AUTO General" (describe-function 'verilog-auto)
1493 :help "Help introduction on AUTOs"]
1494 ["AUTO Library Flags" (describe-variable 'verilog-library-flags)
1495 :help "Help on verilog-library-flags"]
1496 ["AUTO Library Path" (describe-variable 'verilog-library-directories)
1497 :help "Help on verilog-library-directories"]
1498 ["AUTO Library Files" (describe-variable 'verilog-library-files)
1499 :help "Help on verilog-library-files"]
1500 ["AUTO Library Extensions" (describe-variable 'verilog-library-extensions)
1501 :help "Help on verilog-library-extensions"]
1502 ["AUTO `define Reading" (describe-function 'verilog-read-defines)
1503 :help "Help on reading `defines"]
1504 ["AUTO `include Reading" (describe-function 'verilog-read-includes)
1505 :help "Help on parsing `includes"]
1506 ["AUTOARG" (describe-function 'verilog-auto-arg)
1507 :help "Help on AUTOARG - declaring module port list"]
1508 ["AUTOASCIIENUM" (describe-function 'verilog-auto-ascii-enum)
1509 :help "Help on AUTOASCIIENUM - creating ASCII for enumerations"]
1510 ["AUTOASSIGNMODPORT" (describe-function 'verilog-auto-assign-modport)
1511 :help "Help on AUTOASSIGNMODPORT - creating assignments to/from modports"]
1512 ["AUTOINOUT" (describe-function 'verilog-auto-inout)
1513 :help "Help on AUTOINOUT - adding inouts from cells"]
1514 ["AUTOINOUTCOMP" (describe-function 'verilog-auto-inout-comp)
1515 :help "Help on AUTOINOUTCOMP - copying complemented i/o from another file"]
1516 ["AUTOINOUTIN" (describe-function 'verilog-auto-inout-in)
1517 :help "Help on AUTOINOUTIN - copying i/o from another file as all inputs"]
1518 ["AUTOINOUTMODPORT" (describe-function 'verilog-auto-inout-modport)
1519 :help "Help on AUTOINOUTMODPORT - copying i/o from an interface modport"]
1520 ["AUTOINOUTMODULE" (describe-function 'verilog-auto-inout-module)
1521 :help "Help on AUTOINOUTMODULE - copying i/o from another file"]
1522 ["AUTOINOUTPARAM" (describe-function 'verilog-auto-inout-param)
1523 :help "Help on AUTOINOUTPARAM - copying parameters from another file"]
1524 ["AUTOINPUT" (describe-function 'verilog-auto-input)
1525 :help "Help on AUTOINPUT - adding inputs from cells"]
1526 ["AUTOINSERTLISP" (describe-function 'verilog-auto-insert-lisp)
1527 :help "Help on AUTOINSERTLISP - insert text from a lisp function"]
1528 ["AUTOINSERTLAST" (describe-function 'verilog-auto-insert-last)
1529 :help "Help on AUTOINSERTLISPLAST - insert text from a lisp function"]
1530 ["AUTOINST" (describe-function 'verilog-auto-inst)
1531 :help "Help on AUTOINST - adding pins for cells"]
1532 ["AUTOINST (.*)" (describe-function 'verilog-auto-star)
1533 :help "Help on expanding Verilog-2001 .* pins"]
1534 ["AUTOINSTPARAM" (describe-function 'verilog-auto-inst-param)
1535 :help "Help on AUTOINSTPARAM - adding parameter pins to cells"]
1536 ["AUTOLOGIC" (describe-function 'verilog-auto-logic)
1537 :help "Help on AUTOLOGIC - declaring logic signals"]
1538 ["AUTOOUTPUT" (describe-function 'verilog-auto-output)
1539 :help "Help on AUTOOUTPUT - adding outputs from cells"]
1540 ["AUTOOUTPUTEVERY" (describe-function 'verilog-auto-output-every)
1541 :help "Help on AUTOOUTPUTEVERY - adding outputs of all signals"]
1542 ["AUTOREG" (describe-function 'verilog-auto-reg)
1543 :help "Help on AUTOREG - declaring registers for non-wires"]
1544 ["AUTOREGINPUT" (describe-function 'verilog-auto-reg-input)
1545 :help "Help on AUTOREGINPUT - declaring inputs for non-wires"]
1546 ["AUTORESET" (describe-function 'verilog-auto-reset)
1547 :help "Help on AUTORESET - resetting always blocks"]
1548 ["AUTOSENSE or AS" (describe-function 'verilog-auto-sense)
1549 :help "Help on AUTOSENSE - sensitivity lists for always blocks"]
1550 ["AUTOTIEOFF" (describe-function 'verilog-auto-tieoff)
1551 :help "Help on AUTOTIEOFF - tying off unused outputs"]
1552 ["AUTOUNDEF" (describe-function 'verilog-auto-undef)
1553 :help "Help on AUTOUNDEF - undefine all local defines"]
1554 ["AUTOUNUSED" (describe-function 'verilog-auto-unused)
1555 :help "Help on AUTOUNUSED - terminating unused inputs"]
1556 ["AUTOWIRE" (describe-function 'verilog-auto-wire)
1557 :help "Help on AUTOWIRE - declaring wires for cells"]
1560 ["Submit bug report" verilog-submit-bug-report
1561 :help "Submit via mail a bug report on verilog-mode.el"]
1562 ["Version and FAQ" verilog-faq
1563 :help "Show the current version, and where to get the FAQ etc"]
1564 ["Customize Verilog Mode..." verilog-customize
1565 :help "Customize variables and other settings used by Verilog-Mode"]
1566 ["Customize Verilog Fonts & Colors" verilog-font-customize
1567 :help "Customize fonts used by Verilog-Mode."])))
1570 verilog-stmt-menu verilog-mode-map "Menu for statement templates in Verilog."
1571 (verilog-easy-menu-filter
1573 ["Header" verilog-sk-header
1574 :help "Insert a header block at the top of file"]
1575 ["Comment" verilog-sk-comment
1576 :help "Insert a comment block"]
1578 ["Module" verilog-sk-module
1579 :help "Insert a module .. (/*AUTOARG*/);.. endmodule block"]
1580 ["OVM Class" verilog-sk-ovm-class
1581 :help "Insert an OVM class block"]
1582 ["UVM Object" verilog-sk-uvm-object
1583 :help "Insert an UVM object block"]
1584 ["UVM Component" verilog-sk-uvm-component
1585 :help "Insert an UVM component block"]
1586 ["Primitive" verilog-sk-primitive
1587 :help "Insert a primitive .. (.. );.. endprimitive block"]
1589 ["Input" verilog-sk-input
1590 :help "Insert an input declaration"]
1591 ["Output" verilog-sk-output
1592 :help "Insert an output declaration"]
1593 ["Inout" verilog-sk-inout
1594 :help "Insert an inout declaration"]
1595 ["Wire" verilog-sk-wire
1596 :help "Insert a wire declaration"]
1597 ["Reg" verilog-sk-reg
1598 :help "Insert a register declaration"]
1599 ["Define thing under point as a register" verilog-sk-define-signal
1600 :help "Define signal under point as a register at the top of the module"]
1602 ["Initial" verilog-sk-initial
1603 :help "Insert an initial begin .. end block"]
1604 ["Always" verilog-sk-always
1605 :help "Insert an always @(AS) begin .. end block"]
1606 ["Function" verilog-sk-function
1607 :help "Insert a function .. begin .. end endfunction block"]
1608 ["Task" verilog-sk-task
1609 :help "Insert a task .. begin .. end endtask block"]
1610 ["Specify" verilog-sk-specify
1611 :help "Insert a specify .. endspecify block"]
1612 ["Generate" verilog-sk-generate
1613 :help "Insert a generate .. endgenerate block"]
1615 ["Begin" verilog-sk-begin
1616 :help "Insert a begin .. end block"]
1618 :help "Insert an if (..) begin .. end block"]
1619 ["(if) else" verilog-sk-else-if
1620 :help "Insert an else if (..) begin .. end block"]
1621 ["For" verilog-sk-for
1622 :help "Insert a for (...) begin .. end block"]
1623 ["While" verilog-sk-while
1624 :help "Insert a while (...) begin .. end block"]
1625 ["Fork" verilog-sk-fork
1626 :help "Insert a fork begin .. end .. join block"]
1627 ["Repeat" verilog-sk-repeat
1628 :help "Insert a repeat (..) begin .. end block"]
1629 ["Case" verilog-sk-case
1630 :help "Insert a case block, prompting for details"]
1631 ["Casex" verilog-sk-casex
1632 :help "Insert a casex (...) item: begin.. end endcase block"]
1633 ["Casez" verilog-sk-casez
1634 :help "Insert a casez (...) item: begin.. end endcase block"])))
1636 (defvar verilog-mode-abbrev-table nil
1637 "Abbrev table in use in Verilog-mode buffers.")
1639 (define-abbrev-table 'verilog-mode-abbrev-table ())
1640 (verilog-define-abbrev verilog-mode-abbrev-table "class" "" 'verilog-sk-ovm-class)
1641 (verilog-define-abbrev verilog-mode-abbrev-table "always" "" 'verilog-sk-always)
1642 (verilog-define-abbrev verilog-mode-abbrev-table "begin" nil `verilog-sk-begin)
1643 (verilog-define-abbrev verilog-mode-abbrev-table "case" "" `verilog-sk-case)
1644 (verilog-define-abbrev verilog-mode-abbrev-table "for" "" `verilog-sk-for)
1645 (verilog-define-abbrev verilog-mode-abbrev-table "generate" "" `verilog-sk-generate)
1646 (verilog-define-abbrev verilog-mode-abbrev-table "initial" "" `verilog-sk-initial)
1647 (verilog-define-abbrev verilog-mode-abbrev-table "fork" "" `verilog-sk-fork)
1648 (verilog-define-abbrev verilog-mode-abbrev-table "module" "" `verilog-sk-module)
1649 (verilog-define-abbrev verilog-mode-abbrev-table "primitive" "" `verilog-sk-primitive)
1650 (verilog-define-abbrev verilog-mode-abbrev-table "repeat" "" `verilog-sk-repeat)
1651 (verilog-define-abbrev verilog-mode-abbrev-table "specify" "" `verilog-sk-specify)
1652 (verilog-define-abbrev verilog-mode-abbrev-table "task" "" `verilog-sk-task)
1653 (verilog-define-abbrev verilog-mode-abbrev-table "while" "" `verilog-sk-while)
1654 (verilog-define-abbrev verilog-mode-abbrev-table "casex" "" `verilog-sk-casex)
1655 (verilog-define-abbrev verilog-mode-abbrev-table "casez" "" `verilog-sk-casez)
1656 (verilog-define-abbrev verilog-mode-abbrev-table "if" "" `verilog-sk-if)
1657 (verilog-define-abbrev verilog-mode-abbrev-table "else if" "" `verilog-sk-else-if)
1658 (verilog-define-abbrev verilog-mode-abbrev-table "assign" "" `verilog-sk-assign)
1659 (verilog-define-abbrev verilog-mode-abbrev-table "function" "" `verilog-sk-function)
1660 (verilog-define-abbrev verilog-mode-abbrev-table "input" "" `verilog-sk-input)
1661 (verilog-define-abbrev verilog-mode-abbrev-table "output" "" `verilog-sk-output)
1662 (verilog-define-abbrev verilog-mode-abbrev-table "inout" "" `verilog-sk-inout)
1663 (verilog-define-abbrev verilog-mode-abbrev-table "wire" "" `verilog-sk-wire)
1664 (verilog-define-abbrev verilog-mode-abbrev-table "reg" "" `verilog-sk-reg)
1670 (defsubst verilog-within-string ()
1671 (nth 3 (parse-partial-sexp (point-at-bol) (point))))
1673 (defsubst verilog-string-match-fold (regexp string &optional start)
1674 "Like `string-match', but use `verilog-case-fold'.
1675 Return index of start of first match for REGEXP in STRING, or nil.
1676 Matching ignores case if `verilog-case-fold' is non-nil.
1677 If third arg START is non-nil, start search at that index in STRING."
1678 (let ((case-fold-search verilog-case-fold))
1679 (string-match regexp string start)))
1681 (defsubst verilog-string-replace-matches (from-string to-string fixedcase literal string)
1682 "Replace occurrences of FROM-STRING with TO-STRING.
1683 FIXEDCASE and LITERAL as in `replace-match'. STRING is what to replace.
1684 The case (verilog-string-replace-matches \"o\" \"oo\" nil nil \"foobar\")
1685 will break, as the o's continuously replace. xa -> x works ok though."
1686 ;; Hopefully soon to an Emacs built-in
1687 ;; Also note \ in the replacement prevent multiple replacements; IE
1688 ;; (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil "wire@_@")
1689 ;; Gives "wire\([0-9]+\)_@" not "wire\([0-9]+\)_\([0-9]+\)"
1691 (while (string-match from-string string start)
1692 (setq string (replace-match to-string fixedcase literal string)
1693 start (min (length string) (+ (match-beginning 0) (length to-string)))))
1696 (defsubst verilog-string-remove-spaces (string)
1697 "Remove spaces surrounding STRING."
1699 (setq string (verilog-string-replace-matches "^\\s-+" "" nil nil string))
1700 (setq string (verilog-string-replace-matches "\\s-+$" "" nil nil string))
1703 (defsubst verilog-re-search-forward (REGEXP BOUND NOERROR)
1704 ;; checkdoc-params: (REGEXP BOUND NOERROR)
1705 "Like `re-search-forward', but skips over match in comments or strings."
1706 (let ((mdata '(nil nil))) ; So match-end will return nil if no matches found
1708 (re-search-forward REGEXP BOUND NOERROR)
1709 (setq mdata (match-data))
1710 (and (verilog-skip-forward-comment-or-string)
1712 (setq mdata '(nil nil))
1716 (store-match-data mdata)
1719 (defsubst verilog-re-search-backward (REGEXP BOUND NOERROR)
1720 ;; checkdoc-params: (REGEXP BOUND NOERROR)
1721 "Like `re-search-backward', but skips over match in comments or strings."
1722 (let ((mdata '(nil nil))) ; So match-end will return nil if no matches found
1724 (re-search-backward REGEXP BOUND NOERROR)
1725 (setq mdata (match-data))
1726 (and (verilog-skip-backward-comment-or-string)
1728 (setq mdata '(nil nil))
1732 (store-match-data mdata)
1735 (defsubst verilog-re-search-forward-quick (regexp bound noerror)
1736 "Like `verilog-re-search-forward', including use of REGEXP BOUND and NOERROR,
1737 but trashes match data and is faster for REGEXP that doesn't match often.
1738 This uses `verilog-scan' and text properties to ignore comments,
1739 so there may be a large up front penalty for the first search."
1741 (while (and (not pt)
1742 (re-search-forward regexp bound noerror))
1743 (if (verilog-inside-comment-or-string-p)
1744 (re-search-forward "[/\"\n]" nil t) ; Only way a comment or quote can end
1745 (setq pt (match-end 0))))
1748 (defsubst verilog-re-search-backward-quick (regexp bound noerror)
1749 ;; checkdoc-params: (REGEXP BOUND NOERROR)
1750 "Like `verilog-re-search-backward', including use of REGEXP BOUND and NOERROR,
1751 but trashes match data and is faster for REGEXP that doesn't match often.
1752 This uses `verilog-scan' and text properties to ignore comments,
1753 so there may be a large up front penalty for the first search."
1755 (while (and (not pt)
1756 (re-search-backward regexp bound noerror))
1757 (if (verilog-inside-comment-or-string-p)
1758 (re-search-backward "[/\"]" nil t) ; Only way a comment or quote can begin
1759 (setq pt (match-beginning 0))))
1762 (defsubst verilog-re-search-forward-substr (substr regexp bound noerror)
1763 "Like `re-search-forward', but first search for SUBSTR constant.
1764 Then searched for the normal REGEXP (which contains SUBSTR), with given
1765 BOUND and NOERROR. The REGEXP must fit within a single line.
1766 This speeds up complicated regexp matches."
1767 ;; Problem with overlap: search-forward BAR then FOOBARBAZ won't match.
1768 ;; thus require matches to be on one line, and use beginning-of-line.
1770 (while (and (not done)
1771 (search-forward substr bound noerror))
1774 (setq done (re-search-forward regexp (point-at-eol) noerror)))
1775 (unless (and (<= (match-beginning 0) (point))
1776 (>= (match-end 0) (point)))
1778 (when done (goto-char done))
1780 ;;(verilog-re-search-forward-substr "-end" "get-end-of" nil t) ; -end (test bait)
1782 (defsubst verilog-re-search-backward-substr (substr regexp bound noerror)
1783 "Like `re-search-backward', but first search for SUBSTR constant.
1784 Then searched for the normal REGEXP (which contains SUBSTR), with given
1785 BOUND and NOERROR. The REGEXP must fit within a single line.
1786 This speeds up complicated regexp matches."
1787 ;; Problem with overlap: search-backward BAR then FOOBARBAZ won't match.
1788 ;; thus require matches to be on one line, and use beginning-of-line.
1790 (while (and (not done)
1791 (search-backward substr bound noerror))
1794 (setq done (re-search-backward regexp (point-at-bol) noerror)))
1795 (unless (and (<= (match-beginning 0) (point))
1796 (>= (match-end 0) (point)))
1798 (when done (goto-char done))
1800 ;;(verilog-re-search-backward-substr "-end" "get-end-of" nil t) ; -end (test bait)
1802 (defun verilog-delete-trailing-whitespace ()
1803 "Delete trailing spaces or tabs, but not newlines nor linefeeds.
1804 Also add missing final newline.
1806 To call this from the command line, see \\[verilog-batch-diff-auto].
1808 To call on \\[verilog-auto], set `verilog-auto-delete-trailing-whitespace'."
1809 ;; Similar to `delete-trailing-whitespace' but that's not present in XEmacs
1811 (goto-char (point-min))
1812 (while (re-search-forward "[ \t]+$" nil t) ; Not syntactic WS as no formfeed
1813 (replace-match "" nil nil))
1814 (goto-char (point-max))
1815 (unless (bolp) (insert "\n"))))
1817 (defvar compile-command)
1818 (defvar create-lockfiles) ; Emacs 24
1820 ;; compilation program
1821 (defun verilog-set-compile-command ()
1822 "Function to compute shell command to compile Verilog.
1824 This reads `verilog-tool' and sets `compile-command'. This specifies the
1825 program that executes when you type \\[compile] or
1826 \\[verilog-auto-save-compile].
1828 By default `verilog-tool' uses a Makefile if one exists in the
1829 current directory. If not, it is set to the `verilog-linter',
1830 `verilog-compiler', `verilog-coverage', `verilog-preprocessor',
1831 or `verilog-simulator' variables, as selected with the Verilog ->
1832 \"Choose Compilation Action\" menu.
1834 You should set `verilog-tool' or the other variables to the path and
1835 arguments for your Verilog simulator. For example:
1838 \"(cd /tmp; surecov %s)\".
1840 In the former case, the path to the current buffer is concat'ed to the
1841 value of `verilog-tool'; in the later, the path to the current buffer is
1842 substituted for the %s.
1844 Where __FLAGS__ appears in the string `verilog-current-flags'
1845 will be substituted.
1847 Where __FILE__ appears in the string, the variable
1848 `buffer-file-name' of the current buffer, without the directory
1849 portion, will be substituted."
1852 ((or (file-exists-p "makefile") ;If there is a makefile, use it
1853 (file-exists-p "Makefile"))
1854 (set (make-local-variable 'compile-command) "make "))
1856 (set (make-local-variable 'compile-command)
1858 (if (string-match "%s" (eval verilog-tool))
1859 (format (eval verilog-tool) (or buffer-file-name ""))
1860 (concat (eval verilog-tool) " " (or buffer-file-name "")))
1862 (verilog-modify-compile-command))
1864 (defun verilog-expand-command (command)
1865 "Replace meta-information in COMMAND and return it.
1866 Where __FLAGS__ appears in the string `verilog-current-flags'
1867 will be substituted. Where __FILE__ appears in the string, the
1868 current buffer's file-name, without the directory portion, will
1870 (setq command (verilog-string-replace-matches
1871 ;; Note \\b only works if under verilog syntax table
1872 "\\b__FLAGS__\\b" (verilog-current-flags)
1874 (setq command (verilog-string-replace-matches
1875 "\\b__FILE__\\b" (file-name-nondirectory
1876 (or (buffer-file-name) ""))
1880 (defun verilog-modify-compile-command ()
1881 "Update `compile-command' using `verilog-expand-command'."
1883 (stringp compile-command)
1884 (string-match "\\b\\(__FLAGS__\\|__FILE__\\)\\b" compile-command))
1885 (set (make-local-variable 'compile-command)
1886 (verilog-expand-command compile-command))))
1888 (if (featurep 'xemacs)
1889 ;; Following code only gets called from compilation-mode-hook on XEmacs to add error handling.
1890 (defun verilog-error-regexp-add-xemacs ()
1891 "Teach XEmacs about verilog errors.
1892 Called by `compilation-mode-hook'. This allows \\[next-error] to
1895 (if (boundp 'compilation-error-regexp-systems-alist)
1897 (not (equal compilation-error-regexp-systems-list 'all))
1898 (not (member compilation-error-regexp-systems-list 'verilog)))
1899 (push 'verilog compilation-error-regexp-systems-list)))
1900 (if (boundp 'compilation-error-regexp-alist-alist)
1901 (if (not (assoc 'verilog compilation-error-regexp-alist-alist))
1902 (setcdr compilation-error-regexp-alist-alist
1903 (cons verilog-error-regexp-xemacs-alist
1904 (cdr compilation-error-regexp-alist-alist)))))
1905 (if (boundp 'compilation-font-lock-keywords)
1907 (set (make-local-variable 'compilation-font-lock-keywords)
1908 verilog-error-font-lock-keywords)
1909 (font-lock-set-defaults)))
1910 ;; Need to re-run compilation-error-regexp builder
1911 (if (fboundp 'compilation-build-compilation-error-regexp-alist)
1912 (compilation-build-compilation-error-regexp-alist))
1915 ;; Following code only gets called from compilation-mode-hook on Emacs to add error handling.
1916 (defun verilog-error-regexp-add-emacs ()
1917 "Tell Emacs compile that we are Verilog.
1918 Called by `compilation-mode-hook'. This allows \\[next-error] to
1921 (when (boundp 'compilation-error-regexp-alist-alist)
1922 (when (not (assoc 'verilog-xl-1 compilation-error-regexp-alist-alist))
1925 (push (car item) compilation-error-regexp-alist)
1926 (push item compilation-error-regexp-alist-alist))
1927 verilog-error-regexp-emacs-alist))))
1929 (if (featurep 'xemacs) (add-hook 'compilation-mode-hook 'verilog-error-regexp-add-xemacs))
1930 (if (featurep 'emacs) (add-hook 'compilation-mode-hook 'verilog-error-regexp-add-emacs))
1932 (defconst verilog-compiler-directives
1935 ;; compiler directives, from IEEE 1800-2012 section 22.1
1936 "`__FILE__" "`__LINE" "`begin_keywords" "`celldefine" "`default_nettype"
1937 "`define" "`else" "`elsif" "`end_keywords" "`endcelldefine" "`endif"
1938 "`ifdef" "`ifndef" "`include" "`line" "`nounconnected_drive" "`pragma"
1939 "`resetall" "`timescale" "`unconnected_drive" "`undef" "`undefineall"
1940 ;; compiler directives not covered by IEEE 1800
1941 "`case" "`default" "`endfor" "`endprotect" "`endswitch" "`endwhile" "`for"
1942 "`format" "`if" "`let" "`protect" "`switch" "`timescale" "`time_scale"
1945 "List of Verilog compiler directives.")
1947 (defconst verilog-directive-re
1948 (verilog-regexp-words verilog-compiler-directives))
1950 (defconst verilog-directive-re-1
1951 (concat "[ \t]*" verilog-directive-re))
1953 (defconst verilog-directive-begin
1954 "\\<`\\(for\\|i\\(f\\|fdef\\|fndef\\)\\|switch\\|while\\)\\>")
1956 (defconst verilog-directive-middle
1957 "\\<`\\(else\\|elsif\\|default\\|case\\)\\>")
1959 (defconst verilog-directive-end
1960 "`\\(endfor\\|endif\\|endswitch\\|endwhile\\)\\>")
1962 (defconst verilog-ovm-begin-re
1966 "`ovm_component_utils_begin"
1967 "`ovm_component_param_utils_begin"
1968 "`ovm_field_utils_begin"
1969 "`ovm_object_utils_begin"
1970 "`ovm_object_param_utils_begin"
1971 "`ovm_sequence_utils_begin"
1972 "`ovm_sequencer_utils_begin"
1975 (defconst verilog-ovm-end-re
1979 "`ovm_component_utils_end"
1980 "`ovm_field_utils_end"
1981 "`ovm_object_utils_end"
1982 "`ovm_sequence_utils_end"
1983 "`ovm_sequencer_utils_end"
1986 (defconst verilog-uvm-begin-re
1990 "`uvm_component_utils_begin"
1991 "`uvm_component_param_utils_begin"
1992 "`uvm_field_utils_begin"
1993 "`uvm_object_utils_begin"
1994 "`uvm_object_param_utils_begin"
1995 "`uvm_sequence_utils_begin"
1996 "`uvm_sequencer_utils_begin"
1999 (defconst verilog-uvm-end-re
2003 "`uvm_component_utils_end"
2004 "`uvm_field_utils_end"
2005 "`uvm_object_utils_end"
2006 "`uvm_sequence_utils_end"
2007 "`uvm_sequencer_utils_end"
2010 (defconst verilog-vmm-begin-re
2014 "`vmm_data_member_begin"
2015 "`vmm_env_member_begin"
2016 "`vmm_scenario_member_begin"
2017 "`vmm_subenv_member_begin"
2018 "`vmm_xactor_member_begin"
2021 (defconst verilog-vmm-end-re
2025 "`vmm_data_member_end"
2026 "`vmm_env_member_end"
2027 "`vmm_scenario_member_end"
2028 "`vmm_subenv_member_end"
2029 "`vmm_xactor_member_end"
2032 (defconst verilog-vmm-statement-re
2036 "`vmm_\\(data\\|env\\|scenario\\|subenv\\|xactor\\)_member_\\(scalar\\|string\\|enum\\|vmm_data\\|channel\\|xactor\\|subenv\\|user_defined\\)\\(_array\\)?"
2037 ;; "`vmm_xactor_member_enum_array"
2038 ;; "`vmm_xactor_member_scalar_array"
2039 ;; "`vmm_xactor_member_scalar"
2042 (defconst verilog-ovm-statement-re
2051 "`ovm_analysis_imp_decl"
2052 "`ovm_blocking_get_imp_decl"
2053 "`ovm_blocking_get_peek_imp_decl"
2054 "`ovm_blocking_master_imp_decl"
2055 "`ovm_blocking_peek_imp_decl"
2056 "`ovm_blocking_put_imp_decl"
2057 "`ovm_blocking_slave_imp_decl"
2058 "`ovm_blocking_transport_imp_decl"
2059 "`ovm_component_registry"
2060 "`ovm_component_registry_param"
2061 "`ovm_component_utils"
2064 "`ovm_declare_sequence_lib"
2071 "`ovm_field_aa_int_byte"
2072 "`ovm_field_aa_int_byte_unsigned"
2073 "`ovm_field_aa_int_int"
2074 "`ovm_field_aa_int_int_unsigned"
2075 "`ovm_field_aa_int_integer"
2076 "`ovm_field_aa_int_integer_unsigned"
2077 "`ovm_field_aa_int_key"
2078 "`ovm_field_aa_int_longint"
2079 "`ovm_field_aa_int_longint_unsigned"
2080 "`ovm_field_aa_int_shortint"
2081 "`ovm_field_aa_int_shortint_unsigned"
2082 "`ovm_field_aa_int_string"
2083 "`ovm_field_aa_object_int"
2084 "`ovm_field_aa_object_string"
2085 "`ovm_field_aa_string_int"
2086 "`ovm_field_aa_string_string"
2087 "`ovm_field_array_int"
2088 "`ovm_field_array_object"
2089 "`ovm_field_array_string"
2094 "`ovm_field_queue_int"
2095 "`ovm_field_queue_object"
2096 "`ovm_field_queue_string"
2097 "`ovm_field_sarray_int"
2102 "`ovm_get_peek_imp_decl"
2109 "`ovm_master_imp_decl"
2111 "`ovm_non_blocking_transport_imp_decl"
2112 "`ovm_nonblocking_get_imp_decl"
2113 "`ovm_nonblocking_get_peek_imp_decl"
2114 "`ovm_nonblocking_master_imp_decl"
2115 "`ovm_nonblocking_peek_imp_decl"
2116 "`ovm_nonblocking_put_imp_decl"
2117 "`ovm_nonblocking_slave_imp_decl"
2118 "`ovm_object_registry"
2119 "`ovm_object_registry_param"
2121 "`ovm_peek_imp_decl"
2122 "`ovm_phase_func_decl"
2123 "`ovm_phase_task_decl"
2124 "`ovm_print_aa_int_object"
2125 "`ovm_print_aa_string_int"
2126 "`ovm_print_aa_string_object"
2127 "`ovm_print_aa_string_string"
2128 "`ovm_print_array_int"
2129 "`ovm_print_array_object"
2130 "`ovm_print_array_string"
2131 "`ovm_print_object_queue"
2132 "`ovm_print_queue_int"
2133 "`ovm_print_string_queue"
2136 "`ovm_rand_send_with"
2138 "`ovm_sequence_utils"
2139 "`ovm_slave_imp_decl"
2140 "`ovm_transport_imp_decl"
2141 "`ovm_update_sequence_lib"
2142 "`ovm_update_sequence_lib_and_item"
2145 "`static_message") nil )))
2147 (defconst verilog-uvm-statement-re
2152 "`uvm_analysis_imp_decl"
2153 "`uvm_blocking_get_imp_decl"
2154 "`uvm_blocking_get_peek_imp_decl"
2155 "`uvm_blocking_master_imp_decl"
2156 "`uvm_blocking_peek_imp_decl"
2157 "`uvm_blocking_put_imp_decl"
2158 "`uvm_blocking_slave_imp_decl"
2159 "`uvm_blocking_transport_imp_decl"
2160 "`uvm_component_param_utils"
2161 "`uvm_component_registry"
2162 "`uvm_component_registry_param"
2163 "`uvm_component_utils"
2166 "`uvm_create_seq" ; Undocumented in 1.1
2167 "`uvm_declare_p_sequencer"
2168 "`uvm_declare_sequence_lib" ; Deprecated in 1.1
2171 "`uvm_do_callbacks_exit_on"
2172 "`uvm_do_obj_callbacks"
2173 "`uvm_do_obj_callbacks_exit_on"
2176 "`uvm_do_on_pri_with"
2180 "`uvm_do_seq" ; Undocumented in 1.1
2181 "`uvm_do_seq_with" ; Undocumented in 1.1
2184 "`uvm_error_context"
2186 "`uvm_fatal_context"
2187 "`uvm_field_aa_int_byte"
2188 "`uvm_field_aa_int_byte_unsigned"
2189 "`uvm_field_aa_int_enum"
2190 "`uvm_field_aa_int_int"
2191 "`uvm_field_aa_int_int_unsigned"
2192 "`uvm_field_aa_int_integer"
2193 "`uvm_field_aa_int_integer_unsigned"
2194 "`uvm_field_aa_int_key"
2195 "`uvm_field_aa_int_longint"
2196 "`uvm_field_aa_int_longint_unsigned"
2197 "`uvm_field_aa_int_shortint"
2198 "`uvm_field_aa_int_shortint_unsigned"
2199 "`uvm_field_aa_int_string"
2200 "`uvm_field_aa_object_int"
2201 "`uvm_field_aa_object_string"
2202 "`uvm_field_aa_string_int"
2203 "`uvm_field_aa_string_string"
2204 "`uvm_field_array_enum"
2205 "`uvm_field_array_int"
2206 "`uvm_field_array_object"
2207 "`uvm_field_array_string"
2212 "`uvm_field_queue_enum"
2213 "`uvm_field_queue_int"
2214 "`uvm_field_queue_object"
2215 "`uvm_field_queue_string"
2217 "`uvm_field_sarray_enum"
2218 "`uvm_field_sarray_int"
2219 "`uvm_field_sarray_object"
2220 "`uvm_field_sarray_string"
2223 "`uvm_file" ; Undocumented in 1.1, use `__FILE__
2225 "`uvm_get_peek_imp_decl"
2228 "`uvm_line" ; Undocumented in 1.1, use `__LINE__
2229 "`uvm_master_imp_decl"
2230 "`uvm_non_blocking_transport_imp_decl" ; Deprecated in 1.1
2231 "`uvm_nonblocking_get_imp_decl"
2232 "`uvm_nonblocking_get_peek_imp_decl"
2233 "`uvm_nonblocking_master_imp_decl"
2234 "`uvm_nonblocking_peek_imp_decl"
2235 "`uvm_nonblocking_put_imp_decl"
2236 "`uvm_nonblocking_slave_imp_decl"
2237 "`uvm_nonblocking_transport_imp_decl"
2238 "`uvm_object_param_utils"
2239 "`uvm_object_registry"
2240 "`uvm_object_registry_param" ; Undocumented in 1.1
2254 "`uvm_peek_imp_decl"
2257 "`uvm_rand_send_pri"
2258 "`uvm_rand_send_pri_with"
2259 "`uvm_rand_send_with"
2260 "`uvm_record_attribute"
2265 "`uvm_sequence_utils" ; Deprecated in 1.1
2266 "`uvm_set_super_type"
2267 "`uvm_slave_imp_decl"
2268 "`uvm_transport_imp_decl"
2270 "`uvm_unpack_arrayN"
2276 "`uvm_unpack_queueN"
2278 "`uvm_unpack_sarray"
2279 "`uvm_unpack_sarrayN"
2280 "`uvm_unpack_string"
2281 "`uvm_update_sequence_lib" ; Deprecated in 1.1
2282 "`uvm_update_sequence_lib_and_item" ; Deprecated in 1.1
2284 "`uvm_warning_context") nil )))
2288 ;; Regular expressions used to calculate indent, etc.
2290 (defconst verilog-symbol-re "\\<[a-zA-Z_][a-zA-Z_0-9.]*\\>")
2297 (defconst verilog-assignment-operator-re
2301 ;; blocking assignment_operator
2302 "=" "+=" "-=" "*=" "/=" "%=" "&=" "|=" "^=" "<<=" ">>=" "<<<=" ">>>="
2303 ;; non blocking assignment operator
2306 "==" "!=" "===" "!==" "<=" ">=" "==\?" "!=\?" "<->"
2310 "|->" "|=>" "#-#" "#=#"
2311 ;; distribution weighting
2315 (defconst verilog-assignment-operation-re
2317 ;; "\\(^\\s-*[A-Za-z0-9_]+\\(\\[\\([A-Za-z0-9_]+\\)\\]\\)*\\s-*\\)"
2318 ;; "\\(^\\s-*[^=<>+-*/%&|^:\\s-]+[^=<>+-*/%&|^\n]*?\\)"
2319 "\\(^.*?\\)" "\\B" verilog-assignment-operator-re "\\B" ))
2321 (defconst verilog-label-re (concat verilog-symbol-re "\\s-*:\\s-*"))
2322 (defconst verilog-property-re
2323 (concat "\\(" verilog-label-re "\\)?"
2324 ;; "\\(assert\\|assume\\|cover\\)\\s-+property\\>"
2325 "\\(\\(assert\\|assume\\|cover\\)\\>\\s-+\\<property\\>\\)\\|\\(assert\\)"))
2327 (defconst verilog-no-indent-begin-re
2329 (verilog-regexp-words
2330 '("always" "always_comb" "always_ff" "always_latch" "initial" "final" ; procedural blocks
2331 "if" "else" ; conditional statements
2332 "while" "for" "foreach" "repeat" "do" "forever" )))) ; loop statements
2334 (defconst verilog-ends-re
2335 ;; Parenthesis indicate type of keyword found
2337 "\\(\\<else\\>\\)\\|" ; 1
2338 "\\(\\<if\\>\\)\\|" ; 2
2339 "\\(\\<assert\\>\\)\\|" ; 3
2340 "\\(\\<end\\>\\)\\|" ; 3.1
2341 "\\(\\<endcase\\>\\)\\|" ; 4
2342 "\\(\\<endfunction\\>\\)\\|" ; 5
2343 "\\(\\<endtask\\>\\)\\|" ; 6
2344 "\\(\\<endspecify\\>\\)\\|" ; 7
2345 "\\(\\<endtable\\>\\)\\|" ; 8
2346 "\\(\\<endgenerate\\>\\)\\|" ; 9
2347 "\\(\\<join\\(_any\\|_none\\)?\\>\\)\\|" ; 10
2348 "\\(\\<endclass\\>\\)\\|" ; 11
2349 "\\(\\<endgroup\\>\\)\\|" ; 12
2351 "\\(\\<`vmm_data_member_end\\>\\)\\|"
2352 "\\(\\<`vmm_env_member_end\\>\\)\\|"
2353 "\\(\\<`vmm_scenario_member_end\\>\\)\\|"
2354 "\\(\\<`vmm_subenv_member_end\\>\\)\\|"
2355 "\\(\\<`vmm_xactor_member_end\\>\\)\\|"
2357 "\\(\\<`ovm_component_utils_end\\>\\)\\|"
2358 "\\(\\<`ovm_field_utils_end\\>\\)\\|"
2359 "\\(\\<`ovm_object_utils_end\\>\\)\\|"
2360 "\\(\\<`ovm_sequence_utils_end\\>\\)\\|"
2361 "\\(\\<`ovm_sequencer_utils_end\\>\\)"
2363 "\\(\\<`uvm_component_utils_end\\>\\)\\|"
2364 "\\(\\<`uvm_field_utils_end\\>\\)\\|"
2365 "\\(\\<`uvm_object_utils_end\\>\\)\\|"
2366 "\\(\\<`uvm_sequence_utils_end\\>\\)\\|"
2367 "\\(\\<`uvm_sequencer_utils_end\\>\\)"
2370 (defconst verilog-auto-end-comment-lines-re
2371 ;; Matches to names in this list cause auto-end-commenting
2373 verilog-directive-re "\\)\\|\\("
2375 (verilog-regexp-words
2404 ;; NOTE: verilog-leap-to-head expects that verilog-end-block-re and
2405 ;; verilog-end-block-ordered-re matches exactly the same strings.
2406 (defconst verilog-end-block-ordered-re
2407 ;; Parenthesis indicate type of keyword found
2408 (concat "\\(\\<endcase\\>\\)\\|" ; 1
2409 "\\(\\<end\\>\\)\\|" ; 2
2410 "\\(\\<end" ; 3, but not used
2411 "\\(" ; 4, but not used
2412 "\\(function\\)\\|" ; 5
2414 "\\(module\\)\\|" ; 7
2415 "\\(primitive\\)\\|" ; 8
2416 "\\(interface\\)\\|" ; 9
2417 "\\(package\\)\\|" ; 10
2418 "\\(class\\)\\|" ; 11
2419 "\\(group\\)\\|" ; 12
2420 "\\(program\\)\\|" ; 13
2421 "\\(sequence\\)\\|" ; 14
2422 "\\(clocking\\)\\|" ; 15
2423 "\\(property\\)\\|" ; 16
2425 (defconst verilog-end-block-re
2427 (verilog-regexp-words
2429 `("end" ; closes begin
2430 "endcase" ; closes any of case, casex casez or randcase
2431 "join" "join_any" "join_none" ; closes fork
2446 "`ovm_component_utils_end"
2447 "`ovm_field_utils_end"
2448 "`ovm_object_utils_end"
2449 "`ovm_sequence_utils_end"
2450 "`ovm_sequencer_utils_end"
2452 "`uvm_component_utils_end"
2453 "`uvm_field_utils_end"
2454 "`uvm_object_utils_end"
2455 "`uvm_sequence_utils_end"
2456 "`uvm_sequencer_utils_end"
2458 "`vmm_data_member_end"
2459 "`vmm_env_member_end"
2460 "`vmm_scenario_member_end"
2461 "`vmm_subenv_member_end"
2462 "`vmm_xactor_member_end"
2466 (defconst verilog-endcomment-reason-re
2467 ;; Parenthesis indicate type of keyword found
2469 "\\(\\<begin\\>\\)\\|" ; 1
2470 "\\(\\<else\\>\\)\\|" ; 2
2471 "\\(\\<end\\>\\s-+\\<else\\>\\)\\|" ; 3
2472 "\\(\\<always\\(?:_ff\\)?\\>\\(?:\[ \t\]*@\\)\\)\\|" ; 4 (matches always or always_ff w/ @...)
2473 "\\(\\<always\\(?:_comb\\|_latch\\)?\\>\\)\\|" ; 5 (matches always, always_comb, always_latch w/o @...)
2474 "\\(\\<fork\\>\\)\\|" ; 7
2476 verilog-property-re "\\|"
2477 "\\(\\(" verilog-label-re "\\)?\\<assert\\>\\)\\|"
2478 "\\(\\<clocking\\>\\)\\|"
2479 "\\(\\<task\\>\\)\\|"
2480 "\\(\\<function\\>\\)\\|"
2481 "\\(\\<initial\\>\\)\\|"
2482 "\\(\\<interface\\>\\)\\|"
2483 "\\(\\<package\\>\\)\\|"
2484 "\\(\\<final\\>\\)\\|"
2486 "\\(\\<while\\>\\)\\|\\(\\<do\\>\\)\\|"
2487 "\\(\\<for\\(ever\\|each\\)?\\>\\)\\|"
2488 "\\(\\<repeat\\>\\)\\|\\(\\<wait\\>\\)\\|"
2491 (defconst verilog-named-block-re "begin[ \t]*:")
2493 ;; These words begin a block which can occur inside a module which should be indented,
2494 ;; and closed with the respective word from the end-block list
2496 (defconst verilog-beg-block-re
2498 (verilog-regexp-words
2500 "case" "casex" "casez" "randcase"
2510 "`ovm_component_utils_begin"
2511 "`ovm_component_param_utils_begin"
2512 "`ovm_field_utils_begin"
2513 "`ovm_object_utils_begin"
2514 "`ovm_object_param_utils_begin"
2515 "`ovm_sequence_utils_begin"
2516 "`ovm_sequencer_utils_begin"
2518 "`uvm_component_utils_begin"
2519 "`uvm_component_param_utils_begin"
2520 "`uvm_field_utils_begin"
2521 "`uvm_object_utils_begin"
2522 "`uvm_object_param_utils_begin"
2523 "`uvm_sequence_utils_begin"
2524 "`uvm_sequencer_utils_begin"
2526 "`vmm_data_member_begin"
2527 "`vmm_env_member_begin"
2528 "`vmm_scenario_member_begin"
2529 "`vmm_subenv_member_begin"
2530 "`vmm_xactor_member_begin"
2532 ;; These are the same words, in a specific order in the regular
2533 ;; expression so that matching will work nicely for
2534 ;; verilog-forward-sexp and verilog-calc-indent
2535 (defconst verilog-beg-block-re-ordered
2536 ( concat "\\(\\<begin\\>\\)" ;1
2537 "\\|\\(\\<randcase\\>\\|\\(\\<unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\>\\)" ; 2,3
2538 "\\|\\(\\(\\<disable\\>\\s-+\\|\\<wait\\>\\s-+\\)?fork\\>\\)" ;4,5
2539 "\\|\\(\\<class\\>\\)" ;6
2540 "\\|\\(\\<table\\>\\)" ;7
2541 "\\|\\(\\<specify\\>\\)" ;8
2542 "\\|\\(\\<function\\>\\)" ;9
2543 "\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)*\\<function\\>\\)" ;10
2544 "\\|\\(\\<task\\>\\)" ;14
2545 "\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)*\\<task\\>\\)" ;15
2546 "\\|\\(\\<generate\\>\\)" ;18
2547 "\\|\\(\\<covergroup\\>\\)" ;16 20
2548 "\\|\\(\\(\\(\\<cover\\>\\s-+\\)\\|\\(\\<assert\\>\\s-+\\)\\)*\\<property\\>\\)" ;17 21
2549 "\\|\\(\\<\\(rand\\)?sequence\\>\\)" ;21 25
2550 "\\|\\(\\<clocking\\>\\)" ;22 27
2551 "\\|\\(\\<`[ou]vm_[a-z_]+_begin\\>\\)" ;28
2552 "\\|\\(\\<`vmm_[a-z_]+_member_begin\\>\\)"
2556 (defconst verilog-end-block-ordered-rry
2557 [ "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
2558 "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)"
2559 "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
2560 "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)"
2561 "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)"
2562 "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)"
2563 "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)"
2564 "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)"
2565 "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)"
2566 "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)"
2567 "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)"
2568 "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)"
2569 "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)"
2572 (defconst verilog-nameable-item-re
2574 (verilog-regexp-words
2577 "join" "join_any" "join_none"
2599 (defconst verilog-declaration-opener
2601 (verilog-regexp-words
2602 `("module" "begin" "task" "function"))))
2604 (defconst verilog-declaration-prefix-re
2606 (verilog-regexp-words
2609 "inout" "input" "output" "ref"
2611 "const" "static" "protected" "local"
2613 "localparam" "parameter" "var"
2617 (defconst verilog-declaration-core-re
2619 (verilog-regexp-words
2621 ;; port direction (by themselves)
2622 "inout" "input" "output"
2623 ;; integer_atom_type
2624 "byte" "shortint" "int" "longint" "integer" "time"
2625 ;; integer_vector_type
2628 "shortreal" "real" "realtime"
2630 "supply0" "supply1" "tri" "triand" "trior" "trireg" "tri0" "tri1" "uwire" "wire" "wand" "wor"
2632 "string" "event" "chandle" "virtual" "enum" "genvar"
2635 "mailbox" "semaphore"
2637 (defconst verilog-declaration-re
2638 (concat "\\(" verilog-declaration-prefix-re "\\s-*\\)?" verilog-declaration-core-re))
2639 (defconst verilog-range-re "\\(\\[[^]]*\\]\\s-*\\)+")
2640 (defconst verilog-optional-signed-re "\\s-*\\(\\(un\\)?signed\\)?")
2641 (defconst verilog-optional-signed-range-re
2643 "\\s-*\\(\\<\\(reg\\|wire\\)\\>\\s-*\\)?\\(\\<\\(un\\)?signed\\>\\s-*\\)?\\(" verilog-range-re "\\)?"))
2644 (defconst verilog-macroexp-re "`\\sw+")
2646 (defconst verilog-delay-re "#\\s-*\\(\\([0-9_]+\\('s?[hdxbo][0-9a-fA-F_xz]+\\)?\\)\\|\\(([^()]*)\\)\\|\\(\\sw+\\)\\)")
2647 (defconst verilog-declaration-re-2-no-macro
2648 (concat "\\s-*" verilog-declaration-re
2649 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
2651 (defconst verilog-declaration-re-2-macro
2652 (concat "\\s-*" verilog-declaration-re
2653 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
2654 "\\|\\(" verilog-macroexp-re "\\)"
2656 (defconst verilog-declaration-re-1-macro
2657 (concat "^" verilog-declaration-re-2-macro))
2659 (defconst verilog-declaration-re-1-no-macro (concat "^" verilog-declaration-re-2-no-macro))
2661 (defconst verilog-defun-re
2662 (eval-when-compile (verilog-regexp-words `("macromodule" "module" "class" "program" "interface" "package" "primitive" "config"))))
2663 (defconst verilog-end-defun-re
2664 (eval-when-compile (verilog-regexp-words `("endmodule" "endclass" "endprogram" "endinterface" "endpackage" "endprimitive" "endconfig"))))
2665 (defconst verilog-zero-indent-re
2666 (concat verilog-defun-re "\\|" verilog-end-defun-re))
2667 (defconst verilog-inst-comment-re
2668 (eval-when-compile (verilog-regexp-words `("Outputs" "Inouts" "Inputs" "Interfaces" "Interfaced"))))
2670 (defconst verilog-behavioral-block-beg-re
2671 (eval-when-compile (verilog-regexp-words `("initial" "final" "always" "always_comb" "always_latch" "always_ff"
2672 "function" "task"))))
2673 (defconst verilog-coverpoint-re "\\w+\\s*:\\s*\\(coverpoint\\|cross\\constraint\\)" )
2674 (defconst verilog-in-constraint-re ; keywords legal in constraint blocks starting a statement/block
2675 (eval-when-compile (verilog-regexp-words `("if" "else" "solve" "foreach"))))
2677 (defconst verilog-indent-re
2679 (verilog-regexp-words
2682 "always" "always_latch" "always_ff" "always_comb"
2684 ;; "unique" "priority"
2685 "case" "casex" "casez" "randcase" "endcase"
2687 "clocking" "endclocking"
2688 "config" "endconfig"
2689 "covergroup" "endgroup"
2690 "fork" "join" "join_any" "join_none"
2691 "function" "endfunction"
2693 "generate" "endgenerate"
2695 "interface" "endinterface"
2696 "module" "macromodule" "endmodule"
2697 "package" "endpackage"
2698 "primitive" "endprimitive"
2699 "program" "endprogram"
2700 "property" "endproperty"
2701 "sequence" "randsequence" "endsequence"
2702 "specify" "endspecify"
2709 "`if" "`ifdef" "`ifndef" "`else" "`elsif" "`endif"
2710 "`while" "`endwhile"
2715 "`protect" "`endprotect"
2716 "`switch" "`endswitch"
2720 "`ovm_component_utils_begin"
2721 "`ovm_component_param_utils_begin"
2722 "`ovm_field_utils_begin"
2723 "`ovm_object_utils_begin"
2724 "`ovm_object_param_utils_begin"
2725 "`ovm_sequence_utils_begin"
2726 "`ovm_sequencer_utils_begin"
2728 "`ovm_component_utils_end"
2729 "`ovm_field_utils_end"
2730 "`ovm_object_utils_end"
2731 "`ovm_sequence_utils_end"
2732 "`ovm_sequencer_utils_end"
2734 "`uvm_component_utils_begin"
2735 "`uvm_component_param_utils_begin"
2736 "`uvm_field_utils_begin"
2737 "`uvm_object_utils_begin"
2738 "`uvm_object_param_utils_begin"
2739 "`uvm_sequence_utils_begin"
2740 "`uvm_sequencer_utils_begin"
2742 "`uvm_component_utils_end" ; Typo in spec, it's not uvm_component_end
2743 "`uvm_field_utils_end"
2744 "`uvm_object_utils_end"
2745 "`uvm_sequence_utils_end"
2746 "`uvm_sequencer_utils_end"
2748 "`vmm_data_member_begin"
2749 "`vmm_env_member_begin"
2750 "`vmm_scenario_member_begin"
2751 "`vmm_subenv_member_begin"
2752 "`vmm_xactor_member_begin"
2754 "`vmm_data_member_end"
2755 "`vmm_env_member_end"
2756 "`vmm_scenario_member_end"
2757 "`vmm_subenv_member_end"
2758 "`vmm_xactor_member_end"
2761 (defconst verilog-defun-level-not-generate-re
2763 (verilog-regexp-words
2764 `( "module" "macromodule" "primitive" "class" "program"
2765 "interface" "package" "config"))))
2767 (defconst verilog-defun-level-re
2769 (verilog-regexp-words
2771 `( "module" "macromodule" "primitive" "class" "program"
2772 "interface" "package" "config")
2773 `( "initial" "final" "always" "always_comb" "always_ff"
2774 "always_latch" "endtask" "endfunction" )))))
2776 (defconst verilog-defun-level-generate-only-re
2778 (verilog-regexp-words
2779 `( "initial" "final" "always" "always_comb" "always_ff"
2780 "always_latch" "endtask" "endfunction" ))))
2782 (defconst verilog-cpp-level-re
2784 (verilog-regexp-words
2786 "endmodule" "endprimitive" "endinterface" "endpackage" "endprogram" "endclass"
2789 (defconst verilog-dpi-import-export-re
2791 "\\(\\<\\(import\\|export\\)\\>\\s-+\"DPI\\(-C\\)?\"\\s-+\\(\\<\\(context\\|pure\\)\\>\\s-+\\)?\\([A-Za-z_][A-Za-z0-9_]*\\s-*=\\s-*\\)?\\<\\(function\\|task\\)\\>\\)"
2794 (defconst verilog-disable-fork-re "\\(disable\\|wait\\)\\s-+fork\\>")
2795 (defconst verilog-extended-case-re "\\(\\(unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\)")
2796 (defconst verilog-extended-complete-re
2797 (concat "\\(\\(\\<extern\\s-+\\|\\<\\(\\<\\(pure\\|context\\)\\>\\s-+\\)?virtual\\s-+\\|\\<protected\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)\\)"
2798 "\\|\\(\\(\\<typedef\\>\\s-+\\)*\\(\\<struct\\>\\|\\<union\\>\\|\\<class\\>\\)\\)"
2799 "\\|\\(\\(\\<\\(import\\|export\\)\\>\\s-+\\)?\\(\"DPI\\(-C\\)?\"\\s-+\\)?\\(\\<\\(pure\\|context\\)\\>\\s-+\\)?\\([A-Za-z_][A-Za-z0-9_]*\\s-*=\\s-*\\)?\\(function\\>\\|task\\>\\)\\)"
2800 "\\|" verilog-extended-case-re ))
2801 (defconst verilog-basic-complete-re
2803 (verilog-regexp-words
2805 "always" "assign" "always_latch" "always_ff" "always_comb" "constraint"
2806 "import" "initial" "final" "module" "macromodule" "repeat" "randcase" "while"
2807 "if" "for" "forever" "foreach" "else" "parameter" "do" "localparam" "assert"
2809 (defconst verilog-complete-reg
2811 verilog-extended-complete-re "\\|\\(" verilog-basic-complete-re "\\)"))
2813 (defconst verilog-end-statement-re
2814 (concat "\\(" verilog-beg-block-re "\\)\\|\\("
2815 verilog-end-block-re "\\)"))
2817 (defconst verilog-endcase-re
2818 (concat verilog-extended-case-re "\\|"
2823 (defconst verilog-exclude-str-start "/* -----\\/----- EXCLUDED -----\\/-----"
2824 "String used to mark beginning of excluded text.")
2825 (defconst verilog-exclude-str-end " -----/\\----- EXCLUDED -----/\\----- */"
2826 "String used to mark end of excluded text.")
2827 (defconst verilog-preprocessor-re
2832 (verilog-regexp-words
2840 "`nounconnected_drive"
2842 "`unconnected_drive"
2845 ;; two words: i.e. `ifdef DEFINE
2846 "\\<\\(`elsif\\|`ifn?def\\|`undef\\|`default_nettype\\|`begin_keywords\\)\\>\\s-"
2848 ;; `line number "filename" level
2849 "\\<\\(`line\\)\\>\\s-+[0-9]+\\s-+\"[^\"]+\"\\s-+[012]"
2851 ;;`include "file" or `include <file>
2852 "\\<\\(`include\\)\\>\\s-+\\(?:\"[^\"]+\"\\|<[^>]+>\\)"
2854 ;; `pragma <stuff> (no mention in IEEE 1800-2012 that pragma can span multiple lines
2855 "\\<\\(`pragma\\)\\>\\s-+.+$"
2857 ;; `timescale time_unit / time_precision
2858 "\\<\\(`timescale\\)\\>\\s-+10\\{0,2\\}\\s-*[munpf]?s\\s-*\\/\\s-*10\\{0,2\\}\\s-*[munpf]?s"
2860 ;; `define and `if can span multiple lines if line ends in '\'. NOTE: `if is not IEEE 1800-2012
2861 ;; from http://www.emacswiki.org/emacs/MultilineRegexp
2862 (concat "\\<\\(`define\\|`if\\)\\>" ; directive
2864 "\\(?:.*?\\(?:\n.*\\)*?\\)" ; definition: to end of line, then maybe more lines (excludes any trailing \n)
2865 "\\(?:\n\\s-*\n\\|\\'\\)") ; blank line or EOF
2867 ;; `<macro>() : i.e. `uvm_info(a,b,c) or any other pre-defined macro
2868 ;; Since parameters inside the macro can have parentheses, and
2869 ;; the macro can span multiple lines, just look for the opening
2870 ;; parentheses and then continue to the end of the first
2872 (concat "\\<`\\w+\\>\\s-*("
2873 "\\(?:.*?\\(?:\n.*\\)*?\\)" ; definition: to end of line, then maybe more lines (excludes any trailing \n)
2874 "\\(?:\n\\s-*\n\\|\\'\\)") ; blank line or EOF
2878 (defconst verilog-keywords
2879 (append verilog-compiler-directives
2881 "after" "alias" "always" "always_comb" "always_ff" "always_latch" "and"
2882 "assert" "assign" "assume" "automatic" "before" "begin" "bind"
2883 "bins" "binsof" "bit" "break" "buf" "bufif0" "bufif1" "byte"
2884 "case" "casex" "casez" "cell" "chandle" "class" "clocking" "cmos"
2885 "config" "const" "constraint" "context" "continue" "cover"
2886 "covergroup" "coverpoint" "cross" "deassign" "default" "defparam"
2887 "design" "disable" "dist" "do" "edge" "else" "end" "endcase"
2888 "endclass" "endclocking" "endconfig" "endfunction" "endgenerate"
2889 "endgroup" "endinterface" "endmodule" "endpackage" "endprimitive"
2890 "endprogram" "endproperty" "endspecify" "endsequence" "endtable"
2891 "endtask" "enum" "event" "expect" "export" "extends" "extern"
2892 "final" "first_match" "for" "force" "foreach" "forever" "fork"
2893 "forkjoin" "function" "generate" "genvar" "highz0" "highz1" "if"
2894 "iff" "ifnone" "ignore_bins" "illegal_bins" "import" "incdir"
2895 "include" "initial" "inout" "input" "inside" "instance" "int"
2896 "integer" "interface" "intersect" "join" "join_any" "join_none"
2897 "large" "liblist" "library" "local" "localparam" "logic"
2898 "longint" "macromodule" "mailbox" "matches" "medium" "modport" "module"
2899 "nand" "negedge" "new" "nmos" "nor" "noshowcancelled" "not"
2900 "notif0" "notif1" "null" "or" "output" "package" "packed"
2901 "parameter" "pmos" "posedge" "primitive" "priority" "program"
2902 "property" "protected" "pull0" "pull1" "pulldown" "pullup"
2903 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
2904 "randcase" "randsequence" "rcmos" "real" "realtime" "ref" "reg"
2905 "release" "repeat" "return" "rnmos" "rpmos" "rtran" "rtranif0"
2906 "rtranif1" "scalared" "semaphore" "sequence" "shortint" "shortreal"
2907 "showcancelled" "signed" "small" "solve" "specify" "specparam"
2908 "static" "string" "strong0" "strong1" "struct" "super" "supply0"
2909 "supply1" "table" "tagged" "task" "this" "throughout" "time"
2910 "timeprecision" "timeunit" "tran" "tranif0" "tranif1" "tri"
2911 "tri0" "tri1" "triand" "trior" "trireg" "type" "typedef" "union"
2912 "unique" "unsigned" "use" "uwire" "var" "vectored" "virtual" "void"
2913 "wait" "wait_order" "wand" "weak0" "weak1" "while" "wildcard"
2914 "wire" "with" "within" "wor" "xnor" "xor"
2916 "accept_on" "checker" "endchecker" "eventually" "global" "implies"
2917 "let" "nexttime" "reject_on" "restrict" "s_always" "s_eventually"
2918 "s_nexttime" "s_until" "s_until_with" "strong" "sync_accept_on"
2919 "sync_reject_on" "unique0" "until" "until_with" "untyped" "weak"
2921 "implements" "interconnect" "nettype" "soft"
2923 "List of Verilog keywords.")
2925 (defconst verilog-comment-start-regexp "//\\|/\\*"
2926 "Dual comment value for `comment-start-regexp'.")
2928 (defvar verilog-mode-syntax-table
2929 (let ((table (make-syntax-table)))
2930 ;; Populate the syntax TABLE.
2931 (modify-syntax-entry ?\\ "\\" table)
2932 (modify-syntax-entry ?+ "." table)
2933 (modify-syntax-entry ?- "." table)
2934 (modify-syntax-entry ?= "." table)
2935 (modify-syntax-entry ?% "." table)
2936 (modify-syntax-entry ?< "." table)
2937 (modify-syntax-entry ?> "." table)
2938 (modify-syntax-entry ?& "." table)
2939 (modify-syntax-entry ?| "." table)
2940 ;; FIXME: This goes against Emacs conventions. Use "_" syntax instead and
2941 ;; then use regexps with things like "\\_<...\\_>".
2942 (modify-syntax-entry ?` "w" table) ; ` is part of definition symbols in Verilog
2943 (modify-syntax-entry ?_ "w" table)
2944 (modify-syntax-entry ?\' "." table)
2946 ;; Set up TABLE to handle block and line style comments.
2947 (if (featurep 'xemacs)
2949 ;; XEmacs (formerly Lucid) has the best implementation
2950 (modify-syntax-entry ?/ ". 1456" table)
2951 (modify-syntax-entry ?* ". 23" table)
2952 (modify-syntax-entry ?\n "> b" table))
2953 ;; Emacs does things differently, but we can work with it
2954 (modify-syntax-entry ?/ ". 124b" table)
2955 (modify-syntax-entry ?* ". 23" table)
2956 (modify-syntax-entry ?\n "> b" table))
2958 "Syntax table used in Verilog mode buffers.")
2960 (defvar verilog-font-lock-keywords nil
2961 "Default highlighting for Verilog mode.")
2963 (defvar verilog-font-lock-keywords-1 nil
2964 "Subdued level highlighting for Verilog mode.")
2966 (defvar verilog-font-lock-keywords-2 nil
2967 "Medium level highlighting for Verilog mode.
2968 See also `verilog-font-lock-extra-types'.")
2970 (defvar verilog-font-lock-keywords-3 nil
2971 "Gaudy level highlighting for Verilog mode.
2972 See also `verilog-font-lock-extra-types'.")
2974 (defvar verilog-font-lock-translate-off-face
2975 'verilog-font-lock-translate-off-face
2976 "Font to use for translated off regions.")
2977 (defface verilog-font-lock-translate-off-face
2980 (:background "gray90" :italic t ))
2983 (:background "gray10" :italic t ))
2984 (((class grayscale) (background light))
2985 (:foreground "DimGray" :italic t))
2986 (((class grayscale) (background dark))
2987 (:foreground "LightGray" :italic t))
2989 "Font lock mode face used to background highlight translate-off regions."
2990 :group 'font-lock-highlighting-faces)
2992 (defvar verilog-font-lock-p1800-face
2993 'verilog-font-lock-p1800-face
2994 "Font to use for p1800 keywords.")
2995 (defface verilog-font-lock-p1800-face
2998 (:foreground "DarkOrange3" :bold t ))
3001 (:foreground "orange1" :bold t ))
3003 "Font lock mode face used to highlight P1800 keywords."
3004 :group 'font-lock-highlighting-faces)
3006 (defvar verilog-font-lock-ams-face
3007 'verilog-font-lock-ams-face
3008 "Font to use for Analog/Mixed Signal keywords.")
3009 (defface verilog-font-lock-ams-face
3012 (:foreground "Purple" :bold t ))
3015 (:foreground "orange1" :bold t ))
3017 "Font lock mode face used to highlight AMS keywords."
3018 :group 'font-lock-highlighting-faces)
3020 (defvar verilog-font-grouping-keywords-face
3021 'verilog-font-lock-grouping-keywords-face
3022 "Font to use for Verilog Grouping Keywords (such as begin..end).")
3023 (defface verilog-font-lock-grouping-keywords-face
3026 (:foreground "Purple" :bold t ))
3029 (:foreground "orange1" :bold t ))
3031 "Font lock mode face used to highlight verilog grouping keywords."
3032 :group 'font-lock-highlighting-faces)
3034 (let* ((verilog-type-font-keywords
3038 "and" "bit" "buf" "bufif0" "bufif1" "cmos" "defparam"
3039 "event" "genvar" "inout" "input" "integer" "localparam"
3040 "logic" "mailbox" "nand" "nmos" "nor" "not" "notif0" "notif1" "or"
3041 "output" "parameter" "pmos" "pull0" "pull1" "pulldown" "pullup"
3042 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran"
3043 "rtranif0" "rtranif1" "semaphore" "signed" "struct" "supply"
3044 "supply0" "supply1" "time" "tran" "tranif0" "tranif1"
3045 "tri" "tri0" "tri1" "triand" "trior" "trireg" "typedef"
3046 "uwire" "vectored" "wand" "wire" "wor" "xnor" "xor"
3049 (verilog-pragma-keywords
3052 '("surefire" "auto" "synopsys" "rtl_synthesis" "verilint" "leda" "0in"
3055 (verilog-1800-2005-keywords
3058 '("alias" "assert" "assume" "automatic" "before" "bind"
3059 "bins" "binsof" "break" "byte" "cell" "chandle" "class"
3060 "clocking" "config" "const" "constraint" "context" "continue"
3061 "cover" "covergroup" "coverpoint" "cross" "deassign" "design"
3062 "dist" "do" "edge" "endclass" "endclocking" "endconfig"
3063 "endgroup" "endprogram" "endproperty" "endsequence" "enum"
3064 "expect" "export" "extends" "extern" "first_match" "foreach"
3065 "forkjoin" "genvar" "highz0" "highz1" "ifnone" "ignore_bins"
3066 "illegal_bins" "import" "incdir" "include" "inside" "instance"
3067 "int" "intersect" "large" "liblist" "library" "local" "longint"
3068 "matches" "medium" "modport" "new" "noshowcancelled" "null"
3069 "packed" "program" "property" "protected" "pull0" "pull1"
3070 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
3071 "randcase" "randsequence" "ref" "release" "return" "scalared"
3072 "sequence" "shortint" "shortreal" "showcancelled" "small" "solve"
3073 "specparam" "static" "string" "strong0" "strong1" "struct"
3074 "super" "tagged" "this" "throughout" "timeprecision" "timeunit"
3075 "type" "union" "unsigned" "use" "var" "virtual" "void"
3076 "wait_order" "weak0" "weak1" "wildcard" "with" "within"
3079 (verilog-1800-2009-keywords
3082 '("accept_on" "checker" "endchecker" "eventually" "global"
3083 "implies" "let" "nexttime" "reject_on" "restrict" "s_always"
3084 "s_eventually" "s_nexttime" "s_until" "s_until_with" "strong"
3085 "sync_accept_on" "sync_reject_on" "unique0" "until"
3086 "until_with" "untyped" "weak" ) nil )))
3088 (verilog-1800-2012-keywords
3091 '("implements" "interconnect" "nettype" "soft" ) nil )))
3093 (verilog-ams-keywords
3096 '("above" "abs" "absdelay" "acos" "acosh" "ac_stim"
3097 "aliasparam" "analog" "analysis" "asin" "asinh" "atan" "atan2" "atanh"
3098 "branch" "ceil" "connectmodule" "connectrules" "cos" "cosh" "ddt"
3099 "ddx" "discipline" "driver_update" "enddiscipline" "endconnectrules"
3100 "endnature" "endparamset" "exclude" "exp" "final_step" "flicker_noise"
3101 "floor" "flow" "from" "ground" "hypot" "idt" "idtmod" "inf"
3102 "initial_step" "laplace_nd" "laplace_np" "laplace_zd" "laplace_zp"
3103 "last_crossing" "limexp" "ln" "log" "max" "min" "nature"
3104 "net_resolution" "noise_table" "paramset" "potential" "pow" "sin"
3105 "sinh" "slew" "sqrt" "tan" "tanh" "timer" "transition" "white_noise"
3106 "wreal" "zi_nd" "zi_np" "zi_zd" ) nil )))
3108 (verilog-font-keywords
3112 "assign" "case" "casex" "casez" "randcase" "deassign"
3113 "default" "disable" "else" "endcase" "endfunction"
3114 "endgenerate" "endinterface" "endmodule" "endprimitive"
3115 "endspecify" "endtable" "endtask" "final" "for" "force" "return" "break"
3116 "continue" "forever" "fork" "function" "generate" "if" "iff" "initial"
3117 "interface" "join" "join_any" "join_none" "macromodule" "module" "negedge"
3118 "package" "endpackage" "always" "always_comb" "always_ff"
3119 "always_latch" "posedge" "primitive" "priority" "release"
3120 "repeat" "specify" "table" "task" "unique" "wait" "while"
3121 "class" "program" "endclass" "endprogram"
3124 (verilog-font-grouping-keywords
3127 '( "begin" "end" ) nil ))))
3129 (setq verilog-font-lock-keywords
3131 ;; Fontify all builtin keywords
3132 (concat "\\<\\(" verilog-font-keywords "\\|"
3133 ;; And user/system tasks and functions
3134 "\\$[a-zA-Z][a-zA-Z0-9_\\$]*"
3136 ;; Fontify all types
3137 (if verilog-highlight-grouping-keywords
3138 (cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>")
3139 'verilog-font-lock-grouping-keywords-face)
3140 (cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>")
3141 'font-lock-type-face))
3142 (cons (concat "\\<\\(" verilog-type-font-keywords "\\)\\>")
3143 'font-lock-type-face)
3144 ;; Fontify IEEE-1800-2005 keywords appropriately
3145 (if verilog-highlight-p1800-keywords
3146 (cons (concat "\\<\\(" verilog-1800-2005-keywords "\\)\\>")
3147 'verilog-font-lock-p1800-face)
3148 (cons (concat "\\<\\(" verilog-1800-2005-keywords "\\)\\>")
3149 'font-lock-type-face))
3150 ;; Fontify IEEE-1800-2009 keywords appropriately
3151 (if verilog-highlight-p1800-keywords
3152 (cons (concat "\\<\\(" verilog-1800-2009-keywords "\\)\\>")
3153 'verilog-font-lock-p1800-face)
3154 (cons (concat "\\<\\(" verilog-1800-2009-keywords "\\)\\>")
3155 'font-lock-type-face))
3156 ;; Fontify IEEE-1800-2012 keywords appropriately
3157 (if verilog-highlight-p1800-keywords
3158 (cons (concat "\\<\\(" verilog-1800-2012-keywords "\\)\\>")
3159 'verilog-font-lock-p1800-face)
3160 (cons (concat "\\<\\(" verilog-1800-2012-keywords "\\)\\>")
3161 'font-lock-type-face))
3162 ;; Fontify Verilog-AMS keywords
3163 (cons (concat "\\<\\(" verilog-ams-keywords "\\)\\>")
3164 'verilog-font-lock-ams-face)))
3166 (setq verilog-font-lock-keywords-1
3167 (append verilog-font-lock-keywords
3169 ;; Fontify module definitions
3171 "\\<\\(\\(macro\\)?module\\|primitive\\|class\\|program\\|interface\\|package\\|task\\)\\>\\s-*\\(\\sw+\\)"
3172 '(1 font-lock-keyword-face)
3173 '(3 font-lock-function-name-face 'prepend))
3174 ;; Fontify function definitions
3176 (concat "\\<function\\>\\s-+\\(integer\\|real\\(time\\)?\\|time\\)\\s-+\\(\\sw+\\)" )
3177 '(1 font-lock-keyword-face)
3178 '(3 font-lock-constant-face prepend))
3179 '("\\<function\\>\\s-+\\(\\[[^]]+\\]\\)\\s-+\\(\\sw+\\)"
3180 (1 font-lock-keyword-face)
3181 (2 font-lock-constant-face append))
3182 '("\\<function\\>\\s-+\\(\\sw+\\)"
3183 1 'font-lock-constant-face append))))
3185 (setq verilog-font-lock-keywords-2
3186 (append verilog-font-lock-keywords-1
3189 (concat "\\(//\\s-*\\(" verilog-pragma-keywords "\\)\\s-.*\\)")
3190 ;; Fontify escaped names
3191 '("\\(\\\\\\S-*\\s-\\)" 0 font-lock-function-name-face)
3192 ;; Fontify macro definitions/ uses
3193 '("`\\s-*[A-Za-z][A-Za-z0-9_]*" 0 (if (boundp 'font-lock-preprocessor-face)
3194 'font-lock-preprocessor-face
3195 'font-lock-type-face))
3196 ;; Fontify delays/numbers
3197 '("\\(@\\)\\|\\([ \t\n\f\r]#\\s-*\\(\\(\[0-9_.\]+\\('s?[hdxbo][0-9a-fA-F_xz]*\\)?\\)\\|\\(([^()]+)\\|\\sw+\\)\\)\\)"
3198 0 font-lock-type-face append)
3199 ;; Fontify property/sequence cycle delays - these start with '##'
3200 '("\\(##\\(\\sw+\\|\\[[^\]]+\\]\\)\\)"
3201 0 font-lock-type-face append)
3202 ;; Fontify instantiation names
3203 '("\\([A-Za-z][A-Za-z0-9_]*\\)\\s-*(" 1 font-lock-function-name-face)
3206 (setq verilog-font-lock-keywords-3
3207 (append verilog-font-lock-keywords-2
3208 (when verilog-highlight-translate-off
3210 ;; Fontify things in translate off regions
3211 '(verilog-match-translate-off
3212 (0 'verilog-font-lock-translate-off-face prepend))
3216 ;; Buffer state preservation
3218 (defmacro verilog-save-buffer-state (&rest body)
3219 "Execute BODY forms, saving state around insignificant change.
3220 Changes in text properties like `face' or `syntax-table' are
3221 considered insignificant. This macro allows text properties to
3222 be changed, even in a read-only buffer.
3224 A change is considered significant if it affects the buffer text
3225 in any way that isn't completely restored again. Any
3226 user-visible changes to the buffer must not be within a
3227 `verilog-save-buffer-state'."
3228 ;; From c-save-buffer-state
3229 `(let* ((modified (buffer-modified-p))
3230 (buffer-undo-list t)
3231 (inhibit-read-only t)
3232 (inhibit-point-motion-hooks t)
3233 (verilog-no-change-functions t)
3234 before-change-functions
3235 after-change-functions
3237 buffer-file-name ; Prevent primitives checking
3238 buffer-file-truename) ; for file modification
3243 (set-buffer-modified-p nil)))))
3245 (defmacro verilog-save-no-change-functions (&rest body)
3246 "Execute BODY forms, disabling all change hooks in BODY.
3247 For insignificant changes, see instead `verilog-save-buffer-state'."
3248 `(let* ((inhibit-point-motion-hooks t)
3249 (verilog-no-change-functions t)
3250 before-change-functions
3251 after-change-functions)
3254 (defvar verilog-save-font-mod-hooked nil
3255 "Local variable when inside a `verilog-save-font-mods' block.")
3256 (make-variable-buffer-local 'verilog-save-font-mod-hooked)
3258 (defmacro verilog-save-font-mods (&rest body)
3259 "Execute BODY forms, disabling text modifications to allow performing BODY.
3260 Includes temporary disabling of `font-lock' to restore the buffer
3261 to full text form for parsing. Additional actions may be specified with
3262 `verilog-before-save-font-hook' and `verilog-after-save-font-hook'."
3263 ;; Before version 20, match-string with font-lock returns a
3264 ;; vector that is not equal to the string. IE if on "input"
3265 ;; nil==(equal "input" (progn (looking-at "input") (match-string 0)))
3266 `(let* ((hooked (unless verilog-save-font-mod-hooked
3267 (verilog-run-hooks 'verilog-before-save-font-hook)
3269 (verilog-save-font-mod-hooked t)
3270 (fontlocked (when (and (boundp 'font-lock-mode) font-lock-mode)
3276 (when fontlocked (font-lock-mode t))
3277 (when hooked (verilog-run-hooks 'verilog-after-save-font-hook)))))
3280 ;; Comment detection and caching
3282 (defvar verilog-scan-cache-preserving nil
3283 "If true, the specified buffer's comment properties are static.
3284 Buffer changes will be ignored. See `verilog-inside-comment-or-string-p'
3285 and `verilog-scan'.")
3287 (defvar verilog-scan-cache-tick nil
3288 "Modification tick at which `verilog-scan' was last completed.")
3289 (make-variable-buffer-local 'verilog-scan-cache-tick)
3291 (defun verilog-scan-cache-flush ()
3292 "Flush the `verilog-scan' cache."
3293 (setq verilog-scan-cache-tick nil))
3295 (defun verilog-scan-cache-ok-p ()
3296 "Return t if the scan cache is up to date."
3297 (or (and verilog-scan-cache-preserving
3298 (eq verilog-scan-cache-preserving (current-buffer))
3299 verilog-scan-cache-tick)
3300 (equal verilog-scan-cache-tick (buffer-chars-modified-tick))))
3302 (defmacro verilog-save-scan-cache (&rest body)
3303 "Execute the BODY forms, allowing scan cache preservation within BODY.
3304 This requires that insertions must use `verilog-insert'."
3305 ;; If the buffer is out of date, trash it, as we'll not check later the tick
3306 ;; Note this must work properly if there's multiple layers of calls
3307 ;; to verilog-save-scan-cache even with differing ticks.
3309 (unless (verilog-scan-cache-ok-p) ; Must be before let
3310 (setq verilog-scan-cache-tick nil))
3311 (let* ((verilog-scan-cache-preserving (current-buffer)))
3314 (defun verilog-scan-region (beg end)
3315 "Parse between BEG and END for `verilog-inside-comment-or-string-p'.
3316 This creates v-cmts properties where comments are in force."
3317 ;; Why properties and not overlays? Overlays have much slower non O(1)
3319 ;; This function is warm - called on every verilog-insert
3322 (verilog-save-buffer-state
3325 (while (< (point) end)
3326 (cond ((looking-at "//")
3328 (or (search-forward "\n" end t)
3330 ;; "1+": The leading // or /* itself isn't considered as
3331 ;; being "inside" the comment, so that a (search-backward)
3332 ;; that lands at the start of the // won't mis-indicate
3333 ;; it's inside a comment. Also otherwise it would be
3334 ;; hard to find a commented out /*AS*/ vs one that isn't
3335 (put-text-property (1+ pt) (point) 'v-cmts t))
3336 ((looking-at "/\\*")
3338 (or (search-forward "*/" end t)
3339 ;; No error - let later code indicate it so we can
3340 ;; use inside functions on-the-fly
3341 ;;(error "%s: Unmatched /* */, at char %d"
3342 ;; (verilog-point-text) (point))
3344 (put-text-property (1+ pt) (point) 'v-cmts t))
3347 (or (re-search-forward "[^\\]\"" end t) ; don't forward-char first, since we look for a non backslash first
3348 ;; No error - let later code indicate it so we can
3350 (put-text-property (1+ pt) (point) 'v-cmts t))
3353 (if (re-search-forward "[/\"]" end t)
3355 (goto-char end))))))))))
3357 (defun verilog-scan ()
3358 "Parse the buffer, marking all comments with properties.
3359 Also assumes any text inserted since `verilog-scan-cache-tick'
3360 either is ok to parse as a non-comment, or `verilog-insert' was used."
3361 ;; See also `verilog-scan-debug' and `verilog-scan-and-debug'
3362 (unless (verilog-scan-cache-ok-p)
3364 (verilog-save-buffer-state
3366 (message "Scanning %s cache=%s cachetick=%S tick=%S" (current-buffer)
3367 verilog-scan-cache-preserving verilog-scan-cache-tick
3368 (buffer-chars-modified-tick)))
3369 (remove-text-properties (point-min) (point-max) '(v-cmts nil))
3370 (verilog-scan-region (point-min) (point-max))
3371 (setq verilog-scan-cache-tick (buffer-chars-modified-tick))
3372 (when verilog-debug (message "Scanning... done"))))))
3374 (defun verilog-scan-debug ()
3375 "For debugging, show with display face results of `verilog-scan'."
3377 ;;(if dbg (setq dbg (concat dbg (format "verilog-scan-debug\n"))))
3379 (goto-char (point-min))
3380 (remove-text-properties (point-min) (point-max) '(face nil))
3382 (cond ((get-text-property (point) 'v-cmts)
3383 (put-text-property (point) (1+ (point)) `face 'underline)
3384 ;;(if dbg (setq dbg (concat dbg (format " v-cmts at %S\n" (point)))))
3387 (goto-char (or (next-property-change (point)) (point-max))))))))
3389 (defun verilog-scan-and-debug ()
3390 "For debugging, run `verilog-scan' and `verilog-scan-debug'."
3391 (let (verilog-scan-cache-preserving
3392 verilog-scan-cache-tick)
3393 (goto-char (point-min))
3395 (verilog-scan-debug)))
3397 (defun verilog-inside-comment-or-string-p (&optional pos)
3398 "Check if optional point POS is inside a comment.
3399 This may require a slow pre-parse of the buffer with `verilog-scan'
3400 to establish comment properties on all text."
3401 ;; This function is very hot
3404 (and (>= pos (point-min))
3405 (get-text-property pos 'v-cmts))
3406 (get-text-property (point) 'v-cmts)))
3408 (defun verilog-insert (&rest stuff)
3409 "Insert STUFF arguments, tracking for `verilog-inside-comment-or-string-p'.
3410 Any insert that includes a comment must have the entire comment
3411 inserted using a single call to `verilog-insert'."
3414 (insert (car stuff))
3415 (setq stuff (cdr stuff)))
3416 (verilog-scan-region pt (point))))
3420 (defun verilog-declaration-end ()
3421 (search-forward ";"))
3423 (defun verilog-point-text (&optional pointnum)
3424 "Return text describing where POINTNUM or current point is (for errors).
3425 Use filename, if current buffer being edited shorten to just buffer name."
3426 (concat (or (and (equal (window-buffer) (current-buffer))
3430 ":" (int-to-string (1+ (count-lines (point-min) (or pointnum (point)))))))
3432 (defun electric-verilog-backward-sexp ()
3433 "Move backward over one balanced expression."
3435 ;; before that see if we are in a comment
3436 (verilog-backward-sexp))
3438 (defun electric-verilog-forward-sexp ()
3439 "Move forward over one balanced expression."
3441 ;; before that see if we are in a comment
3442 (verilog-forward-sexp))
3444 (defun verilog-forward-sexp-function (arg)
3445 "Move forward a sexp."
3446 ;; Used by hs-minor-mode
3448 (verilog-backward-sexp)
3449 (verilog-forward-sexp)))
3451 (defun verilog-backward-sexp ()
3456 (if (not (looking-at "\\<"))
3459 ((verilog-skip-backward-comment-or-string))
3460 ((looking-at "\\<else\\>")
3462 verilog-end-block-re
3463 "\\|\\(\\<else\\>\\)"
3464 "\\|\\(\\<if\\>\\)"))
3465 (while (and (not found)
3466 (verilog-re-search-backward reg nil 'move))
3468 ((match-end 1) ; matched verilog-end-block-re
3469 ;; try to leap back to matching outward block by striding across
3470 ;; indent level changing tokens then immediately
3471 ;; previous line governs indentation.
3472 (verilog-leap-to-head))
3473 ((match-end 2) ; else, we're in deep
3474 (setq elsec (1+ elsec)))
3475 ((match-end 3) ; found it
3476 (setq elsec (1- elsec))
3478 ;; Now previous line describes syntax
3479 (setq found 't))))))
3480 ((looking-at verilog-end-block-re)
3481 (verilog-leap-to-head))
3482 ((looking-at "\\(endmodule\\>\\)\\|\\(\\<endprimitive\\>\\)\\|\\(\\<endclass\\>\\)\\|\\(\\<endprogram\\>\\)\\|\\(\\<endinterface\\>\\)\\|\\(\\<endpackage\\>\\)")
3485 (verilog-re-search-backward "\\<\\(macro\\)?module\\>" nil 'move))
3487 (verilog-re-search-backward "\\<primitive\\>" nil 'move))
3489 (verilog-re-search-backward "\\<class\\>" nil 'move))
3491 (verilog-re-search-backward "\\<program\\>" nil 'move))
3493 (verilog-re-search-backward "\\<interface\\>" nil 'move))
3495 (verilog-re-search-backward "\\<package\\>" nil 'move))
3498 (backward-sexp 1))))
3503 (defun verilog-forward-sexp ()
3508 (if (not (looking-at "\\<"))
3511 ((verilog-skip-forward-comment-or-string)
3512 (verilog-forward-syntactic-ws))
3513 ((looking-at verilog-beg-block-re-ordered)
3516 ;; Search forward for matching end
3517 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
3519 ;; Search forward for matching endcase
3520 (setq reg "\\(\\<randcase\\>\\|\\(\\<unique0?\\>\\s-+\\|\\<priority\\>\\s-+\\)?\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" )
3521 (setq md 3) ; ender is third item in regexp
3524 ;; might be "disable fork" or "wait fork"
3528 (looking-at verilog-disable-fork-re)
3529 (and (looking-at "fork")
3531 (setq here (point)) ; sometimes a fork is just a fork
3533 (looking-at verilog-disable-fork-re))))
3534 (progn ; it is a disable fork; ignore it
3535 (goto-char (match-end 0))
3538 (progn ; it is a nice simple fork
3539 (goto-char here) ; return from looking for "disable fork"
3540 ;; Search forward for matching join
3541 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))))
3543 ;; Search forward for matching endclass
3544 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
3547 ;; Search forward for matching endtable
3548 (setq reg "\\<endtable\\>" )
3551 ;; Search forward for matching endspecify
3552 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
3554 ;; Search forward for matching endfunction
3555 (setq reg "\\<endfunction\\>" )
3558 ;; Search forward for matching endfunction
3559 (setq reg "\\<endfunction\\>" )
3562 ;; Search forward for matching endtask
3563 (setq reg "\\<endtask\\>" )
3566 ;; Search forward for matching endtask
3567 (setq reg "\\<endtask\\>" )
3570 ;; Search forward for matching endgenerate
3571 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
3573 ;; Search forward for matching endgroup
3574 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
3576 ;; Search forward for matching endproperty
3577 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
3579 ;; Search forward for matching endsequence
3580 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" )
3581 (setq md 3)) ; 3 to get to endsequence in the reg above
3583 ;; Search forward for matching endclocking
3584 (setq reg "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)" )))
3591 (while (verilog-re-search-forward reg nil 'move)
3593 ((match-end md) ; a closer in regular expression, so we are climbing out
3594 (setq depth (1- depth))
3595 (if (= 0 depth) ; we are out!
3597 ((match-end 1) ; an opener in the r-e, so we are in deeper now
3598 (setq here (point)) ; remember where we started
3599 (goto-char (match-beginning 1))
3602 (looking-at verilog-disable-fork-re)
3603 (and (looking-at "fork")
3606 (looking-at verilog-disable-fork-re))))
3607 (progn ; it is a disable fork; another false alarm
3608 (goto-char (match-end 0)))
3609 (progn ; it is a simple fork (or has nothing to do with fork)
3611 (setq depth (1+ depth))))))))))
3612 (if (verilog-re-search-forward reg nil 'move)
3613 (throw 'skip 1))))))
3615 ((looking-at (concat
3616 "\\(\\<\\(macro\\)?module\\>\\)\\|"
3617 "\\(\\<primitive\\>\\)\\|"
3618 "\\(\\<class\\>\\)\\|"
3619 "\\(\\<program\\>\\)\\|"
3620 "\\(\\<interface\\>\\)\\|"
3621 "\\(\\<package\\>\\)"))
3624 (verilog-re-search-forward "\\<endmodule\\>" nil 'move))
3626 (verilog-re-search-forward "\\<endprimitive\\>" nil 'move))
3628 (verilog-re-search-forward "\\<endclass\\>" nil 'move))
3630 (verilog-re-search-forward "\\<endprogram\\>" nil 'move))
3632 (verilog-re-search-forward "\\<endinterface\\>" nil 'move))
3634 (verilog-re-search-forward "\\<endpackage\\>" nil 'move))
3637 (if (= (following-char) ?\) )
3639 (forward-sexp 1)))))
3642 (if (= (following-char) ?\) )
3644 (forward-sexp 1))))))
3646 (defun verilog-declaration-beg ()
3647 (verilog-re-search-backward verilog-declaration-re (bobp) t))
3653 (defvar verilog-which-tool 1)
3655 (define-derived-mode verilog-mode prog-mode "Verilog"
3656 "Major mode for editing Verilog code.
3657 \\<verilog-mode-map>
3658 See \\[describe-function] verilog-auto (\\[verilog-auto]) for details on how
3659 AUTOs can improve coding efficiency.
3661 Use \\[verilog-faq] for a pointer to frequently asked questions.
3663 NEWLINE, TAB indents for Verilog code.
3664 Delete converts tabs to spaces as it moves back.
3666 Supports highlighting.
3668 Turning on Verilog mode calls the value of the variable `verilog-mode-hook'
3669 with no args, if that value is non-nil.
3671 Variables controlling indentation/edit style:
3673 variable `verilog-indent-level' (default 3)
3674 Indentation of Verilog statements with respect to containing block.
3675 `verilog-indent-level-module' (default 3)
3676 Absolute indentation of Module level Verilog statements.
3677 Set to 0 to get initial and always statements lined up
3678 on the left side of your screen.
3679 `verilog-indent-level-declaration' (default 3)
3680 Indentation of declarations with respect to containing block.
3681 Set to 0 to get them list right under containing block.
3682 `verilog-indent-level-behavioral' (default 3)
3683 Indentation of first begin in a task or function block
3684 Set to 0 to get such code to lined up underneath the task or
3686 `verilog-indent-level-directive' (default 1)
3687 Indentation of \\=`ifdef/\\=`endif blocks.
3688 `verilog-cexp-indent' (default 1)
3689 Indentation of Verilog statements broken across lines i.e.:
3692 `verilog-case-indent' (default 2)
3693 Indentation for case statements.
3694 `verilog-auto-newline' (default nil)
3695 Non-nil means automatically newline after semicolons and the punctuation
3697 `verilog-auto-indent-on-newline' (default t)
3698 Non-nil means automatically indent line after newline.
3699 `verilog-tab-always-indent' (default t)
3700 Non-nil means TAB in Verilog mode should always reindent the current line,
3701 regardless of where in the line point is when the TAB command is used.
3702 `verilog-indent-begin-after-if' (default t)
3703 Non-nil means to indent begin statements following a preceding
3704 if, else, while, for and repeat statements, if any. Otherwise,
3705 the begin is lined up with the preceding token. If t, you get:
3707 begin // amount of indent based on `verilog-cexp-indent'
3711 `verilog-auto-endcomments' (default t)
3712 Non-nil means a comment /* ... */ is set after the ends which ends
3713 cases, tasks, functions and modules.
3714 The type and name of the object will be set between the braces.
3715 `verilog-minimum-comment-distance' (default 10)
3716 Minimum distance (in lines) between begin and end required before a comment
3717 will be inserted. Setting this variable to zero results in every
3718 end acquiring a comment; the default avoids too many redundant
3719 comments in tight quarters.
3720 `verilog-auto-lineup' (default 'declarations)
3721 List of contexts where auto lineup of code should be done.
3723 Variables controlling other actions:
3725 `verilog-linter' (default surelint)
3726 Unix program to call to run the lint checker. This is the default
3727 command for \\[compile-command] and \\[verilog-auto-save-compile].
3729 See \\[customize] for the complete list of variables.
3731 AUTO expansion functions are, in part:
3733 \\[verilog-auto] Expand AUTO statements.
3734 \\[verilog-delete-auto] Remove the AUTOs.
3735 \\[verilog-inject-auto] Insert AUTOs for the first time.
3737 Some other functions are:
3739 \\[verilog-complete-word] Complete word with appropriate possibilities.
3740 \\[verilog-mark-defun] Mark function.
3741 \\[verilog-beg-of-defun] Move to beginning of current function.
3742 \\[verilog-end-of-defun] Move to end of current function.
3743 \\[verilog-label-be] Label matching begin ... end, fork ... join, etc statements.
3745 \\[verilog-comment-region] Put marked area in a comment.
3746 \\[verilog-uncomment-region] Uncomment an area commented with \\[verilog-comment-region].
3747 \\[verilog-insert-block] Insert begin ... end.
3748 \\[verilog-star-comment] Insert /* ... */.
3750 \\[verilog-sk-always] Insert an always @(AS) begin .. end block.
3751 \\[verilog-sk-begin] Insert a begin .. end block.
3752 \\[verilog-sk-case] Insert a case block, prompting for details.
3753 \\[verilog-sk-for] Insert a for (...) begin .. end block, prompting for details.
3754 \\[verilog-sk-generate] Insert a generate .. endgenerate block.
3755 \\[verilog-sk-header] Insert a header block at the top of file.
3756 \\[verilog-sk-initial] Insert an initial begin .. end block.
3757 \\[verilog-sk-fork] Insert a fork begin .. end .. join block.
3758 \\[verilog-sk-module] Insert a module .. (/*AUTOARG*/);.. endmodule block.
3759 \\[verilog-sk-ovm-class] Insert an OVM Class block.
3760 \\[verilog-sk-uvm-object] Insert an UVM Object block.
3761 \\[verilog-sk-uvm-component] Insert an UVM Component block.
3762 \\[verilog-sk-primitive] Insert a primitive .. (.. );.. endprimitive block.
3763 \\[verilog-sk-repeat] Insert a repeat (..) begin .. end block.
3764 \\[verilog-sk-specify] Insert a specify .. endspecify block.
3765 \\[verilog-sk-task] Insert a task .. begin .. end endtask block.
3766 \\[verilog-sk-while] Insert a while (...) begin .. end block, prompting for details.
3767 \\[verilog-sk-casex] Insert a casex (...) item: begin.. end endcase block, prompting for details.
3768 \\[verilog-sk-casez] Insert a casez (...) item: begin.. end endcase block, prompting for details.
3769 \\[verilog-sk-if] Insert an if (..) begin .. end block.
3770 \\[verilog-sk-else-if] Insert an else if (..) begin .. end block.
3771 \\[verilog-sk-comment] Insert a comment block.
3772 \\[verilog-sk-assign] Insert an assign .. = ..; statement.
3773 \\[verilog-sk-function] Insert a function .. begin .. end endfunction block.
3774 \\[verilog-sk-input] Insert an input declaration, prompting for details.
3775 \\[verilog-sk-output] Insert an output declaration, prompting for details.
3776 \\[verilog-sk-state-machine] Insert a state machine definition, prompting for details.
3777 \\[verilog-sk-inout] Insert an inout declaration, prompting for details.
3778 \\[verilog-sk-wire] Insert a wire declaration, prompting for details.
3779 \\[verilog-sk-reg] Insert a register declaration, prompting for details.
3780 \\[verilog-sk-define-signal] Define signal under point as a register at the top of the module.
3782 All key bindings can be seen in a Verilog-buffer with \\[describe-bindings].
3783 Key bindings specific to `verilog-mode-map' are:
3785 \\{verilog-mode-map}"
3786 :abbrev-table verilog-mode-abbrev-table
3787 (set (make-local-variable 'beginning-of-defun-function)
3788 'verilog-beg-of-defun)
3789 (set (make-local-variable 'end-of-defun-function)
3790 'verilog-end-of-defun)
3791 (set-syntax-table verilog-mode-syntax-table)
3792 (set (make-local-variable 'indent-line-function)
3793 #'verilog-indent-line-relative)
3794 (set (make-local-variable 'comment-indent-function) 'verilog-comment-indent)
3795 (set (make-local-variable 'parse-sexp-ignore-comments) nil)
3796 (set (make-local-variable 'comment-start) "// ")
3797 (set (make-local-variable 'comment-end) "")
3798 (set (make-local-variable 'comment-start-skip) "/\\*+ *\\|// *")
3799 (set (make-local-variable 'comment-multi-line) nil)
3800 ;; Set up for compilation
3801 (setq verilog-which-tool 1)
3802 (setq verilog-tool 'verilog-linter)
3803 (verilog-set-compile-command)
3804 (when (boundp 'hack-local-variables-hook) ; Also modify any file-local-variables
3805 (add-hook 'hack-local-variables-hook 'verilog-modify-compile-command t))
3808 (when (featurep 'xemacs)
3809 (easy-menu-add verilog-stmt-menu)
3810 (easy-menu-add verilog-menu)
3811 (setq mode-popup-menu (cons "Verilog Mode" verilog-stmt-menu)))
3813 ;; Stuff for GNU Emacs
3814 (set (make-local-variable 'font-lock-defaults)
3815 `((verilog-font-lock-keywords
3816 verilog-font-lock-keywords-1
3817 verilog-font-lock-keywords-2
3818 verilog-font-lock-keywords-3)
3820 ,(if (functionp 'syntax-ppss)
3821 ;; verilog-beg-of-defun uses syntax-ppss, and syntax-ppss uses
3822 ;; font-lock-beginning-of-syntax-function, so
3823 ;; font-lock-beginning-of-syntax-function, can't use
3824 ;; verilog-beg-of-defun.
3826 'verilog-beg-of-defun)))
3827 ;;------------------------------------------------------------
3828 ;; now hook in 'verilog-highlight-include-files (eldo-mode.el&spice-mode.el)
3829 ;; all buffer local:
3830 (unless noninteractive ; Else can't see the result, and change hooks are slow
3831 (when (featurep 'xemacs)
3832 (make-local-hook 'font-lock-mode-hook)
3833 (make-local-hook 'font-lock-after-fontify-buffer-hook); doesn't exist in Emacs
3834 (make-local-hook 'after-change-functions))
3835 (add-hook 'font-lock-mode-hook 'verilog-highlight-buffer t t)
3836 (add-hook 'font-lock-after-fontify-buffer-hook 'verilog-highlight-buffer t t) ; not in Emacs
3837 (add-hook 'after-change-functions 'verilog-highlight-region t t))
3839 ;; Tell imenu how to handle Verilog.
3840 (set (make-local-variable 'imenu-generic-expression)
3841 verilog-imenu-generic-expression)
3842 ;; Tell which-func-modes that imenu knows about verilog
3843 (when (and (boundp 'which-func-modes) (listp which-func-modes))
3844 (add-to-list 'which-func-modes 'verilog-mode))
3846 (when (boundp 'hs-special-modes-alist)
3847 (unless (assq 'verilog-mode hs-special-modes-alist)
3848 (setq hs-special-modes-alist
3849 (cons '(verilog-mode-mode "\\<begin\\>" "\\<end\\>" nil
3850 verilog-forward-sexp-function)
3851 hs-special-modes-alist))))
3854 (add-hook 'write-contents-hooks 'verilog-auto-save-check nil 'local)
3855 ;; verilog-mode-hook call added by define-derived-mode
3858 ;;; Electric functions:
3861 (defun electric-verilog-terminate-line (&optional arg)
3862 "Terminate line and indent next line.
3863 With optional ARG, remove existing end of line comments."
3865 ;; before that see if we are in a comment
3866 (let ((state (save-excursion (verilog-syntax-ppss))))
3868 ((nth 7 state) ; Inside // comment
3871 (delete-horizontal-space)
3876 (beginning-of-line)))
3877 (verilog-indent-line))
3878 ((nth 4 state) ; Inside any comment (hence /**/)
3880 (verilog-more-comment))
3882 ;; First, check if current line should be indented
3884 (delete-horizontal-space)
3886 (skip-chars-forward " \t")
3887 (if (looking-at verilog-auto-end-comment-lines-re)
3888 (let ((indent-str (verilog-indent-line)))
3889 ;; Maybe we should set some endcomments
3890 (if verilog-auto-endcomments
3891 (verilog-set-auto-endcomments indent-str arg))
3893 (delete-horizontal-space)
3900 (delete-horizontal-space)
3902 ;; see if we should line up assignments
3904 (if (or (eq 'all verilog-auto-lineup)
3905 (eq 'assignments verilog-auto-lineup))
3906 (verilog-pretty-expr t "\\(<\\|:\\)?=" ))
3910 (if verilog-auto-indent-on-newline
3911 (verilog-indent-line)))
3915 (defun electric-verilog-terminate-and-indent ()
3916 "Insert a newline and indent for the next statement."
3918 (electric-verilog-terminate-line 1))
3920 (defun electric-verilog-semi ()
3921 "Insert `;' character and reindent the line."
3923 (verilog-insert-last-command-event)
3925 (if (or (verilog-in-comment-or-string-p)
3926 (verilog-in-escaped-name-p))
3930 (verilog-forward-ws&directives)
3931 (verilog-indent-line))
3932 (if (and verilog-auto-newline
3933 (not (verilog-parenthesis-depth)))
3934 (electric-verilog-terminate-line))))
3936 (defun electric-verilog-semi-with-comment ()
3937 "Insert `;' character, reindent the line and indent for comment."
3942 (verilog-indent-line))
3943 (indent-for-comment))
3945 (defun electric-verilog-colon ()
3946 "Insert `:' and do all indentations except line indent on this line."
3948 (verilog-insert-last-command-event)
3949 ;; Do nothing if within string.
3951 (verilog-within-string)
3952 (not (verilog-in-case-region-p)))
3956 (lim (progn (verilog-beg-of-statement) (point))))
3958 (verilog-backward-case-item lim)
3959 (verilog-indent-line)))
3960 ;; (let ((verilog-tab-always-indent nil))
3961 ;; (verilog-indent-line))
3964 ;;(defun electric-verilog-equal ()
3965 ;; "Insert `=', and do indentation if within block."
3967 ;; (verilog-insert-last-command-event)
3968 ;; Could auto line up expressions, but not yet
3969 ;; (if (eq (car (verilog-calculate-indent)) 'block)
3970 ;; (let ((verilog-tab-always-indent nil))
3971 ;; (verilog-indent-command)))
3974 (defun electric-verilog-tick ()
3975 "Insert back-tick, and indent to column 0 if this is a CPP directive."
3977 (verilog-insert-last-command-event)
3979 (if (verilog-in-directive-p)
3980 (verilog-indent-line))))
3982 (defun electric-verilog-tab ()
3983 "Function called when TAB is pressed in Verilog mode."
3985 ;; If verilog-tab-always-indent, indent the beginning of the line.
3987 ;; The region is active, indent it.
3988 ((and (region-active-p)
3989 (not (eq (region-beginning) (region-end))))
3990 (indent-region (region-beginning) (region-end) nil))
3991 ((or verilog-tab-always-indent
3993 (skip-chars-backward " \t")
3995 (let* ((oldpnt (point))
3999 (skip-chars-forward " \t")
4000 (verilog-indent-line)
4001 (back-to-indentation)
4003 (if (< (point) boi-point)
4004 (back-to-indentation)
4005 (cond ((not verilog-tab-to-comment))
4009 (indent-for-comment)
4010 (when (and (eolp) (= oldpnt (point)))
4011 ;; kill existing comment
4013 (re-search-forward comment-start-skip oldpnt 'move)
4014 (goto-char (match-beginning 0))
4015 (skip-chars-backward " \t")
4016 (kill-region (point) oldpnt)))))))
4017 (t (progn (insert "\t")))))
4020 ;;; Interactive functions:
4023 (defun verilog-indent-buffer ()
4024 "Indent-region the entire buffer as Verilog code.
4025 To call this from the command line, see \\[verilog-batch-indent]."
4028 (indent-region (point-min) (point-max) nil))
4030 (defun verilog-insert-block ()
4031 "Insert Verilog begin ... end; block in the code with right indentation."
4033 (verilog-indent-line)
4035 (electric-verilog-terminate-line)
4037 (electric-verilog-terminate-line)
4040 (verilog-indent-line)))
4042 (defun verilog-star-comment ()
4043 "Insert Verilog star comment at point."
4045 (verilog-indent-line)
4053 (defun verilog-insert-1 (fmt max)
4054 "Use format string FMT to insert integers 0 to MAX - 1.
4055 Inserts one integer per line, at the current column. Stops early
4056 if it reaches the end of the buffer."
4057 (let ((col (current-column))
4061 (insert (format fmt n))
4063 ;; Note that this function does not bother to check for lines
4064 ;; shorter than col.
4068 (move-to-column col))))))
4070 (defun verilog-insert-indices (max)
4071 "Insert a set of indices into a rectangle.
4072 The upper left corner is defined by point. Indices begin with 0
4073 and extend to the MAX - 1. If no prefix arg is given, the user
4074 is prompted for a value. The indices are surrounded by square
4075 brackets \[]. For example, the following code with the point
4076 located after the first 'a' gives:
4082 a = b ==> insert-indices ==> a[ 4] = b
4088 (interactive "NMAX: ")
4089 (verilog-insert-1 "[%3d]" max))
4091 (defun verilog-generate-numbers (max)
4092 "Insert a set of generated numbers into a rectangle.
4093 The upper left corner is defined by point. The numbers are padded to three
4094 digits, starting with 000 and extending to (MAX - 1). If no prefix argument
4095 is supplied, then the user is prompted for the MAX number. Consider the
4096 following code fragment:
4102 buf buf ==> generate-numbers ==> buf buf004
4108 (interactive "NMAX: ")
4109 (verilog-insert-1 "%3.3d" max))
4111 (defun verilog-mark-defun ()
4112 "Mark the current Verilog function (or procedure).
4113 This puts the mark at the end, and point at the beginning."
4115 (if (featurep 'xemacs)
4118 (verilog-end-of-defun)
4120 (verilog-beg-of-defun)
4121 (if (fboundp 'zmacs-activate-region)
4122 (zmacs-activate-region)))
4125 (defun verilog-comment-region (start end)
4126 ;; checkdoc-params: (start end)
4127 "Put the region into a Verilog comment.
4128 The comments that are in this area are \"deformed\":
4129 `*)' becomes `!(*' and `}' becomes `!{'.
4130 These deformed comments are returned to normal if you use
4131 \\[verilog-uncomment-region] to undo the commenting.
4133 The commented area starts with `verilog-exclude-str-start', and ends with
4134 `verilog-exclude-str-end'. But if you change these variables,
4135 \\[verilog-uncomment-region] won't recognize the comments."
4138 ;; Insert start and endcomments
4140 (if (and (save-excursion (skip-chars-forward " \t") (eolp))
4141 (not (save-excursion (skip-chars-backward " \t") (bolp))))
4143 (beginning-of-line))
4144 (insert verilog-exclude-str-end)
4149 (insert verilog-exclude-str-start)
4151 ;; Replace end-comments within commented area
4154 (while (re-search-backward "\\*/" start t)
4155 (replace-match "*-/" t t)))
4157 (let ((s+1 (1+ start)))
4158 (while (re-search-backward "/\\*" s+1 t)
4159 (replace-match "/-*" t t))))))
4161 (defun verilog-uncomment-region ()
4162 "Uncomment a commented area; change deformed comments back to normal.
4163 This command does nothing if the pointer is not in a commented
4164 area. See also `verilog-comment-region'."
4167 (let ((start (point))
4169 ;; Find the boundaries of the comment
4171 (setq start (progn (search-backward verilog-exclude-str-start nil t)
4173 (setq end (progn (search-forward verilog-exclude-str-end nil t)
4175 ;; Check if we're really inside a comment
4176 (if (or (equal start (point)) (<= end (point)))
4177 (message "Not standing within commented area.")
4179 ;; Remove endcomment
4182 (let ((pos (point)))
4184 (delete-region pos (1+ (point))))
4185 ;; Change comments back to normal
4187 (while (re-search-backward "\\*-/" start t)
4188 (replace-match "*/" t t)))
4190 (while (re-search-backward "/-\\*" start t)
4191 (replace-match "/*" t t)))
4192 ;; Remove start comment
4195 (let ((pos (point)))
4197 (delete-region pos (1+ (point)))))))))
4199 (defun verilog-beg-of-defun ()
4200 "Move backward to the beginning of the current function or procedure."
4202 (verilog-re-search-backward verilog-defun-re nil 'move))
4204 (defun verilog-beg-of-defun-quick ()
4205 "Move backward to the beginning of the current function or procedure.
4206 Uses `verilog-scan' cache."
4208 (verilog-re-search-backward-quick verilog-defun-re nil 'move))
4210 (defun verilog-end-of-defun ()
4211 "Move forward to the end of the current function or procedure."
4213 (verilog-re-search-forward verilog-end-defun-re nil 'move))
4215 (defun verilog-get-end-of-defun ()
4217 (cond ((verilog-re-search-forward-quick verilog-end-defun-re nil t)
4220 (error "%s: Can't find endmodule" (verilog-point-text))
4223 (defun verilog-label-be ()
4224 "Label matching begin ... end, fork ... join and case ... endcase statements."
4227 (case-fold-search nil)
4230 (verilog-beg-of-defun)
4233 (verilog-end-of-defun)
4235 (goto-char (marker-position b))
4237 (message "Relabeling module..."))
4239 (> (marker-position e) (point))
4240 (verilog-re-search-forward
4241 verilog-auto-end-comment-lines-re
4243 (goto-char (match-beginning 0))
4244 (let ((indent-str (verilog-indent-line)))
4245 (verilog-set-auto-endcomments indent-str 't)
4247 (delete-horizontal-space))
4249 (if (= 9 (% cnt 10))
4250 (message "%d..." cnt)))
4255 (message "%d lines auto commented" cnt))))
4257 (defun verilog-beg-of-statement ()
4258 "Move backward to beginning of statement."
4260 ;; Move back token by token until we see the end
4261 ;; of some earlier line.
4264 ;; If the current point does not begin a new
4265 ;; statement, as in the character ahead of us is a ';', or SOF
4266 ;; or the string after us unambiguously starts a statement,
4267 ;; or the token before us unambiguously ends a statement,
4268 ;; then move back a token and test again.
4270 ;; stop if beginning of buffer
4272 ;; stop if looking at a pre-processor directive
4273 (looking-at "`\\w+")
4274 ;; stop if we find a ;
4275 (= (preceding-char) ?\;)
4276 ;; stop if we see a named coverpoint
4277 (looking-at "\\w+\\W*:\\W*\\(coverpoint\\|cross\\|constraint\\)")
4278 ;; keep going if we are in the middle of a word
4279 (not (or (looking-at "\\<") (forward-word -1)))
4280 ;; stop if we see an assertion (perhaps labeled)
4282 (looking-at "\\(\\w+\\W*:\\W*\\)?\\(\\<\\(assert\\|assume\\|cover\\)\\>\\s-+\\<property\\>\\)\\|\\(\\<assert\\>\\)")
4286 (verilog-backward-token)
4287 (if (and (looking-at verilog-label-re)
4288 (not (looking-at verilog-end-block-re)))
4291 ;; stop if we see an extended complete reg, perhaps a complete one
4293 (looking-at verilog-complete-reg)
4295 (while (and (looking-at verilog-extended-complete-re)
4296 (progn (setq p (point))
4297 (verilog-backward-token)
4300 ;; stop if we see a complete reg (previous found extended ones)
4301 (looking-at verilog-basic-complete-re)
4302 ;; stop if previous token is an ender
4304 (verilog-backward-token)
4305 (looking-at verilog-end-block-re))))
4306 (verilog-backward-syntactic-ws)
4307 (verilog-backward-token))
4308 ;; Now point is where the previous line ended.
4309 (verilog-forward-syntactic-ws)
4310 ;; Skip forward over any preprocessor directives, as they have wacky indentation
4311 (if (looking-at verilog-preprocessor-re)
4312 (progn (goto-char (match-end 0))
4313 (verilog-forward-syntactic-ws)))))
4315 (defun verilog-beg-of-statement-1 ()
4316 "Move backward to beginning of statement."
4318 (if (verilog-in-comment-p)
4319 (verilog-backward-syntactic-ws))
4322 (while (not (looking-at verilog-complete-reg))
4324 (verilog-backward-syntactic-ws)
4326 (= (preceding-char) ?\;)
4328 (verilog-backward-token)
4329 (looking-at verilog-ends-re)))
4333 (verilog-forward-syntactic-ws)))
4336 ;; (not (looking-at verilog-complete-reg))
4338 ;; (not (= (preceding-char) ?\;)))
4339 ;; (verilog-backward-token)
4340 ;; (verilog-backward-syntactic-ws)
4341 ;; (setq pt (point)))
4343 ;; ;(verilog-forward-syntactic-ws)
4345 (defun verilog-end-of-statement ()
4346 "Move forward to end of current statement."
4350 ((verilog-in-directive-p)
4354 ((looking-at verilog-beg-block-re)
4355 (verilog-forward-sexp))
4357 ((equal (char-after) ?\})
4360 ;; Skip to end of statement
4361 ((condition-case nil
4366 (verilog-skip-forward-comment-or-string)
4369 (cond ((looking-at "[ \t]*;")
4370 (skip-chars-forward "^;")
4372 (throw 'found (point)))
4375 (looking-at verilog-beg-block-re))
4376 (goto-char (match-beginning 0))
4378 ((looking-at "[ \t]*)")
4379 (throw 'found (point)))
4381 (throw 'found (point)))
4387 ;; Skip a whole block
4390 (verilog-re-search-forward verilog-end-statement-re nil 'move)
4391 (setq nest (if (match-end 1)
4395 (throw 'found (point)))
4397 (throw 'found (verilog-end-of-statement))))))
4400 (defun verilog-in-case-region-p ()
4401 "Return true if in a case region.
4402 More specifically, point @ in the line foo : @ begin"
4406 (progn (verilog-forward-syntactic-ws)
4407 (looking-at "\\<begin\\>"))
4408 (progn (verilog-backward-syntactic-ws)
4409 (= (preceding-char) ?\:)))
4413 (verilog-re-search-backward
4414 (concat "\\(\\<module\\>\\)\\|\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|"
4415 "\\(\\<endcase\\>\\)\\>")
4419 (setq nest (1+ nest)))
4423 (setq nest (1- nest)))
4425 (throw 'found (= nest 0)))))))
4428 (defun verilog-backward-up-list (arg)
4429 "Call `backward-up-list' ARG, ignoring comments."
4430 (let ((parse-sexp-ignore-comments t))
4431 (backward-up-list arg)))
4433 (defun verilog-forward-sexp-cmt (arg)
4434 "Call `forward-sexp' ARG, inside comments."
4435 (let ((parse-sexp-ignore-comments nil))
4436 (forward-sexp arg)))
4438 (defun verilog-forward-sexp-ign-cmt (arg)
4439 "Call `forward-sexp' ARG, ignoring comments."
4440 (let ((parse-sexp-ignore-comments t))
4441 (forward-sexp arg)))
4443 (defun verilog-in-generate-region-p ()
4444 "Return true if in a generate region.
4445 More specifically, after a generate and before an endgenerate."
4452 (verilog-re-search-backward
4453 "\\<\\(module\\)\\|\\(generate\\)\\|\\(endgenerate\\)\\>" nil 'move)
4455 ((match-end 1) ; module - we have crawled out
4457 ((match-end 2) ; generate
4458 (setq nest (1- nest)))
4459 ((match-end 3) ; endgenerate
4460 (setq nest (1+ nest))))))))
4461 (= nest 0) )) ; return nest
4463 (defun verilog-in-fork-region-p ()
4464 "Return true if between a fork and join."
4466 (let ((lim (save-excursion (verilog-beg-of-defun) (point)))
4471 (verilog-re-search-backward "\\<\\(fork\\)\\|\\(join\\(_any\\|_none\\)?\\)\\>" lim 'move)
4473 ((match-end 1) ; fork
4474 (setq nest (1- nest)))
4475 ((match-end 2) ; join
4476 (setq nest (1+ nest)))))))
4477 (= nest 0) )) ; return nest
4479 (defun verilog-in-deferred-immediate-final-p ()
4480 "Return true if inside an 'assert/assume/cover final' statement."
4482 (and (looking-at "final")
4483 (verilog-looking-back "\\<\\(?:assert\\|assume\\|cover\\)\\>\\s-+" nil))
4486 (defun verilog-backward-case-item (lim)
4487 "Skip backward to nearest enclosing case item.
4488 Limit search to point LIM."
4494 (verilog-re-search-backward verilog-endcomment-reason-re
4497 ;; Try to find the real :
4498 (if (save-excursion (search-backward ":" lim1 t))
4504 (verilog-re-search-backward "\\(\\[\\)\\|\\(\\]\\)\\|\\(:\\)"
4508 (setq colon (1+ colon))
4510 (error "%s: unbalanced [" (verilog-point-text))))
4512 (setq colon (1- colon)))
4515 (setq colon (1+ colon)))))
4516 ;; Skip back to beginning of case item
4517 (skip-chars-backward "\t ")
4518 (verilog-skip-backward-comment-or-string)
4523 (verilog-re-search-backward
4524 "\\<\\(case[zx]?\\)\\>\\|;\\|\\<end\\>" nil 'move)
4528 (goto-char (match-end 1))
4529 (verilog-forward-ws&directives)
4530 (if (looking-at "(")
4533 (verilog-forward-ws&directives)))
4536 (goto-char (match-end 0))
4537 (verilog-forward-ws&directives)
4539 (error "Malformed case item"))))
4540 (setq str (buffer-substring b e))
4544 "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
4545 (setq str (concat (substring str 0 e) "...")))
4549 ;;; Other functions:
4552 (defun verilog-kill-existing-comment ()
4553 "Kill auto comment on this line."
4561 (search-forward "//" e t))))
4563 (delete-region (- b 2) e)))))
4565 (defconst verilog-directive-nest-re
4566 (concat "\\(`else\\>\\)\\|"
4567 "\\(`endif\\>\\)\\|"
4569 "\\(`ifdef\\>\\)\\|"
4570 "\\(`ifndef\\>\\)\\|"
4573 (defun verilog-set-auto-endcomments (indent-str kill-existing-comment)
4574 "Add ending comment with given INDENT-STR.
4575 With KILL-EXISTING-COMMENT, remove what was there before.
4576 Insert `// case: 7 ' or `// NAME ' on this line if appropriate.
4577 Insert `// case expr ' if this line ends a case block.
4578 Insert `// ifdef FOO ' if this line ends code conditional on FOO.
4579 Insert `// NAME ' if this line ends a function, task, module,
4580 primitive or interface named NAME."
4583 (; Comment close preprocessor directives
4585 (looking-at "\\(`endif\\)\\|\\(`else\\)")
4586 (or kill-existing-comment
4587 (not (save-excursion
4589 (search-backward "//" (point-at-bol) t)))))
4592 (else (if (match-end 2) "!" " ")))
4594 (if kill-existing-comment
4595 (verilog-kill-existing-comment))
4596 (delete-horizontal-space)
4599 (while (and (/= nest 0)
4600 (verilog-re-search-backward verilog-directive-nest-re nil 'move))
4602 ((match-end 1) ; `else
4605 ((match-end 2) ; `endif
4606 (setq nest (1+ nest)))
4607 ((match-end 3) ; `if
4608 (setq nest (1- nest)))
4609 ((match-end 4) ; `ifdef
4610 (setq nest (1- nest)))
4611 ((match-end 5) ; `ifndef
4612 (setq nest (1- nest)))
4613 ((match-end 6) ; `elsif
4624 (skip-chars-forward "^ \t")
4625 (verilog-forward-syntactic-ws)
4628 (skip-chars-forward "a-zA-Z0-9_")
4631 (if (> (count-lines (point) b) verilog-minimum-comment-distance)
4632 (insert (concat " // " else m " " (buffer-substring b e))))
4634 (insert " // unmatched `else, `elsif or `endif")
4637 (; Comment close case/class/function/task/module and named block
4638 (and (looking-at "\\<end")
4639 (or kill-existing-comment
4640 (not (save-excursion
4642 (search-backward "//" (point-at-bol) t)))))
4643 (let ((type (car indent-str)))
4644 (unless (eq type 'declaration)
4645 (unless (looking-at (concat "\\(" verilog-end-block-ordered-re "\\)[ \t]*:")) ; ignore named ends
4646 (if (looking-at verilog-end-block-ordered-re)
4648 (;- This is a case block; search back for the start of this case
4649 (match-end 1) ; of verilog-end-block-ordered-re
4652 (str "UNMATCHED!!"))
4654 (verilog-leap-to-head)
4656 ((looking-at "\\<randcase\\>")
4657 (setq str "randcase")
4659 ((looking-at "\\(\\(unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\)")
4660 (goto-char (match-end 0))
4661 (setq str (concat (match-string 0) " " (verilog-get-expr)))
4665 (if kill-existing-comment
4666 (verilog-kill-existing-comment))
4667 (delete-horizontal-space)
4668 (insert (concat " // " str ))
4669 (if err (ding 't))))
4671 (;- This is a begin..end block
4672 (match-end 2) ; of verilog-end-block-ordered-re
4673 (let ((str " // UNMATCHED !!")
4679 (verilog-leap-to-head)
4680 (setq there (point))
4681 (if (not (match-end 0))
4685 (if kill-existing-comment
4686 (verilog-kill-existing-comment))
4687 (delete-horizontal-space)
4691 (save-excursion (verilog-beg-of-defun) (point)))
4694 (;-- handle named block differently
4695 (looking-at verilog-named-block-re)
4696 (search-forward ":")
4697 (setq there (point))
4698 (setq str (verilog-get-expr))
4700 (setq str (concat " // block: " str )))
4702 ((verilog-in-case-region-p) ;-- handle case item differently
4704 (setq str (verilog-backward-case-item lim))
4705 (setq there (point))
4707 (setq str (concat " // case: " str )))
4709 (;- try to find "reason" for this begin
4713 ;; (verilog-backward-token)
4714 (verilog-beg-of-statement)
4718 ((looking-at verilog-endcomment-reason-re)
4719 (setq there (match-end 0))
4720 (setq cntx (concat (match-string 0) " "))
4726 (if (and (verilog-continued-line)
4727 (looking-at "\\<repeat\\>\\|\\<wait\\>\\|\\<always\\>"))
4729 (goto-char (match-end 0))
4730 (setq there (point))
4732 (concat " // " (match-string 0) " " (verilog-get-expr))))
4738 ( reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)\\|\\(assert\\)"))
4740 (while (verilog-re-search-backward reg nil 'move)
4742 ((match-end 1) ; begin
4743 (setq nest (1- nest)))
4744 ((match-end 2) ; end
4745 (setq nest (1+ nest)))
4749 (goto-char (match-end 0))
4750 (setq there (point))
4752 (setq str (verilog-get-expr))
4753 (setq str (concat " // else: !if" str ))
4758 (goto-char (match-end 0))
4759 (setq there (point))
4761 (setq str (verilog-get-expr))
4762 (setq str (concat " // else: !assert " str ))
4763 (throw 'skip 1)))))))))
4768 (reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)\\|\\(assert\\)"))
4770 (while (verilog-re-search-backward reg nil 'move)
4772 ((match-end 1) ; begin
4773 (setq nest (1- nest)))
4774 ((match-end 2) ; end
4775 (setq nest (1+ nest)))
4779 (goto-char (match-end 0))
4780 (setq there (point))
4782 (setq str (verilog-get-expr))
4783 (setq str (concat " // else: !if" str ))
4788 (goto-char (match-end 0))
4789 (setq there (point))
4791 (setq str (verilog-get-expr))
4792 (setq str (concat " // else: !assert " str ))
4793 (throw 'skip 1)))))))))
4795 (; always, always_comb, always_latch w/o @...
4797 (goto-char (match-end 0))
4798 (setq there (point))
4800 (setq str (concat " // " cntx )))
4802 (;- task/function/initial et cetera
4805 (goto-char (match-end 0))
4806 (setq there (point))
4808 (setq str (concat " // " cntx (verilog-get-expr))))
4811 (setq str " // auto-endcomment confused "))))
4814 (verilog-in-case-region-p) ;-- handle case item differently
4816 (setq there (point))
4818 (setq str (verilog-backward-case-item lim))))
4820 (setq str (concat " // case: " str )))
4822 ((verilog-in-fork-region-p)
4824 (setq str " // fork branch" ))
4826 ((looking-at "\\<end\\>")
4829 (verilog-forward-syntactic-ws)
4831 (setq str (verilog-get-expr))
4832 (setq str (concat " // " cntx str )))
4837 (if kill-existing-comment
4838 (verilog-kill-existing-comment))
4839 (delete-horizontal-space)
4841 (> (count-lines here there) verilog-minimum-comment-distance))
4845 (;- this is endclass, which can be nested
4846 (match-end 11) ; of verilog-end-block-ordered-re
4849 (reg "\\<\\(class\\)\\|\\(endclass\\)\\|\\(package\\|primitive\\|\\(macro\\)?module\\)\\>")
4853 (while (verilog-re-search-backward reg nil 'move)
4855 ((match-end 3) ; endclass
4857 (setq string "unmatched endclass")
4860 ((match-end 2) ; endclass
4861 (setq nest (1+ nest)))
4863 ((match-end 1) ; class
4864 (setq nest (1- nest))
4867 (goto-char (match-end 0))
4870 (skip-chars-forward "^ \t")
4871 (verilog-forward-ws&directives)
4874 (skip-chars-forward "a-zA-Z0-9_")
4876 (setq string (buffer-substring b e)))
4880 (if kill-existing-comment
4881 (verilog-kill-existing-comment))
4882 (delete-horizontal-space)
4883 (insert (concat " // " string ))))
4885 (; - this is end{function,generate,task,module,primitive,table,generate}
4886 ;; - which can not be nested.
4888 (let (string reg (name-re nil))
4890 (if kill-existing-comment
4892 (verilog-kill-existing-comment)))
4893 (delete-horizontal-space)
4896 ((match-end 5) ; of verilog-end-block-ordered-re
4897 (setq reg "\\(\\<function\\>\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
4898 (setq name-re "\\w+\\(?:\n\\|\\s-\\)*[(;]"))
4899 ((match-end 6) ; of verilog-end-block-ordered-re
4900 (setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
4901 (setq name-re "\\w+\\(?:\n\\|\\s-\\)*[(;]"))
4902 ((match-end 7) ; of verilog-end-block-ordered-re
4903 (setq reg "\\(\\<\\(macro\\)?module\\>\\)\\|\\<endmodule\\>"))
4904 ((match-end 8) ; of verilog-end-block-ordered-re
4905 (setq reg "\\(\\<primitive\\>\\)\\|\\(\\<\\(endprimitive\\|package\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4906 ((match-end 9) ; of verilog-end-block-ordered-re
4907 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<\\(endinterface\\|package\\|primitive\\|\\(macro\\)?module\\)\\>\\)"))
4908 ((match-end 10) ; of verilog-end-block-ordered-re
4909 (setq reg "\\(\\<package\\>\\)\\|\\(\\<\\(endpackage\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4910 ((match-end 11) ; of verilog-end-block-ordered-re
4911 (setq reg "\\(\\<class\\>\\)\\|\\(\\<\\(endclass\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4912 ((match-end 12) ; of verilog-end-block-ordered-re
4913 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<\\(endcovergroup\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4914 ((match-end 13) ; of verilog-end-block-ordered-re
4915 (setq reg "\\(\\<program\\>\\)\\|\\(\\<\\(endprogram\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4916 ((match-end 14) ; of verilog-end-block-ordered-re
4917 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<\\(endsequence\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4918 ((match-end 15) ; of verilog-end-block-ordered-re
4919 (setq reg "\\(\\<clocking\\>\\)\\|\\<endclocking\\>"))
4920 ((match-end 16) ; of verilog-end-block-ordered-re
4921 (setq reg "\\(\\<property\\>\\)\\|\\<endproperty\\>"))
4923 (t (error "Problem in verilog-set-auto-endcomments")))
4926 (verilog-re-search-backward reg nil 'move)
4930 (skip-chars-forward "^ \t")
4931 (verilog-forward-ws&directives)
4932 (if (looking-at "static\\|automatic")
4934 (goto-char (match-end 0))
4935 (verilog-forward-ws&directives)))
4936 (if (and name-re (verilog-re-search-forward name-re nil 'move))
4938 (goto-char (match-beginning 0))
4939 (verilog-forward-ws&directives)))
4942 (skip-chars-forward "a-zA-Z0-9_")
4944 (setq string (buffer-substring b e)))
4947 (setq string "unmatched end(function|task|module|primitive|interface|package|class|clocking)")))))
4949 (insert (concat " // " string )))
4952 (defun verilog-get-expr()
4953 "Grab expression at point, e.g., case ( a | b & (c ^d))."
4955 (verilog-forward-syntactic-ws)
4956 (skip-chars-forward " \t")
4962 (verilog-forward-syntactic-ws)
4963 (if (looking-at "(")
4966 (while (and (/= par 0)
4967 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
4970 (setq par (1+ par)))
4972 (setq par (1- par)))))))
4976 (while (and (/= par 0)
4977 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
4980 (setq par (1+ par)))
4982 (setq par (1- par)))))
4986 (while (and (/= par 0)
4987 (verilog-re-search-forward "\\(\\[\\)\\|\\(\\]\\)" nil 'move))
4990 (setq par (1+ par)))
4992 (setq par (1- par)))))
4993 (verilog-forward-syntactic-ws)
4994 (skip-chars-forward "^ \t\n\f")
4996 ((looking-at "/[/\\*]")
4999 (skip-chars-forward "^: \t\n\f")
5001 (str (buffer-substring b e)))
5002 (if (setq e (string-match "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
5003 (setq str (concat (substring str 0 e) "...")))
5006 (defun verilog-expand-vector ()
5007 "Take a signal vector on the current line and expand it to multiple lines.
5008 Useful for creating tri's and other expanded fields."
5010 (verilog-expand-vector-internal "[" "]"))
5012 (defun verilog-expand-vector-internal (bra ket)
5013 "Given BRA, the start brace and KET, the end brace, expand one line into many lines."
5016 (let ((signal-string (buffer-substring (point)
5018 (end-of-line) (point)))))
5022 "\\([0-9]*\\)\\(:[0-9]*\\|\\)\\(::[0-9---]*\\|\\)"
5024 "\\(.*\\)$") signal-string)
5025 (let* ((sig-head (match-string 1 signal-string))
5026 (vec-start (string-to-number (match-string 2 signal-string)))
5027 (vec-end (if (= (match-beginning 3) (match-end 3))
5030 (substring signal-string (1+ (match-beginning 3))
5033 (if (= (match-beginning 4) (match-end 4))
5036 (substring signal-string (+ 2 (match-beginning 4))
5038 (sig-tail (match-string 5 signal-string))
5043 (let ((tmp vec-start))
5044 (setq vec-start vec-end
5046 vec-range (- vec-range))))
5047 (if (< vec-end vec-start)
5048 (while (<= vec-end vec-start)
5049 (setq vec (append vec (list vec-start)))
5050 (setq vec-start (- vec-start vec-range)))
5051 (while (<= vec-start vec-end)
5052 (setq vec (append vec (list vec-start)))
5053 (setq vec-start (+ vec-start vec-range))))
5055 ;; Delete current line
5056 (delete-region (point) (progn (forward-line 0) (point)))
5060 (insert (concat sig-head bra
5061 (int-to-string (car vec)) ket sig-tail "\n"))
5062 (setq vec (cdr vec)))
5067 (defun verilog-strip-comments ()
5068 "Strip all comments from the Verilog code."
5070 (goto-char (point-min))
5071 (while (re-search-forward "//" nil t)
5072 (if (verilog-within-string)
5073 (re-search-forward "\"" nil t)
5074 (if (verilog-in-star-comment-p)
5075 (re-search-forward "\*/" nil t)
5076 (let ((bpt (- (point) 2)))
5078 (delete-region bpt (point))))))
5080 (goto-char (point-min))
5081 (while (re-search-forward "/\\*" nil t)
5082 (if (verilog-within-string)
5083 (re-search-forward "\"" nil t)
5084 (let ((bpt (- (point) 2)))
5085 (re-search-forward "\\*/")
5086 (delete-region bpt (point))))))
5088 (defun verilog-one-line ()
5089 "Convert structural Verilog instances to occupy one line."
5091 (goto-char (point-min))
5092 (while (re-search-forward "\\([^;]\\)[ \t]*\n[ \t]*" nil t)
5093 (replace-match "\\1 " nil nil)))
5095 (defun verilog-linter-name ()
5096 "Return name of linter, either surelint or verilint."
5097 (let ((compile-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
5099 (lint-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
5101 (cond ((equal compile-word1 "surelint") `surelint)
5102 ((equal compile-word1 "verilint") `verilint)
5103 ((equal lint-word1 "surelint") `surelint)
5104 ((equal lint-word1 "verilint") `verilint)
5105 (t `surelint)))) ; back compatibility
5107 (defun verilog-lint-off ()
5108 "Convert a Verilog linter warning line into a disable statement.
5110 pci_bfm_null.v, line 46: Unused input: pci_rst_
5111 becomes a comment for the appropriate tool.
5113 The first word of the `compile-command' or `verilog-linter'
5114 variables is used to determine which product is being used.
5116 See \\[verilog-surelint-off] and \\[verilog-verilint-off]."
5118 (let ((linter (verilog-linter-name)))
5119 (cond ((equal linter `surelint)
5120 (verilog-surelint-off))
5121 ((equal linter `verilint)
5122 (verilog-verilint-off))
5123 (t (error "Linter name not set")))))
5125 (defvar compilation-last-buffer)
5126 (defvar next-error-last-buffer)
5128 (defun verilog-surelint-off ()
5129 "Convert a SureLint warning line into a disable statement.
5130 Run from Verilog source window; assumes there is a *compile* buffer
5131 with point set appropriately.
5134 WARNING [STD-UDDONX]: xx.v, line 8: output out is never assigned.
5136 // surefire lint_line_off UDDONX"
5138 (let ((buff (if (boundp 'next-error-last-buffer)
5139 next-error-last-buffer
5140 compilation-last-buffer)))
5141 (when (buffer-live-p buff)
5143 (switch-to-buffer buff)
5146 (looking-at "\\(INFO\\|WARNING\\|ERROR\\) \\[[^-]+-\\([^]]+\\)\\]: \\([^,]+\\), line \\([0-9]+\\): \\(.*\\)$")
5147 (let* ((code (match-string 2))
5148 (file (match-string 3))
5149 (line (match-string 4))
5150 (buffer (get-file-buffer file))
5155 (and (file-exists-p file)
5156 (find-file-noselect file)))
5158 (let* ((pop-up-windows t))
5159 (let ((name (expand-file-name
5161 (format "Find this error in: (default %s) "
5164 (if (file-directory-p name)
5165 (setq name (expand-file-name filename name)))
5167 (and (file-exists-p name)
5168 (find-file-noselect name))))))))
5169 (switch-to-buffer buffer)
5170 (goto-char (point-min))
5171 (forward-line (- (string-to-number line)))
5175 ((verilog-in-slash-comment-p)
5176 (re-search-backward "//")
5178 ((looking-at "// surefire lint_off_line ")
5179 (goto-char (match-end 0))
5180 (let ((lim (point-at-eol)))
5181 (if (re-search-forward code lim 'move)
5183 (insert (concat " " code)))))
5186 ((verilog-in-star-comment-p)
5187 (re-search-backward "/\*")
5188 (insert (format " // surefire lint_off_line %6s" code )))
5190 (insert (format " // surefire lint_off_line %6s" code ))
5193 (defun verilog-verilint-off ()
5194 "Convert a Verilint warning line into a disable statement.
5197 (W240) pci_bfm_null.v, line 46: Unused input: pci_rst_
5199 //Verilint 240 off // WARNING: Unused input"
5203 (when (looking-at "\\(.*\\)([WE]\\([0-9A-Z]+\\)).*,\\s +line\\s +[0-9]+:\\s +\\([^:\n]+\\):?.*$")
5204 (replace-match (format
5205 ;; %3s makes numbers 1-999 line up nicely
5206 "\\1//Verilint %3s off // WARNING: \\3"
5209 (verilog-indent-line))))
5211 (defun verilog-auto-save-compile ()
5212 "Update automatics with \\[verilog-auto], save the buffer, and compile."
5214 (verilog-auto) ; Always do it for safety
5216 (compile compile-command))
5218 (defun verilog-preprocess (&optional command filename)
5219 "Preprocess the buffer, similar to `compile', but put output in Verilog-Mode.
5220 Takes optional COMMAND or defaults to `verilog-preprocessor', and
5221 FILENAME to find directory to run in, or defaults to `buffer-file-name'."
5224 (let ((default (verilog-expand-command verilog-preprocessor)))
5225 (set (make-local-variable `verilog-preprocessor)
5226 (read-from-minibuffer "Run Preprocessor (like this): "
5228 'verilog-preprocess-history default)))))
5229 (unless command (setq command (verilog-expand-command verilog-preprocessor)))
5230 (let* ((fontlocked (and (boundp 'font-lock-mode) font-lock-mode))
5231 (dir (file-name-directory (or filename buffer-file-name)))
5232 (cmd (concat "cd " dir "; " command)))
5233 (with-output-to-temp-buffer "*Verilog-Preprocessed*"
5234 (with-current-buffer (get-buffer "*Verilog-Preprocessed*")
5235 (insert (concat "// " cmd "\n"))
5236 (call-process shell-file-name nil t nil shell-command-switch cmd)
5238 ;; Without this force, it takes a few idle seconds
5239 ;; to get the color, which is very jarring
5240 (unless (fboundp 'font-lock-ensure)
5241 ;; We should use font-lock-ensure in preference to
5242 ;; font-lock-fontify-buffer, but IIUC the problem this is supposed to
5243 ;; solve only appears in Emacsen older than font-lock-ensure anyway.
5244 ;; So avoid bytecomp's interactive-only by going through intern.
5245 (when fontlocked (funcall (intern "font-lock-fontify-buffer"))))))))
5250 (defun verilog-warn (string &rest args)
5251 "Print a warning with `format' using STRING and optional ARGS."
5252 (apply 'message (concat "%%Warning: " string) args))
5254 (defun verilog-warn-error (string &rest args)
5255 "Call `error' using STRING and optional ARGS.
5256 If `verilog-warn-fatal' is non-nil, call `verilog-warn' instead."
5257 (if verilog-warn-fatal
5258 (apply 'error string args)
5259 (apply 'verilog-warn string args)))
5261 (defmacro verilog-batch-error-wrapper (&rest body)
5262 "Execute BODY and add error prefix to any errors found.
5263 This lets programs calling batch mode to easily extract error messages."
5264 `(let ((verilog-warn-fatal nil))
5268 (error "%%Error: %s%s" (error-message-string err)
5269 (if (featurep 'xemacs) "\n" "")))))) ; XEmacs forgets to add a newline
5271 (defun verilog-batch-execute-func (funref &optional no-save)
5272 "Internal processing of a batch command.
5273 Runs FUNREF on all command arguments.
5274 Save the result unless optional NO-SAVE is t."
5275 (verilog-batch-error-wrapper
5276 ;; Setting global variables like that is *VERY NASTY* !!! --Stef
5277 ;; However, this function is called only when Emacs is being used as
5278 ;; a standalone language instead of as an editor, so we'll live.
5280 ;; General globals needed
5281 (setq make-backup-files nil)
5282 (setq-default make-backup-files nil)
5283 (setq enable-local-variables t)
5284 (setq enable-local-eval t)
5285 (setq create-lockfiles nil)
5286 ;; Make sure any sub-files we read get proper mode
5287 (setq-default major-mode 'verilog-mode)
5288 ;; Ditto files already read in
5289 ;; Remember buffer list, so don't later pickup any verilog-getopt files
5290 (let ((orig-buffer-list (buffer-list)))
5292 (when (buffer-file-name buf)
5293 (with-current-buffer buf
5295 (verilog-auto-reeval-locals)
5296 (verilog-getopt-flags))))
5298 ;; Process the files
5299 (mapcar (lambda (buf)
5300 (when (buffer-file-name buf)
5302 (if (not (file-exists-p (buffer-file-name buf)))
5304 (concat "File not found: " (buffer-file-name buf))))
5305 (message (concat "Processing " (buffer-file-name buf)))
5308 (when (and (not no-save)
5309 (buffer-modified-p)) ; Avoid "no changes to be saved"
5311 orig-buffer-list))))
5313 (defun verilog-batch-auto ()
5314 "For use with --batch, perform automatic expansions as a stand-alone tool.
5315 This sets up the appropriate Verilog mode environment, updates automatics
5316 with \\[verilog-auto] on all command-line files, and saves the buffers.
5317 For proper results, multiple filenames need to be passed on the command
5318 line in bottom-up order."
5319 (unless noninteractive
5320 (error "Use verilog-batch-auto only with --batch")) ; Otherwise we'd mess up buffer modes
5321 (verilog-batch-execute-func `verilog-auto))
5323 (defun verilog-batch-delete-auto ()
5324 "For use with --batch, perform automatic deletion as a stand-alone tool.
5325 This sets up the appropriate Verilog mode environment, deletes automatics
5326 with \\[verilog-delete-auto] on all command-line files, and saves the buffers."
5327 (unless noninteractive
5328 (error "Use verilog-batch-delete-auto only with --batch")) ; Otherwise we'd mess up buffer modes
5329 (verilog-batch-execute-func `verilog-delete-auto))
5331 (defun verilog-batch-delete-trailing-whitespace ()
5332 "For use with --batch, perform whitespace deletion as a stand-alone tool.
5333 This sets up the appropriate Verilog mode environment, removes
5334 whitespace with \\[verilog-delete-trailing-whitespace] on all
5335 command-line files, and saves the buffers."
5336 (unless noninteractive
5337 (error "Use verilog-batch-delete-trailing-whitespace only with --batch")) ; Otherwise we'd mess up buffer modes
5338 (verilog-batch-execute-func `verilog-delete-trailing-whitespace))
5340 (defun verilog-batch-diff-auto ()
5341 "For use with --batch, perform automatic differences as a stand-alone tool.
5342 This sets up the appropriate Verilog mode environment, expand automatics
5343 with \\[verilog-diff-auto] on all command-line files, and reports an error
5344 if any differences are observed. This is appropriate for adding to regressions
5345 to insure automatics are always properly maintained."
5346 (unless noninteractive
5347 (error "Use verilog-batch-diff-auto only with --batch")) ; Otherwise we'd mess up buffer modes
5348 (verilog-batch-execute-func `verilog-diff-auto t))
5350 (defun verilog-batch-inject-auto ()
5351 "For use with --batch, perform automatic injection as a stand-alone tool.
5352 This sets up the appropriate Verilog mode environment, injects new automatics
5353 with \\[verilog-inject-auto] on all command-line files, and saves the buffers.
5354 For proper results, multiple filenames need to be passed on the command
5355 line in bottom-up order."
5356 (unless noninteractive
5357 (error "Use verilog-batch-inject-auto only with --batch")) ; Otherwise we'd mess up buffer modes
5358 (verilog-batch-execute-func `verilog-inject-auto))
5360 (defun verilog-batch-indent ()
5361 "For use with --batch, reindent an entire file as a stand-alone tool.
5362 This sets up the appropriate Verilog mode environment, calls
5363 \\[verilog-indent-buffer] on all command-line files, and saves the buffers."
5364 (unless noninteractive
5365 (error "Use verilog-batch-indent only with --batch")) ; Otherwise we'd mess up buffer modes
5366 (verilog-batch-execute-func `verilog-indent-buffer))
5370 (defconst verilog-indent-alist
5371 '((block . (+ ind verilog-indent-level))
5372 (case . (+ ind verilog-case-indent))
5373 (cparenexp . (+ ind verilog-indent-level))
5374 (cexp . (+ ind verilog-cexp-indent))
5375 (defun . verilog-indent-level-module)
5376 (declaration . verilog-indent-level-declaration)
5377 (directive . (verilog-calculate-indent-directive))
5378 (tf . verilog-indent-level)
5379 (behavioral . (+ verilog-indent-level-behavioral verilog-indent-level-module))
5382 (comment . (verilog-comment-indent))
5386 (defun verilog-continued-line-1 (lim)
5387 "Return true if this is a continued line.
5388 Set point to where line starts. Limit search to point LIM."
5389 (let ((continued 't))
5390 (if (eq 0 (forward-line -1))
5393 (verilog-backward-ws&directives lim)
5395 (setq continued nil)
5396 (setq continued (verilog-backward-token))))
5397 (setq continued nil))
5400 (defun verilog-calculate-indent ()
5401 "Calculate the indent of the current Verilog line.
5402 Examine previous lines. Once a line is found that is definitive as to the
5403 type of the current line, return that lines' indent level and its type.
5404 Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
5406 (let* ((starting_position (point))
5407 (case-fold-search nil)
5409 (begin (looking-at "[ \t]*begin\\>"))
5410 (lim (save-excursion (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)" nil t)))
5412 (type (catch 'nesting
5413 ;; Keep working backwards until we can figure out
5414 ;; what type of statement this is.
5415 ;; Basically we need to figure out
5416 ;; 1) if this is a continuation of the previous line;
5417 ;; 2) are we in a block scope (begin..end)
5419 ;; if we are in a comment, done.
5420 (if (verilog-in-star-comment-p)
5421 (throw 'nesting 'comment))
5423 ;; if we have a directive, done.
5424 (if (save-excursion (beginning-of-line)
5425 (and (looking-at verilog-directive-re-1)
5426 (not (or (looking-at "[ \t]*`[ou]vm_")
5427 (looking-at "[ \t]*`vmm_")))))
5428 (throw 'nesting 'directive))
5429 ;; indent structs as if there were module level
5430 (setq structres (verilog-in-struct-nested-p))
5431 (cond ((not structres) nil)
5432 ;;((and structres (equal (char-after) ?\})) (throw 'nesting 'struct-close))
5433 ((> structres 0) (throw 'nesting 'nested-struct))
5434 ((= structres 0) (throw 'nesting 'block))
5437 ;; if we are in a parenthesized list, and the user likes to indent these, return.
5438 ;; unless we are in the newfangled coverpoint or constraint blocks
5440 verilog-indent-lists
5442 (not (verilog-in-coverage-p))
5445 (throw 'nesting 'block)))
5447 ;; See if we are continuing a previous line
5449 ;; trap out if we crawl off the top of the buffer
5450 (if (bobp) (throw 'nesting 'cpp))
5452 (if (and (verilog-continued-line-1 lim)
5453 (or (not (verilog-in-coverage-p))
5454 (looking-at verilog-in-constraint-re) )) ; may still get hosed if concat in constraint
5457 (not (looking-at verilog-complete-reg))
5458 (verilog-continued-line-1 lim))
5459 (progn (goto-char sp)
5460 (throw 'nesting 'cexp))
5463 (if (and (verilog-in-coverage-p)
5464 (looking-at verilog-in-constraint-re))
5467 (skip-chars-forward " \t")
5468 (throw 'nesting 'constraint)))
5470 (not verilog-indent-begin-after-if)
5471 (looking-at verilog-no-indent-begin-re))
5474 (skip-chars-forward " \t")
5475 (throw 'nesting 'statement))
5477 (throw 'nesting 'cexp))))
5478 ;; not a continued line
5479 (goto-char starting_position))
5481 (if (looking-at "\\<else\\>")
5482 ;; search back for governing if, striding across begin..end pairs
5485 (while (verilog-re-search-backward verilog-ends-re nil 'move)
5487 ((match-end 1) ; else, we're in deep
5488 (setq elsec (1+ elsec)))
5490 (setq elsec (1- elsec))
5492 (if verilog-align-ifelse
5493 (throw 'nesting 'statement)
5494 (progn ; back up to first word on this line
5496 (verilog-forward-syntactic-ws)
5497 (throw 'nesting 'statement)))))
5498 ((match-end 3) ; assert block
5499 (setq elsec (1- elsec))
5500 (verilog-beg-of-statement) ; doesn't get to beginning
5501 (if (looking-at verilog-property-re)
5502 (throw 'nesting 'statement) ; We don't need an endproperty for these
5503 (throw 'nesting 'block) ; We still need an endproperty
5506 ;; try to leap back to matching outward block by striding across
5507 ;; indent level changing tokens then immediately
5508 ;; previous line governs indentation.
5509 (let (( reg) (nest 1))
5510 ;; verilog-ends => else|if|end|join(_any|_none|)|endcase|endclass|endtable|endspecify|endfunction|endtask|endgenerate|endgroup
5512 ((match-end 4) ; end
5513 ;; Search back for matching begin
5514 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
5515 ((match-end 5) ; endcase
5516 ;; Search back for matching case
5517 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
5518 ((match-end 6) ; endfunction
5519 ;; Search back for matching function
5520 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
5521 ((match-end 7) ; endtask
5522 ;; Search back for matching task
5523 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
5524 ((match-end 8) ; endspecify
5525 ;; Search back for matching specify
5526 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
5527 ((match-end 9) ; endtable
5528 ;; Search back for matching table
5529 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
5530 ((match-end 10) ; endgenerate
5531 ;; Search back for matching generate
5532 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
5533 ((match-end 11) ; joins
5534 ;; Search back for matching fork
5535 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|none\\)?\\>\\)" ))
5536 ((match-end 12) ; class
5537 ;; Search back for matching class
5538 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
5539 ((match-end 13) ; covergroup
5540 ;; Search back for matching covergroup
5541 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" )))
5543 (while (verilog-re-search-backward reg nil 'move)
5545 ((match-end 1) ; begin
5546 (setq nest (1- nest))
5549 ((match-end 2) ; end
5550 (setq nest (1+ nest)))))
5552 (throw 'nesting (verilog-calc-1)))
5556 ;; Return type of block and indent level.
5559 (if (> par 0) ; Unclosed Parenthesis
5560 (list 'cparenexp par)
5563 (list type (verilog-case-indent-level)))
5564 ((eq type 'statement)
5565 (list type (current-column)))
5568 ((eq type 'constraint)
5569 (list 'block (current-column)))
5570 ((eq type 'nested-struct)
5571 (list 'block structres))
5573 (list type (verilog-current-indent-level))))))))
5575 (defun verilog-wai ()
5576 "Show matching nesting block for debugging."
5579 (let* ((type (verilog-calc-1))
5581 ;; Return type of block and indent level.
5585 verilog-indent-lists
5586 (not(or (verilog-in-coverage-p)
5587 (verilog-in-struct-p)))
5592 (setq depth (verilog-case-indent-level)))
5593 ((eq type 'statement)
5594 (setq depth (current-column)))
5598 (setq depth (verilog-current-indent-level)))))
5599 (message "You are at nesting %s depth %d" type depth))))
5601 (defun verilog-calc-1 ()
5603 (let ((re (concat "\\({\\|}\\|" verilog-indent-re "\\)"))
5604 (inconstraint (verilog-in-coverage-p)))
5605 (while (verilog-re-search-backward re nil 'move)
5608 ((equal (char-after) ?\{)
5609 ;; block type returned based on outer constraint { or inner
5610 (if (verilog-at-constraint-p)
5612 (beginning-of-line nil)
5613 (skip-chars-forward " \t")
5614 (throw 'nesting 'constraint))
5616 (throw 'nesting 'statement)))))
5617 ((equal (char-after) ?\})
5619 (there (verilog-at-close-constraint-p)))
5620 (if there ; we are at the } that closes a constraint. Find the { that opens it
5622 (if (> (verilog-in-paren-count) 0)
5624 (setq par-pos (verilog-parenthesis-depth))
5629 (backward-char 1)))))))
5631 ((looking-at verilog-beg-block-re-ordered)
5633 ((match-end 2) ; *sigh* could be "unique case" or "priority casex"
5634 (let ((here (point)))
5635 (verilog-beg-of-statement)
5636 (if (looking-at verilog-extended-case-re)
5637 (throw 'nesting 'case)
5639 (throw 'nesting 'case))
5641 ((match-end 4) ; *sigh* could be "disable fork"
5642 (let ((here (point)))
5643 (verilog-beg-of-statement)
5644 (if (looking-at verilog-disable-fork-re)
5645 t ; this is a normal statement
5646 (progn ; or is fork, starts a new block
5648 (throw 'nesting 'block)))))
5650 ((match-end 27) ; *sigh* might be a clocking declaration
5651 (let ((here (point)))
5652 (if (verilog-in-paren)
5653 t ; this is a normal statement
5654 (progn ; or is fork, starts a new block
5656 (throw 'nesting 'block)))))
5658 ;; need to consider typedef struct here...
5659 ((looking-at "\\<class\\|struct\\|function\\|task\\>")
5660 ;; *sigh* These words have an optional prefix:
5661 ;; extern {virtual|protected}? function a();
5662 ;; typedef class foo;
5663 ;; and we don't want to confuse this with
5668 (verilog-beg-of-statement)
5670 ((looking-at verilog-dpi-import-export-re)
5671 (throw 'continue 'foo))
5672 ((looking-at "\\<pure\\>\\s-+\\<virtual\\>\\s-+\\(?:\\<\\(local\\|protected\\|static\\)\\>\\s-+\\)?\\<\\(function\\|task\\)\\>\\s-+")
5673 (throw 'nesting 'statement))
5674 ((looking-at verilog-beg-block-re-ordered)
5675 (throw 'nesting 'block))
5677 (throw 'nesting 'defun))))
5680 ((looking-at "\\<property\\>")
5682 ;; {assert|assume|cover} property (); are complete
5683 ;; and could also be labeled: - foo: assert property
5685 ;; property ID () ... needs end_property
5686 (verilog-beg-of-statement)
5687 (if (looking-at verilog-property-re)
5688 (throw 'continue 'statement) ; We don't need an endproperty for these
5689 (throw 'nesting 'block) ;We still need an endproperty
5692 (t (throw 'nesting 'block))))
5694 ((looking-at verilog-end-block-re)
5695 (verilog-leap-to-head)
5696 (if (verilog-in-case-region-p)
5698 (verilog-leap-to-case-head)
5699 (if (looking-at verilog-extended-case-re)
5700 (throw 'nesting 'case)))))
5702 ((looking-at verilog-defun-level-re)
5703 (if (looking-at verilog-defun-level-generate-only-re)
5704 (if (or (verilog-in-generate-region-p)
5705 (verilog-in-deferred-immediate-final-p))
5706 (throw 'continue 'foo) ; always block in a generate - keep looking
5707 (throw 'nesting 'defun))
5708 (throw 'nesting 'defun)))
5710 ((looking-at verilog-cpp-level-re)
5711 (throw 'nesting 'cpp))
5714 (throw 'nesting 'cpp)))))
5716 (throw 'nesting 'cpp))))
5718 (defun verilog-calculate-indent-directive ()
5719 "Return indentation level for directive.
5720 For speed, the searcher looks at the last directive, not the indent
5721 of the appropriate enclosing block."
5722 (let ((base -1) ; Indent of the line that determines our indentation
5723 (ind 0)) ; Relative offset caused by other directives (like `endif on same line as `else)
5724 ;; Start at current location, scan back for another directive
5728 (while (and (< base 0)
5729 (verilog-re-search-backward verilog-directive-re nil t))
5730 (cond ((save-excursion (skip-chars-backward " \t") (bolp))
5731 (setq base (current-indentation))))
5732 (cond ((and (looking-at verilog-directive-end) (< base 0)) ; Only matters when not at BOL
5733 (setq ind (- ind verilog-indent-level-directive)))
5734 ((and (looking-at verilog-directive-middle) (>= base 0)) ; Only matters when at BOL
5735 (setq ind (+ ind verilog-indent-level-directive)))
5736 ((looking-at verilog-directive-begin)
5737 (setq ind (+ ind verilog-indent-level-directive)))))
5738 ;; Adjust indent to starting indent of critical line
5739 (setq ind (max 0 (+ ind base))))
5743 (skip-chars-forward " \t")
5744 (cond ((or (looking-at verilog-directive-middle)
5745 (looking-at verilog-directive-end))
5746 (setq ind (max 0 (- ind verilog-indent-level-directive))))))
5749 (defun verilog-leap-to-case-head ()
5752 (verilog-re-search-backward
5754 "\\(\\<randcase\\>\\|\\(\\<unique0?\\s-+\\|priority\\s-+\\)?\\<case[xz]?\\>\\)"
5755 "\\|\\(\\<endcase\\>\\)" )
5759 (let ((here (point)))
5760 (verilog-beg-of-statement)
5761 (unless (looking-at verilog-extended-case-re)
5763 (setq nest (1- nest)))
5765 (setq nest (1+ nest)))
5770 (defun verilog-leap-to-head ()
5771 "Move point to the head of this block.
5772 Jump from end to matching begin, from endcase to matching case, and so on."
5778 ((looking-at "\\<end\\>")
5779 ;; 1: Search back for matching begin
5780 (setq reg (concat "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|"
5781 "\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))
5782 ((looking-at "\\<endtask\\>")
5783 ;; 2: Search back for matching task
5784 (setq reg "\\(\\<task\\>\\)\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)+\\<task\\>\\)")
5786 ((looking-at "\\<endcase\\>")
5788 (verilog-leap-to-case-head) )
5789 (setq reg nil) ; to force skip
5792 ((looking-at "\\<join\\(_any\\|_none\\)?\\>")
5793 ;; 4: Search back for matching fork
5794 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
5795 ((looking-at "\\<endclass\\>")
5796 ;; 5: Search back for matching class
5797 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
5798 ((looking-at "\\<endtable\\>")
5799 ;; 6: Search back for matching table
5800 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
5801 ((looking-at "\\<endspecify\\>")
5802 ;; 7: Search back for matching specify
5803 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
5804 ((looking-at "\\<endfunction\\>")
5805 ;; 8: Search back for matching function
5806 (setq reg "\\(\\<function\\>\\)\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)+\\<function\\>\\)")
5808 ;;(setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
5809 ((looking-at "\\<endgenerate\\>")
5810 ;; 8: Search back for matching generate
5811 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
5812 ((looking-at "\\<endgroup\\>")
5813 ;; 10: Search back for matching covergroup
5814 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
5815 ((looking-at "\\<endproperty\\>")
5816 ;; 11: Search back for matching property
5817 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
5818 ((looking-at verilog-uvm-end-re)
5819 ;; 12: Search back for matching sequence
5820 (setq reg (concat "\\(" verilog-uvm-begin-re "\\|" verilog-uvm-end-re "\\)")))
5821 ((looking-at verilog-ovm-end-re)
5822 ;; 12: Search back for matching sequence
5823 (setq reg (concat "\\(" verilog-ovm-begin-re "\\|" verilog-ovm-end-re "\\)")))
5824 ((looking-at verilog-vmm-end-re)
5825 ;; 12: Search back for matching sequence
5826 (setq reg (concat "\\(" verilog-vmm-begin-re "\\|" verilog-vmm-end-re "\\)")))
5827 ((looking-at "\\<endinterface\\>")
5828 ;; 12: Search back for matching interface
5829 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<endinterface\\>\\)" ))
5830 ((looking-at "\\<endsequence\\>")
5831 ;; 12: Search back for matching sequence
5832 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" ))
5833 ((looking-at "\\<endclocking\\>")
5834 ;; 12: Search back for matching clocking
5835 (setq reg "\\(\\<clocking\\)\\|\\(\\<endclocking\\>\\)" )))
5838 (if (eq nesting 'yes)
5840 (while (verilog-re-search-backward reg nil 'move)
5842 ((match-end 1) ; begin
5843 (if (looking-at "fork")
5844 (let ((here (point)))
5845 (verilog-beg-of-statement)
5846 (unless (looking-at verilog-disable-fork-re)
5848 (setq nest (1- nest))))
5849 (setq nest (1- nest)))
5851 ;; Now previous line describes syntax
5856 ((match-end 2) ; end
5857 (setq nest (1+ nest)))
5859 ;; endcase, jump to case
5861 (setq nest (1+ nest))
5863 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
5865 ;; join, jump to fork
5867 (setq nest (1+ nest))
5869 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
5873 (verilog-re-search-backward reg nil 'move)
5874 (match-end 1)) ; task -> could be virtual and/or protected
5876 (verilog-beg-of-statement)
5878 (throw 'skip 1)))))))
5880 (defun verilog-continued-line ()
5881 "Return true if this is a continued line.
5882 Set point to where line starts."
5883 (let ((continued 't))
5884 (if (eq 0 (forward-line -1))
5887 (verilog-backward-ws&directives)
5889 (setq continued nil)
5890 (while (and continued
5892 (skip-chars-backward " \t")
5894 (setq continued (verilog-backward-token)))))
5895 (setq continued nil))
5898 (defun verilog-backward-token ()
5899 "Step backward token, returning true if this is a continued line."
5901 (verilog-backward-syntactic-ws)
5905 (;-- Anything ending in a ; is complete
5906 (= (preceding-char) ?\;)
5908 (; If a "}" is prefixed by a ";", then this is a complete statement
5909 ;; i.e.: constraint foo { a = b; }
5910 (= (preceding-char) ?\})
5913 (not(verilog-at-close-constraint-p))))
5914 (;-- constraint foo { a = b }
5915 ;; is a complete statement. *sigh*
5916 (= (preceding-char) ?\{)
5919 (not (verilog-at-constraint-p))))
5921 (= (preceding-char) ?\")
5923 (verilog-skip-backward-comment-or-string)
5927 (= (preceding-char) ?\])
5929 (verilog-backward-open-bracket)
5932 (;-- Could be 'case (foo)' or 'always @(bar)' which is complete
5933 ;; also could be simply '@(foo)'
5935 ;; (b, ... which ISN'T complete
5936 ;; Do we need this???
5937 (= (preceding-char) ?\))
5940 (verilog-backward-up-list 1)
5941 (verilog-backward-syntactic-ws)
5942 (let ((back (point)))
5946 ((looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|case\\(\\|[xz]\\)\\|for\\(\\|each\\|ever\\)\\|i\\(f\\|nitial\\)\\|repeat\\|while\\)\\>")
5947 (not (looking-at "\\<randcase\\>\\|\\<case[xz]?\\>[^:]")))
5948 ((looking-at verilog-uvm-statement-re)
5950 ((looking-at verilog-uvm-begin-re)
5952 ((looking-at verilog-uvm-end-re)
5954 ((looking-at verilog-ovm-statement-re)
5956 ((looking-at verilog-ovm-begin-re)
5958 ((looking-at verilog-ovm-end-re)
5960 ;; JBA find VMM macros
5961 ((looking-at verilog-vmm-statement-re)
5963 ((looking-at verilog-vmm-begin-re)
5965 ((looking-at verilog-vmm-end-re)
5967 ;; JBA trying to catch macro lines with no ; at end
5968 ((looking-at "\\<`")
5973 ((= (preceding-char) ?\@)
5976 (verilog-backward-token)
5977 (not (looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|initial\\|while\\)\\>"))))
5978 ((= (preceding-char) ?\#)
5982 (;-- any of begin|initial|while are complete statements; 'begin : foo' is also complete
5985 (while (or (= (preceding-char) ?\_)
5986 (= (preceding-char) ?\@)
5987 (= (preceding-char) ?\.))
5990 ((looking-at "\\<else\\>")
5992 ((looking-at verilog-behavioral-block-beg-re)
5994 ((looking-at verilog-indent-re)
5999 (verilog-backward-syntactic-ws)
6001 ((= (preceding-char) ?\:)
6003 (verilog-backward-syntactic-ws)
6005 (if (looking-at verilog-nameable-item-re )
6008 ((= (preceding-char) ?\#)
6011 ((= (preceding-char) ?\`)
6019 (defun verilog-backward-syntactic-ws ()
6020 "Move backwards putting point after first non-whitespace non-comment."
6021 (verilog-skip-backward-comments)
6022 (forward-comment (- (buffer-size))))
6024 (defun verilog-backward-syntactic-ws-quick ()
6025 "As with `verilog-backward-syntactic-ws' but use `verilog-scan' cache."
6026 (while (cond ((bobp)
6028 ((< (skip-syntax-backward " ") 0)
6030 ((eq (preceding-char) ?\n) ; \n's terminate // so aren't space syntax
6033 ((or (verilog-inside-comment-or-string-p (1- (point)))
6034 (verilog-inside-comment-or-string-p (point)))
6035 (re-search-backward "[/\"]" nil t) ; Only way a comment or quote can begin
6038 (defun verilog-forward-syntactic-ws ()
6039 (verilog-skip-forward-comment-p)
6040 (forward-comment (buffer-size)))
6042 (defun verilog-backward-ws&directives (&optional bound)
6043 "Backward skip over syntactic whitespace and compiler directives for Emacs 19.
6044 Optional BOUND limits search."
6046 (let* ((bound (or bound (point-min)))
6049 (if (< bound (point))
6051 (let ((state (save-excursion (verilog-syntax-ppss))))
6053 ((nth 7 state) ; in // comment
6054 (verilog-re-search-backward "//" nil 'move)
6055 (skip-chars-backward "/"))
6056 ((nth 4 state) ; in /* */ comment
6057 (verilog-re-search-backward "/\*" nil 'move))))
6058 (narrow-to-region bound (point))
6059 (while (/= here (point))
6061 (verilog-skip-backward-comments)
6065 ;; for as long as we're right after a continued line, keep moving up
6066 (while (and (verilog-looking-back "\\\\[\n\r\f]" nil)
6069 ((and verilog-highlight-translate-off
6070 (verilog-within-translate-off))
6071 (verilog-back-to-start-translate-off (point-min)))
6072 ((looking-at verilog-directive-re-1)
6076 (if p (goto-char p))))))))
6078 (defun verilog-forward-ws&directives (&optional bound)
6079 "Forward skip over syntactic whitespace and compiler directives for Emacs 19.
6080 Optional BOUND limits search."
6082 (let* ((bound (or bound (point-max)))
6085 (if (> bound (point))
6087 (let ((state (save-excursion (verilog-syntax-ppss))))
6089 ((nth 7 state) ; in // comment
6092 (skip-chars-forward " \t\n\f")
6094 ((nth 4 state) ; in /* */ comment
6095 (verilog-re-search-forward "\*\/\\s-*" nil 'move))))
6096 (narrow-to-region (point) bound)
6097 (while (/= here (point))
6100 (forward-comment (buffer-size))
6101 (and (looking-at "\\s-*(\\*.*\\*)\\s-*") ; Attribute
6102 (goto-char (match-end 0)))
6105 (if (looking-at verilog-directive-re-1)
6108 (beginning-of-line 2))))))))
6110 (defun verilog-in-comment-p ()
6111 "Return true if in a star or // comment."
6112 (let ((state (save-excursion (verilog-syntax-ppss))))
6113 (or (nth 4 state) (nth 7 state))))
6115 (defun verilog-in-star-comment-p ()
6116 "Return true if in a star comment."
6117 (let ((state (save-excursion (verilog-syntax-ppss))))
6119 (nth 4 state) ; t if in a comment of style a // or b /**/
6121 (nth 7 state) ; t if in a comment of style b /**/
6124 (defun verilog-in-slash-comment-p ()
6125 "Return true if in a slash comment."
6126 (let ((state (save-excursion (verilog-syntax-ppss))))
6129 (defun verilog-in-comment-or-string-p ()
6130 "Return true if in a string or comment."
6131 (let ((state (save-excursion (verilog-syntax-ppss))))
6132 (or (nth 3 state) (nth 4 state) (nth 7 state)))) ; Inside string or comment)
6134 (defun verilog-in-attribute-p ()
6135 "Return true if point is in an attribute (* [] attribute *)."
6138 (verilog-re-search-backward "\\((\\*\\)\\|\\(\\*)\\)" nil 'move)
6141 (progn (goto-char (match-end 1))
6142 (not (looking-at "\\s-*)")))
6145 (progn (goto-char (match-beginning 2))
6146 (not (looking-at "(\\s-*")))
6150 (defun verilog-in-parameter-p ()
6151 "Return true if point is in a parameter assignment #( p1=1, p2=5)."
6154 (verilog-re-search-backward "\\(#(\\)\\|\\()\\)" nil 'move)
6155 (numberp (match-beginning 1)))))
6157 (defun verilog-in-escaped-name-p ()
6158 "Return true if in an escaped name."
6161 (skip-chars-backward "^ \t\n\f")
6162 (if (equal (char-after (point) ) ?\\ )
6166 (defun verilog-in-directive-p ()
6167 "Return true if in a directive."
6170 (looking-at verilog-directive-re-1)))
6172 (defun verilog-in-parenthesis-p ()
6173 "Return true if in a ( ) expression (but not { } or [ ])."
6176 (verilog-re-search-backward "\\((\\)\\|\\()\\)" nil 'move)
6177 (numberp (match-beginning 1)))))
6179 (defun verilog-in-paren ()
6180 "Return true if in a parenthetical expression.
6181 May cache result using `verilog-syntax-ppss'."
6182 (let ((state (save-excursion (verilog-syntax-ppss))))
6183 (> (nth 0 state) 0 )))
6185 (defun verilog-in-paren-count ()
6186 "Return paren depth, floor to 0.
6187 May cache result using `verilog-syntax-ppss'."
6188 (let ((state (save-excursion (verilog-syntax-ppss))))
6189 (if (> (nth 0 state) 0)
6193 (defun verilog-in-paren-quick ()
6194 "Return true if in a parenthetical expression.
6195 Always starts from `point-min', to allow inserts with hooks disabled."
6196 ;; The -quick refers to its use alongside the other -quick functions,
6197 ;; not that it's likely to be faster than verilog-in-paren.
6198 (let ((state (save-excursion (parse-partial-sexp (point-min) (point)))))
6199 (> (nth 0 state) 0 )))
6201 (defun verilog-in-struct-p ()
6202 "Return true if in a struct declaration."
6205 (if (verilog-in-paren)
6207 (verilog-backward-up-list 1)
6208 (verilog-at-struct-p)
6212 (defun verilog-in-struct-nested-p ()
6213 "Return nil for not in struct.
6214 Return 0 for in non-nested struct.
6215 Return >0 for nested struct."
6219 (if (verilog-in-paren)
6221 (verilog-backward-up-list 1)
6222 (setq col (verilog-at-struct-mv-p))
6224 (if (verilog-in-struct-p) (current-column) 0)))
6227 (defun verilog-in-coverage-p ()
6228 "Return true if in a constraint or coverpoint expression."
6231 (if (verilog-in-paren)
6233 (verilog-backward-up-list 1)
6234 (verilog-at-constraint-p)
6238 (defun verilog-at-close-constraint-p ()
6239 "If at the } that closes a constraint or covergroup, return true."
6241 (equal (char-after) ?\})
6242 (verilog-in-coverage-p))
6245 (verilog-backward-ws&directives)
6246 (if (or (equal (char-before) ?\;)
6247 (equal (char-before) ?\}) ; can end with inner constraint { } block or ;
6248 (equal (char-before) ?\{)) ; empty constraint block
6252 (defun verilog-at-constraint-p ()
6253 "If at the { of a constraint or coverpoint definition, return true, moving point to constraint."
6257 (equal (char-after) ?\{)
6259 (progn (backward-char 1)
6260 (verilog-backward-ws&directives)
6262 (or (equal (char-before) ?\{) ; empty case
6263 (equal (char-before) ?\;)
6264 (equal (char-before) ?\}))
6265 ;; skip what looks like bus repetition operator {#{
6266 (not (string-match "^{\\s-*[0-9]+\\s-*{" (buffer-substring p (point)))))))))
6268 (let ( (pt (point)) (pass 0))
6269 (verilog-backward-ws&directives)
6270 (verilog-backward-token)
6271 (if (looking-at (concat "\\<constraint\\|coverpoint\\|cross\\|with\\>\\|" verilog-in-constraint-re))
6272 (progn (setq pass 1)
6273 (if (looking-at "\\<with\\>")
6274 (progn (verilog-backward-ws&directives)
6275 (beginning-of-line) ; 1
6276 (verilog-forward-ws&directives)
6278 (verilog-beg-of-statement)
6280 ;; if first word token not keyword, it maybe the instance name
6281 ;; check next word token
6282 (if (looking-at "\\<\\w+\\>\\|\\s-*(\\s-*\\S-+")
6283 (progn (verilog-beg-of-statement)
6284 (if (looking-at (concat "\\<\\(constraint\\|"
6285 "\\(?:\\w+\\s-*:\\s-*\\)?\\(coverpoint\\|cross\\)"
6286 "\\|with\\)\\>\\|" verilog-in-constraint-re))
6289 (progn (goto-char pt) nil) 1)))
6293 (defun verilog-at-struct-p ()
6294 "If at the { of a struct, return true, not moving point."
6296 (if (and (equal (char-after) ?\{)
6297 (verilog-backward-token))
6298 (looking-at "\\<struct\\|union\\|packed\\|\\(un\\)?signed\\>")
6301 (defun verilog-at-struct-mv-p ()
6302 "If at the { of a struct, return true, moving point to struct."
6304 (if (and (equal (char-after) ?\{)
6305 (verilog-backward-token))
6306 (if (looking-at "\\<struct\\|union\\|packed\\|\\(un\\)?signed\\>")
6307 (progn (verilog-beg-of-statement) (point))
6308 (progn (goto-char pt) nil))
6309 (progn (goto-char pt) nil))))
6311 (defun verilog-at-close-struct-p ()
6312 "If at the } that closes a struct, return true."
6314 (equal (char-after) ?\})
6315 (verilog-in-struct-p))
6318 (if (looking-at "}\\(?:\\s-*\\w+\\s-*\\)?;") 1))
6322 (defun verilog-parenthesis-depth ()
6323 "Return non zero if in parenthetical-expression."
6324 (save-excursion (nth 1 (verilog-syntax-ppss))))
6327 (defun verilog-skip-forward-comment-or-string ()
6328 "Return true if in a string or comment."
6329 (let ((state (save-excursion (verilog-syntax-ppss))))
6331 ((nth 3 state) ;Inside string
6332 (search-forward "\"")
6334 ((nth 7 state) ;Inside // comment
6337 ((nth 4 state) ;Inside any comment (hence /**/)
6338 (search-forward "*/"))
6342 (defun verilog-skip-backward-comment-or-string ()
6343 "Return true if in a string or comment."
6344 (let ((state (save-excursion (verilog-syntax-ppss))))
6346 ((nth 3 state) ;Inside string
6347 (search-backward "\"")
6349 ((nth 7 state) ;Inside // comment
6350 (search-backward "//")
6351 (skip-chars-backward "/")
6353 ((nth 4 state) ;Inside /* */ comment
6354 (search-backward "/*")
6359 (defun verilog-skip-backward-comments ()
6360 "Return true if a comment was skipped."
6364 (let ((state (save-excursion (verilog-syntax-ppss))))
6366 ((nth 7 state) ;Inside // comment
6367 (search-backward "//")
6368 (skip-chars-backward "/")
6369 (skip-chars-backward " \t\n\f")
6371 ((nth 4 state) ;Inside /* */ comment
6372 (search-backward "/*")
6373 (skip-chars-backward " \t\n\f")
6376 (= (char-before) ?\/)
6377 (= (char-before (1- (point))) ?\*))
6378 (goto-char (- (point) 2))
6379 t) ; Let nth 4 state handle the rest
6381 ;;(verilog-looking-back "\\*)" nil) ;; super slow, use two char-before instead
6382 (= (char-before) ?\))
6383 (= (char-before (1- (point))) ?\*)
6384 (not (verilog-looking-back "(\\s-*\\*)" nil))) ;; slow but unlikely to be called
6385 (goto-char (- (point) 2))
6386 (if (search-backward "(*" nil t)
6388 (skip-chars-backward " \t\n\f")
6391 (goto-char (+ (point) 2))
6394 (/= (skip-chars-backward " \t\n\f") 0))))))))
6396 (defun verilog-skip-forward-comment-p ()
6397 "If in comment, move to end and return true."
6399 (state (save-excursion (verilog-syntax-ppss)))
6401 ((nth 3 state) ;Inside string
6403 ((nth 7 state) ;Inside // comment
6407 ((nth 4 state) ;Inside /* comment
6408 (search-forward "*/")
6410 ((verilog-in-attribute-p) ;Inside (* attribute
6411 (search-forward "*)" nil t)
6414 (skip-chars-forward " \t\n\f")
6417 ((looking-at "\\/\\*")
6420 (goto-char (match-end 0))
6421 (if (search-forward "*/" nil t)
6423 (skip-chars-forward " \t\n\f")
6428 ((and (looking-at "(\\*") ; attribute start, but not an event (*) or (* )
6429 (not (looking-at "(\\*\\s-*)")))
6432 (goto-char (match-end 0))
6433 (if (search-forward "*)" nil t)
6435 (skip-chars-forward " \t\n\f")
6443 (defun verilog-indent-line-relative ()
6444 "Cheap version of indent line.
6445 Only look at a few lines to determine indent level."
6449 (if (looking-at "^[ \t]*$")
6450 (cond ;- A blank line; No need to be too smart.
6452 (setq indent-str (list 'cpp 0)))
6453 ((verilog-continued-line)
6454 (let ((sp1 (point)))
6455 (if (verilog-continued-line)
6459 (list 'statement (verilog-current-indent-level))))
6461 (setq indent-str (list 'block (verilog-current-indent-level)))))
6464 (setq indent-str (verilog-calculate-indent))))
6465 (progn (skip-chars-forward " \t")
6466 (setq indent-str (verilog-calculate-indent))))
6467 (verilog-do-indent indent-str)))
6469 (defun verilog-indent-line ()
6470 "Indent for special part of code."
6471 (verilog-do-indent (verilog-calculate-indent)))
6473 (defun verilog-do-indent (indent-str)
6474 (let ((type (car indent-str))
6475 (ind (car (cdr indent-str))))
6477 (; handle continued exp
6479 (let ((here (point)))
6480 (verilog-backward-syntactic-ws)
6483 (= (preceding-char) ?\,)
6485 (verilog-beg-of-statement-1)
6486 (looking-at verilog-declaration-re)))
6491 (verilog-beg-of-statement-1)
6493 (if (looking-at verilog-declaration-re)
6494 (progn ; we have multiple words
6495 (goto-char (match-end 0))
6496 (skip-chars-forward " \t")
6498 ((and verilog-indent-declaration-macros
6499 (= (following-char) ?\`))
6503 (skip-chars-forward " \t")))
6504 ((= (following-char) ?\[)
6507 (verilog-backward-up-list -1)
6508 (skip-chars-forward " \t"))))
6512 (+ (current-column) verilog-cexp-indent))))))
6514 (indent-line-to val)
6515 (if (and (not verilog-indent-lists)
6517 (verilog-pretty-declarations-auto))
6519 ((= (preceding-char) ?\) )
6521 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
6522 (indent-line-to val)))
6526 (verilog-beg-of-statement-1)
6527 (if (and (< (point) here)
6528 (verilog-re-search-forward "=[ \\t]*" here 'move)
6529 ;; not at a |=>, #=#, or [=n] operator
6530 (not (string-match "\\[=.\\|#=#\\||=>"
6531 (or (buffer-substring (- (point) 2) (1+ (point)))
6532 "")))) ; don't let buffer over/under-run spoil the party
6533 (setq val (current-column))
6534 (setq val (eval (cdr (assoc type verilog-indent-alist)))))
6536 (indent-line-to val))))))
6538 (; handle inside parenthetical expressions
6539 (eq type 'cparenexp)
6541 (val (save-excursion
6542 (verilog-backward-up-list 1)
6544 (if verilog-indent-lists
6545 (skip-chars-forward " \t")
6546 (verilog-forward-syntactic-ws))
6550 (decl (save-excursion
6552 (verilog-forward-syntactic-ws)
6554 (looking-at verilog-declaration-re))))
6555 (indent-line-to val)
6557 (verilog-pretty-declarations-auto))))
6559 (;-- Handle the ends
6561 (looking-at verilog-end-block-re)
6562 (verilog-at-close-constraint-p)
6563 (verilog-at-close-struct-p))
6564 (let ((val (if (eq type 'statement)
6565 (- ind verilog-indent-level)
6567 (indent-line-to val)))
6569 (;-- Case -- maybe line 'em up
6570 (and (eq type 'case) (not (looking-at "^[ \t]*$")))
6573 ((looking-at "\\<endcase\\>")
6574 (indent-line-to ind))
6576 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
6577 (indent-line-to val))))))
6580 (and (eq type 'defun)
6581 (looking-at verilog-zero-indent-re))
6588 (looking-at verilog-declaration-re)
6589 ;; Do not consider "virtual function", "virtual task", "virtual class"
6591 (not (looking-at (concat verilog-declaration-re
6592 "\\s-+\\(function\\|task\\|class\\)\\b"))))
6593 (verilog-indent-declaration ind))
6595 (;-- form feeds - ignored as bug in indent-line-to in < 24.5
6598 (;-- Everything else
6600 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
6601 (indent-line-to val))))
6603 (if (looking-at "[ \t]+$")
6604 (skip-chars-forward " \t"))
6605 indent-str ; Return indent data
6608 (defun verilog-current-indent-level ()
6609 "Return the indent-level of the current statement."
6613 (setq par-pos (verilog-parenthesis-depth))
6617 (setq par-pos (verilog-parenthesis-depth)))
6618 (skip-chars-forward " \t")
6621 (defun verilog-case-indent-level ()
6622 "Return the indent-level of the current statement.
6623 Do not count named blocks or case-statements."
6625 (skip-chars-forward " \t")
6627 ((looking-at verilog-named-block-re)
6629 ((and (not (looking-at verilog-extended-case-re))
6630 (looking-at "^[^:;]+[ \t]*:"))
6631 (verilog-re-search-forward ":" nil t)
6632 (skip-chars-forward " \t")
6635 (current-column)))))
6637 (defun verilog-indent-comment ()
6638 "Indent current line as comment."
6641 ((verilog-in-star-comment-p)
6643 (re-search-backward "/\\*" nil t)
6644 (1+(current-column))))
6649 (re-search-backward "//" nil t)
6650 (current-column))))))
6651 (indent-line-to stcol)
6654 (defun verilog-more-comment ()
6655 "Make more comment lines like the previous."
6659 ((verilog-in-star-comment-p)
6662 (re-search-backward "/\\*" nil t)
6663 (1+(current-column))))
6668 (re-search-backward "//" nil t)
6669 (current-column))))))
6675 (skip-chars-forward " \t")
6679 (defun verilog-comment-indent (&optional _arg)
6680 "Return the column number the line should be indented to.
6681 _ARG is ignored, for `comment-indent-function' compatibility."
6683 ((verilog-in-star-comment-p)
6685 (re-search-backward "/\\*" nil t)
6686 (1+(current-column))))
6691 (re-search-backward "//" nil t)
6692 (current-column)))))
6696 (defun verilog-pretty-declarations-auto (&optional quiet)
6697 "Call `verilog-pretty-declarations' QUIET based on `verilog-auto-lineup'."
6698 (when (or (eq 'all verilog-auto-lineup)
6699 (eq 'declarations verilog-auto-lineup))
6700 (verilog-pretty-declarations quiet)))
6702 (defun verilog-pretty-declarations (&optional quiet)
6703 "Line up declarations around point.
6704 Be verbose about progress unless optional QUIET set."
6706 (let* ((m1 (make-marker))
6720 ;; (verilog-beg-of-statement-1)
6722 (verilog-forward-syntactic-ws)
6723 (and (not (verilog-in-directive-p)) ; could have `define input foo
6724 (looking-at verilog-declaration-re)))
6726 (if (verilog-parenthesis-depth)
6727 ;; in an argument list or parameter block
6728 (setq el (verilog-backward-up-list -1)
6731 (verilog-backward-up-list 1)
6732 (forward-line) ; ignore ( input foo,
6733 (verilog-re-search-forward verilog-declaration-re el 'move)
6734 (goto-char (match-beginning 0))
6735 (skip-chars-backward " \t")
6737 startpos (set-marker (make-marker) start)
6740 (verilog-backward-up-list -1)
6742 (verilog-backward-syntactic-ws)
6744 endpos (set-marker (make-marker) end)
6748 (skip-chars-forward " \t")
6750 ;; in a declaration block (not in argument list)
6753 (verilog-beg-of-statement-1)
6754 (while (and (looking-at verilog-declaration-re)
6756 (skip-chars-backward " \t")
6759 (verilog-backward-syntactic-ws)
6761 (verilog-beg-of-statement-1))
6763 startpos (set-marker (make-marker) start)
6766 (verilog-end-of-statement)
6767 (setq e (point)) ;Might be on last line
6768 (verilog-forward-syntactic-ws)
6769 (while (looking-at verilog-declaration-re)
6770 (verilog-end-of-statement)
6772 (verilog-forward-syntactic-ws))
6774 endpos (set-marker (make-marker) end)
6777 (verilog-do-indent (verilog-calculate-indent))
6778 (verilog-forward-ws&directives)
6780 ;; OK, start and end are set
6781 (goto-char (marker-position startpos))
6782 (if (and (not quiet)
6783 (> (- end start) 100))
6784 (message "Lining up declarations..(please stand by)"))
6785 ;; Get the beginning of line indent first
6786 (while (progn (setq e (marker-position endpos))
6789 ((save-excursion (skip-chars-backward " \t")
6791 (verilog-forward-ws&directives)
6792 (indent-line-to base-ind)
6793 (verilog-forward-ws&directives)
6795 (verilog-re-search-forward "[ \t\n\f]" e 'move)))
6798 (verilog-re-search-forward "[ \t\n\f]" e 'move)))
6801 ;; Now find biggest prefix
6802 (setq ind (verilog-get-lineup-indent (marker-position startpos) endpos))
6803 ;; Now indent each line.
6804 (goto-char (marker-position startpos))
6805 (while (progn (setq e (marker-position endpos))
6806 (setq r (- e (point)))
6809 (unless quiet (message "%d" r))
6810 ;; (verilog-do-indent (verilog-calculate-indent)))
6811 (verilog-forward-ws&directives)
6813 ((or (and verilog-indent-declaration-macros
6814 (looking-at verilog-declaration-re-2-macro))
6815 (looking-at verilog-declaration-re-2-no-macro))
6816 (let ((p (match-end 0)))
6818 (if (verilog-re-search-forward "[[#`]" p 'move)
6822 (goto-char (marker-position m1))
6828 ((verilog-continued-line-1 (marker-position startpos))
6830 (indent-line-to ind))
6831 ((verilog-in-struct-p)
6832 ;; could have a declaration of a user defined item
6834 (verilog-end-of-statement))
6835 (t ; Must be comment or white space
6837 (verilog-forward-ws&directives)
6840 (unless quiet (message "")))))))
6842 (defun verilog-pretty-expr (&optional quiet _myre)
6843 "Line up expressions around point, optionally QUIET with regexp _MYRE ignored."
6845 (if (not (verilog-in-comment-or-string-p))
6847 (let ( (rexp (concat "^\\s-*" verilog-complete-reg))
6848 (rexp1 (concat "^\\s-*" verilog-basic-complete-re)))
6850 (if (and (not (looking-at rexp ))
6851 (looking-at verilog-assignment-operation-re)
6853 (goto-char (match-end 2))
6854 (and (not (verilog-in-attribute-p))
6855 (not (verilog-in-parameter-p))
6856 (not (verilog-in-comment-or-string-p)))))
6857 (let* ((here (point))
6863 (verilog-backward-syntactic-ws)
6865 (while (and (not (looking-at rexp1))
6866 (looking-at verilog-assignment-operation-re)
6870 (verilog-backward-syntactic-ws)
6872 ) ;Ack, need to grok `define
6878 (setq e (point)) ;Might be on last line
6879 (verilog-forward-syntactic-ws)
6882 (not (looking-at rexp1 ))
6883 (looking-at verilog-assignment-operation-re)
6886 (not (eq e (point)))))
6888 (verilog-forward-syntactic-ws)
6892 (endpos (set-marker (make-marker) end))
6896 (verilog-do-indent (verilog-calculate-indent))
6897 (if (and (not quiet)
6898 (> (- end start) 100))
6899 (message "Lining up expressions..(please stand by)"))
6901 ;; Set indent to minimum throughout region
6902 (while (< (point) (marker-position endpos))
6904 (verilog-just-one-space verilog-assignment-operation-re)
6906 (verilog-do-indent (verilog-calculate-indent))
6908 (verilog-forward-syntactic-ws)
6911 ;; Now find biggest prefix
6912 (setq ind (verilog-get-lineup-indent-2 verilog-assignment-operation-re start endpos))
6914 ;; Now indent each line.
6916 (while (progn (setq e (marker-position endpos))
6917 (setq r (- e (point)))
6920 (if (not quiet) (message "%d" r))
6922 ((looking-at verilog-assignment-operation-re)
6923 (goto-char (match-beginning 2))
6924 (if (not (or (verilog-in-parenthesis-p) ; leave attributes and comparisons alone
6925 (verilog-in-coverage-p)))
6926 (if (eq (char-after) ?=)
6927 (indent-to (1+ ind)) ; line up the = of the <= with surrounding =
6931 ((verilog-continued-line-1 start)
6933 (indent-line-to ind))
6934 (t ; Must be comment or white space
6936 (verilog-forward-ws&directives)
6940 (unless quiet (message ""))
6943 (defun verilog-just-one-space (myre)
6944 "Remove extra spaces around regular expression MYRE."
6946 (if (and (not(looking-at verilog-complete-reg))
6948 (let ((p1 (match-end 1))
6954 (just-one-space)))))
6956 (defun verilog-indent-declaration (baseind)
6957 "Indent current lines as declaration.
6958 Line up the variable names based on previous declaration's indentation.
6959 BASEIND is the base indent to offset everything."
6961 (let ((pos (point-marker))
6962 (lim (save-excursion
6963 ;; (verilog-re-search-backward verilog-declaration-opener nil 'move)
6964 (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)\\|\\(\\<task\\>\\)" nil 'move)
6970 (+ baseind (eval (cdr (assoc 'declaration verilog-indent-alist)))))
6971 (indent-line-to val)
6973 ;; Use previous declaration (in this module) as template.
6974 (if (or (eq 'all verilog-auto-lineup)
6975 (eq 'declarations verilog-auto-lineup))
6976 (if (verilog-re-search-backward
6977 (or (and verilog-indent-declaration-macros
6978 verilog-declaration-re-1-macro)
6979 verilog-declaration-re-1-no-macro) lim t)
6981 (goto-char (match-end 0))
6982 (skip-chars-forward " \t")
6983 (setq ind (current-column))
6987 (eval (cdr (assoc 'declaration verilog-indent-alist)))))
6988 (indent-line-to val)
6989 (if (and verilog-indent-declaration-macros
6990 (looking-at verilog-declaration-re-2-macro))
6991 (let ((p (match-end 0)))
6993 (if (verilog-re-search-forward "[[#`]" p 'move)
6997 (goto-char (marker-position m1))
7000 (if (/= (current-column) ind)
7004 (if (looking-at verilog-declaration-re-2-no-macro)
7005 (let ((p (match-end 0)))
7007 (if (verilog-re-search-forward "[[`#]" p 'move)
7011 (goto-char (marker-position m1))
7014 (if (/= (current-column) ind)
7017 (indent-to ind))))))))))
7020 (defun verilog-get-lineup-indent (b edpos)
7021 "Return the indent level that will line up several lines within the region.
7022 Region is defined by B and EDPOS."
7026 ;; Get rightmost position
7027 (while (progn (setq e (marker-position edpos))
7029 (if (verilog-re-search-forward
7030 (or (and verilog-indent-declaration-macros
7031 verilog-declaration-re-1-macro)
7032 verilog-declaration-re-1-no-macro) e 'move)
7034 (goto-char (match-end 0))
7035 (verilog-backward-syntactic-ws)
7036 (if (> (current-column) ind)
7037 (setq ind (current-column)))
7038 (goto-char (match-end 0)))))
7041 ;; No lineup-string found
7044 (verilog-backward-syntactic-ws)
7045 ;;(skip-chars-backward " \t")
7046 (1+ (current-column))))))
7048 (defun verilog-get-lineup-indent-2 (myre b edpos)
7049 "Return the indent level that will line up several lines within the region."
7053 ;; Get rightmost position
7054 (while (progn (setq e (marker-position edpos))
7056 (if (and (verilog-re-search-forward myre e 'move)
7057 (not (verilog-in-attribute-p))) ; skip attribute exprs
7059 (goto-char (match-beginning 2))
7060 (verilog-backward-syntactic-ws)
7061 (if (> (current-column) ind)
7062 (setq ind (current-column)))
7063 (goto-char (match-end 0)))
7067 ;; No lineup-string found
7070 (skip-chars-backward " \t")
7071 (1+ (current-column))))))
7073 (defun verilog-comment-depth (type val)
7074 "A useful mode debugging aide. TYPE and VAL are comments for insertion."
7081 (if (re-search-backward " /\\* \[#-\]# \[a-zA-Z\]+ \[0-9\]+ ## \\*/" b t)
7083 (replace-match " /* -# ## */")
7087 (insert " /* ## ## */"))))
7090 (format "%s %d" type val))))
7095 (defvar verilog-str nil)
7096 (defvar verilog-all nil)
7097 (defvar verilog-pred nil)
7098 (defvar verilog-buffer-to-use nil)
7099 (defvar verilog-flag nil)
7100 (defvar verilog-toggle-completions nil
7101 "True means \\<verilog-mode-map>\\[verilog-complete-word] should try all possible completions one by one.
7102 Repeated use of \\[verilog-complete-word] will show you all of them.
7103 Normally, when there is more than one possible completion,
7104 it displays a list of all possible completions.")
7107 (defvar verilog-type-keywords
7109 "and" "buf" "bufif0" "bufif1" "cmos" "defparam" "inout" "input"
7110 "integer" "localparam" "logic" "mailbox" "nand" "nmos" "nor" "not" "notif0"
7111 "notif1" "or" "output" "parameter" "pmos" "pull0" "pull1" "pulldown" "pullup"
7112 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran" "rtranif0"
7113 "rtranif1" "semaphore" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1"
7114 "triand" "trior" "trireg" "wand" "wire" "wor" "xnor" "xor"
7116 "Keywords for types used when completing a word in a declaration or parmlist.
7117 \(integer, real, reg...)")
7119 (defvar verilog-cpp-keywords
7120 '("module" "macromodule" "primitive" "timescale" "define" "ifdef" "ifndef" "else"
7122 "Keywords to complete when at first word of a line in declarative scope.
7123 \(initial, always, begin, assign...)
7124 The procedures and variables defined within the Verilog program
7125 will be completed at runtime and should not be added to this list.")
7127 (defvar verilog-defun-keywords
7130 "always" "always_comb" "always_ff" "always_latch" "assign"
7131 "begin" "end" "generate" "endgenerate" "module" "endmodule"
7132 "specify" "endspecify" "function" "endfunction" "initial" "final"
7133 "task" "endtask" "primitive" "endprimitive"
7135 verilog-type-keywords)
7136 "Keywords to complete when at first word of a line in declarative scope.
7137 \(initial, always, begin, assign...)
7138 The procedures and variables defined within the Verilog program
7139 will be completed at runtime and should not be added to this list.")
7141 (defvar verilog-block-keywords
7143 "begin" "break" "case" "continue" "else" "end" "endfunction"
7144 "endgenerate" "endinterface" "endpackage" "endspecify" "endtask"
7145 "for" "fork" "if" "join" "join_any" "join_none" "repeat" "return"
7147 "Keywords to complete when at first word of a line in behavioral scope.
7148 \(begin, if, then, else, for, fork...)
7149 The procedures and variables defined within the Verilog program
7150 will be completed at runtime and should not be added to this list.")
7152 (defvar verilog-tf-keywords
7153 '("begin" "break" "fork" "join" "join_any" "join_none" "case" "end" "endtask" "endfunction" "if" "else" "for" "while" "repeat")
7154 "Keywords to complete when at first word of a line in a task or function.
7155 \(begin, if, then, else, for, fork.)
7156 The procedures and variables defined within the Verilog program
7157 will be completed at runtime and should not be added to this list.")
7159 (defvar verilog-case-keywords
7160 '("begin" "fork" "join" "join_any" "join_none" "case" "end" "endcase" "if" "else" "for" "repeat")
7161 "Keywords to complete when at first word of a line in case scope.
7162 \(begin, if, then, else, for, fork...)
7163 The procedures and variables defined within the Verilog program
7164 will be completed at runtime and should not be added to this list.")
7166 (defvar verilog-separator-keywords
7167 '("else" "then" "begin")
7168 "Keywords to complete when NOT standing at the first word of a statement.
7169 \(else, then, begin...)
7170 Variables and function names defined within the Verilog program
7171 will be completed at runtime and should not be added to this list.")
7173 (defvar verilog-gate-ios
7174 ;; All these have an implied {"input"...} at the end
7188 ("pulldown" "output")
7193 ("rtran" "inout" "inout")
7194 ("rtranif0" "inout" "inout")
7195 ("rtranif1" "inout" "inout")
7196 ("tran" "inout" "inout")
7197 ("tranif0" "inout" "inout")
7198 ("tranif1" "inout" "inout")
7201 "Map of direction for each positional argument to each gate primitive.")
7203 (defvar verilog-gate-keywords (mapcar `car verilog-gate-ios)
7204 "Keywords for gate primitives.")
7206 (defun verilog-string-diff (str1 str2)
7207 "Return index of first letter where STR1 and STR2 differs."
7211 (if (or (> (1+ diff) (length str1))
7212 (> (1+ diff) (length str2)))
7214 (or (equal (aref str1 diff) (aref str2 diff))
7216 (setq diff (1+ diff))))))
7218 ;; Calculate all possible completions for functions if argument is `function',
7219 ;; completions for procedures if argument is `procedure' or both functions and
7220 ;; procedures otherwise.
7222 (defun verilog-func-completion (type)
7223 "Build regular expression for module/task/function names.
7224 TYPE is 'module, 'tf for task or function, or t if unknown."
7225 (if (string= verilog-str "")
7226 (setq verilog-str "[a-zA-Z_]"))
7227 (let ((verilog-str (concat (cond
7228 ((eq type 'module) "\\<\\(module\\)\\s +")
7229 ((eq type 'tf) "\\<\\(task\\|function\\)\\s +")
7230 (t "\\<\\(task\\|function\\|module\\)\\s +"))
7231 "\\<\\(" verilog-str "[a-zA-Z0-9_.]*\\)\\>"))
7234 (if (not (looking-at verilog-defun-re))
7235 (verilog-re-search-backward verilog-defun-re nil t))
7238 ;; Search through all reachable functions
7239 (goto-char (point-min))
7240 (while (verilog-re-search-forward verilog-str (point-max) t)
7241 (progn (setq match (buffer-substring (match-beginning 2)
7243 (if (or (null verilog-pred)
7244 (funcall verilog-pred match))
7245 (setq verilog-all (cons match verilog-all)))))
7246 (if (match-beginning 0)
7247 (goto-char (match-beginning 0)))))
7249 (defun verilog-get-completion-decl (end)
7250 "Macro for searching through current declaration (var, type or const)
7251 for matches of `str' and adding the occurrence tp `all' through point END."
7252 (let ((re (or (and verilog-indent-declaration-macros
7253 verilog-declaration-re-2-macro)
7254 verilog-declaration-re-2-no-macro))
7257 (while (and (< (point) end)
7258 (verilog-re-search-forward re end t))
7259 ;; Traverse current line
7260 (setq decl-end (save-excursion (verilog-declaration-end)))
7261 (while (and (verilog-re-search-forward verilog-symbol-re decl-end t)
7262 (not (match-end 1)))
7263 (setq match (buffer-substring (match-beginning 0) (match-end 0)))
7264 (if (string-match (concat "\\<" verilog-str) match)
7265 (if (or (null verilog-pred)
7266 (funcall verilog-pred match))
7267 (setq verilog-all (cons match verilog-all)))))
7271 (defun verilog-var-completion ()
7272 "Calculate all possible completions for variables (or constants)."
7273 (let ((start (point)))
7274 ;; Search for all reachable var declarations
7275 (verilog-beg-of-defun)
7277 ;; Check var declarations
7278 (verilog-get-completion-decl start))))
7280 (defun verilog-keyword-completion (keyword-list)
7281 "Give list of all possible completions of keywords in KEYWORD-LIST."
7283 (if (string-match (concat "\\<" verilog-str) s)
7284 (if (or (null verilog-pred)
7285 (funcall verilog-pred s))
7286 (setq verilog-all (cons s verilog-all)))))
7290 (defun verilog-completion (verilog-str verilog-pred verilog-flag)
7291 "Function passed to `completing-read', `try-completion' or `all-completions'.
7292 Called to get completion on VERILOG-STR. If VERILOG-PRED is non-nil, it
7293 must be a function to be called for every match to check if this should
7294 really be a match. If VERILOG-FLAG is t, the function returns a list of
7295 all possible completions. If VERILOG-FLAG is nil it returns a string,
7296 the longest possible completion, or t if VERILOG-STR is an exact match.
7297 If VERILOG-FLAG is 'lambda, the function returns t if VERILOG-STR is an
7298 exact match, nil otherwise."
7300 (let ((verilog-all nil))
7301 ;; Set buffer to use for searching labels. This should be set
7302 ;; within functions which use verilog-completions
7303 (set-buffer verilog-buffer-to-use)
7305 ;; Determine what should be completed
7306 (let ((state (car (verilog-calculate-indent))))
7307 (cond ((eq state 'defun)
7308 (save-excursion (verilog-var-completion))
7309 (verilog-func-completion 'module)
7310 (verilog-keyword-completion verilog-defun-keywords))
7312 ((eq state 'behavioral)
7313 (save-excursion (verilog-var-completion))
7314 (verilog-func-completion 'module)
7315 (verilog-keyword-completion verilog-defun-keywords))
7318 (save-excursion (verilog-var-completion))
7319 (verilog-func-completion 'tf)
7320 (verilog-keyword-completion verilog-block-keywords))
7323 (save-excursion (verilog-var-completion))
7324 (verilog-func-completion 'tf)
7325 (verilog-keyword-completion verilog-case-keywords))
7328 (save-excursion (verilog-var-completion))
7329 (verilog-func-completion 'tf)
7330 (verilog-keyword-completion verilog-tf-keywords))
7333 (save-excursion (verilog-var-completion))
7334 (verilog-keyword-completion verilog-cpp-keywords))
7336 ((eq state 'cparenexp)
7337 (save-excursion (verilog-var-completion)))
7340 (save-excursion (verilog-var-completion))
7341 (verilog-func-completion 'both)
7342 (verilog-keyword-completion verilog-separator-keywords))))
7344 ;; Now we have built a list of all matches. Give response to caller
7345 (verilog-completion-response))))
7347 (defun verilog-completion-response ()
7348 (cond ((or (equal verilog-flag 'lambda) (null verilog-flag))
7349 ;; This was not called by all-completions
7350 (if (null verilog-all)
7351 ;; Return nil if there was no matching label
7353 ;; Get longest string common in the labels
7354 ;; FIXME: Why not use `try-completion'?
7355 (let* ((elm (cdr verilog-all))
7356 (match (car verilog-all))
7357 (min (length match))
7359 (if (string= match verilog-str)
7360 ;; Return t if first match was an exact match
7362 (while (not (null elm))
7363 ;; Find longest common string
7364 (if (< (setq tmp (verilog-string-diff match (car elm))) min)
7367 (setq match (substring match 0 min))))
7368 ;; Terminate with match=t if this is an exact match
7369 (if (string= (car elm) verilog-str)
7373 (setq elm (cdr elm)))))
7374 ;; If this is a test just for exact match, return nil ot t
7375 (if (and (equal verilog-flag 'lambda) (not (equal match 't)))
7378 ;; If flag is t, this was called by all-completions. Return
7379 ;; list of all possible completions
7383 (defvar verilog-last-word-numb 0)
7384 (defvar verilog-last-word-shown nil)
7385 (defvar verilog-last-completions nil)
7387 (defun verilog-complete-word ()
7388 "Complete word at current point.
7389 \(See also `verilog-toggle-completions', `verilog-type-keywords',
7390 and `verilog-separator-keywords'.)"
7391 ;; FIXME: Provide completion-at-point-function.
7393 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
7394 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
7395 (verilog-str (buffer-substring b e))
7396 ;; The following variable is used in verilog-completion
7397 (verilog-buffer-to-use (current-buffer))
7398 (allcomp (if (and verilog-toggle-completions
7399 (string= verilog-last-word-shown verilog-str))
7400 verilog-last-completions
7401 (all-completions verilog-str 'verilog-completion)))
7402 (match (if verilog-toggle-completions
7404 verilog-str (mapcar (lambda (elm)
7405 (cons elm 0)) allcomp)))))
7406 ;; Delete old string
7409 ;; Toggle-completions inserts whole labels
7410 (if verilog-toggle-completions
7412 ;; Update entry number in list
7413 (setq verilog-last-completions allcomp
7414 verilog-last-word-numb
7415 (if (>= verilog-last-word-numb (1- (length allcomp)))
7417 (1+ verilog-last-word-numb)))
7418 (setq verilog-last-word-shown (elt allcomp verilog-last-word-numb))
7419 ;; Display next match or same string if no match was found
7420 (if (not (null allcomp))
7421 (insert "" verilog-last-word-shown)
7422 (insert "" verilog-str)
7423 (message "(No match)")))
7424 ;; The other form of completion does not necessarily do that.
7426 ;; Insert match if found, or the original string if no match
7427 (if (or (null match) (equal match 't))
7428 (progn (insert "" verilog-str)
7429 (message "(No match)"))
7431 ;; Give message about current status of completion
7432 (cond ((equal match 't)
7433 (if (not (null (cdr allcomp)))
7434 (message "(Complete but not unique)")
7435 (message "(Sole completion)")))
7436 ;; Display buffer if the current completion didn't help
7437 ;; on completing the label.
7438 ((and (not (null (cdr allcomp))) (= (length verilog-str)
7440 (with-output-to-temp-buffer "*Completions*"
7441 (display-completion-list allcomp))
7442 ;; Wait for a key press. Then delete *Completion* window
7443 (momentary-string-display "" (point))
7444 (delete-window (get-buffer-window (get-buffer "*Completions*")))
7447 (defun verilog-show-completions ()
7448 "Show all possible completions at current point."
7450 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
7451 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
7452 (verilog-str (buffer-substring b e))
7453 ;; The following variable is used in verilog-completion
7454 (verilog-buffer-to-use (current-buffer))
7455 (allcomp (if (and verilog-toggle-completions
7456 (string= verilog-last-word-shown verilog-str))
7457 verilog-last-completions
7458 (all-completions verilog-str 'verilog-completion))))
7459 ;; Show possible completions in a temporary buffer.
7460 (with-output-to-temp-buffer "*Completions*"
7461 (display-completion-list allcomp))
7462 ;; Wait for a key press. Then delete *Completion* window
7463 (momentary-string-display "" (point))
7464 (delete-window (get-buffer-window (get-buffer "*Completions*")))))
7467 (defun verilog-get-default-symbol ()
7468 "Return symbol around current point as a string."
7470 (buffer-substring (progn
7471 (skip-chars-backward " \t")
7472 (skip-chars-backward "a-zA-Z0-9_")
7475 (skip-chars-forward "a-zA-Z0-9_")
7478 (defun verilog-build-defun-re (str &optional arg)
7479 "Return function/task/module starting with STR as regular expression.
7480 With optional second ARG non-nil, STR is the complete name of the instruction."
7482 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "\\)\\>")
7483 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "[a-zA-Z0-9_]*\\)\\>")))
7485 (defun verilog-comp-defun (verilog-str verilog-pred verilog-flag)
7486 "Function passed to `completing-read', `try-completion' or `all-completions'.
7487 Returns a completion on any function name based on VERILOG-STR prefix. If
7488 VERILOG-PRED is non-nil, it must be a function to be called for every match
7489 to check if this should really be a match. If VERILOG-FLAG is t, the
7490 function returns a list of all possible completions. If it is nil it
7491 returns a string, the longest possible completion, or t if VERILOG-STR is
7492 an exact match. If VERILOG-FLAG is 'lambda, the function returns t if
7493 VERILOG-STR is an exact match, nil otherwise."
7495 (let ((verilog-all nil)
7498 ;; Set buffer to use for searching labels. This should be set
7499 ;; within functions which use verilog-completions
7500 (set-buffer verilog-buffer-to-use)
7502 (let ((verilog-str verilog-str))
7503 ;; Build regular expression for functions
7504 (if (string= verilog-str "")
7505 (setq verilog-str (verilog-build-defun-re "[a-zA-Z_]"))
7506 (setq verilog-str (verilog-build-defun-re verilog-str)))
7507 (goto-char (point-min))
7509 ;; Build a list of all possible completions
7510 (while (verilog-re-search-forward verilog-str nil t)
7511 (setq match (buffer-substring (match-beginning 2) (match-end 2)))
7512 (if (or (null verilog-pred)
7513 (funcall verilog-pred match))
7514 (setq verilog-all (cons match verilog-all)))))
7516 ;; Now we have built a list of all matches. Give response to caller
7517 (verilog-completion-response))))
7519 (defun verilog-goto-defun ()
7520 "Move to specified Verilog module/interface/task/function.
7521 The default is a name found in the buffer around point.
7522 If search fails, other files are checked based on
7523 `verilog-library-flags'."
7525 (let* ((default (verilog-get-default-symbol))
7526 ;; The following variable is used in verilog-comp-function
7527 (verilog-buffer-to-use (current-buffer))
7528 (label (if (not (string= default ""))
7529 ;; Do completion with default
7530 (completing-read (concat "Goto-Label: (default "
7532 'verilog-comp-defun nil nil "")
7533 ;; There is no default value. Complete without it
7534 (completing-read "Goto-Label: "
7535 'verilog-comp-defun nil nil "")))
7537 ;; Make sure library paths are correct, in case need to resolve module
7538 (verilog-auto-reeval-locals)
7539 (verilog-getopt-flags)
7540 ;; If there was no response on prompt, use default value
7541 (if (string= label "")
7542 (setq label default))
7543 ;; Goto right place in buffer if label is not an empty string
7544 (or (string= label "")
7547 (goto-char (point-min))
7549 (re-search-forward (verilog-build-defun-re label t) nil t)))
7552 (beginning-of-line))
7554 (verilog-goto-defun-file label))))
7556 ;; Eliminate compile warning
7557 (defvar occur-pos-list)
7559 (defun verilog-showscopes ()
7560 "List all scopes in this module."
7562 (let ((buffer (current-buffer))
7566 (prevpos (point-min))
7567 (final-context-start (make-marker))
7568 (regexp "\\(module\\s-+\\w+\\s-*(\\)\\|\\(\\w+\\s-+\\w+\\s-*(\\)"))
7569 (with-output-to-temp-buffer "*Occur*"
7571 (message "Searching for %s ..." regexp)
7572 ;; Find next match, but give up if prev match was at end of buffer.
7573 (while (and (not (= prevpos (point-max)))
7574 (verilog-re-search-forward regexp nil t))
7575 (goto-char (match-beginning 0))
7578 (setq linenum (+ linenum (count-lines prevpos (point)))))
7579 (setq prevpos (point))
7580 (goto-char (match-end 0))
7581 (let* ((start (save-excursion
7582 (goto-char (match-beginning 0))
7583 (forward-line (if (< nlines 0) nlines (- nlines)))
7585 (end (save-excursion
7586 (goto-char (match-end 0))
7588 (forward-line (1+ nlines))
7591 (tag (format "%3d" linenum))
7592 (empty (make-string (length tag) ?\ ))
7595 (setq tem (make-marker))
7596 (set-marker tem (point))
7597 (set-buffer standard-output)
7598 (setq occur-pos-list (cons tem occur-pos-list))
7599 (or first (zerop nlines)
7600 (insert "--------\n"))
7602 (insert-buffer-substring buffer start end)
7603 (backward-char (- end start))
7604 (setq tem (if (< nlines 0) (- nlines) nlines))
7608 (setq tem (1- tem)))
7609 (let ((this-linenum linenum))
7610 (set-marker final-context-start
7611 (+ (point) (- (match-end 0) (match-beginning 0))))
7612 (while (< (point) final-context-start)
7614 (setq tag (format "%3d" this-linenum)))
7615 (insert tag ?:)))))))
7616 (set-buffer-modified-p nil))))
7619 ;; Highlight helper functions
7620 (defconst verilog-directive-regexp "\\(translate\\|coverage\\|lint\\)_")
7622 (defun verilog-within-translate-off ()
7623 "Return point if within translate-off region, else nil."
7624 (and (save-excursion
7626 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "\\(on\\|off\\)\\>")
7628 (equal "off" (match-string 2))
7631 (defun verilog-start-translate-off (limit)
7632 "Return point before translate-off directive if before LIMIT, else nil."
7633 (when (re-search-forward
7634 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
7636 (match-beginning 0)))
7638 (defun verilog-back-to-start-translate-off (limit)
7639 "Return point before translate-off directive if before LIMIT, else nil."
7640 (when (re-search-backward
7641 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
7643 (match-beginning 0)))
7645 (defun verilog-end-translate-off (limit)
7646 "Return point after translate-on directive if before LIMIT, else nil."
7648 (re-search-forward (concat
7649 "//\\s-*.*\\s-*" verilog-directive-regexp "on\\>") limit t))
7651 (defun verilog-match-translate-off (limit)
7652 "Match a translate-off block, setting `match-data' and returning t, else nil.
7653 Bound search by LIMIT."
7654 (when (< (point) limit)
7655 (let ((start (or (verilog-within-translate-off)
7656 (verilog-start-translate-off limit)))
7657 (case-fold-search t))
7659 (let ((end (or (verilog-end-translate-off limit) limit)))
7660 (set-match-data (list start end))
7661 (goto-char end))))))
7663 (defun verilog-font-lock-match-item (limit)
7664 "Match, and move over, any declaration item after point.
7665 Bound search by LIMIT. Adapted from
7666 `font-lock-match-c-style-declaration-item-and-skip-to-next'."
7669 (narrow-to-region (point-min) limit)
7671 (when (looking-at "\\s-*\\([a-zA-Z]\\w*\\)")
7673 (goto-char (match-end 1))
7674 ;; move to next item
7675 (if (looking-at "\\(\\s-*,\\)")
7676 (goto-char (match-end 1))
7681 ;; Added by Subbu Meiyappan for Header
7683 (defun verilog-header ()
7684 "Insert a standard Verilog file header.
7685 See also `verilog-sk-header' for an alternative format."
7687 (let ((start (point)))
7689 //-----------------------------------------------------------------------------
7691 // Project : <project>
7692 //-----------------------------------------------------------------------------
7693 // File : <filename>
7694 // Author : <author>
7695 // Created : <credate>
7696 // Last modified : <moddate>
7697 //-----------------------------------------------------------------------------
7700 //-----------------------------------------------------------------------------
7701 // Copyright (c) <copydate> by <company> This model is the confidential and
7702 // proprietary property of <company> and the possession or use of this
7703 // file requires a written license from <company>.
7704 //------------------------------------------------------------------------------
7705 // Modification history :
7707 //-----------------------------------------------------------------------------
7711 (search-forward "<filename>")
7712 (replace-match (buffer-name) t t)
7713 (search-forward "<author>") (replace-match "" t t)
7714 (insert (user-full-name))
7715 (insert " <" (user-login-name) "@" (system-name) ">")
7716 (search-forward "<credate>") (replace-match "" t t)
7717 (verilog-insert-date)
7718 (search-forward "<moddate>") (replace-match "" t t)
7719 (verilog-insert-date)
7720 (search-forward "<copydate>") (replace-match "" t t)
7721 (verilog-insert-year)
7722 (search-forward "<modhist>") (replace-match "" t t)
7723 (verilog-insert-date)
7724 (insert " : created")
7727 (setq string (read-string "title: "))
7728 (search-forward "<title>")
7729 (replace-match string t t)
7730 (setq string (read-string "project: " verilog-project))
7731 (setq verilog-project string)
7732 (search-forward "<project>")
7733 (replace-match string t t)
7734 (setq string (read-string "Company: " verilog-company))
7735 (setq verilog-company string)
7736 (search-forward "<company>")
7737 (replace-match string t t)
7738 (search-forward "<company>")
7739 (replace-match string t t)
7740 (search-forward "<company>")
7741 (replace-match string t t)
7742 (search-backward "<description>")
7743 (replace-match "" t t))))
7745 ;; verilog-header Uses the verilog-insert-date function
7747 (defun verilog-insert-date ()
7748 "Insert date from the system."
7750 (if verilog-date-scientific-format
7751 (insert (format-time-string "%Y/%m/%d"))
7752 (insert (format-time-string "%d.%m.%Y"))))
7754 (defun verilog-insert-year ()
7755 "Insert year from the system."
7757 (insert (format-time-string "%Y")))
7760 ;;; Signal list parsing:
7763 ;; Elements of a signal list
7764 ;; Unfortunately we use 'assoc' on this, so can't be a vector
7765 (defsubst verilog-sig-new (name bits comment mem enum signed type multidim modport)
7766 (list name bits comment mem enum signed type multidim modport))
7767 (defsubst verilog-sig-name (sig)
7769 (defsubst verilog-sig-bits (sig) ; First element of packed array (pre signal-name)
7771 (defsubst verilog-sig-comment (sig)
7773 (defsubst verilog-sig-memory (sig) ; Unpacked array (post signal-name)
7775 (defsubst verilog-sig-enum (sig)
7777 (defsubst verilog-sig-signed (sig)
7779 (defsubst verilog-sig-type (sig)
7781 (defsubst verilog-sig-type-set (sig type)
7782 (setcar (nthcdr 6 sig) type))
7783 (defsubst verilog-sig-multidim (sig) ; Second and additional elements of packed array
7785 (defsubst verilog-sig-multidim-string (sig)
7786 (if (verilog-sig-multidim sig)
7787 (let ((str "") (args (verilog-sig-multidim sig)))
7789 (setq str (concat str (car args)))
7790 (setq args (cdr args)))
7792 (defsubst verilog-sig-modport (sig)
7794 (defsubst verilog-sig-width (sig)
7795 (verilog-make-width-expression (verilog-sig-bits sig)))
7797 (defsubst verilog-alw-new (outputs-del outputs-imm temps inputs)
7798 (vector outputs-del outputs-imm temps inputs))
7799 (defsubst verilog-alw-get-outputs-delayed (sigs)
7801 (defsubst verilog-alw-get-outputs-immediate (sigs)
7803 (defsubst verilog-alw-get-temps (sigs)
7805 (defsubst verilog-alw-get-inputs (sigs)
7807 (defsubst verilog-alw-get-uses-delayed (sigs)
7810 (defsubst verilog-modport-new (name clockings decls)
7811 (list name clockings decls))
7812 (defsubst verilog-modport-name (sig)
7814 (defsubst verilog-modport-clockings (sig)
7815 (nth 1 sig)) ; Returns list of names
7816 (defsubst verilog-modport-clockings-add (sig val)
7817 (setcar (nthcdr 1 sig) (cons val (nth 1 sig))))
7818 (defsubst verilog-modport-decls (sig)
7819 (nth 2 sig)) ; Returns verilog-decls-* structure
7820 (defsubst verilog-modport-decls-set (sig val)
7821 (setcar (nthcdr 2 sig) val))
7823 (defsubst verilog-modi-new (name fob pt type)
7824 (vector name fob pt type))
7825 (defsubst verilog-modi-name (modi)
7827 (defsubst verilog-modi-file-or-buffer (modi)
7829 (defsubst verilog-modi-get-point (modi)
7831 (defsubst verilog-modi-get-type (modi) ; "module" or "interface"
7833 (defsubst verilog-modi-get-decls (modi)
7834 (verilog-modi-cache-results modi 'verilog-read-decls))
7835 (defsubst verilog-modi-get-sub-decls (modi)
7836 (verilog-modi-cache-results modi 'verilog-read-sub-decls))
7838 ;; Signal reading for given module
7839 ;; Note these all take modi's - as returned from verilog-modi-current
7840 (defsubst verilog-decls-new (out inout in vars modports assigns consts gparams interfaces)
7841 (vector out inout in vars modports assigns consts gparams interfaces))
7842 (defsubst verilog-decls-append (a b)
7843 (cond ((not a) b) ((not b) a)
7844 (t (vector (append (aref a 0) (aref b 0)) (append (aref a 1) (aref b 1))
7845 (append (aref a 2) (aref b 2)) (append (aref a 3) (aref b 3))
7846 (append (aref a 4) (aref b 4)) (append (aref a 5) (aref b 5))
7847 (append (aref a 6) (aref b 6)) (append (aref a 7) (aref b 7))
7848 (append (aref a 8) (aref b 8))))))
7849 (defsubst verilog-decls-get-outputs (decls)
7851 (defsubst verilog-decls-get-inouts (decls)
7853 (defsubst verilog-decls-get-inputs (decls)
7855 (defsubst verilog-decls-get-vars (decls)
7857 (defsubst verilog-decls-get-modports (decls) ; Also for clocking blocks; contains another verilog-decls struct
7858 (aref decls 4)) ; Returns verilog-modport* structure
7859 (defsubst verilog-decls-get-assigns (decls)
7861 (defsubst verilog-decls-get-consts (decls)
7863 (defsubst verilog-decls-get-gparams (decls)
7865 (defsubst verilog-decls-get-interfaces (decls)
7869 (defsubst verilog-subdecls-new (out inout in intf intfd)
7870 (vector out inout in intf intfd))
7871 (defsubst verilog-subdecls-get-outputs (subdecls)
7873 (defsubst verilog-subdecls-get-inouts (subdecls)
7875 (defsubst verilog-subdecls-get-inputs (subdecls)
7877 (defsubst verilog-subdecls-get-interfaces (subdecls)
7879 (defsubst verilog-subdecls-get-interfaced (subdecls)
7882 (defun verilog-signals-from-signame (signame-list)
7883 "Return signals in standard form from SIGNAME-LIST, a simple list of names."
7884 (mapcar (lambda (name) (verilog-sig-new name nil nil nil nil nil nil nil nil))
7887 (defun verilog-signals-in (in-list not-list)
7888 "Return list of signals in IN-LIST that are also in NOT-LIST.
7889 Also remove any duplicates in IN-LIST.
7890 Signals must be in standard (base vector) form."
7891 ;; This function is hot, so implemented as O(1)
7892 (cond ((eval-when-compile (fboundp 'make-hash-table))
7893 (let ((ht (make-hash-table :test 'equal :rehash-size 4.0))
7894 (ht-not (make-hash-table :test 'equal :rehash-size 4.0))
7897 (puthash (car (car not-list)) t ht-not)
7898 (setq not-list (cdr not-list)))
7900 (when (and (gethash (verilog-sig-name (car in-list)) ht-not)
7901 (not (gethash (verilog-sig-name (car in-list)) ht)))
7902 (setq out-list (cons (car in-list) out-list))
7903 (puthash (verilog-sig-name (car in-list)) t ht))
7904 (setq in-list (cdr in-list)))
7905 (nreverse out-list)))
7906 ;; Slower Fallback if no hash tables (pre Emacs 21.1/XEmacs 21.4)
7910 (if (and (assoc (verilog-sig-name (car in-list)) not-list)
7911 (not (assoc (verilog-sig-name (car in-list)) out-list)))
7912 (setq out-list (cons (car in-list) out-list)))
7913 (setq in-list (cdr in-list)))
7914 (nreverse out-list)))))
7915 ;;(verilog-signals-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("C" "")))
7917 (defun verilog-signals-not-in (in-list not-list)
7918 "Return list of signals in IN-LIST that aren't also in NOT-LIST.
7919 Also remove any duplicates in IN-LIST.
7920 Signals must be in standard (base vector) form."
7921 ;; This function is hot, so implemented as O(1)
7922 (cond ((eval-when-compile (fboundp 'make-hash-table))
7923 (let ((ht (make-hash-table :test 'equal :rehash-size 4.0))
7926 (puthash (car (car not-list)) t ht)
7927 (setq not-list (cdr not-list)))
7929 (when (not (gethash (verilog-sig-name (car in-list)) ht))
7930 (setq out-list (cons (car in-list) out-list))
7931 (puthash (verilog-sig-name (car in-list)) t ht))
7932 (setq in-list (cdr in-list)))
7933 (nreverse out-list)))
7934 ;; Slower Fallback if no hash tables (pre Emacs 21.1/XEmacs 21.4)
7938 (if (and (not (assoc (verilog-sig-name (car in-list)) not-list))
7939 (not (assoc (verilog-sig-name (car in-list)) out-list)))
7940 (setq out-list (cons (car in-list) out-list)))
7941 (setq in-list (cdr in-list)))
7942 (nreverse out-list)))))
7943 ;;(verilog-signals-not-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("EXT" "")))
7945 (defun verilog-signals-not-in-struct (in-list not-list)
7946 "Return list of signals in IN-LIST that aren't also in NOT-LIST.
7947 Also remove any duplicates in IN-LIST.
7948 Any structure in not-list will remove all members in in-list.
7949 Signals must be in standard (base vector) form."
7950 (cond ((eval-when-compile (fboundp 'make-hash-table))
7951 (let ((ht (make-hash-table :test 'equal :rehash-size 4.0))
7954 (puthash (car (car not-list)) t ht)
7955 (setq not-list (cdr not-list)))
7957 (setq nm (verilog-sig-name (car in-list)))
7958 (when (not (gethash nm ht))
7960 (while (string-match "^\\([^\\].*\\)\\.[^.]+$" nm)
7961 (setq nm (match-string 1 nm))
7962 (setq addit (and addit
7963 (not (gethash nm ht)))))
7965 (setq out-list (cons (car in-list) out-list))
7966 (puthash (verilog-sig-name (car in-list)) t ht)))
7967 (setq in-list (cdr in-list)))
7968 (nreverse out-list)))
7969 ;; Slower Fallback if no hash tables (pre Emacs 21.1/XEmacs 21.4)
7971 (let (out-list addit nm)
7973 (setq nm (verilog-sig-name (car in-list)))
7974 (when (and (not (assoc nm not-list))
7975 (not (assoc nm out-list)))
7977 (while (string-match "^\\([^\\].*\\)\\.[^.]+$" nm)
7978 (setq nm (match-string 1 nm))
7979 (setq addit (and addit
7980 (not (assoc nm not-list)))))
7982 (setq out-list (cons (car in-list) out-list))))
7983 (setq in-list (cdr in-list)))
7984 (nreverse out-list)))))
7985 ;;(verilog-signals-not-in-struct '(("A" "") ("B" "") ("DEL.SUB.A" "[2:3]")) '(("DEL.SUB" "") ("EXT" "")))
7987 (defun verilog-signals-memory (in-list)
7988 "Return list of signals in IN-LIST that are memorized (multidimensional)."
7991 (if (nth 3 (car in-list))
7992 (setq out-list (cons (car in-list) out-list)))
7993 (setq in-list (cdr in-list)))
7995 ;;(verilog-signals-memory '(("A" nil nil "[3:0]")) '(("B" nil nil nil)))
7997 (defun verilog-signals-sort-compare (a b)
7998 "Compare signal A and B for sorting."
7999 (string< (verilog-sig-name a) (verilog-sig-name b)))
8001 (defun verilog-signals-not-params (in-list)
8002 "Return list of signals in IN-LIST that aren't parameters or numeric constants."
8005 ;; Namespace intentionally short for AUTOs and compatibility
8006 (unless (boundp (intern (concat "vh-" (verilog-sig-name (car in-list)))))
8007 (setq out-list (cons (car in-list) out-list)))
8008 (setq in-list (cdr in-list)))
8009 (nreverse out-list)))
8011 (defun verilog-signals-with (func in-list)
8012 "Return list of signals where FUNC is true executed on each signal in IN-LIST."
8015 (when (funcall func (car in-list))
8016 (setq out-list (cons (car in-list) out-list)))
8017 (setq in-list (cdr in-list)))
8018 (nreverse out-list)))
8020 (defun verilog-signals-combine-bus (in-list)
8021 "Return a list of signals in IN-LIST, with buses combined.
8022 Duplicate signals are also removed. For example A[2] and A[1] become A[2:1]."
8026 sig highbit lowbit ; Temp information about current signal
8027 sv-name sv-highbit sv-lowbit ; Details about signal we are forming
8028 sv-comment sv-memory sv-enum sv-signed sv-type sv-multidim sv-busstring
8031 ;; Shove signals so duplicated signals will be adjacent
8032 (setq in-list (sort in-list `verilog-signals-sort-compare))
8034 (setq sig (car in-list))
8035 ;; No current signal; form from existing details
8037 (setq sv-name (verilog-sig-name sig)
8040 sv-comment (verilog-sig-comment sig)
8041 sv-memory (verilog-sig-memory sig)
8042 sv-enum (verilog-sig-enum sig)
8043 sv-signed (verilog-sig-signed sig)
8044 sv-type (verilog-sig-type sig)
8045 sv-multidim (verilog-sig-multidim sig)
8046 sv-modport (verilog-sig-modport sig)
8049 ;; Extract bus details
8050 (setq bus (verilog-sig-bits sig))
8051 (setq bus (and bus (verilog-simplify-range-expression bus)))
8053 (or (and (string-match "\\[\\([0-9]+\\):\\([0-9]+\\)\\]" bus)
8054 (setq highbit (string-to-number (match-string 1 bus))
8055 lowbit (string-to-number
8056 (match-string 2 bus))))
8057 (and (string-match "\\[\\([0-9]+\\)\\]" bus)
8058 (setq highbit (string-to-number (match-string 1 bus))
8060 ;; Combine bits in bus
8062 (setq sv-highbit (max highbit sv-highbit)
8063 sv-lowbit (min lowbit sv-lowbit))
8064 (setq sv-highbit highbit
8067 ;; String, probably something like `preproc:0
8068 (setq sv-busstring bus)))
8069 ;; Peek ahead to next signal
8070 (setq in-list (cdr in-list))
8071 (setq sig (car in-list))
8072 (cond ((and sig (equal sv-name (verilog-sig-name sig)))
8073 ;; Combine with this signal
8074 (when (and sv-busstring
8075 (not (equal sv-busstring (verilog-sig-bits sig))))
8076 (when nil ; Debugging
8077 (message (concat "Warning, can't merge into single bus "
8079 ", the AUTOs may be wrong")))
8080 (setq buswarn ", Couldn't Merge"))
8081 (if (verilog-sig-comment sig) (setq combo ", ..."))
8082 (setq sv-memory (or sv-memory (verilog-sig-memory sig))
8083 sv-enum (or sv-enum (verilog-sig-enum sig))
8084 sv-signed (or sv-signed (verilog-sig-signed sig))
8085 sv-type (or sv-type (verilog-sig-type sig))
8086 sv-multidim (or sv-multidim (verilog-sig-multidim sig))
8087 sv-modport (or sv-modport (verilog-sig-modport sig))))
8088 ;; Doesn't match next signal, add to queue, zero in prep for next
8089 ;; Note sig may also be nil for the last signal in the list
8092 (cons (verilog-sig-new
8096 (concat "[" (int-to-string sv-highbit) ":"
8097 (int-to-string sv-lowbit) "]")))
8098 (concat sv-comment combo buswarn)
8099 sv-memory sv-enum sv-signed sv-type sv-multidim sv-modport)
8105 (defun verilog-sig-tieoff (sig)
8106 "Return tieoff expression for given SIG, with appropriate width.
8107 Tieoff value uses `verilog-active-low-regexp' and
8108 `verilog-auto-reset-widths'."
8110 (if (and verilog-active-low-regexp
8111 (verilog-string-match-fold verilog-active-low-regexp (verilog-sig-name sig)))
8113 (cond ((not verilog-auto-reset-widths)
8115 ((equal verilog-auto-reset-widths 'unbased)
8117 ;; Else presume verilog-auto-reset-widths is true
8119 (let* ((width (verilog-sig-width sig)))
8122 ((string-match "^[0-9]+$" width)
8123 (concat width (if (verilog-sig-signed sig) "'sh0" "'h0")))
8125 (concat "{" width "{1'b0}}"))))))))
8131 (defun verilog-decls-princ (decls &optional header prefix)
8132 "For debug, dump the `verilog-read-decls' structure DECLS."
8134 (if header (princ header))
8135 (setq prefix (or prefix ""))
8136 (verilog-signals-princ (verilog-decls-get-outputs decls)
8137 (concat prefix "Outputs:\n") (concat prefix " "))
8138 (verilog-signals-princ (verilog-decls-get-inouts decls)
8139 (concat prefix "Inout:\n") (concat prefix " "))
8140 (verilog-signals-princ (verilog-decls-get-inputs decls)
8141 (concat prefix "Inputs:\n") (concat prefix " "))
8142 (verilog-signals-princ (verilog-decls-get-vars decls)
8143 (concat prefix "Vars:\n") (concat prefix " "))
8144 (verilog-signals-princ (verilog-decls-get-assigns decls)
8145 (concat prefix "Assigns:\n") (concat prefix " "))
8146 (verilog-signals-princ (verilog-decls-get-consts decls)
8147 (concat prefix "Consts:\n") (concat prefix " "))
8148 (verilog-signals-princ (verilog-decls-get-gparams decls)
8149 (concat prefix "Gparams:\n") (concat prefix " "))
8150 (verilog-signals-princ (verilog-decls-get-interfaces decls)
8151 (concat prefix "Interfaces:\n") (concat prefix " "))
8152 (verilog-modport-princ (verilog-decls-get-modports decls)
8153 (concat prefix "Modports:\n") (concat prefix " "))
8156 (defun verilog-signals-princ (signals &optional header prefix)
8157 "For debug, dump internal SIGNALS structures, with HEADER and PREFIX."
8159 (if header (princ header))
8161 (let ((sig (car signals)))
8162 (setq signals (cdr signals))
8164 (princ "\"") (princ (verilog-sig-name sig)) (princ "\"")
8165 (princ " bits=") (princ (verilog-sig-bits sig))
8166 (princ " cmt=") (princ (verilog-sig-comment sig))
8167 (princ " mem=") (princ (verilog-sig-memory sig))
8168 (princ " enum=") (princ (verilog-sig-enum sig))
8169 (princ " sign=") (princ (verilog-sig-signed sig))
8170 (princ " type=") (princ (verilog-sig-type sig))
8171 (princ " dim=") (princ (verilog-sig-multidim sig))
8172 (princ " modp=") (princ (verilog-sig-modport sig))
8175 (defun verilog-modport-princ (modports &optional header prefix)
8176 "For debug, dump internal MODPORT structures, with HEADER and PREFIX."
8178 (if header (princ header))
8180 (let ((sig (car modports)))
8181 (setq modports (cdr modports))
8183 (princ "\"") (princ (verilog-modport-name sig)) (princ "\"")
8184 (princ " clockings=") (princ (verilog-modport-clockings sig))
8186 (verilog-decls-princ (verilog-modport-decls sig)
8187 (concat prefix " syms:\n")
8188 (concat prefix " "))))))
8191 ;; Port/Wire/Etc Reading
8194 (defun verilog-read-inst-backward-name ()
8195 "Internal. Move point back to beginning of inst-name."
8196 (verilog-backward-open-paren)
8199 (verilog-re-search-backward-quick "\\()\\|\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil) ; ] isn't word boundary
8200 (cond ((looking-at ")")
8201 (verilog-backward-open-paren))
8202 (t (setq done t)))))
8203 (while (looking-at "\\]")
8204 (verilog-backward-open-bracket)
8205 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil))
8206 (skip-chars-backward "a-zA-Z0-9`_$"))
8208 (defun verilog-read-inst-module-matcher ()
8209 "Set match data 0 with module_name when point is inside instantiation."
8210 (verilog-read-inst-backward-name)
8211 ;; Skip over instantiation name
8212 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|)\\)" nil nil) ; ) isn't word boundary
8213 ;; Check for parameterized instantiations
8214 (when (looking-at ")")
8215 (verilog-backward-open-paren)
8216 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil))
8217 (skip-chars-backward "a-zA-Z0-9'_$")
8218 ;; #1 is legal syntax for gate primitives
8219 (when (save-excursion
8220 (verilog-backward-syntactic-ws-quick)
8221 (eq ?# (char-before)))
8222 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil)
8223 (skip-chars-backward "a-zA-Z0-9'_$"))
8224 (looking-at "[a-zA-Z0-9`_\$]+")
8225 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
8226 (buffer-substring-no-properties (match-beginning 0) (match-end 0))
8227 ;; Caller assumes match-beginning/match-end is still set
8230 (defun verilog-read-inst-module ()
8231 "Return module_name when point is inside instantiation."
8233 (verilog-read-inst-module-matcher)))
8235 (defun verilog-read-inst-name ()
8236 "Return instance_name when point is inside instantiation."
8238 (verilog-read-inst-backward-name)
8239 (looking-at "[a-zA-Z0-9`_\$]+")
8240 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
8241 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
8243 (defun verilog-read-module-name ()
8244 "Return module name when after its ( or ;."
8246 (re-search-backward "[(;]")
8247 ;; Due to "module x import y (" we must search for declaration begin
8248 (verilog-re-search-backward-quick verilog-defun-re nil nil)
8249 (goto-char (match-end 0))
8250 (verilog-re-search-forward-quick "\\b[a-zA-Z0-9`_\$]+" nil nil)
8251 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
8252 (verilog-symbol-detick
8253 (buffer-substring-no-properties (match-beginning 0) (match-end 0)) t)))
8255 (defun verilog-read-inst-param-value ()
8256 "Return list of parameters and values when point is inside instantiation."
8258 (verilog-read-inst-backward-name)
8259 ;; Skip over instantiation name
8260 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|)\\)" nil nil) ; ) isn't word boundary
8261 ;; If there are parameterized instantiations
8262 (when (looking-at ")")
8263 (let ((end-pt (point))
8265 param-name paren-beg-pt param-value)
8266 (verilog-backward-open-paren)
8267 (while (verilog-re-search-forward-quick "\\." end-pt t)
8268 (verilog-re-search-forward-quick "\\([a-zA-Z0-9`_\$]\\)" nil nil)
8269 (skip-chars-backward "a-zA-Z0-9'_$")
8270 (looking-at "[a-zA-Z0-9`_\$]+")
8271 (setq param-name (buffer-substring-no-properties
8272 (match-beginning 0) (match-end 0)))
8273 (verilog-re-search-forward-quick "(" nil nil)
8274 (setq paren-beg-pt (point))
8275 (verilog-forward-close-paren)
8276 (setq param-value (verilog-string-remove-spaces
8277 (buffer-substring-no-properties
8278 paren-beg-pt (1- (point)))))
8279 (setq params (cons (list param-name param-value) params)))
8282 (defun verilog-read-auto-params (num-param &optional max-param)
8283 "Return parameter list inside auto.
8284 Optional NUM-PARAM and MAX-PARAM check for a specific number of parameters."
8287 ;; /*AUTOPUNT("parameter", "parameter")*/
8289 (while (looking-at "(?\\s *\"\\([^\"]*\\)\"\\s *,?")
8290 (setq olist (cons (match-string 1) olist))
8291 (goto-char (match-end 0))))
8292 (or (eq nil num-param)
8293 (<= num-param (length olist))
8294 (error "%s: Expected %d parameters" (verilog-point-text) num-param))
8295 (if (eq max-param nil) (setq max-param num-param))
8296 (or (eq nil max-param)
8297 (>= max-param (length olist))
8298 (error "%s: Expected <= %d parameters" (verilog-point-text) max-param))
8301 (defun verilog-read-decls ()
8302 "Compute signal declaration information for the current module at point.
8303 Return an array of [outputs inouts inputs wire reg assign const]."
8304 (let ((end-mod-point (or (verilog-get-end-of-defun) (point-max)))
8305 (functask 0) (paren 0) (sig-paren 0) (v2kargs-ok t)
8306 in-modport in-clocking in-ign-to-semi ptype ign-prop
8307 sigs-in sigs-out sigs-inout sigs-var sigs-assign sigs-const
8308 sigs-gparam sigs-intf sigs-modports
8309 vec expect-signal keywd newsig rvalue enum io signed typedefed multidim
8312 ;;(if dbg (setq dbg (concat dbg (format "\n\nverilog-read-decls START PT %s END %s\n" (point) end-mod-point))))
8314 (verilog-beg-of-defun-quick)
8315 (setq sigs-const (verilog-read-auto-constants (point) end-mod-point))
8316 (while (< (point) end-mod-point)
8317 ;;(if dbg (setq dbg (concat dbg (format "Pt %s Vec %s C%c Kwd'%s'\n" (point) vec (following-char) keywd))))
8320 (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
8321 (setq enum (match-string 2)))
8322 (search-forward "\n"))
8323 ((looking-at "/\\*")
8325 (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
8326 (setq enum (match-string 2)))
8327 (or (search-forward "*/")
8328 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
8329 ((looking-at "(\\*")
8330 ;; To advance past either "(*)" or "(* ... *)" don't forward past first *
8332 (or (search-forward "*)")
8333 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
8334 ((eq ?\" (following-char))
8335 (or (re-search-forward "[^\\]\"" nil t) ; don't forward-char first, since we look for a non backslash first
8336 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
8337 ((eq ?\; (following-char))
8338 (cond (in-ign-to-semi ; Such as inside a "import ...;" in a module header
8339 (setq in-ign-to-semi nil))
8340 ((and in-modport (not (eq in-modport t))) ; end of a modport declaration
8341 (verilog-modport-decls-set
8343 (verilog-decls-new sigs-out sigs-inout sigs-in
8344 nil nil nil nil nil nil))
8345 ;; Pop from varstack to restore state to pre-clocking
8346 (setq tmp (car varstack)
8347 varstack (cdr varstack)
8348 sigs-out (aref tmp 0)
8349 sigs-inout (aref tmp 1)
8350 sigs-in (aref tmp 2))
8351 (setq vec nil io nil expect-signal nil newsig nil paren 0 rvalue nil
8352 v2kargs-ok nil in-modport nil ign-prop nil))
8354 (setq vec nil io nil expect-signal nil newsig nil paren 0 rvalue nil
8355 v2kargs-ok nil in-modport nil ign-prop nil)))
8357 ((eq ?= (following-char))
8358 (setq rvalue t newsig nil)
8360 ((and (eq ?, (following-char))
8361 (eq paren sig-paren))
8364 ;; ,'s can occur inside {} & funcs
8365 ((looking-at "[{(]")
8366 (setq paren (1+ paren))
8368 ((looking-at "[})]")
8369 (setq paren (1- paren))
8371 (when (< paren sig-paren)
8372 (setq expect-signal nil rvalue nil))) ; ) that ends variables inside v2k arg list
8373 ((looking-at "\\s-*\\(\\[[^]]+\\]\\)")
8374 (goto-char (match-end 0))
8375 (cond (newsig ; Memory, not just width. Patch last signal added's memory (nth 3)
8376 (setcar (cdr (cdr (cdr newsig)))
8377 (if (verilog-sig-memory newsig)
8378 (concat (verilog-sig-memory newsig) (match-string 1))
8380 (vec ; Multidimensional
8381 (setq multidim (cons vec multidim))
8382 (setq vec (verilog-string-replace-matches
8383 "\\s-+" "" nil nil (match-string 1))))
8385 (setq vec (verilog-string-replace-matches
8386 "\\s-+" "" nil nil (match-string 1))))))
8387 ;; Normal or escaped identifier -- note we remember the \ if escaped
8388 ((looking-at "\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
8389 (goto-char (match-end 0))
8390 (setq keywd (match-string 1))
8391 (when (string-match "^\\\\" (match-string 1))
8392 (setq keywd (concat keywd " "))) ; Escaped ID needs space at end
8393 ;; Add any :: package names to same identifier
8394 (while (looking-at "\\s-*::\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
8395 (goto-char (match-end 0))
8396 (setq keywd (concat keywd "::" (match-string 1)))
8397 (when (string-match "^\\\\" (match-string 1))
8398 (setq keywd (concat keywd " ")))) ; Escaped ID needs space at end
8399 (cond ((equal keywd "input")
8400 (setq vec nil enum nil rvalue nil newsig nil signed nil
8401 typedefed nil multidim nil ptype nil modport nil
8402 expect-signal 'sigs-in io t sig-paren paren))
8403 ((equal keywd "output")
8404 (setq vec nil enum nil rvalue nil newsig nil signed nil
8405 typedefed nil multidim nil ptype nil modport nil
8406 expect-signal 'sigs-out io t sig-paren paren))
8407 ((equal keywd "inout")
8408 (setq vec nil enum nil rvalue nil newsig nil signed nil
8409 typedefed nil multidim nil ptype nil modport nil
8410 expect-signal 'sigs-inout io t sig-paren paren))
8411 ((equal keywd "parameter")
8412 (setq vec nil enum nil rvalue nil signed nil
8413 typedefed nil multidim nil ptype nil modport nil
8414 expect-signal 'sigs-gparam io t sig-paren paren))
8415 ((member keywd '("wire" "reg" ; Fast
8417 "tri" "tri0" "tri1" "triand" "trior" "trireg"
8418 "uwire" "wand" "wor"
8419 ;; integer_atom_type
8420 "byte" "shortint" "int" "longint" "integer" "time"
8422 ;; integer_vector_type - "reg" above
8425 "shortreal" "real" "realtime"
8427 "string" "event" "chandle"))
8430 (if typedefed (concat typedefed " " keywd) keywd)))
8431 (t (setq vec nil enum nil rvalue nil signed nil
8432 typedefed nil multidim nil sig-paren paren
8433 expect-signal 'sigs-var modport nil))))
8434 ((equal keywd "assign")
8435 (setq vec nil enum nil rvalue nil signed nil
8436 typedefed nil multidim nil ptype nil modport nil
8437 expect-signal 'sigs-assign sig-paren paren))
8438 ((member keywd '("localparam" "genvar"))
8439 (setq vec nil enum nil rvalue nil signed nil
8440 typedefed nil multidim nil ptype nil modport nil
8441 expect-signal 'sigs-const sig-paren paren))
8442 ((member keywd '("signed" "unsigned"))
8443 (setq signed keywd))
8444 ((member keywd '("assert" "assume" "cover" "expect" "restrict"))
8446 ((member keywd '("class" "covergroup" "function"
8447 "property" "randsequence" "sequence" "task"))
8449 (setq functask (1+ functask))))
8450 ((member keywd '("endclass" "endgroup" "endfunction"
8451 "endproperty" "endsequence" "endtask"))
8452 (setq functask (1- functask)))
8453 ((equal keywd "modport")
8454 (setq in-modport t))
8455 ((equal keywd "clocking")
8456 (setq in-clocking t))
8457 ((equal keywd "import")
8458 (if v2kargs-ok ; import in module header, not a modport import
8459 (setq in-ign-to-semi t rvalue t)))
8460 ((equal keywd "type")
8462 ((equal keywd "var"))
8463 ;; Ifdef? Ignore name of define
8464 ((member keywd '("`ifdef" "`ifndef" "`elsif"))
8468 (verilog-typedef-name-p keywd))
8471 (if typedefed (concat typedefed " " keywd) keywd)))
8472 (t (setq vec nil enum nil rvalue nil signed nil
8473 typedefed keywd ; Have a type
8474 multidim nil sig-paren paren
8475 expect-signal 'sigs-var modport nil))))
8476 ;; Interface with optional modport in v2k arglist?
8477 ;; Skip over parsing modport, and take the interface name as the type
8481 (looking-at "\\s-*\\(\\.\\(\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*\\)\\|\\)\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*"))
8482 (when (match-end 2) (goto-char (match-end 2)))
8483 (setq vec nil enum nil rvalue nil signed nil
8484 typedefed keywd multidim nil ptype nil modport (match-string 2)
8485 newsig nil sig-paren paren
8486 expect-signal 'sigs-intf io t ))
8487 ;; Ignore dotted LHS assignments: "assign foo.bar = z;"
8488 ((looking-at "\\s-*\\.")
8489 (goto-char (match-end 0))
8491 (setq expect-signal nil)))
8492 ;; "modport <keywd>"
8493 ((and (eq in-modport t)
8494 (not (member keywd verilog-keywords)))
8495 (setq in-modport (verilog-modport-new keywd nil nil))
8496 (setq sigs-modports (cons in-modport sigs-modports))
8497 ;; Push old sig values to stack and point to new signal list
8498 (setq varstack (cons (vector sigs-out sigs-inout sigs-in)
8500 (setq sigs-in nil sigs-inout nil sigs-out nil))
8501 ;; "modport x (clocking <keywd>)"
8502 ((and in-modport in-clocking)
8503 (verilog-modport-clockings-add in-modport keywd)
8504 (setq in-clocking nil))
8507 (equal keywd "endclocking"))
8508 (unless (eq in-clocking t)
8509 (verilog-modport-decls-set
8511 (verilog-decls-new sigs-out sigs-inout sigs-in
8512 nil nil nil nil nil nil))
8513 ;; Pop from varstack to restore state to pre-clocking
8514 (setq tmp (car varstack)
8515 varstack (cdr varstack)
8516 sigs-out (aref tmp 0)
8517 sigs-inout (aref tmp 1)
8518 sigs-in (aref tmp 2)))
8519 (setq in-clocking nil))
8520 ;; "clocking <keywd>"
8521 ((and (eq in-clocking t)
8522 (not (member keywd verilog-keywords)))
8523 (setq in-clocking (verilog-modport-new keywd nil nil))
8524 (setq sigs-modports (cons in-clocking sigs-modports))
8525 ;; Push old sig values to stack and point to new signal list
8526 (setq varstack (cons (vector sigs-out sigs-inout sigs-in)
8528 (setq sigs-in nil sigs-inout nil sigs-out nil))
8529 ;; New signal, maybe?
8533 (not (member keywd verilog-keywords)))
8534 ;; Add new signal to expect-signal's variable
8535 ;;(if dbg (setq dbg (concat dbg (format "Pt %s New sig %s'\n" (point) keywd))))
8536 (setq newsig (verilog-sig-new keywd vec nil nil enum signed typedefed multidim modport))
8537 (set expect-signal (cons newsig
8538 (symbol-value expect-signal))))))
8541 (skip-syntax-forward " "))
8543 (setq tmp (verilog-decls-new (nreverse sigs-out)
8544 (nreverse sigs-inout)
8547 (nreverse sigs-modports)
8548 (nreverse sigs-assign)
8549 (nreverse sigs-const)
8550 (nreverse sigs-gparam)
8551 (nreverse sigs-intf)))
8552 ;;(if dbg (verilog-decls-princ tmp))
8555 (defvar verilog-read-sub-decls-in-interfaced nil
8556 "For `verilog-read-sub-decls', process next signal as under interfaced block.")
8558 (defvar verilog-read-sub-decls-gate-ios nil
8559 "For `verilog-read-sub-decls', gate IO pins remaining, nil if non-primitive.")
8562 ;; Prevent compile warnings; these are let's, not globals
8563 ;; Do not remove the eval-when-compile
8564 ;; - we want an error when we are debugging this code if they are refed.
8572 (defvar sigs-out-unk)
8574 ;; These are known to be from other packages and may not be defined
8575 (defvar diff-command nil)
8576 ;; There are known to be from newer versions of Emacs
8577 (defvar create-lockfiles))
8579 (defun verilog-read-sub-decls-sig (submoddecls comment port sig vec multidim)
8580 "For `verilog-read-sub-decls-line', add a signal."
8581 ;; sig eq t to indicate .name syntax
8582 ;;(message "vrsds: %s(%S)" port sig)
8583 (let ((dotname (eq sig t))
8586 (setq port (verilog-symbol-detick-denumber port))
8587 (setq sig (if dotname port (verilog-symbol-detick-denumber sig)))
8588 (if vec (setq vec (verilog-symbol-detick-denumber vec)))
8589 (if multidim (setq multidim (mapcar `verilog-symbol-detick-denumber multidim)))
8590 (unless (or (not sig)
8591 (equal sig "")) ; Ignore .foo(1'b1) assignments
8592 (cond ((or (setq portdata (assoc port (verilog-decls-get-inouts submoddecls)))
8593 (equal "inout" verilog-read-sub-decls-gate-ios))
8595 (cons (verilog-sig-new
8597 (if dotname (verilog-sig-bits portdata) vec)
8598 (concat "To/From " comment)
8599 (verilog-sig-memory portdata)
8601 (verilog-sig-signed portdata)
8602 (unless (member (verilog-sig-type portdata) '("wire" "reg"))
8603 (verilog-sig-type portdata))
8606 ((or (setq portdata (assoc port (verilog-decls-get-outputs submoddecls)))
8607 (equal "output" verilog-read-sub-decls-gate-ios))
8609 (cons (verilog-sig-new
8611 (if dotname (verilog-sig-bits portdata) vec)
8612 (concat "From " comment)
8613 (verilog-sig-memory portdata)
8615 (verilog-sig-signed portdata)
8616 ;; Though ok in SV, in V2K code, propagating the
8617 ;; "reg" in "output reg" upwards isn't legal.
8618 ;; Also for backwards compatibility we don't propagate
8619 ;; "input wire" upwards.
8620 ;; See also `verilog-signals-edit-wire-reg'.
8621 (unless (member (verilog-sig-type portdata) '("wire" "reg"))
8622 (verilog-sig-type portdata))
8625 ((or (setq portdata (assoc port (verilog-decls-get-inputs submoddecls)))
8626 (equal "input" verilog-read-sub-decls-gate-ios))
8628 (cons (verilog-sig-new
8630 (if dotname (verilog-sig-bits portdata) vec)
8631 (concat "To " comment)
8632 (verilog-sig-memory portdata)
8634 (verilog-sig-signed portdata)
8635 (unless (member (verilog-sig-type portdata) '("wire" "reg"))
8636 (verilog-sig-type portdata))
8639 ((setq portdata (assoc port (verilog-decls-get-interfaces submoddecls)))
8641 (cons (verilog-sig-new
8643 (if dotname (verilog-sig-bits portdata) vec)
8644 (concat "To/From " comment)
8645 (verilog-sig-memory portdata)
8647 (verilog-sig-signed portdata)
8648 (verilog-sig-type portdata)
8651 ((setq portdata (and verilog-read-sub-decls-in-interfaced
8652 (assoc port (verilog-decls-get-vars submoddecls))))
8654 (cons (verilog-sig-new
8656 (if dotname (verilog-sig-bits portdata) vec)
8657 (concat "To/From " comment)
8658 (verilog-sig-memory portdata)
8660 (verilog-sig-signed portdata)
8661 (verilog-sig-type portdata)
8664 ;; (t -- warning pin isn't defined.) ; Leave for lint tool
8667 (defun verilog-read-sub-decls-expr (submoddecls comment port expr)
8668 "For `verilog-read-sub-decls-line', parse a subexpression and add signals."
8669 ;;(message "vrsde: '%s'" expr)
8670 ;; Replace special /*[....]*/ comments inserted by verilog-auto-inst-port
8671 (setq expr (verilog-string-replace-matches "/\\*\\(\\[[^*]+\\]\\)\\*/" "\\1" nil nil expr))
8672 ;; Remove front operators
8673 (setq expr (verilog-string-replace-matches "^\\s-*[---+~!|&]+\\s-*" "" nil nil expr))
8676 ;; {..., a, b} requires us to recurse on a,b
8677 ;; To support {#{},{#{a,b}} we'll just split everything on [{},]
8678 ((string-match "^\\s-*{\\(.*\\)}\\s-*$" expr)
8679 (unless verilog-auto-ignore-concat
8680 (let ((mlst (split-string (match-string 1 expr) "[{},]"))
8682 (while (setq mstr (pop mlst))
8683 (verilog-read-sub-decls-expr submoddecls comment port mstr)))))
8685 (let (sig vec multidim)
8686 ;; Remove leading reduction operators, etc
8687 (setq expr (verilog-string-replace-matches "^\\s-*[---+~!|&]+\\s-*" "" nil nil expr))
8688 ;;(message "vrsde-ptop: '%s'" expr)
8689 (cond ; Find \signal. Final space is part of escaped signal name
8690 ((string-match "^\\s-*\\(\\\\[^ \t\n\f]+\\s-\\)" expr)
8691 ;;(message "vrsde-s: '%s'" (match-string 1 expr))
8692 (setq sig (match-string 1 expr)
8693 expr (substring expr (match-end 0))))
8695 ((string-match "^\\s-*\\([a-zA-Z_][a-zA-Z_0-9]*\\)" expr)
8696 ;;(message "vrsde-s: '%s'" (match-string 1 expr))
8697 (setq sig (verilog-string-remove-spaces (match-string 1 expr))
8698 expr (substring expr (match-end 0)))))
8699 ;; Find [vector] or [multi][multi][multi][vector]
8700 (while (string-match "^\\s-*\\(\\[[^]]+\\]\\)" expr)
8701 ;;(message "vrsde-v: '%s'" (match-string 1 expr))
8702 (when vec (setq multidim (cons vec multidim)))
8703 (setq vec (match-string 1 expr)
8704 expr (substring expr (match-end 0))))
8705 ;; If found signal, and nothing unrecognized, add the signal
8706 ;;(message "vrsde-rem: '%s'" expr)
8707 (when (and sig (string-match "^\\s-*$" expr))
8708 (verilog-read-sub-decls-sig submoddecls comment port sig vec multidim))))))
8710 (defun verilog-read-sub-decls-line (submoddecls comment)
8711 "For `verilog-read-sub-decls', read lines of port defs until none match.
8712 Inserts the list of signals found, using submodi to look up each port."
8718 (cond ((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*(\\s-*")
8719 (setq port (match-string 1))
8720 (goto-char (match-end 0)))
8722 ((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n\f]*\\)\\s-*(\\s-*")
8723 (setq port (concat (match-string 1) " ")) ; escaped id's need trailing space
8724 (goto-char (match-end 0)))
8726 ((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*[,)/]")
8727 (verilog-read-sub-decls-sig
8728 submoddecls comment (match-string 1) t ; sig==t for .name
8729 nil nil) ; vec multidim
8732 ((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n\f]*\\)\\s-*[,)/]")
8733 (verilog-read-sub-decls-sig
8734 submoddecls comment (concat (match-string 1) " ") t ; sig==t for .name
8735 nil nil) ; vec multidim
8738 ((looking-at "\\s-*\\.[^(]*(")
8739 (setq port nil) ; skip this line
8740 (goto-char (match-end 0)))
8742 (setq port nil done t))) ; Unknown, ignore rest of line
8743 ;; Get signal name. Point is at the first-non-space after (
8744 ;; We intentionally ignore (non-escaped) signals with .s in them
8745 ;; this prevents AUTOWIRE etc from noticing hierarchical sigs.
8747 (cond ((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*)")
8748 (verilog-read-sub-decls-sig
8749 submoddecls comment port
8750 (verilog-string-remove-spaces (match-string 1)) ; sig
8751 nil nil)) ; vec multidim
8753 ((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*)")
8754 (verilog-read-sub-decls-sig
8755 submoddecls comment port
8756 (verilog-string-remove-spaces (match-string 1)) ; sig
8757 (match-string 2) nil)) ; vec multidim
8758 ;; Fastpath was above looking-at's.
8759 ;; For something more complicated invoke a parser
8760 ((looking-at "[^)]+")
8761 (verilog-read-sub-decls-expr
8762 submoddecls comment port
8764 (point) (1- (progn (search-backward "(") ; start at (
8765 (verilog-forward-sexp-ign-cmt 1)
8766 (point)))))))) ; expr
8768 (forward-line 1)))))
8770 (defun verilog-read-sub-decls-gate (submoddecls comment submod end-inst-point)
8771 "For `verilog-read-sub-decls', read lines of UDP gate decl until none match.
8772 Inserts the list of signals found."
8774 (let ((iolist (cdr (assoc submod verilog-gate-ios))))
8775 (while (< (point) end-inst-point)
8776 ;; Get primitive's signal name, as will never have port, and no trailing )
8777 (cond ((looking-at "//")
8778 (search-forward "\n"))
8779 ((looking-at "/\\*")
8780 (or (search-forward "*/")
8781 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
8782 ((looking-at "(\\*")
8783 ;; To advance past either "(*)" or "(* ... *)" don't forward past first *
8785 (or (search-forward "*)")
8786 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
8787 ;; On pins, parse and advance to next pin
8788 ;; Looking at pin, but *not* an // Output comment, or ) to end the inst
8789 ((looking-at "\\s-*[a-zA-Z0-9`_$({}\\\\][^,]*")
8790 (goto-char (match-end 0))
8791 (setq verilog-read-sub-decls-gate-ios (or (car iolist) "input")
8792 iolist (cdr iolist))
8793 (verilog-read-sub-decls-expr
8794 submoddecls comment "primitive_port"
8798 (skip-syntax-forward " ")))))))
8800 (defun verilog-read-sub-decls ()
8801 "Internally parse signals going to modules under this module.
8802 Return an array of [ outputs inouts inputs ] signals for modules that are
8803 instantiated in this module. For example if declare A A (.B(SIG)) and SIG
8804 is an output, then SIG will be included in the list.
8806 This only works on instantiations created with /*AUTOINST*/ converted by
8807 \\[verilog-auto-inst]. Otherwise, it would have to read in the whole
8808 component library to determine connectivity of the design.
8810 One work around for this problem is to manually create // Inputs and //
8811 Outputs comments above subcell signals, for example:
8819 (let ((end-mod-point (verilog-get-end-of-defun))
8820 st-point end-inst-point
8821 ;; below 3 modified by verilog-read-sub-decls-line
8822 sigs-out sigs-inout sigs-in sigs-intf sigs-intfd)
8823 (verilog-beg-of-defun-quick)
8824 (while (verilog-re-search-forward-quick "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-mod-point t)
8826 (goto-char (match-beginning 0))
8827 (unless (verilog-inside-comment-or-string-p)
8828 ;; Attempt to snarf a comment
8829 (let* ((submod (verilog-read-inst-module))
8830 (inst (verilog-read-inst-name))
8831 (subprim (member submod verilog-gate-keywords))
8832 (comment (concat inst " of " submod ".v"))
8833 submodi submoddecls)
8836 (setq submodi `primitive
8837 submoddecls (verilog-decls-new nil nil nil nil nil nil nil nil nil)
8838 comment (concat inst " of " submod))
8839 (verilog-backward-open-paren)
8840 (setq end-inst-point (save-excursion (verilog-forward-sexp-ign-cmt 1)
8844 (verilog-read-sub-decls-gate submoddecls comment submod end-inst-point))
8847 (when (setq submodi (verilog-modi-lookup submod t))
8848 (setq submoddecls (verilog-modi-get-decls submodi)
8849 verilog-read-sub-decls-gate-ios nil)
8850 (verilog-backward-open-paren)
8851 (setq end-inst-point (save-excursion (verilog-forward-sexp-ign-cmt 1)
8854 ;; This could have used a list created by verilog-auto-inst
8855 ;; However I want it to be runnable even on user's manually added signals
8856 (let ((verilog-read-sub-decls-in-interfaced t))
8857 (while (re-search-forward "\\s *(?\\s *// Interfaced" end-inst-point t)
8858 (verilog-read-sub-decls-line submoddecls comment))) ; Modifies sigs-ifd
8859 (goto-char st-point)
8860 (while (re-search-forward "\\s *(?\\s *// Interfaces" end-inst-point t)
8861 (verilog-read-sub-decls-line submoddecls comment)) ; Modifies sigs-out
8862 (goto-char st-point)
8863 (while (re-search-forward "\\s *(?\\s *// Outputs" end-inst-point t)
8864 (verilog-read-sub-decls-line submoddecls comment)) ; Modifies sigs-out
8865 (goto-char st-point)
8866 (while (re-search-forward "\\s *(?\\s *// Inouts" end-inst-point t)
8867 (verilog-read-sub-decls-line submoddecls comment)) ; Modifies sigs-inout
8868 (goto-char st-point)
8869 (while (re-search-forward "\\s *(?\\s *// Inputs" end-inst-point t)
8870 (verilog-read-sub-decls-line submoddecls comment)) ; Modifies sigs-in
8872 ;; Combine duplicate bits
8873 ;;(setq rr (vector sigs-out sigs-inout sigs-in))
8874 (verilog-subdecls-new
8875 (verilog-signals-combine-bus (nreverse sigs-out))
8876 (verilog-signals-combine-bus (nreverse sigs-inout))
8877 (verilog-signals-combine-bus (nreverse sigs-in))
8878 (verilog-signals-combine-bus (nreverse sigs-intf))
8879 (verilog-signals-combine-bus (nreverse sigs-intfd))))))
8881 (defun verilog-read-inst-pins ()
8882 "Return an array of [ pins ] for the current instantiation at point.
8883 For example if declare A A (.B(SIG)) then B will be included in the list."
8885 (let ((end-mod-point (point)) ; presume at /*AUTOINST*/ point
8887 (verilog-backward-open-paren)
8888 (while (re-search-forward "\\.\\([^(,) \t\n\f]*\\)\\s-*" end-mod-point t)
8889 (setq pin (match-string 1))
8890 (unless (verilog-inside-comment-or-string-p)
8891 (setq pins (cons (list pin) pins))
8892 (when (looking-at "(")
8893 (verilog-forward-sexp-ign-cmt 1))))
8896 (defun verilog-read-arg-pins ()
8897 "Return an array of [ pins ] for the current argument declaration at point."
8899 (let ((end-mod-point (point)) ; presume at /*AUTOARG*/ point
8901 (verilog-backward-open-paren)
8902 (while (re-search-forward "\\([a-zA-Z0-9$_.%`]+\\)" end-mod-point t)
8903 (setq pin (match-string 1))
8904 (unless (verilog-inside-comment-or-string-p)
8905 (setq pins (cons (list pin) pins))))
8908 (defun verilog-read-auto-constants (beg end-mod-point)
8909 "Return a list of AUTO_CONSTANTs used in the region from BEG to END-MOD-POINT."
8912 (let (sig-list tpl-end-pt)
8914 (while (re-search-forward "\\<AUTO_CONSTANT" end-mod-point t)
8915 (if (not (looking-at "\\s *("))
8916 (error "%s: Missing () after AUTO_CONSTANT" (verilog-point-text)))
8917 (search-forward "(" end-mod-point)
8918 (setq tpl-end-pt (save-excursion
8920 (verilog-forward-sexp-cmt 1) ; Moves to paren that closes argdecl's
8923 (while (re-search-forward "\\s-*\\([\"a-zA-Z0-9$_.%`]+\\)\\s-*,*" tpl-end-pt t)
8924 (setq sig-list (cons (list (match-string 1) nil nil) sig-list))))
8927 (defvar verilog-cache-has-lisp nil "True if any AUTO_LISP in buffer.")
8928 (make-variable-buffer-local 'verilog-cache-has-lisp)
8930 (defun verilog-read-auto-lisp-present ()
8931 "Set `verilog-cache-has-lisp' if any AUTO_LISP in this buffer."
8933 (goto-char (point-min))
8934 (setq verilog-cache-has-lisp (re-search-forward "\\<AUTO_LISP(" nil t))))
8936 (defun verilog-read-auto-lisp (start end)
8937 "Look for and evaluate an AUTO_LISP between START and END.
8938 Must call `verilog-read-auto-lisp-present' before this function."
8939 ;; This function is expensive for large buffers, so we cache if any AUTO_LISP exists
8940 (when verilog-cache-has-lisp
8943 (while (re-search-forward "\\<AUTO_LISP(" end t)
8945 (let* ((beg-pt (prog1 (point)
8946 (verilog-forward-sexp-cmt 1))) ; Closing paren
8948 (verilog-in-hooks t))
8949 (eval-region beg-pt end-pt nil))))))
8951 (defun verilog-read-always-signals-recurse
8952 (exit-keywd rvalue temp-next)
8953 "Recursive routine for parentheses/bracket matching.
8954 EXIT-KEYWD is expression to stop at, nil if top level.
8955 RVALUE is true if at right hand side of equal.
8956 IGNORE-NEXT is true to ignore next token, fake from inside case statement."
8957 (let* ((semi-rvalue (equal "endcase" exit-keywd)) ; true if after a ; we are looking for rvalue
8958 keywd last-keywd sig-tolk sig-last-tolk gotend got-sig got-list end-else-check
8960 ;;(if dbg (setq dbg (concat dbg (format "Recursion %S %S %S\n" exit-keywd rvalue temp-next))))
8961 (while (not (or (eobp) gotend))
8964 (search-forward "\n"))
8965 ((looking-at "/\\*")
8966 (or (search-forward "*/")
8967 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
8968 ((looking-at "(\\*")
8969 ;; To advance past either "(*)" or "(* ... *)" don't forward past first *
8971 (or (search-forward "*)")
8972 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
8973 (t (setq keywd (buffer-substring-no-properties
8975 (save-excursion (when (eq 0 (skip-chars-forward "a-zA-Z0-9$_.%`"))
8978 sig-last-tolk sig-tolk
8980 ;;(if dbg (setq dbg (concat dbg (format "\tPt=%S %S\trv=%S in=%S ee=%S gs=%S\n" (point) keywd rvalue ignore-next end-else-check got-sig))))
8983 (or (re-search-forward "[^\\]\"" nil t)
8984 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
8985 ;; else at top level loop, keep parsing
8986 ((and end-else-check (equal keywd "else"))
8987 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else %s\n" keywd))))
8988 ;; no forward movement, want to see else in lower loop
8989 (setq end-else-check nil))
8990 ;; End at top level loop
8991 ((and end-else-check (looking-at "[^ \t\n\f]"))
8992 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else-other %s\n" keywd))))
8995 ((and exit-keywd (equal keywd exit-keywd))
8997 (forward-char (length keywd)))
8998 ;; Standard tokens...
9000 (setq ignore-next nil rvalue semi-rvalue)
9001 ;; Final statement at top level loop?
9002 (when (not exit-keywd)
9003 ;;(if dbg (setq dbg (concat dbg (format "\ttop-end-check %s\n" keywd))))
9004 (setq end-else-check t))
9007 (if (looking-at "'[sS]?[hdxboHDXBO]?[ \t]*[0-9a-fA-F_xzXZ?]+")
9008 (goto-char (match-end 0))
9010 ((equal keywd ":") ; Case statement, begin/end label, x?y:z
9011 (cond ((equal "endcase" exit-keywd) ; case x: y=z; statement next
9012 (setq ignore-next nil rvalue nil))
9013 ((equal "?" exit-keywd) ; x?y:z rvalue
9015 ((equal "]" exit-keywd) ; [x:y] rvalue
9017 (got-sig ; label: statement
9018 (setq ignore-next nil rvalue semi-rvalue got-sig nil))
9019 ((not rvalue) ; begin label
9020 (setq ignore-next t rvalue nil)))
9024 ;;(if dbg (setq dbg (concat dbg (format "\t\tequal got-sig=%S got-list=%s\n" got-sig got-list))))
9025 (set got-list (cons got-sig (symbol-value got-list)))
9028 (if (eq (char-before) ?< )
9029 (setq sigs-out-d (append sigs-out-d sigs-out-unk)
9031 (setq sigs-out-i (append sigs-out-i sigs-out-unk)
9033 (setq ignore-next nil rvalue t)
9037 (verilog-read-always-signals-recurse ":" rvalue nil))
9040 (verilog-read-always-signals-recurse "]" t nil))
9043 (cond (sig-last-tolk ; Function call; zap last signal
9044 (setq got-sig nil)))
9045 (cond ((equal last-keywd "for")
9046 ;; temp-next: Variables on LHS are lvalues, but generally we want
9047 ;; to ignore them, assuming they are loop increments
9048 (verilog-read-always-signals-recurse ";" nil t)
9049 (verilog-read-always-signals-recurse ";" t nil)
9050 (verilog-read-always-signals-recurse ")" nil nil))
9051 (t (verilog-read-always-signals-recurse ")" t nil))))
9052 ((equal keywd "begin")
9053 (skip-syntax-forward "w_")
9054 (verilog-read-always-signals-recurse "end" nil nil)
9055 ;;(if dbg (setq dbg (concat dbg (format "\tgot-end %s\n" exit-keywd))))
9056 (setq ignore-next nil rvalue semi-rvalue)
9057 (if (not exit-keywd) (setq end-else-check t)))
9058 ((member keywd '("case" "casex" "casez"))
9059 (skip-syntax-forward "w_")
9060 (verilog-read-always-signals-recurse "endcase" t nil)
9061 (setq ignore-next nil rvalue semi-rvalue)
9062 (if (not exit-keywd) (setq gotend t))) ; top level begin/end
9063 ((string-match "^[$`a-zA-Z_]" keywd) ; not exactly word constituent
9064 (cond ((member keywd '("`ifdef" "`ifndef" "`elsif"))
9065 (setq ignore-next t))
9067 (member keywd verilog-keywords)
9068 (string-match "^\\$" keywd)) ; PLI task
9069 (setq ignore-next nil))
9071 (setq keywd (verilog-symbol-detick-denumber keywd))
9073 (set got-list (cons got-sig (symbol-value got-list)))
9074 ;;(if dbg (setq dbg (concat dbg (format "\t\tgot-sig=%S got-list=%S\n" got-sig got-list))))
9076 (setq got-list (cond (temp-next 'sigs-temp)
9079 got-sig (if (or (not keywd)
9080 (assoc keywd (symbol-value got-list)))
9081 nil (list keywd nil nil))
9084 (skip-chars-forward "a-zA-Z0-9$_.%`"))
9087 ;; End of non-comment token
9088 (setq last-keywd keywd)))
9089 (skip-syntax-forward " "))
9090 ;; Append the final pending signal
9092 ;;(if dbg (setq dbg (concat dbg (format "\t\tfinal got-sig=%S got-list=%s\n" got-sig got-list))))
9093 (set got-list (cons got-sig (symbol-value got-list)))
9095 ;;(if dbg (setq dbg (concat dbg (format "ENDRecursion %s\n" exit-keywd))))
9098 (defun verilog-read-always-signals ()
9099 "Parse always block at point and return list of (outputs inout inputs)."
9102 sigs-out-d sigs-out-i sigs-out-unk sigs-temp sigs-in)
9103 (verilog-read-always-signals-recurse nil nil nil)
9104 (setq sigs-out-i (append sigs-out-i sigs-out-unk)
9106 ;;(if dbg (with-current-buffer (get-buffer-create "*vl-dbg*")) (delete-region (point-min) (point-max)) (insert dbg) (setq dbg ""))
9107 ;; Return what was found
9108 (verilog-alw-new sigs-out-d sigs-out-i sigs-temp sigs-in))))
9110 (defun verilog-read-instants ()
9111 "Parse module at point and return list of ( ( file instance ) ... )."
9112 (verilog-beg-of-defun-quick)
9113 (let* ((end-mod-point (verilog-get-end-of-defun))
9115 (instants-list nil))
9117 (while (< (point) end-mod-point)
9118 ;; Stay at level 0, no comments
9120 (setq state (parse-partial-sexp (point) end-mod-point 0 t nil))
9121 (or (> (car state) 0) ; in parens
9122 (nth 5 state) ; comment
9126 (if (looking-at "^\\s-*\\([a-zA-Z0-9`_$]+\\)\\s-+\\([a-zA-Z0-9`_$]+\\)\\s-*(")
9127 ;;(if (looking-at "^\\(.+\\)$")
9128 (let ((module (match-string 1))
9129 (instant (match-string 2)))
9130 (if (not (member module verilog-keywords))
9131 (setq instants-list (cons (list module instant) instants-list)))))
9136 (defun verilog-read-auto-template-middle ()
9137 "With point in middle of an AUTO_TEMPLATE, parse it.
9138 Returns REGEXP and list of ( (signal_name connection_name)... )."
9141 (let ((tpl-regexp "\\([0-9]+\\)")
9142 (lineno -1) ; -1 to offset for the AUTO_TEMPLATE's newline
9144 tpl-sig-list tpl-wild-list tpl-end-pt rep)
9146 ;; We reserve @"..." for future lisp expressions that evaluate
9147 ;; once-per-AUTOINST
9148 (when (looking-at "\\s-*\"\\([^\"]*\\)\"")
9149 (setq tpl-regexp (match-string 1))
9150 (goto-char (match-end 0)))
9151 (search-forward "(")
9152 ;; Parse lines in the template
9153 (when (or verilog-auto-inst-template-numbers
9154 verilog-auto-template-warn-unused)
9156 (let ((pre-pt (point)))
9157 (goto-char (point-min))
9158 (while (search-forward "AUTO_TEMPLATE" pre-pt t)
9159 (setq templateno (1+ templateno)))
9160 (while (< (point) pre-pt)
9162 (setq lineno (1+ lineno))))))
9163 (setq tpl-end-pt (save-excursion
9165 (verilog-forward-sexp-cmt 1) ; Moves to paren that closes argdecl's
9169 (while (< (point) tpl-end-pt)
9170 (cond ((looking-at "\\s-*\\.\\([a-zA-Z0-9`_$]+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
9173 (match-string-no-properties 1)
9174 (match-string-no-properties 2)
9177 (goto-char (match-end 0)))
9180 ;; Regexp bug in XEmacs disallows ][ inside [], and wants + last
9181 "\\s-*\\.\\(\\([a-zA-Z0-9`_$+@^.*?|---]+\\|[][]\\|\\\\[()|]\\)+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
9182 (setq rep (match-string-no-properties 3))
9183 (goto-char (match-end 0))
9187 (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil
9193 ((looking-at "[ \t\f]+")
9194 (goto-char (match-end 0)))
9196 (setq lineno (1+ lineno))
9197 (goto-char (match-end 0)))
9199 (search-forward "\n")
9200 (setq lineno (1+ lineno)))
9201 ((looking-at "/\\*")
9203 (or (search-forward "*/")
9204 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
9206 (error "%s: AUTO_TEMPLATE parsing error: %s"
9207 (verilog-point-text)
9208 (progn (looking-at ".*$") (match-string 0))))))
9211 (list tpl-sig-list tpl-wild-list)))))
9213 (defun verilog-read-auto-template (module)
9214 "Look for an auto_template for the instantiation of the given MODULE.
9215 If found returns `verilog-read-auto-template-inside' structure."
9219 ;; Note this search is expensive, as we hunt from mod-begin to point
9220 ;; for every instantiation. Likewise in verilog-read-auto-lisp.
9221 ;; So, we look first for an exact string rather than a slow regexp.
9222 ;; Someday we may keep a cache of every template, but this would also
9223 ;; need to record the relative position of each AUTOINST, as multiple
9224 ;; templates exist for each module, and we're inserting lines.
9226 ;; See also regexp in `verilog-auto-template-lint'
9227 (verilog-re-search-backward-substr
9229 (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)
9230 ;; Also try forward of this AUTOINST
9231 ;; This is for historical support; this isn't speced as working
9234 (verilog-re-search-forward-substr
9236 (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)))
9237 (goto-char (match-end 0))
9238 (verilog-read-auto-template-middle))
9239 ;; If no template found
9240 (t (vector "" nil))))))
9241 ;;(progn (find-file "auto-template.v") (verilog-read-auto-template "ptl_entry"))
9243 (defvar verilog-auto-template-hits nil "Successful lookups with `verilog-read-auto-template-hit'.")
9244 (make-variable-buffer-local 'verilog-auto-template-hits)
9246 (defun verilog-read-auto-template-init ()
9247 "Initialize `verilog-read-auto-template'."
9248 (when (eval-when-compile (fboundp 'make-hash-table)) ; else feature not allowed
9249 (when verilog-auto-template-warn-unused
9250 (setq verilog-auto-template-hits
9251 (make-hash-table :test 'equal :rehash-size 4.0)))))
9253 (defun verilog-read-auto-template-hit (tpl-ass)
9254 "Record that TPL-ASS template from `verilog-read-auto-template' was used."
9255 (when (eval-when-compile (fboundp 'make-hash-table)) ; else feature not allowed
9256 (when verilog-auto-template-warn-unused
9257 (unless verilog-auto-template-hits
9258 (verilog-read-auto-template-init))
9259 (puthash (vector (nth 2 tpl-ass) (nth 3 tpl-ass)) t
9260 verilog-auto-template-hits))))
9262 (defun verilog-set-define (defname defvalue &optional buffer enumname)
9263 "Set the definition DEFNAME to the DEFVALUE in the given BUFFER.
9264 Optionally associate it with the specified enumeration ENUMNAME."
9265 (with-current-buffer (or buffer (current-buffer))
9266 ;; Namespace intentionally short for AUTOs and compatibility
9267 (let ((mac (intern (concat "vh-" defname))))
9268 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
9269 ;; Need to define to a constant if no value given
9270 (set (make-local-variable mac)
9271 (if (equal defvalue "") "1" defvalue)))
9273 ;; Namespace intentionally short for AUTOs and compatibility
9274 (let ((enumvar (intern (concat "venum-" enumname))))
9275 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
9276 (unless (boundp enumvar) (set enumvar nil))
9277 (add-to-list (make-local-variable enumvar) defname)))))
9279 (defun verilog-read-defines (&optional filename recurse subcall)
9280 "Read \\=`defines and parameters for the current file, or optional FILENAME.
9281 If the filename is provided, `verilog-library-flags' will be used to
9282 resolve it. If optional RECURSE is non-nil, recurse through \\=`includes.
9284 Parameters must be simple assignments to constants, or have their own
9285 \"parameter\" label rather than a list of parameters. Thus:
9287 parameter X = 5, Y = 10; // Ok
9288 parameter X = {1'b1, 2'h2}; // Ok
9289 parameter X = {1'b1, 2'h2}, Y = 10; // Bad, make into 2 parameter lines
9291 Defines must be simple text substitutions, one on a line, starting
9292 at the beginning of the line. Any ifdefs or multiline comments around the
9295 Defines are stored inside Emacs variables using the name vh-{definename}.
9297 This function is useful for setting vh-* variables. The file variables
9298 feature can be used to set defines that `verilog-mode' can see; put at the
9299 *END* of your file something like:
9302 // vh-macro:\"macro_definition\"
9305 If macros are defined earlier in the same file and you want their values,
9306 you can read them automatically (provided `enable-local-eval' is on):
9309 // eval:(verilog-read-defines)
9310 // eval:(verilog-read-defines \"group_standard_includes.v\")
9313 Note these are only read when the file is first visited, you must use
9314 \\[find-alternate-file] RET to have these take effect after editing them!
9316 If you want to disable the \"Process `eval' or hook local variables\"
9317 warning message, you need to add to your init file:
9319 (setq enable-local-eval t)"
9320 (let ((origbuf (current-buffer)))
9322 (unless subcall (verilog-getopt-flags))
9324 (let ((fns (verilog-library-filenames filename (buffer-file-name))))
9326 (set-buffer (find-file-noselect (car fns)))
9327 (error (concat (verilog-point-text)
9328 ": Can't find verilog-read-defines file: " filename)))))
9330 (goto-char (point-min))
9331 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
9332 (let ((inc (verilog-string-replace-matches
9333 "\"" "" nil nil (match-string-no-properties 1))))
9334 (unless (verilog-inside-comment-or-string-p)
9335 (verilog-read-defines inc recurse t)))))
9337 ;; note we don't use verilog-re... it's faster this way, and that
9338 ;; function has problems when comments are at the end of the define
9339 (goto-char (point-min))
9340 (while (re-search-forward "^\\s-*`define\\s-+\\([a-zA-Z0-9_$]+\\)\\s-+\\(.*\\)$" nil t)
9341 (let ((defname (match-string-no-properties 1))
9342 (defvalue (match-string-no-properties 2)))
9343 (unless (verilog-inside-comment-or-string-p (match-beginning 0))
9344 (setq defvalue (verilog-string-replace-matches "\\s-*/[/*].*$" "" nil nil defvalue))
9345 (verilog-set-define defname defvalue origbuf))))
9346 ;; Hack: Read parameters
9347 (goto-char (point-min))
9348 (while (re-search-forward
9349 "^\\s-*\\(parameter\\|localparam\\)\\(\\s-*\\[[^]]*\\]\\)?\\s-*" nil t)
9351 ;; The primary way of getting defines is verilog-read-decls
9352 ;; However, that isn't called yet for included files, so we'll add another scheme
9353 (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
9354 (setq enumname (match-string-no-properties 2)))
9355 (forward-comment 99999)
9356 (while (looking-at (concat "\\s-*,?\\s-*\\(?:/[/*].*?$\\)?\\s-*\\([a-zA-Z0-9_$]+\\)"
9357 "\\s-*=\\s-*\\([^;,]*\\),?\\s-*\\(/[/*].*?$\\)?\\s-*"))
9358 (unless (verilog-inside-comment-or-string-p (match-beginning 0))
9359 (verilog-set-define (match-string-no-properties 1)
9360 (match-string-no-properties 2) origbuf enumname))
9361 (goto-char (match-end 0))
9362 (forward-comment 99999)))))))
9364 (defun verilog-read-includes ()
9365 "Read \\=`includes for the current file.
9366 This will find all of the \\=`includes which are at the beginning of lines,
9367 ignoring any ifdefs or multiline comments around them.
9368 `verilog-read-defines' is then performed on the current and each included
9371 It is often useful put at the *END* of your file something like:
9374 // eval:(verilog-read-defines)
9375 // eval:(verilog-read-includes)
9378 Note includes are only read when the file is first visited, you must use
9379 \\[find-alternate-file] RET to have these take effect after editing them!
9381 It is good to get in the habit of including all needed files in each .v
9382 file that needs it, rather than waiting for compile time. This will aid
9383 this process, Verilint, and readability. To prevent defining the same
9384 variable over and over when many modules are compiled together, put a test
9385 around the inside each include file:
9387 foo.v (an include file):
9388 \\=`ifdef _FOO_V // include if not already included
9391 ... contents of file
9392 \\=`endif // _FOO_V"
9393 ;;slow: (verilog-read-defines nil t)
9395 (verilog-getopt-flags)
9396 (goto-char (point-min))
9397 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
9398 (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string 1))))
9399 (verilog-read-defines inc nil t)))))
9401 (defun verilog-read-signals (&optional start end)
9402 "Return a simple list of all possible signals in the file.
9403 Bounded by optional region from START to END. Overly aggressive but fast.
9404 Some macros and such are also found and included. For dinotrace.el."
9405 (let (sigs-all keywd)
9406 (progn;save-excursion
9407 (goto-char (or start (point-min)))
9408 (setq end (or end (point-max)))
9409 (while (re-search-forward "[\"/a-zA-Z_.%`]" end t)
9413 (search-forward "\n"))
9414 ((looking-at "/\\*")
9415 (search-forward "*/"))
9416 ((looking-at "(\\*")
9417 (or (looking-at "(\\*\\s-*)") ; It's an "always @ (*)"
9418 (search-forward "*)")))
9419 ((eq ?\" (following-char))
9420 (re-search-forward "[^\\]\"")) ; don't forward-char first, since we look for a non backslash first
9421 ((looking-at "\\s-*\\([a-zA-Z0-9$_.%`]+\\)")
9422 (goto-char (match-end 0))
9423 (setq keywd (match-string-no-properties 1))
9424 (or (member keywd verilog-keywords)
9425 (member keywd sigs-all)
9426 (setq sigs-all (cons keywd sigs-all))))
9427 (t (forward-char 1))))
9432 ;; Argument file parsing
9435 (defun verilog-getopt (arglist)
9436 "Parse -f, -v etc arguments in ARGLIST list or string."
9437 (unless (listp arglist) (setq arglist (list arglist)))
9438 (let ((space-args '())
9440 ;; Split on spaces, so users can pass whole command lines
9442 (setq arg (car arglist)
9443 arglist (cdr arglist))
9444 (while (string-match "^\\([^ \t\n\f]+\\)[ \t\n\f]*\\(.*$\\)" arg)
9445 (setq space-args (append space-args
9446 (list (match-string-no-properties 1 arg))))
9447 (setq arg (match-string 2 arg))))
9450 (setq arg (car space-args)
9451 space-args (cdr space-args))
9455 (setq next-param arg))
9457 (setq next-param arg))
9459 (setq next-param arg))
9460 ;; +libext+(ext1)+(ext2)...
9461 ((string-match "^\\+libext\\+\\(.*\\)" arg)
9462 (setq arg (match-string 1 arg))
9463 (while (string-match "\\([^+]+\\)\\+?\\(.*\\)" arg)
9464 (verilog-add-list-unique `verilog-library-extensions
9465 (match-string 1 arg))
9466 (setq arg (match-string 2 arg))))
9468 ((or (string-match "^-D\\([^+=]*\\)[+=]\\(.*\\)" arg) ; -Ddefine=val
9469 (string-match "^-D\\([^+=]*\\)\\(\\)" arg) ; -Ddefine
9470 (string-match "^\\+define\\([^+=]*\\)[+=]\\(.*\\)" arg) ; +define+val
9471 (string-match "^\\+define\\([^+=]*\\)\\(\\)" arg)) ; +define+define
9472 (verilog-set-define (match-string 1 arg) (match-string 2 arg)))
9474 ((or (string-match "^\\+incdir\\+\\(.*\\)" arg) ; +incdir+dir
9475 (string-match "^-I\\(.*\\)" arg)) ; -Idir
9476 (verilog-add-list-unique `verilog-library-directories
9477 (match-string 1 (substitute-in-file-name arg))))
9479 ((equal "+librescan" arg))
9480 ((string-match "^-U\\(.*\\)" arg)) ; -Udefine
9481 ;; Second parameters
9482 ((equal next-param "-f")
9483 (setq next-param nil)
9484 (verilog-getopt-file (substitute-in-file-name arg)))
9485 ((equal next-param "-v")
9486 (setq next-param nil)
9487 (verilog-add-list-unique `verilog-library-files
9488 (substitute-in-file-name arg)))
9489 ((equal next-param "-y")
9490 (setq next-param nil)
9491 (verilog-add-list-unique `verilog-library-directories
9492 (substitute-in-file-name arg)))
9494 ((string-match "^[^-+]" arg)
9495 (verilog-add-list-unique `verilog-library-files
9496 (substitute-in-file-name arg)))
9497 ;; Default - ignore; no warning
9499 ;;(verilog-getopt (list "+libext+.a+.b" "+incdir+foodir" "+define+a+aval" "-f" "otherf" "-v" "library" "-y" "dir"))
9501 (defun verilog-getopt-file (filename)
9502 "Read Verilog options from the specified FILENAME."
9504 (let ((fns (verilog-library-filenames filename (buffer-file-name)))
9505 (orig-buffer (current-buffer))
9508 (set-buffer (find-file-noselect (car fns)))
9509 (error (concat (verilog-point-text)
9510 ": Can't find verilog-getopt-file -f file: " filename)))
9511 (goto-char (point-min))
9513 (setq line (buffer-substring (point) (point-at-eol)))
9515 (when (string-match "//" line)
9516 (setq line (substring line 0 (match-beginning 0))))
9517 (with-current-buffer orig-buffer ; Variables are buffer-local, so need right context.
9518 (verilog-getopt line))))))
9520 (defun verilog-getopt-flags ()
9521 "Convert `verilog-library-flags' into standard library variables."
9522 ;; If the flags are local, then all the outputs should be local also
9523 (when (local-variable-p `verilog-library-flags (current-buffer))
9524 (mapc 'make-local-variable '(verilog-library-extensions
9525 verilog-library-directories
9526 verilog-library-files
9527 verilog-library-flags)))
9528 ;; Allow user to customize
9529 (verilog-run-hooks 'verilog-before-getopt-flags-hook)
9530 ;; Process arguments
9531 (verilog-getopt verilog-library-flags)
9532 ;; Allow user to customize
9533 (verilog-run-hooks 'verilog-getopt-flags-hook))
9535 (defun verilog-add-list-unique (varref object)
9536 "Append to VARREF list the given OBJECT,
9537 unless it is already a member of the variable's list."
9538 (unless (member object (symbol-value varref))
9539 (set varref (append (symbol-value varref) (list object))))
9541 ;;(progn (setq l '()) (verilog-add-list-unique `l "a") (verilog-add-list-unique `l "a") l)
9543 (defun verilog-current-flags ()
9544 "Convert `verilog-library-flags' and similar variables to command line.
9545 Used for __FLAGS__ in `verilog-expand-command'."
9546 (let ((cmd (mapconcat `concat verilog-library-flags " ")))
9547 (when (equal cmd "")
9549 "+libext+" (mapconcat `concat verilog-library-extensions "+")
9550 (mapconcat (lambda (i) (concat " -y " i " +incdir+" i))
9551 verilog-library-directories "")
9552 (mapconcat (lambda (i) (concat " -v " i))
9553 verilog-library-files ""))))
9555 ;;(verilog-current-flags)
9558 ;;; Cached directory support:
9561 (defvar verilog-dir-cache-preserving nil
9562 "If true, the directory cache is enabled, and file system changes are ignored.
9563 See `verilog-dir-exists-p' and `verilog-dir-files'.")
9565 ;; If adding new cached variable, add also to verilog-preserve-dir-cache
9566 (defvar verilog-dir-cache-list nil
9567 "Alist of (((Cwd Dirname) Results)...) for caching `verilog-dir-files'.")
9568 (defvar verilog-dir-cache-lib-filenames nil
9569 "Cached data for `verilog-library-filenames'.")
9571 (defmacro verilog-preserve-dir-cache (&rest body)
9572 "Execute the BODY forms, allowing directory cache preservation within BODY.
9573 This means that changes inside BODY made to the file system will not be
9574 seen by the `verilog-dir-files' and related functions."
9575 `(let ((verilog-dir-cache-preserving (current-buffer))
9576 verilog-dir-cache-list
9577 verilog-dir-cache-lib-filenames)
9580 (defun verilog-dir-files (dirname)
9581 "Return all filenames in the DIRNAME directory.
9582 Relative paths depend on the `default-directory'.
9583 Results are cached if inside `verilog-preserve-dir-cache'."
9584 (unless verilog-dir-cache-preserving
9585 (setq verilog-dir-cache-list nil)) ; Cache disabled
9586 ;; We don't use expand-file-name on the dirname to make key, as it's slow
9587 (let* ((cache-key (list dirname default-directory))
9588 (fass (assoc cache-key verilog-dir-cache-list))
9590 (cond (fass ; Return data from cache hit
9593 (setq exp-dirname (expand-file-name dirname)
9594 data (and (file-directory-p exp-dirname)
9595 (directory-files exp-dirname nil nil nil)))
9596 ;; Note we also encache nil for non-existing dirs.
9597 (setq verilog-dir-cache-list (cons (list cache-key data)
9598 verilog-dir-cache-list))
9600 ;; Miss-and-hit test:
9601 ;;(verilog-preserve-dir-cache (prin1 (verilog-dir-files "."))
9602 ;; (prin1 (verilog-dir-files ".")) nil)
9604 (defun verilog-dir-file-exists-p (filename)
9605 "Return true if FILENAME exists.
9606 Like `file-exists-p' but results are cached if inside
9607 `verilog-preserve-dir-cache'."
9608 (let* ((dirname (file-name-directory filename))
9609 ;; Correct for file-name-nondirectory returning same if no slash.
9610 (dirnamed (if (or (not dirname) (equal dirname filename))
9611 default-directory dirname))
9612 (flist (verilog-dir-files dirnamed)))
9614 (member (file-name-nondirectory filename) flist)
9616 ;;(verilog-dir-file-exists-p "verilog-mode.el")
9617 ;;(verilog-dir-file-exists-p "../verilog-mode/verilog-mode.el")
9620 ;;; Module name lookup:
9623 (defun verilog-module-inside-filename-p (module filename)
9624 "Return modi if MODULE is specified inside FILENAME, else nil.
9625 Allows version control to check out the file if need be."
9626 (and (or (file-exists-p filename)
9627 (and (fboundp 'vc-backend)
9628 (vc-backend filename)))
9630 (with-current-buffer (find-file-noselect filename)
9632 (goto-char (point-min))
9634 ;; It may be tempting to look for verilog-defun-re,
9635 ;; don't, it slows things down a lot!
9636 (verilog-re-search-forward-quick "\\<\\(module\\|interface\\|program\\)\\>" nil t)
9637 (setq type (match-string-no-properties 0))
9638 (verilog-re-search-forward-quick "[(;]" nil t))
9639 (if (equal module (verilog-read-module-name))
9640 (setq modi (verilog-modi-new module filename (point) type))))
9643 (defun verilog-is-number (symbol)
9644 "Return true if SYMBOL is number-like."
9645 (or (string-match "^[0-9 \t:]+$" symbol)
9646 (string-match "^[---]*[0-9]+$" symbol)
9647 (string-match "^[0-9 \t]+'s?[hdxbo][0-9a-fA-F_xz? \t]*$" symbol)))
9649 (defun verilog-symbol-detick (symbol wing-it)
9650 "Return an expanded SYMBOL name without any defines.
9651 If the variable vh-{symbol} is defined, return that value.
9652 If undefined, and WING-IT, return just SYMBOL without the tick, else nil."
9653 (while (and symbol (string-match "^`" symbol))
9654 (setq symbol (substring symbol 1))
9656 ;; Namespace intentionally short for AUTOs and compatibility
9657 (if (boundp (intern (concat "vh-" symbol)))
9658 ;; Emacs has a bug where boundp on a buffer-local
9659 ;; variable in only one buffer returns t in another.
9660 ;; This can confuse, so check for nil.
9661 ;; Namespace intentionally short for AUTOs and compatibility
9662 (let ((val (eval (intern (concat "vh-" symbol)))))
9664 (if wing-it symbol nil)
9666 (if wing-it symbol nil))))
9668 ;;(verilog-symbol-detick "`mod" nil)
9670 (defun verilog-symbol-detick-denumber (symbol)
9671 "Return SYMBOL with defines converted and any numbers dropped to nil."
9672 (when (string-match "^`" symbol)
9673 ;; This only will work if the define is a simple signal, not
9674 ;; something like a[b]. Sorry, it should be substituted into the parser
9676 (verilog-string-replace-matches
9677 "\[[^0-9: \t]+\]" "" nil nil
9678 (or (verilog-symbol-detick symbol nil)
9679 (if verilog-auto-sense-defines-constant
9682 (if (verilog-is-number symbol)
9686 (defun verilog-symbol-detick-text (text)
9687 "Return TEXT without any known defines.
9688 If the variable vh-{symbol} is defined, substitute that value."
9689 (let ((ok t) symbol val)
9690 (while (and ok (string-match "`\\([a-zA-Z0-9_]+\\)" text))
9691 (setq symbol (match-string 1 text))
9694 ;; Namespace intentionally short for AUTOs and compatibility
9695 (boundp (intern (concat "vh-" symbol)))
9696 ;; Emacs has a bug where boundp on a buffer-local
9697 ;; variable in only one buffer returns t in another.
9698 ;; This can confuse, so check for nil.
9699 ;; Namespace intentionally short for AUTOs and compatibility
9700 (setq val (eval (intern (concat "vh-" symbol)))))
9701 (setq text (replace-match val nil nil text)))
9702 (t (setq ok nil)))))
9704 ;;(progn (setq vh-mod "`foo" vh-foo "bar") (verilog-symbol-detick-text "bar `mod `undefed"))
9706 (defun verilog-expand-dirnames (&optional dirnames)
9707 "Return a list of existing directories given a list of wildcarded DIRNAMES.
9708 Or, just the existing dirnames themselves if there are no wildcards."
9709 ;; Note this function is performance critical.
9710 ;; Do not call anything that requires disk access that cannot be cached.
9712 (unless dirnames (error "`verilog-library-directories' should include at least '.'"))
9713 (setq dirnames (reverse dirnames)) ; not nreverse
9715 pattern dirfile dirfiles dirname root filename rest basefile)
9717 (setq dirname (substitute-in-file-name (car dirnames))
9718 dirnames (cdr dirnames))
9719 (cond ((string-match (concat "^\\(\\|[/\\]*[^*?]*[/\\]\\)" ; root
9720 "\\([^/\\]*[*?][^/\\]*\\)" ; filename with *?
9723 (setq root (match-string 1 dirname)
9724 filename (match-string 2 dirname)
9725 rest (match-string 3 dirname)
9727 ;; now replace those * and ? with .+ and .
9728 ;; use ^ and /> to get only whole file names
9729 (setq pattern (verilog-string-replace-matches "[*]" ".+" nil nil pattern)
9730 pattern (verilog-string-replace-matches "[?]" "." nil nil pattern)
9731 pattern (concat "^" pattern "$")
9732 dirfiles (verilog-dir-files root))
9734 (setq basefile (car dirfiles)
9735 dirfile (expand-file-name (concat root basefile rest))
9736 dirfiles (cdr dirfiles))
9737 (if (and (string-match pattern basefile)
9738 ;; Don't allow abc/*/rtl to match abc/rtl via ..
9739 (not (equal basefile "."))
9740 (not (equal basefile ".."))
9741 (file-directory-p dirfile))
9742 (setq dirlist (cons dirfile dirlist)))))
9745 (if (file-directory-p dirname)
9746 (setq dirlist (cons dirname dirlist))))))
9748 ;;(verilog-expand-dirnames (list "." ".." "nonexist" "../*" "/home/wsnyder/*/v"))
9750 (defun verilog-library-filenames (filename &optional current check-ext)
9751 "Return a search path to find the given FILENAME or module name.
9752 Uses the optional CURRENT filename or variable `buffer-file-name', plus
9753 `verilog-library-directories' and `verilog-library-extensions'
9754 variables to build the path. With optional CHECK-EXT also check
9755 `verilog-library-extensions'."
9756 (unless current (setq current (buffer-file-name)))
9757 (unless verilog-dir-cache-preserving
9758 (setq verilog-dir-cache-lib-filenames nil))
9759 (let* ((cache-key (list filename current check-ext))
9760 (fass (assoc cache-key verilog-dir-cache-lib-filenames))
9761 chkdirs chkdir chkexts fn outlist)
9762 (cond (fass ; Return data from cache hit
9765 ;; Note this expand can't be easily cached, as we need to
9766 ;; pick up buffer-local variables for newly read sub-module files
9767 (setq chkdirs (verilog-expand-dirnames verilog-library-directories))
9769 (setq chkdir (expand-file-name (car chkdirs)
9770 (file-name-directory current))
9771 chkexts (if check-ext verilog-library-extensions `("")))
9773 (setq fn (expand-file-name (concat filename (car chkexts))
9775 ;;(message "Check for %s" fn)
9776 (if (verilog-dir-file-exists-p fn)
9777 (setq outlist (cons (expand-file-name
9778 fn (file-name-directory current))
9780 (setq chkexts (cdr chkexts)))
9781 (setq chkdirs (cdr chkdirs)))
9782 (setq outlist (nreverse outlist))
9783 (setq verilog-dir-cache-lib-filenames
9784 (cons (list cache-key outlist)
9785 verilog-dir-cache-lib-filenames))
9788 (defun verilog-module-filenames (module current)
9789 "Return a search path to find the given MODULE name.
9790 Uses the CURRENT filename, `verilog-library-extensions',
9791 `verilog-library-directories' and `verilog-library-files'
9792 variables to build the path."
9793 ;; Return search locations for it
9794 (append (list current) ; first, current buffer
9795 (verilog-library-filenames module current t)
9796 verilog-library-files)) ; finally, any libraries
9799 ;; Module Information
9801 ;; Many of these functions work on "modi" a module information structure
9802 ;; A modi is: [module-name-string file-name begin-point]
9804 (defvar verilog-cache-enabled t
9805 "Non-nil enables caching of signals, etc. Set to nil for debugging to make things SLOW!")
9807 (defvar verilog-modi-cache-list nil
9808 "Cache of ((Module Function) Buf-Tick Buf-Modtime Func-Returns)...
9809 For speeding up verilog-modi-get-* commands.
9811 (make-variable-buffer-local 'verilog-modi-cache-list)
9813 (defvar verilog-modi-cache-preserve-tick nil
9814 "Modification tick after which the cache is still considered valid.
9815 Use `verilog-preserve-modi-cache' to set it.")
9816 (defvar verilog-modi-cache-preserve-buffer nil
9817 "Modification tick after which the cache is still considered valid.
9818 Use `verilog-preserve-modi-cache' to set it.")
9819 (defvar verilog-modi-cache-current-enable nil
9820 "Non-nil means allow caching `verilog-modi-current', set by let().")
9821 (defvar verilog-modi-cache-current nil
9822 "Currently active `verilog-modi-current', if any, set by let().")
9823 (defvar verilog-modi-cache-current-max nil
9824 "Current endmodule point for `verilog-modi-cache-current', if any.")
9826 (defun verilog-modi-current ()
9827 "Return the modi structure for the module currently at point, possibly cached."
9828 (cond ((and verilog-modi-cache-current
9829 (>= (point) (verilog-modi-get-point verilog-modi-cache-current))
9830 (<= (point) verilog-modi-cache-current-max))
9831 ;; Slow assertion, for debugging the cache:
9832 ;;(or (equal verilog-modi-cache-current (verilog-modi-current-get)) (debug))
9833 verilog-modi-cache-current)
9834 (verilog-modi-cache-current-enable
9835 (setq verilog-modi-cache-current (verilog-modi-current-get)
9836 verilog-modi-cache-current-max
9837 ;; The cache expires when we pass "endmodule" as then the
9838 ;; current modi may change to the next module
9839 ;; This relies on the AUTOs generally inserting, not deleting text
9841 (verilog-re-search-forward-quick verilog-end-defun-re nil nil)))
9842 verilog-modi-cache-current)
9844 (verilog-modi-current-get))))
9846 (defun verilog-modi-current-get ()
9847 "Return the modi structure for the module currently at point."
9848 (let* (name type pt)
9849 ;; read current module's name
9851 (verilog-re-search-backward-quick verilog-defun-re nil nil)
9852 (setq type (match-string-no-properties 0))
9853 (verilog-re-search-forward-quick "(" nil nil)
9854 (setq name (verilog-read-module-name))
9856 ;; return modi - note this vector built two places
9857 (verilog-modi-new name (or (buffer-file-name) (current-buffer)) pt type)))
9859 (defvar verilog-modi-lookup-cache nil "Hash of (modulename modi).")
9860 (make-variable-buffer-local 'verilog-modi-lookup-cache)
9861 (defvar verilog-modi-lookup-last-current nil "Cache of `current-buffer' at last lookup.")
9862 (defvar verilog-modi-lookup-last-tick nil "Cache of `buffer-chars-modified-tick' at last lookup.")
9864 (defun verilog-modi-lookup (module allow-cache &optional ignore-error)
9865 "Find the file and point at which MODULE is defined.
9866 If ALLOW-CACHE is set, check and remember cache of previous lookups.
9867 Return modi if successful, else print message unless IGNORE-ERROR is true."
9868 (let* ((current (or (buffer-file-name) (current-buffer)))
9871 ;;(message "verilog-modi-lookup: %s" module)
9872 (cond ((and verilog-modi-lookup-cache
9873 verilog-cache-enabled
9875 (setq modi (gethash module verilog-modi-lookup-cache))
9876 (equal verilog-modi-lookup-last-current current)
9877 ;; If hit is in current buffer, then tick must match
9878 (or (equal verilog-modi-lookup-last-tick (buffer-chars-modified-tick))
9879 (not (equal current (verilog-modi-file-or-buffer modi)))))
9880 ;;(message "verilog-modi-lookup: HIT %S" modi)
9883 (t (let* ((realname (verilog-symbol-detick module t))
9884 (orig-filenames (verilog-module-filenames realname current))
9885 (filenames orig-filenames)
9887 (while (and filenames (not mif))
9888 (if (not (setq mif (verilog-module-inside-filename-p realname (car filenames))))
9889 (setq filenames (cdr filenames))))
9890 ;; mif has correct form to become later elements of modi
9891 (cond (mif (setq modi mif))
9894 (error (concat (verilog-point-text)
9895 ": Can't locate " module " module definition"
9896 (if (not (equal module realname))
9897 (concat " (Expanded macro to " realname ")")
9899 "\n Check the verilog-library-directories variable."
9900 "\n I looked in (if not listed, doesn't exist):\n\t"
9901 (mapconcat 'concat orig-filenames "\n\t"))))))
9902 (when (eval-when-compile (fboundp 'make-hash-table))
9903 (unless verilog-modi-lookup-cache
9904 (setq verilog-modi-lookup-cache
9905 (make-hash-table :test 'equal :rehash-size 4.0)))
9906 (puthash module modi verilog-modi-lookup-cache))
9907 (setq verilog-modi-lookup-last-current current
9908 verilog-modi-lookup-last-tick (buffer-chars-modified-tick)))))
9911 (defun verilog-modi-filename (modi)
9912 "Filename of MODI, or name of buffer if it's never been saved."
9913 (if (bufferp (verilog-modi-file-or-buffer modi))
9914 (or (buffer-file-name (verilog-modi-file-or-buffer modi))
9915 (buffer-name (verilog-modi-file-or-buffer modi)))
9916 (verilog-modi-file-or-buffer modi)))
9918 (defun verilog-modi-goto (modi)
9919 "Move point/buffer to specified MODI."
9920 (or modi (error "Passed unfound modi to goto, check earlier"))
9921 (set-buffer (if (bufferp (verilog-modi-file-or-buffer modi))
9922 (verilog-modi-file-or-buffer modi)
9923 (find-file-noselect (verilog-modi-file-or-buffer modi))))
9924 (or (equal major-mode `verilog-mode) ; Put into Verilog mode to get syntax
9926 (goto-char (verilog-modi-get-point modi)))
9928 (defun verilog-goto-defun-file (module)
9929 "Move point to the file at which a given MODULE is defined."
9930 (interactive "sGoto File for Module: ")
9931 (let* ((modi (verilog-modi-lookup module nil)))
9933 (verilog-modi-goto modi)
9934 (switch-to-buffer (current-buffer)))))
9936 (defun verilog-modi-cache-results (modi function)
9937 "Run on MODI the given FUNCTION. Locate the module in a file.
9938 Cache the output of function so next call may have faster access."
9940 (save-excursion ; Cache is buffer-local so can't avoid this.
9941 (verilog-modi-goto modi)
9942 (if (and (setq fass (assoc (list modi function)
9943 verilog-modi-cache-list))
9944 ;; Destroy caching when incorrect; Modified or file changed
9945 (not (and verilog-cache-enabled
9946 (or (equal (buffer-chars-modified-tick) (nth 1 fass))
9947 (and verilog-modi-cache-preserve-tick
9948 (<= verilog-modi-cache-preserve-tick (nth 1 fass))
9949 (equal verilog-modi-cache-preserve-buffer (current-buffer))))
9950 (equal (visited-file-modtime) (nth 2 fass)))))
9951 (setq verilog-modi-cache-list nil
9954 ;; Return data from cache hit
9958 ;; Clear then restore any highlighting to make emacs19 happy
9960 (verilog-save-font-mods
9961 (setq func-returns (funcall function)))
9962 ;; Cache for next time
9963 (setq verilog-modi-cache-list
9964 (cons (list (list modi function)
9965 (buffer-chars-modified-tick)
9966 (visited-file-modtime)
9968 verilog-modi-cache-list))
9971 (defun verilog-modi-cache-add (modi function element sig-list)
9972 "Add function return results to the module cache.
9973 Update MODI's cache for given FUNCTION so that the return ELEMENT of that
9974 function now contains the additional SIG-LIST parameters."
9977 (verilog-modi-goto modi)
9978 (if (setq fass (assoc (list modi function)
9979 verilog-modi-cache-list))
9980 (let ((func-returns (nth 3 fass)))
9981 (aset func-returns element
9982 (append sig-list (aref func-returns element))))))))
9984 (defmacro verilog-preserve-modi-cache (&rest body)
9985 "Execute the BODY forms, allowing cache preservation within BODY.
9986 This means that changes to the buffer will not result in the cache being
9987 flushed. If the changes affect the modsig state, they must call the
9988 modsig-cache-add-* function, else the results of later calls may be
9989 incorrect. Without this, changes are assumed to be adding/removing signals
9990 and invalidating the cache."
9991 `(let ((verilog-modi-cache-preserve-tick (buffer-chars-modified-tick))
9992 (verilog-modi-cache-preserve-buffer (current-buffer)))
9996 (defun verilog-modi-modport-lookup-one (modi name &optional ignore-error)
9997 "Given a MODI, return the declarations related to the given modport NAME."
9998 ;; Recursive routine - see below
9999 (let* ((realname (verilog-symbol-detick name t))
10000 (modport (assoc name (verilog-decls-get-modports (verilog-modi-get-decls modi)))))
10001 (or modport ignore-error
10002 (error (concat (verilog-point-text)
10003 ": Can't locate " name " modport definition"
10004 (if (not (equal name realname))
10005 (concat " (Expanded macro to " realname ")")
10007 (let* ((decls (verilog-modport-decls modport))
10008 (clks (verilog-modport-clockings modport)))
10009 ;; Now expand any clocking's
10011 (setq decls (verilog-decls-append
10013 (verilog-modi-modport-lookup-one modi (car clks) ignore-error)))
10014 (setq clks (cdr clks)))
10017 (defun verilog-modi-modport-lookup (modi name-re &optional ignore-error)
10018 "Given a MODI, return the declarations related to the given modport NAME-RE.
10019 If the modport points to any clocking blocks, expand the signals to include
10020 those clocking block's signals."
10021 ;; Recursive routine - see below
10022 (let* ((mod-decls (verilog-modi-get-decls modi))
10023 (clks (verilog-decls-get-modports mod-decls))
10024 (name-re (concat "^" name-re "$"))
10025 (decls (verilog-decls-new nil nil nil nil nil nil nil nil nil)))
10026 ;; Pull in all modports
10028 (when (string-match name-re (verilog-modport-name (car clks)))
10029 (setq decls (verilog-decls-append
10031 (verilog-modi-modport-lookup-one modi (verilog-modport-name (car clks)) ignore-error))))
10032 (setq clks (cdr clks)))
10035 (defun verilog-signals-matching-enum (in-list enum)
10036 "Return all signals in IN-LIST matching the given ENUM."
10039 (if (equal (verilog-sig-enum (car in-list)) enum)
10040 (setq out-list (cons (car in-list) out-list)))
10041 (setq in-list (cdr in-list)))
10043 ;; Namespace intentionally short for AUTOs and compatibility
10044 (let* ((enumvar (intern (concat "venum-" enum)))
10045 (enumlist (and (boundp enumvar) (eval enumvar))))
10047 (add-to-list 'out-list (list (car enumlist)))
10048 (setq enumlist (cdr enumlist))))
10049 (nreverse out-list)))
10051 (defun verilog-signals-matching-regexp (in-list regexp)
10052 "Return all signals in IN-LIST matching the given REGEXP, if non-nil."
10053 (if (or (not regexp) (equal regexp ""))
10055 (let ((case-fold-search verilog-case-fold)
10058 (if (string-match regexp (verilog-sig-name (car in-list)))
10059 (setq out-list (cons (car in-list) out-list)))
10060 (setq in-list (cdr in-list)))
10061 (nreverse out-list))))
10063 (defun verilog-signals-not-matching-regexp (in-list regexp)
10064 "Return all signals in IN-LIST not matching the given REGEXP, if non-nil."
10065 (if (or (not regexp) (equal regexp ""))
10067 (let ((case-fold-search verilog-case-fold)
10070 (if (not (string-match regexp (verilog-sig-name (car in-list))))
10071 (setq out-list (cons (car in-list) out-list)))
10072 (setq in-list (cdr in-list)))
10073 (nreverse out-list))))
10075 (defun verilog-signals-matching-dir-re (in-list decl-type regexp)
10076 "Return all signals in IN-LIST matching the given DECL-TYPE and REGEXP,
10078 (if (or (not regexp) (equal regexp ""))
10080 (let (out-list to-match)
10082 ;; Note verilog-insert-one-definition matches on this order
10083 (setq to-match (concat
10085 " " (verilog-sig-signed (car in-list))
10086 " " (verilog-sig-multidim (car in-list))
10087 (verilog-sig-bits (car in-list))))
10088 (if (string-match regexp to-match)
10089 (setq out-list (cons (car in-list) out-list)))
10090 (setq in-list (cdr in-list)))
10091 (nreverse out-list))))
10093 (defun verilog-signals-edit-wire-reg (in-list)
10094 "Return all signals in IN-LIST with wire/reg data types made blank."
10095 (mapcar (lambda (sig)
10096 (when (member (verilog-sig-type sig) '("wire" "reg"))
10097 (verilog-sig-type-set sig nil))
10101 (defun verilog-decls-get-signals (decls)
10102 "Return all declared signals in DECLS, excluding 'assign' statements."
10104 (verilog-decls-get-outputs decls)
10105 (verilog-decls-get-inouts decls)
10106 (verilog-decls-get-inputs decls)
10107 (verilog-decls-get-vars decls)
10108 (verilog-decls-get-consts decls)
10109 (verilog-decls-get-gparams decls)))
10111 (defun verilog-decls-get-ports (decls)
10113 (verilog-decls-get-outputs decls)
10114 (verilog-decls-get-inouts decls)
10115 (verilog-decls-get-inputs decls)))
10117 (defun verilog-decls-get-iovars (decls)
10119 (verilog-decls-get-vars decls)
10120 (verilog-decls-get-outputs decls)
10121 (verilog-decls-get-inouts decls)
10122 (verilog-decls-get-inputs decls)))
10124 (defsubst verilog-modi-cache-add-outputs (modi sig-list)
10125 (verilog-modi-cache-add modi 'verilog-read-decls 0 sig-list))
10126 (defsubst verilog-modi-cache-add-inouts (modi sig-list)
10127 (verilog-modi-cache-add modi 'verilog-read-decls 1 sig-list))
10128 (defsubst verilog-modi-cache-add-inputs (modi sig-list)
10129 (verilog-modi-cache-add modi 'verilog-read-decls 2 sig-list))
10130 (defsubst verilog-modi-cache-add-vars (modi sig-list)
10131 (verilog-modi-cache-add modi 'verilog-read-decls 3 sig-list))
10132 (defsubst verilog-modi-cache-add-gparams (modi sig-list)
10133 (verilog-modi-cache-add modi 'verilog-read-decls 7 sig-list))
10136 ;;; Auto creation utilities:
10139 (defun verilog-auto-re-search-do (search-for func)
10140 "Search for the given auto text regexp SEARCH-FOR, and perform FUNC where it occurs."
10141 (goto-char (point-min))
10142 (while (verilog-re-search-forward-quick search-for nil t)
10145 (defun verilog-insert-one-definition (sig type indent-pt)
10146 "Print out a definition for SIG of the given TYPE,
10147 with appropriate INDENT-PT indentation."
10148 (indent-to indent-pt)
10149 ;; Note verilog-signals-matching-dir-re matches on this order
10151 (when (verilog-sig-modport sig)
10152 (insert "." (verilog-sig-modport sig)))
10153 (when (verilog-sig-signed sig)
10154 (insert " " (verilog-sig-signed sig)))
10155 (when (verilog-sig-multidim sig)
10156 (insert " " (verilog-sig-multidim-string sig)))
10157 (when (verilog-sig-bits sig)
10158 (insert " " (verilog-sig-bits sig)))
10159 (indent-to (max 24 (+ indent-pt 16)))
10160 (unless (= (char-syntax (preceding-char)) ?\ )
10161 (insert " ")) ; Need space between "]name" if indent-to did nothing
10162 (insert (verilog-sig-name sig))
10163 (when (verilog-sig-memory sig)
10164 (insert " " (verilog-sig-memory sig))))
10166 (defun verilog-insert-definition (modi sigs direction indent-pt v2k &optional dont-sort)
10167 "Print out a definition for MODI's list of SIGS of the given DIRECTION,
10168 with appropriate INDENT-PT indentation. If V2K, use Verilog 2001 I/O
10169 format. Sort unless DONT-SORT. DIRECTION is normally wire/reg/output.
10170 When MODI is non-null, also add to modi-cache, for tracking."
10172 (cond ((equal direction "wire")
10173 (verilog-modi-cache-add-vars modi sigs))
10174 ((equal direction "reg")
10175 (verilog-modi-cache-add-vars modi sigs))
10176 ((equal direction "output")
10177 (verilog-modi-cache-add-outputs modi sigs)
10178 (when verilog-auto-declare-nettype
10179 (verilog-modi-cache-add-vars modi sigs)))
10180 ((equal direction "input")
10181 (verilog-modi-cache-add-inputs modi sigs)
10182 (when verilog-auto-declare-nettype
10183 (verilog-modi-cache-add-vars modi sigs)))
10184 ((equal direction "inout")
10185 (verilog-modi-cache-add-inouts modi sigs)
10186 (when verilog-auto-declare-nettype
10187 (verilog-modi-cache-add-vars modi sigs)))
10188 ((equal direction "interface"))
10189 ((equal direction "parameter")
10190 (verilog-modi-cache-add-gparams modi sigs))
10192 (error "Unsupported verilog-insert-definition direction: %s" direction))))
10194 (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
10196 (let ((sig (car sigs)))
10197 (verilog-insert-one-definition
10199 ;; Want "type x" or "output type x", not "wire type x"
10200 (cond ((or (verilog-sig-type sig)
10201 verilog-auto-wire-type)
10203 (when (member direction '("input" "output" "inout"))
10204 (concat direction " "))
10205 (or (verilog-sig-type sig)
10206 verilog-auto-wire-type)))
10207 ((and verilog-auto-declare-nettype
10208 (member direction '("input" "output" "inout")))
10209 (concat direction " " verilog-auto-declare-nettype))
10213 (insert (if v2k "," ";"))
10214 (if (or (not (verilog-sig-comment sig))
10215 (equal "" (verilog-sig-comment sig)))
10217 (indent-to (max 48 (+ indent-pt 40)))
10218 (verilog-insert "// " (verilog-sig-comment sig) "\n"))
10219 (setq sigs (cdr sigs)))))
10222 (if (not (boundp 'indent-pt))
10223 (defvar indent-pt nil "Local used by insert-indent")))
10225 (defun verilog-insert-indent (&rest stuff)
10226 "Indent to position stored in local `indent-pt' variable, then insert STUFF.
10227 Presumes that any newlines end a list element."
10228 (let ((need-indent t))
10230 (if need-indent (indent-to indent-pt))
10231 (setq need-indent nil)
10232 (verilog-insert (car stuff))
10233 (setq need-indent (string-match "\n$" (car stuff))
10234 stuff (cdr stuff)))))
10235 ;;(let ((indent-pt 10)) (verilog-insert-indent "hello\n" "addon" "there\n"))
10237 (defun verilog-forward-or-insert-line ()
10238 "Move forward a line, unless at EOB, then insert a newline."
10239 (if (eobp) (insert "\n")
10242 (defun verilog-repair-open-comma ()
10243 "Insert comma if previous argument is other than an open parenthesis or endif."
10244 ;; We can't just search backward for ) as it might be inside another expression.
10245 ;; Also want "`ifdef X input foo `endif" to just leave things to the human to deal with
10247 (verilog-backward-syntactic-ws-quick)
10248 (when (and (not (save-excursion ; Not beginning (, or existing ,
10250 (looking-at "[(,]")))
10251 (not (save-excursion ; Not `endif, or user define
10253 (skip-chars-backward "[a-zA-Z0-9_`]")
10254 (looking-at "`"))))
10257 (defun verilog-repair-close-comma ()
10258 "If point is at a comma followed by a close parenthesis, fix it.
10259 This repairs those mis-inserted by an AUTOARG."
10260 ;; It would be much nicer if Verilog allowed extra commas like Perl does!
10262 (verilog-forward-close-paren)
10264 (verilog-backward-syntactic-ws-quick)
10266 (when (looking-at ",")
10269 (defun verilog-make-width-expression (range-exp)
10270 "Return an expression calculating the length of a range [x:y] in RANGE-EXP."
10271 ;; strip off the []
10272 (cond ((not range-exp)
10275 (if (string-match "^\\[\\(.*\\)\\]$" range-exp)
10276 (setq range-exp (match-string 1 range-exp)))
10277 (cond ((not range-exp)
10279 ;; [#:#] We can compute a numeric result
10280 ((string-match "^\\s *\\([0-9]+\\)\\s *:\\s *\\([0-9]+\\)\\s *$"
10283 (1+ (abs (- (string-to-number (match-string 1 range-exp))
10284 (string-to-number (match-string 2 range-exp)))))))
10285 ;; [PARAM-1:0] can just return PARAM
10286 ((string-match "^\\s *\\([a-zA-Z_][a-zA-Z0-9_]*\\)\\s *-\\s *1\\s *:\\s *0\\s *$" range-exp)
10287 (match-string 1 range-exp))
10288 ;; [arbitrary] need math
10289 ((string-match "^\\(.*\\)\\s *:\\s *\\(.*\\)\\s *$" range-exp)
10290 (concat "(1+(" (match-string 1 range-exp) ")"
10291 (if (equal "0" (match-string 2 range-exp))
10292 "" ; Don't bother with -(0)
10293 (concat "-(" (match-string 2 range-exp) ")"))
10296 ;;(verilog-make-width-expression "`A:`B")
10298 (defun verilog-simplify-range-expression (expr)
10299 "Return a simplified range expression with constants eliminated from EXPR."
10300 ;; Note this is always called with brackets; ie [z] or [z:z]
10301 (if (not (string-match "[---+*()]" expr))
10302 expr ; short-circuit
10305 (while (not (equal last-pass out))
10306 (setq last-pass out)
10307 ;; Prefix regexp needs beginning of match, or some symbol of
10308 ;; lesser or equal precedence. We assume the [:]'s exist in expr.
10310 (while (string-match
10311 (concat "\\([[({:*+-]\\)" ; - must be last
10312 "(\\<\\([0-9A-Za-z_]+\\))"
10315 (setq out (replace-match "\\1\\2\\3" nil nil out)))
10316 (while (string-match
10317 (concat "\\([[({:*+-]\\)" ; - must be last
10318 "\\$clog2\\s *(\\<\\([0-9]+\\))"
10321 (setq out (replace-match
10323 (match-string 1 out)
10324 (int-to-string (verilog-clog2 (string-to-number (match-string 2 out))))
10325 (match-string 3 out))
10327 ;; For precedence do * before +/-
10328 (while (string-match
10329 (concat "\\([[({:*+-]\\)"
10330 "\\([0-9]+\\)\\s *\\([*]\\)\\s *\\([0-9]+\\)"
10333 (setq out (replace-match
10334 (concat (match-string 1 out)
10335 (int-to-string (* (string-to-number (match-string 2 out))
10336 (string-to-number (match-string 4 out))))
10337 (match-string 5 out))
10339 (while (string-match
10340 (concat "\\([[({:+-]\\)" ; No * here as higher prec
10341 "\\([0-9]+\\)\\s *\\([---+]\\)\\s *\\([0-9]+\\)"
10344 (let ((pre (match-string 1 out))
10345 (lhs (string-to-number (match-string 2 out)))
10346 (rhs (string-to-number (match-string 4 out)))
10347 (post (match-string 5 out))
10349 (when (equal pre "-")
10350 (setq lhs (- lhs)))
10351 (setq val (if (equal (match-string 3 out) "-")
10355 (concat (if (and (equal pre "-")
10357 "" ; Not "--20" but just "-20"
10359 (int-to-string val)
10364 ;;(verilog-simplify-range-expression "[1:3]") ; 1
10365 ;;(verilog-simplify-range-expression "[(1):3]") ; 1
10366 ;;(verilog-simplify-range-expression "[(((16)+1)+1+(1+1))]") ; 20
10367 ;;(verilog-simplify-range-expression "[(2*3+6*7)]") ; 48
10368 ;;(verilog-simplify-range-expression "[(FOO*4-1*2)]") ; FOO*4-2
10369 ;;(verilog-simplify-range-expression "[(FOO*4+1-1)]") ; FOO*4+0
10370 ;;(verilog-simplify-range-expression "[(func(BAR))]") ; func(BAR)
10371 ;;(verilog-simplify-range-expression "[FOO-1+1-1+1]") ; FOO-0
10372 ;;(verilog-simplify-range-expression "[$clog2(2)]") ; 1
10373 ;;(verilog-simplify-range-expression "[$clog2(7)]") ; 3
10375 (defun verilog-clog2 (value)
10376 "Compute $clog2 - ceiling log2 of VALUE."
10379 (ceiling (/ (log value) (log 2)))))
10381 (defun verilog-typedef-name-p (variable-name)
10382 "Return true if the VARIABLE-NAME is a type definition."
10383 (when verilog-typedef-regexp
10384 (verilog-string-match-fold verilog-typedef-regexp variable-name)))
10389 (defun verilog-delete-autos-lined ()
10390 "Delete autos that occupy multiple lines, between begin and end comments."
10391 ;; The newline must not have a comment property, so we must
10392 ;; delete the end auto's newline, not the first newline
10394 (let ((pt (point)))
10396 (looking-at "\\s-*// Beginning")
10397 (search-forward "// End of automatic" nil t))
10401 (delete-region pt (point)))))
10403 (defun verilog-delete-empty-auto-pair ()
10404 "Delete begin/end auto pair at point, if empty."
10406 (when (looking-at (concat "\\s-*// Beginning of automatic.*\n"
10407 "\\s-*// End of automatics\n"))
10408 (delete-region (point) (save-excursion (forward-line 2) (point)))))
10410 (defun verilog-forward-close-paren ()
10411 "Find the close parenthesis that match the current point.
10412 Ignore other close parenthesis with matching open parens."
10414 (while (> parens 0)
10415 (unless (verilog-re-search-forward-quick "[()]" nil t)
10416 (error "%s: Mismatching ()" (verilog-point-text)))
10417 (cond ((= (preceding-char) ?\( )
10418 (setq parens (1+ parens)))
10419 ((= (preceding-char) ?\) )
10420 (setq parens (1- parens)))))))
10422 (defun verilog-backward-open-paren ()
10423 "Find the open parenthesis that match the current point.
10424 Ignore other open parenthesis with matching close parens."
10426 (while (> parens 0)
10427 (unless (verilog-re-search-backward-quick "[()]" nil t)
10428 (error "%s: Mismatching ()" (verilog-point-text)))
10429 (cond ((= (following-char) ?\) )
10430 (setq parens (1+ parens)))
10431 ((= (following-char) ?\( )
10432 (setq parens (1- parens)))))))
10434 (defun verilog-backward-open-bracket ()
10435 "Find the open bracket that match the current point.
10436 Ignore other open bracket with matching close bracket."
10438 (while (> parens 0)
10439 (unless (verilog-re-search-backward-quick "[][]" nil t)
10440 (error "%s: Mismatching []" (verilog-point-text)))
10441 (cond ((= (following-char) ?\] )
10442 (setq parens (1+ parens)))
10443 ((= (following-char) ?\[ )
10444 (setq parens (1- parens)))))))
10446 (defun verilog-delete-to-paren ()
10447 "Delete the automatic inst/sense/arg created by autos.
10448 Deletion stops at the matching end parenthesis, outside comments."
10449 (delete-region (point)
10451 (verilog-backward-open-paren)
10452 (verilog-forward-sexp-ign-cmt 1) ; Moves to paren that closes argdecl's
10456 (defun verilog-auto-star-safe ()
10457 "Return if a .* AUTOINST is safe to delete or expand.
10458 It was created by the AUTOS themselves, or by the user."
10459 (and verilog-auto-star-expand
10461 (concat "[ \t\n\f,]*\\([)]\\|// " verilog-inst-comment-re "\\)"))))
10463 (defun verilog-delete-auto-star-all ()
10464 "Delete a .* AUTOINST, if it is safe."
10465 (when (verilog-auto-star-safe)
10466 (verilog-delete-to-paren)))
10468 (defun verilog-delete-auto-star-implicit ()
10469 "Delete all .* implicit connections created by `verilog-auto-star'.
10470 This function will be called automatically at save unless
10471 `verilog-auto-star-save' is set, any non-templated expanded pins will be
10474 (let (paren-pt indent have-close-paren)
10476 (goto-char (point-min))
10477 ;; We need to match these even outside of comments.
10478 ;; For reasonable performance, we don't check if inside comments, sorry.
10479 (while (re-search-forward "// Implicit \\.\\*" nil t)
10480 (setq paren-pt (point))
10481 (beginning-of-line)
10482 (setq have-close-paren
10484 (when (search-forward ");" paren-pt t)
10485 (setq indent (current-indentation))
10487 (delete-region (point) (+ 1 paren-pt)) ; Nuke line incl CR
10488 (when have-close-paren
10489 ;; Delete extra commentary
10493 (looking-at (concat "\\s *//\\s *" verilog-inst-comment-re "\n")))
10494 (delete-region (match-beginning 0) (match-end 0))))
10495 ;; If it is simple, we can put the ); on the same line as the last text
10496 (let ((rtn-pt (point)))
10498 (while (progn (backward-char 1)
10499 (looking-at "[ \t\n\f]")))
10500 (when (looking-at ",")
10501 (delete-region (+ 1 (point)) rtn-pt))))
10503 (indent-to indent))
10505 ;; Still need to kill final comma - always is one as we put one after the .*
10506 (re-search-backward ",")
10507 (delete-char 1))))))
10509 (defun verilog-delete-auto ()
10510 "Delete the automatic outputs, regs, and wires created by \\[verilog-auto].
10511 Use \\[verilog-auto] to re-insert the updated AUTOs.
10513 The hooks `verilog-before-delete-auto-hook' and `verilog-delete-auto-hook' are
10514 called before and after this function, respectively."
10517 (if (buffer-file-name)
10518 (find-file-noselect (buffer-file-name))) ; To check we have latest version
10519 (verilog-save-no-change-functions
10520 (verilog-save-scan-cache
10521 ;; Allow user to customize
10522 (verilog-run-hooks 'verilog-before-delete-auto-hook)
10524 ;; Remove those that have multi-line insertions, possibly with parameters
10525 ;; We allow anything beginning with AUTO, so that users can add their own
10527 (verilog-auto-re-search-do
10528 (concat "/\\*AUTO[A-Za-z0-9_]+"
10529 ;; Optional parens or quoted parameter or .* for (((...)))
10530 "\\(\\|([^)]*)\\|(\"[^\"]*\")\\).*?"
10532 'verilog-delete-autos-lined)
10533 ;; Remove those that are in parenthesis
10534 (verilog-auto-re-search-do
10537 (verilog-regexp-words
10538 `("AS" "AUTOARG" "AUTOCONCATWIDTH" "AUTOINST" "AUTOINSTPARAM"
10541 'verilog-delete-to-paren)
10542 ;; Do .* instantiations, but avoid removing any user pins by looking for our magic comments
10543 (verilog-auto-re-search-do "\\.\\*"
10544 'verilog-delete-auto-star-all)
10545 ;; Remove template comments ... anywhere in case was pasted after AUTOINST removed
10546 (goto-char (point-min))
10547 (while (re-search-forward "\\s-*// \\(Templated\\|Implicit \\.\\*\\)\\([ \tLT0-9]*\\| LHS: .*\\)?$" nil t)
10548 (replace-match ""))
10551 (verilog-run-hooks 'verilog-delete-auto-hook)))))
10556 (defun verilog-inject-auto ()
10557 "Examine legacy non-AUTO code and insert AUTOs in appropriate places.
10559 Any always @ blocks with sensitivity lists that match computed lists will
10560 be replaced with /*AS*/ comments.
10562 Any cells will get /*AUTOINST*/ added to the end of the pin list.
10563 Pins with have identical names will be deleted.
10565 Argument lists will not be deleted, /*AUTOARG*/ will only be inserted to
10566 support adding new ports. You may wish to delete older ports yourself.
10570 module ExampInject (i, o);
10576 InstModule instName
10581 Typing \\[verilog-inject-auto] will make this into:
10583 module ExampInject (i, o/*AUTOARG*/
10588 always @ (/*AS*/i or j)
10590 InstModule instName
10599 (defun verilog-inject-arg ()
10600 "Inject AUTOARG into new code. See `verilog-inject-auto'."
10601 ;; Presume one module per file.
10603 (goto-char (point-min))
10604 (while (verilog-re-search-forward-quick "\\<module\\>" nil t)
10605 (let ((endmodp (save-excursion
10606 (verilog-re-search-forward-quick "\\<endmodule\\>" nil t)
10608 ;; See if there's already a comment .. inside a comment so not verilog-re-search
10609 (when (not (re-search-forward "/\\*AUTOARG\\*/" endmodp t))
10610 (verilog-re-search-forward-quick ";" nil t)
10612 (verilog-backward-syntactic-ws-quick)
10613 (backward-char 1) ; Moves to paren that closes argdecl's
10614 (when (looking-at ")")
10615 (verilog-insert "/*AUTOARG*/")))))))
10617 (defun verilog-inject-sense ()
10618 "Inject AUTOSENSE into new code. See `verilog-inject-auto'."
10620 (goto-char (point-min))
10621 (while (verilog-re-search-forward-quick "\\<always\\s *@\\s *(" nil t)
10622 (let* ((start-pt (point))
10623 (modi (verilog-modi-current))
10624 (moddecls (verilog-modi-get-decls modi))
10628 (verilog-forward-sexp-ign-cmt 1)
10629 (backward-char 1) ; End )
10630 (when (not (verilog-re-search-backward-quick "/\\*\\(AUTOSENSE\\|AS\\)\\*/" start-pt t))
10631 (setq pre-sigs (verilog-signals-from-signame
10632 (verilog-read-signals start-pt (point)))
10633 got-sigs (verilog-auto-sense-sigs moddecls nil))
10634 (when (not (or (verilog-signals-not-in pre-sigs got-sigs) ; Both are equal?
10635 (verilog-signals-not-in got-sigs pre-sigs)))
10636 (delete-region start-pt (point))
10637 (verilog-insert "/*AS*/")))))))
10639 (defun verilog-inject-inst ()
10640 "Inject AUTOINST into new code. See `verilog-inject-auto'."
10642 (goto-char (point-min))
10643 ;; It's hard to distinguish modules; we'll instead search for pins.
10644 (while (verilog-re-search-forward-quick "\\.\\s *[a-zA-Z0-9`_\$]+\\s *(\\s *[a-zA-Z0-9`_\$]+\\s *)" nil t)
10645 (verilog-backward-open-paren) ; Inst start
10647 ((= (preceding-char) ?\#) ; #(...) parameter section, not pin. Skip.
10649 (verilog-forward-close-paren)) ; Parameters done
10652 (let ((indent-pt (+ (current-column)))
10653 (end-pt (save-excursion (verilog-forward-close-paren) (point))))
10654 (cond ((verilog-re-search-forward-quick "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-pt t)
10655 (goto-char end-pt)) ; Already there, continue search with next instance
10657 ;; Delete identical interconnect
10658 (let ((case-fold-search nil)) ; So we don't convert upper-to-lower, etc
10659 (while (verilog-re-search-forward-quick "\\.\\s *\\([a-zA-Z0-9`_\$]+\\)*\\s *(\\s *\\1\\s *)\\s *" end-pt t)
10660 (delete-region (match-beginning 0) (match-end 0))
10661 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))) ; Keep it correct
10662 (while (or (looking-at "[ \t\n\f,]+")
10663 (looking-at "//[^\n]*"))
10664 (delete-region (match-beginning 0) (match-end 0))
10665 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))))))
10666 (verilog-forward-close-paren)
10668 ;; Not verilog-re-search, as we don't want to strip comments
10669 (while (re-search-backward "[ \t\n\f]+" (- (point) 1) t)
10670 (delete-region (match-beginning 0) (match-end 0)))
10671 (verilog-insert "\n")
10672 (verilog-insert-indent "/*AUTOINST*/")))))))))
10678 (defun verilog-diff-buffers-p (b1 b2 &optional whitespace)
10679 "Return nil if buffers B1 and B2 have same contents.
10680 Else, return point in B1 that first mismatches.
10681 If optional WHITESPACE true, ignore whitespace."
10683 (let* ((case-fold-search nil) ; compare-buffer-substrings cares
10684 (p1 (with-current-buffer b1 (goto-char (point-min))))
10685 (p2 (with-current-buffer b2 (goto-char (point-min))))
10686 (maxp1 (with-current-buffer b1 (point-max)))
10687 (maxp2 (with-current-buffer b2 (point-max)))
10690 (while (not (and (eq p1 op1) (eq p2 op2)))
10691 ;; If both windows have whitespace optionally skip over it.
10693 ;; skip-syntax-* doesn't count \n
10694 (with-current-buffer b1
10696 (skip-chars-forward " \t\n\r\f\v")
10698 (with-current-buffer b2
10700 (skip-chars-forward " \t\n\r\f\v")
10701 (setq p2 (point))))
10702 (setq size (min (- maxp1 p1) (- maxp2 p2)))
10703 (setq progress (compare-buffer-substrings b2 p2 (+ size p2)
10704 b1 p1 (+ size p1)))
10705 (setq progress (if (zerop progress) size (1- (abs progress))))
10706 (setq op1 p1 op2 p2
10708 p2 (+ p2 progress)))
10710 (if (and (eq p1 maxp1) (eq p2 maxp2))
10713 (defun verilog-diff-file-with-buffer (f1 b2 &optional whitespace show)
10714 "View the differences between file F1 and buffer B2.
10715 This requires the external program `diff-command' to be in your `exec-path',
10716 and uses `diff-switches' in which you may want to have \"-u\" flag.
10717 Ignores WHITESPACE if t, and writes output to stdout if SHOW."
10718 ;; Similar to `diff-buffer-with-file' but works on XEmacs, and doesn't
10719 ;; call `diff' as `diff' has different calling semantics on different
10720 ;; versions of Emacs.
10721 (if (not (file-exists-p f1))
10722 (message "Buffer %s has no associated file on disc" (buffer-name b2))
10723 (with-temp-buffer "*Verilog-Diff*"
10724 (let ((outbuf (current-buffer))
10725 (f2 (make-temp-file "vm-diff-auto-")))
10728 (with-current-buffer b2
10731 (write-region (point-min) (point-max) f2 nil 'nomessage)))
10732 (call-process diff-command nil outbuf t
10733 diff-switches ; User may want -u in diff-switches
10734 (if whitespace "-b" "")
10736 ;; Print out results. Alternatively we could have call-processed
10737 ;; ourself, but this way we can reuse diff switches
10739 (with-current-buffer outbuf (message "%s" (buffer-string))))))
10741 (when (file-exists-p f2)
10742 (delete-file f2))))))
10744 (defun verilog-diff-report (b1 b2 diffpt)
10745 "Report differences detected with `verilog-diff-auto'.
10746 Differences are between buffers B1 and B2, starting at point
10747 DIFFPT. This function is called via `verilog-diff-function'."
10748 (let ((name1 (with-current-buffer b1 (buffer-file-name))))
10749 (verilog-warn "%s:%d: Difference in AUTO expansion found"
10750 name1 (with-current-buffer b1
10751 (count-lines (point-min) diffpt)))
10752 (cond (noninteractive
10753 (verilog-diff-file-with-buffer name1 b2 t t))
10755 (ediff-buffers b1 b2)))))
10757 (defun verilog-diff-auto ()
10758 "Expand AUTOs in a temporary buffer and indicate any change.
10759 Whitespace is ignored when detecting differences, but once a
10760 difference is detected, whitespace differences may be shown.
10762 To call this from the command line, see \\[verilog-batch-diff-auto].
10764 The action on differences is selected with
10765 `verilog-diff-function'. The default is `verilog-diff-report'
10766 which will report an error and run `ediff' in interactive mode,
10767 or `diff' in batch mode."
10769 (let ((b1 (current-buffer)) b2 diffpt
10770 (name1 (buffer-file-name))
10771 (newname "*Verilog-Diff*"))
10773 (when (get-buffer newname)
10774 (kill-buffer newname))
10775 (setq b2 (let (buffer-file-name) ; Else clone is upset
10776 (clone-buffer newname)))
10777 (with-current-buffer b2
10778 ;; auto requires the filename, but can't have same filename in two
10779 ;; buffers; so override both b1 and b2's names
10780 (let ((buffer-file-name name1))
10783 (with-current-buffer b1 (setq buffer-file-name nil))
10785 (when (not verilog-auto-star-save)
10786 (verilog-delete-auto-star-implicit)))
10787 ;; Restore name if unwind
10788 (with-current-buffer b1 (setq buffer-file-name name1)))))
10790 (setq diffpt (verilog-diff-buffers-p b1 b2 t))
10791 (cond ((not diffpt)
10792 (unless noninteractive (message "AUTO expansion identical"))
10793 (kill-buffer newname)) ; Nice to cleanup after oneself
10795 (funcall verilog-diff-function b1 b2 diffpt)))
10796 ;; Return result of compare
10803 (defun verilog-auto-save-check ()
10804 "On saving see if we need auto update."
10805 (cond ((not verilog-auto-save-policy)) ; disabled
10806 ((not (save-excursion
10808 (let ((case-fold-search nil))
10809 (goto-char (point-min))
10810 (re-search-forward "AUTO" nil t))))))
10811 ((eq verilog-auto-save-policy 'force)
10813 ((not (buffer-modified-p)))
10814 ((eq verilog-auto-update-tick (buffer-chars-modified-tick))) ; up-to-date
10815 ((eq verilog-auto-save-policy 'detect)
10818 (when (yes-or-no-p "AUTO statements not recomputed, do it now? ")
10820 ;; Don't ask again if didn't update
10821 (set (make-local-variable 'verilog-auto-update-tick) (buffer-chars-modified-tick))))
10822 (when (not verilog-auto-star-save)
10823 (verilog-delete-auto-star-implicit))
10824 nil) ; Always return nil -- we don't write the file ourselves
10826 (defun verilog-auto-read-locals ()
10827 "Return file local variable segment at bottom of file."
10829 (goto-char (point-max))
10830 (if (re-search-backward "Local Variables:" nil t)
10831 (buffer-substring-no-properties (point) (point-max))
10834 (defun verilog-auto-reeval-locals (&optional force)
10835 "Read file local variable segment at bottom of file if it has changed.
10836 If FORCE, always reread it."
10837 (let ((curlocal (verilog-auto-read-locals)))
10838 (when (or force (not (equal verilog-auto-last-file-locals curlocal)))
10839 (set (make-local-variable 'verilog-auto-last-file-locals) curlocal)
10840 ;; Note this may cause this function to be recursively invoked,
10841 ;; because hack-local-variables may call (verilog-mode)
10842 ;; The above when statement will prevent it from recursing forever.
10843 (hack-local-variables)
10849 (defun verilog-auto-arg-ports (sigs message indent-pt)
10850 "Print a list of ports for AUTOARG.
10851 Takes SIGS list, adds MESSAGE to front and inserts each at INDENT-PT."
10853 (when verilog-auto-arg-sort
10854 (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
10856 (indent-to indent-pt)
10860 (indent-to indent-pt)
10862 (cond ((equal verilog-auto-arg-format 'single)
10864 (indent-to indent-pt)
10866 ;; verilog-auto-arg-format 'packed
10867 ((> (+ 2 (current-column) (length (verilog-sig-name (car sigs)))) fill-column)
10869 (indent-to indent-pt)
10874 (insert (verilog-sig-name (car sigs)) ",")
10875 (setq sigs (cdr sigs))))))
10877 (defun verilog-auto-arg ()
10878 "Expand AUTOARG statements.
10879 Replace the argument declarations at the beginning of the
10880 module with ones automatically derived from input and output
10881 statements. This can be dangerous if the module is instantiated
10882 using position-based connections, so use only name-based when
10883 instantiating the resulting module. Long lines are split based
10884 on the `fill-column', see \\[set-fill-column].
10887 Concatenation and outputting partial buses is not supported.
10889 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
10893 module ExampArg (/*AUTOARG*/);
10898 Typing \\[verilog-auto] will make this into:
10900 module ExampArg (/*AUTOARG*/
10910 The argument declarations may be printed in declaration order to
10911 best suit order based instantiations, or alphabetically, based on
10912 the `verilog-auto-arg-sort' variable.
10914 Formatting is controlled with `verilog-auto-arg-format' variable.
10916 Any ports declared between the ( and /*AUTOARG*/ are presumed to be
10917 predeclared and are not redeclared by AUTOARG. AUTOARG will make a
10918 conservative guess on adding a comma for the first signal, if you have
10919 any ifdefs or complicated expressions before the AUTOARG you will need
10920 to choose the comma yourself.
10922 Avoid declaring ports manually, as it makes code harder to maintain."
10924 (let* ((modi (verilog-modi-current))
10925 (moddecls (verilog-modi-get-decls modi))
10926 (skip-pins (aref (verilog-read-arg-pins) 0)))
10927 (verilog-repair-open-comma)
10928 (verilog-auto-arg-ports (verilog-signals-not-in
10929 (verilog-decls-get-outputs moddecls)
10932 verilog-indent-level-declaration)
10933 (verilog-auto-arg-ports (verilog-signals-not-in
10934 (verilog-decls-get-inouts moddecls)
10937 verilog-indent-level-declaration)
10938 (verilog-auto-arg-ports (verilog-signals-not-in
10939 (verilog-decls-get-inputs moddecls)
10942 verilog-indent-level-declaration)
10943 (verilog-repair-close-comma)
10944 (unless (eq (char-before) ?/ )
10946 (indent-to verilog-indent-level-declaration))))
10948 (defun verilog-auto-assign-modport ()
10949 "Expand AUTOASSIGNMODPORT statements, as part of \\[verilog-auto].
10950 Take input/output/inout statements from the specified interface
10951 and modport and use to build assignments into the modport, for
10952 making verification modules that connect to UVM interfaces.
10954 The first parameter is the name of an interface.
10956 The second parameter is a regexp of modports to read from in
10959 The third parameter is the instance name to use to dot reference into.
10961 The optional fourth parameter is a regular expression, and only
10962 signals matching the regular expression will be included.
10966 Interface names must be resolvable to filenames. See `verilog-auto-inst'.
10968 Inouts are not supported, as assignments must be unidirectional.
10970 If a signal is part of the interface header and in both a
10971 modport and the interface itself, it will not be listed. (As
10972 this would result in a syntax error when the connections are
10975 See the example in `verilog-auto-inout-modport'."
10977 (let* ((params (verilog-read-auto-params 3 4))
10978 (submod (nth 0 params))
10979 (modport-re (nth 1 params))
10980 (inst-name (nth 2 params))
10981 (regexp (nth 3 params))
10982 direction-re submodi) ; direction argument not supported until requested
10983 ;; Lookup position, etc of co-module
10984 ;; Note this may raise an error
10985 (when (setq submodi (verilog-modi-lookup submod t))
10986 (let* ((indent-pt (current-indentation))
10987 (submoddecls (verilog-modi-get-decls submodi))
10988 (submodportdecls (verilog-modi-modport-lookup submodi modport-re))
10989 (sig-list-i (verilog-signals-in ; Decls doesn't have data types, must resolve
10990 (verilog-decls-get-vars submoddecls)
10991 (verilog-signals-not-in
10992 (verilog-decls-get-inputs submodportdecls)
10993 (verilog-decls-get-ports submoddecls))))
10994 (sig-list-o (verilog-signals-in ; Decls doesn't have data types, must resolve
10995 (verilog-decls-get-vars submoddecls)
10996 (verilog-signals-not-in
10997 (verilog-decls-get-outputs submodportdecls)
10998 (verilog-decls-get-ports submoddecls)))))
11000 (setq sig-list-i (verilog-signals-edit-wire-reg
11001 (verilog-signals-matching-dir-re
11002 (verilog-signals-matching-regexp sig-list-i regexp)
11003 "input" direction-re))
11004 sig-list-o (verilog-signals-edit-wire-reg
11005 (verilog-signals-matching-dir-re
11006 (verilog-signals-matching-regexp sig-list-o regexp)
11007 "output" direction-re)))
11008 (setq sig-list-i (sort (copy-alist sig-list-i) `verilog-signals-sort-compare))
11009 (setq sig-list-o (sort (copy-alist sig-list-o) `verilog-signals-sort-compare))
11010 (when (or sig-list-i sig-list-o)
11011 (verilog-insert-indent "// Beginning of automatic assignments from modport\n")
11012 ;; Don't sort them so an upper AUTOINST will match the main module
11013 (let ((sigs sig-list-o))
11015 (verilog-insert-indent "assign " (verilog-sig-name (car sigs))
11017 "." (verilog-sig-name (car sigs)) ";\n")
11018 (setq sigs (cdr sigs))))
11019 (let ((sigs sig-list-i))
11021 (verilog-insert-indent "assign " inst-name
11022 "." (verilog-sig-name (car sigs))
11023 " = " (verilog-sig-name (car sigs)) ";\n")
11024 (setq sigs (cdr sigs))))
11025 (verilog-insert-indent "// End of automatics\n")))))))
11027 (defun verilog-auto-inst-port-map (_port-st)
11030 (defvar vl-cell-type nil "See `verilog-auto-inst'.") ; Prevent compile warning
11031 (defvar vl-cell-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
11032 (defvar vl-modport nil "See `verilog-auto-inst'.") ; Prevent compile warning
11033 (defvar vl-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
11034 (defvar vl-width nil "See `verilog-auto-inst'.") ; Prevent compile warning
11035 (defvar vl-dir nil "See `verilog-auto-inst'.") ; Prevent compile warning
11036 (defvar vl-bits nil "See `verilog-auto-inst'.") ; Prevent compile warning
11037 (defvar vl-mbits nil "See `verilog-auto-inst'.") ; Prevent compile warning
11039 (defun verilog-auto-inst-port (port-st indent-pt moddecls tpl-list tpl-num for-star par-values)
11040 "Print out an instantiation connection for this PORT-ST.
11041 Insert to INDENT-PT, use template TPL-LIST.
11042 @ are instantiation numbers, replaced with TPL-NUM.
11043 @\"(expression @)\" are evaluated, with @ as a variable.
11044 If FOR-STAR add comment it is a .* expansion.
11045 If PAR-VALUES replace final strings with these parameter values."
11046 (let* ((port (verilog-sig-name port-st))
11047 (tpl-ass (or (assoc port (car tpl-list))
11048 (verilog-auto-inst-port-map port-st)))
11049 ;; vl-* are documented for user use
11050 (vl-name (verilog-sig-name port-st))
11051 (vl-width (verilog-sig-width port-st))
11052 (vl-modport (verilog-sig-modport port-st))
11053 (vl-mbits (if (verilog-sig-multidim port-st)
11054 (verilog-sig-multidim-string port-st) ""))
11055 (vl-bits (if (or verilog-auto-inst-vector
11056 (not (assoc port (verilog-decls-get-signals moddecls)))
11057 (not (equal (verilog-sig-bits port-st)
11059 (assoc port (verilog-decls-get-signals moddecls))))))
11060 (or (verilog-sig-bits port-st) "")
11062 (case-fold-search nil)
11063 (check-values par-values)
11065 ;; Replace parameters in bit-width
11066 (when (and check-values
11067 (not (equal vl-bits "")))
11068 (while check-values
11069 (setq vl-bits (verilog-string-replace-matches
11070 (concat "\\<" (nth 0 (car check-values)) "\\>")
11071 (concat "(" (nth 1 (car check-values)) ")")
11073 vl-mbits (verilog-string-replace-matches
11074 (concat "\\<" (nth 0 (car check-values)) "\\>")
11075 (concat "(" (nth 1 (car check-values)) ")")
11077 check-values (cdr check-values)))
11078 (setq vl-bits (verilog-simplify-range-expression vl-bits)
11079 vl-mbits (verilog-simplify-range-expression vl-mbits)
11080 vl-width (verilog-make-width-expression vl-bits))) ; Not in the loop for speed
11081 ;; Default net value if not found
11082 (setq dflt-bits (if (and (verilog-sig-bits port-st)
11083 (or (verilog-sig-multidim port-st)
11084 (verilog-sig-memory port-st)))
11085 (concat "/*" vl-mbits vl-bits "*/")
11087 tpl-net (concat port
11088 (if (and vl-modport
11089 ;; .modport cannot be added if attachment is
11090 ;; already declared as modport, VCS croaks
11091 (let ((sig (assoc port (verilog-decls-get-interfaces moddecls))))
11092 (not (and sig (verilog-sig-modport sig)))))
11093 (concat "." vl-modport) "")
11096 (cond (tpl-ass ; Template of exact port name
11097 (setq tpl-net (nth 1 tpl-ass)))
11098 ((nth 1 tpl-list) ; Wildcards in template, search them
11099 (let ((wildcards (nth 1 tpl-list)))
11101 (when (string-match (nth 0 (car wildcards)) port)
11102 (setq tpl-ass (car wildcards) ; so allow @ parsing
11103 tpl-net (replace-match (nth 1 (car wildcards))
11105 (setq wildcards (cdr wildcards))))))
11106 ;; Parse Templated variable
11108 ;; Evaluate @"(lispcode)"
11109 (when (string-match "@\".*[^\\]\"" tpl-net)
11110 (while (string-match "@\"\\(\\([^\\\"]*\\(\\\\.\\)*\\)*\\)\"" tpl-net)
11113 (substring tpl-net 0 (match-beginning 0))
11115 (let* ((expr (match-string 1 tpl-net))
11118 (setq expr (verilog-string-replace-matches "\\\\\"" "\"" nil nil expr))
11119 (setq expr (verilog-string-replace-matches "@" tpl-num nil nil expr))
11120 (prin1 (eval (car (read-from-string expr)))
11121 (lambda (_ch) ())))))
11122 (if (numberp value) (setq value (number-to-string value)))
11124 (substring tpl-net (match-end 0))))))
11125 ;; Replace @ and [] magic variables in final output
11126 (setq tpl-net (verilog-string-replace-matches "@" tpl-num nil nil tpl-net))
11127 (setq tpl-net (verilog-string-replace-matches "\\[\\]\\[\\]" dflt-bits nil nil tpl-net))
11128 (setq tpl-net (verilog-string-replace-matches "\\[\\]" vl-bits nil nil tpl-net)))
11130 (indent-to indent-pt)
11132 (unless (and verilog-auto-inst-dot-name
11133 (equal port tpl-net))
11134 (indent-to verilog-auto-inst-column)
11135 (insert "(" tpl-net ")"))
11138 (verilog-read-auto-template-hit tpl-ass)
11139 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
11140 verilog-auto-inst-column))
11141 ;; verilog-insert requires the complete comment in one call - including the newline
11142 (cond ((equal verilog-auto-inst-template-numbers `lhs)
11143 (verilog-insert " // Templated"
11144 " LHS: " (nth 0 tpl-ass)
11146 (verilog-auto-inst-template-numbers
11147 (verilog-insert " // Templated"
11148 " T" (int-to-string (nth 2 tpl-ass))
11149 " L" (int-to-string (nth 3 tpl-ass))
11152 (verilog-insert " // Templated\n"))))
11154 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
11155 verilog-auto-inst-column))
11156 (verilog-insert " // Implicit .\*\n")) ;For some reason the . or * must be escaped...
11159 ;;(verilog-auto-inst-port (list "foo" "[5:0]") 10 (list (list "foo" "a@\"(% (+ @ 1) 4)\"a")) "3")
11160 ;;(x "incom[@\"(+ (* 8 @) 7)\":@\"(* 8 @)\"]")
11161 ;;(x ".out (outgo[@\"(concat (+ (* 8 @) 7) \\\":\\\" ( * 8 @))\"]));")
11163 (defun verilog-auto-inst-port-list (sig-list indent-pt moddecls tpl-list tpl-num for-star par-values)
11164 "For `verilog-auto-inst' print a list of ports using `verilog-auto-inst-port'."
11165 (when verilog-auto-inst-sort
11166 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare)))
11167 (mapc (lambda (port)
11168 (verilog-auto-inst-port port indent-pt moddecls
11169 tpl-list tpl-num for-star par-values))
11172 (defun verilog-auto-inst-first ()
11173 "Insert , etc before first ever port in this instant, as part of \\[verilog-auto-inst]."
11174 ;; Do we need a trailing comma?
11175 ;; There maybe an ifdef or something similar before us. What a mess. Thus
11176 ;; to avoid trouble we only insert on preceding ) or *.
11177 ;; Insert first port on new line
11178 (insert "\n") ; Must insert before search, so point will move forward if insert comma
11180 (verilog-re-search-backward-quick "[^ \t\n\f]" nil nil)
11181 (when (looking-at ")\\|\\*") ; Generally don't insert, unless we are fairly sure
11185 (defun verilog-auto-star ()
11186 "Expand SystemVerilog .* pins, as part of \\[verilog-auto].
11188 If `verilog-auto-star-expand' is set, .* pins are treated if they were
11189 AUTOINST statements, otherwise they are ignored. For safety, Verilog mode
11190 will also ignore any .* that are not last in your pin list (this prevents
11191 it from deleting pins following the .* when it expands the AUTOINST.)
11193 On writing your file, unless `verilog-auto-star-save' is set, any
11194 non-templated expanded pins will be removed. You may do this at any time
11195 with \\[verilog-delete-auto-star-implicit].
11197 If you are converting a module to use .* for the first time, you may wish
11198 to use \\[verilog-inject-auto] and then replace the created AUTOINST with .*.
11200 See `verilog-auto-inst' for examples, templates, and more information."
11201 (when (verilog-auto-star-safe)
11202 (verilog-auto-inst)))
11204 (defun verilog-auto-inst ()
11205 "Expand AUTOINST statements, as part of \\[verilog-auto].
11206 Replace the pin connections to an instantiation or interface
11207 declaration with ones automatically derived from the module or
11208 interface header of the instantiated item.
11210 If `verilog-auto-star-expand' is set, also expand SystemVerilog .* ports,
11211 and delete them before saving unless `verilog-auto-star-save' is set.
11212 See `verilog-auto-star' for more information.
11214 The pins are printed in declaration order or alphabetically,
11215 based on the `verilog-auto-inst-sort' variable.
11218 Module names must be resolvable to filenames by adding a
11219 `verilog-library-extensions', and being found in the same directory, or
11220 by changing the variable `verilog-library-flags' or
11221 `verilog-library-directories'. Macros `modname are translated through the
11222 vh-{name} Emacs variable, if that is not found, it just ignores the \\=`.
11224 In templates you must have one signal per line, ending in a ), or ));,
11225 and have proper () nesting, including a final ); to end the template.
11227 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
11229 SystemVerilog multidimensional input/output has only experimental support.
11231 SystemVerilog .name syntax is used if `verilog-auto-inst-dot-name' is set.
11233 Parameters referenced by the instantiation will remain symbolic, unless
11234 `verilog-auto-inst-param-value' is set.
11236 Gate primitives (and/or) may have AUTOINST for the purpose of
11237 AUTOWIRE declarations, etc. Gates are the only case when
11238 position based connections are passed.
11240 The array part of arrayed instances are ignored; this may
11241 result in undesirable default AUTOINST connections; use a
11244 For example, first take the submodule InstModule.v:
11246 module InstModule (o,i);
11249 wire [31:0] o = {32{i}};
11252 This is then used in an upper level module:
11254 module ExampInst (o,i);
11257 InstModule instName
11261 Typing \\[verilog-auto] will make this into:
11263 module ExampInst (o,i);
11266 InstModule instName
11274 Where the list of inputs and outputs came from the inst module.
11278 Unless you are instantiating a module multiple times, or the module is
11279 something trivial like an adder, DO NOT CHANGE SIGNAL NAMES ACROSS HIERARCHY.
11280 It just makes for unmaintainable code. To sanitize signal names, try
11281 vrename from URL `http://www.veripool.org'.
11283 When you need to violate this suggestion there are two ways to list
11284 exceptions, placing them before the AUTOINST, or using templates.
11286 Any ports defined before the /*AUTOINST*/ are not included in the list of
11287 automatics. This is similar to making a template as described below, but
11288 is restricted to simple connections just like you normally make. Also note
11289 that any signals before the AUTOINST will only be picked up by AUTOWIRE if
11290 you have the appropriate // Input or // Output comment, and exactly the
11291 same line formatting as AUTOINST itself uses.
11293 InstModule instName
11295 .i (my_i_dont_mess_with_it),
11303 For multiple instantiations based upon a single template, create a
11304 commented out template:
11306 /* InstModule AUTO_TEMPLATE (
11311 Templates go ABOVE the instantiation(s). When an instantiation is
11312 expanded `verilog-mode' simply searches up for the closest template.
11313 Thus you can have multiple templates for the same module, just alternate
11314 between the template for an instantiation and the instantiation itself.
11315 (For backward compatibility if no template is found above, it
11316 will also look below, but do not use this behavior in new designs.)
11318 The module name must be the same as the name of the module in the
11319 instantiation name, and the code \"AUTO_TEMPLATE\" must be in these exact
11320 words and capitalized. Only signals that must be different for each
11321 instantiation need to be listed.
11323 Inside a template, a [] in a connection name (with nothing else
11324 inside the brackets) will be replaced by the same bus subscript
11325 as it is being connected to, or the [] will be removed if it is
11326 a single bit signal.
11328 Inside a template, a [][] in a connection name will behave
11329 similarly to a [] for scalar or single-dimensional connection;
11330 for a multidimensional connection it will print a comment
11331 similar to that printed when a template is not used. Generally
11332 it is a good idea to do this for all connections in a template,
11333 as then they will work for any width signal, and with AUTOWIRE.
11334 See PTL_BUS becoming PTL_BUSNEW below.
11336 Inside a template, a [] in a connection name (with nothing else inside
11337 the brackets) will be replaced by the same bus subscript as it is being
11338 connected to, or the [] will be removed if it is a single bit signal.
11339 Generally it is a good idea to do this for all connections in a template,
11340 as then they will work for any width signal, and with AUTOWIRE. See
11341 PTL_BUS becoming PTL_BUSNEW below.
11343 If you have a complicated template, set `verilog-auto-inst-template-numbers'
11344 to see which regexps are matching. Don't leave that mode set after
11345 debugging is completed though, it will result in lots of extra differences
11346 and merge conflicts.
11348 Setting `verilog-auto-template-warn-unused' will report errors
11349 if any template lines are unused.
11353 /* InstModule AUTO_TEMPLATE (
11354 .ptl_bus (ptl_busnew[]),
11357 InstModule ms2m (/*AUTOINST*/);
11359 Typing \\[verilog-auto] will make this into:
11361 InstModule ms2m (/*AUTOINST*/
11363 .NotInTemplate (NotInTemplate),
11364 .ptl_bus (ptl_busnew[3:0]), // Templated
11368 Multiple Module Templates:
11370 The same template lines can be applied to multiple modules with
11371 the syntax as follows:
11373 /* InstModuleA AUTO_TEMPLATE
11374 InstModuleB AUTO_TEMPLATE
11375 InstModuleC AUTO_TEMPLATE
11376 InstModuleD AUTO_TEMPLATE (
11377 .ptl_bus (ptl_busnew[]),
11381 Note there is only one AUTO_TEMPLATE opening parenthesis.
11385 It is common to instantiate a cell multiple times, so templates make it
11386 trivial to substitute part of the cell name into the connection name.
11388 /* InstName AUTO_TEMPLATE <optional \"REGEXP\"> (
11390 .sig2 (sigy[@\"(% (+ 1 @) 4)\"]),
11394 If no regular expression is provided immediately after the AUTO_TEMPLATE
11395 keyword, then the @ character in any connection names will be replaced
11396 with the instantiation number; the first digits found in the cell's
11397 instantiation name.
11399 If a regular expression is provided, the @ character will be replaced
11400 with the first \(\) grouping that matches against the cell name. Using a
11401 regexp of \"\\([0-9]+\\)\" provides identical values for @ as when no
11402 regexp is provided. If you use multiple layers of parenthesis,
11403 \"test\\([^0-9]+\\)_\\([0-9]+\\)\" would replace @ with non-number
11404 characters after test and before _, whereas
11405 \"\\(test\\([a-z]+\\)_\\([0-9]+\\)\\)\" would replace @ with the entire
11410 /* InstModule AUTO_TEMPLATE (
11411 .ptl_mapvalidx (ptl_mapvalid[@]),
11412 .ptl_mapvalidp1x (ptl_mapvalid[@\"(% (+ 1 @) 4)\"]),
11415 InstModule ms2m (/*AUTOINST*/);
11417 Typing \\[verilog-auto] will make this into:
11419 InstModule ms2m (/*AUTOINST*/
11421 .ptl_mapvalidx (ptl_mapvalid[2]),
11422 .ptl_mapvalidp1x (ptl_mapvalid[3]));
11424 Note the @ character was replaced with the 2 from \"ms2m\".
11426 Alternatively, using a regular expression for @:
11428 /* InstModule AUTO_TEMPLATE \"_\\([a-z]+\\)\" (
11429 .ptl_mapvalidx (@_ptl_mapvalid),
11430 .ptl_mapvalidp1x (ptl_mapvalid_@),
11433 InstModule ms2_FOO (/*AUTOINST*/);
11434 InstModule ms2_BAR (/*AUTOINST*/);
11436 Typing \\[verilog-auto] will make this into:
11438 InstModule ms2_FOO (/*AUTOINST*/
11440 .ptl_mapvalidx (FOO_ptl_mapvalid),
11441 .ptl_mapvalidp1x (ptl_mapvalid_FOO));
11442 InstModule ms2_BAR (/*AUTOINST*/
11444 .ptl_mapvalidx (BAR_ptl_mapvalid),
11445 .ptl_mapvalidp1x (ptl_mapvalid_BAR));
11450 A template entry of the form
11452 .pci_req\\([0-9]+\\)_l (pci_req_jtag_[\\1]),
11454 will apply an Emacs style regular expression search for any port beginning
11455 in pci_req followed by numbers and ending in _l and connecting that to
11456 the pci_req_jtag_[] net, with the bus subscript coming from what matches
11457 inside the first set of \\( \\). Thus pci_req2_l becomes pci_req_jtag_[2].
11459 Since \\([0-9]+\\) is so common and ugly to read, a @ in the port name
11460 does the same thing. (Note a @ in the connection/replacement text is
11461 completely different -- still use \\1 there!) Thus this is the same as
11462 the above template:
11464 .pci_req@_l (pci_req_jtag_[\\1]),
11466 Here's another example to remove the _l, useful when naming conventions
11467 specify _ alone to mean active low. Note the use of [] to keep the bus
11470 .\\(.*\\)_l (\\1_[]),
11474 First any regular expression template is expanded.
11476 If the syntax @\"( ... )\" is found in a connection, the expression in
11477 quotes will be evaluated as a Lisp expression, with @ replaced by the
11478 instantiation number. The MAPVALIDP1X example above would put @+1 modulo
11479 4 into the brackets. Quote all double-quotes inside the expression with
11480 a leading backslash (\\\"...\\\"); or if the Lisp template is also a
11481 regexp template backslash the backslash quote (\\\\\"...\\\\\").
11483 There are special variables defined that are useful in these
11486 vl-name Name portion of the input/output port.
11487 vl-bits Bus bits portion of the input/output port ('[2:0]').
11488 vl-mbits Multidimensional array bits for port ('[2:0][3:0]').
11489 vl-width Width of the input/output port ('3' for [2:0]).
11490 May be a (...) expression if bits isn't a constant.
11491 vl-dir Direction of the pin input/output/inout/interface.
11492 vl-modport The modport, if an interface with a modport.
11493 vl-cell-type Module name/type of the cell ('InstModule').
11494 vl-cell-name Instance name of the cell ('instName').
11496 Normal Lisp variables may be used in expressions. See
11497 `verilog-read-defines' which can set vh-{definename} variables for use
11498 here. Also, any comments of the form:
11500 /*AUTO_LISP(setq foo 1)*/
11502 will evaluate any Lisp expression inside the parenthesis between the
11503 beginning of the buffer and the point of the AUTOINST. This allows
11504 functions to be defined or variables to be changed between instantiations.
11505 (See also `verilog-auto-insert-lisp' if you want the output from your
11506 lisp function to be inserted.)
11508 Note that when using lisp expressions errors may occur when @ is not a
11509 number; you may need to use the standard Emacs Lisp functions
11510 `number-to-string' and `string-to-number'.
11512 After the evaluation is completed, @ substitution and [] substitution
11515 For more information see the \\[verilog-faq] and forums at URL
11516 `http://www.veripool.org'."
11519 (let* ((pt (point))
11520 (for-star (save-excursion (backward-char 2) (looking-at "\\.\\*")))
11521 (indent-pt (save-excursion (verilog-backward-open-paren)
11522 (1+ (current-column))))
11523 (verilog-auto-inst-column (max verilog-auto-inst-column
11524 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
11525 (modi (verilog-modi-current))
11526 (moddecls (verilog-modi-get-decls modi))
11527 submod submodi submoddecls
11528 inst skip-pins tpl-list tpl-num did-first par-values)
11530 ;; Find module name that is instantiated
11531 (setq submod (verilog-read-inst-module)
11532 inst (verilog-read-inst-name)
11533 vl-cell-type submod
11535 skip-pins (aref (verilog-read-inst-pins) 0))
11537 ;; Parse any AUTO_LISP() before here
11538 (verilog-read-auto-lisp (point-min) pt)
11540 ;; Read parameters (after AUTO_LISP)
11541 (setq par-values (and verilog-auto-inst-param-value
11542 (verilog-read-inst-param-value)))
11544 ;; Lookup position, etc of submodule
11545 ;; Note this may raise an error
11546 (when (and (not (member submod verilog-gate-keywords))
11547 (setq submodi (verilog-modi-lookup submod t)))
11548 (setq submoddecls (verilog-modi-get-decls submodi))
11549 ;; If there's a number in the instantiation, it may be an argument to the
11550 ;; automatic variable instantiation program.
11551 (let* ((tpl-info (verilog-read-auto-template submod))
11552 (tpl-regexp (aref tpl-info 0)))
11553 (setq tpl-num (if (verilog-string-match-fold tpl-regexp inst)
11554 (match-string 1 inst)
11556 tpl-list (aref tpl-info 1)))
11557 ;; Find submodule's signals and dump
11558 (let ((sig-list (and (equal (verilog-modi-get-type submodi) "interface")
11559 (verilog-signals-not-in
11560 (verilog-decls-get-vars submoddecls)
11562 (vl-dir "interfaced"))
11563 (when (and sig-list
11564 verilog-auto-inst-interfaced-ports)
11565 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11566 ;; Note these are searched for in verilog-read-sub-decls.
11567 (verilog-insert-indent "// Interfaced\n")
11568 (verilog-auto-inst-port-list sig-list indent-pt moddecls
11569 tpl-list tpl-num for-star par-values)))
11570 (let ((sig-list (verilog-signals-not-in
11571 (verilog-decls-get-interfaces submoddecls)
11573 (vl-dir "interface"))
11575 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11576 ;; Note these are searched for in verilog-read-sub-decls.
11577 (verilog-insert-indent "// Interfaces\n")
11578 (verilog-auto-inst-port-list sig-list indent-pt moddecls
11579 tpl-list tpl-num for-star par-values)))
11580 (let ((sig-list (verilog-signals-not-in
11581 (verilog-decls-get-outputs submoddecls)
11585 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11586 (verilog-insert-indent "// Outputs\n")
11587 (verilog-auto-inst-port-list sig-list indent-pt moddecls
11588 tpl-list tpl-num for-star par-values)))
11589 (let ((sig-list (verilog-signals-not-in
11590 (verilog-decls-get-inouts submoddecls)
11594 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11595 (verilog-insert-indent "// Inouts\n")
11596 (verilog-auto-inst-port-list sig-list indent-pt moddecls
11597 tpl-list tpl-num for-star par-values)))
11598 (let ((sig-list (verilog-signals-not-in
11599 (verilog-decls-get-inputs submoddecls)
11603 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11604 (verilog-insert-indent "// Inputs\n")
11605 (verilog-auto-inst-port-list sig-list indent-pt moddecls
11606 tpl-list tpl-num for-star par-values)))
11610 (re-search-backward "," pt t)
11613 (search-forward "\n") ; Added by inst-port
11615 (if (search-forward ")" nil t) ; From user, moved up a line
11617 (if (search-forward ";" nil t) ; Don't error if user had syntax error and forgot it
11618 (delete-char -1)))))))))
11620 (defun verilog-auto-inst-param ()
11621 "Expand AUTOINSTPARAM statements, as part of \\[verilog-auto].
11622 Replace the parameter connections to an instantiation with ones
11623 automatically derived from the module header of the instantiated netlist.
11625 See \\[verilog-auto-inst] for limitations, and templates to customize the
11628 For example, first take the submodule InstModule.v:
11630 module InstModule (o,i);
11634 This is then used in an upper level module:
11636 module ExampInst (o,i);
11638 InstModule #(/*AUTOINSTPARAM*/)
11639 instName (/*AUTOINST*/);
11642 Typing \\[verilog-auto] will make this into:
11644 module ExampInst (o,i);
11647 InstModule #(/*AUTOINSTPARAM*/
11650 instName (/*AUTOINST*/);
11653 Where the list of parameter connections come from the inst module.
11657 You can customize the parameter connections using AUTO_TEMPLATEs,
11658 just as you would with \\[verilog-auto-inst]."
11661 (let* ((pt (point))
11662 (indent-pt (save-excursion (verilog-backward-open-paren)
11663 (1+ (current-column))))
11664 (verilog-auto-inst-column (max verilog-auto-inst-column
11665 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
11666 (modi (verilog-modi-current))
11667 (moddecls (verilog-modi-get-decls modi))
11668 submod submodi submoddecls
11669 inst skip-pins tpl-list tpl-num did-first)
11670 ;; Find module name that is instantiated
11671 (setq submod (save-excursion
11672 ;; Get to the point where AUTOINST normally is to read the module
11673 (verilog-re-search-forward-quick "[(;]" nil nil)
11674 (verilog-read-inst-module))
11675 inst (save-excursion
11676 ;; Get to the point where AUTOINST normally is to read the module
11677 (verilog-re-search-forward-quick "[(;]" nil nil)
11678 (verilog-read-inst-name))
11679 vl-cell-type submod
11681 skip-pins (aref (verilog-read-inst-pins) 0))
11683 ;; Parse any AUTO_LISP() before here
11684 (verilog-read-auto-lisp (point-min) pt)
11686 ;; Lookup position, etc of submodule
11687 ;; Note this may raise an error
11688 (when (setq submodi (verilog-modi-lookup submod t))
11689 (setq submoddecls (verilog-modi-get-decls submodi))
11690 ;; If there's a number in the instantiation, it may be an argument to the
11691 ;; automatic variable instantiation program.
11692 (let* ((tpl-info (verilog-read-auto-template submod))
11693 (tpl-regexp (aref tpl-info 0)))
11694 (setq tpl-num (if (verilog-string-match-fold tpl-regexp inst)
11695 (match-string 1 inst)
11697 tpl-list (aref tpl-info 1)))
11698 ;; Find submodule's signals and dump
11699 (let ((sig-list (verilog-signals-not-in
11700 (verilog-decls-get-gparams submoddecls)
11702 (vl-dir "parameter"))
11704 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11705 ;; Note these are searched for in verilog-read-sub-decls.
11706 (verilog-insert-indent "// Parameters\n")
11707 (verilog-auto-inst-port-list sig-list indent-pt moddecls
11708 tpl-list tpl-num nil nil)))
11712 (re-search-backward "," pt t)
11715 (search-forward "\n") ; Added by inst-port
11717 (if (search-forward ")" nil t) ; From user, moved up a line
11718 (delete-char -1)))))))))
11720 (defun verilog-auto-reg ()
11721 "Expand AUTOREG statements, as part of \\[verilog-auto].
11722 Make reg statements for any output that isn't already declared,
11723 and isn't a wire output from a block. `verilog-auto-wire-type'
11724 may be used to change the datatype of the declarations.
11727 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
11729 This does NOT work on memories, declare those yourself.
11733 module ExampReg (o,i);
11740 Typing \\[verilog-auto] will make this into:
11742 module ExampReg (o,i);
11746 // Beginning of automatic regs (for this module's undeclared outputs)
11748 // End of automatics
11752 ;; Point must be at insertion point.
11753 (let* ((indent-pt (current-indentation))
11754 (modi (verilog-modi-current))
11755 (moddecls (verilog-modi-get-decls modi))
11756 (modsubdecls (verilog-modi-get-sub-decls modi))
11757 (sig-list (verilog-signals-not-in
11758 (verilog-decls-get-outputs moddecls)
11759 (append (verilog-signals-with ; ignore typed signals
11761 (verilog-decls-get-outputs moddecls))
11762 (verilog-decls-get-vars moddecls)
11763 (verilog-decls-get-assigns moddecls)
11764 (verilog-decls-get-consts moddecls)
11765 (verilog-decls-get-gparams moddecls)
11766 (verilog-subdecls-get-interfaced modsubdecls)
11767 (verilog-subdecls-get-outputs modsubdecls)
11768 (verilog-subdecls-get-inouts modsubdecls)))))
11770 (verilog-forward-or-insert-line)
11771 (verilog-insert-indent "// Beginning of automatic regs (for this module's undeclared outputs)\n")
11772 (verilog-insert-definition modi sig-list "reg" indent-pt nil)
11773 (verilog-insert-indent "// End of automatics\n")))))
11775 (defun verilog-auto-reg-input ()
11776 "Expand AUTOREGINPUT statements, as part of \\[verilog-auto].
11777 Make reg statements instantiation inputs that aren't already declared.
11778 This is useful for making a top level shell for testing the module that is
11779 to be instantiated.
11782 This ONLY detects inputs of AUTOINSTants (see `verilog-read-sub-decls').
11784 This does NOT work on memories, declare those yourself.
11786 An example (see `verilog-auto-inst' for what else is going on here):
11788 module ExampRegInput (o,i);
11792 InstModule instName
11796 Typing \\[verilog-auto] will make this into:
11798 module ExampRegInput (o,i);
11802 // Beginning of automatic reg inputs (for undeclared ...
11803 reg [31:0] iv; // From inst of inst.v
11804 // End of automatics
11805 InstModule instName
11813 ;; Point must be at insertion point.
11814 (let* ((indent-pt (current-indentation))
11815 (modi (verilog-modi-current))
11816 (moddecls (verilog-modi-get-decls modi))
11817 (modsubdecls (verilog-modi-get-sub-decls modi))
11818 (sig-list (verilog-signals-combine-bus
11819 (verilog-signals-not-in
11820 (append (verilog-subdecls-get-inputs modsubdecls)
11821 (verilog-subdecls-get-inouts modsubdecls))
11822 (append (verilog-decls-get-signals moddecls)
11823 (verilog-decls-get-assigns moddecls))))))
11825 (verilog-forward-or-insert-line)
11826 (verilog-insert-indent "// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)\n")
11827 (verilog-insert-definition modi sig-list "reg" indent-pt nil)
11828 (verilog-insert-indent "// End of automatics\n")))))
11830 (defun verilog-auto-logic-setup ()
11831 "Prepare variables due to AUTOLOGIC."
11832 (unless verilog-auto-wire-type
11833 (set (make-local-variable 'verilog-auto-wire-type)
11836 (defun verilog-auto-logic ()
11837 "Expand AUTOLOGIC statements, as part of \\[verilog-auto].
11838 Make wire statements using the SystemVerilog logic keyword.
11839 This is currently equivalent to:
11843 with the below at the bottom of the file
11845 // Local Variables:
11846 // verilog-auto-logic-type:\"logic\"
11849 In the future AUTOLOGIC may declare additional identifiers,
11850 while AUTOWIRE will not."
11852 (verilog-auto-logic-setup)
11853 (verilog-auto-wire)))
11855 (defun verilog-auto-wire ()
11856 "Expand AUTOWIRE statements, as part of \\[verilog-auto].
11857 Make wire statements for instantiations outputs that aren't
11858 already declared. `verilog-auto-wire-type' may be used to change
11859 the datatype of the declarations.
11862 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'),
11863 and all buses must have widths, such as those from AUTOINST, or using []
11866 This does NOT work on memories or SystemVerilog .name connections,
11867 declare those yourself.
11869 Verilog mode will add \"Couldn't Merge\" comments to signals it cannot
11870 determine how to bus together. This occurs when you have ports with
11871 non-numeric or non-sequential bus subscripts. If Verilog mode
11872 mis-guessed, you'll have to declare them yourself.
11874 An example (see `verilog-auto-inst' for what else is going on here):
11876 module ExampWire (o,i);
11880 InstModule instName
11884 Typing \\[verilog-auto] will make this into:
11886 module ExampWire (o,i);
11890 // Beginning of automatic wires
11891 wire [31:0] ov; // From inst of inst.v
11892 // End of automatics
11893 InstModule instName
11902 ;; Point must be at insertion point.
11903 (let* ((indent-pt (current-indentation))
11904 (modi (verilog-modi-current))
11905 (moddecls (verilog-modi-get-decls modi))
11906 (modsubdecls (verilog-modi-get-sub-decls modi))
11907 (sig-list (verilog-signals-combine-bus
11908 (verilog-signals-not-in
11909 (append (verilog-subdecls-get-outputs modsubdecls)
11910 (verilog-subdecls-get-inouts modsubdecls))
11911 (verilog-decls-get-signals moddecls)))))
11913 (verilog-forward-or-insert-line)
11914 (verilog-insert-indent "// Beginning of automatic wires (for undeclared instantiated-module outputs)\n")
11915 (verilog-insert-definition modi sig-list "wire" indent-pt nil)
11916 (verilog-insert-indent "// End of automatics\n")
11917 ;; We used to optionally call verilog-pretty-declarations and
11918 ;; verilog-pretty-expr here, but it's too slow on huge modules,
11919 ;; plus makes everyone's module change. Finally those call
11920 ;; syntax-ppss which is broken when change hooks are disabled.
11923 (defun verilog-auto-output ()
11924 "Expand AUTOOUTPUT statements, as part of \\[verilog-auto].
11925 Make output statements for any output signal from an /*AUTOINST*/ that
11926 isn't an input to another AUTOINST. This is useful for modules which
11927 only instantiate other modules.
11930 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
11932 If placed inside the parenthesis of a module declaration, it creates
11933 Verilog 2001 style, else uses Verilog 1995 style.
11935 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
11936 instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
11938 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
11940 Types are added to declarations if an AUTOLOGIC or
11941 `verilog-auto-wire-type' is set to logic.
11943 Signals matching `verilog-auto-output-ignore-regexp' are not included.
11945 An example (see `verilog-auto-inst' for what else is going on here):
11947 module ExampOutput (ov,i);
11950 InstModule instName
11954 Typing \\[verilog-auto] will make this into:
11956 module ExampOutput (ov,i);
11959 // Beginning of automatic outputs (from unused autoinst outputs)
11960 output [31:0] ov; // From inst of inst.v
11961 // End of automatics
11962 InstModule instName
11970 You may also provide an optional regular expression, in which case only
11971 signals matching the regular expression will be included. For example the
11972 same expansion will result from only extracting outputs starting with ov:
11974 /*AUTOOUTPUT(\"^ov\")*/"
11976 ;; Point must be at insertion point.
11977 (let* ((indent-pt (current-indentation))
11978 (params (verilog-read-auto-params 0 1))
11979 (regexp (nth 0 params))
11980 (v2k (verilog-in-paren-quick))
11981 (modi (verilog-modi-current))
11982 (moddecls (verilog-modi-get-decls modi))
11983 (modsubdecls (verilog-modi-get-sub-decls modi))
11984 (sig-list (verilog-signals-not-in
11985 (verilog-subdecls-get-outputs modsubdecls)
11986 (append (verilog-decls-get-outputs moddecls)
11987 (verilog-decls-get-inouts moddecls)
11988 (verilog-decls-get-inputs moddecls)
11989 (verilog-subdecls-get-inputs modsubdecls)
11990 (verilog-subdecls-get-inouts modsubdecls)))))
11992 (setq sig-list (verilog-signals-matching-regexp
11994 (setq sig-list (verilog-signals-not-matching-regexp
11995 sig-list verilog-auto-output-ignore-regexp))
11996 (verilog-forward-or-insert-line)
11997 (when v2k (verilog-repair-open-comma))
11999 (verilog-insert-indent "// Beginning of automatic outputs (from unused autoinst outputs)\n")
12000 (verilog-insert-definition modi sig-list "output" indent-pt v2k)
12001 (verilog-insert-indent "// End of automatics\n"))
12002 (when v2k (verilog-repair-close-comma)))))
12004 (defun verilog-auto-output-every ()
12005 "Expand AUTOOUTPUTEVERY statements, as part of \\[verilog-auto].
12006 Make output statements for any signals that aren't primary inputs or
12007 outputs already. This makes every signal in the design an output. This is
12008 useful to get Synopsys to preserve every signal in the design, since it
12009 won't optimize away the outputs.
12013 module ExampOutputEvery (o,i,tempa,tempb);
12016 /*AUTOOUTPUTEVERY*/
12018 wire tempb = tempa;
12022 Typing \\[verilog-auto] will make this into:
12024 module ExampOutputEvery (o,i,tempa,tempb);
12027 /*AUTOOUTPUTEVERY*/
12028 // Beginning of automatic outputs (every signal)
12031 // End of automatics
12033 wire tempb = tempa;
12037 You may also provide an optional regular expression, in which case only
12038 signals matching the regular expression will be included. For example the
12039 same expansion will result from only extracting outputs starting with ov:
12041 /*AUTOOUTPUTEVERY(\"^ov\")*/"
12043 ;;Point must be at insertion point
12044 (let* ((indent-pt (current-indentation))
12045 (params (verilog-read-auto-params 0 1))
12046 (regexp (nth 0 params))
12047 (v2k (verilog-in-paren-quick))
12048 (modi (verilog-modi-current))
12049 (moddecls (verilog-modi-get-decls modi))
12050 (sig-list (verilog-signals-combine-bus
12051 (verilog-signals-not-in
12052 (verilog-decls-get-signals moddecls)
12053 (verilog-decls-get-ports moddecls)))))
12055 (setq sig-list (verilog-signals-matching-regexp
12057 (setq sig-list (verilog-signals-not-matching-regexp
12058 sig-list verilog-auto-output-ignore-regexp))
12059 (verilog-forward-or-insert-line)
12060 (when v2k (verilog-repair-open-comma))
12062 (verilog-insert-indent "// Beginning of automatic outputs (every signal)\n")
12063 (verilog-insert-definition modi sig-list "output" indent-pt v2k)
12064 (verilog-insert-indent "// End of automatics\n"))
12065 (when v2k (verilog-repair-close-comma)))))
12067 (defun verilog-auto-input ()
12068 "Expand AUTOINPUT statements, as part of \\[verilog-auto].
12069 Make input statements for any input signal into an /*AUTOINST*/ that
12070 isn't declared elsewhere inside the module. This is useful for modules which
12071 only instantiate other modules.
12074 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
12076 If placed inside the parenthesis of a module declaration, it creates
12077 Verilog 2001 style, else uses Verilog 1995 style.
12079 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
12080 instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
12082 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
12084 Types are added to declarations if an AUTOLOGIC or
12085 `verilog-auto-wire-type' is set to logic.
12087 Signals matching `verilog-auto-input-ignore-regexp' are not included.
12089 An example (see `verilog-auto-inst' for what else is going on here):
12091 module ExampInput (ov,i);
12094 InstModule instName
12098 Typing \\[verilog-auto] will make this into:
12100 module ExampInput (ov,i);
12103 // Beginning of automatic inputs (from unused autoinst inputs)
12104 input i; // From inst of inst.v
12105 // End of automatics
12106 InstModule instName
12114 You may also provide an optional regular expression, in which case only
12115 signals matching the regular expression will be included. For example the
12116 same expansion will result from only extracting inputs starting with i:
12118 /*AUTOINPUT(\"^i\")*/"
12120 (let* ((indent-pt (current-indentation))
12121 (params (verilog-read-auto-params 0 1))
12122 (regexp (nth 0 params))
12123 (v2k (verilog-in-paren-quick))
12124 (modi (verilog-modi-current))
12125 (moddecls (verilog-modi-get-decls modi))
12126 (modsubdecls (verilog-modi-get-sub-decls modi))
12127 (sig-list (verilog-signals-not-in
12128 (verilog-subdecls-get-inputs modsubdecls)
12129 (append (verilog-decls-get-inputs moddecls)
12130 (verilog-decls-get-inouts moddecls)
12131 (verilog-decls-get-outputs moddecls)
12132 (verilog-decls-get-vars moddecls)
12133 (verilog-decls-get-consts moddecls)
12134 (verilog-decls-get-gparams moddecls)
12135 (verilog-subdecls-get-interfaced modsubdecls)
12136 (verilog-subdecls-get-outputs modsubdecls)
12137 (verilog-subdecls-get-inouts modsubdecls)))))
12139 (setq sig-list (verilog-signals-matching-regexp
12141 (setq sig-list (verilog-signals-not-matching-regexp
12142 sig-list verilog-auto-input-ignore-regexp))
12143 (verilog-forward-or-insert-line)
12144 (when v2k (verilog-repair-open-comma))
12146 (verilog-insert-indent "// Beginning of automatic inputs (from unused autoinst inputs)\n")
12147 (verilog-insert-definition modi sig-list "input" indent-pt v2k)
12148 (verilog-insert-indent "// End of automatics\n"))
12149 (when v2k (verilog-repair-close-comma)))))
12151 (defun verilog-auto-inout ()
12152 "Expand AUTOINOUT statements, as part of \\[verilog-auto].
12153 Make inout statements for any inout signal in an /*AUTOINST*/ that
12154 isn't declared elsewhere inside the module.
12157 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
12159 If placed inside the parenthesis of a module declaration, it creates
12160 Verilog 2001 style, else uses Verilog 1995 style.
12162 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
12163 instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
12165 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
12167 Types are added to declarations if an AUTOLOGIC or
12168 `verilog-auto-wire-type' is set to logic.
12170 Signals matching `verilog-auto-inout-ignore-regexp' are not included.
12172 An example (see `verilog-auto-inst' for what else is going on here):
12174 module ExampInout (ov,i);
12177 InstModule instName
12181 Typing \\[verilog-auto] will make this into:
12183 module ExampInout (ov,i);
12186 // Beginning of automatic inouts (from unused autoinst inouts)
12187 inout [31:0] ov; // From inst of inst.v
12188 // End of automatics
12189 InstModule instName
12197 You may also provide an optional regular expression, in which case only
12198 signals matching the regular expression will be included. For example the
12199 same expansion will result from only extracting inouts starting with i:
12201 /*AUTOINOUT(\"^i\")*/"
12203 ;; Point must be at insertion point.
12204 (let* ((indent-pt (current-indentation))
12205 (params (verilog-read-auto-params 0 1))
12206 (regexp (nth 0 params))
12207 (v2k (verilog-in-paren-quick))
12208 (modi (verilog-modi-current))
12209 (moddecls (verilog-modi-get-decls modi))
12210 (modsubdecls (verilog-modi-get-sub-decls modi))
12211 (sig-list (verilog-signals-not-in
12212 (verilog-subdecls-get-inouts modsubdecls)
12213 (append (verilog-decls-get-outputs moddecls)
12214 (verilog-decls-get-inouts moddecls)
12215 (verilog-decls-get-inputs moddecls)
12216 (verilog-subdecls-get-inputs modsubdecls)
12217 (verilog-subdecls-get-outputs modsubdecls)))))
12219 (setq sig-list (verilog-signals-matching-regexp
12221 (setq sig-list (verilog-signals-not-matching-regexp
12222 sig-list verilog-auto-inout-ignore-regexp))
12223 (verilog-forward-or-insert-line)
12224 (when v2k (verilog-repair-open-comma))
12226 (verilog-insert-indent "// Beginning of automatic inouts (from unused autoinst inouts)\n")
12227 (verilog-insert-definition modi sig-list "inout" indent-pt v2k)
12228 (verilog-insert-indent "// End of automatics\n"))
12229 (when v2k (verilog-repair-close-comma)))))
12231 (defun verilog-auto-inout-module (&optional complement all-in)
12232 "Expand AUTOINOUTMODULE statements, as part of \\[verilog-auto].
12233 Take input/output/inout statements from the specified module and insert
12234 into the current module. This is useful for making null templates and
12235 shell modules which need to have identical I/O with another module.
12236 Any I/O which are already defined in this module will not be redefined.
12237 For the complement of this function, see `verilog-auto-inout-comp',
12238 and to make monitors with all inputs, see `verilog-auto-inout-in'.
12241 If placed inside the parenthesis of a module declaration, it creates
12242 Verilog 2001 style, else uses Verilog 1995 style.
12244 Concatenation and outputting partial buses is not supported.
12246 Module names must be resolvable to filenames. See `verilog-auto-inst'.
12248 Signals are not inserted in the same order as in the original module,
12249 though they will appear to be in the same order to an AUTOINST
12250 instantiating either module.
12252 Signals declared as \"output reg\" or \"output wire\" etc will
12253 lose the wire/reg declaration so that shell modules may
12254 generate those outputs differently. However, \"output logic\"
12259 module ExampShell (/*AUTOARG*/);
12260 /*AUTOINOUTMODULE(\"ExampMain\")*/
12263 module ExampMain (i,o,io);
12269 Typing \\[verilog-auto] will make this into:
12271 module ExampShell (/*AUTOARG*/i,o,io);
12272 /*AUTOINOUTMODULE(\"ExampMain\")*/
12273 // Beginning of automatic in/out/inouts (from specific module)
12277 // End of automatics
12280 You may also provide an optional regular expression, in which case only
12281 signals matching the regular expression will be included. For example the
12282 same expansion will result from only extracting signals starting with i:
12284 /*AUTOINOUTMODULE(\"ExampMain\",\"^i\")*/
12286 You may also provide an optional third argument regular
12287 expression, in which case only signals which have that pin
12288 direction and data type matching that regular expression will be
12289 included. This matches against everything before the signal name
12290 in the declaration, for example against \"input\" (single
12291 bit), \"output logic\" (direction and type) or
12292 \"output [1:0]\" (direction and implicit type). You also
12293 probably want to skip spaces in your regexp.
12295 For example, the below will result in matching the output \"o\"
12296 against the previous example's module:
12298 /*AUTOINOUTMODULE(\"ExampMain\",\"\",\"^output.*\")*/
12300 You may also provide an optional fourth argument regular
12301 expression, which if not \"\" only signals which do NOT match
12302 that expression are included."
12303 ;; Beware spacing of quotes in above as can mess up Emacs indenter
12305 (let* ((params (verilog-read-auto-params 1 4))
12306 (submod (nth 0 params))
12307 (regexp (nth 1 params))
12308 (direction-re (nth 2 params))
12309 (not-re (nth 3 params))
12311 ;; Lookup position, etc of co-module
12312 ;; Note this may raise an error
12313 (when (setq submodi (verilog-modi-lookup submod t))
12314 (let* ((indent-pt (current-indentation))
12315 (v2k (verilog-in-paren-quick))
12316 (modi (verilog-modi-current))
12317 (moddecls (verilog-modi-get-decls modi))
12318 (submoddecls (verilog-modi-get-decls submodi))
12319 (sig-list-i (verilog-signals-not-in
12322 (verilog-decls-get-inputs submoddecls)
12323 (verilog-decls-get-inouts submoddecls)
12324 (verilog-decls-get-outputs submoddecls)))
12326 (verilog-decls-get-outputs submoddecls))
12327 (t (verilog-decls-get-inputs submoddecls)))
12328 (append (verilog-decls-get-inputs moddecls))))
12329 (sig-list-o (verilog-signals-not-in
12332 (verilog-decls-get-inputs submoddecls))
12333 (t (verilog-decls-get-outputs submoddecls)))
12334 (append (verilog-decls-get-outputs moddecls))))
12335 (sig-list-io (verilog-signals-not-in
12337 (t (verilog-decls-get-inouts submoddecls)))
12338 (append (verilog-decls-get-inouts moddecls))))
12339 (sig-list-if (verilog-signals-not-in
12340 (verilog-decls-get-interfaces submoddecls)
12341 (append (verilog-decls-get-interfaces moddecls)))))
12343 (setq sig-list-i (verilog-signals-edit-wire-reg
12344 (verilog-signals-not-matching-regexp
12345 (verilog-signals-matching-dir-re
12346 (verilog-signals-matching-regexp sig-list-i regexp)
12347 "input" direction-re) not-re))
12348 sig-list-o (verilog-signals-edit-wire-reg
12349 (verilog-signals-not-matching-regexp
12350 (verilog-signals-matching-dir-re
12351 (verilog-signals-matching-regexp sig-list-o regexp)
12352 "output" direction-re) not-re))
12353 sig-list-io (verilog-signals-edit-wire-reg
12354 (verilog-signals-not-matching-regexp
12355 (verilog-signals-matching-dir-re
12356 (verilog-signals-matching-regexp sig-list-io regexp)
12357 "inout" direction-re) not-re))
12358 sig-list-if (verilog-signals-not-matching-regexp
12359 (verilog-signals-matching-dir-re
12360 (verilog-signals-matching-regexp sig-list-if regexp)
12361 "interface" direction-re) not-re))
12362 (when v2k (verilog-repair-open-comma))
12363 (when (or sig-list-i sig-list-o sig-list-io sig-list-if)
12364 (verilog-insert-indent "// Beginning of automatic in/out/inouts (from specific module)\n")
12365 ;; Don't sort them so an upper AUTOINST will match the main module
12366 (verilog-insert-definition modi sig-list-o "output" indent-pt v2k t)
12367 (verilog-insert-definition modi sig-list-io "inout" indent-pt v2k t)
12368 (verilog-insert-definition modi sig-list-i "input" indent-pt v2k t)
12369 (verilog-insert-definition modi sig-list-if "interface" indent-pt v2k t)
12370 (verilog-insert-indent "// End of automatics\n"))
12371 (when v2k (verilog-repair-close-comma)))))))
12373 (defun verilog-auto-inout-comp ()
12374 "Expand AUTOINOUTCOMP statements, as part of \\[verilog-auto].
12375 Take input/output/inout statements from the specified module and
12376 insert the inverse into the current module (inputs become outputs
12377 and vice-versa.) This is useful for making test and stimulus
12378 modules which need to have complementing I/O with another module.
12379 Any I/O which are already defined in this module will not be
12380 redefined. For the complement of this function, see
12381 `verilog-auto-inout-module'.
12384 If placed inside the parenthesis of a module declaration, it creates
12385 Verilog 2001 style, else uses Verilog 1995 style.
12387 Concatenation and outputting partial buses is not supported.
12389 Module names must be resolvable to filenames. See `verilog-auto-inst'.
12391 Signals are not inserted in the same order as in the original module,
12392 though they will appear to be in the same order to an AUTOINST
12393 instantiating either module.
12397 module ExampShell (/*AUTOARG*/);
12398 /*AUTOINOUTCOMP(\"ExampMain\")*/
12401 module ExampMain (i,o,io);
12407 Typing \\[verilog-auto] will make this into:
12409 module ExampShell (/*AUTOARG*/i,o,io);
12410 /*AUTOINOUTCOMP(\"ExampMain\")*/
12411 // Beginning of automatic in/out/inouts (from specific module)
12415 // End of automatics
12418 You may also provide an optional regular expression, in which case only
12419 signals matching the regular expression will be included. For example the
12420 same expansion will result from only extracting signals starting with i:
12422 /*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/
12424 You may also provide an optional third argument regular
12425 expression, in which case only signals which have that pin
12426 direction and data type matching that regular expression will be
12427 included. This matches against everything before the signal name
12428 in the declaration, for example against \"input\" (single
12429 bit), \"output logic\" (direction and type)
12430 or \"output [1:0]\" (direction and implicit type). You also
12431 probably want to skip spaces in your regexp.
12433 For example, the below will result in matching the output \"o\"
12434 against the previous example's module:
12436 /*AUTOINOUTCOMP(\"ExampMain\",\"\",\"^output.*\")*/
12438 You may also provide an optional fourth argument regular
12439 expression, which if not \"\" only signals which do NOT match
12440 that expression are included."
12441 ;; Beware spacing of quotes in above as can mess up Emacs indenter
12442 (verilog-auto-inout-module t nil))
12444 (defun verilog-auto-inout-in ()
12445 "Expand AUTOINOUTIN statements, as part of \\[verilog-auto].
12446 Take input/output/inout statements from the specified module and
12447 insert them as all inputs into the current module. This is
12448 useful for making monitor modules which need to see all signals
12449 as inputs based on another module. Any I/O which are already
12450 defined in this module will not be redefined. See also
12451 `verilog-auto-inout-module'.
12454 If placed inside the parenthesis of a module declaration, it creates
12455 Verilog 2001 style, else uses Verilog 1995 style.
12457 Concatenation and outputting partial buses is not supported.
12459 Module names must be resolvable to filenames. See `verilog-auto-inst'.
12461 Signals are not inserted in the same order as in the original module,
12462 though they will appear to be in the same order to an AUTOINST
12463 instantiating either module.
12467 module ExampShell (/*AUTOARG*/);
12468 /*AUTOINOUTIN(\"ExampMain\")*/
12471 module ExampMain (i,o,io);
12477 Typing \\[verilog-auto] will make this into:
12479 module ExampShell (/*AUTOARG*/i,o,io);
12480 /*AUTOINOUTIN(\"ExampMain\")*/
12481 // Beginning of automatic in/out/inouts (from specific module)
12485 // End of automatics
12488 You may also provide an optional regular expression, in which case only
12489 signals matching the regular expression will be included. For example the
12490 same expansion will result from only extracting signals starting with i:
12492 /*AUTOINOUTIN(\"ExampMain\",\"^i\")*/"
12493 (verilog-auto-inout-module nil t))
12495 (defun verilog-auto-inout-param ()
12496 "Expand AUTOINOUTPARAM statements, as part of \\[verilog-auto].
12497 Take input/output/inout statements from the specified module and insert
12498 into the current module. This is useful for making null templates and
12499 shell modules which need to have identical I/O with another module.
12500 Any I/O which are already defined in this module will not be redefined.
12501 For the complement of this function, see `verilog-auto-inout-comp',
12502 and to make monitors with all inputs, see `verilog-auto-inout-in'.
12505 If placed inside the parenthesis of a module declaration, it creates
12506 Verilog 2001 style, else uses Verilog 1995 style.
12508 Module names must be resolvable to filenames. See `verilog-auto-inst'.
12510 Parameters are inserted in the same order as in the original module.
12512 Parameters do not have values, which is SystemVerilog 2009 syntax.
12516 module ExampShell ();
12517 /*AUTOINOUTPARAM(\"ExampMain\")*/
12520 module ExampMain ();
12521 parameter PARAM = 22;
12524 Typing \\[verilog-auto] will make this into:
12526 module ExampShell (/*AUTOARG*/i,o,io);
12527 /*AUTOINOUTPARAM(\"ExampMain\")*/
12528 // Beginning of automatic parameters (from specific module)
12530 // End of automatics
12533 You may also provide an optional regular expression, in which case only
12534 parameters matching the regular expression will be included. For example the
12535 same expansion will result from only extracting parameters starting with i:
12537 /*AUTOINOUTPARAM(\"ExampMain\",\"^i\")*/"
12539 (let* ((params (verilog-read-auto-params 1 2))
12540 (submod (nth 0 params))
12541 (regexp (nth 1 params))
12543 ;; Lookup position, etc of co-module
12544 ;; Note this may raise an error
12545 (when (setq submodi (verilog-modi-lookup submod t))
12546 (let* ((indent-pt (current-indentation))
12547 (v2k (verilog-in-paren-quick))
12548 (modi (verilog-modi-current))
12549 (moddecls (verilog-modi-get-decls modi))
12550 (submoddecls (verilog-modi-get-decls submodi))
12551 (sig-list-p (verilog-signals-not-in
12552 (verilog-decls-get-gparams submoddecls)
12553 (append (verilog-decls-get-gparams moddecls)))))
12555 (setq sig-list-p (verilog-signals-matching-regexp sig-list-p regexp))
12556 (when v2k (verilog-repair-open-comma))
12558 (verilog-insert-indent "// Beginning of automatic parameters (from specific module)\n")
12559 ;; Don't sort them so an upper AUTOINST will match the main module
12560 (verilog-insert-definition modi sig-list-p "parameter" indent-pt v2k t)
12561 (verilog-insert-indent "// End of automatics\n"))
12562 (when v2k (verilog-repair-close-comma)))))))
12564 (defun verilog-auto-inout-modport ()
12565 "Expand AUTOINOUTMODPORT statements, as part of \\[verilog-auto].
12566 Take input/output/inout statements from the specified interface
12567 and modport and insert into the current module. This is useful
12568 for making verification modules that connect to UVM interfaces.
12570 The first parameter is the name of an interface.
12572 The second parameter is a regexp of modports to read from in
12575 The optional third parameter is a regular expression, and only
12576 signals matching the regular expression will be included.
12579 If placed inside the parenthesis of a module declaration, it creates
12580 Verilog 2001 style, else uses Verilog 1995 style.
12582 Interface names must be resolvable to filenames. See `verilog-auto-inst'.
12584 As with other autos, any inputs/outputs declared in the module
12585 will suppress the AUTO from redeclaring an inputs/outputs by
12591 ( input logic clk );
12593 logic [7:0] req_dat;
12594 clocking mon_clkblk @(posedge clk);
12598 modport mp(clocking mon_clkblk);
12603 /*AUTOINOUTMODPORT(\"ExampIf\" \"mp\")*/
12604 // Beginning of automatic in/out/inouts (from modport)
12605 input [7:0] req_dat,
12607 // End of automatics
12609 /*AUTOASSIGNMODPORT(\"ExampIf\" \"mp\")*/
12612 Typing \\[verilog-auto] will make this into:
12617 /*AUTOINOUTMODPORT(\"ExampIf\" \"mp\")*/
12618 // Beginning of automatic in/out/inouts (from modport)
12621 // End of automatics
12624 If the modport is part of a UVM monitor/driver class, this
12625 creates a wrapper module that may be used to instantiate the
12626 driver/monitor using AUTOINST in the testbench."
12628 (let* ((params (verilog-read-auto-params 2 3))
12629 (submod (nth 0 params))
12630 (modport-re (nth 1 params))
12631 (regexp (nth 2 params))
12632 direction-re submodi) ; direction argument not supported until requested
12633 ;; Lookup position, etc of co-module
12634 ;; Note this may raise an error
12635 (when (setq submodi (verilog-modi-lookup submod t))
12636 (let* ((indent-pt (current-indentation))
12637 (v2k (verilog-in-paren-quick))
12638 (modi (verilog-modi-current))
12639 (moddecls (verilog-modi-get-decls modi))
12640 (submoddecls (verilog-modi-get-decls submodi))
12641 (submodportdecls (verilog-modi-modport-lookup submodi modport-re))
12642 (sig-list-i (verilog-signals-in ; Decls doesn't have data types, must resolve
12643 (verilog-decls-get-vars submoddecls)
12644 (verilog-signals-not-in
12645 (verilog-decls-get-inputs submodportdecls)
12646 (append (verilog-decls-get-ports submoddecls)
12647 (verilog-decls-get-ports moddecls)))))
12648 (sig-list-o (verilog-signals-in ; Decls doesn't have data types, must resolve
12649 (verilog-decls-get-vars submoddecls)
12650 (verilog-signals-not-in
12651 (verilog-decls-get-outputs submodportdecls)
12652 (append (verilog-decls-get-ports submoddecls)
12653 (verilog-decls-get-ports moddecls)))))
12654 (sig-list-io (verilog-signals-in ; Decls doesn't have data types, must resolve
12655 (verilog-decls-get-vars submoddecls)
12656 (verilog-signals-not-in
12657 (verilog-decls-get-inouts submodportdecls)
12658 (append (verilog-decls-get-ports submoddecls)
12659 (verilog-decls-get-ports moddecls))))))
12661 (setq sig-list-i (verilog-signals-edit-wire-reg
12662 (verilog-signals-matching-dir-re
12663 (verilog-signals-matching-regexp sig-list-i regexp)
12664 "input" direction-re))
12665 sig-list-o (verilog-signals-edit-wire-reg
12666 (verilog-signals-matching-dir-re
12667 (verilog-signals-matching-regexp sig-list-o regexp)
12668 "output" direction-re))
12669 sig-list-io (verilog-signals-edit-wire-reg
12670 (verilog-signals-matching-dir-re
12671 (verilog-signals-matching-regexp sig-list-io regexp)
12672 "inout" direction-re)))
12673 (when v2k (verilog-repair-open-comma))
12674 (when (or sig-list-i sig-list-o sig-list-io)
12675 (verilog-insert-indent "// Beginning of automatic in/out/inouts (from modport)\n")
12676 ;; Don't sort them so an upper AUTOINST will match the main module
12677 (verilog-insert-definition modi sig-list-o "output" indent-pt v2k t)
12678 (verilog-insert-definition modi sig-list-io "inout" indent-pt v2k t)
12679 (verilog-insert-definition modi sig-list-i "input" indent-pt v2k t)
12680 (verilog-insert-indent "// End of automatics\n"))
12681 (when v2k (verilog-repair-close-comma)))))))
12683 (defun verilog-auto-insert-lisp ()
12684 "Expand AUTOINSERTLISP statements, as part of \\[verilog-auto].
12685 The Lisp code provided is called before other AUTOS are expanded,
12686 and the Lisp code generally will call `insert' to insert text
12687 into the current file beginning on the line after the
12690 See also AUTOINSERTLAST and `verilog-auto-insert-last' which
12691 executes after (as opposed to before) other AUTOs.
12693 See also AUTO_LISP, which takes a Lisp expression and evaluates
12694 it during `verilog-auto-inst' but does not insert any text.
12698 module ExampInsertLisp;
12699 /*AUTOINSERTLISP(my-verilog-insert-hello \"world\")*/
12702 // For this example we declare the function in the
12703 // module's file itself. Often you'd define it instead
12704 // in a site-start.el or init file.
12708 (defun my-verilog-insert-hello (who)
12709 (insert (concat \"initial $write(\\\"hello \" who \"\\\");\\n\")))
12713 Typing \\[verilog-auto] will call my-verilog-insert-hello and
12714 expand the above into:
12716 // Beginning of automatic insert lisp
12717 initial $write(\"hello world\");
12718 // End of automatics
12720 You can also call an external program and insert the returned
12723 /*AUTOINSERTLISP(insert (shell-command-to-string \"echo //hello\"))*/
12724 // Beginning of automatic insert lisp
12726 // End of automatics"
12728 ;; Point is at end of /*AUTO...*/
12729 (let* ((indent-pt (current-indentation))
12730 (cmd-end-pt (save-excursion (search-backward ")")
12732 (point))) ; Closing paren
12733 (cmd-beg-pt (save-excursion (goto-char cmd-end-pt)
12734 (backward-sexp 1) ; Inside comment
12735 (point))) ; Beginning paren
12736 (cmd (buffer-substring-no-properties cmd-beg-pt cmd-end-pt)))
12737 (verilog-forward-or-insert-line)
12738 ;; Some commands don't move point (like insert-file) so we always
12739 ;; add the begin/end comments, then delete it if not needed
12740 (verilog-insert-indent "// Beginning of automatic insert lisp\n")
12741 (verilog-insert-indent "// End of automatics\n")
12745 (setq verilog-scan-cache-tick nil) ; Clear cache; inserted unknown text
12746 (verilog-delete-empty-auto-pair))))
12748 (defun verilog-auto-insert-last ()
12749 "Expand AUTOINSERTLAST statements, as part of \\[verilog-auto].
12750 The Lisp code provided is called after all other AUTOS have been
12751 expanded, and the Lisp code generally will call `insert' to
12752 insert text into the current file beginning on the line after the
12755 Other than when called (after AUTOs are expanded), the functionality
12756 is otherwise identical to AUTOINSERTLISP and `verilog-auto-insert-lisp' which
12757 executes before (as opposed to after) other AUTOs.
12759 See `verilog-auto-insert-lisp' for examples."
12760 (verilog-auto-insert-lisp))
12762 (defun verilog-auto-sense-sigs (moddecls presense-sigs)
12763 "Return list of signals for current AUTOSENSE block."
12764 (let* ((sigss (save-excursion
12765 (search-forward ")")
12766 (verilog-read-always-signals)))
12767 (sig-list (verilog-signals-not-params
12768 (verilog-signals-not-in (verilog-alw-get-inputs sigss)
12769 (append (and (not verilog-auto-sense-include-inputs)
12770 (verilog-alw-get-outputs-delayed sigss))
12771 (and (not verilog-auto-sense-include-inputs)
12772 (verilog-alw-get-outputs-immediate sigss))
12773 (verilog-alw-get-temps sigss)
12774 (verilog-decls-get-consts moddecls)
12775 (verilog-decls-get-gparams moddecls)
12779 (defun verilog-auto-sense ()
12780 "Expand AUTOSENSE statements, as part of \\[verilog-auto].
12781 Replace the always (/*AUTOSENSE*/) sensitivity list (/*AS*/ for short)
12782 with one automatically derived from all inputs declared in the always
12783 statement. Signals that are generated within the same always block are NOT
12784 placed into the sensitivity list (see `verilog-auto-sense-include-inputs').
12785 Long lines are split based on the `fill-column', see \\[set-fill-column].
12788 Verilog does not allow memories (multidimensional arrays) in sensitivity
12789 lists. AUTOSENSE will thus exclude them, and add a /*memory or*/ comment.
12792 AUTOSENSE cannot always determine if a \\=`define is a constant or a signal
12793 (it could be in an include file for example). If a \\=`define or other signal
12794 is put into the AUTOSENSE list and is not desired, use the AUTO_CONSTANT
12795 declaration anywhere in the module (parenthesis are required):
12797 /* AUTO_CONSTANT ( `this_is_really_constant_dont_autosense_it ) */
12799 Better yet, use a parameter, which will be understood to be constant
12803 If AUTOSENSE makes a mistake, please report it. (First try putting
12804 a begin/end after your always!) As a workaround, if a signal that
12805 shouldn't be in the sensitivity list was, use the AUTO_CONSTANT above.
12806 If a signal should be in the sensitivity list wasn't, placing it before
12807 the /*AUTOSENSE*/ comment will prevent it from being deleted when the
12808 autos are updated (or added if it occurs there already).
12812 always @ (/*AS*/) begin
12813 /* AUTO_CONSTANT (`constant) */
12814 outin = ina | inb | `constant;
12818 Typing \\[verilog-auto] will make this into:
12820 always @ (/*AS*/ina or inb) begin
12821 /* AUTO_CONSTANT (`constant) */
12822 outin = ina | inb | `constant;
12826 Note in Verilog 2001, you can often get the same result from the new @*
12827 operator. (This was added to the language in part due to AUTOSENSE!)
12830 outin = ina | inb | `constant;
12835 (let* ((start-pt (save-excursion
12836 (verilog-re-search-backward-quick "(" nil t)
12838 (indent-pt (save-excursion
12839 (or (and (goto-char start-pt) (1+ (current-column)))
12840 (current-indentation))))
12841 (modi (verilog-modi-current))
12842 (moddecls (verilog-modi-get-decls modi))
12843 (sig-memories (verilog-signals-memory
12844 (verilog-decls-get-vars moddecls)))
12845 sig-list not-first presense-sigs)
12846 ;; Read signals in always, eliminate outputs from sense list
12847 (setq presense-sigs (verilog-signals-from-signame
12849 (verilog-read-signals start-pt (point)))))
12850 (setq sig-list (verilog-auto-sense-sigs moddecls presense-sigs))
12852 (let ((tlen (length sig-list)))
12853 (setq sig-list (verilog-signals-not-in sig-list sig-memories))
12854 (if (not (eq tlen (length sig-list))) (verilog-insert " /*memory or*/ "))))
12855 (if (and presense-sigs ; Add a "or" if not "(.... or /*AUTOSENSE*/"
12856 (save-excursion (goto-char (point))
12857 (verilog-re-search-backward-quick "[a-zA-Z0-9$_.%`]+" start-pt t)
12858 (verilog-re-search-backward-quick "\\s-" start-pt t)
12859 (while (looking-at "\\s-`endif")
12860 (verilog-re-search-backward-quick "[a-zA-Z0-9$_.%`]+" start-pt t)
12861 (verilog-re-search-backward-quick "\\s-" start-pt t))
12862 (not (looking-at "\\s-or\\b"))))
12863 (setq not-first t))
12864 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
12866 (cond ((> (+ 4 (current-column) (length (verilog-sig-name (car sig-list)))) fill-column) ;+4 for width of or
12868 (indent-to indent-pt)
12869 (if not-first (insert "or ")))
12870 (not-first (insert " or ")))
12871 (insert (verilog-sig-name (car sig-list)))
12872 (setq sig-list (cdr sig-list)
12875 (defun verilog-auto-reset ()
12876 "Expand AUTORESET statements, as part of \\[verilog-auto].
12877 Replace the /*AUTORESET*/ comment with code to initialize all
12878 registers set elsewhere in the always block.
12881 AUTORESET will not clear memories.
12883 AUTORESET uses <= if the signal has a <= assignment in the block,
12886 If <= is used, all = assigned variables are ignored if
12887 `verilog-auto-reset-blocking-in-non' is nil; they are presumed
12890 /*AUTORESET*/ presumes that any signals mentioned between the previous
12891 begin/case/if statement and the AUTORESET comment are being reset manually
12892 and should not be automatically reset. This includes omitting any signals
12893 used on the right hand side of assignments.
12895 By default, AUTORESET will include the width of the signal in the
12896 autos, SystemVerilog designs may want to change this. To control
12897 this behavior, see `verilog-auto-reset-widths'. In some cases
12898 AUTORESET must use a '0 assignment and it will print NOWIDTH; use
12899 `verilog-auto-reset-widths' unbased to prevent this.
12901 AUTORESET ties signals to deasserted, which is presumed to be zero.
12902 Signals that match `verilog-active-low-regexp' will be deasserted by tying
12905 AUTORESET may try to reset arrays or structures that cannot be
12906 reset by a simple assignment, resulting in compile errors. This
12907 is a feature to be taken as a hint that you need to reset these
12908 signals manually (or put them into a \"\\=`ifdef NEVER signal<=\\=`0;
12909 \\=`endif\" so Verilog-Mode ignores them.)
12913 always @(posedge clk or negedge reset_l) begin
12914 if (!reset_l) begin
12925 Typing \\[verilog-auto] will make this into:
12927 always @(posedge core_clk or negedge reset_l) begin
12928 if (!reset_l) begin
12931 // Beginning of autoreset for uninitialized flops
12933 b = 0; // if `verilog-auto-reset-blocking-in-non' true
12934 // End of automatics
12946 (let* ((indent-pt (current-indentation))
12947 (modi (verilog-modi-current))
12948 (moddecls (verilog-modi-get-decls modi))
12949 (all-list (verilog-decls-get-signals moddecls))
12950 sigss sig-list dly-list prereset-sigs)
12951 ;; Read signals in always, eliminate outputs from reset list
12952 (setq prereset-sigs (verilog-signals-from-signame
12954 (verilog-read-signals
12956 (verilog-re-search-backward-quick
12957 "\\(@\\|\\<\\(begin\\|if\\|case\\|always\\(_latch\\|_ff\\|_comb\\)?\\)\\>\\)" nil t)
12961 (verilog-re-search-backward-quick "\\(@\\|\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\)\\>\\)" nil t)
12962 (setq sigss (verilog-read-always-signals)))
12963 (setq dly-list (verilog-alw-get-outputs-delayed sigss))
12964 (setq sig-list (verilog-signals-not-in-struct
12966 (verilog-alw-get-outputs-delayed sigss)
12967 (when (or (not (verilog-alw-get-uses-delayed sigss))
12968 verilog-auto-reset-blocking-in-non)
12969 (verilog-alw-get-outputs-immediate sigss)))
12971 (verilog-alw-get-temps sigss)
12973 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
12976 (verilog-insert-indent "// Beginning of autoreset for uninitialized flops\n");
12978 (let ((sig (or (assoc (verilog-sig-name (car sig-list)) all-list) ; As sig-list has no widths
12980 (indent-to indent-pt)
12981 (insert (verilog-sig-name sig)
12982 (if (assoc (verilog-sig-name sig) dly-list)
12983 (concat " <= " verilog-assignment-delay)
12985 (verilog-sig-tieoff sig)
12987 (setq sig-list (cdr sig-list))))
12988 (verilog-insert-indent "// End of automatics")))))
12990 (defun verilog-auto-tieoff ()
12991 "Expand AUTOTIEOFF statements, as part of \\[verilog-auto].
12992 Replace the /*AUTOTIEOFF*/ comment with code to wire-tie all unused output
12993 signals to deasserted.
12995 /*AUTOTIEOFF*/ is used to make stub modules; modules that have the same
12996 input/output list as another module, but no internals. Specifically, it
12997 finds all outputs in the module, and if that input is not otherwise declared
12998 as a register or wire, creates a tieoff.
13000 AUTORESET ties signals to deasserted, which is presumed to be zero.
13001 Signals that match `verilog-active-low-regexp' will be deasserted by tying
13004 You can add signals you do not want included in AUTOTIEOFF with
13005 `verilog-auto-tieoff-ignore-regexp'.
13007 `verilog-auto-wire-type' may be used to change the datatype of
13010 `verilog-auto-reset-widths' may be used to change how the tieoff
13011 value's width is generated.
13013 An example of making a stub for another module:
13015 module ExampStub (/*AUTOINST*/);
13016 /*AUTOINOUTPARAM(\"Foo\")*/
13017 /*AUTOINOUTMODULE(\"Foo\")*/
13019 // verilator lint_off UNUSED
13020 wire _unused_ok = &{1'b0,
13023 // verilator lint_on UNUSED
13026 Typing \\[verilog-auto] will make this into:
13028 module ExampStub (/*AUTOINST*/...);
13029 /*AUTOINOUTPARAM(\"Foo\")*/
13030 /*AUTOINOUTMODULE(\"Foo\")*/
13031 // Beginning of autotieoff
13033 // End of automatics
13036 // Beginning of autotieoff
13037 wire [2:0] foo = 3'b0;
13038 // End of automatics
13044 (let* ((indent-pt (current-indentation))
13045 (modi (verilog-modi-current))
13046 (moddecls (verilog-modi-get-decls modi))
13047 (modsubdecls (verilog-modi-get-sub-decls modi))
13048 (sig-list (verilog-signals-not-in
13049 (verilog-decls-get-outputs moddecls)
13050 (append (verilog-decls-get-vars moddecls)
13051 (verilog-decls-get-assigns moddecls)
13052 (verilog-decls-get-consts moddecls)
13053 (verilog-decls-get-gparams moddecls)
13054 (verilog-subdecls-get-interfaced modsubdecls)
13055 (verilog-subdecls-get-outputs modsubdecls)
13056 (verilog-subdecls-get-inouts modsubdecls)))))
13057 (setq sig-list (verilog-signals-not-matching-regexp
13058 sig-list verilog-auto-tieoff-ignore-regexp))
13060 (verilog-forward-or-insert-line)
13061 (verilog-insert-indent "// Beginning of automatic tieoffs (for this module's unterminated outputs)\n")
13062 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
13063 (verilog-modi-cache-add-vars modi sig-list) ; Before we trash list
13065 (let ((sig (car sig-list)))
13066 (cond ((equal verilog-auto-tieoff-declaration "assign")
13067 (indent-to indent-pt)
13068 (insert "assign " (verilog-sig-name sig)))
13070 (verilog-insert-one-definition sig verilog-auto-tieoff-declaration indent-pt)))
13071 (indent-to (max 48 (+ indent-pt 40)))
13072 (insert "= " (verilog-sig-tieoff sig)
13074 (setq sig-list (cdr sig-list))))
13075 (verilog-insert-indent "// End of automatics\n")))))
13077 (defun verilog-auto-undef ()
13078 "Expand AUTOUNDEF statements, as part of \\[verilog-auto].
13079 Take any \\=`defines since the last AUTOUNDEF in the current file
13080 and create \\=`undefs for them. This is used to insure that
13081 file-local defines do not pollute the global \\=`define name space.
13084 AUTOUNDEF presumes any identifier following \\=`define is the
13085 name of a define. Any \\=`ifdefs are ignored.
13087 AUTOUNDEF suppresses creating an \\=`undef for any define that was
13088 \\=`undefed before the AUTOUNDEF. This may be used to work around
13089 the ignoring of \\=`ifdefs as shown below.
13094 \\=`define M_BAR(x)
13098 \\=`undef M_BAZ // Emacs will see this and not \\=`undef M_BAZ
13103 Typing \\[verilog-auto] will make this into:
13107 // Beginning of automatic undefs
13110 // End of automatics
13112 You may also provide an optional regular expression, in which case only
13113 defines the regular expression will be undefed."
13115 (let* ((params (verilog-read-auto-params 0 1))
13116 (regexp (nth 0 params))
13117 (indent-pt (current-indentation))
13121 ;; Scan from start of file, or last AUTOUNDEF
13122 (or (verilog-re-search-backward-quick "/\\*AUTOUNDEF\\>" end-pt t)
13123 (goto-char (point-min)))
13124 (while (verilog-re-search-forward-quick
13125 "`\\(define\\|undef\\)\\s-*\\([a-zA-Z_][a-zA-Z_0-9]*\\)" end-pt t)
13126 (cond ((equal (match-string-no-properties 1) "define")
13127 (setq def (match-string-no-properties 2))
13128 (when (and (or (not regexp)
13129 (string-match regexp def))
13130 (not (member def defs))) ; delete-dups not in 21.1
13131 (setq defs (cons def defs))))
13133 (setq defs (delete (match-string-no-properties 2) defs))))))
13135 (setq defs (sort defs 'string<))
13137 (verilog-forward-or-insert-line)
13138 (verilog-insert-indent "// Beginning of automatic undefs\n")
13140 (verilog-insert-indent "`undef " (car defs) "\n")
13141 (setq defs (cdr defs)))
13142 (verilog-insert-indent "// End of automatics\n")))))
13144 (defun verilog-auto-unused ()
13145 "Expand AUTOUNUSED statements, as part of \\[verilog-auto].
13146 Replace the /*AUTOUNUSED*/ comment with a comma separated list of all unused
13147 input and inout signals.
13149 /*AUTOUNUSED*/ is used to make stub modules; modules that have the same
13150 input/output list as another module, but no internals. Specifically, it
13151 finds all inputs and inouts in the module, and if that input is not otherwise
13152 used, adds it to a comma separated list.
13154 The comma separated list is intended to be used to create a _unused_ok
13155 signal. Using the exact name \"_unused_ok\" for name of the temporary
13156 signal is recommended as it will insure maximum forward compatibility, it
13157 also makes lint warnings easy to understand; ignore any unused warnings
13158 with \"unused\" in the signal name.
13160 To reduce simulation time, the _unused_ok signal should be forced to a
13161 constant to prevent wiggling. The easiest thing to do is use a
13162 reduction-and with 1'b0 as shown.
13164 This way all unused signals are in one place, making it convenient to add
13165 your tool's specific pragmas around the assignment to disable any unused
13168 You can add signals you do not want included in AUTOUNUSED with
13169 `verilog-auto-unused-ignore-regexp'.
13171 An example of making a stub for another module:
13173 module ExampStub (/*AUTOINST*/);
13174 /*AUTOINOUTPARAM(\"Examp\")*/
13175 /*AUTOINOUTMODULE(\"Examp\")*/
13177 // verilator lint_off UNUSED
13178 wire _unused_ok = &{1'b0,
13181 // verilator lint_on UNUSED
13184 Typing \\[verilog-auto] will make this into:
13187 // verilator lint_off UNUSED
13188 wire _unused_ok = &{1'b0,
13190 // Beginning of automatics
13194 // End of automatics
13196 // verilator lint_on UNUSED
13201 (let* ((indent-pt (progn (search-backward "/*") (current-column)))
13202 (modi (verilog-modi-current))
13203 (moddecls (verilog-modi-get-decls modi))
13204 (modsubdecls (verilog-modi-get-sub-decls modi))
13205 (sig-list (verilog-signals-not-in
13206 (append (verilog-decls-get-inputs moddecls)
13207 (verilog-decls-get-inouts moddecls))
13208 (append (verilog-subdecls-get-inputs modsubdecls)
13209 (verilog-subdecls-get-inouts modsubdecls)))))
13210 (setq sig-list (verilog-signals-not-matching-regexp
13211 sig-list verilog-auto-unused-ignore-regexp))
13213 (verilog-forward-or-insert-line)
13214 (verilog-insert-indent "// Beginning of automatic unused inputs\n")
13215 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
13217 (let ((sig (car sig-list)))
13218 (indent-to indent-pt)
13219 (insert (verilog-sig-name sig) ",\n")
13220 (setq sig-list (cdr sig-list))))
13221 (verilog-insert-indent "// End of automatics\n")))))
13223 (defun verilog-enum-ascii (signm elim-regexp)
13224 "Convert an enum name SIGNM to an ascii string for insertion.
13225 Remove user provided prefix ELIM-REGEXP."
13226 (or elim-regexp (setq elim-regexp "_ DONT MATCH IT_"))
13227 (let ((case-fold-search t))
13228 ;; All upper becomes all lower for readability
13229 (downcase (verilog-string-replace-matches elim-regexp "" nil nil signm))))
13231 (defun verilog-auto-ascii-enum ()
13232 "Expand AUTOASCIIENUM statements, as part of \\[verilog-auto].
13233 Create a register to contain the ASCII decode of an enumerated signal type.
13234 This will allow trace viewers to show the ASCII name of states.
13236 First, parameters are built into an enumeration using the synopsys enum
13237 comment. The comment must be between the keyword and the symbol.
13238 \(Annoying, but that's what Synopsys's dc_shell FSM reader requires.)
13240 Next, registers which that enum applies to are also tagged with the same
13243 Finally, an AUTOASCIIENUM command is used.
13245 The first parameter is the name of the signal to be decoded.
13247 The second parameter is the name to store the ASCII code into. For the
13248 signal foo, I suggest the name _foo__ascii, where the leading _ indicates
13249 a signal that is just for simulation, and the magic characters _ascii
13250 tell viewers like Dinotrace to display in ASCII format.
13252 The third optional parameter is a string which will be removed
13253 from the state names. It defaults to \"\" which removes nothing.
13255 The fourth optional parameter is \"onehot\" to force one-hot
13256 decoding. If unspecified, if and only if the first parameter
13257 width is 2^(number of states in enum) and does NOT match the
13258 width of the enum, the signal is assumed to be a one-hot
13259 decode. Otherwise, it's a normal encoded state vector.
13261 `verilog-auto-wire-type' may be used to change the datatype of
13264 \"auto enum\" may be used in place of \"synopsys enum\".
13268 //== State enumeration
13269 parameter [2:0] // synopsys enum state_info
13273 //== State variables
13274 reg [2:0] /* synopsys enum state_info */
13275 state_r; /* synopsys state_vector state_r */
13276 reg [2:0] /* synopsys enum state_info */
13279 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
13281 Typing \\[verilog-auto] will make this into:
13283 ... same front matter ...
13285 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
13286 // Beginning of automatic ASCII enum decoding
13287 reg [39:0] state_ascii_r; // Decode of state_r
13288 always @(state_r) begin
13290 SM_IDLE: state_ascii_r = \"idle \";
13291 SM_SEND: state_ascii_r = \"send \";
13292 SM_WAIT1: state_ascii_r = \"wait1\";
13293 default: state_ascii_r = \"%Erro\";
13296 // End of automatics"
13298 (let* ((params (verilog-read-auto-params 2 4))
13299 (undecode-name (nth 0 params))
13300 (ascii-name (nth 1 params))
13301 (elim-regexp (and (nth 2 params)
13302 (not (equal (nth 2 params) ""))
13304 (one-hot-flag (nth 3 params))
13306 (indent-pt (current-indentation))
13307 (modi (verilog-modi-current))
13308 (moddecls (verilog-modi-get-decls modi))
13310 (sig-list-consts (append (verilog-decls-get-consts moddecls)
13311 (verilog-decls-get-gparams moddecls)))
13312 (sig-list-all (verilog-decls-get-iovars moddecls))
13314 (undecode-sig (or (assoc undecode-name sig-list-all)
13315 (error "%s: Signal %s not found in design" (verilog-point-text) undecode-name)))
13316 (undecode-enum (or (verilog-sig-enum undecode-sig)
13317 (error "%s: Signal %s does not have an enum tag" (verilog-point-text) undecode-name)))
13319 (enum-sigs (verilog-signals-not-in
13320 (or (verilog-signals-matching-enum sig-list-consts undecode-enum)
13321 (error "%s: No state definitions for %s" (verilog-point-text) undecode-enum))
13325 (string-match "onehot" (or one-hot-flag ""))
13326 (and ; width(enum) != width(sig)
13327 (or (not (verilog-sig-bits (car enum-sigs)))
13328 (not (equal (verilog-sig-width (car enum-sigs))
13329 (verilog-sig-width undecode-sig))))
13330 ;; count(enums) == width(sig)
13331 (equal (number-to-string (length enum-sigs))
13332 (verilog-sig-width undecode-sig)))))
13336 ;; Find number of ascii chars needed
13337 (let ((tmp-sigs enum-sigs))
13339 (setq enum-chars (max enum-chars (length (verilog-sig-name (car tmp-sigs))))
13340 ascii-chars (max ascii-chars (length (verilog-enum-ascii
13341 (verilog-sig-name (car tmp-sigs))
13343 tmp-sigs (cdr tmp-sigs))))
13345 (verilog-forward-or-insert-line)
13346 (verilog-insert-indent "// Beginning of automatic ASCII enum decoding\n")
13347 (let ((decode-sig-list (list (list ascii-name (format "[%d:0]" (- (* ascii-chars 8) 1))
13348 (concat "Decode of " undecode-name) nil nil))))
13349 (verilog-insert-definition modi decode-sig-list "reg" indent-pt nil))
13351 (verilog-insert-indent "always @(" undecode-name ") begin\n")
13352 (setq indent-pt (+ indent-pt verilog-indent-level))
13353 (verilog-insert-indent "case ({" undecode-name "})\n")
13354 (setq indent-pt (+ indent-pt verilog-case-indent))
13356 (let ((tmp-sigs enum-sigs)
13357 (chrfmt (format "%%-%ds %s = \"%%-%ds\";\n"
13358 (+ (if one-hot 9 1) (max 8 enum-chars))
13359 ascii-name ascii-chars))
13360 (errname (substring "%Error" 0 (min 6 ascii-chars))))
13362 (verilog-insert-indent
13365 (concat (if one-hot "(")
13366 ;; Use enum-sigs length as that's numeric
13367 ;; verilog-sig-width undecode-sig might not be.
13368 (if one-hot (number-to-string (length enum-sigs)))
13369 ;; We use a shift instead of var[index]
13370 ;; so that a non-one hot value will show as error.
13371 (if one-hot "'b1<<")
13372 (verilog-sig-name (car tmp-sigs))
13373 (if one-hot ")") ":")
13374 (verilog-enum-ascii (verilog-sig-name (car tmp-sigs))
13376 (setq tmp-sigs (cdr tmp-sigs)))
13377 (verilog-insert-indent (format chrfmt "default:" errname)))
13379 (setq indent-pt (- indent-pt verilog-case-indent))
13380 (verilog-insert-indent "endcase\n")
13381 (setq indent-pt (- indent-pt verilog-indent-level))
13382 (verilog-insert-indent "end\n"
13383 "// End of automatics\n"))))
13385 (defun verilog-auto-templated-rel ()
13386 "Replace Templated relative line numbers with absolute line numbers.
13387 Internal use only. This hacks around the line numbers in AUTOINST Templates
13388 being different from the final output's line numbering."
13389 (let ((templateno 0) (template-line (list 0)) (buf-line 1))
13390 ;; Find line number each template is on
13391 ;; Count lines as we go, as otherwise it's O(n^2) to use count-lines
13392 (goto-char (point-min))
13393 (while (not (eobp))
13394 (when (looking-at ".*AUTO_TEMPLATE")
13395 (setq templateno (1+ templateno))
13396 (setq template-line (cons buf-line template-line)))
13397 (setq buf-line (1+ buf-line))
13399 (setq template-line (nreverse template-line))
13400 ;; Replace T# L# with absolute line number
13401 (goto-char (point-min))
13402 (while (re-search-forward " Templated T\\([0-9]+\\) L\\([0-9]+\\)" nil t)
13404 (concat " Templated "
13405 (int-to-string (+ (nth (string-to-number (match-string 1))
13407 (string-to-number (match-string 2)))))
13410 (defun verilog-auto-template-lint ()
13411 "Check AUTO_TEMPLATEs for unused lines.
13412 Enable with `verilog-auto-template-warn-unused'."
13413 (let ((name1 (or (buffer-file-name) (buffer-name))))
13415 (goto-char (point-min))
13416 (while (re-search-forward
13417 "^\\s-*/?\\*?\\s-*[a-zA-Z0-9`_$]+\\s-+AUTO_TEMPLATE" nil t)
13418 (let* ((tpl-info (verilog-read-auto-template-middle))
13419 (tpl-list (aref tpl-info 1))
13420 (tlines (append (nth 0 tpl-list) (nth 1 tpl-list)))
13423 (setq tpl-ass (car tlines)
13424 tlines (cdr tlines))
13426 (unless (or (not (eval-when-compile (fboundp 'make-hash-table))) ; Not supported, no warning
13427 (not verilog-auto-template-hits)
13428 (gethash (vector (nth 2 tpl-ass) (nth 3 tpl-ass))
13429 verilog-auto-template-hits))
13430 (verilog-warn-error "%s:%d: AUTO_TEMPLATE line unused: \".%s (%s)\""
13432 (+ (elt tpl-ass 3) ; Template line number
13433 (count-lines (point-min) (point)))
13434 (elt tpl-ass 0) (elt tpl-ass 1))
13438 ;;; Auto top level:
13441 (defun verilog-auto (&optional inject) ; Use verilog-inject-auto instead of passing an arg
13442 "Expand AUTO statements.
13443 Look for any /*AUTO...*/ commands in the code, as used in
13444 instantiations or argument headers. Update the list of signals
13445 following the /*AUTO...*/ command.
13447 Use \\[verilog-delete-auto] to remove the AUTOs.
13449 Use \\[verilog-diff-auto] to see differences in AUTO expansion.
13451 Use \\[verilog-inject-auto] to insert AUTOs for the first time.
13453 Use \\[verilog-faq] for a pointer to frequently asked questions.
13455 For new users, we recommend setting `verilog-case-fold' to nil
13456 and `verilog-auto-arg-sort' to t.
13458 The hooks `verilog-before-auto-hook' and `verilog-auto-hook' are
13459 called before and after this function, respectively.
13462 module ModuleName (/*AUTOARG*/);
13467 InstMod instName #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);
13469 You can also update the AUTOs from the shell using:
13470 emacs --batch <filenames.v> -f verilog-batch-auto
13471 Or fix indentation with:
13472 emacs --batch <filenames.v> -f verilog-batch-indent
13473 Likewise, you can delete or inject AUTOs with:
13474 emacs --batch <filenames.v> -f verilog-batch-delete-auto
13475 emacs --batch <filenames.v> -f verilog-batch-inject-auto
13476 Or check if AUTOs have the same expansion
13477 emacs --batch <filenames.v> -f verilog-batch-diff-auto
13479 Using \\[describe-function], see also:
13480 `verilog-auto-arg' for AUTOARG module instantiations
13481 `verilog-auto-ascii-enum' for AUTOASCIIENUM enumeration decoding
13482 `verilog-auto-assign-modport' for AUTOASSIGNMODPORT assignment to/from modport
13483 `verilog-auto-inout' for AUTOINOUT making hierarchy inouts
13484 `verilog-auto-inout-comp' for AUTOINOUTCOMP copy complemented i/o
13485 `verilog-auto-inout-in' for AUTOINOUTIN inputs for all i/o
13486 `verilog-auto-inout-modport' for AUTOINOUTMODPORT i/o from an interface modport
13487 `verilog-auto-inout-module' for AUTOINOUTMODULE copying i/o from elsewhere
13488 `verilog-auto-inout-param' for AUTOINOUTPARAM copying params from elsewhere
13489 `verilog-auto-input' for AUTOINPUT making hierarchy inputs
13490 `verilog-auto-insert-lisp' for AUTOINSERTLISP insert code from lisp function
13491 `verilog-auto-insert-last' for AUTOINSERTLAST insert code from lisp function
13492 `verilog-auto-inst' for AUTOINST instantiation pins
13493 `verilog-auto-star' for AUTOINST .* SystemVerilog pins
13494 `verilog-auto-inst-param' for AUTOINSTPARAM instantiation params
13495 `verilog-auto-logic' for AUTOLOGIC declaring logic signals
13496 `verilog-auto-output' for AUTOOUTPUT making hierarchy outputs
13497 `verilog-auto-output-every' for AUTOOUTPUTEVERY making all outputs
13498 `verilog-auto-reg' for AUTOREG registers
13499 `verilog-auto-reg-input' for AUTOREGINPUT instantiation registers
13500 `verilog-auto-reset' for AUTORESET flop resets
13501 `verilog-auto-sense' for AUTOSENSE or AS always sensitivity lists
13502 `verilog-auto-tieoff' for AUTOTIEOFF output tieoffs
13503 `verilog-auto-undef' for AUTOUNDEF \\=`undef of local \\=`defines
13504 `verilog-auto-unused' for AUTOUNUSED unused inputs/inouts
13505 `verilog-auto-wire' for AUTOWIRE instantiation wires
13507 `verilog-read-defines' for reading \\=`define values
13508 `verilog-read-includes' for reading \\=`includes
13510 If you have bugs with these autos, please file an issue at
13511 URL `http://www.veripool.org/verilog-mode' or contact the AUTOAUTHOR
13512 Wilson Snyder (wsnyder@wsnyder.org)."
13514 (unless noninteractive (message "Updating AUTOs..."))
13515 (if (fboundp 'dinotrace-unannotate-all)
13516 (dinotrace-unannotate-all))
13517 (verilog-save-font-mods
13518 (let ((oldbuf (if (not (buffer-modified-p))
13520 (case-fold-search verilog-case-fold)
13521 ;; Cache directories; we don't write new files, so can't change
13522 (verilog-dir-cache-preserving t)
13523 ;; Cache current module
13524 (verilog-modi-cache-current-enable t)
13525 (verilog-modi-cache-current-max (point-min)) ; IE it's invalid
13526 verilog-modi-cache-current)
13528 ;; Disable change hooks for speed
13529 ;; This let can't be part of above let; must restore
13530 ;; after-change-functions before font-lock resumes
13531 (verilog-save-no-change-functions
13532 (verilog-save-scan-cache
13534 ;; Wipe cache; otherwise if we AUTOed a block above this one,
13535 ;; we'll misremember we have generated IOs, confusing AUTOOUTPUT
13536 (setq verilog-modi-cache-list nil)
13538 (verilog-read-auto-template-init)
13539 ;; If we're not in verilog-mode, change syntax table so parsing works right
13540 (unless (eq major-mode `verilog-mode) (verilog-mode))
13541 ;; Allow user to customize
13542 (verilog-run-hooks 'verilog-before-auto-hook)
13543 ;; Try to save the user from needing to revert-file to reread file local-variables
13544 (verilog-auto-reeval-locals)
13545 (verilog-read-auto-lisp-present)
13546 (verilog-read-auto-lisp (point-min) (point-max))
13547 (verilog-getopt-flags)
13548 ;; From here on out, we can cache anything we read from disk
13549 (verilog-preserve-dir-cache
13550 ;; These two may seem obvious to do always, but on large includes it can be way too slow
13551 (when verilog-auto-read-includes
13552 (verilog-read-includes)
13553 (verilog-read-defines nil nil t))
13554 ;; Setup variables due to SystemVerilog expansion
13555 (verilog-auto-re-search-do "/\\*AUTOLOGIC\\*/" 'verilog-auto-logic-setup)
13556 ;; This particular ordering is important
13557 ;; INST: Lower modules correct, no internal dependencies, FIRST
13558 (verilog-preserve-modi-cache
13559 ;; Clear existing autos else we'll be screwed by existing ones
13560 (verilog-delete-auto)
13561 ;; Injection if appropriate
13563 (verilog-inject-inst)
13564 (verilog-inject-sense)
13565 (verilog-inject-arg))
13567 ;; Do user inserts first, so their code can insert AUTOs
13568 (verilog-auto-re-search-do "/\\*AUTOINSERTLISP(.*?)\\*/"
13569 'verilog-auto-insert-lisp)
13570 ;; Expand instances before need the signals the instances input/output
13571 (verilog-auto-re-search-do "/\\*AUTOINSTPARAM\\*/" 'verilog-auto-inst-param)
13572 (verilog-auto-re-search-do "/\\*AUTOINST\\*/" 'verilog-auto-inst)
13573 (verilog-auto-re-search-do "\\.\\*" 'verilog-auto-star)
13574 ;; Doesn't matter when done, but combine it with a common changer
13575 (verilog-auto-re-search-do "/\\*\\(AUTOSENSE\\|AS\\)\\*/" 'verilog-auto-sense)
13576 (verilog-auto-re-search-do "/\\*AUTORESET\\*/" 'verilog-auto-reset)
13577 ;; Must be done before autoin/out as creates a reg
13578 (verilog-auto-re-search-do "/\\*AUTOASCIIENUM(.*?)\\*/" 'verilog-auto-ascii-enum)
13580 ;; first in/outs from other files
13581 (verilog-auto-re-search-do "/\\*AUTOINOUTMODPORT(.*?)\\*/" 'verilog-auto-inout-modport)
13582 (verilog-auto-re-search-do "/\\*AUTOINOUTMODULE(.*?)\\*/" 'verilog-auto-inout-module)
13583 (verilog-auto-re-search-do "/\\*AUTOINOUTCOMP(.*?)\\*/" 'verilog-auto-inout-comp)
13584 (verilog-auto-re-search-do "/\\*AUTOINOUTIN(.*?)\\*/" 'verilog-auto-inout-in)
13585 (verilog-auto-re-search-do "/\\*AUTOINOUTPARAM(.*?)\\*/" 'verilog-auto-inout-param)
13586 ;; next in/outs which need previous sucked inputs first
13587 (verilog-auto-re-search-do "/\\*AUTOOUTPUT\\((.*?)\\)?\\*/" 'verilog-auto-output)
13588 (verilog-auto-re-search-do "/\\*AUTOINPUT\\((.*?)\\)?\\*/" 'verilog-auto-input)
13589 (verilog-auto-re-search-do "/\\*AUTOINOUT\\((.*?)\\)?\\*/" 'verilog-auto-inout)
13590 ;; Then tie off those in/outs
13591 (verilog-auto-re-search-do "/\\*AUTOTIEOFF\\*/" 'verilog-auto-tieoff)
13592 ;; These can be anywhere after AUTOINSERTLISP
13593 (verilog-auto-re-search-do "/\\*AUTOUNDEF\\((.*?)\\)?\\*/" 'verilog-auto-undef)
13594 ;; Wires/regs must be after inputs/outputs
13595 (verilog-auto-re-search-do "/\\*AUTOASSIGNMODPORT(.*?)\\*/" 'verilog-auto-assign-modport)
13596 (verilog-auto-re-search-do "/\\*AUTOLOGIC\\*/" 'verilog-auto-logic)
13597 (verilog-auto-re-search-do "/\\*AUTOWIRE\\*/" 'verilog-auto-wire)
13598 (verilog-auto-re-search-do "/\\*AUTOREG\\*/" 'verilog-auto-reg)
13599 (verilog-auto-re-search-do "/\\*AUTOREGINPUT\\*/" 'verilog-auto-reg-input)
13600 ;; outputevery needs AUTOOUTPUTs done first
13601 (verilog-auto-re-search-do "/\\*AUTOOUTPUTEVERY\\((.*?)\\)?\\*/" 'verilog-auto-output-every)
13602 ;; After we've created all new variables
13603 (verilog-auto-re-search-do "/\\*AUTOUNUSED\\*/" 'verilog-auto-unused)
13604 ;; Must be after all inputs outputs are generated
13605 (verilog-auto-re-search-do "/\\*AUTOARG\\*/" 'verilog-auto-arg)
13607 (verilog-auto-re-search-do "/\\*AUTOINSERTLAST(.*?)\\*/" 'verilog-auto-insert-last)
13608 ;; Fix line numbers (comments only)
13609 (when verilog-auto-inst-template-numbers
13610 (verilog-auto-templated-rel))
13611 (when verilog-auto-template-warn-unused
13612 (verilog-auto-template-lint))))
13614 (verilog-run-hooks 'verilog-auto-hook)
13616 (when verilog-auto-delete-trailing-whitespace
13617 (verilog-delete-trailing-whitespace))
13619 (set (make-local-variable 'verilog-auto-update-tick) (buffer-chars-modified-tick))
13621 ;; If end result is same as when started, clear modified flag
13622 (cond ((and oldbuf (equal oldbuf (buffer-string)))
13623 (set-buffer-modified-p nil)
13624 (unless noninteractive (message "Updating AUTOs...done (no changes)")))
13625 (t (unless noninteractive (message "Updating AUTOs...done"))))
13626 ;; End of after-change protection
13629 ;; Currently handled in verilog-save-font-mods
13635 (defvar verilog-template-map
13636 (let ((map (make-sparse-keymap)))
13637 (define-key map "a" 'verilog-sk-always)
13638 (define-key map "b" 'verilog-sk-begin)
13639 (define-key map "c" 'verilog-sk-case)
13640 (define-key map "f" 'verilog-sk-for)
13641 (define-key map "g" 'verilog-sk-generate)
13642 (define-key map "h" 'verilog-sk-header)
13643 (define-key map "i" 'verilog-sk-initial)
13644 (define-key map "j" 'verilog-sk-fork)
13645 (define-key map "m" 'verilog-sk-module)
13646 (define-key map "o" 'verilog-sk-ovm-class)
13647 (define-key map "p" 'verilog-sk-primitive)
13648 (define-key map "r" 'verilog-sk-repeat)
13649 (define-key map "s" 'verilog-sk-specify)
13650 (define-key map "t" 'verilog-sk-task)
13651 (define-key map "u" 'verilog-sk-uvm-object)
13652 (define-key map "w" 'verilog-sk-while)
13653 (define-key map "x" 'verilog-sk-casex)
13654 (define-key map "z" 'verilog-sk-casez)
13655 (define-key map "?" 'verilog-sk-if)
13656 (define-key map ":" 'verilog-sk-else-if)
13657 (define-key map "/" 'verilog-sk-comment)
13658 (define-key map "A" 'verilog-sk-assign)
13659 (define-key map "F" 'verilog-sk-function)
13660 (define-key map "I" 'verilog-sk-input)
13661 (define-key map "O" 'verilog-sk-output)
13662 (define-key map "S" 'verilog-sk-state-machine)
13663 (define-key map "=" 'verilog-sk-inout)
13664 (define-key map "U" 'verilog-sk-uvm-component)
13665 (define-key map "W" 'verilog-sk-wire)
13666 (define-key map "R" 'verilog-sk-reg)
13667 (define-key map "D" 'verilog-sk-define-signal)
13669 "Keymap used in Verilog mode for smart template operations.")
13673 ;; Place the templates into Verilog Mode. They may be inserted under any key.
13674 ;; C-c C-t will be the default. If you use templates a lot, you
13675 ;; may want to consider moving the binding to another key in your init
13678 ;; Note \C-c and letter are reserved for users
13679 (define-key verilog-mode-map "\C-c\C-t" verilog-template-map)
13681 ;; ---- statement skeletons ------------------------------------------
13683 (define-skeleton verilog-sk-prompt-condition
13684 "Prompt for the loop condition."
13685 "[condition]: " str )
13687 (define-skeleton verilog-sk-prompt-init
13688 "Prompt for the loop init statement."
13689 "[initial statement]: " str )
13691 (define-skeleton verilog-sk-prompt-inc
13692 "Prompt for the loop increment statement."
13693 "[increment statement]: " str )
13695 (define-skeleton verilog-sk-prompt-name
13696 "Prompt for the name of something."
13699 (define-skeleton verilog-sk-prompt-clock
13700 "Prompt for the name of something."
13701 "name and edge of clock(s): " str)
13703 (defvar verilog-sk-reset nil)
13704 (defun verilog-sk-prompt-reset ()
13705 "Prompt for the name of a state machine reset."
13706 (setq verilog-sk-reset (read-string "name of reset: " "rst")))
13709 (define-skeleton verilog-sk-prompt-state-selector
13710 "Prompt for the name of a state machine selector."
13711 "name of selector (eg {a,b,c,d}): " str )
13713 (define-skeleton verilog-sk-prompt-output
13714 "Prompt for the name of something."
13717 (define-skeleton verilog-sk-prompt-msb
13718 "Prompt for most significant bit specification."
13719 "msb:" str & ?: & '(verilog-sk-prompt-lsb) | -1 )
13721 (define-skeleton verilog-sk-prompt-lsb
13722 "Prompt for least significant bit specification."
13725 (defvar verilog-sk-p nil)
13726 (define-skeleton verilog-sk-prompt-width
13727 "Prompt for a width specification."
13730 (setq verilog-sk-p (point))
13731 (verilog-sk-prompt-msb)
13732 (if (> (point) verilog-sk-p) "] " " ")))
13734 (defun verilog-sk-header ()
13735 "Insert a descriptive header at the top of the file.
13736 See also `verilog-header' for an alternative format."
13739 (goto-char (point-min))
13740 (verilog-sk-header-tmpl)))
13742 (define-skeleton verilog-sk-header-tmpl
13743 "Insert a comment block containing the module title, author, etc."
13745 "// -*- Mode: Verilog -*-"
13746 "\n// Filename : " (buffer-name)
13747 "\n// Description : " str
13748 "\n// Author : " (user-full-name)
13749 "\n// Created On : " (current-time-string)
13750 "\n// Last Modified By: " (user-full-name)
13751 "\n// Last Modified On: " (current-time-string)
13752 "\n// Update Count : 0"
13753 "\n// Status : Unknown, Use with caution!"
13756 (define-skeleton verilog-sk-module
13757 "Insert a module definition."
13759 > "module " '(verilog-sk-prompt-name) " (/*AUTOARG*/ ) ;" \n
13761 > (- verilog-indent-level-behavioral) "endmodule" (progn (electric-verilog-terminate-line) nil))
13763 ;; ------------------------------------------------------------------------
13764 ;; Define a default OVM class, with macros and new()
13765 ;; ------------------------------------------------------------------------
13767 (define-skeleton verilog-sk-ovm-class
13768 "Insert a class definition"
13770 > "class " (setq name (skeleton-read "Name: ")) " extends " (skeleton-read "Extends: ") ";" \n
13772 > "`ovm_object_utils_begin(" name ")" \n
13773 > (- verilog-indent-level) " `ovm_object_utils_end" \n
13775 > "function new(string name=\"" name "\");" \n
13776 > "super.new(name);" \n
13777 > (- verilog-indent-level) "endfunction" \n
13779 > "endclass" (progn (electric-verilog-terminate-line) nil))
13781 (define-skeleton verilog-sk-uvm-object
13782 "Insert a class definition"
13784 > "class " (setq name (skeleton-read "Name: ")) " extends " (skeleton-read "Extends: ") ";" \n
13786 > "`uvm_object_utils_begin(" name ")" \n
13787 > (- verilog-indent-level) "`uvm_object_utils_end" \n
13789 > "function new(string name=\"" name "\");" \n
13790 > "super.new(name);" \n
13791 > (- verilog-indent-level) "endfunction" \n
13793 > "endclass" (progn (electric-verilog-terminate-line) nil))
13795 (define-skeleton verilog-sk-uvm-component
13796 "Insert a class definition"
13798 > "class " (setq name (skeleton-read "Name: ")) " extends " (skeleton-read "Extends: ") ";" \n
13800 > "`uvm_component_utils_begin(" name ")" \n
13801 > (- verilog-indent-level) "`uvm_component_utils_end" \n
13803 > "function new(string name=\"\", uvm_component parent);" \n
13804 > "super.new(name, parent);" \n
13805 > (- verilog-indent-level) "endfunction" \n
13807 > "endclass" (progn (electric-verilog-terminate-line) nil))
13809 (define-skeleton verilog-sk-primitive
13810 "Insert a task definition."
13812 > "primitive " '(verilog-sk-prompt-name) " ( " '(verilog-sk-prompt-output) ("input:" ", " str ) " );"\n
13814 > (- verilog-indent-level-behavioral) "endprimitive" (progn (electric-verilog-terminate-line) nil))
13816 (define-skeleton verilog-sk-task
13817 "Insert a task definition."
13819 > "task " '(verilog-sk-prompt-name) & ?; \n
13823 > (- verilog-indent-level-behavioral) "end" \n
13824 > (- verilog-indent-level-behavioral) "endtask" (progn (electric-verilog-terminate-line) nil))
13826 (define-skeleton verilog-sk-function
13827 "Insert a function definition."
13829 > "function [" '(verilog-sk-prompt-width) | -1 '(verilog-sk-prompt-name) ?; \n
13833 > (- verilog-indent-level-behavioral) "end" \n
13834 > (- verilog-indent-level-behavioral) "endfunction" (progn (electric-verilog-terminate-line) nil))
13836 (define-skeleton verilog-sk-always
13837 "Insert always block. Uses the minibuffer to prompt
13838 for sensitivity list."
13840 > "always @ ( /*AUTOSENSE*/ ) begin\n"
13842 > (- verilog-indent-level-behavioral) "end" \n >
13845 (define-skeleton verilog-sk-initial
13846 "Insert an initial block."
13848 > "initial begin\n"
13850 > (- verilog-indent-level-behavioral) "end" \n > )
13852 (define-skeleton verilog-sk-specify
13853 "Insert specify block. "
13857 > (- verilog-indent-level-behavioral) "endspecify" \n > )
13859 (define-skeleton verilog-sk-generate
13860 "Insert generate block. "
13864 > (- verilog-indent-level-behavioral) "endgenerate" \n > )
13866 (define-skeleton verilog-sk-begin
13867 "Insert begin end block. Uses the minibuffer to prompt for name."
13869 > "begin" '(verilog-sk-prompt-name) \n
13871 > (- verilog-indent-level-behavioral) "end" )
13873 (define-skeleton verilog-sk-fork
13874 "Insert a fork join block."
13879 > (- verilog-indent-level-behavioral) "end" \n
13882 > (- verilog-indent-level-behavioral) "end" \n
13883 > (- verilog-indent-level-behavioral) "join" \n
13887 (define-skeleton verilog-sk-case
13888 "Build skeleton case statement, prompting for the selector expression,
13889 and the case items."
13890 "[selector expression]: "
13891 > "case (" str ") " \n
13892 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
13893 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
13895 (define-skeleton verilog-sk-casex
13896 "Build skeleton casex statement, prompting for the selector expression,
13897 and the case items."
13898 "[selector expression]: "
13899 > "casex (" str ") " \n
13900 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
13901 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
13903 (define-skeleton verilog-sk-casez
13904 "Build skeleton casez statement, prompting for the selector expression,
13905 and the case items."
13906 "[selector expression]: "
13907 > "casez (" str ") " \n
13908 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
13909 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
13911 (define-skeleton verilog-sk-if
13912 "Insert a skeleton if statement."
13913 > "if (" '(verilog-sk-prompt-condition) & ")" " begin" \n
13915 > (- verilog-indent-level-behavioral) "end " \n )
13917 (define-skeleton verilog-sk-else-if
13918 "Insert a skeleton else if statement."
13919 > (verilog-indent-line) "else if ("
13920 (progn (setq verilog-sk-p (point)) nil) '(verilog-sk-prompt-condition) (if (> (point) verilog-sk-p) ") " -1 ) & " begin" \n
13922 > "end" (progn (electric-verilog-terminate-line) nil))
13924 (define-skeleton verilog-sk-datadef
13925 "Common routine to get data definition."
13927 '(verilog-sk-prompt-width) | -1 ("name (RET to end):" str ", ") -2 ";" \n)
13929 (define-skeleton verilog-sk-input
13930 "Insert an input definition."
13932 > "input [" '(verilog-sk-datadef))
13934 (define-skeleton verilog-sk-output
13935 "Insert an output definition."
13937 > "output [" '(verilog-sk-datadef))
13939 (define-skeleton verilog-sk-inout
13940 "Insert an inout definition."
13942 > "inout [" '(verilog-sk-datadef))
13944 (defvar verilog-sk-signal nil)
13945 (define-skeleton verilog-sk-def-reg
13946 "Insert a reg definition."
13948 > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-signal ";" \n (verilog-pretty-declarations-auto) )
13950 (defun verilog-sk-define-signal ()
13951 "Insert a definition of signal under point at top of module."
13953 (let* ((sig-re "[a-zA-Z0-9_]*")
13954 (v1 (buffer-substring
13956 (skip-chars-backward sig-re)
13959 (skip-chars-forward sig-re)
13961 (if (not (member v1 verilog-keywords))
13963 (setq verilog-sk-signal v1)
13964 (verilog-beg-of-defun)
13965 (verilog-end-of-statement)
13966 (verilog-forward-syntactic-ws)
13967 (verilog-sk-def-reg)
13968 (message "signal at point is %s" v1))
13969 (message "object at point (%s) is a keyword" v1))))
13971 (define-skeleton verilog-sk-wire
13972 "Insert a wire definition."
13974 > "wire [" '(verilog-sk-datadef))
13976 (define-skeleton verilog-sk-reg
13977 "Insert a reg definition."
13979 > "reg [" '(verilog-sk-datadef))
13981 (define-skeleton verilog-sk-assign
13982 "Insert a skeleton assign statement."
13984 > "assign " '(verilog-sk-prompt-name) " = " _ ";" \n)
13986 (define-skeleton verilog-sk-while
13987 "Insert a skeleton while loop statement."
13989 > "while (" '(verilog-sk-prompt-condition) ") begin" \n
13991 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
13993 (define-skeleton verilog-sk-repeat
13994 "Insert a skeleton repeat loop statement."
13996 > "repeat (" '(verilog-sk-prompt-condition) ") begin" \n
13998 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
14000 (define-skeleton verilog-sk-for
14001 "Insert a skeleton while loop statement."
14004 '(verilog-sk-prompt-init) "; "
14005 '(verilog-sk-prompt-condition) "; "
14006 '(verilog-sk-prompt-inc)
14009 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
14011 (define-skeleton verilog-sk-comment
14012 "Inserts three comment lines, making a display comment."
14018 (define-skeleton verilog-sk-state-machine
14019 "Insert a state machine definition."
14020 "Name of state variable: "
14021 '(setq input "state")
14022 > "// State registers for " str | -23 \n
14023 '(setq verilog-sk-state str)
14024 > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-state ", next_" verilog-sk-state ?; \n
14027 > "// State FF for " verilog-sk-state \n
14028 > "always @ ( " (read-string "clock:" "posedge clk") " or " (verilog-sk-prompt-reset) " ) begin" \n
14029 > "if ( " verilog-sk-reset " ) " verilog-sk-state " = 0; else" \n
14030 > verilog-sk-state " = next_" verilog-sk-state ?; \n
14031 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil)
14033 > "// Next State Logic for " verilog-sk-state \n
14034 > "always @ ( /*AUTOSENSE*/ ) begin\n"
14035 > "case (" '(verilog-sk-prompt-state-selector) ") " \n
14036 > ("case selector: " str ": begin" \n > "next_" verilog-sk-state " = " _ ";" \n > (- verilog-indent-level-behavioral) "end" \n )
14037 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil)
14038 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil))
14042 ;; Include file loading with mouse/return event
14044 ;; idea & first impl.: M. Rouat (eldo-mode.el)
14045 ;; second (emacs/xemacs) impl.: G. Van der Plas (spice-mode.el)
14047 (if (featurep 'xemacs)
14048 (require 'overlay))
14050 (defconst verilog-include-file-regexp
14051 "^`include\\s-+\"\\([^\n\"]*\\)\""
14052 "Regexp that matches the include file.")
14054 (defvar verilog-mode-mouse-map
14055 (let ((map (make-sparse-keymap))) ; as described in info pages, make a map
14056 (set-keymap-parent map verilog-mode-map)
14057 ;; mouse button bindings
14058 (define-key map "\r" 'verilog-load-file-at-point)
14059 (if (featurep 'xemacs)
14060 (define-key map 'button2 'verilog-load-file-at-mouse);ffap-at-mouse ?
14061 (define-key map [mouse-2] 'verilog-load-file-at-mouse))
14062 (if (featurep 'xemacs)
14063 (define-key map 'Sh-button2 'mouse-yank) ; you wanna paste don't you ?
14064 (define-key map [S-mouse-2] 'mouse-yank-at-click))
14066 "Map containing mouse bindings for `verilog-mode'.")
14069 (defun verilog-highlight-region (beg end _old-len)
14070 "Colorize included files and modules in the (changed?) region.
14071 Clicking on the middle-mouse button loads them in a buffer (as in dired)."
14072 (when (or verilog-highlight-includes
14073 verilog-highlight-modules)
14075 (save-match-data ; A query-replace may call this function - do not disturb
14076 (verilog-save-buffer-state
14077 (verilog-save-scan-cache
14080 (setq end-point (point-at-eol))
14082 (beginning-of-line) ; scan entire line
14083 ;; delete overlays existing on this line
14084 (let ((overlays (overlays-in (point) end-point)))
14087 (overlay-get (car overlays) 'detachable)
14088 (or (overlay-get (car overlays) 'verilog-include-file)
14089 (overlay-get (car overlays) 'verilog-inst-module)))
14090 (delete-overlay (car overlays)))
14091 (setq overlays (cdr overlays))))
14093 ;; make new include overlays
14094 (when verilog-highlight-includes
14095 (while (search-forward-regexp verilog-include-file-regexp end-point t)
14096 (goto-char (match-beginning 1))
14097 (let ((ov (make-overlay (match-beginning 1) (match-end 1))))
14098 (overlay-put ov 'start-closed 't)
14099 (overlay-put ov 'end-closed 't)
14100 (overlay-put ov 'evaporate 't)
14101 (overlay-put ov 'verilog-include-file 't)
14102 (overlay-put ov 'mouse-face 'highlight)
14103 (overlay-put ov 'local-map verilog-mode-mouse-map))))
14105 ;; make new module overlays
14107 ;; This scanner is syntax-fragile, so don't get bent
14108 (when verilog-highlight-modules
14109 (condition-case nil
14110 (while (verilog-re-search-forward-quick "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-point t)
14112 (goto-char (match-beginning 0))
14113 (unless (verilog-inside-comment-or-string-p)
14114 (verilog-read-inst-module-matcher) ; sets match 0
14115 (let* ((ov (make-overlay (match-beginning 0) (match-end 0))))
14116 (overlay-put ov 'start-closed 't)
14117 (overlay-put ov 'end-closed 't)
14118 (overlay-put ov 'evaporate 't)
14119 (overlay-put ov 'verilog-inst-module 't)
14120 (overlay-put ov 'mouse-face 'highlight)
14121 (overlay-put ov 'local-map verilog-mode-mouse-map)))))
14124 ;; Future highlights:
14125 ;; variables - make an Occur buffer of where referenced
14126 ;; pins - make an Occur buffer of the sig in the declaration module
14129 (defun verilog-highlight-buffer ()
14130 "Colorize included files and modules across the whole buffer."
14131 ;; Invoked via verilog-mode calling font-lock then `font-lock-mode-hook'
14133 ;; delete and remake overlays
14134 (verilog-highlight-region (point-min) (point-max) nil))
14136 ;; Deprecated, but was interactive, so we'll keep it around
14137 (defalias 'verilog-colorize-include-files-buffer 'verilog-highlight-buffer)
14139 ;; ffap-at-mouse isn't useful for Verilog mode. It uses library paths.
14140 ;; so define this function to do more or less the same as ffap-at-mouse
14141 ;; but first resolve filename...
14142 (defun verilog-load-file-at-mouse (event)
14143 "Load file under button 2 click's EVENT.
14144 Files are checked based on `verilog-library-flags'."
14146 (save-excursion ; implement a Verilog specific ffap-at-mouse
14147 (mouse-set-point event)
14148 (verilog-load-file-at-point t)))
14150 ;; ffap isn't usable for Verilog mode. It uses library paths.
14151 ;; so define this function to do more or less the same as ffap
14152 ;; but first resolve filename...
14153 (defun verilog-load-file-at-point (&optional warn)
14154 "Load file under point.
14155 If WARN, throw warning if not found.
14156 Files are checked based on `verilog-library-flags'."
14158 (save-excursion ; implement a Verilog specific ffap
14159 (let ((overlays (overlays-in (point) (point)))
14161 (while (and overlays (not hit))
14162 (when (overlay-get (car overlays) 'verilog-inst-module)
14163 (verilog-goto-defun-file (buffer-substring
14164 (overlay-start (car overlays))
14165 (overlay-end (car overlays))))
14167 (setq overlays (cdr overlays)))
14169 (beginning-of-line)
14170 (when (and (not hit)
14171 (looking-at verilog-include-file-regexp))
14172 (if (and (car (verilog-library-filenames
14173 (match-string 1) (buffer-file-name)))
14174 (file-readable-p (car (verilog-library-filenames
14175 (match-string 1) (buffer-file-name)))))
14176 (find-file (car (verilog-library-filenames
14177 (match-string 1) (buffer-file-name))))
14180 "File '%s' isn't readable, use shift-mouse2 to paste in this field"
14181 (match-string 1))))))))
14187 (defun verilog-faq ()
14188 "Tell the user their current version, and where to get the FAQ etc."
14190 (with-output-to-temp-buffer "*verilog-mode help*"
14191 (princ (format "You are using verilog-mode %s\n" verilog-mode-version))
14193 (princ "For new releases, see http://www.verilog.com\n")
14195 (princ "For frequently asked questions, see http://www.veripool.org/verilog-mode-faq.html\n")
14197 (princ "To submit a bug, use M-x verilog-submit-bug-report\n")
14200 (autoload 'reporter-submit-bug-report "reporter")
14201 (defvar reporter-prompt-for-summary-p)
14203 (defun verilog-submit-bug-report ()
14204 "Submit via mail a bug report on verilog-mode.el."
14206 (let ((reporter-prompt-for-summary-p t))
14207 (reporter-submit-bug-report
14208 "mac@verilog.com, wsnyder@wsnyder.org"
14209 (concat "verilog-mode v" verilog-mode-version)
14211 verilog-active-low-regexp
14212 verilog-after-save-font-hook
14213 verilog-align-ifelse
14214 verilog-assignment-delay
14215 verilog-auto-arg-sort
14216 verilog-auto-declare-nettype
14217 verilog-auto-delete-trailing-whitespace
14218 verilog-auto-endcomments
14220 verilog-auto-ignore-concat
14221 verilog-auto-indent-on-newline
14222 verilog-auto-inout-ignore-regexp
14223 verilog-auto-input-ignore-regexp
14224 verilog-auto-inst-column
14225 verilog-auto-inst-dot-name
14226 verilog-auto-inst-interfaced-ports
14227 verilog-auto-inst-param-value
14228 verilog-auto-inst-sort
14229 verilog-auto-inst-template-numbers
14230 verilog-auto-inst-vector
14231 verilog-auto-lineup
14232 verilog-auto-newline
14233 verilog-auto-output-ignore-regexp
14234 verilog-auto-read-includes
14235 verilog-auto-reset-blocking-in-non
14236 verilog-auto-reset-widths
14237 verilog-auto-save-policy
14238 verilog-auto-sense-defines-constant
14239 verilog-auto-sense-include-inputs
14240 verilog-auto-star-expand
14241 verilog-auto-star-save
14242 verilog-auto-template-warn-unused
14243 verilog-auto-tieoff-declaration
14244 verilog-auto-tieoff-ignore-regexp
14245 verilog-auto-unused-ignore-regexp
14246 verilog-auto-wire-type
14247 verilog-before-auto-hook
14248 verilog-before-delete-auto-hook
14249 verilog-before-getopt-flags-hook
14250 verilog-before-save-font-hook
14251 verilog-cache-enabled
14253 verilog-case-indent
14254 verilog-cexp-indent
14257 verilog-delete-auto-hook
14258 verilog-getopt-flags-hook
14259 verilog-highlight-grouping-keywords
14260 verilog-highlight-includes
14261 verilog-highlight-modules
14262 verilog-highlight-p1800-keywords
14263 verilog-highlight-translate-off
14264 verilog-indent-begin-after-if
14265 verilog-indent-declaration-macros
14266 verilog-indent-level
14267 verilog-indent-level-behavioral
14268 verilog-indent-level-declaration
14269 verilog-indent-level-directive
14270 verilog-indent-level-module
14271 verilog-indent-lists
14272 verilog-library-directories
14273 verilog-library-extensions
14274 verilog-library-files
14275 verilog-library-flags
14277 verilog-minimum-comment-distance
14279 verilog-mode-release-emacs
14280 verilog-mode-version
14281 verilog-preprocessor
14283 verilog-tab-always-indent
14284 verilog-tab-to-comment
14285 verilog-typedef-regexp
14291 I want to report a bug.
14293 Before I go further, I want to say that Verilog mode has changed my life.
14294 I save so much time, my files are colored nicely, my co workers respect
14295 my coding ability... until now. I'd really appreciate anything you
14296 could do to help me out with this minor deficiency in the product.
14298 I've taken a look at the Verilog-Mode FAQ at
14299 http://www.veripool.org/verilog-mode-faq.html.
14301 And, I've considered filing the bug on the issue tracker at
14302 http://www.veripool.org/verilog-mode-bugs
14303 since I realize that public bugs are easier for you to track,
14304 and for others to search, but would prefer to email.
14306 So, to reproduce the bug, start a fresh Emacs via " invocation-name "
14307 -no-init-file -no-site-file'. In a new buffer, in Verilog mode, type
14308 the code included below.
14310 Given those lines, I expected [[Fill in here]] to happen;
14311 but instead, [[Fill in here]] happens!.
14313 == The code: =="))))
14315 (provide 'verilog-mode)
14317 ;; Local Variables:
14318 ;; checkdoc-permit-comma-termination-flag:t
14319 ;; checkdoc-force-docstrings-flag:nil
14320 ;; indent-tabs-mode:nil
14323 ;;; verilog-mode.el ends here