| blob | b565e9aeff46f1ec9057972f66116cc89e164331 |
1 ;; verilog-mode.el --- major mode for editing verilog source in Emacs
3 ;; Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
4 ;; 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
6 ;; Author: Michael McNamara (mac@verilog.com),
7 ;; Wilson Snyder (wsnyder@wsnyder.org)
8 ;; Please see our web sites:
9 ;; http://www.verilog.com
10 ;; http://www.veripool.org
11 ;;
12 ;; Keywords: languages
14 ;; Yoni Rabkin <yoni@rabkins.net> contacted the maintainer of this
15 ;; file on 19/3/2008, and the maintainer agreed that when a bug is
16 ;; filed in the Emacs bug reporting system against this file, a copy
17 ;; of the bug report be sent to the maintainer's email address.
19 ;; This code supports Emacs 21.1 and later
20 ;; And XEmacs 21.1 and later
21 ;; Please do not make changes that break Emacs 21. Thanks!
22 ;;
23 ;;
25 ;; This file is part of GNU Emacs.
27 ;; GNU Emacs is free software: you can redistribute it and/or modify
28 ;; it under the terms of the GNU General Public License as published by
29 ;; the Free Software Foundation, either version 3 of the License, or
30 ;; (at your option) any later version.
32 ;; GNU Emacs is distributed in the hope that it will be useful,
33 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
34 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35 ;; GNU General Public License for more details.
37 ;; You should have received a copy of the GNU General Public License
38 ;; along with GNU Emacs. If not, see <http://www.gnu.org/licenses/>.
40 ;;; Commentary:
42 ;; This mode borrows heavily from the Pascal-mode and the cc-mode of Emacs
44 ;; USAGE
45 ;; =====
47 ;; A major mode for editing Verilog HDL source code. When you have
48 ;; entered Verilog mode, you may get more info by pressing C-h m. You
49 ;; may also get online help describing various functions by: C-h f
50 ;; <Name of function you want described>
52 ;; KNOWN BUGS / BUG REPORTS
53 ;; =======================
55 ;; Verilog is a rapidly evolving language, and hence this mode is
56 ;; under continuous development. Hence this is beta code, and likely
57 ;; has bugs. Please report any issues to the issue tracker at
58 ;; http://www.veripool.org/verilog-mode
59 ;; Please use verilog-submit-bug-report to submit a report; type C-c
60 ;; C-b to invoke this and as a result I will have a much easier time
61 ;; of reproducing the bug you find, and hence fixing it.
63 ;; INSTALLING THE MODE
64 ;; ===================
66 ;; An older version of this mode may be already installed as a part of
67 ;; your environment, and one method of updating would be to update
68 ;; your Emacs environment. Sometimes this is difficult for local
69 ;; political/control reasons, and hence you can always install a
70 ;; private copy (or even a shared copy) which overrides the system
71 ;; default.
73 ;; You can get step by step help in installing this file by going to
74 ;; <http://www.verilog.com/emacs_install.html>
76 ;; The short list of installation instructions are: To set up
77 ;; automatic Verilog mode, put this file in your load path, and put
78 ;; the following in code (please un comment it first!) in your
79 ;; .emacs, or in your site's site-load.el
81 ; (autoload 'verilog-mode "verilog-mode" "Verilog mode" t )
82 ; (add-to-list 'auto-mode-alist '("\\.[ds]?vh?\\'" . verilog-mode))
84 ;; Be sure to examine at the help for verilog-auto, and the other
85 ;; verilog-auto-* functions for some major coding time savers.
86 ;;
87 ;; If you want to customize Verilog mode to fit your needs better,
88 ;; you may add the below lines (the values of the variables presented
89 ;; here are the defaults). Note also that if you use an Emacs that
90 ;; supports custom, it's probably better to use the custom menu to
91 ;; edit these. If working as a member of a large team these settings
92 ;; should be common across all users (in a site-start file), or set
93 ;; in Local Variables in every file. Otherwise, different people's
94 ;; AUTO expansion may result different whitespace changes.
95 ;;
96 ; ;; Enable syntax highlighting of **all** languages
97 ; (global-font-lock-mode t)
98 ;
99 ; ;; User customization for Verilog mode
100 ; (setq verilog-indent-level 3
101 ; verilog-indent-level-module 3
102 ; verilog-indent-level-declaration 3
103 ; verilog-indent-level-behavioral 3
104 ; verilog-indent-level-directive 1
105 ; verilog-case-indent 2
106 ; verilog-auto-newline t
107 ; verilog-auto-indent-on-newline t
108 ; verilog-tab-always-indent t
109 ; verilog-auto-endcomments t
110 ; verilog-minimum-comment-distance 40
111 ; verilog-indent-begin-after-if t
112 ; verilog-auto-lineup 'declarations
113 ; verilog-highlight-p1800-keywords nil
114 ; verilog-linter "my_lint_shell_command"
115 ; )
117 ;; \f
119 ;;; History:
120 ;;
121 ;; See commit history at http://www.veripool.org/verilog-mode.html
122 ;; (This section is required to appease checkdoc.)
124 ;;; Code:
126 ;; This variable will always hold the version number of the mode
135 "Inform caller of the version of this file."
139 ;; Insure we have certain packages, and deal with it if we don't
140 ;; Be sure to note which Emacs flavor and version added each feature.
142 ;; Provide stuff if we are XEmacs
150 ;; Bug in 19.28 through 19.30 skeleton.el, not provided.
156 nil ;; fab
162 nil ;; fab
168 nil ;; fab
173 nil ;; great
182 nil ;; great
184 "Return string of text matched by last search, without text properties.
185 NUM specifies which parenthesized expression in the last regexp.
186 Value is nil if NUMth pair didn't match, or there were less than NUM pairs.
187 Zero means the entire text matched by the whole regexp or whole string.
188 STRING should be given if the last search was by `string-match' on STRING."
195 result)
199 )
202 nil ;; We've got what we needed
203 ;; We have the old custom-library, hack around it!
210 )
212 nil ; great!
215 )
218 nil ;; We've got what we needed
219 ;; We have an intermediate custom-library, hack around it!
222 )
228 )
229 ;;
230 ;; OK, do this stuff if we are NOT XEmacs:
235 )
237 ;; Provide a regular expression optimization routine, using regexp-opt
238 ;; if provided by the user's elisp libraries
240 ;; The below were disabled when GNU Emacs 22 was released;
241 ;; perhaps some still need to be there to support Emacs 21.
244 ;; regexp-opt is defined, does it take 3 or 2 arguments?
250 ;with just a two input regexp
252 "Deal with differing number of required arguments for `regexp-opt'.
253 Call 'regexp-opt' on A and B."
256 )
259 "Call 'regexp-opt' on A and B."
261 )
263 ;; We can't tell; assume it takes 2
265 "Call 'regexp-opt' on A and B."
267 )
268 ;; There is no regexp-opt, provide our own
272 )
273 ;; Emacs.
277 ;; Both xemacs and emacs
285 "Call 'regexp-opt' with word delimiters for the words A."
288 "Call 'regexp-opt' with word delimiters for the words A."
289 ;; The FAQ references this function, so user LISP sometimes calls it
293 "Filter `easy-menu-define' MENU to support new features."
296 ;; Xemacs doesn't support :help. Strip it.
297 ;; Recursively filter the a submenu
300 ;; Look for [:help "blah"] and remove
308 out))
310 ;;(verilog-easy-menu-filter
311 ;; `("Verilog" ("MA" ["SAA" nil :help "Help SAA"] ["SAB" nil :help "Help SAA"])
312 ;; "----" ["MB" nil :help "Help MB"]))
315 "Customize variables and other settings used by Verilog-Mode."
320 "Customize fonts used by Verilog-Mode."
326 "Return t if VALUE is boolean.
327 This implements GNU Emacs 22.1's `booleanp' function in earlier Emacs.
328 This function may be removed when Emacs 21 is no longer supported."
332 "Insert the `last-command-event'."
334 ;; XEmacs 21.5 doesn't like last-command-event
335 last-command-char
336 ;; And GNU Emacs 22 has obsoleted last-command-char
337 last-command-event)))
344 "Facilitates easy editing of Verilog source text."
348 ; (defgroup verilog-mode-fonts nil
349 ; "Facilitates easy customization fonts used in Verilog source text"
350 ; :link '(customize-apropos "font-lock-*" 'faces)
351 ; :group 'verilog-mode)
354 "Customize indentation and highlighting of Verilog source text."
358 "Customize actions on Verilog source text."
362 "Customize AUTO actions when expanding Verilog source text."
370 "*Unix program and arguments to call to run a lint checker on Verilog source.
371 Depending on the `verilog-set-compile-command', this may be invoked when
373 you to the next lint error."
376 ;; We don't mark it safe, as it's used as a shell command
380 "*Program and arguments to use to annotate for coverage Verilog source.
381 Depending on the `verilog-set-compile-command', this may be invoked when
383 you to the next lint error."
386 ;; We don't mark it safe, as it's used as a shell command
390 "*Program and arguments to use to interpret Verilog source.
391 Depending on the `verilog-set-compile-command', this may be invoked when
393 you to the next lint error."
396 ;; We don't mark it safe, as it's used as a shell command
400 "*Program and arguments to use to compile Verilog source.
401 Depending on the `verilog-set-compile-command', this may be invoked when
403 you to the next lint error."
406 ;; We don't mark it safe, as it's used as a shell command
409 ;; Very few tools give preprocessed output, so we'll default to Verilog-Perl
410 "vppreproc __FLAGS__ __FILE__"
411 "*Program and arguments to use to preprocess Verilog source.
412 This is invoked with `verilog-preprocess', and depending on the
413 `verilog-set-compile-command', may also be invoked when you type
415 take you to the next lint error."
418 ;; We don't mark it safe, as it's used as a shell command
424 "Which tool to use for building compiler-command.
425 Either nil, `verilog-linter, `verilog-compiler,
426 `verilog-coverage, `verilog-preprocessor, or `verilog-simulator.
431 "*Non-nil means background-highlight code excluded from translation.
434 \(face `verilog-font-lock-translate-off-face').
436 Note: This will slow down on-the-fly fontification (and thus editing).
438 Note: Activate the new setting in a Verilog buffer by re-fontifying it (menu
442 ;; Note we don't use :safe, as that would break on Emacsen before 22.0.
446 "*Type of statements to lineup across multiple lines.
447 If 'all' is selected, then all line ups described below are done.
449 If 'declaration', then just declarations are lined up with any
450 preceding declarations, taking into account widths and the like,
451 so or example the code:
452 reg [31:0] a;
453 reg b;
454 would become
455 reg [31:0] a;
456 reg b;
458 If 'assignment', then assignments are lined up with any preceding
459 assignments, so for example the code
460 a_long_variable <= b + c;
461 d = e + f;
462 would become
463 a_long_variable <= b + c;
464 d = e + f;
466 In order to speed up editing, large blocks of statements are lined up
477 "*Indentation of Verilog statements with respect to containing block."
483 "*Indentation of Module level Verilog statements (eg always, initial).
484 Set to 0 to get initial and always statements lined up on the left side of
485 your screen."
491 "*Indentation of declarations with respect to containing block.
492 Set to 0 to get them list right under containing block."
498 "*How to treat macro expansions in a declaration.
499 If nil, indent as:
500 input [31:0] a;
501 input `CP;
502 output c;
503 If non nil, treat as:
504 input [31:0] a;
505 input `CP ;
506 output c;"
512 "*How to treat indenting items in a list.
513 If t (the default), indent as:
514 always @( posedge a or
515 reset ) begin
517 If nil, treat as:
518 always @( posedge a or
519 reset ) begin"
525 "*Absolute indentation of first begin in a task or function block.
526 Set to 0 to get such code to start at the left side of the screen."
532 "*Indentation to add to each level of `ifdef declarations.
533 Set to 0 to have all directives start at the left side of the screen."
539 "*Indentation of Verilog statements split across lines."
545 "*Indentation for case statements."
551 "*True means automatically newline after semicolons."
557 "*True means automatically indent line after newline."
563 "*True means TAB should always re-indent the current line.
564 A nil value means TAB will only reindent when at the beginning of the line."
570 "*True means TAB moves to the right hand column in preparation for a comment."
576 "*If true, indent begin statements following if, else, while, for and repeat.
577 Otherwise, line them up."
584 "*If true, align `else' under matching `if'.
585 Otherwise else is lined up with first character on line holding matching if."
591 "*Minimum distance (in lines) between begin and end required before a comment.
592 Setting this variable to zero results in every end acquiring a comment; the
593 default avoids too many redundant comments in tight quarters."
599 "*True means highlight words newly reserved by IEEE-1800.
600 These will appear in `verilog-font-lock-p1800-face' in order to gently
601 suggest changing where these words are used as variables to something else.
602 A nil value means highlight these words as appropriate for the SystemVerilog
603 IEEE-1800 standard. Note that changing this will require restarting Emacs
604 to see the effect as font color choices are cached by Emacs."
610 "*True means highlight grouping keywords 'begin' and 'end' more dramatically.
611 If false, these words are in the `font-lock-type-face'; if True then they are in
612 `verilog-font-lock-ams-face'. Some find that special highlighting on these
613 grouping constructs allow the structure of the code to be understood at a glance."
619 "*True means highlight module statements for `verilog-load-file-at-point'.
620 When true, mousing over module names will allow jumping to the
621 module definition. If false, this is not supported. Setting
622 this is experimental, and may lead to bad performance."
628 "*True means highlight module statements for `verilog-load-file-at-point'.
629 When true, mousing over include file names will allow jumping to the
630 file referenced. If false, this is not supported."
636 "*True means insert a comment /* ... */ after 'end's.
637 The name of the function or case will be set between the braces."
643 "*True means ignore signals in {...} concatenations for AUTOWIRE etc.
644 This will exclude signals referenced as pin connections in {...}
645 from AUTOWIRE, AUTOOUTPUT and friends. This flag should be set
646 for backward compatibility only and not set in new designs; it
647 may be removed in future versions."
653 "*True means to automatically read includes before AUTOs.
654 This will do a `verilog-read-defines' and `verilog-read-includes' before
655 each AUTO expansion. This makes it easier to embed defines and includes,
656 but can result in very slow reading times if there are many or large
657 include files."
663 "*Non-nil indicates action to take when saving a Verilog buffer with AUTOs.
666 automatically when it thinks necessary. A value of `ask' will query the
667 user when it thinks updating is needed.
669 You should not rely on the 'ask or 'detect policies, they are safeguards
670 only. They do not detect when AUTOINSTs need to be updated because a
671 sub-module's port list has changed."
676 "*Non-nil indicates to expand a SystemVerilog .* instance ports.
677 They will be expanded in the same way as if there was a AUTOINST in the
678 instantiation. See also `verilog-auto-star' and `verilog-auto-star-save'."
684 "*Non-nil indicates to save to disk SystemVerilog .* instance expansions.
685 A nil value indicates direct connections will be removed before saving.
686 Only meaningful to those created due to `verilog-auto-star-expand' being set.
688 Instead of setting this, you may want to use /*AUTOINST*/, which will
689 always be saved."
700 ;;; Compile support
705 '(
717 "\
733 "^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 1 2)
734 )
735 "List of regexps for Verilog compilers.
739 ;; Emacs form is '((v-tool "re" 1 2) ...)
740 ;; XEmacs form is '(verilog ("re" 1 2) ...)
741 ;; So we can just map from Emacs to Xemacs
743 "List of regexps for Verilog compilers.
747 '(
748 ;; verilog-xl-1
751 ;; verilog-xl-2
754 ;; verilog-IES (nc-verilog)
757 ;; verilog-surefire-1
760 ;; verilog-surefire-2
763 ;; verilog-verbose
770 ;; verilog-vcs-1
773 ;; verilog-vcs-2
776 ;; verilog-vcs-3
779 ;; verilog-vcs-4
782 ;; verilog-verilator
785 ;; verilog-leda
786 ("^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 1 bold t)
787 ("^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 2 bold t)
788 )
789 "*Keywords to also highlight in Verilog *compilation* buffers.
793 "*List of standard Verilog arguments to use for /*AUTOINST*/.
794 These arguments are used to find files for `verilog-auto', and match
795 the flags accepted by a standard Verilog-XL simulator.
797 -f filename Reads more `verilog-library-flags' from the filename.
798 +incdir+dir Adds the directory to `verilog-library-directories'.
799 -Idir Adds the directory to `verilog-library-directories'.
800 -y dir Adds the directory to `verilog-library-directories'.
801 +libext+.v Adds the extensions to `verilog-library-extensions'.
802 -v filename Adds the filename to `verilog-library-files'.
804 filename Adds the filename to `verilog-library-files'.
805 This is not recommended, -v is a better choice.
807 You might want these defined in each file; put at the *END* of your file
808 something like:
810 // Local Variables:
812 // End:
814 Verilog-mode attempts to detect changes to this local variable, but they
815 are only insured to be correct when the file is first visited. Thus if you
818 See also the variables mentioned above."
824 "*List of directories when looking for files for /*AUTOINST*/.
825 The directory may be relative to the current file, or absolute.
826 Environment variables are also expanded in the directory names.
827 Having at least the current directory is a good idea.
829 You might want these defined in each file; put at the *END* of your file
830 something like:
832 // Local Variables:
834 // End:
836 Verilog-mode attempts to detect changes to this local variable, but they
837 are only insured to be correct when the file is first visited. Thus if you
840 See also `verilog-library-flags', `verilog-library-files'
841 and `verilog-library-extensions'."
847 "*List of files to search for modules.
848 AUTOINST will use this when it needs to resolve a module name.
849 This is a complete path, usually to a technology file with many standard
850 cells defined in it.
852 You might want these defined in each file; put at the *END* of your file
853 something like:
855 // Local Variables:
857 // End:
859 Verilog-mode attempts to detect changes to this local variable, but they
860 are only insured to be correct when the file is first visited. Thus if you
863 See also `verilog-library-flags', `verilog-library-directories'."
869 "*List of extensions to use when looking for files for /*AUTOINST*/.
870 See also `verilog-library-flags', `verilog-library-directories'."
876 "*If set, treat signals matching this regexp as active low.
877 This is used for AUTORESET and AUTOTIEOFF. For proper behavior,
878 you will probably also need `verilog-auto-reset-widths' set."
884 "*If true, AUTOSENSE should include all inputs.
885 If nil, only inputs that are NOT output signals in the same block are
886 included."
892 "*If true, AUTOSENSE should assume all defines represent constants.
893 When true, the defines will not be included in sensitivity lists. To
894 maintain compatibility with other sites, this should be set at the bottom
895 of each Verilog file that requires it, rather than being set globally."
901 "*If true, AUTORESET should determine the width of signals.
902 This is then used to set the width of the zero (32'h0 for example). This
903 is required by some lint tools that aren't smart enough to ignore widths of
904 the constant zero. This may result in ugly code when parameters determine
905 the MSB or LSB of a signal inside an AUTORESET."
911 "*Text used for delays in delayed assignments. Add a trailing space if set."
917 "*If set, AUTOARG signal names will be sorted, not in delaration order.
918 Declaration order is advantageous with order based instantiations
919 and is the default for backward compatibility. Sorted order
920 reduces changes when declarations are moved around in a file, and
921 it's bad practice to rely on order based instantiations anyhow."
927 "*If true, when creating ports with AUTOINST, use .name syntax.
929 This is only legal in SystemVerilog files, and will confuse older
930 simulators. Setting `verilog-auto-inst-vector' to nil may also
931 be desirable to increase how often .name will be used."
937 "*If set, AUTOINST will replace parameters with the parameter value.
938 If nil, leave parameters as symbolic names.
940 Parameters must be in Verilog 2001 format #(...), and if a parameter is not
941 listed as such there (as when the default value is acceptable), it will not
942 be replaced, and will remain symbolic.
944 For example, imagine a submodule uses parameters to declare the size of its
945 inputs. This is then used by a upper module:
947 module InstModule (o,i);
948 parameter WIDTH;
949 input [WIDTH-1:0] i;
950 endmodule
952 module ExampInst;
953 InstModule
954 #(PARAM(10))
955 instName
956 (/*AUTOINST*/
957 .i (i[PARAM-1:0]));
959 Note even though PARAM=10, the AUTOINST has left the parameter as a
960 symbolic name. If `verilog-auto-inst-param-value' is set, this will
961 instead expand to:
963 module ExampInst;
964 InstModule
965 #(PARAM(10))
966 instName
967 (/*AUTOINST*/
968 .i (i[9:0]));"
974 "*If true, when creating default ports with AUTOINST, use bus subscripts.
975 If nil, skip the subscript when it matches the entire bus as declared in
976 the module (AUTOWIRE signals always are subscripted, you must manually
977 declare the wire to have the subscripts removed.) Setting this to nil may
978 speed up some simulators, but is less general and harder to read, so avoid."
984 "*If true, when creating templated ports with AUTOINST, add a comment.
985 The comment will add the line number of the template that was used for that
986 port declaration. Setting this aids in debugging, but nil is suggested for
987 regular use to prevent large numbers of merge conflicts."
993 "*Indent-to column number for net name part of AUTOINST created pin."
999 "*If set, when creating AUTOINPUT list, ignore signals matching this regexp.
1006 "*If set, when creating AUTOINOUT list, ignore signals matching this regexp.
1013 "*If set, when creating AUTOOUTPUT list, ignore signals matching this regexp.
1020 "*If set, when creating AUTOTIEOFF list, ignore signals matching this regexp.
1027 "*If set, when creating AUTOUNUSED list, ignore signals matching this regexp.
1034 "*If non-nil, regular expression that matches Verilog-2001 typedef names.
1041 "*Hook run after Verilog mode is loaded."
1046 "*Hook run after `verilog-mode' updates AUTOs."
1051 "*Hook run before `verilog-mode' updates AUTOs."
1056 "*Hook run after `verilog-mode' deletes AUTOs."
1061 "*Hook run before `verilog-mode' deletes AUTOs."
1066 "*Hook run after `verilog-getopt-flags' determines the Verilog option lists."
1071 "*Hook run before `verilog-getopt-flags' determines the Verilog option lists."
1080 ;;
1081 ;; provide a verilog-header function.
1082 ;; Customization variables:
1083 ;;
1085 "*If non-nil, dates are written in scientific format (e.g. 1997/09/17).
1086 If nil, in European format (e.g. 17.09.1997). The brain-dead American
1090 "*Default name of Company for Verilog header.
1095 "*Default name of Project for Verilog header.
1104 ;;(define-key map "=" 'electric-verilog-equal)
1108 ;; backspace/delete key bindings
1110 (unless (boundp 'delete-key-deletes-forward) ; XEmacs variable
1111 (define-key map [delete] 'delete-char)
1112 (define-key map [(meta delete)] 'kill-word))
1113 (define-key map "\M-\C-b" 'electric-verilog-backward-sexp)
1114 (define-key map "\M-\C-f" 'electric-verilog-forward-sexp)
1117 (define-key map "\M-?" 'verilog-show-completions)
1118 (define-key map "\C-c\`" 'verilog-lint-off)
1119 (define-key map "\C-c\*" 'verilog-delete-auto-star-implicit)
1120 (define-key map "\C-c\C-r" 'verilog-label-be)
1121 (define-key map "\C-c\C-i" 'verilog-pretty-declarations)
1122 (define-key map "\C-c=" 'verilog-pretty-expr)
1123 (define-key map "\C-c\C-b" 'verilog-submit-bug-report)
1124 (define-key map "\M-*" 'verilog-star-comment)
1125 (define-key map "\C-c\C-c" 'verilog-comment-region)
1126 (define-key map "\C-c\C-u" 'verilog-uncomment-region)
1127 (when (featurep 'xemacs)
1128 (define-key map [(meta control h)] 'verilog-mark-defun)
1129 (define-key map "\M-\C-a" 'verilog-beg-of-defun)
1130 (define-key map "\M-\C-e" 'verilog-end-of-defun))
1131 (define-key map "\C-c\C-d" 'verilog-goto-defun)
1132 (define-key map "\C-c\C-k" 'verilog-delete-auto)
1133 (define-key map "\C-c\C-a" 'verilog-auto)
1134 (define-key map "\C-c\C-s" 'verilog-auto-save-compile)
1135 (define-key map "\C-c\C-p" 'verilog-preprocess)
1136 (define-key map "\C-c\C-z" 'verilog-inject-auto)
1137 (define-key map "\C-c\C-e" 'verilog-expand-vector)
1138 (define-key map "\C-c\C-h" 'verilog-header)
1139 map)
1140 "Keymap used in Verilog mode.")
1142 ;; menus
1143 (easy-menu-define
1144 verilog-menu verilog-mode-map "Menu for Verilog mode"
1145 (verilog-easy-menu-filter
1146 '("Verilog"
1147 ("Choose Compilation Action"
1148 ["None"
1149 (progn
1150 (setq verilog-tool nil)
1151 (verilog-set-compile-command))
1152 :style radio
1153 :selected (equal verilog-tool nil)
1154 :help "When invoking compilation, use compile-command"]
1155 ["Lint"
1156 (progn
1157 (setq verilog-tool 'verilog-linter)
1158 (verilog-set-compile-command))
1159 :style radio
1160 :selected (equal verilog-tool `verilog-linter)
1161 :help "When invoking compilation, use lint checker"]
1162 ["Coverage"
1163 (progn
1164 (setq verilog-tool 'verilog-coverage)
1165 (verilog-set-compile-command))
1166 :style radio
1167 :selected (equal verilog-tool `verilog-coverage)
1168 :help "When invoking compilation, annotate for coverage"]
1169 ["Simulator"
1170 (progn
1171 (setq verilog-tool 'verilog-simulator)
1172 (verilog-set-compile-command))
1173 :style radio
1174 :selected (equal verilog-tool `verilog-simulator)
1175 :help "When invoking compilation, interpret Verilog source"]
1176 ["Compiler"
1177 (progn
1178 (setq verilog-tool 'verilog-compiler)
1179 (verilog-set-compile-command))
1180 :style radio
1181 :selected (equal verilog-tool `verilog-compiler)
1182 :help "When invoking compilation, compile Verilog source"]
1183 ["Preprocessor"
1184 (progn
1185 (setq verilog-tool 'verilog-preprocessor)
1186 (verilog-set-compile-command))
1187 :style radio
1188 :selected (equal verilog-tool `verilog-preprocessor)
1189 :help "When invoking compilation, preprocess Verilog source, see also `verilog-preprocess'"]
1190 )
1191 ("Move"
1192 ["Beginning of function" verilog-beg-of-defun
1193 :keys "C-M-a"
1194 :help "Move backward to the beginning of the current function or procedure"]
1195 ["End of function" verilog-end-of-defun
1196 :keys "C-M-e"
1197 :help "Move forward to the end of the current function or procedure"]
1198 ["Mark function" verilog-mark-defun
1199 :keys "C-M-h"
1200 :help "Mark the current Verilog function or procedure"]
1201 ["Goto function/module" verilog-goto-defun
1202 :help "Move to specified Verilog module/task/function"]
1203 ["Move to beginning of block" electric-verilog-backward-sexp
1204 :help "Move backward over one balanced expression"]
1205 ["Move to end of block" electric-verilog-forward-sexp
1206 :help "Move forward over one balanced expression"]
1207 )
1208 ("Comments"
1209 ["Comment Region" verilog-comment-region
1210 :help "Put marked area into a comment"]
1211 ["UnComment Region" verilog-uncomment-region
1212 :help "Uncomment an area commented with Comment Region"]
1213 ["Multi-line comment insert" verilog-star-comment
1214 :help "Insert Verilog /* */ comment at point"]
1215 ["Lint error to comment" verilog-lint-off
1216 :help "Convert a Verilog linter warning line into a disable statement"]
1217 )
1218 "----"
1219 ["Compile" compile
1220 :help "Perform compilation-action (above) on the current buffer"]
1221 ["AUTO, Save, Compile" verilog-auto-save-compile
1222 :help "Recompute AUTOs, save buffer, and compile"]
1223 ["Next Compile Error" next-error
1224 :help "Visit next compilation error message and corresponding source code"]
1225 ["Ignore Lint Warning at point" verilog-lint-off
1226 :help "Convert a Verilog linter warning line into a disable statement"]
1227 "----"
1228 ["Line up declarations around point" verilog-pretty-declarations
1229 :help "Line up declarations around point"]
1230 ["Line up equations around point" verilog-pretty-expr
1231 :help "Line up expressions around point"]
1232 ["Redo/insert comments on every end" verilog-label-be
1233 :help "Label matching begin ... end statements"]
1234 ["Expand [x:y] vector line" verilog-expand-vector
1235 :help "Take a signal vector on the current line and expand it to multiple lines"]
1236 ["Insert begin-end block" verilog-insert-block
1237 :help "Insert begin ... end"]
1238 ["Complete word" verilog-complete-word
1239 :help "Complete word at point"]
1240 "----"
1241 ["Recompute AUTOs" verilog-auto
1242 :help "Expand AUTO meta-comment statements"]
1243 ["Kill AUTOs" verilog-delete-auto
1244 :help "Remove AUTO expansions"]
1245 ["Inject AUTOs" verilog-inject-auto
1246 :help "Inject AUTOs into legacy non-AUTO buffer"]
1247 ("AUTO Help..."
1248 ["AUTO General" (describe-function 'verilog-auto)
1249 :help "Help introduction on AUTOs"]
1250 ["AUTO Library Flags" (describe-variable 'verilog-library-flags)
1251 :help "Help on verilog-library-flags"]
1252 ["AUTO Library Path" (describe-variable 'verilog-library-directories)
1253 :help "Help on verilog-library-directories"]
1254 ["AUTO Library Files" (describe-variable 'verilog-library-files)
1255 :help "Help on verilog-library-files"]
1256 ["AUTO Library Extensions" (describe-variable 'verilog-library-extensions)
1257 :help "Help on verilog-library-extensions"]
1258 ["AUTO `define Reading" (describe-function 'verilog-read-defines)
1259 :help "Help on reading `defines"]
1260 ["AUTO `include Reading" (describe-function 'verilog-read-includes)
1261 :help "Help on parsing `includes"]
1262 ["AUTOARG" (describe-function 'verilog-auto-arg)
1263 :help "Help on AUTOARG - declaring module port list"]
1264 ["AUTOASCIIENUM" (describe-function 'verilog-auto-ascii-enum)
1265 :help "Help on AUTOASCIIENUM - creating ASCII for enumerations"]
1266 ["AUTOINOUTCOMP" (describe-function 'verilog-auto-inout-comp)
1267 :help "Help on AUTOINOUTCOMP - copying complemented i/o from another file"]
1268 ["AUTOINOUTMODULE" (describe-function 'verilog-auto-inout-module)
1269 :help "Help on AUTOINOUTMODULE - copying i/o from another file"]
1270 ["AUTOINSERTLISP" (describe-function 'verilog-auto-insert-lisp)
1271 :help "Help on AUTOINSERTLISP - insert text from a lisp function"]
1272 ["AUTOINOUT" (describe-function 'verilog-auto-inout)
1273 :help "Help on AUTOINOUT - adding inouts from cells"]
1274 ["AUTOINPUT" (describe-function 'verilog-auto-input)
1275 :help "Help on AUTOINPUT - adding inputs from cells"]
1276 ["AUTOINST" (describe-function 'verilog-auto-inst)
1277 :help "Help on AUTOINST - adding pins for cells"]
1278 ["AUTOINST (.*)" (describe-function 'verilog-auto-star)
1279 :help "Help on expanding Verilog-2001 .* pins"]
1280 ["AUTOINSTPARAM" (describe-function 'verilog-auto-inst-param)
1281 :help "Help on AUTOINSTPARAM - adding parameter pins to cells"]
1282 ["AUTOOUTPUT" (describe-function 'verilog-auto-output)
1283 :help "Help on AUTOOUTPUT - adding outputs from cells"]
1284 ["AUTOOUTPUTEVERY" (describe-function 'verilog-auto-output-every)
1285 :help "Help on AUTOOUTPUTEVERY - adding outputs of all signals"]
1286 ["AUTOREG" (describe-function 'verilog-auto-reg)
1287 :help "Help on AUTOREG - declaring registers for non-wires"]
1288 ["AUTOREGINPUT" (describe-function 'verilog-auto-reg-input)
1289 :help "Help on AUTOREGINPUT - declaring inputs for non-wires"]
1290 ["AUTORESET" (describe-function 'verilog-auto-reset)
1291 :help "Help on AUTORESET - resetting always blocks"]
1292 ["AUTOSENSE" (describe-function 'verilog-auto-sense)
1293 :help "Help on AUTOSENSE - sensitivity lists for always blocks"]
1294 ["AUTOTIEOFF" (describe-function 'verilog-auto-tieoff)
1295 :help "Help on AUTOTIEOFF - tieing off unused outputs"]
1296 ["AUTOUNUSED" (describe-function 'verilog-auto-unused)
1297 :help "Help on AUTOUNUSED - terminating unused inputs"]
1298 ["AUTOWIRE" (describe-function 'verilog-auto-wire)
1299 :help "Help on AUTOWIRE - declaring wires for cells"]
1300 )
1301 "----"
1302 ["Submit bug report" verilog-submit-bug-report
1303 :help "Submit via mail a bug report on verilog-mode.el"]
1304 ["Version and FAQ" verilog-faq
1305 :help "Show the current version, and where to get the FAQ etc"]
1306 ["Customize Verilog Mode..." verilog-customize
1307 :help "Customize variables and other settings used by Verilog-Mode"]
1308 ["Customize Verilog Fonts & Colors" verilog-font-customize
1309 :help "Customize fonts used by Verilog-Mode."])))
1311 (easy-menu-define
1312 verilog-stmt-menu verilog-mode-map "Menu for statement templates in Verilog."
1313 (verilog-easy-menu-filter
1314 '("Statements"
1315 ["Header" verilog-sk-header
1316 :help "Insert a header block at the top of file"]
1317 ["Comment" verilog-sk-comment
1318 :help "Insert a comment block"]
1319 "----"
1320 ["Module" verilog-sk-module
1321 :help "Insert a module .. (/*AUTOARG*/);.. endmodule block"]
1322 ["Primitive" verilog-sk-primitive
1323 :help "Insert a primitive .. (.. );.. endprimitive block"]
1324 "----"
1325 ["Input" verilog-sk-input
1326 :help "Insert an input declaration"]
1327 ["Output" verilog-sk-output
1328 :help "Insert an output declaration"]
1329 ["Inout" verilog-sk-inout
1330 :help "Insert an inout declaration"]
1331 ["Wire" verilog-sk-wire
1332 :help "Insert a wire declaration"]
1333 ["Reg" verilog-sk-reg
1334 :help "Insert a register declaration"]
1335 ["Define thing under point as a register" verilog-sk-define-signal
1336 :help "Define signal under point as a register at the top of the module"]
1337 "----"
1338 ["Initial" verilog-sk-initial
1339 :help "Insert an initial begin .. end block"]
1340 ["Always" verilog-sk-always
1341 :help "Insert an always @(AS) begin .. end block"]
1342 ["Function" verilog-sk-function
1343 :help "Insert a function .. begin .. end endfunction block"]
1344 ["Task" verilog-sk-task
1345 :help "Insert a task .. begin .. end endtask block"]
1346 ["Specify" verilog-sk-specify
1347 :help "Insert a specify .. endspecify block"]
1348 ["Generate" verilog-sk-generate
1349 :help "Insert a generate .. endgenerate block"]
1350 "----"
1351 ["Begin" verilog-sk-begin
1352 :help "Insert a begin .. end block"]
1353 ["If" verilog-sk-if
1354 :help "Insert an if (..) begin .. end block"]
1355 ["(if) else" verilog-sk-else-if
1356 :help "Insert an else if (..) begin .. end block"]
1357 ["For" verilog-sk-for
1358 :help "Insert a for (...) begin .. end block"]
1359 ["While" verilog-sk-while
1360 :help "Insert a while (...) begin .. end block"]
1361 ["Fork" verilog-sk-fork
1362 :help "Insert a fork begin .. end .. join block"]
1363 ["Repeat" verilog-sk-repeat
1364 :help "Insert a repeat (..) begin .. end block"]
1365 ["Case" verilog-sk-case
1366 :help "Insert a case block, prompting for details"]
1367 ["Casex" verilog-sk-casex
1368 :help "Insert a casex (...) item: begin.. end endcase block"]
1369 ["Casez" verilog-sk-casez
1370 :help "Insert a casez (...) item: begin.. end endcase block"])))
1372 (defvar verilog-mode-abbrev-table nil
1373 "Abbrev table in use in Verilog-mode buffers.")
1375 (define-abbrev-table 'verilog-mode-abbrev-table ())
1377 ;;
1378 ;; Macros
1379 ;;
1381 (defsubst verilog-get-beg-of-line (&optional arg)
1382 (save-excursion
1383 (beginning-of-line arg)
1384 (point)))
1386 (defsubst verilog-get-end-of-line (&optional arg)
1387 (save-excursion
1388 (end-of-line arg)
1389 (point)))
1391 (defsubst verilog-within-string ()
1392 (save-excursion
1393 (nth 3 (parse-partial-sexp (verilog-get-beg-of-line) (point)))))
1395 (defsubst verilog-string-replace-matches (from-string to-string fixedcase literal string)
1396 "Replace occurrences of FROM-STRING with TO-STRING.
1397 FIXEDCASE and LITERAL as in `replace-match`. STRING is what to replace.
1399 will break, as the o's continuously replace. xa -> x works ok though."
1400 ;; Hopefully soon to a emacs built-in
1401 (let ((start 0))
1402 (while (string-match from-string string start)
1403 (setq string (replace-match to-string fixedcase literal string)
1404 start (min (length string) (+ (match-beginning 0) (length to-string)))))
1405 string))
1407 (defsubst verilog-string-remove-spaces (string)
1408 "Remove spaces surrounding STRING."
1409 (save-match-data
1412 string))
1414 (defsubst verilog-re-search-forward (REGEXP BOUND NOERROR)
1415 ; checkdoc-params: (REGEXP BOUND NOERROR)
1416 "Like `re-search-forward', but skips over match in comments or strings."
1417 (let ((mdata '(nil nil))) ;; So match-end will return nil if no matches found
1418 (while (and
1419 (re-search-forward REGEXP BOUND NOERROR)
1420 (setq mdata (match-data))
1421 (and (verilog-skip-forward-comment-or-string)
1422 (progn
1423 (setq mdata '(nil nil))
1424 (if BOUND
1425 (< (point) BOUND)
1426 t)))))
1427 (store-match-data mdata)
1428 (match-end 0)))
1430 (defsubst verilog-re-search-backward (REGEXP BOUND NOERROR)
1431 ; checkdoc-params: (REGEXP BOUND NOERROR)
1432 "Like `re-search-backward', but skips over match in comments or strings."
1433 (let ((mdata '(nil nil))) ;; So match-end will return nil if no matches found
1434 (while (and
1435 (re-search-backward REGEXP BOUND NOERROR)
1436 (setq mdata (match-data))
1437 (and (verilog-skip-backward-comment-or-string)
1438 (progn
1439 (setq mdata '(nil nil))
1440 (if BOUND
1441 (> (point) BOUND)
1442 t)))))
1443 (store-match-data mdata)
1444 (match-end 0)))
1446 (defsubst verilog-re-search-forward-quick (regexp bound noerror)
1447 "Like `verilog-re-search-forward', including use of REGEXP BOUND and NOERROR,
1448 but trashes match data and is faster for REGEXP that doesn't match often.
1449 This may at some point use text properties to ignore comments,
1450 so there may be a large up front penalty for the first search."
1451 (let (pt)
1452 (while (and (not pt)
1453 (re-search-forward regexp bound noerror))
1454 (if (not (verilog-inside-comment-p))
1455 (setq pt (match-end 0))))
1456 pt))
1458 (defsubst verilog-re-search-backward-quick (regexp bound noerror)
1459 ; checkdoc-params: (REGEXP BOUND NOERROR)
1460 "Like `verilog-re-search-backward', including use of REGEXP BOUND and NOERROR,
1461 but trashes match data and is faster for REGEXP that doesn't match often.
1462 This may at some point use text properties to ignore comments,
1463 so there may be a large up front penalty for the first search."
1464 (let (pt)
1465 (while (and (not pt)
1466 (re-search-backward regexp bound noerror))
1467 (if (not (verilog-inside-comment-p))
1468 (setq pt (match-end 0))))
1469 pt))
1471 (defsubst verilog-re-search-forward-substr (substr regexp bound noerror)
1472 "Like `re-search-forward', but first search for SUBSTR constant.
1473 Then searched for the normal REGEXP (which contains SUBSTR), with given
1474 BOUND and NOERROR. The REGEXP must fit within a single line.
1475 This speeds up complicated regexp matches."
1476 ;; Problem with overlap: search-forward BAR then FOOBARBAZ won't match.
1477 ;; thus require matches to be on one line, and use beginning-of-line.
1478 (let (done)
1479 (while (and (not done)
1480 (search-forward substr bound noerror))
1481 (save-excursion
1482 (beginning-of-line)
1483 (setq done (re-search-forward regexp (verilog-get-end-of-line) noerror)))
1484 (unless (and (<= (match-beginning 0) (point))
1485 (>= (match-end 0) (point)))
1486 (setq done nil)))
1487 (when done (goto-char done))
1488 done))
1489 ;;(verilog-re-search-forward-substr "-end" "get-end-of" nil t) ;;-end (test bait)
1491 (defsubst verilog-re-search-backward-substr (substr regexp bound noerror)
1492 "Like `re-search-backward', but first search for SUBSTR constant.
1493 Then searched for the normal REGEXP (which contains SUBSTR), with given
1494 BOUND and NOERROR. The REGEXP must fit within a single line.
1495 This speeds up complicated regexp matches."
1496 ;; Problem with overlap: search-backward BAR then FOOBARBAZ won't match.
1497 ;; thus require matches to be on one line, and use beginning-of-line.
1498 (let (done)
1499 (while (and (not done)
1500 (search-backward substr bound noerror))
1501 (save-excursion
1502 (end-of-line)
1503 (setq done (re-search-backward regexp (verilog-get-beg-of-line) noerror)))
1504 (unless (and (<= (match-beginning 0) (point))
1505 (>= (match-end 0) (point)))
1506 (setq done nil)))
1507 (when done (goto-char done))
1508 done))
1509 ;;(verilog-re-search-backward-substr "-end" "get-end-of" nil t) ;;-end (test bait)
1511 (defvar compile-command)
1513 ;; compilation program
1514 (defun verilog-set-compile-command ()
1515 "Function to compute shell command to compile Verilog.
1517 This reads `verilog-tool' and sets `compile-command'. This specifies the
1521 By default `verilog-tool' uses a Makefile if one exists in the
1522 current directory. If not, it is set to the `verilog-linter',
1523 `verilog-compiler', `verilog-coverage', `verilog-preprocessor',
1524 or `verilog-simulator' variables, as selected with the Verilog ->
1527 You should set `verilog-tool' or the other variables to the path and
1528 arguments for your Verilog simulator. For example:
1530 or a string like:
1533 In the former case, the path to the current buffer is concat'ed to the
1534 value of `verilog-tool'; in the later, the path to the current buffer is
1535 substituted for the %s.
1537 Where __FLAGS__ appears in the string `verilog-current-flags'
1538 will be substituted.
1540 Where __FILE__ appears in the string, the variable
1541 `buffer-file-name' of the current buffer, without the directory
1542 portion, will be substituted."
1543 (interactive)
1544 (cond
1545 ((or (file-exists-p "makefile") ;If there is a makefile, use it
1546 (file-exists-p "Makefile"))
1547 (make-local-variable 'compile-command)
1548 (setq compile-command "make "))
1549 (t
1550 (make-local-variable 'compile-command)
1551 (setq compile-command
1552 (if verilog-tool
1553 (if (string-match "%s" (eval verilog-tool))
1554 (format (eval verilog-tool) (or buffer-file-name ""))
1555 (concat (eval verilog-tool) " " (or buffer-file-name "")))
1556 ""))))
1557 (verilog-modify-compile-command))
1559 (defun verilog-expand-command (command)
1560 "Replace meta-information in COMMAND and return it.
1561 Where __FLAGS__ appears in the string `verilog-current-flags'
1562 will be substituted. Where __FILE__ appears in the string, the
1563 current buffer's file-name, without the directory portion, will
1564 be substituted."
1565 (setq command (verilog-string-replace-matches
1568 t t command))
1569 (setq command (verilog-string-replace-matches
1571 (or (buffer-file-name) ""))
1572 t t command))
1573 command)
1575 (defun verilog-modify-compile-command ()
1576 "Update `compile-command' using `verilog-expand-command'."
1577 (when (and
1578 (stringp compile-command)
1580 (make-local-variable 'compile-command)
1581 (setq compile-command (verilog-expand-command compile-command))))
1583 (if (featurep 'xemacs)
1584 ;; Following code only gets called from compilation-mode-hook on XEmacs to add error handling.
1585 (defun verilog-error-regexp-add-xemacs ()
1586 "Teach XEmacs about verilog errors.
1588 find the errors."
1589 (interactive)
1590 (if (boundp 'compilation-error-regexp-systems-alist)
1591 (if (and
1592 (not (equal compilation-error-regexp-systems-list 'all))
1593 (not (member compilation-error-regexp-systems-list 'verilog)))
1594 (push 'verilog compilation-error-regexp-systems-list)))
1595 (if (boundp 'compilation-error-regexp-alist-alist)
1596 (if (not (assoc 'verilog compilation-error-regexp-alist-alist))
1597 (setcdr compilation-error-regexp-alist-alist
1598 (cons verilog-error-regexp-xemacs-alist
1599 (cdr compilation-error-regexp-alist-alist)))))
1600 (if (boundp 'compilation-font-lock-keywords)
1601 (progn
1602 (make-local-variable 'compilation-font-lock-keywords)
1603 (setq compilation-font-lock-keywords verilog-error-font-lock-keywords)
1604 (font-lock-set-defaults)))
1605 ;; Need to re-run compilation-error-regexp builder
1606 (if (fboundp 'compilation-build-compilation-error-regexp-alist)
1607 (compilation-build-compilation-error-regexp-alist))
1608 ))
1610 ;; Following code only gets called from compilation-mode-hook on Emacs to add error handling.
1611 (defun verilog-error-regexp-add-emacs ()
1612 "Tell Emacs compile that we are Verilog.
1614 find the errors."
1615 (interactive)
1616 (if (boundp 'compilation-error-regexp-alist-alist)
1617 (progn
1618 (if (not (assoc 'verilog-xl-1 compilation-error-regexp-alist-alist))
1619 (mapcar
1620 (lambda (item)
1621 (push (car item) compilation-error-regexp-alist)
1622 (push item compilation-error-regexp-alist-alist)
1623 )
1624 verilog-error-regexp-emacs-alist)))))
1626 (if (featurep 'xemacs) (add-hook 'compilation-mode-hook 'verilog-error-regexp-add-xemacs))
1627 (if (featurep 'emacs) (add-hook 'compilation-mode-hook 'verilog-error-regexp-add-emacs))
1629 (defconst verilog-directive-re
1630 (eval-when-compile
1631 (verilog-regexp-words
1632 '(
1633 "`case" "`default" "`define" "`else" "`elsif" "`endfor" "`endif"
1634 "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef"
1635 "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale"
1636 "`time_scale" "`undef" "`while" ))))
1638 (defconst verilog-directive-re-1
1641 (defconst verilog-directive-begin
1644 (defconst verilog-directive-middle
1647 (defconst verilog-directive-end
1650 (defconst verilog-ovm-begin-re
1651 (eval-when-compile
1652 (verilog-regexp-opt
1653 '(
1654 "`ovm_component_utils_begin"
1655 "`ovm_component_param_utils_begin"
1656 "`ovm_field_utils_begin"
1657 "`ovm_object_utils_begin"
1658 "`ovm_object_param_utils_begin"
1659 "`ovm_sequence_utils_begin"
1660 "`ovm_sequencer_utils_begin"
1661 ) nil )))
1663 (defconst verilog-ovm-end-re
1664 (eval-when-compile
1665 (verilog-regexp-opt
1666 '(
1667 "`ovm_component_utils_end"
1668 "`ovm_field_utils_end"
1669 "`ovm_object_utils_end"
1670 "`ovm_sequence_utils_end"
1671 "`ovm_sequencer_utils_end"
1672 ) nil )))
1674 (defconst verilog-vmm-begin-re
1675 (eval-when-compile
1676 (verilog-regexp-opt
1677 '(
1678 "`vmm_data_member_begin"
1679 "`vmm_env_member_begin"
1680 "`vmm_scenario_member_begin"
1681 "`vmm_subenv_member_begin"
1682 "`vmm_xactor_member_begin"
1683 ) nil ) ) )
1685 (defconst verilog-vmm-end-re
1686 (eval-when-compile
1687 (verilog-regexp-opt
1688 '(
1689 "`vmm_data_member_end"
1690 "`vmm_env_member_end"
1691 "`vmm_scenario_member_end"
1692 "`vmm_subenv_member_end"
1693 "`vmm_xactor_member_end"
1694 ) nil ) ) )
1696 (defconst verilog-vmm-statement-re
1697 (eval-when-compile
1698 (verilog-regexp-opt
1699 '(
1700 ;; "`vmm_xactor_member_enum_array"
1701 "`vmm_\\(data\\|env\\|scenario\\|subenv\\|xactor\\)_member_\\(scalar\\|string\\|enum\\|vmm_data\\|channel\\|xactor\\|subenv\\|user_defined\\)\\(_array\\)?"
1702 ;; "`vmm_xactor_member_scalar_array"
1703 ;; "`vmm_xactor_member_scalar"
1704 ) nil )))
1706 (defconst verilog-ovm-statement-re
1707 (eval-when-compile
1708 (verilog-regexp-opt
1709 '(
1710 ;; Statements
1711 "`DUT_ERROR"
1712 "`MESSAGE"
1713 "`dut_error"
1714 "`message"
1715 "`ovm_analysis_imp_decl"
1716 "`ovm_blocking_get_imp_decl"
1717 "`ovm_blocking_get_peek_imp_decl"
1718 "`ovm_blocking_master_imp_decl"
1719 "`ovm_blocking_peek_imp_decl"
1720 "`ovm_blocking_put_imp_decl"
1721 "`ovm_blocking_slave_imp_decl"
1722 "`ovm_blocking_transport_imp_decl"
1723 "`ovm_component_registry"
1724 "`ovm_component_registry_param"
1725 "`ovm_component_utils"
1726 "`ovm_create"
1727 "`ovm_create_seq"
1728 "`ovm_declare_sequence_lib"
1729 "`ovm_do"
1730 "`ovm_do_seq"
1731 "`ovm_do_seq_with"
1732 "`ovm_do_with"
1733 "`ovm_error"
1734 "`ovm_fatal"
1735 "`ovm_field_aa_int_byte"
1736 "`ovm_field_aa_int_byte_unsigned"
1737 "`ovm_field_aa_int_int"
1738 "`ovm_field_aa_int_int_unsigned"
1739 "`ovm_field_aa_int_integer"
1740 "`ovm_field_aa_int_integer_unsigned"
1741 "`ovm_field_aa_int_key"
1742 "`ovm_field_aa_int_longint"
1743 "`ovm_field_aa_int_longint_unsigned"
1744 "`ovm_field_aa_int_shortint"
1745 "`ovm_field_aa_int_shortint_unsigned"
1746 "`ovm_field_aa_int_string"
1747 "`ovm_field_aa_object_int"
1748 "`ovm_field_aa_object_string"
1749 "`ovm_field_aa_string_int"
1750 "`ovm_field_aa_string_string"
1751 "`ovm_field_array_int"
1752 "`ovm_field_array_object"
1753 "`ovm_field_array_string"
1754 "`ovm_field_enum"
1755 "`ovm_field_event"
1756 "`ovm_field_int"
1757 "`ovm_field_object"
1758 "`ovm_field_queue_int"
1759 "`ovm_field_queue_object"
1760 "`ovm_field_queue_string"
1761 "`ovm_field_sarray_int"
1762 "`ovm_field_string"
1763 "`ovm_field_utils"
1764 "`ovm_file"
1765 "`ovm_get_imp_decl"
1766 "`ovm_get_peek_imp_decl"
1767 "`ovm_info"
1768 "`ovm_info1"
1769 "`ovm_info2"
1770 "`ovm_info3"
1771 "`ovm_info4"
1772 "`ovm_line"
1773 "`ovm_master_imp_decl"
1774 "`ovm_msg_detail"
1775 "`ovm_non_blocking_transport_imp_decl"
1776 "`ovm_nonblocking_get_imp_decl"
1777 "`ovm_nonblocking_get_peek_imp_decl"
1778 "`ovm_nonblocking_master_imp_decl"
1779 "`ovm_nonblocking_peek_imp_decl"
1780 "`ovm_nonblocking_put_imp_decl"
1781 "`ovm_nonblocking_slave_imp_decl"
1782 "`ovm_object_registry"
1783 "`ovm_object_registry_param"
1784 "`ovm_object_utils"
1785 "`ovm_peek_imp_decl"
1786 "`ovm_phase_func_decl"
1787 "`ovm_phase_task_decl"
1788 "`ovm_print_aa_int_object"
1789 "`ovm_print_aa_string_int"
1790 "`ovm_print_aa_string_object"
1791 "`ovm_print_aa_string_string"
1792 "`ovm_print_array_int"
1793 "`ovm_print_array_object"
1794 "`ovm_print_array_string"
1795 "`ovm_print_object_queue"
1796 "`ovm_print_queue_int"
1797 "`ovm_print_string_queue"
1798 "`ovm_put_imp_decl"
1799 "`ovm_rand_send"
1800 "`ovm_rand_send_with"
1801 "`ovm_send"
1802 "`ovm_sequence_utils"
1803 "`ovm_slave_imp_decl"
1804 "`ovm_transport_imp_decl"
1805 "`ovm_update_sequence_lib"
1806 "`ovm_update_sequence_lib_and_item"
1807 "`ovm_warning"
1808 "`static_dut_error"
1809 "`static_message") nil )))
1812 ;;
1813 ;; Regular expressions used to calculate indent, etc.
1814 ;;
1816 ;; Want to match
1817 ;; aa :
1818 ;; aa,bb :
1819 ;; a[34:32] :
1820 ;; a,
1821 ;; b :
1824 (defconst verilog-property-re
1829 (defconst verilog-no-indent-begin-re
1830 "\\<\\(if\\|else\\|while\\|for\\|repeat\\|always\\|always_comb\\|always_ff\\|always_latch\\)\\>")
1832 (defconst verilog-ends-re
1833 ;; Parenthesis indicate type of keyword found
1834 (concat
1848 ;; VMM
1854 ;; OVM
1861 ))
1863 (defconst verilog-auto-end-comment-lines-re
1864 ;; Matches to names in this list cause auto-end-commentation
1867 (eval-when-compile
1868 (verilog-regexp-words
1869 `( "begin"
1870 "else"
1871 "end"
1872 "endcase"
1873 "endclass"
1874 "endclocking"
1875 "endgroup"
1876 "endfunction"
1877 "endmodule"
1878 "endprogram"
1879 "endprimitive"
1880 "endinterface"
1881 "endpackage"
1882 "endsequence"
1883 "endspecify"
1884 "endtable"
1885 "endtask"
1886 "join"
1887 "join_any"
1888 "join_none"
1889 "module"
1890 "macromodule"
1891 "primitive"
1892 "interface"
1893 "package")))
1896 ;;; NOTE: verilog-leap-to-head expects that verilog-end-block-re and
1897 ;;; verilog-end-block-ordered-re matches exactly the same strings.
1898 (defconst verilog-end-block-ordered-re
1899 ;; Parenthesis indicate type of keyword found
1916 (defconst verilog-end-block-re
1917 (eval-when-compile
1918 (verilog-regexp-words
1920 `("end" ;; closes begin
1921 "endcase" ;; closes any of case, casex casez or randcase
1922 "join" "join_any" "join_none" ;; closes fork
1923 "endclass"
1924 "endtable"
1925 "endspecify"
1926 "endfunction"
1927 "endgenerate"
1928 "endtask"
1929 "endgroup"
1930 "endproperty"
1931 "endinterface"
1932 "endpackage"
1933 "endprogram"
1934 "endsequence"
1935 "endclocking"
1936 ;; OVM
1937 "`ovm_component_utils_end"
1938 "`ovm_field_utils_end"
1939 "`ovm_object_utils_end"
1940 "`ovm_sequence_utils_end"
1941 "`ovm_sequencer_utils_end"
1942 ;; VMM
1943 "`vmm_data_member_end"
1944 "`vmm_env_member_end"
1945 "`vmm_scenario_member_end"
1946 "`vmm_subenv_member_end"
1947 "`vmm_xactor_member_end"
1948 ))))
1951 (defconst verilog-endcomment-reason-re
1952 ;; Parenthesis indicate type of keyword found
1953 (concat
1976 "#"))
1980 ;; These words begin a block which can occur inside a module which should be indented,
1981 ;; and closed with the respective word from the end-block list
1983 (defconst verilog-beg-block-re
1984 (eval-when-compile
1985 (verilog-regexp-words
1986 `("begin"
1987 "case" "casex" "casez" "randcase"
1988 "clocking"
1989 "generate"
1990 "fork"
1991 "function"
1992 "property"
1993 "specify"
1994 "table"
1995 "task"
1996 ;;; OVM
1997 "`ovm_component_utils_begin"
1998 "`ovm_component_param_utils_begin"
1999 "`ovm_field_utils_begin"
2000 "`ovm_object_utils_begin"
2001 "`ovm_object_param_utils_begin"
2002 "`ovm_sequence_utils_begin"
2003 "`ovm_sequencer_utils_begin"
2004 ;; VMM
2005 "`vmm_data_member_begin"
2006 "`vmm_env_member_begin"
2007 "`vmm_scenario_member_begin"
2008 "`vmm_subenv_member_begin"
2009 "`vmm_xactor_member_begin"
2010 ))))
2011 ;; These are the same words, in a specific order in the regular
2012 ;; expression so that matching will work nicely for
2013 ;; verilog-forward-sexp and verilog-calc-indent
2014 (defconst verilog-beg-block-re-ordered
2032 ;;
2034 ))
2036 (defconst verilog-end-block-ordered-rry
2037 [ "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
2050 ] )
2052 (defconst verilog-nameable-item-re
2053 (eval-when-compile
2054 (verilog-regexp-words
2055 `("begin"
2056 "fork"
2057 "join" "join_any" "join_none"
2058 "end"
2059 "endcase"
2060 "endconfig"
2061 "endclass"
2062 "endclocking"
2063 "endfunction"
2064 "endgenerate"
2065 "endmodule"
2066 "endprimitive"
2067 "endinterface"
2068 "endpackage"
2069 "endspecify"
2070 "endtable"
2071 "endtask" )
2072 )))
2074 (defconst verilog-declaration-opener
2075 (eval-when-compile
2076 (verilog-regexp-words
2077 `("module" "begin" "task" "function"))))
2079 (defconst verilog-declaration-prefix-re
2080 (eval-when-compile
2081 (verilog-regexp-words
2082 `(
2083 ;; port direction
2084 "inout" "input" "output" "ref"
2085 ;; changeableness
2086 "const" "static" "protected" "local"
2087 ;; parameters
2088 "localparam" "parameter" "var"
2089 ;; type creation
2090 "typedef"
2091 ))))
2092 (defconst verilog-declaration-core-re
2093 (eval-when-compile
2094 (verilog-regexp-words
2095 `(
2096 ;; port direction (by themselves)
2097 "inout" "input" "output"
2098 ;; integer_atom_type
2099 "byte" "shortint" "int" "longint" "integer" "time"
2100 ;; integer_vector_type
2101 "bit" "logic" "reg"
2102 ;; non_integer_type
2103 "shortreal" "real" "realtime"
2104 ;; net_type
2105 "supply0" "supply1" "tri" "triand" "trior" "trireg" "tri0" "tri1" "uwire" "wire" "wand" "wor"
2106 ;; misc
2107 "string" "event" "chandle" "virtual" "enum" "genvar"
2108 "struct" "union"
2109 ;; builtin classes
2110 "mailbox" "semaphore"
2111 ))))
2112 (defconst verilog-declaration-re
2116 (defconst verilog-optional-signed-range-re
2117 (concat
2121 (defconst verilog-delay-re "#\\s-*\\(\\([0-9_]+\\('s?[hdxbo][0-9a-fA-F_xz]+\\)?\\)\\|\\(([^()]*)\\)\\|\\(\\sw+\\)\\)")
2122 (defconst verilog-declaration-re-2-no-macro
2126 (defconst verilog-declaration-re-2-macro
2131 (defconst verilog-declaration-re-1-macro
2132 (concat "^" verilog-declaration-re-2-macro))
2134 (defconst verilog-declaration-re-1-no-macro (concat "^" verilog-declaration-re-2-no-macro))
2136 (defconst verilog-defun-re
2137 (eval-when-compile (verilog-regexp-words `("macromodule" "module" "class" "program" "interface" "package" "primitive" "config"))))
2138 (defconst verilog-end-defun-re
2139 (eval-when-compile (verilog-regexp-words `("endmodule" "endclass" "endprogram" "endinterface" "endpackage" "endprimitive" "endconfig"))))
2140 (defconst verilog-zero-indent-re
2143 (defconst verilog-behavioral-block-beg-re
2144 (eval-when-compile (verilog-regexp-words `("initial" "final" "always" "always_comb" "always_latch" "always_ff"
2145 "function" "task"))))
2147 (defconst verilog-indent-re
2148 (eval-when-compile
2149 (verilog-regexp-words
2150 `(
2151 "{"
2152 "always" "always_latch" "always_ff" "always_comb"
2153 "begin" "end"
2154 ; "unique" "priority"
2155 "case" "casex" "casez" "randcase" "endcase"
2156 "class" "endclass"
2157 "clocking" "endclocking"
2158 "config" "endconfig"
2159 "covergroup" "endgroup"
2160 "fork" "join" "join_any" "join_none"
2161 "function" "endfunction"
2162 "final"
2163 "generate" "endgenerate"
2164 "initial"
2165 "interface" "endinterface"
2166 "module" "macromodule" "endmodule"
2167 "package" "endpackage"
2168 "primitive" "endprimative"
2169 "program" "endprogram"
2170 "property" "endproperty"
2171 "sequence" "randsequence" "endsequence"
2172 "specify" "endspecify"
2173 "table" "endtable"
2174 "task" "endtask"
2175 "virtual"
2176 "`case"
2177 "`default"
2178 "`define" "`undef"
2179 "`if" "`ifdef" "`ifndef" "`else" "`elsif" "`endif"
2180 "`while" "`endwhile"
2181 "`for" "`endfor"
2182 "`format"
2183 "`include"
2184 "`let"
2185 "`protect" "`endprotect"
2186 "`switch" "`endswitch"
2187 "`timescale"
2188 "`time_scale"
2189 ;; OVM Begin tokens
2190 "`ovm_component_utils_begin"
2191 "`ovm_component_param_utils_begin"
2192 "`ovm_field_utils_begin"
2193 "`ovm_object_utils_begin"
2194 "`ovm_object_param_utils_begin"
2195 "`ovm_sequence_utils_begin"
2196 "`ovm_sequencer_utils_begin"
2197 ;; OVM End tokens
2198 "`ovm_component_utils_end"
2199 "`ovm_field_utils_end"
2200 "`ovm_object_utils_end"
2201 "`ovm_sequence_utils_end"
2202 "`ovm_sequencer_utils_end"
2203 ;; VMM Begin tokens
2204 "`vmm_data_member_begin"
2205 "`vmm_env_member_begin"
2206 "`vmm_scenario_member_begin"
2207 "`vmm_subenv_member_begin"
2208 "`vmm_xactor_member_begin"
2209 ;; VMM End tokens
2210 "`vmm_data_member_end"
2211 "`vmm_env_member_end"
2212 "`vmm_scenario_member_end"
2213 "`vmm_subenv_member_end"
2214 "`vmm_xactor_member_end"
2215 ))))
2217 (defconst verilog-defun-level-not-generate-re
2218 (eval-when-compile
2219 (verilog-regexp-words
2220 `( "module" "macromodule" "primitive" "class" "program"
2221 "interface" "package" "config"))))
2223 (defconst verilog-defun-level-re
2224 (eval-when-compile
2225 (verilog-regexp-words
2226 (append
2227 `( "module" "macromodule" "primitive" "class" "program"
2228 "interface" "package" "config")
2229 `( "initial" "final" "always" "always_comb" "always_ff"
2230 "always_latch" "endtask" "endfunction" )))))
2232 (defconst verilog-defun-level-generate-only-re
2233 (eval-when-compile
2234 (verilog-regexp-words
2235 `( "initial" "final" "always" "always_comb" "always_ff"
2236 "always_latch" "endtask" "endfunction" ))))
2238 (defconst verilog-cpp-level-re
2239 (eval-when-compile
2240 (verilog-regexp-words
2241 `(
2242 "endmodule" "endprimitive" "endinterface" "endpackage" "endprogram" "endclass"
2243 ))))
2247 (defconst verilog-extended-complete-re
2248 (concat "\\(\\<extern\\s-+\\|\\<\\(\\<pure\\>\\s-+\\)?virtual\\s-+\\|\\<protected\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)"
2252 (defconst verilog-basic-complete-re
2253 (eval-when-compile
2254 (verilog-regexp-words
2255 `(
2256 "always" "assign" "always_latch" "always_ff" "always_comb" "constraint"
2257 "import" "initial" "final" "module" "macromodule" "repeat" "randcase" "while"
2258 "if" "for" "forever" "foreach" "else" "parameter" "do" "localparam" "assert"
2259 ))))
2260 (defconst verilog-complete-reg
2261 (concat
2262 verilog-extended-complete-re
2264 verilog-basic-complete-re))
2266 (defconst verilog-end-statement-re
2270 (defconst verilog-endcase-re
2273 verilog-defun-re
2274 ))
2277 "String used to mark beginning of excluded text.")
2279 "String used to mark end of excluded text.")
2280 (defconst verilog-preprocessor-re
2281 (eval-when-compile
2282 (verilog-regexp-words
2283 `(
2284 "`define" "`include" "`ifdef" "`ifndef" "`if" "`endif" "`else"
2285 ))))
2287 (defconst verilog-keywords
2288 '( "`case" "`default" "`define" "`else" "`endfor" "`endif"
2289 "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef"
2290 "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale"
2291 "`time_scale" "`undef" "`while"
2293 "after" "alias" "always" "always_comb" "always_ff" "always_latch" "and"
2294 "assert" "assign" "assume" "automatic" "before" "begin" "bind"
2295 "bins" "binsof" "bit" "break" "buf" "bufif0" "bufif1" "byte"
2296 "case" "casex" "casez" "cell" "chandle" "class" "clocking" "cmos"
2297 "config" "const" "constraint" "context" "continue" "cover"
2298 "covergroup" "coverpoint" "cross" "deassign" "default" "defparam"
2299 "design" "disable" "dist" "do" "edge" "else" "end" "endcase"
2300 "endclass" "endclocking" "endconfig" "endfunction" "endgenerate"
2301 "endgroup" "endinterface" "endmodule" "endpackage" "endprimitive"
2302 "endprogram" "endproperty" "endspecify" "endsequence" "endtable"
2303 "endtask" "enum" "event" "expect" "export" "extends" "extern"
2304 "final" "first_match" "for" "force" "foreach" "forever" "fork"
2305 "forkjoin" "function" "generate" "genvar" "highz0" "highz1" "if"
2306 "iff" "ifnone" "ignore_bins" "illegal_bins" "import" "incdir"
2307 "include" "initial" "inout" "input" "inside" "instance" "int"
2308 "integer" "interface" "intersect" "join" "join_any" "join_none"
2309 "large" "liblist" "library" "local" "localparam" "logic"
2310 "longint" "macromodule" "mailbox" "matches" "medium" "modport" "module"
2311 "nand" "negedge" "new" "nmos" "nor" "noshowcancelled" "not"
2312 "notif0" "notif1" "null" "or" "output" "package" "packed"
2313 "parameter" "pmos" "posedge" "primitive" "priority" "program"
2314 "property" "protected" "pull0" "pull1" "pulldown" "pullup"
2315 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
2316 "randcase" "randsequence" "rcmos" "real" "realtime" "ref" "reg"
2317 "release" "repeat" "return" "rnmos" "rpmos" "rtran" "rtranif0"
2318 "rtranif1" "scalared" "semaphore" "sequence" "shortint" "shortreal"
2319 "showcancelled" "signed" "small" "solve" "specify" "specparam"
2320 "static" "string" "strong0" "strong1" "struct" "super" "supply0"
2321 "supply1" "table" "tagged" "task" "this" "throughout" "time"
2322 "timeprecision" "timeunit" "tran" "tranif0" "tranif1" "tri"
2323 "tri0" "tri1" "triand" "trior" "trireg" "type" "typedef" "union"
2324 "unique" "unsigned" "use" "uwire" "var" "vectored" "virtual" "void"
2325 "wait" "wait_order" "wand" "weak0" "weak1" "while" "wildcard"
2326 "wire" "with" "within" "wor" "xnor" "xor"
2327 ;; 1800-2009
2328 "accept_on" "checker" "endchecker" "eventually" "global" "implies"
2329 "let" "nexttime" "reject_on" "restrict" "s_always" "s_eventually"
2330 "s_nexttime" "s_until" "s_until_with" "strong" "sync_accept_on"
2331 "sync_reject_on" "unique0" "until" "until_with" "untyped" "weak"
2332 )
2333 "List of Verilog keywords.")
2336 "Dual comment value for `comment-start-regexp'.")
2338 (defvar verilog-mode-syntax-table
2339 (let ((table (make-syntax-table)))
2340 ;; Populate the syntax TABLE.
2342 (modify-syntax-entry ?+ "." table)
2343 (modify-syntax-entry ?- "." table)
2344 (modify-syntax-entry ?= "." table)
2345 (modify-syntax-entry ?% "." table)
2346 (modify-syntax-entry ?< "." table)
2347 (modify-syntax-entry ?> "." table)
2348 (modify-syntax-entry ?& "." table)
2349 (modify-syntax-entry ?| "." table)
2350 (modify-syntax-entry ?` "w" table)
2351 (modify-syntax-entry ?_ "w" table)
2354 ;; Set up TABLE to handle block and line style comments.
2355 (if (featurep 'xemacs)
2356 (progn
2357 ;; XEmacs (formerly Lucid) has the best implementation
2358 (modify-syntax-entry ?/ ". 1456" table)
2359 (modify-syntax-entry ?* ". 23" table)
2361 ;; Emacs does things differently, but we can work with it
2362 (modify-syntax-entry ?/ ". 124b" table)
2363 (modify-syntax-entry ?* ". 23" table)
2365 table)
2366 "Syntax table used in Verilog mode buffers.")
2368 (defvar verilog-font-lock-keywords nil
2369 "Default highlighting for Verilog mode.")
2371 (defvar verilog-font-lock-keywords-1 nil
2372 "Subdued level highlighting for Verilog mode.")
2374 (defvar verilog-font-lock-keywords-2 nil
2375 "Medium level highlighting for Verilog mode.
2376 See also `verilog-font-lock-extra-types'.")
2378 (defvar verilog-font-lock-keywords-3 nil
2379 "Gaudy level highlighting for Verilog mode.
2380 See also `verilog-font-lock-extra-types'.")
2381 (defvar verilog-font-lock-translate-off-face
2382 'verilog-font-lock-translate-off-face
2383 "Font to use for translated off regions.")
2384 (defface verilog-font-lock-translate-off-face
2385 '((((class color)
2386 (background light))
2387 (:background "gray90" :italic t ))
2388 (((class color)
2389 (background dark))
2390 (:background "gray10" :italic t ))
2391 (((class grayscale) (background light))
2392 (:foreground "DimGray" :italic t))
2393 (((class grayscale) (background dark))
2394 (:foreground "LightGray" :italic t))
2395 (t (:italis t)))
2396 "Font lock mode face used to background highlight translate-off regions."
2397 :group 'font-lock-highlighting-faces)
2399 (defvar verilog-font-lock-p1800-face
2400 'verilog-font-lock-p1800-face
2401 "Font to use for p1800 keywords.")
2402 (defface verilog-font-lock-p1800-face
2403 '((((class color)
2404 (background light))
2405 (:foreground "DarkOrange3" :bold t ))
2406 (((class color)
2407 (background dark))
2408 (:foreground "orange1" :bold t ))
2409 (t (:italic t)))
2410 "Font lock mode face used to highlight P1800 keywords."
2411 :group 'font-lock-highlighting-faces)
2413 (defvar verilog-font-lock-ams-face
2414 'verilog-font-lock-ams-face
2415 "Font to use for Analog/Mixed Signal keywords.")
2416 (defface verilog-font-lock-ams-face
2417 '((((class color)
2418 (background light))
2419 (:foreground "Purple" :bold t ))
2420 (((class color)
2421 (background dark))
2422 (:foreground "orange1" :bold t ))
2423 (t (:italic t)))
2424 "Font lock mode face used to highlight AMS keywords."
2425 :group 'font-lock-highlighting-faces)
2427 (defvar verilog-font-grouping-keywords-face
2428 'verilog-font-lock-grouping-keywords-face
2429 "Font to use for Verilog Grouping Keywords (such as begin..end).")
2430 (defface verilog-font-lock-grouping-keywords-face
2431 '((((class color)
2432 (background light))
2433 (:foreground "red4" :bold t ))
2434 (((class color)
2435 (background dark))
2436 (:foreground "red4" :bold t ))
2437 (t (:italic t)))
2438 "Font lock mode face used to highlight verilog grouping keywords."
2439 :group 'font-lock-highlighting-faces)
2441 (let* ((verilog-type-font-keywords
2442 (eval-when-compile
2443 (verilog-regexp-opt
2444 '(
2445 "and" "bit" "buf" "bufif0" "bufif1" "cmos" "defparam"
2446 "event" "genvar" "inout" "input" "integer" "localparam"
2447 "logic" "mailbox" "nand" "nmos" "not" "notif0" "notif1" "or"
2448 "output" "parameter" "pmos" "pull0" "pull1" "pulldown" "pullup"
2449 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran"
2450 "rtranif0" "rtranif1" "semaphore" "signed" "struct" "supply"
2451 "supply0" "supply1" "time" "tran" "tranif0" "tranif1"
2452 "tri" "tri0" "tri1" "triand" "trior" "trireg" "typedef"
2453 "uwire" "vectored" "wand" "wire" "wor" "xnor" "xor"
2454 ) nil )))
2456 (verilog-pragma-keywords
2457 (eval-when-compile
2458 (verilog-regexp-opt
2459 '("surefire" "synopsys" "rtl_synthesis" "verilint" "leda" "0in") nil
2460 )))
2462 (verilog-1800-2005-keywords
2463 (eval-when-compile
2464 (verilog-regexp-opt
2465 '("alias" "assert" "assume" "automatic" "before" "bind"
2466 "bins" "binsof" "break" "byte" "cell" "chandle" "class"
2467 "clocking" "config" "const" "constraint" "context" "continue"
2468 "cover" "covergroup" "coverpoint" "cross" "deassign" "design"
2469 "dist" "do" "edge" "endclass" "endclocking" "endconfig"
2470 "endgroup" "endprogram" "endproperty" "endsequence" "enum"
2471 "expect" "export" "extends" "extern" "first_match" "foreach"
2472 "forkjoin" "genvar" "highz0" "highz1" "ifnone" "ignore_bins"
2473 "illegal_bins" "import" "incdir" "include" "inside" "instance"
2474 "int" "intersect" "large" "liblist" "library" "local" "longint"
2475 "matches" "medium" "modport" "new" "noshowcancelled" "null"
2476 "packed" "program" "property" "protected" "pull0" "pull1"
2477 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
2478 "randcase" "randsequence" "ref" "release" "return" "scalared"
2479 "sequence" "shortint" "shortreal" "showcancelled" "small" "solve"
2480 "specparam" "static" "string" "strong0" "strong1" "struct"
2481 "super" "tagged" "this" "throughout" "timeprecision" "timeunit"
2482 "type" "union" "unsigned" "use" "var" "virtual" "void"
2483 "wait_order" "weak0" "weak1" "wildcard" "with" "within"
2484 ) nil )))
2486 (verilog-1800-2009-keywords
2487 (eval-when-compile
2488 (verilog-regexp-opt
2489 '("accept_on" "checker" "endchecker" "eventually" "global"
2490 "implies" "let" "nexttime" "reject_on" "restrict" "s_always"
2491 "s_eventually" "s_nexttime" "s_until" "s_until_with" "strong"
2492 "sync_accept_on" "sync_reject_on" "unique0" "until"
2493 "until_with" "untyped" "weak" ) nil )))
2495 (verilog-ams-keywords
2496 (eval-when-compile
2497 (verilog-regexp-opt
2498 '("above" "abs" "absdelay" "acos" "acosh" "ac_stim"
2499 "aliasparam" "analog" "analysis" "asin" "asinh" "atan" "atan2" "atanh"
2500 "branch" "ceil" "connectmodule" "connectrules" "cos" "cosh" "ddt"
2501 "ddx" "discipline" "driver_update" "enddiscipline" "endconnectrules"
2502 "endnature" "endparamset" "exclude" "exp" "final_step" "flicker_noise"
2503 "floor" "flow" "from" "ground" "hypot" "idt" "idtmod" "inf"
2504 "initial_step" "laplace_nd" "laplace_np" "laplace_zd" "laplace_zp"
2505 "last_crossing" "limexp" "ln" "log" "max" "min" "nature"
2506 "net_resolution" "noise_table" "paramset" "potential" "pow" "sin"
2507 "sinh" "slew" "sqrt" "tan" "tanh" "timer" "transition" "white_noise"
2508 "wreal" "zi_nd" "zi_np" "zi_zd" ) nil )))
2510 (verilog-font-keywords
2511 (eval-when-compile
2512 (verilog-regexp-opt
2513 '(
2514 "assign" "case" "casex" "casez" "randcase" "deassign"
2515 "default" "disable" "else" "endcase" "endfunction"
2516 "endgenerate" "endinterface" "endmodule" "endprimitive"
2517 "endspecify" "endtable" "endtask" "final" "for" "force" "return" "break"
2518 "continue" "forever" "fork" "function" "generate" "if" "iff" "initial"
2519 "interface" "join" "join_any" "join_none" "macromodule" "module" "negedge"
2520 "package" "endpackage" "always" "always_comb" "always_ff"
2521 "always_latch" "posedge" "primitive" "priority" "release"
2522 "repeat" "specify" "table" "task" "unique" "wait" "while"
2523 "class" "program" "endclass" "endprogram"
2524 ) nil )))
2526 (verilog-font-grouping-keywords
2527 (eval-when-compile
2528 (verilog-regexp-opt
2529 '( "begin" "end" ) nil ))))
2531 (setq verilog-font-lock-keywords
2532 (list
2533 ;; Fontify all builtin keywords
2535 ;; And user/system tasks and functions
2538 ;; Fontify all types
2539 (if verilog-highlight-grouping-keywords
2541 'verilog-font-lock-ams-face)
2543 'font-lock-type-face))
2545 'font-lock-type-face)
2546 ;; Fontify IEEE-1800-2005 keywords appropriately
2547 (if verilog-highlight-p1800-keywords
2549 'verilog-font-lock-p1800-face)
2551 'font-lock-type-face))
2552 ;; Fontify IEEE-1800-2009 keywords appropriately
2553 (if verilog-highlight-p1800-keywords
2555 'verilog-font-lock-p1800-face)
2557 'font-lock-type-face))
2558 ;; Fontify Verilog-AMS keywords
2560 'verilog-font-lock-ams-face)))
2562 (setq verilog-font-lock-keywords-1
2563 (append verilog-font-lock-keywords
2564 (list
2565 ;; Fontify module definitions
2566 (list
2567 "\\<\\(\\(macro\\)?module\\|primitive\\|class\\|program\\|interface\\|package\\|task\\)\\>\\s-*\\(\\sw+\\)"
2568 '(1 font-lock-keyword-face)
2569 '(3 font-lock-function-name-face 'prepend))
2570 ;; Fontify function definitions
2571 (list
2573 '(1 font-lock-keyword-face)
2574 '(3 font-lock-constant-face prepend))
2576 (1 font-lock-keyword-face)
2577 (2 font-lock-constant-face append))
2579 1 'font-lock-constant-face append))))
2581 (setq verilog-font-lock-keywords-2
2582 (append verilog-font-lock-keywords-1
2583 (list
2584 ;; Fontify pragmas
2586 ;; Fontify escaped names
2588 ;; Fontify macro definitions/ uses
2590 'font-lock-preprocessor-face
2591 'font-lock-type-face))
2592 ;; Fontify delays/numbers
2593 '("\\(@\\)\\|\\(#\\s-*\\(\\(\[0-9_.\]+\\('s?[hdxbo][0-9a-fA-F_xz]*\\)?\\)\\|\\(([^()]+)\\|\\sw+\\)\\)\\)"
2594 0 font-lock-type-face append)
2595 ;; Fontify instantiation names
2597 )))
2599 (setq verilog-font-lock-keywords-3
2600 (append verilog-font-lock-keywords-2
2601 (when verilog-highlight-translate-off
2602 (list
2603 ;; Fontify things in translate off regions
2604 '(verilog-match-translate-off
2605 (0 'verilog-font-lock-translate-off-face prepend))
2606 )))))
2608 ;;
2609 ;; Buffer state preservation
2611 (defmacro verilog-save-buffer-state (&rest body)
2612 "Execute BODY forms, saving state around insignificant change.
2613 Changes in text properties like `face' or `syntax-table' are
2614 considered insignificant. This macro allows text properties to
2615 be changed, even in a read-only buffer.
2617 A change is considered significant if it affects the buffer text
2618 in any way that isn't completely restored again. Any
2619 user-visible changes to the buffer must not be within a
2620 `verilog-save-buffer-state'."
2621 ;; From c-save-buffer-state
2622 `(let* ((modified (buffer-modified-p))
2623 (buffer-undo-list t)
2624 (inhibit-read-only t)
2625 (inhibit-point-motion-hooks t)
2626 before-change-functions
2627 after-change-functions
2628 deactivate-mark
2629 buffer-file-name ; Prevent primitives checking
2630 buffer-file-truename) ; for file modification
2631 (unwind-protect
2632 (progn ,@body)
2633 (and (not modified)
2634 (buffer-modified-p)
2635 (set-buffer-modified-p nil)))))
2637 (defmacro verilog-save-no-change-functions (&rest body)
2638 "Execute BODY forms, disabling all change hooks in BODY.
2639 For insigificant changes, see instead `verilog-save-buffer-state'."
2640 `(let* ((inhibit-point-motion-hooks t)
2641 before-change-functions
2642 after-change-functions)
2643 (progn ,@body)))
2645 ;;
2646 ;; Comment detection and caching
2648 (defvar verilog-scan-cache-preserving nil
2649 "If set, the specified buffer's comment properties are static.
2650 Buffer changes will be ignored. See `verilog-inside-comment-p'
2651 and `verilog-scan'.")
2653 (defvar verilog-scan-cache-tick nil
2654 "Modification tick at which `verilog-scan' was last completed.")
2655 (make-variable-buffer-local 'verilog-scan-cache-tick)
2657 (defun verilog-scan-cache-ok-p ()
2658 "Return t iff the scan cache is up to date."
2659 (or (and verilog-scan-cache-preserving
2660 (eq verilog-scan-cache-preserving (current-buffer))
2661 verilog-scan-cache-tick)
2662 (equal verilog-scan-cache-tick (buffer-chars-modified-tick))))
2664 (defmacro verilog-save-scan-cache (&rest body)
2665 "Execute the BODY forms, allowing scan cache preservation within BODY.
2666 This requires that insertions must use `verilog-insert'."
2667 ;; If the buffer is out of date, trash it, as we'll not check later the tick
2668 ;; Note this must work properly if there's multiple layers of calls
2669 ;; to verilog-save-scan-cache even with differing ticks.
2670 `(progn
2671 (unless (verilog-scan-cache-ok-p) ;; Must be before let
2672 (setq verilog-scan-cache-tick nil))
2673 (let* ((verilog-scan-cache-preserving (current-buffer)))
2674 (progn ,@body))))
2676 (defun verilog-scan-region (beg end)
2677 "Parse comments between BEG and END for `verilog-inside-comment-p'.
2678 This creates v-cmt properties where comments are in force."
2679 ;; Why properties and not overlays? Overlays have much slower non O(1)
2680 ;; lookup times.
2681 ;; This function is warm - called on every verilog-insert
2682 (save-excursion
2683 (save-match-data
2684 (verilog-save-buffer-state
2685 (let (pt)
2686 (goto-char beg)
2687 (while (< (point) end)
2688 (cond ((looking-at "//")
2689 (setq pt (point))
2691 (goto-char end))
2692 ;; "1+": The leading // or /* itself isn't considered as
2693 ;; being "inside" the comment, so that a (search-backward)
2694 ;; that lands at the start of the // won't mis-indicate
2695 ;; it's inside a comment
2696 (put-text-property (1+ pt) (point) 'v-cmt t))
2698 (setq pt (point))
2699 (or (search-forward "*/" end t)
2700 ;; No error - let later code indicate it so we can
2701 ;; use inside functions on-the-fly
2702 ;;(error "%s: Unmatched /* */, at char %d"
2703 ;; (verilog-point-text) (point))
2704 (goto-char end))
2705 (put-text-property (1+ pt) (point) 'v-cmt t))
2706 (t
2707 (forward-char 1)
2708 (if (re-search-forward "/[/*]" end t)
2709 (backward-char 2)
2710 (goto-char end))))))))))
2712 (defun verilog-scan ()
2713 "Parse the buffer, marking all comments with properties.
2714 Also assumes any text inserted since `verilog-scan-cache-tick'
2715 either is ok to parse as a non-comment, or `verilog-insert' was used."
2716 (unless (verilog-scan-cache-ok-p)
2717 (save-excursion
2718 (verilog-save-buffer-state
2719 (when verilog-debug
2720 (message "Scanning %s cache=%s cachetick=%S tick=%S" (current-buffer)
2721 verilog-scan-cache-preserving verilog-scan-cache-tick
2722 (buffer-chars-modified-tick)))
2723 (remove-text-properties (point-min) (point-max) '(v-cmt nil))
2724 (verilog-scan-region (point-min) (point-max))
2725 (setq verilog-scan-cache-tick (buffer-chars-modified-tick))
2726 (when verilog-debug (message "Scaning... done"))))))
2728 (defun verilog-inside-comment-p ()
2729 "Check if point inside a comment.
2730 This may require a slow pre-parse of the buffer with `verilog-scan'
2731 to establish comment properties on all text."
2732 ;; This function is very hot
2733 (verilog-scan)
2734 (get-text-property (point) 'v-cmt))
2736 (defun verilog-insert (&rest stuff)
2737 "Insert STUFF arguments, tracking comments for `verilog-inside-comment-p'.
2738 Any insert that includes a comment must have the entire commente
2739 inserted using a single call to `verilog-insert'."
2740 (let ((pt (point)))
2741 (while stuff
2742 (insert (car stuff))
2743 (setq stuff (cdr stuff)))
2744 (verilog-scan-region pt (point))))
2746 ;; More searching
2748 (defun verilog-declaration-end ()
2749 (search-forward ";"))
2751 (defun verilog-point-text (&optional pointnum)
2752 "Return text describing where POINTNUM or current point is (for errors).
2753 Use filename, if current buffer being edited shorten to just buffer name."
2754 (concat (or (and (equal (window-buffer (selected-window)) (current-buffer))
2755 (buffer-name))
2756 buffer-file-name
2757 (buffer-name))
2758 ":" (int-to-string (count-lines (point-min) (or pointnum (point))))))
2760 (defun electric-verilog-backward-sexp ()
2761 "Move backward over one balanced expression."
2762 (interactive)
2763 ;; before that see if we are in a comment
2764 (verilog-backward-sexp))
2766 (defun electric-verilog-forward-sexp ()
2767 "Move forward over one balanced expression."
2768 (interactive)
2769 ;; before that see if we are in a comment
2770 (verilog-forward-sexp))
2772 ;;;used by hs-minor-mode
2773 (defun verilog-forward-sexp-function (arg)
2774 (if (< arg 0)
2775 (verilog-backward-sexp)
2776 (verilog-forward-sexp)))
2779 (defun verilog-backward-sexp ()
2780 (let ((reg)
2781 (elsec 1)
2782 (found nil)
2783 (st (point)))
2785 (forward-word -1))
2786 (cond
2787 ((verilog-skip-backward-comment-or-string))
2789 (setq reg (concat
2790 verilog-end-block-re
2793 (while (and (not found)
2794 (verilog-re-search-backward reg nil 'move))
2795 (cond
2796 ((match-end 1) ; matched verilog-end-block-re
2797 ; try to leap back to matching outward block by striding across
2798 ; indent level changing tokens then immediately
2799 ; previous line governs indentation.
2800 (verilog-leap-to-head))
2801 ((match-end 2) ; else, we're in deep
2802 (setq elsec (1+ elsec)))
2803 ((match-end 3) ; found it
2804 (setq elsec (1- elsec))
2805 (if (= 0 elsec)
2806 ;; Now previous line describes syntax
2807 (setq found 't))))))
2808 ((looking-at verilog-end-block-re)
2809 (verilog-leap-to-head))
2810 ((looking-at "\\(endmodule\\>\\)\\|\\(\\<endprimitive\\>\\)\\|\\(\\<endclass\\>\\)\\|\\(\\<endprogram\\>\\)\\|\\(\\<endinterface\\>\\)\\|\\(\\<endpackage\\>\\)")
2811 (cond
2812 ((match-end 1)
2814 ((match-end 2)
2816 ((match-end 3)
2818 ((match-end 4)
2820 ((match-end 5)
2822 ((match-end 6)
2824 (t
2825 (goto-char st)
2826 (backward-sexp 1))))
2827 (t
2828 (goto-char st)
2829 (backward-sexp)))))
2831 (defun verilog-forward-sexp ()
2832 (let ((reg)
2833 (md 2)
2834 (st (point))
2835 (nest 'yes))
2837 (forward-word -1))
2838 (cond
2839 ((verilog-skip-forward-comment-or-string)
2840 (verilog-forward-syntactic-ws))
2841 ((looking-at verilog-beg-block-re-ordered)
2842 (cond
2843 ((match-end 1);
2844 ;; Search forward for matching end
2846 ((match-end 2)
2847 ;; Search forward for matching endcase
2848 (setq reg "\\(\\<randcase\\>\\|\\(\\<unique\\>\\s-+\\|\\<priority\\>\\s-+\\)?\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" )
2849 (setq md 3) ;; ender is third item in regexp
2850 )
2851 ((match-end 4)
2852 ;; might be "disable fork" or "fork wait"
2853 (let
2854 (here)
2855 (if (looking-at verilog-fork-wait-re)
2856 (progn ;; it is a fork wait; ignore it
2857 (goto-char (match-end 0))
2858 (setq reg nil))
2859 (if (or
2860 (looking-at verilog-disable-fork-re)
2861 (and (looking-at "fork")
2862 (progn
2863 (setq here (point)) ;; sometimes a fork is just a fork
2864 (forward-word -1)
2865 (looking-at verilog-disable-fork-re))))
2866 (progn ;; it is a disable fork; ignore it
2867 (goto-char (match-end 0))
2868 (forward-word 1)
2869 (setq reg nil))
2870 (progn ;; it is a nice simple fork
2871 (goto-char here) ;; return from looking for "disable fork"
2872 ;; Search forward for matching join
2874 ((match-end 6)
2875 ;; Search forward for matching endclass
2878 ((match-end 7)
2879 ;; Search forward for matching endtable
2881 (setq nest 'no))
2882 ((match-end 8)
2883 ;; Search forward for matching endspecify
2885 ((match-end 9)
2886 ;; Search forward for matching endfunction
2888 (setq nest 'no))
2889 ((match-end 10)
2890 ;; Search forward for matching endfunction
2892 (setq nest 'no))
2893 ((match-end 14)
2894 ;; Search forward for matching endtask
2896 (setq nest 'no))
2897 ((match-end 15)
2898 ;; Search forward for matching endtask
2900 (setq nest 'no))
2901 ((match-end 19)
2902 ;; Search forward for matching endgenerate
2904 ((match-end 20)
2905 ;; Search forward for matching endgroup
2907 ((match-end 21)
2908 ;; Search forward for matching endproperty
2910 ((match-end 25)
2911 ;; Search forward for matching endsequence
2913 (setq md 3)) ; 3 to get to endsequence in the reg above
2914 ((match-end 27)
2915 ;; Search forward for matching endclocking
2917 (if (and reg
2918 (forward-word 1))
2919 (catch 'skip
2920 (if (eq nest 'yes)
2921 (let ((depth 1)
2922 here)
2923 (while (verilog-re-search-forward reg nil 'move)
2924 (cond
2925 ((match-end md) ; a closer in regular expression, so we are climbing out
2926 (setq depth (1- depth))
2927 (if (= 0 depth) ; we are out!
2928 (throw 'skip 1)))
2929 ((match-end 1) ; an opener in the r-e, so we are in deeper now
2930 (setq here (point)) ; remember where we started
2931 (goto-char (match-beginning 1))
2932 (cond
2933 ((looking-at verilog-fork-wait-re)
2934 (goto-char (match-end 0))) ; false alarm
2935 ((if (or
2936 (looking-at verilog-disable-fork-re)
2937 (and (looking-at "fork")
2938 (progn
2939 (forward-word -1)
2940 (looking-at verilog-disable-fork-re))))
2941 (progn ;; it is a disable fork; another false alarm
2942 (goto-char (match-end 0)))
2943 (progn ;; it is a simple fork (or has nothing to do with fork)
2944 (goto-char here)
2945 (setq depth (1+ depth))))))))))
2946 (if (verilog-re-search-forward reg nil 'move)
2947 (throw 'skip 1))))))
2949 ((looking-at (concat
2956 (cond
2957 ((match-end 1)
2959 ((match-end 2)
2961 ((match-end 3)
2963 ((match-end 4)
2965 ((match-end 5)
2967 ((match-end 6)
2969 (t
2970 (goto-char st)
2971 (if (= (following-char) ?\) )
2972 (forward-char 1)
2973 (forward-sexp 1)))))
2974 (t
2975 (goto-char st)
2976 (if (= (following-char) ?\) )
2977 (forward-char 1)
2978 (forward-sexp 1))))))
2980 (defun verilog-declaration-beg ()
2981 (verilog-re-search-backward verilog-declaration-re (bobp) t))
2983 ;;
2984 ;;
2985 ;; Mode
2986 ;;
2987 (defvar verilog-which-tool 1)
2988 ;;;###autoload
2989 (defun verilog-mode ()
2990 "Major mode for editing Verilog code.
2993 AUTOs can improve coding efficiency.
2997 NEWLINE, TAB indents for Verilog code.
2998 Delete converts tabs to spaces as it moves back.
3000 Supports highlighting.
3002 Turning on Verilog mode calls the value of the variable `verilog-mode-hook'
3003 with no args, if that value is non-nil.
3005 Variables controlling indentation/edit style:
3007 variable `verilog-indent-level' (default 3)
3008 Indentation of Verilog statements with respect to containing block.
3009 `verilog-indent-level-module' (default 3)
3010 Absolute indentation of Module level Verilog statements.
3011 Set to 0 to get initial and always statements lined up
3012 on the left side of your screen.
3013 `verilog-indent-level-declaration' (default 3)
3014 Indentation of declarations with respect to containing block.
3015 Set to 0 to get them list right under containing block.
3016 `verilog-indent-level-behavioral' (default 3)
3017 Indentation of first begin in a task or function block
3018 Set to 0 to get such code to lined up underneath the task or
3019 function keyword.
3020 `verilog-indent-level-directive' (default 1)
3021 Indentation of `ifdef/`endif blocks.
3022 `verilog-cexp-indent' (default 1)
3023 Indentation of Verilog statements broken across lines i.e.:
3024 if (a)
3025 begin
3026 `verilog-case-indent' (default 2)
3027 Indentation for case statements.
3028 `verilog-auto-newline' (default nil)
3029 Non-nil means automatically newline after semicolons and the punctuation
3030 mark after an end.
3031 `verilog-auto-indent-on-newline' (default t)
3032 Non-nil means automatically indent line after newline.
3033 `verilog-tab-always-indent' (default t)
3034 Non-nil means TAB in Verilog mode should always reindent the current line,
3035 regardless of where in the line point is when the TAB command is used.
3036 `verilog-indent-begin-after-if' (default t)
3037 Non-nil means to indent begin statements following a preceding
3038 if, else, while, for and repeat statements, if any. Otherwise,
3039 the begin is lined up with the preceding token. If t, you get:
3040 if (a)
3041 begin // amount of indent based on `verilog-cexp-indent'
3042 otherwise you get:
3043 if (a)
3044 begin
3045 `verilog-auto-endcomments' (default t)
3046 Non-nil means a comment /* ... */ is set after the ends which ends
3047 cases, tasks, functions and modules.
3048 The type and name of the object will be set between the braces.
3049 `verilog-minimum-comment-distance' (default 10)
3050 Minimum distance (in lines) between begin and end required before a comment
3051 will be inserted. Setting this variable to zero results in every
3052 end acquiring a comment; the default avoids too many redundant
3053 comments in tight quarters.
3054 `verilog-auto-lineup' (default 'declarations)
3055 List of contexts where auto lineup of code should be done.
3057 Variables controlling other actions:
3059 `verilog-linter' (default surelint)
3060 Unix program to call to run the lint checker. This is the default
3065 AUTO expansion functions are, in part:
3071 Some other functions are:
3098 \\[verilog-sk-casex] Insert a casex (...) item: begin.. end endcase block, prompting for details.
3099 \\[verilog-sk-casez] Insert a casez (...) item: begin.. end endcase block, prompting for details.
3114 Key bindings specific to `verilog-mode-map' are:
3117 (interactive)
3118 (kill-all-local-variables)
3119 (use-local-map verilog-mode-map)
3120 (setq major-mode 'verilog-mode)
3121 (setq mode-name "Verilog")
3122 (setq local-abbrev-table verilog-mode-abbrev-table)
3123 (set (make-local-variable 'beginning-of-defun-function)
3124 'verilog-beg-of-defun)
3125 (set (make-local-variable 'end-of-defun-function)
3126 'verilog-end-of-defun)
3127 (set-syntax-table verilog-mode-syntax-table)
3128 (make-local-variable 'indent-line-function)
3129 (setq indent-line-function 'verilog-indent-line-relative)
3130 (setq comment-indent-function 'verilog-comment-indent)
3131 (make-local-variable 'parse-sexp-ignore-comments)
3132 (setq parse-sexp-ignore-comments nil)
3133 (make-local-variable 'comment-start)
3134 (make-local-variable 'comment-end)
3135 (make-local-variable 'comment-multi-line)
3136 (make-local-variable 'comment-start-skip)
3137 (setq comment-start "// "
3138 comment-end ""
3140 comment-multi-line nil)
3141 ;; Set up for compilation
3142 (setq verilog-which-tool 1)
3143 (setq verilog-tool 'verilog-linter)
3144 (verilog-set-compile-command)
3145 (when (boundp 'hack-local-variables-hook) ;; Also modify any file-local-variables
3146 (add-hook 'hack-local-variables-hook 'verilog-modify-compile-command t))
3148 ;; Setting up menus
3149 (when (featurep 'xemacs)
3150 (easy-menu-add verilog-stmt-menu)
3151 (easy-menu-add verilog-menu)
3152 (setq mode-popup-menu (cons "Verilog Mode" verilog-stmt-menu)))
3154 ;; Stuff for GNU Emacs
3155 (set (make-local-variable 'font-lock-defaults)
3156 `((verilog-font-lock-keywords verilog-font-lock-keywords-1
3157 verilog-font-lock-keywords-2
3158 verilog-font-lock-keywords-3)
3159 nil nil nil
3160 ,(if (functionp 'syntax-ppss)
3161 ;; verilog-beg-of-defun uses syntax-ppss, and syntax-ppss uses
3162 ;; font-lock-beginning-of-syntax-function, so
3163 ;; font-lock-beginning-of-syntax-function, can't use
3164 ;; verilog-beg-of-defun.
3165 nil
3166 'verilog-beg-of-defun)))
3167 ;;------------------------------------------------------------
3168 ;; now hook in 'verilog-highlight-include-files (eldo-mode.el&spice-mode.el)
3169 ;; all buffer local:
3170 (unless noninteractive ;; Else can't see the result, and change hooks are slow
3171 (when (featurep 'xemacs)
3172 (make-local-hook 'font-lock-mode-hook)
3173 (make-local-hook 'font-lock-after-fontify-buffer-hook); doesn't exist in Emacs
3174 (make-local-hook 'after-change-functions))
3175 (add-hook 'font-lock-mode-hook 'verilog-highlight-buffer t t)
3176 (add-hook 'font-lock-after-fontify-buffer-hook 'verilog-highlight-buffer t t) ; not in Emacs
3177 (add-hook 'after-change-functions 'verilog-highlight-region t t))
3179 ;; Tell imenu how to handle Verilog.
3180 (make-local-variable 'imenu-generic-expression)
3181 (setq imenu-generic-expression verilog-imenu-generic-expression)
3182 ;; Tell which-func-modes that imenu knows about verilog
3183 (when (boundp 'which-function-modes)
3184 (add-to-list 'which-func-modes 'verilog-mode))
3185 ;; hideshow support
3186 (when (boundp 'hs-special-modes-alist)
3187 (unless (assq 'verilog-mode hs-special-modes-alist)
3188 (setq hs-special-modes-alist
3190 verilog-forward-sexp-function)
3191 hs-special-modes-alist))))
3193 ;; Stuff for autos
3194 (add-hook 'write-contents-hooks 'verilog-auto-save-check) ; already local
3195 (run-hooks 'verilog-mode-hook))
3196 \f
3198 ;;
3199 ;; Electric functions
3200 ;;
3201 (defun electric-verilog-terminate-line (&optional arg)
3202 "Terminate line and indent next line.
3203 With optional ARG, remove existing end of line comments."
3204 (interactive)
3205 ;; before that see if we are in a comment
3206 (let ((state (save-excursion (verilog-syntax-ppss))))
3207 (cond
3208 ((nth 7 state) ; Inside // comment
3209 (if (eolp)
3210 (progn
3211 (delete-horizontal-space)
3212 (newline))
3213 (progn
3214 (newline)
3215 (insert "// ")
3216 (beginning-of-line)))
3217 (verilog-indent-line))
3218 ((nth 4 state) ; Inside any comment (hence /**/)
3219 (newline)
3220 (verilog-more-comment))
3221 ((eolp)
3222 ;; First, check if current line should be indented
3223 (if (save-excursion
3224 (delete-horizontal-space)
3225 (beginning-of-line)
3227 (if (looking-at verilog-auto-end-comment-lines-re)
3228 (let ((indent-str (verilog-indent-line)))
3229 ;; Maybe we should set some endcomments
3230 (if verilog-auto-endcomments
3231 (verilog-set-auto-endcomments indent-str arg))
3232 (end-of-line)
3233 (delete-horizontal-space)
3234 (if arg
3235 ()
3236 (newline))
3237 nil)
3238 (progn
3239 (end-of-line)
3240 (delete-horizontal-space)
3241 't)))
3242 ;; see if we should line up assignments
3243 (progn
3244 (if (or (eq 'all verilog-auto-lineup)
3245 (eq 'assignments verilog-auto-lineup))
3247 (newline))
3248 (forward-line 1))
3249 ;; Indent next line
3250 (if verilog-auto-indent-on-newline
3251 (verilog-indent-line)))
3252 (t
3253 (newline)))))
3255 (defun electric-verilog-terminate-and-indent ()
3256 "Insert a newline and indent for the next statement."
3257 (interactive)
3258 (electric-verilog-terminate-line 1))
3260 (defun electric-verilog-semi ()
3261 "Insert `;' character and reindent the line."
3262 (interactive)
3263 (verilog-insert-last-command-event)
3265 (if (or (verilog-in-comment-or-string-p)
3266 (verilog-in-escaped-name-p))
3267 ()
3268 (save-excursion
3269 (beginning-of-line)
3270 (verilog-forward-ws&directives)
3271 (verilog-indent-line))
3272 (if (and verilog-auto-newline
3273 (not (verilog-parenthesis-depth)))
3274 (electric-verilog-terminate-line))))
3276 (defun electric-verilog-semi-with-comment ()
3277 "Insert `;' character, reindent the line and indent for comment."
3278 (interactive)
3279 (insert "\;")
3280 (save-excursion
3281 (beginning-of-line)
3282 (verilog-indent-line))
3283 (indent-for-comment))
3285 (defun electric-verilog-colon ()
3286 "Insert `:' and do all indentations except line indent on this line."
3287 (interactive)
3288 (verilog-insert-last-command-event)
3289 ;; Do nothing if within string.
3290 (if (or
3291 (verilog-within-string)
3292 (not (verilog-in-case-region-p)))
3293 ()
3294 (save-excursion
3295 (let ((p (point))
3296 (lim (progn (verilog-beg-of-statement) (point))))
3297 (goto-char p)
3298 (verilog-backward-case-item lim)
3299 (verilog-indent-line)))
3300 ;; (let ((verilog-tab-always-indent nil))
3301 ;; (verilog-indent-line))
3302 ))
3304 ;;(defun electric-verilog-equal ()
3305 ;; "Insert `=', and do indentation if within block."
3306 ;; (interactive)
3307 ;; (verilog-insert-last-command-event)
3308 ;; Could auto line up expressions, but not yet
3309 ;; (if (eq (car (verilog-calculate-indent)) 'block)
3310 ;; (let ((verilog-tab-always-indent nil))
3311 ;; (verilog-indent-command)))
3312 ;; )
3314 (defun electric-verilog-tick ()
3315 "Insert back-tick, and indent to column 0 if this is a CPP directive."
3316 (interactive)
3317 (verilog-insert-last-command-event)
3318 (save-excursion
3319 (if (verilog-in-directive-p)
3320 (verilog-indent-line))))
3322 (defun electric-verilog-tab ()
3323 "Function called when TAB is pressed in Verilog mode."
3324 (interactive)
3325 ;; If verilog-tab-always-indent, indent the beginning of the line.
3326 (cond
3327 ;; The region is active, indent it.
3328 ((and (region-active-p)
3329 (not (eq (region-beginning) (region-end))))
3330 (indent-region (region-beginning) (region-end) nil))
3331 ((or verilog-tab-always-indent
3332 (save-excursion
3334 (bolp)))
3335 (let* ((oldpnt (point))
3336 (boi-point
3337 (save-excursion
3338 (beginning-of-line)
3340 (verilog-indent-line)
3341 (back-to-indentation)
3342 (point))))
3343 (if (< (point) boi-point)
3344 (back-to-indentation)
3345 (cond ((not verilog-tab-to-comment))
3346 ((not (eolp))
3347 (end-of-line))
3348 (t
3349 (indent-for-comment)
3350 (when (and (eolp) (= oldpnt (point)))
3351 ; kill existing comment
3352 (beginning-of-line)
3353 (re-search-forward comment-start-skip oldpnt 'move)
3354 (goto-char (match-beginning 0))
3356 (kill-region (point) oldpnt)))))))
3359 \f
3361 ;;
3362 ;; Interactive functions
3363 ;;
3365 (defun verilog-indent-buffer ()
3366 "Indent-region the entire buffer as Verilog code.
3368 (interactive)
3369 (verilog-mode)
3370 (indent-region (point-min) (point-max) nil))
3372 (defun verilog-insert-block ()
3373 "Insert Verilog begin ... end; block in the code with right indentation."
3374 (interactive)
3375 (verilog-indent-line)
3376 (insert "begin")
3377 (electric-verilog-terminate-line)
3378 (save-excursion
3379 (electric-verilog-terminate-line)
3380 (insert "end")
3381 (beginning-of-line)
3382 (verilog-indent-line)))
3384 (defun verilog-star-comment ()
3385 "Insert Verilog star comment at point."
3386 (interactive)
3387 (verilog-indent-line)
3388 (insert "/*")
3389 (save-excursion
3390 (newline)
3391 (insert " */"))
3392 (newline)
3393 (insert " * "))
3395 (defun verilog-insert-1 (fmt max)
3396 "Use format string FMT to insert integers 0 to MAX - 1.
3397 Inserts one integer per line, at the current column. Stops early
3398 if it reaches the end of the buffer."
3399 (let ((col (current-column))
3400 (n 0))
3401 (save-excursion
3402 (while (< n max)
3403 (insert (format fmt n))
3404 (forward-line 1)
3405 ;; Note that this function does not bother to check for lines
3406 ;; shorter than col.
3407 (if (eobp)
3408 (setq n max)
3409 (setq n (1+ n))
3410 (move-to-column col))))))
3412 (defun verilog-insert-indices (max)
3413 "Insert a set of indices into a rectangle.
3414 The upper left corner is defined by point. Indices begin with 0
3415 and extend to the MAX - 1. If no prefix arg is given, the user
3416 is prompted for a value. The indices are surrounded by square
3417 brackets \[]. For example, the following code with the point
3418 located after the first 'a' gives:
3420 a = b a[ 0] = b
3421 a = b a[ 1] = b
3422 a = b a[ 2] = b
3423 a = b a[ 3] = b
3424 a = b ==> insert-indices ==> a[ 4] = b
3425 a = b a[ 5] = b
3426 a = b a[ 6] = b
3427 a = b a[ 7] = b
3428 a = b a[ 8] = b"
3430 (interactive "NMAX: ")
3431 (verilog-insert-1 "[%3d]" max))
3433 (defun verilog-generate-numbers (max)
3434 "Insert a set of generated numbers into a rectangle.
3435 The upper left corner is defined by point. The numbers are padded to three
3436 digits, starting with 000 and extending to (MAX - 1). If no prefix argument
3437 is supplied, then the user is prompted for the MAX number. Consider the
3438 following code fragment:
3440 buf buf buf buf000
3441 buf buf buf buf001
3442 buf buf buf buf002
3443 buf buf buf buf003
3444 buf buf ==> generate-numbers ==> buf buf004
3445 buf buf buf buf005
3446 buf buf buf buf006
3447 buf buf buf buf007
3448 buf buf buf buf008"
3450 (interactive "NMAX: ")
3451 (verilog-insert-1 "%3.3d" max))
3453 (defun verilog-mark-defun ()
3454 "Mark the current Verilog function (or procedure).
3455 This puts the mark at the end, and point at the beginning."
3456 (interactive)
3457 (if (featurep 'xemacs)
3458 (progn
3459 (push-mark (point))
3460 (verilog-end-of-defun)
3461 (push-mark (point))
3462 (verilog-beg-of-defun)
3463 (if (fboundp 'zmacs-activate-region)
3464 (zmacs-activate-region)))
3465 (mark-defun)))
3467 (defun verilog-comment-region (start end)
3468 ; checkdoc-params: (start end)
3469 "Put the region into a Verilog comment.
3471 `*)' becomes `!(*' and `}' becomes `!{'.
3472 These deformed comments are returned to normal if you use
3475 The commented area starts with `verilog-exclude-str-start', and ends with
3476 `verilog-exclude-str-end'. But if you change these variables,
3478 (interactive "r")
3479 (save-excursion
3480 ;; Insert start and endcomments
3481 (goto-char end)
3484 (forward-line 1)
3485 (beginning-of-line))
3486 (insert verilog-exclude-str-end)
3487 (setq end (point))
3488 (newline)
3489 (goto-char start)
3490 (beginning-of-line)
3491 (insert verilog-exclude-str-start)
3492 (newline)
3493 ;; Replace end-comments within commented area
3494 (goto-char end)
3495 (save-excursion
3497 (replace-match "*-/" t t)))
3498 (save-excursion
3499 (let ((s+1 (1+ start)))
3501 (replace-match "/-*" t t))))))
3503 (defun verilog-uncomment-region ()
3504 "Uncomment a commented area; change deformed comments back to normal.
3505 This command does nothing if the pointer is not in a commented
3506 area. See also `verilog-comment-region'."
3507 (interactive)
3508 (save-excursion
3509 (let ((start (point))
3510 (end (point)))
3511 ;; Find the boundaries of the comment
3512 (save-excursion
3513 (setq start (progn (search-backward verilog-exclude-str-start nil t)
3514 (point)))
3515 (setq end (progn (search-forward verilog-exclude-str-end nil t)
3516 (point))))
3517 ;; Check if we're really inside a comment
3518 (if (or (equal start (point)) (<= end (point)))
3519 (message "Not standing within commented area.")
3520 (progn
3521 ;; Remove endcomment
3522 (goto-char end)
3523 (beginning-of-line)
3524 (let ((pos (point)))
3525 (end-of-line)
3526 (delete-region pos (1+ (point))))
3527 ;; Change comments back to normal
3528 (save-excursion
3530 (replace-match "*/" t t)))
3531 (save-excursion
3533 (replace-match "/*" t t)))
3534 ;; Remove start comment
3535 (goto-char start)
3536 (beginning-of-line)
3537 (let ((pos (point)))
3538 (end-of-line)
3539 (delete-region pos (1+ (point)))))))))
3541 (defun verilog-beg-of-defun ()
3542 "Move backward to the beginning of the current function or procedure."
3543 (interactive)
3544 (verilog-re-search-backward verilog-defun-re nil 'move))
3546 (defun verilog-end-of-defun ()
3547 "Move forward to the end of the current function or procedure."
3548 (interactive)
3549 (verilog-re-search-forward verilog-end-defun-re nil 'move))
3551 (defun verilog-get-beg-of-defun (&optional warn)
3552 (save-excursion
3553 (cond ((verilog-re-search-forward-quick verilog-defun-re nil t)
3554 (point))
3555 (t
3556 (error "%s: Can't find module beginning" (verilog-point-text))
3557 (point-max)))))
3558 (defun verilog-get-end-of-defun (&optional warn)
3559 (save-excursion
3560 (cond ((verilog-re-search-forward-quick verilog-end-defun-re nil t)
3561 (point))
3562 (t
3563 (error "%s: Can't find endmodule" (verilog-point-text))
3564 (point-max)))))
3566 (defun verilog-label-be (&optional arg)
3567 "Label matching begin ... end, fork ... join and case ... endcase statements.
3568 With ARG, first kill any existing labels."
3569 (interactive)
3570 (let ((cnt 0)
3571 (oldpos (point))
3572 (b (progn
3573 (verilog-beg-of-defun)
3574 (point-marker)))
3575 (e (progn
3576 (verilog-end-of-defun)
3577 (point-marker))))
3578 (goto-char (marker-position b))
3579 (if (> (- e b) 200)
3580 (message "Relabeling module..."))
3581 (while (and
3582 (> (marker-position e) (point))
3583 (verilog-re-search-forward
3584 (concat
3585 "\\<end\\(\\(function\\)\\|\\(task\\)\\|\\(module\\)\\|\\(primitive\\)\\|\\(interface\\)\\|\\(package\\)\\|\\(case\\)\\)?\\>"
3587 nil 'move))
3588 (goto-char (match-beginning 0))
3589 (let ((indent-str (verilog-indent-line)))
3590 (verilog-set-auto-endcomments indent-str 't)
3591 (end-of-line)
3592 (delete-horizontal-space))
3593 (setq cnt (1+ cnt))
3594 (if (= 9 (% cnt 10))
3595 (message "%d..." cnt)))
3596 (goto-char oldpos)
3597 (if (or
3598 (> (- e b) 200)
3599 (> cnt 20))
3600 (message "%d lines auto commented" cnt))))
3602 (defun verilog-beg-of-statement ()
3603 "Move backward to beginning of statement."
3604 (interactive)
3605 ;; Move back token by token until we see the end
3606 ;; of some ealier line.
3607 (let (h)
3608 (while
3609 ;; If the current point does not begin a new
3610 ;; statement, as in the character ahead of us is a ';', or SOF
3611 ;; or the string after us unambiguously starts a statement,
3612 ;; or the token before us unambiguously ends a statement,
3613 ;; then move back a token and test again.
3614 (not (or
3615 ;; stop if beginning of buffer
3616 (bolp)
3617 ;; stop if we find a ;
3618 (= (preceding-char) ?\;)
3619 ;; stop if we see a named coverpoint
3621 ;; keep going if we are in the middle of a word
3623 ;; stop if we see an assertion (perhaps labled)
3624 (and
3625 (looking-at "\\(\\<\\(assert\\|assume\\|cover\\)\\>\\s-+\\<property\\>\\)\\|\\(\\<assert\\>\\)")
3626 (progn
3627 (setq h (point))
3628 (save-excursion
3629 (verilog-backward-token)
3630 (if (looking-at verilog-label-re)
3631 (setq h (point))))
3632 (goto-char h)))
3633 ;; stop if we see a complete reg, perhaps an extended one
3634 (and
3635 (looking-at verilog-complete-reg)
3636 (let* ((p (point)))
3637 (while (and (looking-at verilog-extended-complete-re)
3638 (progn (setq p (point))
3639 (verilog-backward-token)
3640 (/= p (point)))))
3641 (goto-char p)))
3642 ;; stop if we see a complete reg (previous found extended ones)
3643 (looking-at verilog-basic-complete-re)
3644 ;; stop if previous token is an ender
3645 (save-excursion
3646 (verilog-backward-token)
3647 (or
3648 (looking-at verilog-end-block-re)
3649 (looking-at verilog-preprocessor-re))))) ;; end of test
3650 (verilog-backward-syntactic-ws)
3651 (verilog-backward-token))
3652 ;; Now point is where the previous line ended.
3653 (verilog-forward-syntactic-ws)))
3655 (defun verilog-beg-of-statement-1 ()
3656 "Move backward to beginning of statement."
3657 (interactive)
3658 (if (verilog-in-comment-p)
3659 (verilog-backward-syntactic-ws))
3660 (let ((pt (point)))
3661 (catch 'done
3662 (while (not (looking-at verilog-complete-reg))
3663 (setq pt (point))
3664 (verilog-backward-syntactic-ws)
3665 (if (or (bolp)
3666 (= (preceding-char) ?\;)
3667 (save-excursion
3668 (verilog-backward-token)
3669 (looking-at verilog-ends-re)))
3670 (progn
3671 (goto-char pt)
3672 (throw 'done t))
3673 (verilog-backward-token))))
3674 (verilog-forward-syntactic-ws)))
3675 ;
3676 ; (while (and
3677 ; (not (looking-at verilog-complete-reg))
3678 ; (not (bolp))
3679 ; (not (= (preceding-char) ?\;)))
3680 ; (verilog-backward-token)
3681 ; (verilog-backward-syntactic-ws)
3682 ; (setq pt (point)))
3683 ; (goto-char pt)
3684 ; ;(verilog-forward-syntactic-ws)
3686 (defun verilog-end-of-statement ()
3687 "Move forward to end of current statement."
3688 (interactive)
3689 (let ((nest 0) pos)
3690 (cond
3691 ((verilog-in-directive-p)
3692 (forward-line 1)
3693 (backward-char 1))
3695 ((looking-at verilog-beg-block-re)
3696 (verilog-forward-sexp))
3698 ((equal (char-after) ?\})
3699 (forward-char))
3701 ;; Skip to end of statement
3702 ((condition-case nil
3703 (setq pos
3704 (catch 'found
3705 (while t
3706 (forward-sexp 1)
3707 (verilog-skip-forward-comment-or-string)
3708 (if (eolp)
3709 (forward-line 1))
3711 (skip-chars-forward "^;")
3712 (forward-char 1)
3713 (throw 'found (point)))
3714 ((save-excursion
3715 (forward-sexp -1)
3716 (looking-at verilog-beg-block-re))
3717 (goto-char (match-beginning 0))
3718 (throw 'found nil))
3720 (throw 'found (point)))
3721 ((eobp)
3722 (throw 'found (point)))
3723 )))
3725 )
3726 (error nil))
3727 (if (not pos)
3728 ;; Skip a whole block
3729 (catch 'found
3730 (while t
3731 (verilog-re-search-forward verilog-end-statement-re nil 'move)
3732 (setq nest (if (match-end 1)
3733 (1+ nest)
3734 (1- nest)))
3735 (cond ((eobp)
3736 (throw 'found (point)))
3737 ((= 0 nest)
3738 (throw 'found (verilog-end-of-statement))))))
3739 pos)))))
3741 (defun verilog-in-case-region-p ()
3742 "Return true if in a case region.
3743 More specifically, point @ in the line foo : @ begin"
3744 (interactive)
3745 (save-excursion
3746 (if (and
3747 (progn (verilog-forward-syntactic-ws)
3749 (progn (verilog-backward-syntactic-ws)
3750 (= (preceding-char) ?\:)))
3751 (catch 'found
3752 (let ((nest 1))
3753 (while t
3754 (verilog-re-search-backward
3757 nil 'move)
3758 (cond
3759 ((match-end 3)
3760 (setq nest (1+ nest)))
3761 ((match-end 2)
3762 (if (= nest 1)
3763 (throw 'found 1))
3764 (setq nest (1- nest)))
3765 (t
3766 (throw 'found (= nest 0)))))))
3767 nil)))
3768 (defun verilog-backward-up-list (arg)
3769 "Like backward-up-list, but deal with comments."
3770 (let (saved-psic parse-sexp-ignore-comments)
3771 (setq parse-sexp-ignore-comments 1)
3772 (backward-up-list arg)
3773 (setq parse-sexp-ignore-comments saved-psic)
3774 ))
3776 (defun verilog-in-struct-region-p ()
3777 "Return true if in a struct region.
3778 More specifically, in a list after a struct|union keyword."
3779 (interactive)
3780 (save-excursion
3781 (let* ((state (verilog-syntax-ppss))
3782 (depth (nth 0 state)))
3783 (if depth
3784 (progn (verilog-backward-up-list depth)
3785 (verilog-beg-of-statement)
3788 (defun verilog-in-generate-region-p ()
3789 "Return true if in a generate region.
3790 More specifically, after a generate and before an endgenerate."
3791 (interactive)
3792 (let ((nest 1))
3793 (save-excursion
3794 (catch 'done
3795 (while (and
3796 (/= nest 0)
3797 (verilog-re-search-backward
3799 (cond
3800 ((match-end 1) ; module - we have crawled out
3801 (throw 'done 1))
3802 ((match-end 2) ; generate
3803 (setq nest (1- nest)))
3804 ((match-end 3) ; endgenerate
3805 (setq nest (1+ nest))))))))
3806 (= nest 0) )) ; return nest
3808 (defun verilog-in-fork-region-p ()
3809 "Return true if between a fork and join."
3810 (interactive)
3811 (let ((lim (save-excursion (verilog-beg-of-defun) (point)))
3812 (nest 1))
3813 (save-excursion
3814 (while (and
3815 (/= nest 0)
3817 (cond
3818 ((match-end 1) ; fork
3819 (setq nest (1- nest)))
3820 ((match-end 2) ; join
3821 (setq nest (1+ nest)))))))
3822 (= nest 0) )) ; return nest
3824 (defun verilog-backward-case-item (lim)
3825 "Skip backward to nearest enclosing case item.
3826 Limit search to point LIM."
3827 (interactive)
3828 (let ((str 'nil)
3829 (lim1
3830 (progn
3831 (save-excursion
3832 (verilog-re-search-backward verilog-endcomment-reason-re
3833 lim 'move)
3834 (point)))))
3835 ;; Try to find the real :
3836 (if (save-excursion (search-backward ":" lim1 t))
3837 (let ((colon 0)
3838 b e )
3839 (while
3840 (and
3841 (< colon 1)
3843 lim1 'move))
3844 (cond
3845 ((match-end 1) ;; [
3846 (setq colon (1+ colon))
3847 (if (>= colon 0)
3848 (error "%s: unbalanced [" (verilog-point-text))))
3849 ((match-end 2) ;; ]
3850 (setq colon (1- colon)))
3852 ((match-end 3) ;; :
3853 (setq colon (1+ colon)))))
3854 ;; Skip back to beginning of case item
3856 (verilog-skip-backward-comment-or-string)
3857 (setq e (point))
3858 (setq b
3859 (progn
3860 (if
3861 (verilog-re-search-backward
3863 (progn
3864 (cond
3865 ((match-end 1)
3866 (goto-char (match-end 1))
3867 (verilog-forward-ws&directives)
3868 (if (looking-at "(")
3869 (progn
3870 (forward-sexp)
3871 (verilog-forward-ws&directives)))
3872 (point))
3873 (t
3874 (goto-char (match-end 0))
3875 (verilog-forward-ws&directives)
3876 (point))))
3877 (error "Malformed case item"))))
3878 (setq str (buffer-substring b e))
3879 (if
3880 (setq e
3881 (string-match
3883 (setq str (concat (substring str 0 e) "...")))
3884 str)
3885 'nil)))
3886 \f
3888 ;;
3889 ;; Other functions
3890 ;;
3892 (defun verilog-kill-existing-comment ()
3893 "Kill auto comment on this line."
3894 (save-excursion
3895 (let* (
3896 (e (progn
3897 (end-of-line)
3898 (point)))
3899 (b (progn
3900 (beginning-of-line)
3901 (search-forward "//" e t))))
3902 (if b
3903 (delete-region (- b 2) e)))))
3905 (defconst verilog-directive-nest-re
3912 (defun verilog-set-auto-endcomments (indent-str kill-existing-comment)
3913 "Add ending comment with given INDENT-STR.
3914 With KILL-EXISTING-COMMENT, remove what was there before.
3915 Insert `// case: 7 ' or `// NAME ' on this line if appropriate.
3916 Insert `// case expr ' if this line ends a case block.
3917 Insert `// ifdef FOO ' if this line ends code conditional on FOO.
3918 Insert `// NAME ' if this line ends a function, task, module,
3919 primitive or interface named NAME."
3920 (save-excursion
3921 (cond
3922 (; Comment close preprocessor directives
3923 (and
3925 (or kill-existing-comment
3926 (not (save-excursion
3927 (end-of-line)
3928 (search-backward "//" (verilog-get-beg-of-line) t)))))
3929 (let ((nest 1) b e
3930 m
3931 (else (if (match-end 2) "!" " ")))
3932 (end-of-line)
3933 (if kill-existing-comment
3934 (verilog-kill-existing-comment))
3935 (delete-horizontal-space)
3936 (save-excursion
3937 (backward-sexp 1)
3938 (while (and (/= nest 0)
3939 (verilog-re-search-backward verilog-directive-nest-re nil 'move))
3940 (cond
3941 ((match-end 1) ; `else
3942 (if (= nest 1)
3943 (setq else "!")))
3944 ((match-end 2) ; `endif
3945 (setq nest (1+ nest)))
3946 ((match-end 3) ; `if
3947 (setq nest (1- nest)))
3948 ((match-end 4) ; `ifdef
3949 (setq nest (1- nest)))
3950 ((match-end 5) ; `ifndef
3951 (setq nest (1- nest)))
3952 ((match-end 6) ; `elsif
3953 (if (= nest 1)
3954 (progn
3955 (setq else "!")
3956 (setq nest 0))))))
3957 (if (match-end 0)
3958 (setq
3959 m (buffer-substring
3960 (match-beginning 0)
3961 (match-end 0))
3962 b (progn
3964 (verilog-forward-syntactic-ws)
3965 (point))
3966 e (progn
3967 (skip-chars-forward "a-zA-Z0-9_")
3968 (point)))))
3969 (if b
3970 (if (> (count-lines (point) b) verilog-minimum-comment-distance)
3971 (insert (concat " // " else m " " (buffer-substring b e))))
3972 (progn
3973 (insert " // unmatched `else, `elsif or `endif")
3974 (ding 't)))))
3976 (; Comment close case/class/function/task/module and named block
3978 (or kill-existing-comment
3979 (not (save-excursion
3980 (end-of-line)
3981 (search-backward "//" (verilog-get-beg-of-line) t)))))
3982 (let ((type (car indent-str)))
3983 (unless (eq type 'declaration)
3984 (unless (looking-at (concat "\\(" verilog-end-block-ordered-re "\\)[ \t]*:")) ;; ignore named ends
3985 (if (looking-at verilog-end-block-ordered-re)
3986 (cond
3987 (;- This is a case block; search back for the start of this case
3988 (match-end 1) ;; of verilog-end-block-ordered-re
3990 (let ((err 't)
3991 (str "UNMATCHED!!"))
3992 (save-excursion
3993 (verilog-leap-to-head)
3994 (cond
3996 (setq str "randcase")
3997 (setq err nil))
3999 (goto-char (match-end 0))
4000 (setq str (concat (match-string 0) " " (verilog-get-expr)))
4001 (setq err nil))
4002 ))
4003 (end-of-line)
4004 (if kill-existing-comment
4005 (verilog-kill-existing-comment))
4006 (delete-horizontal-space)
4007 (insert (concat " // " str ))
4008 (if err (ding 't))))
4010 (;- This is a begin..end block
4011 (match-end 2) ;; of verilog-end-block-ordered-re
4012 (let ((str " // UNMATCHED !!")
4013 (err 't)
4014 (here (point))
4015 there
4016 cntx)
4017 (save-excursion
4018 (verilog-leap-to-head)
4019 (setq there (point))
4020 (if (not (match-end 0))
4021 (progn
4022 (goto-char here)
4023 (end-of-line)
4024 (if kill-existing-comment
4025 (verilog-kill-existing-comment))
4026 (delete-horizontal-space)
4027 (insert str)
4028 (ding 't))
4029 (let ((lim
4030 (save-excursion (verilog-beg-of-defun) (point)))
4031 (here (point)))
4032 (cond
4033 (;-- handle named block differently
4034 (looking-at verilog-named-block-re)
4035 (search-forward ":")
4036 (setq there (point))
4037 (setq str (verilog-get-expr))
4038 (setq err nil)
4039 (setq str (concat " // block: " str )))
4041 ((verilog-in-case-region-p) ;-- handle case item differently
4042 (goto-char here)
4043 (setq str (verilog-backward-case-item lim))
4044 (setq there (point))
4045 (setq err nil)
4046 (setq str (concat " // case: " str )))
4048 (;- try to find "reason" for this begin
4049 (cond
4050 (;
4051 (eq here (progn
4052 ;; (verilog-backward-token)
4053 (verilog-beg-of-statement)
4054 (point)))
4055 (setq err nil)
4056 (setq str ""))
4057 ((looking-at verilog-endcomment-reason-re)
4058 (setq there (match-end 0))
4059 (setq cntx (concat (match-string 0) " "))
4060 (cond
4061 (;- begin
4062 (match-end 1)
4063 (setq err nil)
4064 (save-excursion
4065 (if (and (verilog-continued-line)
4067 (progn
4068 (goto-char (match-end 0))
4069 (setq there (point))
4070 (setq str
4071 (concat " // " (match-string 0) " " (verilog-get-expr))))
4072 (setq str ""))))
4074 (;- else
4075 (match-end 2)
4076 (let ((nest 0)
4078 (catch 'skip
4079 (while (verilog-re-search-backward reg nil 'move)
4080 (cond
4081 ((match-end 1) ; begin
4082 (setq nest (1- nest)))
4083 ((match-end 2) ; end
4084 (setq nest (1+ nest)))
4085 ((match-end 3)
4086 (if (= 0 nest)
4087 (progn
4088 (goto-char (match-end 0))
4089 (setq there (point))
4090 (setq err nil)
4091 (setq str (verilog-get-expr))
4092 (setq str (concat " // else: !if" str ))
4093 (throw 'skip 1))))
4094 ((match-end 4)
4095 (if (= 0 nest)
4096 (progn
4097 (goto-char (match-end 0))
4098 (setq there (point))
4099 (setq err nil)
4100 (setq str (verilog-get-expr))
4101 (setq str (concat " // else: !assert " str ))
4102 (throw 'skip 1)))))))))
4103 (;- end else
4104 (match-end 3)
4105 (goto-char there)
4106 (let ((nest 0)
4108 (catch 'skip
4109 (while (verilog-re-search-backward reg nil 'move)
4110 (cond
4111 ((match-end 1) ; begin
4112 (setq nest (1- nest)))
4113 ((match-end 2) ; end
4114 (setq nest (1+ nest)))
4115 ((match-end 3)
4116 (if (= 0 nest)
4117 (progn
4118 (goto-char (match-end 0))
4119 (setq there (point))
4120 (setq err nil)
4121 (setq str (verilog-get-expr))
4122 (setq str (concat " // else: !if" str ))
4123 (throw 'skip 1))))
4124 ((match-end 4)
4125 (if (= 0 nest)
4126 (progn
4127 (goto-char (match-end 0))
4128 (setq there (point))
4129 (setq err nil)
4130 (setq str (verilog-get-expr))
4131 (setq str (concat " // else: !assert " str ))
4132 (throw 'skip 1)))))))))
4134 (; always_comb, always_ff, always_latch
4135 (or (match-end 4) (match-end 5) (match-end 6))
4136 (goto-char (match-end 0))
4137 (setq there (point))
4138 (setq err nil)
4139 (setq str (concat " // " cntx )))
4141 (;- task/function/initial et cetera
4142 t
4143 (match-end 0)
4144 (goto-char (match-end 0))
4145 (setq there (point))
4146 (setq err nil)
4147 (setq str (concat " // " cntx (verilog-get-expr))))
4149 (;-- otherwise...
4150 (setq str " // auto-endcomment confused "))))
4152 ((and
4153 (verilog-in-case-region-p) ;-- handle case item differently
4154 (progn
4155 (setq there (point))
4156 (goto-char here)
4157 (setq str (verilog-backward-case-item lim))))
4158 (setq err nil)
4159 (setq str (concat " // case: " str )))
4161 ((verilog-in-fork-region-p)
4162 (setq err nil)
4163 (setq str " // fork branch" ))
4166 ;; HERE
4167 (forward-word 1)
4168 (verilog-forward-syntactic-ws)
4169 (setq err nil)
4170 (setq str (verilog-get-expr))
4171 (setq str (concat " // " cntx str )))
4173 ))))
4174 (goto-char here)
4175 (end-of-line)
4176 (if kill-existing-comment
4177 (verilog-kill-existing-comment))
4178 (delete-horizontal-space)
4179 (if (or err
4180 (> (count-lines here there) verilog-minimum-comment-distance))
4181 (insert str))
4182 (if err (ding 't))
4183 ))))
4184 (;- this is endclass, which can be nested
4185 (match-end 11) ;; of verilog-end-block-ordered-re
4186 ;;(goto-char there)
4187 (let ((nest 0)
4189 string)
4190 (save-excursion
4191 (catch 'skip
4192 (while (verilog-re-search-backward reg nil 'move)
4193 (cond
4194 ((match-end 3) ; endclass
4195 (ding 't)
4196 (setq string "unmatched endclass")
4197 (throw 'skip 1))
4199 ((match-end 2) ; endclass
4200 (setq nest (1+ nest)))
4202 ((match-end 1) ; class
4203 (setq nest (1- nest))
4204 (if (< nest 0)
4205 (progn
4206 (goto-char (match-end 0))
4207 (let (b e)
4208 (setq b (progn
4210 (verilog-forward-ws&directives)
4211 (point))
4212 e (progn
4213 (skip-chars-forward "a-zA-Z0-9_")
4214 (point)))
4215 (setq string (buffer-substring b e)))
4216 (throw 'skip 1))))
4217 ))))
4218 (end-of-line)
4219 (insert (concat " // " string ))))
4221 (;- this is end{function,generate,task,module,primitive,table,generate}
4222 ;- which can not be nested.
4223 t
4224 (let (string reg (name-re nil))
4225 (end-of-line)
4226 (if kill-existing-comment
4227 (save-match-data
4228 (verilog-kill-existing-comment)))
4229 (delete-horizontal-space)
4230 (backward-sexp)
4231 (cond
4232 ((match-end 5) ;; of verilog-end-block-ordered-re
4233 (setq reg "\\(\\<function\\>\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
4235 )
4236 ((match-end 6) ;; of verilog-end-block-ordered-re
4237 (setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)"))
4238 ((match-end 7) ;; of verilog-end-block-ordered-re
4240 ((match-end 8) ;; of verilog-end-block-ordered-re
4241 (setq reg "\\(\\<primitive\\>\\)\\|\\(\\<\\(endprimitive\\|package\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4242 ((match-end 9) ;; of verilog-end-block-ordered-re
4243 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<\\(endinterface\\|package\\|primitive\\|\\(macro\\)?module\\)\\>\\)"))
4244 ((match-end 10) ;; of verilog-end-block-ordered-re
4245 (setq reg "\\(\\<package\\>\\)\\|\\(\\<\\(endpackage\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4246 ((match-end 11) ;; of verilog-end-block-ordered-re
4247 (setq reg "\\(\\<class\\>\\)\\|\\(\\<\\(endclass\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4248 ((match-end 12) ;; of verilog-end-block-ordered-re
4249 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<\\(endcovergroup\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4250 ((match-end 13) ;; of verilog-end-block-ordered-re
4251 (setq reg "\\(\\<program\\>\\)\\|\\(\\<\\(endprogram\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4252 ((match-end 14) ;; of verilog-end-block-ordered-re
4253 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<\\(endsequence\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4254 ((match-end 15) ;; of verilog-end-block-ordered-re
4257 (t (error "Problem in verilog-set-auto-endcomments")))
4258 (let (b e)
4259 (save-excursion
4260 (verilog-re-search-backward reg nil 'move)
4261 (cond
4262 ((match-end 1)
4263 (setq b (progn
4265 (verilog-forward-ws&directives)
4267 (progn
4268 (goto-char (match-end 0))
4269 (verilog-forward-ws&directives)))
4270 (if (and name-re (verilog-re-search-forward name-re nil 'move))
4271 (progn
4272 (goto-char (match-beginning 0))
4273 (verilog-forward-ws&directives)))
4274 (point))
4275 e (progn
4276 (skip-chars-forward "a-zA-Z0-9_")
4277 (point)))
4278 (setq string (buffer-substring b e)))
4279 (t
4280 (ding 't)
4281 (setq string "unmatched end(function|task|module|primitive|interface|package|class|clocking)")))))
4282 (end-of-line)
4283 (insert (concat " // " string )))
4284 ))))))))))
4286 (defun verilog-get-expr()
4287 "Grab expression at point, e.g, case ( a | b & (c ^d))."
4288 (let* ((b (progn
4289 (verilog-forward-syntactic-ws)
4291 (point)))
4292 (e (let ((par 1))
4293 (cond
4294 ((looking-at "@")
4295 (forward-char 1)
4296 (verilog-forward-syntactic-ws)
4297 (if (looking-at "(")
4298 (progn
4299 (forward-char 1)
4300 (while (and (/= par 0)
4302 (cond
4303 ((match-end 1)
4304 (setq par (1+ par)))
4305 ((match-end 2)
4306 (setq par (1- par)))))))
4307 (point))
4308 ((looking-at "(")
4309 (forward-char 1)
4310 (while (and (/= par 0)
4312 (cond
4313 ((match-end 1)
4314 (setq par (1+ par)))
4315 ((match-end 2)
4316 (setq par (1- par)))))
4317 (point))
4319 (forward-char 1)
4320 (while (and (/= par 0)
4322 (cond
4323 ((match-end 1)
4324 (setq par (1+ par)))
4325 ((match-end 2)
4326 (setq par (1- par)))))
4327 (verilog-forward-syntactic-ws)
4329 (point))
4331 b)
4332 ('t
4334 (point)))))
4335 (str (buffer-substring b e)))
4337 (setq str (concat (substring str 0 e) "...")))
4338 str))
4340 (defun verilog-expand-vector ()
4341 "Take a signal vector on the current line and expand it to multiple lines.
4342 Useful for creating tri's and other expanded fields."
4343 (interactive)
4344 (verilog-expand-vector-internal "[" "]"))
4346 (defun verilog-expand-vector-internal (bra ket)
4347 "Given BRA, the start brace and KET, the end brace, expand one line into many lines."
4348 (save-excursion
4349 (forward-line 0)
4350 (let ((signal-string (buffer-substring (point)
4351 (progn
4352 (end-of-line) (point)))))
4353 (if (string-match
4355 (regexp-quote bra)
4357 (regexp-quote ket)
4359 (let* ((sig-head (match-string 1 signal-string))
4360 (vec-start (string-to-number (match-string 2 signal-string)))
4361 (vec-end (if (= (match-beginning 3) (match-end 3))
4362 vec-start
4363 (string-to-number
4364 (substring signal-string (1+ (match-beginning 3))
4365 (match-end 3)))))
4366 (vec-range
4367 (if (= (match-beginning 4) (match-end 4))
4368 1
4369 (string-to-number
4370 (substring signal-string (+ 2 (match-beginning 4))
4371 (match-end 4)))))
4372 (sig-tail (match-string 5 signal-string))
4373 vec)
4374 ;; Decode vectors
4375 (setq vec nil)
4376 (if (< vec-range 0)
4377 (let ((tmp vec-start))
4378 (setq vec-start vec-end
4379 vec-end tmp
4380 vec-range (- vec-range))))
4381 (if (< vec-end vec-start)
4382 (while (<= vec-end vec-start)
4383 (setq vec (append vec (list vec-start)))
4384 (setq vec-start (- vec-start vec-range)))
4385 (while (<= vec-start vec-end)
4386 (setq vec (append vec (list vec-start)))
4387 (setq vec-start (+ vec-start vec-range))))
4388 ;;
4389 ;; Delete current line
4390 (delete-region (point) (progn (forward-line 0) (point)))
4391 ;;
4392 ;; Expand vector
4393 (while vec
4394 (insert (concat sig-head bra
4396 (setq vec (cdr vec)))
4397 (delete-char -1)
4398 ;;
4399 )))))
4401 (defun verilog-strip-comments ()
4402 "Strip all comments from the Verilog code."
4403 (interactive)
4404 (goto-char (point-min))
4405 (while (re-search-forward "//" nil t)
4406 (if (verilog-within-string)
4408 (if (verilog-in-star-comment-p)
4409 (re-search-forward "\*/" nil t)
4410 (let ((bpt (- (point) 2)))
4411 (end-of-line)
4412 (delete-region bpt (point))))))
4413 ;;
4414 (goto-char (point-min))
4416 (if (verilog-within-string)
4418 (let ((bpt (- (point) 2)))
4420 (delete-region bpt (point))))))
4422 (defun verilog-one-line ()
4423 "Convert structural Verilog instances to occupy one line."
4424 (interactive)
4425 (goto-char (point-min))
4429 (defun verilog-linter-name ()
4430 "Return name of linter, either surelint or verilint."
4432 compile-command))
4434 verilog-linter)))
4435 (cond ((equal compile-word1 "surelint") `surelint)
4436 ((equal compile-word1 "verilint") `verilint)
4437 ((equal lint-word1 "surelint") `surelint)
4438 ((equal lint-word1 "verilint") `verilint)
4439 (t `surelint)))) ;; back compatibility
4441 (defun verilog-lint-off ()
4442 "Convert a Verilog linter warning line into a disable statement.
4443 For example:
4444 pci_bfm_null.v, line 46: Unused input: pci_rst_
4445 becomes a comment for the appropriate tool.
4447 The first word of the `compile-command' or `verilog-linter'
4448 variables is used to determine which product is being used.
4451 (interactive)
4452 (let ((linter (verilog-linter-name)))
4453 (cond ((equal linter `surelint)
4454 (verilog-surelint-off))
4455 ((equal linter `verilint)
4456 (verilog-verilint-off))
4457 (t (error "Linter name not set")))))
4459 (defvar compilation-last-buffer)
4460 (defvar next-error-last-buffer)
4462 (defun verilog-surelint-off ()
4463 "Convert a SureLint warning line into a disable statement.
4464 Run from Verilog source window; assumes there is a *compile* buffer
4465 with point set appropriately.
4467 For example:
4468 WARNING [STD-UDDONX]: xx.v, line 8: output out is never assigned.
4469 becomes:
4470 // surefire lint_line_off UDDONX"
4471 (interactive)
4472 (let ((buff (if (boundp 'next-error-last-buffer)
4473 next-error-last-buffer
4474 compilation-last-buffer)))
4475 (when (buffer-live-p buff)
4476 ;; FIXME with-current-buffer?
4477 (save-excursion
4478 (switch-to-buffer buff)
4479 (beginning-of-line)
4480 (when
4481 (looking-at "\\(INFO\\|WARNING\\|ERROR\\) \\[[^-]+-\\([^]]+\\)\\]: \\([^,]+\\), line \\([0-9]+\\): \\(.*\\)$")
4482 (let* ((code (match-string 2))
4483 (file (match-string 3))
4484 (line (match-string 4))
4485 (buffer (get-file-buffer file))
4486 dir filename)
4487 (unless buffer
4488 (progn
4489 (setq buffer
4490 (and (file-exists-p file)
4491 (find-file-noselect file)))
4492 (or buffer
4493 (let* ((pop-up-windows t))
4494 (let ((name (expand-file-name
4495 (read-file-name
4496 (format "Find this error in: (default %s) "
4497 file)
4498 dir file t))))
4499 (if (file-directory-p name)
4500 (setq name (expand-file-name filename name)))
4501 (setq buffer
4502 (and (file-exists-p name)
4503 (find-file-noselect name))))))))
4504 (switch-to-buffer buffer)
4505 (goto-char (point-min))
4506 (forward-line (- (string-to-number line)))
4507 (end-of-line)
4508 (catch 'already
4509 (cond
4510 ((verilog-in-slash-comment-p)
4511 (re-search-backward "//")
4512 (cond
4513 ((looking-at "// surefire lint_off_line ")
4514 (goto-char (match-end 0))
4515 (let ((lim (save-excursion (end-of-line) (point))))
4516 (if (re-search-forward code lim 'move)
4517 (throw 'already t)
4518 (insert (concat " " code)))))
4519 (t
4520 )))
4521 ((verilog-in-star-comment-p)
4522 (re-search-backward "/\*")
4523 (insert (format " // surefire lint_off_line %6s" code )))
4524 (t
4525 (insert (format " // surefire lint_off_line %6s" code ))
4526 )))))))))
4528 (defun verilog-verilint-off ()
4529 "Convert a Verilint warning line into a disable statement.
4531 For example:
4532 (W240) pci_bfm_null.v, line 46: Unused input: pci_rst_
4533 becomes:
4534 //Verilint 240 off // WARNING: Unused input"
4535 (interactive)
4536 (save-excursion
4537 (beginning-of-line)
4538 (when (looking-at "\\(.*\\)([WE]\\([0-9A-Z]+\\)).*,\\s +line\\s +[0-9]+:\\s +\\([^:\n]+\\):?.*$")
4539 (replace-match (format
4540 ;; %3s makes numbers 1-999 line up nicely
4542 (match-string 2)))
4543 (beginning-of-line)
4544 (verilog-indent-line))))
4546 (defun verilog-auto-save-compile ()
4548 (interactive)
4549 (verilog-auto) ; Always do it for safety
4550 (save-buffer)
4551 (compile compile-command))
4553 (defun verilog-preprocess (&optional command filename)
4554 "Preprocess the buffer, similar to `compile', but leave output in Verilog-Mode.
4555 Takes optional COMMAND or defaults to `verilog-preprocessor', and
4556 FILENAME or defaults to `buffer-file-name`."
4557 (interactive
4558 (list
4559 (let ((default (verilog-expand-command verilog-preprocessor)))
4560 (set (make-local-variable `verilog-preprocessor)
4561 (read-from-minibuffer "Run Preprocessor (like this): "
4562 default nil nil
4563 'verilog-preprocess-history default)))))
4564 (unless command (setq command (verilog-expand-command verilog-preprocessor)))
4565 (let* ((dir (file-name-directory (or filename buffer-file-name)))
4566 (file (file-name-nondirectory (or filename buffer-file-name)))
4567 (cmd (concat "cd " dir "; " command " " file)))
4568 (with-output-to-temp-buffer "*Verilog-Preprocessed*"
4569 (save-excursion
4570 (set-buffer "*Verilog-Preprocessed*")
4572 (shell-command cmd "*Verilog-Preprocessed*")
4573 (verilog-mode)
4574 (font-lock-mode)))))
4575 \f
4577 ;;
4578 ;; Batch
4579 ;;
4581 (defmacro verilog-batch-error-wrapper (&rest body)
4582 "Execute BODY and add error prefix to any errors found.
4583 This lets programs calling batch mode to easily extract error messages."
4584 `(condition-case err
4585 (progn ,@body)
4586 (error
4587 (error "%%Error: %s%s" (error-message-string err)
4590 (defun verilog-batch-execute-func (funref)
4591 "Internal processing of a batch command, running FUNREF on all command arguments."
4592 (verilog-batch-error-wrapper
4593 ;; Setting global variables like that is *VERY NASTY* !!! --Stef
4594 ;; However, this function is called only when Emacs is being used as
4595 ;; a standalone language instead of as an editor, so we'll live.
4596 ;;
4597 ;; General globals needed
4598 (setq make-backup-files nil)
4599 (setq-default make-backup-files nil)
4600 (setq enable-local-variables t)
4601 (setq enable-local-eval t)
4602 ;; Make sure any sub-files we read get proper mode
4603 (setq-default major-mode 'verilog-mode)
4604 ;; Ditto files already read in
4605 (mapc (lambda (buf)
4606 (when (buffer-file-name buf)
4607 (with-current-buffer buf
4608 (verilog-mode))))
4609 (buffer-list))
4610 ;; Process the files
4611 (mapcar '(lambda (buf)
4612 (when (buffer-file-name buf)
4613 (save-excursion
4614 (if (not (file-exists-p (buffer-file-name buf)))
4615 (error
4616 (concat "File not found: " (buffer-file-name buf))))
4617 (message (concat "Processing " (buffer-file-name buf)))
4618 (set-buffer buf)
4619 (funcall funref)
4620 (save-buffer))))
4621 (buffer-list))))
4623 (defun verilog-batch-auto ()
4624 "For use with --batch, perform automatic expansions as a stand-alone tool.
4625 This sets up the appropriate Verilog mode environment, updates automatics
4627 For proper results, multiple filenames need to be passed on the command
4628 line in bottom-up order."
4629 (unless noninteractive
4630 (error "Use verilog-batch-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
4631 (verilog-batch-execute-func `verilog-auto))
4633 (defun verilog-batch-delete-auto ()
4634 "For use with --batch, perform automatic deletion as a stand-alone tool.
4635 This sets up the appropriate Verilog mode environment, deletes automatics
4637 (unless noninteractive
4638 (error "Use verilog-batch-delete-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
4639 (verilog-batch-execute-func `verilog-delete-auto))
4641 (defun verilog-batch-inject-auto ()
4642 "For use with --batch, perform automatic injection as a stand-alone tool.
4643 This sets up the appropriate Verilog mode environment, injects new automatics
4645 For proper results, multiple filenames need to be passed on the command
4646 line in bottom-up order."
4647 (unless noninteractive
4648 (error "Use verilog-batch-inject-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
4649 (verilog-batch-execute-func `verilog-inject-auto))
4651 (defun verilog-batch-indent ()
4652 "For use with --batch, reindent an a entire file as a stand-alone tool.
4653 This sets up the appropriate Verilog mode environment, calls
4655 (unless noninteractive
4656 (error "Use verilog-batch-indent only with --batch")) ;; Otherwise we'd mess up buffer modes
4657 (verilog-batch-execute-func `verilog-indent-buffer))
4658 \f
4660 ;;
4661 ;; Indentation
4662 ;;
4663 (defconst verilog-indent-alist
4664 '((block . (+ ind verilog-indent-level))
4665 (case . (+ ind verilog-case-indent))
4666 (cparenexp . (+ ind verilog-indent-level))
4667 (cexp . (+ ind verilog-cexp-indent))
4668 (defun . verilog-indent-level-module)
4669 (declaration . verilog-indent-level-declaration)
4670 (directive . (verilog-calculate-indent-directive))
4671 (tf . verilog-indent-level)
4672 (behavioral . (+ verilog-indent-level-behavioral verilog-indent-level-module))
4673 (statement . ind)
4674 (cpp . 0)
4675 (comment . (verilog-comment-indent))
4676 (unknown . 3)
4677 (string . 0)))
4679 (defun verilog-continued-line-1 (lim)
4680 "Return true if this is a continued line.
4681 Set point to where line starts. Limit search to point LIM."
4682 (let ((continued 't))
4683 (if (eq 0 (forward-line -1))
4684 (progn
4685 (end-of-line)
4686 (verilog-backward-ws&directives lim)
4687 (if (bobp)
4688 (setq continued nil)
4689 (setq continued (verilog-backward-token))))
4690 (setq continued nil))
4691 continued))
4693 (defun verilog-calculate-indent ()
4694 "Calculate the indent of the current Verilog line.
4695 Examine previous lines. Once a line is found that is definitive as to the
4696 type of the current line, return that lines' indent level and its type.
4697 Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
4698 (save-excursion
4699 (let* ((starting_position (point))
4700 (par 0)
4702 (lim (save-excursion (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)" nil t)))
4703 (type (catch 'nesting
4704 ;; Keep working backwards until we can figure out
4705 ;; what type of statement this is.
4706 ;; Basically we need to figure out
4707 ;; 1) if this is a continuation of the previous line;
4708 ;; 2) are we in a block scope (begin..end)
4710 ;; if we are in a comment, done.
4711 (if (verilog-in-star-comment-p)
4712 (throw 'nesting 'comment))
4714 ;; if we have a directive, done.
4715 (if (save-excursion (beginning-of-line)
4716 (and (looking-at verilog-directive-re-1)
4719 (throw 'nesting 'directive))
4720 ;; indent structs as if there were module level
4721 (if (verilog-in-struct-p)
4722 (throw 'nesting 'block))
4724 ;; unless we are in the newfangled coverpoint or constraint blocks
4725 ;; if we are in a parenthesized list, and the user likes to indent these, return.
4726 (if (and
4727 verilog-indent-lists
4728 (verilog-in-paren)
4729 (not (verilog-in-coverage-p))
4730 )
4731 (progn (setq par 1)
4732 (throw 'nesting 'block)))
4734 ;; See if we are continuing a previous line
4735 (while t
4736 ;; trap out if we crawl off the top of the buffer
4737 (if (bobp) (throw 'nesting 'cpp))
4739 (if (verilog-continued-line-1 lim)
4740 (let ((sp (point)))
4741 (if (and
4742 (not (looking-at verilog-complete-reg))
4743 (verilog-continued-line-1 lim))
4744 (progn (goto-char sp)
4745 (throw 'nesting 'cexp))
4747 (goto-char sp))
4749 (if (and begin
4750 (not verilog-indent-begin-after-if)
4751 (looking-at verilog-no-indent-begin-re))
4752 (progn
4753 (beginning-of-line)
4755 (throw 'nesting 'statement))
4756 (progn
4757 (throw 'nesting 'cexp))))
4758 ;; not a continued line
4759 (goto-char starting_position))
4762 ;; search back for governing if, striding across begin..end pairs
4763 ;; appropriately
4764 (let ((elsec 1))
4765 (while (verilog-re-search-backward verilog-ends-re nil 'move)
4766 (cond
4767 ((match-end 1) ; else, we're in deep
4768 (setq elsec (1+ elsec)))
4769 ((match-end 2) ; if
4770 (setq elsec (1- elsec))
4771 (if (= 0 elsec)
4772 (if verilog-align-ifelse
4773 (throw 'nesting 'statement)
4774 (progn ;; back up to first word on this line
4775 (beginning-of-line)
4776 (verilog-forward-syntactic-ws)
4777 (throw 'nesting 'statement)))))
4778 ((match-end 3) ; assert block
4779 (setq elsec (1- elsec))
4780 (verilog-beg-of-statement) ;; doesn't get to beginning
4781 (if (looking-at verilog-property-re)
4782 (throw 'nesting 'statement) ; We don't need an endproperty for these
4783 (throw 'nesting 'block) ;We still need a endproperty
4784 ))
4785 (t ; endblock
4786 ; try to leap back to matching outward block by striding across
4787 ; indent level changing tokens then immediately
4788 ; previous line governs indentation.
4789 (let (( reg) (nest 1))
4790 ;; verilog-ends => else|if|end|join(_any|_none|)|endcase|endclass|endtable|endspecify|endfunction|endtask|endgenerate|endgroup
4791 (cond
4792 ((match-end 4) ; end
4793 ;; Search back for matching begin
4795 ((match-end 5) ; endcase
4796 ;; Search back for matching case
4798 ((match-end 6) ; endfunction
4799 ;; Search back for matching function
4801 ((match-end 7) ; endtask
4802 ;; Search back for matching task
4804 ((match-end 8) ; endspecify
4805 ;; Search back for matching specify
4807 ((match-end 9) ; endtable
4808 ;; Search back for matching table
4810 ((match-end 10) ; endgenerate
4811 ;; Search back for matching generate
4813 ((match-end 11) ; joins
4814 ;; Search back for matching fork
4816 ((match-end 12) ; class
4817 ;; Search back for matching class
4819 ((match-end 13) ; covergroup
4820 ;; Search back for matching covergroup
4822 (catch 'skip
4823 (while (verilog-re-search-backward reg nil 'move)
4824 (cond
4825 ((match-end 1) ; begin
4826 (setq nest (1- nest))
4827 (if (= 0 nest)
4828 (throw 'skip 1)))
4829 ((match-end 2) ; end
4830 (setq nest (1+ nest)))))
4831 )))))))
4832 (throw 'nesting (verilog-calc-1)))
4833 );; catch nesting
4834 );; type
4835 )
4836 ;; Return type of block and indent level.
4837 (if (not type)
4838 (setq type 'cpp))
4839 (if (> par 0) ; Unclosed Parenthesis
4840 (list 'cparenexp par)
4841 (cond
4842 ((eq type 'case)
4843 (list type (verilog-case-indent-level)))
4844 ((eq type 'statement)
4845 (list type (current-column)))
4846 ((eq type 'defun)
4847 (list type 0))
4848 (t
4849 (list type (verilog-current-indent-level))))))))
4851 (defun verilog-wai ()
4852 "Show matching nesting block for debugging."
4853 (interactive)
4854 (save-excursion
4855 (let* ((type (verilog-calc-1))
4856 depth)
4857 ;; Return type of block and indent level.
4858 (if (not type)
4859 (setq type 'cpp))
4860 (if (and
4861 verilog-indent-lists
4862 (not(or (verilog-in-coverage-p)
4863 (verilog-in-struct-p)))
4864 (verilog-in-paren))
4865 (setq depth 1)
4866 (cond
4867 ((eq type 'case)
4868 (setq depth (verilog-case-indent-level)))
4869 ((eq type 'statement)
4870 (setq depth (current-column)))
4871 ((eq type 'defun)
4872 (setq depth 0))
4873 (t
4874 (setq depth (verilog-current-indent-level)))))
4875 (message "You are at nesting %s depth %d" type depth))))
4877 (defun verilog-calc-1 ()
4878 (catch 'nesting
4880 (while (verilog-re-search-backward re nil 'move)
4881 (catch 'continue
4882 (cond
4883 ((equal (char-after) ?\{)
4884 (if (verilog-at-constraint-p)
4885 (throw 'nesting 'block)))
4887 ((equal (char-after) ?\})
4888 (let ((there (verilog-at-close-constraint-p)))
4889 (if there ;; we are at the } that closes a constraint. Find the { that opens it
4890 (progn
4891 (forward-char 1)
4892 (backward-list 1)
4893 (verilog-beg-of-statement)))))
4895 ((looking-at verilog-beg-block-re-ordered)
4896 (cond
4897 ((match-end 2) ; *sigh* could be "unique case" or "priority casex"
4898 (let ((here (point)))
4899 (verilog-beg-of-statement)
4900 (if (looking-at verilog-extended-case-re)
4901 (throw 'nesting 'case)
4902 (goto-char here)))
4903 (throw 'nesting 'case))
4905 ((match-end 4) ; *sigh* could be "disable fork"
4906 (let ((here (point)))
4907 (verilog-beg-of-statement)
4908 (if (or (looking-at verilog-disable-fork-re)
4909 (looking-at verilog-fork-wait-re))
4910 t ; this is a normal statement
4911 (progn ; or is fork, starts a new block
4912 (goto-char here)
4913 (throw 'nesting 'block)))))
4915 ((match-end 27) ; *sigh* might be a clocking declaration
4916 (let ((here (point)))
4917 (if (verilog-in-paren)
4918 t ; this is a normal statement
4919 (progn ; or is fork, starts a new block
4920 (goto-char here)
4921 (throw 'nesting 'block)))))
4923 ;; need to consider typedef struct here...
4925 ; *sigh* These words have an optional prefix:
4926 ; extern {virtual|protected}? function a();
4927 ; typedef class foo;
4928 ; and we don't want to confuse this with
4929 ; function a();
4930 ; property
4931 ; ...
4932 ; endfunction
4933 (verilog-beg-of-statement)
4934 (if (looking-at verilog-beg-block-re-ordered)
4935 (throw 'nesting 'block)
4936 (throw 'nesting 'defun)))
4939 ; *sigh*
4940 ; {assert|assume|cover} property (); are complete
4941 ; and could also be labeled: - foo: assert property
4942 ; but
4943 ; property ID () ... needs end_property
4944 (verilog-beg-of-statement)
4945 (if (looking-at verilog-property-re)
4946 (throw 'continue 'statement) ; We don't need an endproperty for these
4947 (throw 'nesting 'block) ;We still need a endproperty
4948 ))
4950 (t (throw 'nesting 'block))))
4952 ((looking-at verilog-end-block-re)
4953 (verilog-leap-to-head)
4954 (if (verilog-in-case-region-p)
4955 (progn
4956 (verilog-leap-to-case-head)
4957 (if (looking-at verilog-extended-case-re)
4958 (throw 'nesting 'case)))))
4960 ((looking-at verilog-defun-level-re)
4961 (if (looking-at verilog-defun-level-generate-only-re)
4962 (if (verilog-in-generate-region-p)
4963 (throw 'continue 'foo) ; always block in a generate - keep looking
4964 (throw 'nesting 'defun))
4965 (throw 'nesting 'defun)))
4967 ((looking-at verilog-cpp-level-re)
4968 (throw 'nesting 'cpp))
4970 ((bobp)
4971 (throw 'nesting 'cpp)))))
4973 (throw 'nesting 'cpp))))
4975 (defun verilog-calculate-indent-directive ()
4976 "Return indentation level for directive.
4977 For speed, the searcher looks at the last directive, not the indent
4978 of the appropriate enclosing block."
4979 (let ((base -1) ;; Indent of the line that determines our indentation
4980 (ind 0)) ;; Relative offset caused by other directives (like `endif on same line as `else)
4981 ;; Start at current location, scan back for another directive
4983 (save-excursion
4984 (beginning-of-line)
4985 (while (and (< base 0)
4986 (verilog-re-search-backward verilog-directive-re nil t))
4988 (setq base (current-indentation))))
4989 (cond ((and (looking-at verilog-directive-end) (< base 0)) ;; Only matters when not at BOL
4990 (setq ind (- ind verilog-indent-level-directive)))
4991 ((and (looking-at verilog-directive-middle) (>= base 0)) ;; Only matters when at BOL
4992 (setq ind (+ ind verilog-indent-level-directive)))
4993 ((looking-at verilog-directive-begin)
4994 (setq ind (+ ind verilog-indent-level-directive)))))
4995 ;; Adjust indent to starting indent of critical line
4996 (setq ind (max 0 (+ ind base))))
4998 (save-excursion
4999 (beginning-of-line)
5001 (cond ((or (looking-at verilog-directive-middle)
5002 (looking-at verilog-directive-end))
5003 (setq ind (max 0 (- ind verilog-indent-level-directive))))))
5004 ind))
5006 (defun verilog-leap-to-case-head ()
5007 (let ((nest 1))
5008 (while (/= 0 nest)
5009 (verilog-re-search-backward
5010 (concat
5013 nil 'move)
5014 (cond
5015 ((match-end 1)
5016 (let ((here (point)))
5017 (verilog-beg-of-statement)
5018 (unless (looking-at verilog-extended-case-re)
5019 (goto-char here)))
5020 (setq nest (1- nest)))
5021 ((match-end 3)
5022 (setq nest (1+ nest)))
5023 ((bobp)
5024 (ding 't)
5025 (setq nest 0))))))
5027 (defun verilog-leap-to-head ()
5028 "Move point to the head of this block.
5029 Jump from end to matching begin, from endcase to matching case, and so on."
5030 (let ((reg nil)
5031 snest
5032 (nesting 'yes)
5033 (nest 1))
5034 (cond
5036 ;; 1: Search back for matching begin
5040 ;; 2: Search back for matching task
5041 (setq reg "\\(\\<task\\>\\)\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)+\\<task\\>\\)")
5042 (setq nesting 'no))
5044 (catch 'nesting
5045 (verilog-leap-to-case-head) )
5046 (setq reg nil) ; to force skip
5047 )
5050 ;; 4: Search back for matching fork
5053 ;; 5: Search back for matching class
5056 ;; 6: Search back for matching table
5059 ;; 7: Search back for matching specify
5062 ;; 8: Search back for matching function
5063 (setq reg "\\(\\<function\\>\\)\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)+\\<function\\>\\)")
5064 (setq nesting 'no))
5067 ;; 8: Search back for matching generate
5070 ;; 10: Search back for matching covergroup
5073 ;; 11: Search back for matching property
5075 ((looking-at verilog-ovm-end-re)
5076 ;; 12: Search back for matching sequence
5078 ((looking-at verilog-vmm-end-re)
5079 ;; 12: Search back for matching sequence
5082 ;; 12: Search back for matching interface
5085 ;; 12: Search back for matching sequence
5088 ;; 12: Search back for matching clocking
5090 (if reg
5091 (catch 'skip
5092 (if (eq nesting 'yes)
5093 (let (sreg)
5094 (while (verilog-re-search-backward reg nil 'move)
5095 (cond
5096 ((match-end 1) ; begin
5097 (if (looking-at "fork")
5098 (let ((here (point)))
5099 (verilog-beg-of-statement)
5100 (unless (looking-at verilog-disable-fork-re)
5101 (goto-char here)
5102 (setq nest (1- nest))))
5103 (setq nest (1- nest)))
5104 (if (= 0 nest)
5105 ;; Now previous line describes syntax
5106 (throw 'skip 1))
5107 (if (and snest
5108 (= snest nest))
5109 (setq reg sreg)))
5110 ((match-end 2) ; end
5111 (setq nest (1+ nest)))
5112 ((match-end 3)
5113 ;; endcase, jump to case
5114 (setq snest nest)
5115 (setq nest (1+ nest))
5116 (setq sreg reg)
5118 ((match-end 4)
5119 ;; join, jump to fork
5120 (setq snest nest)
5121 (setq nest (1+ nest))
5122 (setq sreg reg)
5124 )))
5125 ;no nesting
5126 (if (and
5127 (verilog-re-search-backward reg nil 'move)
5128 (match-end 1)) ; task -> could be virtual and/or protected
5129 (progn
5130 (verilog-beg-of-statement)
5131 (throw 'skip 1))
5132 (throw 'skip 1)))))))
5134 (defun verilog-continued-line ()
5135 "Return true if this is a continued line.
5136 Set point to where line starts."
5137 (let ((continued 't))
5138 (if (eq 0 (forward-line -1))
5139 (progn
5140 (end-of-line)
5141 (verilog-backward-ws&directives)
5142 (if (bobp)
5143 (setq continued nil)
5144 (while (and continued
5145 (save-excursion
5147 (not (bolp))))
5148 (setq continued (verilog-backward-token)))))
5149 (setq continued nil))
5150 continued))
5152 (defun verilog-backward-token ()
5153 "Step backward token, returing true if this is a continued line."
5154 (interactive)
5155 (verilog-backward-syntactic-ws)
5156 (cond
5157 ((bolp)
5158 nil)
5159 (;-- Anything ending in a ; is complete
5160 (= (preceding-char) ?\;)
5161 nil)
5162 (; If a "}" is prefixed by a ";", then this is a complete statement
5163 ; i.e.: constraint foo { a = b; }
5164 (= (preceding-char) ?\})
5165 (progn
5166 (backward-char)
5167 (not(verilog-at-close-constraint-p))))
5168 (;-- constraint foo { a = b }
5169 ; is a complete statement. *sigh*
5170 (= (preceding-char) ?\{)
5171 (progn
5172 (backward-char)
5173 (not (verilog-at-constraint-p))))
5174 (;" string "
5176 (backward-char)
5177 (verilog-skip-backward-comment-or-string)
5178 nil)
5180 (; [3:4]
5181 (= (preceding-char) ?\])
5182 (backward-char)
5183 (verilog-backward-open-bracket)
5184 t)
5186 (;-- Could be 'case (foo)' or 'always @(bar)' which is complete
5187 ; also could be simply '@(foo)'
5188 ; or foo u1 #(a=8)
5189 ; (b, ... which ISN'T complete
5190 ;;;; Do we need this???
5191 (= (preceding-char) ?\))
5192 (progn
5193 (backward-char)
5194 (verilog-backward-up-list 1)
5195 (verilog-backward-syntactic-ws)
5196 (let ((back (point)))
5197 (forward-word -1)
5198 (cond
5199 ;;XX
5200 ((looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|case\\(\\|[xz]\\)\\|for\\(\\|each\\|ever\\)\\|i\\(f\\|nitial\\)\\|repeat\\|while\\)\\>")
5202 ((looking-at verilog-ovm-statement-re)
5203 nil)
5204 ((looking-at verilog-ovm-begin-re)
5205 t)
5206 ((looking-at verilog-ovm-end-re)
5207 t)
5208 ;; JBA find VMM macros
5209 ((looking-at verilog-vmm-statement-re)
5210 nil )
5211 ((looking-at verilog-vmm-begin-re)
5212 t)
5213 ((looking-at verilog-vmm-end-re)
5214 nil)
5215 ;; JBA trying to catch macro lines with no ; at end
5217 nil)
5218 (t
5219 (goto-char back)
5220 (cond
5221 ((= (preceding-char) ?\@)
5222 (backward-char)
5223 (save-excursion
5224 (verilog-backward-token)
5226 ((= (preceding-char) ?\#)
5227 (backward-char))
5228 (t t)))))))
5230 (;-- any of begin|initial|while are complete statements; 'begin : foo' is also complete
5231 t
5232 (forward-word -1)
5233 (while (= (preceding-char) ?\_)
5234 (forward-word -1))
5235 (cond
5237 t)
5238 ((looking-at verilog-behavioral-block-beg-re)
5239 t)
5240 ((looking-at verilog-indent-re)
5241 nil)
5242 (t
5243 (let
5244 ((back (point)))
5245 (verilog-backward-syntactic-ws)
5246 (cond
5247 ((= (preceding-char) ?\:)
5248 (backward-char)
5249 (verilog-backward-syntactic-ws)
5250 (backward-sexp)
5251 (if (looking-at verilog-nameable-item-re )
5252 nil
5253 t))
5254 ((= (preceding-char) ?\#)
5255 (backward-char)
5256 t)
5257 ((= (preceding-char) ?\`)
5258 (backward-char)
5259 t)
5261 (t
5262 (goto-char back)
5263 t))))))))
5265 (defun verilog-backward-syntactic-ws ()
5266 (verilog-skip-backward-comments)
5267 (forward-comment (- (buffer-size))))
5269 (defun verilog-forward-syntactic-ws ()
5270 (verilog-skip-forward-comment-p)
5271 (forward-comment (buffer-size)))
5273 (defun verilog-backward-ws&directives (&optional bound)
5274 "Backward skip over syntactic whitespace and compiler directives for Emacs 19.
5275 Optional BOUND limits search."
5276 (save-restriction
5277 (let* ((bound (or bound (point-min)))
5278 (here bound)
5279 (p nil) )
5280 (if (< bound (point))
5281 (progn
5282 (let ((state (save-excursion (verilog-syntax-ppss))))
5283 (cond
5284 ((nth 7 state) ;; in // comment
5285 (verilog-re-search-backward "//" nil 'move)
5286 (skip-chars-backward "/"))
5287 ((nth 4 state) ;; in /* */ comment
5288 (verilog-re-search-backward "/\*" nil 'move))))
5289 (narrow-to-region bound (point))
5290 (while (/= here (point))
5291 (setq here (point))
5292 (verilog-skip-backward-comments)
5293 (setq p
5294 (save-excursion
5295 (beginning-of-line)
5296 (cond
5297 ((and verilog-highlight-translate-off
5298 (verilog-within-translate-off))
5299 (verilog-back-to-start-translate-off (point-min)))
5300 ((looking-at verilog-directive-re-1)
5301 (point))
5302 (t
5303 nil))))
5304 (if p (goto-char p))))))))
5306 (defun verilog-forward-ws&directives (&optional bound)
5307 "Forward skip over syntactic whitespace and compiler directives for Emacs 19.
5308 Optional BOUND limits search."
5309 (save-restriction
5310 (let* ((bound (or bound (point-max)))
5311 (here bound)
5312 jump)
5313 (if (> bound (point))
5314 (progn
5315 (let ((state (save-excursion (verilog-syntax-ppss))))
5316 (cond
5317 ((nth 7 state) ;; in // comment
5318 (end-of-line)
5319 (forward-char 1)
5321 )
5322 ((nth 4 state) ;; in /* */ comment
5324 (narrow-to-region (point) bound)
5325 (while (/= here (point))
5326 (setq here (point)
5327 jump nil)
5328 (forward-comment (buffer-size))
5330 (goto-char (match-end 0)))
5331 (save-excursion
5332 (beginning-of-line)
5333 (if (looking-at verilog-directive-re-1)
5334 (setq jump t)))
5335 (if jump
5336 (beginning-of-line 2))))))))
5338 (defun verilog-in-comment-p ()
5339 "Return true if in a star or // comment."
5340 (let ((state (save-excursion (verilog-syntax-ppss))))
5341 (or (nth 4 state) (nth 7 state))))
5343 (defun verilog-in-star-comment-p ()
5344 "Return true if in a star comment."
5345 (let ((state (save-excursion (verilog-syntax-ppss))))
5346 (and
5347 (nth 4 state) ; t if in a comment of style a // or b /**/
5348 (not
5349 (nth 7 state) ; t if in a comment of style b /**/
5350 ))))
5352 (defun verilog-in-slash-comment-p ()
5353 "Return true if in a slash comment."
5354 (let ((state (save-excursion (verilog-syntax-ppss))))
5355 (nth 7 state)))
5357 (defun verilog-in-comment-or-string-p ()
5358 "Return true if in a string or comment."
5359 (let ((state (save-excursion (verilog-syntax-ppss))))
5360 (or (nth 3 state) (nth 4 state) (nth 7 state)))) ; Inside string or comment)
5362 (defun verilog-in-attribute-p ()
5363 "Return true if point is in an attribute (* [] attribute *)."
5364 (save-excursion
5366 (numberp (match-beginning 1))))
5368 (defun verilog-in-escaped-name-p ()
5369 "Return true if in an escaped name."
5370 (save-excursion
5371 (backward-char)
5374 t
5375 nil)))
5376 (defun verilog-in-directive-p ()
5377 "Return true if in a directive."
5378 (save-excursion
5379 (beginning-of-line)
5380 (looking-at verilog-directive-re-1)))
5382 (defun verilog-in-paren ()
5383 "Return true if in a parenthetical expression."
5384 (let ((state (save-excursion (verilog-syntax-ppss))))
5385 (> (nth 0 state) 0 )))
5387 (defun verilog-in-struct-p ()
5388 "Return true if in a struct declaration."
5389 (interactive)
5390 (save-excursion
5391 (if (verilog-in-paren)
5392 (progn
5393 (verilog-backward-up-list 1)
5394 (verilog-at-struct-p)
5395 )
5396 nil)))
5398 (defun verilog-in-coverage-p ()
5399 "Return true if in a constraint or coverpoint expression."
5400 (interactive)
5401 (save-excursion
5402 (if (verilog-in-paren)
5403 (progn
5404 (verilog-backward-up-list 1)
5405 (verilog-at-constraint-p)
5406 )
5407 nil)))
5408 (defun verilog-at-close-constraint-p ()
5409 "If at the } that closes a constraint or covergroup, return true."
5410 (if (and
5411 (equal (char-after) ?\})
5412 (verilog-in-paren))
5414 (save-excursion
5415 (verilog-backward-ws&directives)
5416 (if (equal (char-before) ?\;)
5417 (point)
5418 nil))))
5420 (defun verilog-at-constraint-p ()
5421 "If at the { of a constraint or coverpoint definition, return true, moving point to constraint."
5422 (if (save-excursion
5423 (and
5424 (equal (char-after) ?\{)
5425 (forward-list)
5426 (progn (backward-char 1)
5427 (verilog-backward-ws&directives)
5428 (equal (char-before) ?\;))))
5429 ;; maybe
5431 ;; not
5432 nil))
5434 (defun verilog-at-struct-p ()
5435 "If at the { of a struct, return true, moving point to struct."
5436 (save-excursion
5437 (if (and (equal (char-after) ?\{)
5438 (verilog-backward-token))
5440 nil)))
5442 (defun verilog-parenthesis-depth ()
5443 "Return non zero if in parenthetical-expression."
5444 (save-excursion (nth 1 (verilog-syntax-ppss))))
5447 (defun verilog-skip-forward-comment-or-string ()
5448 "Return true if in a string or comment."
5449 (let ((state (save-excursion (verilog-syntax-ppss))))
5450 (cond
5451 ((nth 3 state) ;Inside string
5453 t)
5454 ((nth 7 state) ;Inside // comment
5455 (forward-line 1)
5456 t)
5457 ((nth 4 state) ;Inside any comment (hence /**/)
5458 (search-forward "*/"))
5459 (t
5460 nil))))
5462 (defun verilog-skip-backward-comment-or-string ()
5463 "Return true if in a string or comment."
5464 (let ((state (save-excursion (verilog-syntax-ppss))))
5465 (cond
5466 ((nth 3 state) ;Inside string
5468 t)
5469 ((nth 7 state) ;Inside // comment
5470 (search-backward "//")
5471 (skip-chars-backward "/")
5472 t)
5473 ((nth 4 state) ;Inside /* */ comment
5474 (search-backward "/*")
5475 t)
5476 (t
5477 nil))))
5479 (defun verilog-skip-backward-comments ()
5480 "Return true if a comment was skipped."
5481 (let ((more t))
5482 (while more
5483 (setq more
5484 (let ((state (save-excursion (verilog-syntax-ppss))))
5485 (cond
5486 ((nth 7 state) ;Inside // comment
5487 (search-backward "//")
5488 (skip-chars-backward "/")
5490 t)
5491 ((nth 4 state) ;Inside /* */ comment
5492 (search-backward "/*")
5494 t)
5495 ((and (not (bobp))
5496 (= (char-before) ?\/)
5497 (= (char-before (1- (point))) ?\*))
5498 (goto-char (- (point) 2))
5499 t) ;; Let nth 4 state handle the rest
5500 ((and (not (bobp))
5501 (= (char-before) ?\))
5502 (= (char-before (1- (point))) ?\*))
5503 (goto-char (- (point) 2))
5504 (if (search-backward "(*" nil t)
5505 (progn
5507 t)
5508 (progn
5509 (goto-char (+ (point) 2))
5510 nil)))
5511 (t
5514 (defun verilog-skip-forward-comment-p ()
5515 "If in comment, move to end and return true."
5516 (let* (h
5517 (state (save-excursion (verilog-syntax-ppss)))
5518 (skip (cond
5519 ((nth 3 state) ;Inside string
5520 t)
5521 ((nth 7 state) ;Inside // comment
5522 (end-of-line)
5523 (forward-char 1)
5524 t)
5525 ((nth 4 state) ;Inside /* comment
5526 (search-forward "*/")
5527 t)
5528 ((verilog-in-attribute-p) ;Inside (* attribute
5529 (search-forward "*)" nil t)
5530 t)
5531 (t nil))))
5533 (while
5534 (cond
5536 (progn
5537 (setq h (point))
5538 (goto-char (match-end 0))
5539 (if (search-forward "*/" nil t)
5540 (progn
5542 (setq skip 't))
5543 (progn
5544 (goto-char h)
5545 nil))))
5547 (progn
5548 (setq h (point))
5549 (goto-char (match-end 0))
5550 (if (search-forward "*)" nil t)
5551 (progn
5553 (setq skip 't))
5554 (progn
5555 (goto-char h)
5556 nil))))
5557 (t nil)))
5558 skip))
5560 (defun verilog-indent-line-relative ()
5561 "Cheap version of indent line.
5562 Only look at a few lines to determine indent level."
5563 (interactive)
5564 (let ((indent-str)
5565 (sp (point)))
5567 (cond ;- A blank line; No need to be too smart.
5568 ((bobp)
5569 (setq indent-str (list 'cpp 0)))
5570 ((verilog-continued-line)
5571 (let ((sp1 (point)))
5572 (if (verilog-continued-line)
5573 (progn
5574 (goto-char sp)
5575 (setq indent-str
5576 (list 'statement (verilog-current-indent-level))))
5577 (goto-char sp1)
5578 (setq indent-str (list 'block (verilog-current-indent-level)))))
5579 (goto-char sp))
5580 ((goto-char sp)
5581 (setq indent-str (verilog-calculate-indent))))
5583 (setq indent-str (verilog-calculate-indent))))
5584 (verilog-do-indent indent-str)))
5586 (defun verilog-indent-line ()
5587 "Indent for special part of code."
5588 (verilog-do-indent (verilog-calculate-indent)))
5590 (defun verilog-do-indent (indent-str)
5591 (let ((type (car indent-str))
5592 (ind (car (cdr indent-str))))
5593 (cond
5594 (; handle continued exp
5595 (eq type 'cexp)
5596 (let ((here (point)))
5597 (verilog-backward-syntactic-ws)
5598 (cond
5599 ((or
5600 (= (preceding-char) ?\,)
5601 (= (preceding-char) ?\])
5602 (save-excursion
5603 (verilog-beg-of-statement-1)
5604 (looking-at verilog-declaration-re)))
5605 (let* ( fst
5606 (val
5607 (save-excursion
5608 (backward-char 1)
5609 (verilog-beg-of-statement-1)
5610 (setq fst (point))
5611 (if (looking-at verilog-declaration-re)
5612 (progn ;; we have multiple words
5613 (goto-char (match-end 0))
5615 (cond
5616 ((and verilog-indent-declaration-macros
5617 (= (following-char) ?\`))
5618 (progn
5619 (forward-char 1)
5620 (forward-word 1)
5622 ((= (following-char) ?\[)
5623 (progn
5624 (forward-char 1)
5625 (verilog-backward-up-list -1)
5627 (current-column))
5628 (progn
5629 (goto-char fst)
5630 (+ (current-column) verilog-cexp-indent))))))
5631 (goto-char here)
5632 (indent-line-to val)))
5633 ((= (preceding-char) ?\) )
5634 (goto-char here)
5635 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
5636 (indent-line-to val)))
5637 (t
5638 (goto-char here)
5639 (let ((val))
5640 (verilog-beg-of-statement-1)
5641 (if (and (< (point) here)
5643 (setq val (current-column))
5644 (setq val (eval (cdr (assoc type verilog-indent-alist)))))
5645 (goto-char here)
5646 (indent-line-to val))))))
5648 (; handle inside parenthetical expressions
5649 (eq type 'cparenexp)
5650 (let* ( here
5651 (val (save-excursion
5652 (verilog-backward-up-list 1)
5653 (forward-char 1)
5654 (if verilog-indent-lists
5656 (verilog-forward-syntactic-ws))
5657 (setq here (point))
5658 (current-column)))
5660 (decl (save-excursion
5661 (goto-char here)
5662 (verilog-forward-syntactic-ws)
5663 (setq here (point))
5664 (looking-at verilog-declaration-re))))
5665 (indent-line-to val)
5666 (if decl
5667 (verilog-pretty-declarations))))
5669 (;-- Handle the ends
5670 (or
5671 (looking-at verilog-end-block-re )
5672 (verilog-at-close-constraint-p))
5673 (let ((val (if (eq type 'statement)
5674 (- ind verilog-indent-level)
5675 ind)))
5676 (indent-line-to val)))
5678 (;-- Case -- maybe line 'em up
5680 (progn
5681 (cond
5683 (indent-line-to ind))
5684 (t
5685 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
5686 (indent-line-to val))))))
5688 (;-- defun
5689 (and (eq type 'defun)
5690 (looking-at verilog-zero-indent-re))
5691 (indent-line-to 0))
5693 (;-- declaration
5694 (and (or
5695 (eq type 'defun)
5696 (eq type 'block))
5697 (looking-at verilog-declaration-re))
5698 (verilog-indent-declaration ind))
5700 (;-- Everything else
5701 t
5702 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
5703 (indent-line-to val))))
5707 indent-str ; Return indent data
5708 ))
5710 (defun verilog-current-indent-level ()
5711 "Return the indent-level of the current statement."
5712 (save-excursion
5713 (let (par-pos)
5714 (beginning-of-line)
5715 (setq par-pos (verilog-parenthesis-depth))
5716 (while par-pos
5717 (goto-char par-pos)
5718 (beginning-of-line)
5719 (setq par-pos (verilog-parenthesis-depth)))
5721 (current-column))))
5723 (defun verilog-case-indent-level ()
5724 "Return the indent-level of the current statement.
5725 Do not count named blocks or case-statements."
5726 (save-excursion
5728 (cond
5729 ((looking-at verilog-named-block-re)
5730 (current-column))
5731 ((and (not (looking-at verilog-extended-case-re))
5733 (verilog-re-search-forward ":" nil t)
5735 (current-column))
5736 (t
5737 (current-column)))))
5739 (defun verilog-indent-comment ()
5740 "Indent current line as comment."
5741 (let* ((stcol
5742 (cond
5743 ((verilog-in-star-comment-p)
5744 (save-excursion
5746 (1+(current-column))))
5747 (comment-column
5748 comment-column )
5749 (t
5750 (save-excursion
5751 (re-search-backward "//" nil t)
5752 (current-column))))))
5753 (indent-line-to stcol)
5754 stcol))
5756 (defun verilog-more-comment ()
5757 "Make more comment lines like the previous."
5758 (let* ((star 0)
5759 (stcol
5760 (cond
5761 ((verilog-in-star-comment-p)
5762 (save-excursion
5763 (setq star 1)
5765 (1+(current-column))))
5766 (comment-column
5767 comment-column )
5768 (t
5769 (save-excursion
5770 (re-search-backward "//" nil t)
5771 (current-column))))))
5772 (progn
5773 (indent-to stcol)
5774 (if (and star
5775 (save-excursion
5776 (forward-line -1)
5778 (looking-at "\*")))
5779 (insert "* ")))))
5781 (defun verilog-comment-indent (&optional arg)
5782 "Return the column number the line should be indented to.
5783 ARG is ignored, for `comment-indent-function' compatibility."
5784 (cond
5785 ((verilog-in-star-comment-p)
5786 (save-excursion
5788 (1+(current-column))))
5789 ( comment-column
5790 comment-column )
5791 (t
5792 (save-excursion
5793 (re-search-backward "//" nil t)
5794 (current-column)))))
5796 ;;
5798 (defun verilog-pretty-declarations (&optional quiet)
5799 "Line up declarations around point.
5800 Be verbose about progress unless optional QUIET set."
5801 (interactive)
5802 (let* ((m1 (make-marker))
5803 (e (point))
5804 el
5805 r
5806 (here (point))
5807 ind
5808 start
5809 startpos
5810 end
5811 endpos
5812 base-ind
5813 )
5814 (save-excursion
5815 (if (progn
5816 ; (verilog-beg-of-statement-1)
5817 (beginning-of-line)
5818 (verilog-forward-syntactic-ws)
5819 (and (not (verilog-in-directive-p)) ;; could have `define input foo
5820 (looking-at verilog-declaration-re)))
5821 (progn
5822 (if (verilog-parenthesis-depth)
5823 ;; in an argument list or parameter block
5824 (setq el (verilog-backward-up-list -1)
5825 start (progn
5826 (goto-char e)
5827 (verilog-backward-up-list 1)
5828 (forward-line) ;; ignore ( input foo,
5829 (verilog-re-search-forward verilog-declaration-re el 'move)
5830 (goto-char (match-beginning 0))
5832 (point))
5833 startpos (set-marker (make-marker) start)
5834 end (progn
5835 (goto-char start)
5836 (verilog-backward-up-list -1)
5837 (forward-char -1)
5838 (verilog-backward-syntactic-ws)
5839 (point))
5840 endpos (set-marker (make-marker) end)
5841 base-ind (progn
5842 (goto-char start)
5843 (forward-char 1)
5845 (current-column))
5846 )
5847 ;; in a declaration block (not in argument list)
5848 (setq
5849 start (progn
5850 (verilog-beg-of-statement-1)
5851 (while (and (looking-at verilog-declaration-re)
5852 (not (bobp)))
5854 (setq e (point))
5855 (beginning-of-line)
5856 (verilog-backward-syntactic-ws)
5857 (backward-char)
5858 (verilog-beg-of-statement-1))
5859 e)
5860 startpos (set-marker (make-marker) start)
5861 end (progn
5862 (goto-char here)
5863 (verilog-end-of-statement)
5864 (setq e (point)) ;Might be on last line
5865 (verilog-forward-syntactic-ws)
5866 (while (looking-at verilog-declaration-re)
5867 (verilog-end-of-statement)
5868 (setq e (point))
5869 (verilog-forward-syntactic-ws))
5870 e)
5871 endpos (set-marker (make-marker) end)
5872 base-ind (progn
5873 (goto-char start)
5874 (verilog-do-indent (verilog-calculate-indent))
5875 (verilog-forward-ws&directives)
5876 (current-column))))
5877 ;; OK, start and end are set
5878 (goto-char (marker-position startpos))
5879 (if (and (not quiet)
5880 (> (- end start) 100))
5881 (message "Lining up declarations..(please stand by)"))
5882 ;; Get the beginning of line indent first
5883 (while (progn (setq e (marker-position endpos))
5884 (< (point) e))
5885 (cond
5887 (bolp))
5888 (verilog-forward-ws&directives)
5889 (indent-line-to base-ind)
5890 (verilog-forward-ws&directives)
5891 (if (< (point) e)
5893 (t
5894 (just-one-space)
5896 ;;(forward-line)
5897 )
5898 ;; Now find biggest prefix
5899 (setq ind (verilog-get-lineup-indent (marker-position startpos) endpos))
5900 ;; Now indent each line.
5901 (goto-char (marker-position startpos))
5902 (while (progn (setq e (marker-position endpos))
5903 (setq r (- e (point)))
5904 (> r 0))
5905 (setq e (point))
5906 (unless quiet (message "%d" r))
5907 ;;(verilog-do-indent (verilog-calculate-indent)))
5908 (verilog-forward-ws&directives)
5909 (cond
5910 ((or (and verilog-indent-declaration-macros
5911 (looking-at verilog-declaration-re-2-macro))
5912 (looking-at verilog-declaration-re-2-no-macro))
5913 (let ((p (match-end 0)))
5914 (set-marker m1 p)
5915 (if (verilog-re-search-forward "[[#`]" p 'move)
5916 (progn
5917 (forward-char -1)
5918 (just-one-space)
5919 (goto-char (marker-position m1))
5920 (just-one-space)
5921 (indent-to ind))
5922 (progn
5923 (just-one-space)
5924 (indent-to ind)))))
5925 ((verilog-continued-line-1 (marker-position startpos))
5926 (goto-char e)
5927 (indent-line-to ind))
5928 ((verilog-in-struct-p)
5929 ;; could have a declaration of a user defined item
5930 (goto-char e)
5931 (verilog-end-of-statement))
5932 (t ; Must be comment or white space
5933 (goto-char e)
5934 (verilog-forward-ws&directives)
5935 (forward-line -1)))
5936 (forward-line 1))
5937 (unless quiet (message "")))))))
5939 (defun verilog-pretty-expr (&optional quiet myre)
5940 "Line up expressions around point, optionally QUIET with regexp MYRE."
5942 (save-excursion
5943 (if (or (eq myre nil)
5944 (string-equal myre ""))
5946 ;; want to match the first <= | := | =
5949 (beginning-of-line)
5950 (if (and (not (looking-at rexp ))
5951 (looking-at myre)
5952 (save-excursion
5953 (goto-char (match-beginning 2))
5954 (not (verilog-in-comment-or-string-p))))
5955 (let* ((here (point))
5956 (e) (r)
5957 (start
5958 (progn
5959 (beginning-of-line)
5960 (setq e (point))
5961 (verilog-backward-syntactic-ws)
5962 (beginning-of-line)
5963 (while (and (not (looking-at rexp ))
5964 (looking-at myre)
5965 (not (bobp))
5966 )
5967 (setq e (point))
5968 (verilog-backward-syntactic-ws)
5969 (beginning-of-line)
5970 ) ;Ack, need to grok `define
5971 e))
5972 (end
5973 (progn
5974 (goto-char here)
5975 (end-of-line)
5976 (setq e (point)) ;Might be on last line
5977 (verilog-forward-syntactic-ws)
5978 (beginning-of-line)
5979 (while (and
5980 (not (looking-at rexp ))
5981 (looking-at myre)
5982 (progn
5983 (end-of-line)
5984 (not (eq e (point)))))
5985 (setq e (point))
5986 (verilog-forward-syntactic-ws)
5987 (beginning-of-line)
5988 )
5989 e))
5990 (endpos (set-marker (make-marker) end))
5991 (ind)
5992 )
5993 (goto-char start)
5994 (verilog-do-indent (verilog-calculate-indent))
5995 (if (and (not quiet)
5996 (> (- end start) 100))
5997 (message "Lining up expressions..(please stand by)"))
5999 ;; Set indent to minimum throughout region
6000 (while (< (point) (marker-position endpos))
6001 (beginning-of-line)
6002 (verilog-just-one-space myre)
6003 (end-of-line)
6004 (verilog-forward-syntactic-ws)
6005 )
6007 ;; Now find biggest prefix
6008 (setq ind (verilog-get-lineup-indent-2 myre start endpos))
6010 ;; Now indent each line.
6011 (goto-char start)
6012 (while (progn (setq e (marker-position endpos))
6013 (setq r (- e (point)))
6014 (> r 0))
6015 (setq e (point))
6016 (if (not quiet) (message "%d" r))
6017 (cond
6018 ((looking-at myre)
6019 (goto-char (match-beginning 2))
6020 (if (not (verilog-parenthesis-depth)) ;; ignore parenthesized exprs
6021 (if (eq (char-after) ?=)
6022 (indent-to (1+ ind)) ; line up the = of the <= with surrounding =
6023 (indent-to ind)
6024 )))
6025 ((verilog-continued-line-1 start)
6026 (goto-char e)
6027 (indent-line-to ind))
6028 (t ; Must be comment or white space
6029 (goto-char e)
6030 (verilog-forward-ws&directives)
6031 (forward-line -1))
6032 )
6033 (forward-line 1))
6034 (unless quiet (message ""))
6035 )))))
6037 (defun verilog-just-one-space (myre)
6038 "Remove extra spaces around regular expression MYRE."
6039 (interactive)
6040 (if (and (not(looking-at verilog-complete-reg))
6041 (looking-at myre))
6042 (let ((p1 (match-end 1))
6043 (p2 (match-end 2)))
6044 (progn
6045 (goto-char p2)
6047 (goto-char p1)
6048 (forward-char -1)
6050 ))))
6052 (defun verilog-indent-declaration (baseind)
6053 "Indent current lines as declaration.
6054 Line up the variable names based on previous declaration's indentation.
6055 BASEIND is the base indent to offset everything."
6056 (interactive)
6057 (let ((pos (point-marker))
6058 (lim (save-excursion
6059 ;; (verilog-re-search-backward verilog-declaration-opener nil 'move)
6060 (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)\\|\\(\\<task\\>\\)" nil 'move)
6061 (point)))
6062 (ind)
6063 (val)
6064 (m1 (make-marker)))
6065 (setq val
6066 (+ baseind (eval (cdr (assoc 'declaration verilog-indent-alist)))))
6067 (indent-line-to val)
6069 ;; Use previous declaration (in this module) as template.
6070 (if (or (eq 'all verilog-auto-lineup)
6071 (eq 'declarations verilog-auto-lineup))
6072 (if (verilog-re-search-backward
6073 (or (and verilog-indent-declaration-macros
6074 verilog-declaration-re-1-macro)
6075 verilog-declaration-re-1-no-macro) lim t)
6076 (progn
6077 (goto-char (match-end 0))
6079 (setq ind (current-column))
6080 (goto-char pos)
6081 (setq val
6082 (+ baseind
6083 (eval (cdr (assoc 'declaration verilog-indent-alist)))))
6084 (indent-line-to val)
6085 (if (and verilog-indent-declaration-macros
6086 (looking-at verilog-declaration-re-2-macro))
6087 (let ((p (match-end 0)))
6088 (set-marker m1 p)
6089 (if (verilog-re-search-forward "[[#`]" p 'move)
6090 (progn
6091 (forward-char -1)
6092 (just-one-space)
6093 (goto-char (marker-position m1))
6094 (just-one-space)
6095 (indent-to ind))
6096 (if (/= (current-column) ind)
6097 (progn
6098 (just-one-space)
6099 (indent-to ind)))))
6100 (if (looking-at verilog-declaration-re-2-no-macro)
6101 (let ((p (match-end 0)))
6102 (set-marker m1 p)
6103 (if (verilog-re-search-forward "[[`#]" p 'move)
6104 (progn
6105 (forward-char -1)
6106 (just-one-space)
6107 (goto-char (marker-position m1))
6108 (just-one-space)
6109 (indent-to ind))
6110 (if (/= (current-column) ind)
6111 (progn
6112 (just-one-space)
6113 (indent-to ind))))))))))
6114 (goto-char pos)))
6116 (defun verilog-get-lineup-indent (b edpos)
6117 "Return the indent level that will line up several lines within the region.
6118 Region is defined by B and EDPOS."
6119 (save-excursion
6120 (let ((ind 0) e)
6121 (goto-char b)
6122 ;; Get rightmost position
6123 (while (progn (setq e (marker-position edpos))
6124 (< (point) e))
6125 (if (verilog-re-search-forward
6126 (or (and verilog-indent-declaration-macros
6127 verilog-declaration-re-1-macro)
6128 verilog-declaration-re-1-no-macro) e 'move)
6129 (progn
6130 (goto-char (match-end 0))
6131 (verilog-backward-syntactic-ws)
6132 (if (> (current-column) ind)
6133 (setq ind (current-column)))
6134 (goto-char (match-end 0)))))
6135 (if (> ind 0)
6136 (1+ ind)
6137 ;; No lineup-string found
6138 (goto-char b)
6139 (end-of-line)
6140 (verilog-backward-syntactic-ws)
6142 (1+ (current-column))))))
6144 (defun verilog-get-lineup-indent-2 (myre b edpos)
6145 "Return the indent level that will line up several lines within the region."
6146 (save-excursion
6147 (let ((ind 0) e)
6148 (goto-char b)
6149 ;; Get rightmost position
6150 (while (progn (setq e (marker-position edpos))
6151 (< (point) e))
6152 (if (and (verilog-re-search-forward myre e 'move)
6153 (not (verilog-parenthesis-depth))) ;; skip parenthesized exprs
6154 (progn
6155 (goto-char (match-beginning 2))
6156 (verilog-backward-syntactic-ws)
6157 (if (> (current-column) ind)
6158 (setq ind (current-column)))
6159 (goto-char (match-end 0)))
6160 ))
6161 (if (> ind 0)
6162 (1+ ind)
6163 ;; No lineup-string found
6164 (goto-char b)
6165 (end-of-line)
6167 (1+ (current-column))))))
6169 (defun verilog-comment-depth (type val)
6170 "A useful mode debugging aide. TYPE and VAL are comments for insertion."
6171 (save-excursion
6172 (let
6173 ((b (prog2
6174 (beginning-of-line)
6175 (point-marker)
6176 (end-of-line)))
6177 (e (point-marker)))
6179 (progn
6180 (replace-match " /* -# ## */")
6181 (end-of-line))
6182 (progn
6183 (end-of-line)
6184 (insert " /* ## ## */"))))
6185 (backward-char 6)
6186 (insert
6187 (format "%s %d" type val))))
6189 ;; \f
6190 ;;
6191 ;; Completion
6192 ;;
6193 (defvar verilog-str nil)
6194 (defvar verilog-all nil)
6195 (defvar verilog-pred nil)
6196 (defvar verilog-buffer-to-use nil)
6197 (defvar verilog-flag nil)
6198 (defvar verilog-toggle-completions nil
6199 "*True means \\<verilog-mode-map>\\[verilog-complete-word] should try all possible completions one by one.
6201 Normally, when there is more than one possible completion,
6202 it displays a list of all possible completions.")
6205 (defvar verilog-type-keywords
6206 '(
6207 "and" "buf" "bufif0" "bufif1" "cmos" "defparam" "inout" "input"
6208 "integer" "localparam" "logic" "mailbox" "nand" "nmos" "nor" "not" "notif0"
6209 "notif1" "or" "output" "parameter" "pmos" "pull0" "pull1" "pulldown" "pullup"
6210 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran" "rtranif0"
6211 "rtranif1" "semaphore" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1"
6212 "triand" "trior" "trireg" "wand" "wire" "wor" "xnor" "xor"
6213 )
6214 "*Keywords for types used when completing a word in a declaration or parmlist.
6215 \(integer, real, reg...)")
6217 (defvar verilog-cpp-keywords
6218 '("module" "macromodule" "primitive" "timescale" "define" "ifdef" "ifndef" "else"
6219 "endif")
6220 "*Keywords to complete when at first word of a line in declarative scope.
6221 \(initial, always, begin, assign...)
6222 The procedures and variables defined within the Verilog program
6223 will be completed at runtime and should not be added to this list.")
6225 (defvar verilog-defun-keywords
6226 (append
6227 '(
6228 "always" "always_comb" "always_ff" "always_latch" "assign"
6229 "begin" "end" "generate" "endgenerate" "module" "endmodule"
6230 "specify" "endspecify" "function" "endfunction" "initial" "final"
6231 "task" "endtask" "primitive" "endprimitive"
6232 )
6233 verilog-type-keywords)
6234 "*Keywords to complete when at first word of a line in declarative scope.
6235 \(initial, always, begin, assign...)
6236 The procedures and variables defined within the Verilog program
6237 will be completed at runtime and should not be added to this list.")
6239 (defvar verilog-block-keywords
6240 '(
6241 "begin" "break" "case" "continue" "else" "end" "endfunction"
6242 "endgenerate" "endinterface" "endpackage" "endspecify" "endtask"
6243 "for" "fork" "if" "join" "join_any" "join_none" "repeat" "return"
6244 "while")
6245 "*Keywords to complete when at first word of a line in behavioral scope.
6246 \(begin, if, then, else, for, fork...)
6247 The procedures and variables defined within the Verilog program
6248 will be completed at runtime and should not be added to this list.")
6250 (defvar verilog-tf-keywords
6251 '("begin" "break" "fork" "join" "join_any" "join_none" "case" "end" "endtask" "endfunction" "if" "else" "for" "while" "repeat")
6252 "*Keywords to complete when at first word of a line in a task or function.
6253 \(begin, if, then, else, for, fork.)
6254 The procedures and variables defined within the Verilog program
6255 will be completed at runtime and should not be added to this list.")
6257 (defvar verilog-case-keywords
6258 '("begin" "fork" "join" "join_any" "join_none" "case" "end" "endcase" "if" "else" "for" "repeat")
6259 "*Keywords to complete when at first word of a line in case scope.
6260 \(begin, if, then, else, for, fork...)
6261 The procedures and variables defined within the Verilog program
6262 will be completed at runtime and should not be added to this list.")
6264 (defvar verilog-separator-keywords
6265 '("else" "then" "begin")
6266 "*Keywords to complete when NOT standing at the first word of a statement.
6267 \(else, then, begin...)
6268 Variables and function names defined within the Verilog program
6269 will be completed at runtime and should not be added to this list.")
6271 (defvar verilog-gate-ios
6272 ;; All these have an implied {"input"...} at the end
6273 '(("and" "output")
6274 ("buf" "output")
6275 ("bufif0" "output")
6276 ("bufif1" "output")
6277 ("cmos" "output")
6278 ("nand" "output")
6279 ("nmos" "output")
6280 ("nor" "output")
6281 ("not" "output")
6282 ("notif0" "output")
6283 ("notif1" "output")
6284 ("or" "output")
6285 ("pmos" "output")
6286 ("pulldown" "output")
6287 ("pullup" "output")
6288 ("rcmos" "output")
6289 ("rnmos" "output")
6290 ("rpmos" "output")
6291 ("rtran" "inout" "inout")
6292 ("rtranif0" "inout" "inout")
6293 ("rtranif1" "inout" "inout")
6294 ("tran" "inout" "inout")
6295 ("tranif0" "inout" "inout")
6296 ("tranif1" "inout" "inout")
6297 ("xnor" "output")
6298 ("xor" "output"))
6299 "*Map of direction for each positional argument to each gate primitive.")
6301 (defvar verilog-gate-keywords (mapcar `car verilog-gate-ios)
6302 "*Keywords for gate primitives.")
6304 (defun verilog-string-diff (str1 str2)
6305 "Return index of first letter where STR1 and STR2 differs."
6306 (catch 'done
6307 (let ((diff 0))
6308 (while t
6309 (if (or (> (1+ diff) (length str1))
6310 (> (1+ diff) (length str2)))
6311 (throw 'done diff))
6312 (or (equal (aref str1 diff) (aref str2 diff))
6313 (throw 'done diff))
6314 (setq diff (1+ diff))))))
6316 ;; Calculate all possible completions for functions if argument is `function',
6317 ;; completions for procedures if argument is `procedure' or both functions and
6318 ;; procedures otherwise.
6320 (defun verilog-func-completion (type)
6321 "Build regular expression for module/task/function names.
6322 TYPE is 'module, 'tf for task or function, or t if unknown."
6323 (if (string= verilog-str "")
6324 (setq verilog-str "[a-zA-Z_]"))
6325 (let ((verilog-str (concat (cond
6330 match)
6332 (if (not (looking-at verilog-defun-re))
6333 (verilog-re-search-backward verilog-defun-re nil t))
6334 (forward-char 1)
6336 ;; Search through all reachable functions
6337 (goto-char (point-min))
6338 (while (verilog-re-search-forward verilog-str (point-max) t)
6339 (progn (setq match (buffer-substring (match-beginning 2)
6340 (match-end 2)))
6341 (if (or (null verilog-pred)
6342 (funcall verilog-pred match))
6343 (setq verilog-all (cons match verilog-all)))))
6344 (if (match-beginning 0)
6345 (goto-char (match-beginning 0)))))
6347 (defun verilog-get-completion-decl (end)
6348 "Macro for searching through current declaration (var, type or const)
6349 for matches of `str' and adding the occurrence tp `all' through point END."
6350 (let ((re (or (and verilog-indent-declaration-macros
6351 verilog-declaration-re-2-macro)
6352 verilog-declaration-re-2-no-macro))
6353 decl-end match)
6354 ;; Traverse lines
6355 (while (and (< (point) end)
6356 (verilog-re-search-forward re end t))
6357 ;; Traverse current line
6358 (setq decl-end (save-excursion (verilog-declaration-end)))
6359 (while (and (verilog-re-search-forward verilog-symbol-re decl-end t)
6360 (not (match-end 1)))
6361 (setq match (buffer-substring (match-beginning 0) (match-end 0)))
6363 (if (or (null verilog-pred)
6364 (funcall verilog-pred match))
6365 (setq verilog-all (cons match verilog-all)))))
6366 (forward-line 1)))
6367 verilog-all)
6369 (defun verilog-type-completion ()
6370 "Calculate all possible completions for types."
6371 (let ((start (point))
6372 goon)
6373 ;; Search for all reachable type declarations
6374 (while (or (verilog-beg-of-defun)
6375 (setq goon (not goon)))
6376 (save-excursion
6377 (if (and (< start (prog1 (save-excursion (verilog-end-of-defun)
6378 (point))
6379 (forward-char 1)))
6380 (verilog-re-search-forward
6382 start t)
6383 (not (match-end 1)))
6384 ;; Check current type declaration
6385 (verilog-get-completion-decl start))))))
6387 (defun verilog-var-completion ()
6388 "Calculate all possible completions for variables (or constants)."
6389 (let ((start (point)))
6390 ;; Search for all reachable var declarations
6391 (verilog-beg-of-defun)
6392 (save-excursion
6393 ;; Check var declarations
6394 (verilog-get-completion-decl start))))
6396 (defun verilog-keyword-completion (keyword-list)
6397 "Give list of all possible completions of keywords in KEYWORD-LIST."
6398 (mapcar '(lambda (s)
6400 (if (or (null verilog-pred)
6401 (funcall verilog-pred s))
6402 (setq verilog-all (cons s verilog-all)))))
6403 keyword-list))
6406 (defun verilog-completion (verilog-str verilog-pred verilog-flag)
6407 "Function passed to `completing-read', `try-completion' or `all-completions'.
6408 Called to get completion on VERILOG-STR. If VERILOG-PRED is non-nil, it
6409 must be a function to be called for every match to check if this should
6410 really be a match. If VERILOG-FLAG is t, the function returns a list of
6411 all possible completions. If VERILOG-FLAG is nil it returns a string,
6412 the longest possible completion, or t if VERILOG-STR is an exact match.
6413 If VERILOG-FLAG is 'lambda, the function returns t if VERILOG-STR is an
6414 exact match, nil otherwise."
6415 (save-excursion
6416 (let ((verilog-all nil))
6417 ;; Set buffer to use for searching labels. This should be set
6418 ;; within functions which use verilog-completions
6419 (set-buffer verilog-buffer-to-use)
6421 ;; Determine what should be completed
6422 (let ((state (car (verilog-calculate-indent))))
6423 (cond ((eq state 'defun)
6424 (save-excursion (verilog-var-completion))
6425 (verilog-func-completion 'module)
6426 (verilog-keyword-completion verilog-defun-keywords))
6428 ((eq state 'behavioral)
6429 (save-excursion (verilog-var-completion))
6430 (verilog-func-completion 'module)
6431 (verilog-keyword-completion verilog-defun-keywords))
6433 ((eq state 'block)
6434 (save-excursion (verilog-var-completion))
6435 (verilog-func-completion 'tf)
6436 (verilog-keyword-completion verilog-block-keywords))
6438 ((eq state 'case)
6439 (save-excursion (verilog-var-completion))
6440 (verilog-func-completion 'tf)
6441 (verilog-keyword-completion verilog-case-keywords))
6443 ((eq state 'tf)
6444 (save-excursion (verilog-var-completion))
6445 (verilog-func-completion 'tf)
6446 (verilog-keyword-completion verilog-tf-keywords))
6448 ((eq state 'cpp)
6449 (save-excursion (verilog-var-completion))
6450 (verilog-keyword-completion verilog-cpp-keywords))
6452 ((eq state 'cparenexp)
6453 (save-excursion (verilog-var-completion)))
6455 (t;--Anywhere else
6456 (save-excursion (verilog-var-completion))
6457 (verilog-func-completion 'both)
6458 (verilog-keyword-completion verilog-separator-keywords))))
6460 ;; Now we have built a list of all matches. Give response to caller
6461 (verilog-completion-response))))
6463 (defun verilog-completion-response ()
6464 (cond ((or (equal verilog-flag 'lambda) (null verilog-flag))
6465 ;; This was not called by all-completions
6466 (if (null verilog-all)
6467 ;; Return nil if there was no matching label
6468 nil
6469 ;; Get longest string common in the labels
6470 (let* ((elm (cdr verilog-all))
6471 (match (car verilog-all))
6472 (min (length match))
6473 tmp)
6474 (if (string= match verilog-str)
6475 ;; Return t if first match was an exact match
6476 (setq match t)
6477 (while (not (null elm))
6478 ;; Find longest common string
6479 (if (< (setq tmp (verilog-string-diff match (car elm))) min)
6480 (progn
6481 (setq min tmp)
6482 (setq match (substring match 0 min))))
6483 ;; Terminate with match=t if this is an exact match
6484 (if (string= (car elm) verilog-str)
6485 (progn
6486 (setq match t)
6487 (setq elm nil))
6488 (setq elm (cdr elm)))))
6489 ;; If this is a test just for exact match, return nil ot t
6490 (if (and (equal verilog-flag 'lambda) (not (equal match 't)))
6491 nil
6492 match))))
6493 ;; If flag is t, this was called by all-completions. Return
6494 ;; list of all possible completions
6495 (verilog-flag
6496 verilog-all)))
6498 (defvar verilog-last-word-numb 0)
6499 (defvar verilog-last-word-shown nil)
6500 (defvar verilog-last-completions nil)
6502 (defun verilog-complete-word ()
6503 "Complete word at current point.
6504 \(See also `verilog-toggle-completions', `verilog-type-keywords',
6505 and `verilog-separator-keywords'.)"
6506 (interactive)
6507 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
6508 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
6509 (verilog-str (buffer-substring b e))
6510 ;; The following variable is used in verilog-completion
6511 (verilog-buffer-to-use (current-buffer))
6512 (allcomp (if (and verilog-toggle-completions
6513 (string= verilog-last-word-shown verilog-str))
6514 verilog-last-completions
6515 (all-completions verilog-str 'verilog-completion)))
6516 (match (if verilog-toggle-completions
6517 "" (try-completion
6518 verilog-str (mapcar '(lambda (elm)
6519 (cons elm 0)) allcomp)))))
6520 ;; Delete old string
6521 (delete-region b e)
6523 ;; Toggle-completions inserts whole labels
6524 (if verilog-toggle-completions
6525 (progn
6526 ;; Update entry number in list
6527 (setq verilog-last-completions allcomp
6528 verilog-last-word-numb
6529 (if (>= verilog-last-word-numb (1- (length allcomp)))
6530 0
6531 (1+ verilog-last-word-numb)))
6532 (setq verilog-last-word-shown (elt allcomp verilog-last-word-numb))
6533 ;; Display next match or same string if no match was found
6534 (if (not (null allcomp))
6535 (insert "" verilog-last-word-shown)
6536 (insert "" verilog-str)
6537 (message "(No match)")))
6538 ;; The other form of completion does not necessarily do that.
6540 ;; Insert match if found, or the original string if no match
6541 (if (or (null match) (equal match 't))
6542 (progn (insert "" verilog-str)
6543 (message "(No match)"))
6544 (insert "" match))
6545 ;; Give message about current status of completion
6546 (cond ((equal match 't)
6547 (if (not (null (cdr allcomp)))
6548 (message "(Complete but not unique)")
6549 (message "(Sole completion)")))
6550 ;; Display buffer if the current completion didn't help
6551 ;; on completing the label.
6552 ((and (not (null (cdr allcomp))) (= (length verilog-str)
6553 (length match)))
6554 (with-output-to-temp-buffer "*Completions*"
6555 (display-completion-list allcomp))
6556 ;; Wait for a key press. Then delete *Completion* window
6557 (momentary-string-display "" (point))
6558 (delete-window (get-buffer-window (get-buffer "*Completions*")))
6559 )))))
6561 (defun verilog-show-completions ()
6562 "Show all possible completions at current point."
6563 (interactive)
6564 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
6565 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
6566 (verilog-str (buffer-substring b e))
6567 ;; The following variable is used in verilog-completion
6568 (verilog-buffer-to-use (current-buffer))
6569 (allcomp (if (and verilog-toggle-completions
6570 (string= verilog-last-word-shown verilog-str))
6571 verilog-last-completions
6572 (all-completions verilog-str 'verilog-completion))))
6573 ;; Show possible completions in a temporary buffer.
6574 (with-output-to-temp-buffer "*Completions*"
6575 (display-completion-list allcomp))
6576 ;; Wait for a key press. Then delete *Completion* window
6577 (momentary-string-display "" (point))
6578 (delete-window (get-buffer-window (get-buffer "*Completions*")))))
6581 (defun verilog-get-default-symbol ()
6582 "Return symbol around current point as a string."
6583 (save-excursion
6584 (buffer-substring (progn
6586 (skip-chars-backward "a-zA-Z0-9_")
6587 (point))
6588 (progn
6589 (skip-chars-forward "a-zA-Z0-9_")
6590 (point)))))
6592 (defun verilog-build-defun-re (str &optional arg)
6593 "Return function/task/module starting with STR as regular expression.
6594 With optional second ARG non-nil, STR is the complete name of the instruction."
6595 (if arg
6599 (defun verilog-comp-defun (verilog-str verilog-pred verilog-flag)
6600 "Function passed to `completing-read', `try-completion' or `all-completions'.
6601 Returns a completion on any function name based on VERILOG-STR prefix. If
6602 VERILOG-PRED is non-nil, it must be a function to be called for every match
6603 to check if this should really be a match. If VERILOG-FLAG is t, the
6604 function returns a list of all possible completions. If it is nil it
6605 returns a string, the longest possible completion, or t if VERILOG-STR is
6606 an exact match. If VERILOG-FLAG is 'lambda, the function returns t if
6607 VERILOG-STR is an exact match, nil otherwise."
6608 (save-excursion
6609 (let ((verilog-all nil)
6610 match)
6612 ;; Set buffer to use for searching labels. This should be set
6613 ;; within functions which use verilog-completions
6614 (set-buffer verilog-buffer-to-use)
6616 (let ((verilog-str verilog-str))
6617 ;; Build regular expression for functions
6618 (if (string= verilog-str "")
6619 (setq verilog-str (verilog-build-defun-re "[a-zA-Z_]"))
6620 (setq verilog-str (verilog-build-defun-re verilog-str)))
6621 (goto-char (point-min))
6623 ;; Build a list of all possible completions
6624 (while (verilog-re-search-forward verilog-str nil t)
6625 (setq match (buffer-substring (match-beginning 2) (match-end 2)))
6626 (if (or (null verilog-pred)
6627 (funcall verilog-pred match))
6628 (setq verilog-all (cons match verilog-all)))))
6630 ;; Now we have built a list of all matches. Give response to caller
6631 (verilog-completion-response))))
6633 (defun verilog-goto-defun ()
6634 "Move to specified Verilog module/interface/task/function.
6635 The default is a name found in the buffer around point.
6636 If search fails, other files are checked based on
6637 `verilog-library-flags'."
6638 (interactive)
6639 (let* ((default (verilog-get-default-symbol))
6640 ;; The following variable is used in verilog-comp-function
6641 (verilog-buffer-to-use (current-buffer))
6642 (label (if (not (string= default ""))
6643 ;; Do completion with default
6644 (completing-read (concat "Goto-Label: (default "
6645 default ") ")
6646 'verilog-comp-defun nil nil "")
6647 ;; There is no default value. Complete without it
6648 (completing-read "Goto-Label: "
6649 'verilog-comp-defun nil nil "")))
6650 pt)
6651 ;; Make sure library paths are correct, in case need to resolve module
6652 (verilog-auto-reeval-locals)
6653 (verilog-getopt-flags)
6654 ;; If there was no response on prompt, use default value
6655 (if (string= label "")
6656 (setq label default))
6657 ;; Goto right place in buffer if label is not an empty string
6658 (or (string= label "")
6659 (progn
6660 (save-excursion
6661 (goto-char (point-min))
6662 (setq pt
6663 (re-search-forward (verilog-build-defun-re label t) nil t)))
6664 (when pt
6665 (goto-char pt)
6666 (beginning-of-line))
6667 pt)
6668 (verilog-goto-defun-file label))))
6670 ;; Eliminate compile warning
6671 (defvar occur-pos-list)
6673 (defun verilog-showscopes ()
6674 "List all scopes in this module."
6675 (interactive)
6676 (let ((buffer (current-buffer))
6677 (linenum 1)
6678 (nlines 0)
6679 (first 1)
6680 (prevpos (point-min))
6681 (final-context-start (make-marker))
6683 (with-output-to-temp-buffer "*Occur*"
6684 (save-excursion
6685 (message (format "Searching for %s ..." regexp))
6686 ;; Find next match, but give up if prev match was at end of buffer.
6687 (while (and (not (= prevpos (point-max)))
6688 (verilog-re-search-forward regexp nil t))
6689 (goto-char (match-beginning 0))
6690 (beginning-of-line)
6691 (save-match-data
6692 (setq linenum (+ linenum (count-lines prevpos (point)))))
6693 (setq prevpos (point))
6694 (goto-char (match-end 0))
6695 (let* ((start (save-excursion
6696 (goto-char (match-beginning 0))
6697 (forward-line (if (< nlines 0) nlines (- nlines)))
6698 (point)))
6699 (end (save-excursion
6700 (goto-char (match-end 0))
6701 (if (> nlines 0)
6702 (forward-line (1+ nlines))
6703 (forward-line 1))
6704 (point)))
6705 (tag (format "%3d" linenum))
6706 (empty (make-string (length tag) ?\ ))
6707 tem)
6708 (save-excursion
6709 (setq tem (make-marker))
6710 (set-marker tem (point))
6711 (set-buffer standard-output)
6712 (setq occur-pos-list (cons tem occur-pos-list))
6713 (or first (zerop nlines)
6715 (setq first nil)
6716 (insert-buffer-substring buffer start end)
6717 (backward-char (- end start))
6718 (setq tem (if (< nlines 0) (- nlines) nlines))
6719 (while (> tem 0)
6720 (insert empty ?:)
6721 (forward-line 1)
6722 (setq tem (1- tem)))
6723 (let ((this-linenum linenum))
6724 (set-marker final-context-start
6725 (+ (point) (- (match-end 0) (match-beginning 0))))
6726 (while (< (point) final-context-start)
6727 (if (null tag)
6728 (setq tag (format "%3d" this-linenum)))
6729 (insert tag ?:)))))))
6730 (set-buffer-modified-p nil))))
6733 ;; Highlight helper functions
6735 (defun verilog-within-translate-off ()
6736 "Return point if within translate-off region, else nil."
6737 (and (save-excursion
6738 (re-search-backward
6740 nil t))
6741 (equal "off" (match-string 2))
6742 (point)))
6744 (defun verilog-start-translate-off (limit)
6745 "Return point before translate-off directive if before LIMIT, else nil."
6746 (when (re-search-forward
6748 limit t)
6749 (match-beginning 0)))
6751 (defun verilog-back-to-start-translate-off (limit)
6752 "Return point before translate-off directive if before LIMIT, else nil."
6753 (when (re-search-backward
6755 limit t)
6756 (match-beginning 0)))
6758 (defun verilog-end-translate-off (limit)
6759 "Return point after translate-on directive if before LIMIT, else nil."
6761 (re-search-forward (concat
6764 (defun verilog-match-translate-off (limit)
6765 "Match a translate-off block, setting `match-data' and returning t, else nil.
6766 Bound search by LIMIT."
6767 (when (< (point) limit)
6768 (let ((start (or (verilog-within-translate-off)
6769 (verilog-start-translate-off limit)))
6770 (case-fold-search t))
6771 (when start
6772 (let ((end (or (verilog-end-translate-off limit) limit)))
6773 (set-match-data (list start end))
6774 (goto-char end))))))
6776 (defun verilog-font-lock-match-item (limit)
6777 "Match, and move over, any declaration item after point.
6778 Bound search by LIMIT. Adapted from
6779 `font-lock-match-c-style-declaration-item-and-skip-to-next'."
6780 (condition-case nil
6781 (save-restriction
6782 (narrow-to-region (point-min) limit)
6783 ;; match item
6785 (save-match-data
6786 (goto-char (match-end 1))
6787 ;; move to next item
6789 (goto-char (match-end 1))
6790 (end-of-line) t))))
6791 (error nil)))
6794 ;; Added by Subbu Meiyappan for Header
6796 (defun verilog-header ()
6797 "Insert a standard Verilog file header.
6798 See also `verilog-sk-header' for an alternative format."
6799 (interactive)
6800 (let ((start (point)))
6801 (insert "\
6802 //-----------------------------------------------------------------------------
6803 // Title : <title>
6804 // Project : <project>
6805 //-----------------------------------------------------------------------------
6806 // File : <filename>
6807 // Author : <author>
6808 // Created : <credate>
6809 // Last modified : <moddate>
6810 //-----------------------------------------------------------------------------
6811 // Description :
6812 // <description>
6813 //-----------------------------------------------------------------------------
6814 // Copyright (c) <copydate> by <company> This model is the confidential and
6815 // proprietary property of <company> and the possession or use of this
6816 // file requires a written license from <company>.
6817 //------------------------------------------------------------------------------
6818 // Modification history :
6819 // <modhist>
6820 //-----------------------------------------------------------------------------
6822 ")
6823 (goto-char start)
6824 (search-forward "<filename>")
6825 (replace-match (buffer-name) t t)
6826 (search-forward "<author>") (replace-match "" t t)
6827 (insert (user-full-name))
6828 (insert " <" (user-login-name) "@" (system-name) ">")
6829 (search-forward "<credate>") (replace-match "" t t)
6830 (verilog-insert-date)
6831 (search-forward "<moddate>") (replace-match "" t t)
6832 (verilog-insert-date)
6833 (search-forward "<copydate>") (replace-match "" t t)
6834 (verilog-insert-year)
6835 (search-forward "<modhist>") (replace-match "" t t)
6836 (verilog-insert-date)
6837 (insert " : created")
6838 (goto-char start)
6839 (let (string)
6840 (setq string (read-string "title: "))
6841 (search-forward "<title>")
6842 (replace-match string t t)
6843 (setq string (read-string "project: " verilog-project))
6844 (setq verilog-project string)
6845 (search-forward "<project>")
6846 (replace-match string t t)
6847 (setq string (read-string "Company: " verilog-company))
6848 (setq verilog-company string)
6849 (search-forward "<company>")
6850 (replace-match string t t)
6851 (search-forward "<company>")
6852 (replace-match string t t)
6853 (search-forward "<company>")
6854 (replace-match string t t)
6855 (search-backward "<description>")
6856 (replace-match "" t t))))
6858 ;; verilog-header Uses the verilog-insert-date function
6860 (defun verilog-insert-date ()
6861 "Insert date from the system."
6862 (interactive)
6863 (if verilog-date-scientific-format
6864 (insert (format-time-string "%Y/%m/%d"))
6865 (insert (format-time-string "%d.%m.%Y"))))
6867 (defun verilog-insert-year ()
6868 "Insert year from the system."
6869 (interactive)
6870 (insert (format-time-string "%Y")))
6872 \f
6873 ;;
6874 ;; Signal list parsing
6875 ;;
6877 ;; Elements of a signal list
6878 (defsubst verilog-sig-new (name bits comment mem enum signed type multidim modport)
6879 (list name bits comment mem enum signed type multidim modport))
6880 (defsubst verilog-sig-name (sig)
6881 (car sig))
6882 (defsubst verilog-sig-bits (sig)
6883 (nth 1 sig))
6884 (defsubst verilog-sig-comment (sig)
6885 (nth 2 sig))
6886 (defsubst verilog-sig-memory (sig)
6887 (nth 3 sig))
6888 (defsubst verilog-sig-enum (sig)
6889 (nth 4 sig))
6890 (defsubst verilog-sig-signed (sig)
6891 (nth 5 sig))
6892 (defsubst verilog-sig-type (sig)
6893 (nth 6 sig))
6894 (defsubst verilog-sig-multidim (sig)
6895 (nth 7 sig))
6896 (defsubst verilog-sig-multidim-string (sig)
6897 (if (verilog-sig-multidim sig)
6898 (let ((str "") (args (verilog-sig-multidim sig)))
6899 (while args
6900 (setq str (concat str (car args)))
6901 (setq args (cdr args)))
6902 str)))
6903 (defsubst verilog-sig-modport (sig)
6904 (nth 8 sig))
6905 (defsubst verilog-sig-width (sig)
6906 (verilog-make-width-expression (verilog-sig-bits sig)))
6908 (defsubst verilog-alw-new (outputs temps inputs delayed)
6909 (list outputs temps inputs delayed))
6910 (defsubst verilog-alw-get-outputs (sigs)
6911 (nth 0 sigs))
6912 (defsubst verilog-alw-get-temps (sigs)
6913 (nth 1 sigs))
6914 (defsubst verilog-alw-get-inputs (sigs)
6915 (nth 2 sigs))
6916 (defsubst verilog-alw-get-uses-delayed (sigs)
6917 (nth 3 sigs))
6919 (defsubst verilog-modi-new (name fob pt type)
6920 (vector name fob pt type))
6921 (defsubst verilog-modi-name (modi)
6922 (aref modi 0))
6923 (defsubst verilog-modi-file-or-buffer (modi)
6924 (aref modi 1))
6925 (defsubst verilog-modi-get-point (modi)
6926 (aref modi 2))
6927 (defsubst verilog-modi-get-type (modi) ;; "module" or "interface"
6928 (aref modi 3))
6929 (defsubst verilog-modi-get-decls (modi)
6930 (verilog-modi-cache-results modi 'verilog-read-decls))
6931 (defsubst verilog-modi-get-sub-decls (modi)
6932 (verilog-modi-cache-results modi 'verilog-read-sub-decls))
6934 ;; Signal reading for given module
6935 ;; Note these all take modi's - as returned from verilog-modi-current
6936 (defsubst verilog-decls-new (out inout in wires regs assigns consts gparams interfaces)
6937 (vector out inout in wires regs assigns consts gparams interfaces))
6938 (defsubst verilog-decls-get-outputs (decls)
6939 (aref decls 0))
6940 (defsubst verilog-decls-get-inouts (decls)
6941 (aref decls 1))
6942 (defsubst verilog-decls-get-inputs (decls)
6943 (aref decls 2))
6944 (defsubst verilog-decls-get-wires (decls)
6945 (aref decls 3))
6946 (defsubst verilog-decls-get-regs (decls)
6947 (aref decls 4))
6948 (defsubst verilog-decls-get-assigns (decls)
6949 (aref decls 5))
6950 (defsubst verilog-decls-get-consts (decls)
6951 (aref decls 6))
6952 (defsubst verilog-decls-get-gparams (decls)
6953 (aref decls 7))
6954 (defsubst verilog-decls-get-interfaces (decls)
6955 (aref decls 8))
6957 (defsubst verilog-subdecls-new (out inout in intf intfd)
6958 (vector out inout in intf intfd))
6959 (defsubst verilog-subdecls-get-outputs (subdecls)
6960 (aref subdecls 0))
6961 (defsubst verilog-subdecls-get-inouts (subdecls)
6962 (aref subdecls 1))
6963 (defsubst verilog-subdecls-get-inputs (subdecls)
6964 (aref subdecls 2))
6965 (defsubst verilog-subdecls-get-interfaces (subdecls)
6966 (aref subdecls 3))
6967 (defsubst verilog-subdecls-get-interfaced (subdecls)
6968 (aref subdecls 4))
6970 (defun verilog-signals-not-in (in-list not-list)
6971 "Return list of signals in IN-LIST that aren't also in NOT-LIST.
6972 Also remove any duplicates in IN-LIST.
6973 Signals must be in standard (base vector) form."
6974 ;; This function is hot, so implemented as O(1)
6975 (cond ((eval-when-compile (fboundp 'make-hash-table))
6976 (let ((ht (make-hash-table :test 'equal :rehash-size 4.0))
6977 out-list)
6978 (while not-list
6979 (puthash (car (car not-list)) t ht)
6980 (setq not-list (cdr not-list)))
6981 (while in-list
6982 (when (not (gethash (car (car in-list)) ht))
6983 (setq out-list (cons (car in-list) out-list))
6984 (puthash (car (car in-list)) t ht))
6985 (setq in-list (cdr in-list)))
6986 (nreverse out-list)))
6987 ;; Slower Fallback if no hash tables (pre Emacs 21.1/XEmacs 21.4)
6988 (t
6989 (let (out-list)
6990 (while in-list
6991 (if (not (or (assoc (car (car in-list)) not-list)
6992 (assoc (car (car in-list)) out-list)))
6993 (setq out-list (cons (car in-list) out-list)))
6994 (setq in-list (cdr in-list)))
6995 (nreverse out-list)))))
6996 ;;(verilog-signals-not-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("EXT" "")))
6998 (defun verilog-signals-memory (in-list)
6999 "Return list of signals in IN-LIST that are memoried (multidimensional)."
7000 (let (out-list)
7001 (while in-list
7002 (if (nth 3 (car in-list))
7003 (setq out-list (cons (car in-list) out-list)))
7004 (setq in-list (cdr in-list)))
7005 out-list))
7006 ;;(verilog-signals-memory '(("A" nil nil "[3:0]")) '(("B" nil nil nil)))
7008 (defun verilog-signals-sort-compare (a b)
7009 "Compare signal A and B for sorting."
7010 (string< (car a) (car b)))
7012 (defun verilog-signals-not-params (in-list)
7013 "Return list of signals in IN-LIST that aren't parameters or numeric constants."
7014 (let (out-list)
7015 (while in-list
7016 (unless (boundp (intern (concat "vh-" (car (car in-list)))))
7017 (setq out-list (cons (car in-list) out-list)))
7018 (setq in-list (cdr in-list)))
7019 (nreverse out-list)))
7021 (defun verilog-signals-combine-bus (in-list)
7022 "Return a list of signals in IN-LIST, with busses combined.
7023 Duplicate signals are also removed. For example A[2] and A[1] become A[2:1]."
7024 (let (combo buswarn
7025 out-list
7026 sig highbit lowbit ; Temp information about current signal
7027 sv-name sv-highbit sv-lowbit ; Details about signal we are forming
7028 sv-comment sv-memory sv-enum sv-signed sv-type sv-multidim sv-busstring
7029 sv-modport
7030 bus)
7031 ;; Shove signals so duplicated signals will be adjacent
7032 (setq in-list (sort in-list `verilog-signals-sort-compare))
7033 (while in-list
7034 (setq sig (car in-list))
7035 ;; No current signal; form from existing details
7036 (unless sv-name
7037 (setq sv-name (verilog-sig-name sig)
7038 sv-highbit nil
7039 sv-busstring nil
7040 sv-comment (verilog-sig-comment sig)
7041 sv-memory (verilog-sig-memory sig)
7042 sv-enum (verilog-sig-enum sig)
7043 sv-signed (verilog-sig-signed sig)
7044 sv-type (verilog-sig-type sig)
7045 sv-multidim (verilog-sig-multidim sig)
7046 sv-modport (verilog-sig-modport sig)
7047 combo ""
7048 buswarn ""))
7049 ;; Extract bus details
7050 (setq bus (verilog-sig-bits sig))
7051 (cond ((and bus
7053 (setq highbit (string-to-number (match-string 1 bus))
7054 lowbit (string-to-number
7055 (match-string 2 bus))))
7057 (setq highbit (string-to-number (match-string 1 bus))
7058 lowbit highbit))))
7059 ;; Combine bits in bus
7060 (if sv-highbit
7061 (setq sv-highbit (max highbit sv-highbit)
7062 sv-lowbit (min lowbit sv-lowbit))
7063 (setq sv-highbit highbit
7064 sv-lowbit lowbit)))
7065 (bus
7066 ;; String, probably something like `preproc:0
7067 (setq sv-busstring bus)))
7068 ;; Peek ahead to next signal
7069 (setq in-list (cdr in-list))
7070 (setq sig (car in-list))
7071 (cond ((and sig (equal sv-name (verilog-sig-name sig)))
7072 ;; Combine with this signal
7073 (when (and sv-busstring
7074 (not (equal sv-busstring (verilog-sig-bits sig))))
7075 (when nil ;; Debugging
7076 (message (concat "Warning, can't merge into single bus "
7077 sv-name bus
7078 ", the AUTOs may be wrong")))
7079 (setq buswarn ", Couldn't Merge"))
7080 (if (verilog-sig-comment sig) (setq combo ", ..."))
7081 (setq sv-memory (or sv-memory (verilog-sig-memory sig))
7082 sv-enum (or sv-enum (verilog-sig-enum sig))
7083 sv-signed (or sv-signed (verilog-sig-signed sig))
7084 sv-type (or sv-type (verilog-sig-type sig))
7085 sv-multidim (or sv-multidim (verilog-sig-multidim sig))
7086 sv-modport (or sv-modport (verilog-sig-modport sig))))
7087 ;; Doesn't match next signal, add to queue, zero in prep for next
7088 ;; Note sig may also be nil for the last signal in the list
7089 (t
7090 (setq out-list
7091 (cons (verilog-sig-new
7092 sv-name
7093 (or sv-busstring
7094 (if sv-highbit
7095 (concat "[" (int-to-string sv-highbit) ":"
7096 (int-to-string sv-lowbit) "]")))
7097 (concat sv-comment combo buswarn)
7098 sv-memory sv-enum sv-signed sv-type sv-multidim sv-modport)
7099 out-list)
7100 sv-name nil))))
7101 ;;
7102 out-list))
7104 (defun verilog-sig-tieoff (sig &optional no-width)
7105 "Return tieoff expression for given SIG, with appropriate width.
7106 Ignore width if optional NO-WIDTH is set."
7107 (let* ((width (if no-width nil (verilog-sig-width sig))))
7108 (concat
7109 (if (and verilog-active-low-regexp
7110 (string-match verilog-active-low-regexp (verilog-sig-name sig)))
7111 "~" "")
7112 (cond ((not width)
7113 "0")
7114 ((string-match "^[0-9]+$" width)
7115 (concat width (if (verilog-sig-signed sig) "'sh0" "'h0")))
7116 (t
7117 (concat "{" width "{1'b0}}"))))))
7119 ;;
7120 ;; Port/Wire/Etc Reading
7121 ;;
7123 (defun verilog-read-inst-backward-name ()
7124 "Internal. Move point back to beginning of inst-name."
7125 (verilog-backward-open-paren)
7126 (let (done)
7127 (while (not done)
7128 (verilog-re-search-backward-quick "\\()\\|\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil) ; ] isn't word boundary
7129 (cond ((looking-at ")")
7130 (verilog-backward-open-paren))
7131 (t (setq done t)))))
7133 (verilog-backward-open-bracket)
7135 (skip-chars-backward "a-zA-Z0-9`_$"))
7137 (defun verilog-read-inst-module-matcher ()
7138 "Set match data 0 with module_name when point is inside instantiation."
7139 (verilog-read-inst-backward-name)
7140 ;; Skip over instantiation name
7141 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|)\\)" nil nil) ; ) isn't word boundary
7142 ;; Check for parameterized instantiations
7143 (when (looking-at ")")
7144 (verilog-backward-open-paren)
7146 (skip-chars-backward "a-zA-Z0-9'_$")
7147 (looking-at "[a-zA-Z0-9`_\$]+")
7148 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
7149 (buffer-substring-no-properties (match-beginning 0) (match-end 0))
7150 ;; Caller assumes match-beginning/match-end is still set
7151 )
7153 (defun verilog-read-inst-module ()
7154 "Return module_name when point is inside instantiation."
7155 (save-excursion
7156 (verilog-read-inst-module-matcher)))
7158 (defun verilog-read-inst-name ()
7159 "Return instance_name when point is inside instantiation."
7160 (save-excursion
7161 (verilog-read-inst-backward-name)
7162 (looking-at "[a-zA-Z0-9`_\$]+")
7163 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
7164 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
7166 (defun verilog-read-module-name ()
7167 "Return module name when after its ( or ;."
7168 (save-excursion
7169 (re-search-backward "[(;]")
7171 (skip-chars-backward "a-zA-Z0-9`_$")
7172 (looking-at "[a-zA-Z0-9`_\$]+")
7173 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
7174 (verilog-symbol-detick
7175 (buffer-substring-no-properties (match-beginning 0) (match-end 0)) t)))
7177 (defun verilog-read-inst-param-value ()
7178 "Return list of parameters and values when point is inside instantiation."
7179 (save-excursion
7180 (verilog-read-inst-backward-name)
7181 ;; Skip over instantiation name
7182 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|)\\)" nil nil) ; ) isn't word boundary
7183 ;; If there are parameterized instantiations
7184 (when (looking-at ")")
7185 (let ((end-pt (point))
7186 params
7187 param-name paren-beg-pt param-value)
7188 (verilog-backward-open-paren)
7191 (skip-chars-backward "a-zA-Z0-9'_$")
7192 (looking-at "[a-zA-Z0-9`_\$]+")
7193 (setq param-name (buffer-substring-no-properties
7194 (match-beginning 0) (match-end 0)))
7195 (verilog-re-search-forward-quick "(" nil nil)
7196 (setq paren-beg-pt (point))
7197 (verilog-forward-close-paren)
7198 (setq param-value (verilog-string-remove-spaces
7199 (buffer-substring-no-properties
7200 paren-beg-pt (1- (point)))))
7201 (setq params (cons (list param-name param-value) params)))
7202 params))))
7204 (defun verilog-read-auto-params (num-param &optional max-param)
7205 "Return parameter list inside auto.
7206 Optional NUM-PARAM and MAX-PARAM check for a specific number of parameters."
7207 (let ((olist))
7208 (save-excursion
7209 ;; /*AUTOPUNT("parameter", "parameter")*/
7210 (search-backward "(")
7212 (setq olist (cons (match-string 1) olist))
7213 (goto-char (match-end 0))))
7214 (or (eq nil num-param)
7215 (<= num-param (length olist))
7216 (error "%s: Expected %d parameters" (verilog-point-text) num-param))
7217 (if (eq max-param nil) (setq max-param num-param))
7218 (or (eq nil max-param)
7219 (>= max-param (length olist))
7220 (error "%s: Expected <= %d parameters" (verilog-point-text) max-param))
7221 (nreverse olist)))
7223 (defun verilog-read-decls ()
7224 "Compute signal declaration information for the current module at point.
7225 Return a array of [outputs inouts inputs wire reg assign const]."
7226 (let ((end-mod-point (or (verilog-get-end-of-defun t) (point-max)))
7227 (functask 0) (paren 0) (sig-paren 0) (v2kargs-ok t)
7228 in-modport
7229 sigs-in sigs-out sigs-inout sigs-wire sigs-reg sigs-assign sigs-const
7230 sigs-gparam sigs-intf
7231 vec expect-signal keywd newsig rvalue enum io signed typedefed multidim
7232 modport)
7233 (save-excursion
7234 (verilog-beg-of-defun)
7235 (setq sigs-const (verilog-read-auto-constants (point) end-mod-point))
7236 (while (< (point) end-mod-point)
7237 ;;(if dbg (setq dbg (concat dbg (format "Pt %s Vec %s C%c Kwd'%s'\n" (point) vec (following-char) keywd))))
7238 (cond
7239 ((looking-at "//")
7241 (setq enum (match-string 1)))
7244 (forward-char 2)
7246 (setq enum (match-string 1)))
7247 (or (search-forward "*/")
7248 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
7250 (forward-char 2)
7252 (search-forward "*)")
7253 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
7255 (or (re-search-forward "[^\\]\"" nil t) ;; don't forward-char first, since we look for a non backslash first
7256 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
7257 ((eq ?\; (following-char))
7258 (setq vec nil io nil expect-signal nil newsig nil paren 0 rvalue nil
7259 v2kargs-ok nil in-modport nil)
7260 (forward-char 1))
7261 ((eq ?= (following-char))
7262 (setq rvalue t newsig nil)
7263 (forward-char 1))
7264 ((and (eq ?, (following-char))
7265 (eq paren sig-paren))
7266 (setq rvalue nil)
7267 (forward-char 1))
7268 ;; ,'s can occur inside {} & funcs
7269 ((looking-at "[{(]")
7270 (setq paren (1+ paren))
7271 (forward-char 1))
7272 ((looking-at "[})]")
7273 (setq paren (1- paren))
7274 (forward-char 1)
7275 (when (< paren sig-paren)
7276 (setq expect-signal nil))) ; ) that ends variables inside v2k arg list
7278 (goto-char (match-end 0))
7279 (cond (newsig ; Memory, not just width. Patch last signal added's memory (nth 3)
7280 (setcar (cdr (cdr (cdr newsig))) (match-string 1)))
7281 (vec ;; Multidimensional
7282 (setq multidim (cons vec multidim))
7283 (setq vec (verilog-string-replace-matches
7285 (t ;; Bit width
7286 (setq vec (verilog-string-replace-matches
7288 ;; Normal or escaped identifier -- note we remember the \ if escaped
7290 (goto-char (match-end 0))
7291 (setq keywd (match-string 1))
7293 (setq keywd (concat keywd " "))) ;; Escaped ID needs space at end
7294 ;; Add any :: package names to same identifier
7296 (goto-char (match-end 0))
7297 (setq keywd (concat keywd "::" (match-string 1)))
7299 (setq keywd (concat keywd " ")))) ;; Escaped ID needs space at end
7300 (cond ((equal keywd "input")
7301 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren
7302 expect-signal 'sigs-in io t modport nil))
7303 ((equal keywd "output")
7304 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren
7305 expect-signal 'sigs-out io t modport nil))
7306 ((equal keywd "inout")
7307 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren
7308 expect-signal 'sigs-inout io t modport nil))
7309 ((equal keywd "parameter")
7310 (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
7311 expect-signal 'sigs-gparam io t modport nil))
7312 ((member keywd '("wire" "tri" "tri0" "tri1" "triand" "trior" "wand" "wor"))
7313 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
7314 expect-signal 'sigs-wire modport nil)))
7315 ((member keywd '("reg" "trireg"
7316 "byte" "shortint" "int" "longint" "integer" "time"
7317 "bit" "logic"
7318 "shortreal" "real" "realtime"
7319 "string" "event" "chandle"))
7320 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
7321 expect-signal 'sigs-reg modport nil)))
7322 ((equal keywd "assign")
7323 (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
7324 expect-signal 'sigs-assign modport nil))
7325 ((member keywd '("supply0" "supply1" "supply"
7326 "localparam" "genvar"))
7327 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
7328 expect-signal 'sigs-const modport nil)))
7329 ((equal keywd "signed")
7330 (setq signed "signed"))
7331 ((member keywd '("class" "clocking" "covergroup" "function"
7332 "property" "randsequence" "sequence" "task"))
7333 (setq functask (1+ functask)))
7334 ((member keywd '("endclass" "endclocking" "endgroup" "endfunction"
7335 "endproperty" "endsequence" "endtask"))
7336 (setq functask (1- functask)))
7337 ((equal keywd "modport")
7338 (setq in-modport t))
7339 ;; Ifdef? Ignore name of define
7340 ((member keywd '("`ifdef" "`ifndef" "`elsif"))
7341 (setq rvalue t))
7342 ;; Type?
7343 ((verilog-typedef-name-p keywd)
7344 (setq typedefed keywd))
7345 ;; Interface with optional modport in v2k arglist?
7346 ;; Skip over parsing modport, and take the interface name as the type
7347 ((and v2kargs-ok
7348 (eq paren 1)
7349 (not rvalue)
7350 (looking-at "\\s-*\\(\\.\\(\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*\\)\\|\\)\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*"))
7351 (when (match-end 2) (goto-char (match-end 2)))
7352 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed keywd multidim nil sig-paren paren
7353 expect-signal 'sigs-intf io t modport (match-string 2)))
7354 ;; Ignore dotted LHS assignments: "assign foo.bar = z;"
7356 (goto-char (match-end 0))
7357 (when (not rvalue)
7358 (setq expect-signal nil)))
7359 ;; New signal, maybe?
7360 ((and expect-signal
7361 (not rvalue)
7362 (eq functask 0)
7363 (not in-modport)
7364 (not (member keywd verilog-keywords)))
7365 ;; Add new signal to expect-signal's variable
7366 (setq newsig (verilog-sig-new keywd vec nil nil enum signed typedefed multidim modport))
7367 (set expect-signal (cons newsig
7368 (symbol-value expect-signal))))))
7369 (t
7370 (forward-char 1)))
7371 (skip-syntax-forward " "))
7372 ;; Return arguments
7373 (verilog-decls-new (nreverse sigs-out)
7374 (nreverse sigs-inout)
7375 (nreverse sigs-in)
7376 (nreverse sigs-wire)
7377 (nreverse sigs-reg)
7378 (nreverse sigs-assign)
7379 (nreverse sigs-const)
7380 (nreverse sigs-gparam)
7381 (nreverse sigs-intf)))))
7383 (defvar verilog-read-sub-decls-in-interfaced nil
7384 "For `verilog-read-sub-decls', process next signal as under interfaced block.")
7386 (defvar verilog-read-sub-decls-gate-ios nil
7387 "For `verilog-read-sub-decls', gate IO pins remaining, nil if non-primitive.")
7389 (eval-when-compile
7390 ;; Prevent compile warnings; these are let's, not globals
7391 ;; Do not remove the eval-when-compile
7392 ;; - we want a error when we are debugging this code if they are refed.
7393 (defvar sigs-in)
7394 (defvar sigs-inout)
7395 (defvar sigs-out)
7396 (defvar sigs-intf)
7397 (defvar sigs-intfd))
7399 (defun verilog-read-sub-decls-sig (submoddecls comment port sig vec multidim)
7400 "For `verilog-read-sub-decls-line', add a signal."
7401 ;; sig eq t to indicate .name syntax
7402 ;;(message "vrsds: %s(%S)" port sig)
7403 (let ((dotname (eq sig t))
7404 portdata)
7405 (when sig
7406 (setq port (verilog-symbol-detick-denumber port))
7407 (setq sig (if dotname port (verilog-symbol-detick-denumber sig)))
7408 (if vec (setq vec (verilog-symbol-detick-denumber vec)))
7409 (if multidim (setq multidim (mapcar `verilog-symbol-detick-denumber multidim)))
7410 (unless (or (not sig)
7411 (equal sig "")) ;; Ignore .foo(1'b1) assignments
7412 (cond ((or (setq portdata (assoc port (verilog-decls-get-inouts submoddecls)))
7413 (equal "inout" verilog-read-sub-decls-gate-ios))
7414 (setq sigs-inout
7415 (cons (verilog-sig-new
7416 sig
7417 (if dotname (verilog-sig-bits portdata) vec)
7418 (concat "To/From " comment) nil nil
7419 (verilog-sig-signed portdata)
7420 (verilog-sig-type portdata)
7421 multidim nil)
7422 sigs-inout)))
7423 ((or (setq portdata (assoc port (verilog-decls-get-outputs submoddecls)))
7424 (equal "output" verilog-read-sub-decls-gate-ios))
7425 (setq sigs-out
7426 (cons (verilog-sig-new
7427 sig
7428 (if dotname (verilog-sig-bits portdata) vec)
7429 (concat "From " comment) nil nil
7430 (verilog-sig-signed portdata)
7431 (verilog-sig-type portdata)
7432 multidim nil)
7433 sigs-out)))
7434 ((or (setq portdata (assoc port (verilog-decls-get-inputs submoddecls)))
7435 (equal "input" verilog-read-sub-decls-gate-ios))
7436 (setq sigs-in
7437 (cons (verilog-sig-new
7438 sig
7439 (if dotname (verilog-sig-bits portdata) vec)
7440 (concat "To " comment) nil nil
7441 (verilog-sig-signed portdata)
7442 (verilog-sig-type portdata)
7443 multidim nil)
7444 sigs-in)))
7445 ((setq portdata (assoc port (verilog-decls-get-interfaces submoddecls)))
7446 (setq sigs-intf
7447 (cons (verilog-sig-new
7448 sig
7449 (if dotname (verilog-sig-bits portdata) vec)
7450 (concat "To/From " comment) nil nil
7451 (verilog-sig-signed portdata)
7452 (verilog-sig-type portdata)
7453 multidim nil)
7454 sigs-intf)))
7455 ((setq portdata (and verilog-read-sub-decls-in-interfaced
7456 (or (assoc port (verilog-decls-get-regs submoddecls))
7457 (assoc port (verilog-decls-get-wires submoddecls)))))
7458 (setq sigs-intfd
7459 (cons (verilog-sig-new
7460 sig
7461 (if dotname (verilog-sig-bits portdata) vec)
7462 (concat "To/From " comment) nil nil
7463 (verilog-sig-signed portdata)
7464 (verilog-sig-type portdata)
7465 multidim nil)
7466 sigs-intf)))
7467 ;; (t -- warning pin isn't defined.) ; Leave for lint tool
7468 )))))
7470 (defun verilog-read-sub-decls-expr (submoddecls comment port expr)
7471 "For `verilog-read-sub-decls-line', parse a subexpression and add signals."
7472 ;;(message "vrsde: '%s'" expr)
7473 ;; Replace special /*[....]*/ comments inserted by verilog-auto-inst-port
7475 ;; Remove front operators
7477 ;;
7478 (cond
7479 ;; {..., a, b} requires us to recurse on a,b
7480 ;; To support {#{},{#{a,b}} we'll just split everything on [{},]
7482 (unless verilog-auto-ignore-concat
7483 (let ((mlst (split-string (match-string 1 expr) "[{},]"))
7484 mstr)
7485 (while (setq mstr (pop mlst))
7486 (verilog-read-sub-decls-expr submoddecls comment port mstr)))))
7487 (t
7488 (let (sig vec multidim)
7489 ;; Remove leading reduction operators, etc
7491 ;;(message "vrsde-ptop: '%s'" expr)
7492 (cond ;; Find \signal. Final space is part of escaped signal name
7494 ;;(message "vrsde-s: '%s'" (match-string 1 expr))
7495 (setq sig (match-string 1 expr)
7496 expr (substring expr (match-end 0))))
7497 ;; Find signal
7499 ;;(message "vrsde-s: '%s'" (match-string 1 expr))
7500 (setq sig (verilog-string-remove-spaces (match-string 1 expr))
7501 expr (substring expr (match-end 0)))))
7502 ;; Find [vector] or [multi][multi][multi][vector]
7504 ;;(message "vrsde-v: '%s'" (match-string 1 expr))
7505 (when vec (setq multidim (cons vec multidim)))
7506 (setq vec (match-string 1 expr)
7507 expr (substring expr (match-end 0))))
7508 ;; If found signal, and nothing unrecognized, add the signal
7509 ;;(message "vrsde-rem: '%s'" expr)
7511 (verilog-read-sub-decls-sig submoddecls comment port sig vec multidim))))))
7513 (defun verilog-read-sub-decls-line (submoddecls comment)
7514 "For `verilog-read-sub-decls', read lines of port defs until none match.
7515 Inserts the list of signals found, using submodi to look up each port."
7516 (let (done port)
7517 (save-excursion
7518 (forward-line 1)
7519 (while (not done)
7520 ;; Get port name
7522 (setq port (match-string 1))
7523 (goto-char (match-end 0)))
7524 ;; .\escaped (
7526 (setq port (concat (match-string 1) " ")) ;; escaped id's need trailing space
7527 (goto-char (match-end 0)))
7528 ;; .name
7530 (verilog-read-sub-decls-sig
7531 submoddecls comment (match-string 1) t ; sig==t for .name
7532 nil nil) ; vec multidim
7533 (setq port nil))
7534 ;; .\escaped_name
7536 (verilog-read-sub-decls-sig
7537 submoddecls comment (concat (match-string 1) " ") t ; sig==t for .name
7538 nil nil) ; vec multidim
7539 (setq port nil))
7540 ;; random
7542 (setq port nil) ;; skip this line
7543 (goto-char (match-end 0)))
7544 (t
7545 (setq port nil done t))) ;; Unknown, ignore rest of line
7546 ;; Get signal name. Point is at the first-non-space after (
7547 ;; We intentionally ignore (non-escaped) signals with .s in them
7548 ;; this prevents AUTOWIRE etc from noticing hierarchical sigs.
7549 (when port
7551 (verilog-read-sub-decls-sig
7552 submoddecls comment port
7553 (verilog-string-remove-spaces (match-string 1)) ; sig
7554 nil nil)) ; vec multidim
7555 ;;
7557 (verilog-read-sub-decls-sig
7558 submoddecls comment port
7559 (verilog-string-remove-spaces (match-string 1)) ; sig
7560 (match-string 2) nil)) ; vec multidim
7561 ;; Fastpath was above looking-at's.
7562 ;; For something more complicated invoke a parser
7563 ((looking-at "[^)]+")
7564 (verilog-read-sub-decls-expr
7565 submoddecls comment port
7566 (buffer-substring
7567 (point) (1- (progn (search-backward "(") ; start at (
7568 (forward-sexp 1) (point)))))))) ; expr
7569 ;;
7570 (forward-line 1)))))
7572 (defun verilog-read-sub-decls-gate (submoddecls comment submod end-inst-point)
7573 "For `verilog-read-sub-decls', read lines of UDP gate decl until none match.
7574 Inserts the list of signals found."
7575 (save-excursion
7576 (let ((iolist (cdr (assoc submod verilog-gate-ios))))
7577 (while (< (point) end-inst-point)
7578 ;; Get primitive's signal name, as will never have port, and no trailing )
7579 (cond ((looking-at "//")
7582 (or (search-forward "*/")
7583 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
7586 (search-forward "*)")
7587 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
7588 ;; On pins, parse and advance to next pin
7589 ;; Looking at pin, but *not* an // Output comment, or ) to end the inst
7591 (goto-char (match-end 0))
7592 (setq verilog-read-sub-decls-gate-ios (or (car iolist) "input")
7593 iolist (cdr iolist))
7594 (verilog-read-sub-decls-expr
7595 submoddecls comment "primitive_port"
7596 (match-string 0)))
7597 (t
7598 (forward-char 1)
7599 (skip-syntax-forward " ")))))))
7601 (defun verilog-read-sub-decls ()
7602 "Internally parse signals going to modules under this module.
7603 Return a array of [ outputs inouts inputs ] signals for modules that are
7604 instantiated in this module. For example if declare A A (.B(SIG)) and SIG
7605 is a output, then SIG will be included in the list.
7607 This only works on instantiations created with /*AUTOINST*/ converted by
7609 component library to determine connectivity of the design.
7611 One work around for this problem is to manually create // Inputs and //
7612 Outputs comments above subcell signals, for example:
7614 module ModuleName (
7615 // Outputs
7616 .out (out),
7617 // Inputs
7618 .in (in));"
7619 (save-excursion
7620 (let ((end-mod-point (verilog-get-end-of-defun t))
7621 st-point end-inst-point
7622 ;; below 3 modified by verilog-read-sub-decls-line
7623 sigs-out sigs-inout sigs-in sigs-intf sigs-intfd)
7624 (verilog-beg-of-defun)
7626 (save-excursion
7627 (goto-char (match-beginning 0))
7628 (unless (verilog-inside-comment-p)
7629 ;; Attempt to snarf a comment
7630 (let* ((submod (verilog-read-inst-module))
7631 (inst (verilog-read-inst-name))
7632 (subprim (member submod verilog-gate-keywords))
7633 (comment (concat inst " of " submod ".v"))
7634 submodi submoddecls)
7635 (cond
7636 (subprim
7637 (setq submodi `primitive
7638 submoddecls (verilog-decls-new nil nil nil nil nil nil nil nil nil)
7639 comment (concat inst " of " submod))
7640 (verilog-backward-open-paren)
7641 (setq end-inst-point (save-excursion (forward-sexp 1) (point))
7642 st-point (point))
7643 (forward-char 1)
7644 (verilog-read-sub-decls-gate submoddecls comment submod end-inst-point))
7645 ;; Non-primitive
7646 (t
7647 (when (setq submodi (verilog-modi-lookup submod t))
7648 (setq submoddecls (verilog-modi-get-decls submodi)
7649 verilog-read-sub-decls-gate-ios nil)
7650 (verilog-backward-open-paren)
7651 (setq end-inst-point (save-excursion (forward-sexp 1) (point))
7652 st-point (point))
7653 ;; This could have used a list created by verilog-auto-inst
7654 ;; However I want it to be runnable even on user's manually added signals
7655 (let ((verilog-read-sub-decls-in-interfaced t))
7657 (verilog-read-sub-decls-line submoddecls comment))) ;; Modifies sigs-ifd
7658 (goto-char st-point)
7660 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-out
7661 (goto-char st-point)
7663 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-out
7664 (goto-char st-point)
7666 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-inout
7667 (goto-char st-point)
7669 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-in
7670 )))))))
7671 ;; Combine duplicate bits
7672 ;;(setq rr (vector sigs-out sigs-inout sigs-in))
7673 (verilog-subdecls-new
7674 (verilog-signals-combine-bus (nreverse sigs-out))
7675 (verilog-signals-combine-bus (nreverse sigs-inout))
7676 (verilog-signals-combine-bus (nreverse sigs-in))
7677 (verilog-signals-combine-bus (nreverse sigs-intf))
7678 (verilog-signals-combine-bus (nreverse sigs-intfd))))))
7680 (defun verilog-read-inst-pins ()
7681 "Return an array of [ pins ] for the current instantiation at point.
7682 For example if declare A A (.B(SIG)) then B will be included in the list."
7683 (save-excursion
7684 (let ((end-mod-point (point)) ;; presume at /*AUTOINST*/ point
7685 pins pin)
7686 (verilog-backward-open-paren)
7688 (setq pin (match-string 1))
7689 (unless (verilog-inside-comment-p)
7690 (setq pins (cons (list pin) pins))
7691 (when (looking-at "(")
7692 (forward-sexp 1))))
7693 (vector pins))))
7695 (defun verilog-read-arg-pins ()
7696 "Return an array of [ pins ] for the current argument declaration at point."
7697 (save-excursion
7698 (let ((end-mod-point (point)) ;; presume at /*AUTOARG*/ point
7699 pins pin)
7700 (verilog-backward-open-paren)
7702 (setq pin (match-string 1))
7703 (unless (verilog-inside-comment-p)
7704 (setq pins (cons (list pin) pins))))
7705 (vector pins))))
7707 (defun verilog-read-auto-constants (beg end-mod-point)
7708 "Return a list of AUTO_CONSTANTs used in the region from BEG to END-MOD-POINT."
7709 ;; Insert new
7710 (save-excursion
7711 (let (sig-list tpl-end-pt)
7712 (goto-char beg)
7715 (error "%s: Missing () after AUTO_CONSTANT" (verilog-point-text)))
7716 (search-forward "(" end-mod-point)
7717 (setq tpl-end-pt (save-excursion
7718 (backward-char 1)
7719 (forward-sexp 1) ;; Moves to paren that closes argdecl's
7720 (backward-char 1)
7721 (point)))
7723 (setq sig-list (cons (list (match-string 1) nil nil) sig-list))))
7724 sig-list)))
7726 (defvar verilog-cache-has-lisp nil "True if any AUTO_LISP in buffer.")
7727 (make-variable-buffer-local 'verilog-cache-has-lisp)
7729 (defun verilog-read-auto-lisp-present ()
7730 "Set `verilog-cache-has-lisp' if any AUTO_LISP in this buffer."
7731 (save-excursion
7734 (defun verilog-read-auto-lisp (start end)
7735 "Look for and evaluate a AUTO_LISP between START and END.
7736 Must call `verilog-read-auto-lisp-present' before this function."
7737 ;; This function is expensive for large buffers, so we cache if any AUTO_LISP exists
7738 (when verilog-cache-has-lisp
7739 (save-excursion
7740 (goto-char start)
7742 (backward-char)
7743 (let* ((beg-pt (prog1 (point)
7744 (forward-sexp 1))) ;; Closing paren
7745 (end-pt (point)))
7746 (eval-region beg-pt end-pt nil))))))
7748 (eval-when-compile
7749 ;; Prevent compile warnings; these are let's, not globals
7750 ;; Do not remove the eval-when-compile
7751 ;; - we want a error when we are debugging this code if they are refed.
7752 (defvar sigs-in)
7753 (defvar sigs-out)
7754 (defvar sigs-temp)
7755 (defvar uses-delayed)
7756 (defvar vector-skip-list))
7758 (defun verilog-read-always-signals-recurse
7759 (exit-keywd rvalue temp-next)
7760 "Recursive routine for parentheses/bracket matching.
7761 EXIT-KEYWD is expression to stop at, nil if top level.
7762 RVALUE is true if at right hand side of equal.
7763 IGNORE-NEXT is true to ignore next token, fake from inside case statement."
7764 (let* ((semi-rvalue (equal "endcase" exit-keywd)) ;; true if after a ; we are looking for rvalue
7765 keywd last-keywd sig-tolk sig-last-tolk gotend got-sig got-list end-else-check
7766 ignore-next)
7768 (while (not (or (eobp) gotend))
7769 (cond
7770 ((looking-at "//")
7773 (or (search-forward "*/")
7774 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
7777 (search-forward "*)")
7778 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
7779 (t (setq keywd (buffer-substring-no-properties
7780 (point)
7781 (save-excursion (when (eq 0 (skip-chars-forward "a-zA-Z0-9$_.%`"))
7782 (forward-char 1))
7783 (point)))
7784 sig-last-tolk sig-tolk
7785 sig-tolk nil)
7786 ;;(if dbg (setq dbg (concat dbg (format "\tPt=%S %S\trv=%S in=%S ee=%S gs=%S\n" (point) keywd rvalue ignore-next end-else-check got-sig))))
7787 (cond
7790 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
7791 ;; else at top level loop, keep parsing
7792 ((and end-else-check (equal keywd "else"))
7794 ;; no forward movement, want to see else in lower loop
7795 (setq end-else-check nil))
7796 ;; End at top level loop
7799 (setq gotend t))
7800 ;; Final statement?
7801 ((and exit-keywd (equal keywd exit-keywd))
7802 (setq gotend t)
7803 (forward-char (length keywd)))
7804 ;; Standard tokens...
7805 ((equal keywd ";")
7806 (setq ignore-next nil rvalue semi-rvalue)
7807 ;; Final statement at top level loop?
7808 (when (not exit-keywd)
7810 (setq end-else-check t))
7811 (forward-char 1))
7812 ((equal keywd "'")
7814 (goto-char (match-end 0))
7815 (forward-char 1)))
7816 ((equal keywd ":") ;; Case statement, begin/end label, x?y:z
7817 (cond ((equal "endcase" exit-keywd) ;; case x: y=z; statement next
7818 (setq ignore-next nil rvalue nil))
7819 ((equal "?" exit-keywd) ;; x?y:z rvalue
7820 ) ;; NOP
7821 ((equal "]" exit-keywd) ;; [x:y] rvalue
7822 ) ;; NOP
7823 (got-sig ;; label: statement
7824 (setq ignore-next nil rvalue semi-rvalue got-sig nil))
7825 ((not rvalue) ;; begin label
7826 (setq ignore-next t rvalue nil)))
7827 (forward-char 1))
7828 ((equal keywd "=")
7829 (if (and (eq (char-before) ?< )
7830 (not rvalue))
7831 (setq uses-delayed 1))
7832 (setq ignore-next nil rvalue t)
7833 (forward-char 1))
7834 ((equal keywd "?")
7835 (forward-char 1)
7836 (verilog-read-always-signals-recurse ":" rvalue nil))
7837 ((equal keywd "[")
7838 (forward-char 1)
7839 (verilog-read-always-signals-recurse "]" t nil))
7840 ((equal keywd "(")
7841 (forward-char 1)
7842 (cond (sig-last-tolk ;; Function call; zap last signal
7843 (setq got-sig nil)))
7844 (cond ((equal last-keywd "for")
7845 ;; temp-next: Variables on LHS are lvalues, but generally we want
7846 ;; to ignore them, assuming they are loop increments
7847 (verilog-read-always-signals-recurse ";" nil t)
7848 (verilog-read-always-signals-recurse ";" t nil)
7849 (verilog-read-always-signals-recurse ")" nil nil))
7850 (t (verilog-read-always-signals-recurse ")" t nil))))
7851 ((equal keywd "begin")
7852 (skip-syntax-forward "w_")
7853 (verilog-read-always-signals-recurse "end" nil nil)
7855 (setq ignore-next nil rvalue semi-rvalue)
7856 (if (not exit-keywd) (setq end-else-check t)))
7857 ((member keywd '("case" "casex" "casez"))
7858 (skip-syntax-forward "w_")
7859 (verilog-read-always-signals-recurse "endcase" t nil)
7860 (setq ignore-next nil rvalue semi-rvalue)
7861 (if (not exit-keywd) (setq gotend t))) ;; top level begin/end
7862 ((string-match "^[$`a-zA-Z_]" keywd) ;; not exactly word constituent
7863 (cond ((member keywd '("`ifdef" "`ifndef" "`elsif"))
7864 (setq ignore-next t))
7865 ((or ignore-next
7866 (member keywd verilog-keywords)
7868 (setq ignore-next nil))
7869 (t
7870 (setq keywd (verilog-symbol-detick-denumber keywd))
7871 (when got-sig
7872 (set got-list (cons got-sig (symbol-value got-list)))
7874 )
7875 (setq got-list (cond (temp-next 'sigs-temp)
7876 (rvalue 'sigs-in)
7877 (t 'sigs-out))
7878 got-sig (if (or (not keywd)
7879 (assoc keywd (symbol-value got-list)))
7880 nil (list keywd nil nil))
7881 temp-next nil
7882 sig-tolk t)))
7883 (skip-chars-forward "a-zA-Z0-9$_.%`"))
7884 (t
7885 (forward-char 1)))
7886 ;; End of non-comment token
7887 (setq last-keywd keywd)))
7888 (skip-syntax-forward " "))
7889 ;; Append the final pending signal
7890 (when got-sig
7891 ;;(if dbg (setq dbg (concat dbg (format "\t\tfinal got-sig=%S got-list=%s\n" got-sig got-list))))
7892 (set got-list (cons got-sig (symbol-value got-list)))
7893 (setq got-sig nil))
7895 ))
7897 (defun verilog-read-always-signals ()
7898 "Parse always block at point and return list of (outputs inout inputs)."
7899 (save-excursion
7900 (let* (;;(dbg "")
7901 sigs-out sigs-temp sigs-in
7902 uses-delayed) ;; Found signal/rvalue; push if not function
7903 (search-forward ")")
7904 (verilog-read-always-signals-recurse nil nil nil)
7905 ;;(if dbg (with-current-buffer (get-buffer-create "*vl-dbg*")) (delete-region (point-min) (point-max)) (insert dbg) (setq dbg ""))
7906 ;; Return what was found
7907 (verilog-alw-new sigs-out sigs-temp sigs-in uses-delayed))))
7909 (defun verilog-read-instants ()
7910 "Parse module at point and return list of ( ( file instance ) ... )."
7911 (verilog-beg-of-defun)
7912 (let* ((end-mod-point (verilog-get-end-of-defun t))
7913 (state nil)
7914 (instants-list nil))
7915 (save-excursion
7916 (while (< (point) end-mod-point)
7917 ;; Stay at level 0, no comments
7918 (while (progn
7919 (setq state (parse-partial-sexp (point) end-mod-point 0 t nil))
7920 (or (> (car state) 0) ; in parens
7921 (nth 5 state) ; comment
7922 ))
7923 (forward-line 1))
7924 (beginning-of-line)
7927 (let ((module (match-string 1))
7928 (instant (match-string 2)))
7929 (if (not (member module verilog-keywords))
7930 (setq instants-list (cons (list module instant) instants-list)))))
7931 (forward-line 1)))
7932 instants-list))
7935 (defun verilog-read-auto-template (module)
7936 "Look for a auto_template for the instantiation of the given MODULE.
7937 If found returns the signal name connections. Return REGEXP and
7938 list of ( (signal_name connection_name)... )."
7939 (save-excursion
7940 ;; Find beginning
7942 (lineno 0)
7943 (templateno 0)
7944 (pt (point))
7945 tpl-sig-list tpl-wild-list tpl-end-pt rep)
7946 ;; Note this search is expensive, as we hunt from mod-begin to point
7947 ;; for every instantiation. Likewise in verilog-read-auto-lisp.
7948 ;; So, we look first for an exact string rather than a slow regexp.
7949 ;; Someday we may keep a cache of every template, but this would also
7950 ;; need to record the relative position of each AUTOINST, as multiple
7951 ;; templates exist for each module, and we're inserting lines.
7952 (cond ((or
7953 (verilog-re-search-backward-substr
7954 "AUTO_TEMPLATE"
7956 ;; Also try forward of this AUTOINST
7957 ;; This is for historical support; this isn't speced as working
7958 (progn
7959 (goto-char pt)
7960 (verilog-re-search-forward-substr
7961 "AUTO_TEMPLATE"
7963 (goto-char (match-end 0))
7964 ;; Parse "REGEXP"
7965 ;; We reserve @"..." for future lisp expressions that evaluate
7966 ;; once-per-AUTOINST
7968 (setq tpl-regexp (match-string 1))
7969 (goto-char (match-end 0)))
7970 (search-forward "(")
7971 ;; Parse lines in the template
7972 (when verilog-auto-inst-template-numbers
7973 (save-excursion
7974 (goto-char (point-min))
7975 (while (search-forward "AUTO_TEMPLATE" nil t)
7976 (setq templateno (1+ templateno)))))
7977 (setq tpl-end-pt (save-excursion
7978 (backward-char 1)
7979 (forward-sexp 1) ;; Moves to paren that closes argdecl's
7980 (backward-char 1)
7981 (point)))
7982 ;;
7983 (while (< (point) tpl-end-pt)
7985 (setq tpl-sig-list (cons (list
7986 (match-string-no-properties 1)
7987 (match-string-no-properties 2)
7988 templateno lineno)
7989 tpl-sig-list))
7990 (goto-char (match-end 0)))
7991 ;; Regexp form??
7992 ((looking-at
7993 ;; Regexp bug in XEmacs disallows ][ inside [], and wants + last
7994 "\\s-*\\.\\(\\([a-zA-Z0-9`_$+@^.*?|---]+\\|[][]\\|\\\\[()|]\\)+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
7995 (setq rep (match-string-no-properties 3))
7996 (goto-char (match-end 0))
7997 (setq tpl-wild-list
7998 (cons (list
7999 (concat "^"
8001 (match-string 1))
8002 "$")
8003 rep
8004 templateno lineno)
8005 tpl-wild-list)))
8007 (goto-char (match-end 0)))
8009 (setq lineno (1+ lineno))
8010 (goto-char (match-end 0)))
8011 ((looking-at "//")
8014 (forward-char 2)
8015 (or (search-forward "*/")
8016 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
8017 (t
8018 (error "%s: AUTO_TEMPLATE parsing error: %s"
8019 (verilog-point-text)
8020 (progn (looking-at ".*$") (match-string 0))))))
8021 ;; Return
8022 (vector tpl-regexp
8023 (list tpl-sig-list tpl-wild-list)))
8024 ;; If no template found
8025 (t (vector tpl-regexp nil))))))
8026 ;;(progn (find-file "auto-template.v") (verilog-read-auto-template "ptl_entry"))
8028 (defun verilog-set-define (defname defvalue &optional buffer enumname)
8029 "Set the definition DEFNAME to the DEFVALUE in the given BUFFER.
8030 Optionally associate it with the specified enumeration ENUMNAME."
8031 (with-current-buffer (or buffer (current-buffer))
8032 (let ((mac (intern (concat "vh-" defname))))
8033 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
8034 ;; Need to define to a constant if no value given
8035 (set (make-local-variable mac)
8036 (if (equal defvalue "") "1" defvalue)))
8037 (if enumname
8038 (let ((enumvar (intern (concat "venum-" enumname))))
8039 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
8040 (unless (boundp enumvar) (set enumvar nil))
8041 (make-local-variable enumvar)
8042 (add-to-list enumvar defname)))))
8044 (defun verilog-read-defines (&optional filename recurse subcall)
8045 "Read `defines and parameters for the current file, or optional FILENAME.
8046 If the filename is provided, `verilog-library-flags' will be used to
8047 resolve it. If optional RECURSE is non-nil, recurse through `includes.
8049 Parameters must be simple assignments to constants, or have their own
8052 parameter X = 5, Y = 10; // Ok
8053 parameter X = {1'b1, 2'h2}; // Ok
8054 parameter X = {1'b1, 2'h2}, Y = 10; // Bad, make into 2 parameter lines
8056 Defines must be simple text substitutions, one on a line, starting
8057 at the beginning of the line. Any ifdefs or multiline comments around the
8058 define are ignored.
8060 Defines are stored inside Emacs variables using the name vh-{definename}.
8062 This function is useful for setting vh-* variables. The file variables
8063 feature can be used to set defines that `verilog-mode' can see; put at the
8064 *END* of your file something like:
8066 // Local Variables:
8068 // End:
8070 If macros are defined earlier in the same file and you want their values,
8071 you can read them automatically (provided `enable-local-eval' is on):
8073 // Local Variables:
8074 // eval:(verilog-read-defines)
8076 // End:
8078 Note these are only read when the file is first visited, you must use
8082 warning message, you need to add to your .emacs file:
8084 (setq enable-local-eval t)"
8085 (let ((origbuf (current-buffer)))
8086 (save-excursion
8087 (unless subcall (verilog-getopt-flags))
8088 (when filename
8089 (let ((fns (verilog-library-filenames filename (buffer-file-name))))
8090 (if fns
8091 (set-buffer (find-file-noselect (car fns)))
8092 (error (concat (verilog-point-text)
8093 ": Can't find verilog-read-defines file: " filename)))))
8094 (when recurse
8095 (goto-char (point-min))
8097 (let ((inc (verilog-string-replace-matches
8099 (unless (verilog-inside-comment-p)
8100 (verilog-read-defines inc recurse t)))))
8101 ;; Read `defines
8102 ;; note we don't use verilog-re... it's faster this way, and that
8103 ;; function has problems when comments are at the end of the define
8104 (goto-char (point-min))
8106 (let ((defname (match-string-no-properties 1))
8107 (defvalue (match-string-no-properties 2)))
8109 (verilog-set-define defname defvalue origbuf)))
8110 ;; Hack: Read parameters
8111 (goto-char (point-min))
8112 (while (re-search-forward
8114 (let (enumname)
8115 ;; The primary way of getting defines is verilog-read-decls
8116 ;; However, that isn't called yet for included files, so we'll add another scheme
8118 (setq enumname (match-string-no-properties 1)))
8119 (forward-comment 999)
8121 (verilog-set-define (match-string-no-properties 1)
8122 (match-string-no-properties 2) origbuf enumname)
8123 (goto-char (match-end 0))
8124 (forward-comment 999)))))))
8126 (defun verilog-read-includes ()
8127 "Read `includes for the current file.
8128 This will find all of the `includes which are at the beginning of lines,
8129 ignoring any ifdefs or multiline comments around them.
8130 `verilog-read-defines' is then performed on the current and each included
8131 file.
8133 It is often useful put at the *END* of your file something like:
8135 // Local Variables:
8136 // eval:(verilog-read-defines)
8137 // eval:(verilog-read-includes)
8138 // End:
8140 Note includes are only read when the file is first visited, you must use
8143 It is good to get in the habit of including all needed files in each .v
8144 file that needs it, rather than waiting for compile time. This will aid
8145 this process, Verilint, and readability. To prevent defining the same
8146 variable over and over when many modules are compiled together, put a test
8147 around the inside each include file:
8149 foo.v (a include):
8150 `ifdef _FOO_V // include if not already included
8151 `else
8152 `define _FOO_V
8153 ... contents of file
8154 `endif // _FOO_V"
8155 ;;slow: (verilog-read-defines nil t))
8156 (save-excursion
8157 (verilog-getopt-flags)
8158 (goto-char (point-min))
8161 (verilog-read-defines inc nil t)))))
8163 (defun verilog-read-signals (&optional start end)
8164 "Return a simple list of all possible signals in the file.
8165 Bounded by optional region from START to END. Overly aggressive but fast.
8166 Some macros and such are also found and included. For dinotrace.el."
8167 (let (sigs-all keywd)
8168 (progn;save-excursion
8169 (goto-char (or start (point-min)))
8170 (setq end (or end (point-max)))
8172 (forward-char -1)
8173 (cond
8174 ((looking-at "//")
8177 (search-forward "*/"))
8180 (search-forward "*)")))
8182 (re-search-forward "[^\\]\"")) ;; don't forward-char first, since we look for a non backslash first
8184 (goto-char (match-end 0))
8185 (setq keywd (match-string-no-properties 1))
8186 (or (member keywd verilog-keywords)
8187 (member keywd sigs-all)
8188 (setq sigs-all (cons keywd sigs-all))))
8189 (t (forward-char 1))))
8190 ;; Return list
8191 sigs-all)))
8193 ;;
8194 ;; Argument file parsing
8195 ;;
8197 (defun verilog-getopt (arglist)
8198 "Parse -f, -v etc arguments in ARGLIST list or string."
8199 (unless (listp arglist) (setq arglist (list arglist)))
8200 (let ((space-args '())
8201 arg next-param)
8202 ;; Split on spaces, so users can pass whole command lines
8203 (while arglist
8204 (setq arg (car arglist)
8205 arglist (cdr arglist))
8207 (setq space-args (append space-args
8208 (list (match-string-no-properties 1 arg))))
8209 (setq arg (match-string 2 arg))))
8210 ;; Parse arguments
8211 (while space-args
8212 (setq arg (car space-args)
8213 space-args (cdr space-args))
8214 (cond
8215 ;; Need another arg
8216 ((equal arg "-f")
8217 (setq next-param arg))
8218 ((equal arg "-v")
8219 (setq next-param arg))
8220 ((equal arg "-y")
8221 (setq next-param arg))
8222 ;; +libext+(ext1)+(ext2)...
8224 (setq arg (match-string 1 arg))
8226 (verilog-add-list-unique `verilog-library-extensions
8227 (match-string 1 arg))
8228 (setq arg (match-string 2 arg))))
8229 ;;
8234 (verilog-set-define (match-string 1 arg) (match-string 2 arg)))
8235 ;;
8238 (verilog-add-list-unique `verilog-library-directories
8239 (match-string 1 (substitute-in-file-name arg))))
8240 ;; Ignore
8241 ((equal "+librescan" arg))
8243 ;; Second parameters
8244 ((equal next-param "-f")
8245 (setq next-param nil)
8246 (verilog-getopt-file (substitute-in-file-name arg)))
8247 ((equal next-param "-v")
8248 (setq next-param nil)
8249 (verilog-add-list-unique `verilog-library-files
8250 (substitute-in-file-name arg)))
8251 ((equal next-param "-y")
8252 (setq next-param nil)
8253 (verilog-add-list-unique `verilog-library-directories
8254 (substitute-in-file-name arg)))
8255 ;; Filename
8256 ((string-match "^[^-+]" arg)
8257 (verilog-add-list-unique `verilog-library-files
8258 (substitute-in-file-name arg)))
8259 ;; Default - ignore; no warning
8260 ))))
8261 ;;(verilog-getopt (list "+libext+.a+.b" "+incdir+foodir" "+define+a+aval" "-f" "otherf" "-v" "library" "-y" "dir"))
8263 (defun verilog-getopt-file (filename)
8264 "Read Verilog options from the specified FILENAME."
8265 (save-excursion
8266 (let ((fns (verilog-library-filenames filename (buffer-file-name)))
8267 (orig-buffer (current-buffer))
8268 line)
8269 (if fns
8270 (set-buffer (find-file-noselect (car fns)))
8271 (error (concat (verilog-point-text)
8272 ": Can't find verilog-getopt-file -f file: " filename)))
8273 (goto-char (point-min))
8274 (while (not (eobp))
8275 (setq line (buffer-substring (point)
8276 (save-excursion (end-of-line) (point))))
8277 (forward-line 1)
8278 (when (string-match "//" line)
8279 (setq line (substring line 0 (match-beginning 0))))
8280 (with-current-buffer orig-buffer ; Variables are buffer-local, so need right context.
8281 (verilog-getopt line))))))
8283 (defun verilog-getopt-flags ()
8284 "Convert `verilog-library-flags' into standard library variables."
8285 ;; If the flags are local, then all the outputs should be local also
8286 (when (local-variable-p `verilog-library-flags (current-buffer))
8287 (mapc 'make-local-variable '(verilog-library-extensions
8288 verilog-library-directories
8289 verilog-library-files
8290 verilog-library-flags)))
8291 ;; Allow user to customize
8292 (run-hooks 'verilog-before-getopt-flags-hook)
8293 ;; Process arguments
8294 (verilog-getopt verilog-library-flags)
8295 ;; Allow user to customize
8296 (run-hooks 'verilog-getopt-flags-hook))
8298 (defun verilog-add-list-unique (varref object)
8299 "Append to VARREF list the given OBJECT,
8300 unless it is already a member of the variable's list."
8301 (unless (member object (symbol-value varref))
8302 (set varref (append (symbol-value varref) (list object))))
8303 varref)
8304 ;;(progn (setq l '()) (verilog-add-list-unique `l "a") (verilog-add-list-unique `l "a") l)
8306 (defun verilog-current-flags ()
8307 "Convert `verilog-library-flags' and similar variables to command line.
8308 Used for __FLAGS__ in `verilog-expand-command'."
8309 (let ((cmd (mapconcat `concat verilog-library-flags " ")))
8310 (when (equal cmd "")
8311 (setq cmd (concat
8312 "+libext+" (mapconcat `concat verilog-library-extensions "+")
8313 (mapconcat (lambda (i) (concat " -y " i " +incdir+" i))
8314 verilog-library-directories "")
8315 (mapconcat (lambda (i) (concat " -v " i))
8316 verilog-library-files ""))))
8317 cmd))
8318 ;;(verilog-current-flags)
8320 \f
8321 ;;
8322 ;; Cached directory support
8323 ;;
8325 (defvar verilog-dir-cache-preserving nil
8326 "If set, the directory cache is enabled, and file system changes are ignored.
8327 See `verilog-dir-exists-p' and `verilog-dir-files'.")
8329 ;; If adding new cached variable, add also to verilog-preserve-dir-cache
8330 (defvar verilog-dir-cache-list nil
8331 "Alist of (((Cwd Dirname) Results)...) for caching `verilog-dir-files'.")
8332 (defvar verilog-dir-cache-lib-filenames nil
8333 "Cached data for `verilog-library-filenames'.")
8335 (defmacro verilog-preserve-dir-cache (&rest body)
8336 "Execute the BODY forms, allowing directory cache preservation within BODY.
8337 This means that changes inside BODY made to the file system will not be
8338 seen by the `verilog-dir-files' and related functions."
8339 `(let ((verilog-dir-cache-preserving (current-buffer))
8340 verilog-dir-cache-list
8341 verilog-dir-cache-lib-filenames)
8342 (progn ,@body)))
8344 (defun verilog-dir-files (dirname)
8345 "Return all filenames in the DIRNAME directory.
8346 Relative paths depend on the `default-directory'.
8347 Results are cached if inside `verilog-preserve-dir-cache'."
8348 (unless verilog-dir-cache-preserving
8349 (setq verilog-dir-cache-list nil)) ;; Cache disabled
8350 ;; We don't use expand-file-name on the dirname to make key, as it's slow
8351 (let* ((cache-key (list dirname default-directory))
8352 (fass (assoc cache-key verilog-dir-cache-list))
8353 exp-dirname data)
8354 (cond (fass ;; Return data from cache hit
8355 (nth 1 fass))
8356 (t
8357 (setq exp-dirname (expand-file-name dirname)
8358 data (and (file-directory-p exp-dirname)
8359 (directory-files exp-dirname nil nil nil)))
8360 ;; Note we also encache nil for non-existing dirs.
8361 (setq verilog-dir-cache-list (cons (list cache-key data)
8362 verilog-dir-cache-list))
8363 data))))
8364 ;; Miss-and-hit test:
8365 ;;(verilog-preserve-dir-cache (prin1 (verilog-dir-files "."))
8366 ;; (prin1 (verilog-dir-files ".")) nil)
8368 (defun verilog-dir-file-exists-p (filename)
8369 "Return true if FILENAME exists.
8370 Like `file-exists-p' but results are cached if inside
8371 `verilog-preserve-dir-cache'."
8372 (let* ((dirname (file-name-directory filename))
8373 ;; Correct for file-name-nondirectory returning same if no slash.
8374 (dirnamed (if (or (not dirname) (equal dirname filename))
8375 default-directory dirname))
8376 (flist (verilog-dir-files dirnamed)))
8377 (and flist
8378 (member (file-name-nondirectory filename) flist)
8379 t)))
8380 ;;(verilog-dir-file-exists-p "verilog-mode.el")
8381 ;;(verilog-dir-file-exists-p "../verilog-mode/verilog-mode.el")
8383 \f
8384 ;;
8385 ;; Module name lookup
8386 ;;
8388 (defun verilog-module-inside-filename-p (module filename)
8389 "Return modi if MODULE is specified inside FILENAME, else nil.
8390 Allows version control to check out the file if need be."
8391 (and (or (file-exists-p filename)
8392 (and (fboundp 'vc-backend)
8393 (vc-backend filename)))
8394 (let (modi type)
8395 (with-current-buffer (find-file-noselect filename)
8396 (save-excursion
8397 (goto-char (point-min))
8398 (while (and
8399 ;; It may be tempting to look for verilog-defun-re,
8400 ;; don't, it slows things down a lot!
8402 (setq type (match-string-no-properties 0))
8403 (verilog-re-search-forward-quick "[(;]" nil t))
8404 (if (equal module (verilog-read-module-name))
8405 (setq modi (verilog-modi-new module filename (point) type))))
8406 modi)))))
8408 (defun verilog-is-number (symbol)
8409 "Return true if SYMBOL is number-like."
8411 (string-match "^[---]*[0-9]+$" symbol)
8414 (defun verilog-symbol-detick (symbol wing-it)
8415 "Return an expanded SYMBOL name without any defines.
8416 If the variable vh-{symbol} is defined, return that value.
8417 If undefined, and WING-IT, return just SYMBOL without the tick, else nil."
8418 (while (and symbol (string-match "^`" symbol))
8419 (setq symbol (substring symbol 1))
8420 (setq symbol
8421 (if (boundp (intern (concat "vh-" symbol)))
8422 ;; Emacs has a bug where boundp on a buffer-local
8423 ;; variable in only one buffer returns t in another.
8424 ;; This can confuse, so check for nil.
8425 (let ((val (eval (intern (concat "vh-" symbol)))))
8426 (if (eq val nil)
8427 (if wing-it symbol nil)
8428 val))
8429 (if wing-it symbol nil))))
8430 symbol)
8431 ;;(verilog-symbol-detick "`mod" nil)
8433 (defun verilog-symbol-detick-denumber (symbol)
8434 "Return SYMBOL with defines converted and any numbers dropped to nil."
8435 (when (string-match "^`" symbol)
8436 ;; This only will work if the define is a simple signal, not
8437 ;; something like a[b]. Sorry, it should be substituted into the parser
8438 (setq symbol
8439 (verilog-string-replace-matches
8441 (or (verilog-symbol-detick symbol nil)
8442 (if verilog-auto-sense-defines-constant
8443 "0"
8444 symbol)))))
8445 (if (verilog-is-number symbol)
8446 nil
8447 symbol))
8449 (defun verilog-symbol-detick-text (text)
8450 "Return TEXT without any known defines.
8451 If the variable vh-{symbol} is defined, substitute that value."
8452 (let ((ok t) symbol val)
8454 (setq symbol (match-string 1 text))
8455 ;;(message symbol)
8456 (cond ((and
8457 (boundp (intern (concat "vh-" symbol)))
8458 ;; Emacs has a bug where boundp on a buffer-local
8459 ;; variable in only one buffer returns t in another.
8460 ;; This can confuse, so check for nil.
8461 (setq val (eval (intern (concat "vh-" symbol)))))
8462 (setq text (replace-match val nil nil text)))
8463 (t (setq ok nil)))))
8464 text)
8465 ;;(progn (setq vh-mod "`foo" vh-foo "bar") (verilog-symbol-detick-text "bar `mod `undefed"))
8467 (defun verilog-expand-dirnames (&optional dirnames)
8468 "Return a list of existing directories given a list of wildcarded DIRNAMES.
8469 Or, just the existing dirnames themselves if there are no wildcards."
8470 ;; Note this function is performance critical.
8471 ;; Do not call anything that requires disk access that cannot be cached.
8472 (interactive)
8473 (unless dirnames (error "`verilog-library-directories' should include at least '.'"))
8474 (setq dirnames (reverse dirnames)) ; not nreverse
8475 (let ((dirlist nil)
8476 pattern dirfile dirfiles dirname root filename rest basefile)
8477 (while dirnames
8478 (setq dirname (substitute-in-file-name (car dirnames))
8479 dirnames (cdr dirnames))
8483 dirname)
8484 (setq root (match-string 1 dirname)
8485 filename (match-string 2 dirname)
8486 rest (match-string 3 dirname)
8487 pattern filename)
8488 ;; now replace those * and ? with .+ and .
8489 ;; use ^ and /> to get only whole file names
8490 (setq pattern (verilog-string-replace-matches "[*]" ".+" nil nil pattern)
8491 pattern (verilog-string-replace-matches "[?]" "." nil nil pattern)
8492 pattern (concat "^" pattern "$")
8493 dirfiles (verilog-dir-files root))
8494 (while dirfiles
8495 (setq basefile (car dirfiles)
8496 dirfile (expand-file-name (concat root basefile rest))
8497 dirfiles (cdr dirfiles))
8498 (if (and (string-match pattern basefile)
8499 ;; Don't allow abc/*/rtl to match abc/rtl via ..
8500 (not (equal basefile "."))
8501 (not (equal basefile ".."))
8502 (file-directory-p dirfile))
8503 (setq dirlist (cons dirfile dirlist)))))
8504 ;; Defaults
8505 (t
8506 (if (file-directory-p dirname)
8507 (setq dirlist (cons dirname dirlist))))))
8508 dirlist))
8509 ;;(verilog-expand-dirnames (list "." ".." "nonexist" "../*" "/home/wsnyder/*/v"))
8511 (defun verilog-library-filenames (filename &optional current check-ext)
8512 "Return a search path to find the given FILENAME or module name.
8513 Uses the optional CURRENT filename or buffer-file-name, plus
8514 `verilog-library-directories' and `verilog-library-extensions'
8515 variables to build the path. With optional CHECK-EXT also check
8516 `verilog-library-extensions'."
8517 (unless current (setq current (buffer-file-name)))
8518 (unless verilog-dir-cache-preserving
8519 (setq verilog-dir-cache-lib-filenames nil))
8520 (let* ((cache-key (list filename current check-ext))
8521 (fass (assoc cache-key verilog-dir-cache-lib-filenames))
8522 chkdirs chkdir chkexts fn outlist)
8523 (cond (fass ;; Return data from cache hit
8524 (nth 1 fass))
8525 (t
8526 ;; Note this expand can't be easily cached, as we need to
8527 ;; pick up buffer-local variables for newly read sub-module files
8528 (setq chkdirs (verilog-expand-dirnames verilog-library-directories))
8529 (while chkdirs
8530 (setq chkdir (expand-file-name (car chkdirs)
8531 (file-name-directory current))
8532 chkexts (if check-ext verilog-library-extensions `("")))
8533 (while chkexts
8534 (setq fn (expand-file-name (concat filename (car chkexts))
8535 chkdir))
8536 ;;(message "Check for %s" fn)
8537 (if (verilog-dir-file-exists-p fn)
8538 (setq outlist (cons (expand-file-name
8539 fn (file-name-directory current))
8540 outlist)))
8541 (setq chkexts (cdr chkexts)))
8542 (setq chkdirs (cdr chkdirs)))
8543 (setq outlist (nreverse outlist))
8544 (setq verilog-dir-cache-lib-filenames
8545 (cons (list cache-key outlist)
8546 verilog-dir-cache-lib-filenames))
8547 outlist))))
8549 (defun verilog-module-filenames (module current)
8550 "Return a search path to find the given MODULE name.
8551 Uses the CURRENT filename, `verilog-library-extensions',
8552 `verilog-library-directories' and `verilog-library-files'
8553 variables to build the path."
8554 ;; Return search locations for it
8555 (append (list current) ; first, current buffer
8556 (verilog-library-filenames module current t)
8557 verilog-library-files)) ; finally, any libraries
8559 ;;
8560 ;; Module Information
8561 ;;
8562 ;; Many of these functions work on "modi" a module information structure
8563 ;; A modi is: [module-name-string file-name begin-point]
8565 (defvar verilog-cache-enabled t
8566 "If true, enable caching of signals, etc. Set to nil for debugging to make things SLOW!")
8568 (defvar verilog-modi-cache-list nil
8569 "Cache of ((Module Function) Buf-Tick Buf-Modtime Func-Returns)...
8570 For speeding up verilog-modi-get-* commands.
8571 Buffer-local.")
8572 (make-variable-buffer-local 'verilog-modi-cache-list)
8574 (defvar verilog-modi-cache-preserve-tick nil
8575 "Modification tick after which the cache is still considered valid.
8576 Use `verilog-preserve-modi-cache' to set it.")
8577 (defvar verilog-modi-cache-preserve-buffer nil
8578 "Modification tick after which the cache is still considered valid.
8579 Use `verilog-preserve-modi-cache' to set it.")
8580 (defvar verilog-modi-cache-current-enable nil
8581 "If true, allow caching `verilog-modi-current', set by let().")
8582 (defvar verilog-modi-cache-current nil
8583 "Currently active `verilog-modi-current', if any, set by let().")
8584 (defvar verilog-modi-cache-current-max nil
8585 "Current endmodule point for `verilog-modi-cache-current', if any.")
8587 (defun verilog-modi-current ()
8588 "Return the modi structure for the module currently at point, possibly cached."
8589 (cond ((and verilog-modi-cache-current
8590 (>= (point) (verilog-modi-get-point verilog-modi-cache-current))
8591 (<= (point) verilog-modi-cache-current-max))
8592 ;; Slow assertion, for debugging the cache:
8593 ;;(or (equal verilog-modi-cache-current (verilog-modi-current-get)) (debug))
8594 verilog-modi-cache-current)
8595 (verilog-modi-cache-current-enable
8596 (setq verilog-modi-cache-current (verilog-modi-current-get)
8597 verilog-modi-cache-current-max
8598 ;; The cache expires when we pass "endmodule" as then the
8599 ;; current modi may change to the next module
8600 ;; This relies on the AUTOs generally inserting, not deleting text
8601 (save-excursion
8602 (verilog-re-search-forward-quick verilog-end-defun-re nil nil)))
8603 verilog-modi-cache-current)
8604 (t
8605 (verilog-modi-current-get))))
8607 (defun verilog-modi-current-get ()
8608 "Return the modi structure for the module currently at point."
8609 (let* (name type pt)
8610 ;; read current module's name
8611 (save-excursion
8612 (verilog-re-search-backward-quick verilog-defun-re nil nil)
8613 (setq type (match-string-no-properties 0))
8614 (verilog-re-search-forward-quick "(" nil nil)
8615 (setq name (verilog-read-module-name))
8616 (setq pt (point)))
8617 ;; return modi - note this vector built two places
8618 (verilog-modi-new name (or (buffer-file-name) (current-buffer)) pt type)))
8620 (defvar verilog-modi-lookup-cache nil "Hash of (modulename modi).")
8621 (make-variable-buffer-local 'verilog-modi-lookup-cache)
8622 (defvar verilog-modi-lookup-last-current nil "Cache of `current-buffer' at last lookup.")
8623 (defvar verilog-modi-lookup-last-tick nil "Cache of `buffer-chars-modified-tick' at last lookup.")
8625 (defun verilog-modi-lookup (module allow-cache &optional ignore-error)
8626 "Find the file and point at which MODULE is defined.
8627 If ALLOW-CACHE is set, check and remember cache of previous lookups.
8628 Return modi if successful, else print message unless IGNORE-ERROR is true."
8629 (let* ((current (or (buffer-file-name) (current-buffer)))
8630 modi)
8631 ;; Check cache
8632 ;;(message "verilog-modi-lookup: %s" module)
8633 (cond ((and verilog-modi-lookup-cache
8634 verilog-cache-enabled
8635 allow-cache
8636 (setq modi (gethash module verilog-modi-lookup-cache))
8637 (equal verilog-modi-lookup-last-current current)
8638 ;; Iff hit is in current buffer, then tick must match
8639 (or (equal verilog-modi-lookup-last-tick (buffer-chars-modified-tick))
8640 (not (equal current (verilog-modi-file-or-buffer modi)))))
8641 ;;(message "verilog-modi-lookup: HIT %S" modi)
8642 modi)
8643 ;; Miss
8644 (t (let* ((realmod (verilog-symbol-detick module t))
8645 (orig-filenames (verilog-module-filenames realmod current))
8646 (filenames orig-filenames)
8647 mif)
8648 (while (and filenames (not mif))
8649 (if (not (setq mif (verilog-module-inside-filename-p realmod (car filenames))))
8650 (setq filenames (cdr filenames))))
8651 ;; mif has correct form to become later elements of modi
8652 (cond (mif (setq modi mif))
8653 (t (setq modi nil)
8654 (or ignore-error
8655 (error (concat (verilog-point-text)
8656 ": Can't locate " module " module definition"
8657 (if (not (equal module realmod))
8658 (concat " (Expanded macro to " realmod ")")
8659 "")
8663 (when (eval-when-compile (fboundp 'make-hash-table))
8664 (unless verilog-modi-lookup-cache
8665 (setq verilog-modi-lookup-cache
8666 (make-hash-table :test 'equal :rehash-size 4.0)))
8667 (puthash module modi verilog-modi-lookup-cache))
8668 (setq verilog-modi-lookup-last-current current
8669 verilog-modi-lookup-last-tick (buffer-chars-modified-tick)))))
8670 modi))
8672 (defun verilog-modi-filename (modi)
8673 "Filename of MODI, or name of buffer if it's never been saved."
8674 (if (bufferp (verilog-modi-file-or-buffer modi))
8675 (or (buffer-file-name (verilog-modi-file-or-buffer modi))
8676 (buffer-name (verilog-modi-file-or-buffer modi)))
8677 (verilog-modi-file-or-buffer modi)))
8679 (defun verilog-modi-goto (modi)
8680 "Move point/buffer to specified MODI."
8681 (or modi (error "Passed unfound modi to goto, check earlier"))
8682 (set-buffer (if (bufferp (verilog-modi-file-or-buffer modi))
8683 (verilog-modi-file-or-buffer modi)
8684 (find-file-noselect (verilog-modi-file-or-buffer modi))))
8685 (or (equal major-mode `verilog-mode) ;; Put into Verilog mode to get syntax
8686 (verilog-mode))
8687 (goto-char (verilog-modi-get-point modi)))
8689 (defun verilog-goto-defun-file (module)
8690 "Move point to the file at which a given MODULE is defined."
8691 (interactive "sGoto File for Module: ")
8692 (let* ((modi (verilog-modi-lookup module nil)))
8693 (when modi
8694 (verilog-modi-goto modi)
8695 (switch-to-buffer (current-buffer)))))
8697 (defun verilog-modi-cache-results (modi function)
8698 "Run on MODI the given FUNCTION. Locate the module in a file.
8699 Cache the output of function so next call may have faster access."
8700 (let (fass)
8701 (save-excursion ;; Cache is buffer-local so can't avoid this.
8702 (verilog-modi-goto modi)
8703 (if (and (setq fass (assoc (list modi function)
8704 verilog-modi-cache-list))
8705 ;; Destroy caching when incorrect; Modified or file changed
8706 (not (and verilog-cache-enabled
8707 (or (equal (buffer-chars-modified-tick) (nth 1 fass))
8708 (and verilog-modi-cache-preserve-tick
8709 (<= verilog-modi-cache-preserve-tick (nth 1 fass))
8710 (equal verilog-modi-cache-preserve-buffer (current-buffer))))
8711 (equal (visited-file-modtime) (nth 2 fass)))))
8712 (setq verilog-modi-cache-list nil
8713 fass nil))
8714 (cond (fass
8715 ;; Return data from cache hit
8716 (nth 3 fass))
8717 (t
8718 ;; Read from file
8719 ;; Clear then restore any highlighting to make emacs19 happy
8720 (let ((fontlocked (when (and (boundp 'font-lock-mode)
8721 font-lock-mode)
8722 (font-lock-mode 0)
8723 t))
8724 func-returns)
8725 (setq func-returns (funcall function))
8726 (when fontlocked (font-lock-mode t))
8727 ;; Cache for next time
8728 (setq verilog-modi-cache-list
8729 (cons (list (list modi function)
8730 (buffer-chars-modified-tick)
8731 (visited-file-modtime)
8732 func-returns)
8733 verilog-modi-cache-list))
8734 func-returns))))))
8736 (defun verilog-modi-cache-add (modi function element sig-list)
8737 "Add function return results to the module cache.
8738 Update MODI's cache for given FUNCTION so that the return ELEMENT of that
8739 function now contains the additional SIG-LIST parameters."
8740 (let (fass)
8741 (save-excursion
8742 (verilog-modi-goto modi)
8743 (if (setq fass (assoc (list modi function)
8744 verilog-modi-cache-list))
8745 (let ((func-returns (nth 3 fass)))
8746 (aset func-returns element
8747 (append sig-list (aref func-returns element))))))))
8749 (defmacro verilog-preserve-modi-cache (&rest body)
8750 "Execute the BODY forms, allowing cache preservation within BODY.
8751 This means that changes to the buffer will not result in the cache being
8752 flushed. If the changes affect the modsig state, they must call the
8753 modsig-cache-add-* function, else the results of later calls may be
8754 incorrect. Without this, changes are assumed to be adding/removing signals
8755 and invalidating the cache."
8756 `(let ((verilog-modi-cache-preserve-tick (buffer-chars-modified-tick))
8757 (verilog-modi-cache-preserve-buffer (current-buffer)))
8758 (progn ,@body)))
8761 (defun verilog-signals-matching-enum (in-list enum)
8762 "Return all signals in IN-LIST matching the given ENUM."
8763 (let (out-list)
8764 (while in-list
8765 (if (equal (verilog-sig-enum (car in-list)) enum)
8766 (setq out-list (cons (car in-list) out-list)))
8767 (setq in-list (cdr in-list)))
8768 ;; New scheme
8769 (let* ((enumvar (intern (concat "venum-" enum)))
8770 (enumlist (and (boundp enumvar) (eval enumvar))))
8771 (while enumlist
8772 (add-to-list 'out-list (list (car enumlist)))
8773 (setq enumlist (cdr enumlist))))
8774 (nreverse out-list)))
8776 (defun verilog-signals-matching-regexp (in-list regexp)
8777 "Return all signals in IN-LIST matching the given REGEXP, if non-nil."
8778 (if (or (not regexp) (equal regexp ""))
8779 in-list
8780 (let (out-list)
8781 (while in-list
8782 (if (string-match regexp (verilog-sig-name (car in-list)))
8783 (setq out-list (cons (car in-list) out-list)))
8784 (setq in-list (cdr in-list)))
8785 (nreverse out-list))))
8787 (defun verilog-signals-not-matching-regexp (in-list regexp)
8788 "Return all signals in IN-LIST not matching the given REGEXP, if non-nil."
8789 (if (or (not regexp) (equal regexp ""))
8790 in-list
8791 (let (out-list)
8792 (while in-list
8793 (if (not (string-match regexp (verilog-sig-name (car in-list))))
8794 (setq out-list (cons (car in-list) out-list)))
8795 (setq in-list (cdr in-list)))
8796 (nreverse out-list))))
8798 (defun verilog-signals-matching-dir-re (in-list decl-type regexp)
8799 "Return all signals in IN-LIST matching the given DECL-TYPE and REGEXP,
8800 if non-nil."
8801 (if (or (not regexp) (equal regexp ""))
8802 in-list
8803 (let (out-list to-match)
8804 (while in-list
8805 ;; Note verilog-insert-one-definition matches on this order
8806 (setq to-match (concat
8807 decl-type
8808 " " (verilog-sig-signed (car in-list))
8809 " " (verilog-sig-multidim (car in-list))
8810 (verilog-sig-bits (car in-list))))
8811 (if (string-match regexp to-match)
8812 (setq out-list (cons (car in-list) out-list)))
8813 (setq in-list (cdr in-list)))
8814 (nreverse out-list))))
8816 ;; Combined
8817 (defun verilog-decls-get-signals (decls)
8818 (append
8819 (verilog-decls-get-outputs decls)
8820 (verilog-decls-get-inouts decls)
8821 (verilog-decls-get-inputs decls)
8822 (verilog-decls-get-wires decls)
8823 (verilog-decls-get-regs decls)
8824 (verilog-decls-get-assigns decls)
8825 (verilog-decls-get-consts decls)
8826 (verilog-decls-get-gparams decls)))
8828 (defun verilog-decls-get-ports (decls)
8829 (append
8830 (verilog-decls-get-outputs decls)
8831 (verilog-decls-get-inouts decls)
8832 (verilog-decls-get-inputs decls)))
8834 (defsubst verilog-modi-cache-add-outputs (modi sig-list)
8835 (verilog-modi-cache-add modi 'verilog-read-decls 0 sig-list))
8836 (defsubst verilog-modi-cache-add-inouts (modi sig-list)
8837 (verilog-modi-cache-add modi 'verilog-read-decls 1 sig-list))
8838 (defsubst verilog-modi-cache-add-inputs (modi sig-list)
8839 (verilog-modi-cache-add modi 'verilog-read-decls 2 sig-list))
8840 (defsubst verilog-modi-cache-add-wires (modi sig-list)
8841 (verilog-modi-cache-add modi 'verilog-read-decls 3 sig-list))
8842 (defsubst verilog-modi-cache-add-regs (modi sig-list)
8843 (verilog-modi-cache-add modi 'verilog-read-decls 4 sig-list))
8845 (defun verilog-signals-from-signame (signame-list)
8846 "Return signals in standard form from SIGNAME-LIST, a simple list of signal names."
8847 (mapcar (function (lambda (name) (list name nil nil)))
8848 signame-list))
8849 \f
8850 ;;
8851 ;; Auto creation utilities
8852 ;;
8854 (defun verilog-auto-re-search-do (search-for func)
8855 "Search for the given auto text regexp SEARCH-FOR, and perform FUNC where it occurs."
8856 (goto-char (point-min))
8857 (while (verilog-re-search-forward search-for nil t)
8858 (funcall func)))
8860 (defun verilog-insert-one-definition (sig type indent-pt)
8861 "Print out a definition for SIG of the given TYPE,
8862 with appropriate INDENT-PT indentation."
8863 (indent-to indent-pt)
8864 ;; Note verilog-signals-matching-dir-re matches on this order
8865 (insert type)
8866 (when (verilog-sig-modport sig)
8867 (insert "." (verilog-sig-modport sig)))
8868 (when (verilog-sig-signed sig)
8869 (insert " " (verilog-sig-signed sig)))
8870 (when (verilog-sig-multidim sig)
8871 (insert " " (verilog-sig-multidim-string sig)))
8872 (when (verilog-sig-bits sig)
8873 (insert " " (verilog-sig-bits sig)))
8874 (indent-to (max 24 (+ indent-pt 16)))
8875 (unless (= (char-syntax (preceding-char)) ?\ )
8876 (insert " ")) ; Need space between "]name" if indent-to did nothing
8877 (insert (verilog-sig-name sig)))
8879 (defun verilog-insert-definition (sigs direction indent-pt v2k &optional dont-sort)
8880 "Print out a definition for a list of SIGS of the given DIRECTION,
8881 with appropriate INDENT-PT indentation. If V2K, use Verilog 2001 I/O
8882 format. Sort unless DONT-SORT. DIRECTION is normally wire/reg/output."
8883 (or dont-sort
8884 (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
8885 (while sigs
8886 (let ((sig (car sigs)))
8887 (verilog-insert-one-definition
8888 sig
8889 ;; Want "type x" or "output type x", not "wire type x"
8890 (cond ((verilog-sig-type sig)
8891 (concat
8892 (if (not (member direction '("wire" "interface")))
8893 (concat direction " "))
8894 (verilog-sig-type sig)))
8895 (t direction))
8896 indent-pt)
8897 (insert (if v2k "," ";"))
8898 (if (or (not (verilog-sig-comment sig))
8899 (equal "" (verilog-sig-comment sig)))
8901 (indent-to (max 48 (+ indent-pt 40)))
8903 (setq sigs (cdr sigs)))))
8905 (eval-when-compile
8906 (if (not (boundp 'indent-pt))
8907 (defvar indent-pt nil "Local used by insert-indent")))
8909 (defun verilog-insert-indent (&rest stuff)
8910 "Indent to position stored in local `indent-pt' variable, then insert STUFF.
8911 Presumes that any newlines end a list element."
8912 (let ((need-indent t))
8913 (while stuff
8914 (if need-indent (indent-to indent-pt))
8915 (setq need-indent nil)
8916 (verilog-insert (car stuff))
8918 stuff (cdr stuff)))))
8921 (defun verilog-repair-open-comma ()
8922 "Insert comma if previous argument is other than a open parenthesis or endif."
8923 ;; We can't just search backward for ) as it might be inside another expression.
8924 ;; Also want "`ifdef X input foo `endif" to just leave things to the human to deal with
8925 (save-excursion
8926 (verilog-backward-syntactic-ws)
8927 (when (and (not (save-excursion ;; Not beginning (, or existing ,
8928 (backward-char 1)
8929 (looking-at "[(,]")))
8930 (not (save-excursion ;; Not `endif, or user define
8931 (backward-char 1)
8932 (skip-chars-backward "[a-zA-Z0-9_`]")
8933 (looking-at "`"))))
8934 (insert ","))))
8936 (defun verilog-repair-close-comma ()
8937 "If point is at a comma followed by a close parenthesis, fix it.
8938 This repairs those mis-inserted by a AUTOARG."
8939 ;; It would be much nicer if Verilog allowed extra commas like Perl does!
8940 (save-excursion
8941 (verilog-forward-close-paren)
8942 (backward-char 1)
8943 (verilog-backward-syntactic-ws)
8944 (backward-char 1)
8945 (when (looking-at ",")
8946 (delete-char 1))))
8948 (defun verilog-get-list (start end)
8949 "Return the elements of a comma separated list between START and END."
8950 (interactive)
8951 (let ((my-list (list))
8952 my-string)
8953 (save-excursion
8954 (while (< (point) end)
8956 (setq my-string (verilog-string-remove-spaces (match-string 1)))
8957 (setq my-list (nconc my-list (list my-string) ))
8958 (goto-char (match-end 0))))
8959 my-list)))
8961 (defun verilog-make-width-expression (range-exp)
8962 "Return an expression calculating the length of a range [x:y] in RANGE-EXP."
8963 ;; strip off the []
8964 (cond ((not range-exp)
8965 "1")
8966 (t
8968 (setq range-exp (match-string 1 range-exp)))
8969 (cond ((not range-exp)
8970 "1")
8971 ;; [#:#] We can compute a numeric result
8973 range-exp)
8974 (int-to-string
8975 (1+ (abs (- (string-to-number (match-string 1 range-exp))
8976 (string-to-number (match-string 2 range-exp)))))))
8977 ;; [PARAM-1:0] can just return PARAM
8979 (match-string 1 range-exp))
8980 ;; [arbitrary] need math
8982 (concat "(1+(" (match-string 1 range-exp) ")"
8983 (if (equal "0" (match-string 2 range-exp))
8984 "" ;; Don't bother with -(0)
8985 (concat "-(" (match-string 2 range-exp) ")"))
8986 ")"))
8987 (t nil)))))
8988 ;;(verilog-make-width-expression "`A:`B")
8990 (defun verilog-simplify-range-expression (range-exp)
8991 "Return a simplified range expression with constants eliminated from RANGE-EXP."
8992 (let ((out range-exp)
8993 (last-pass ""))
8994 (while (not (equal last-pass out))
8995 (setq last-pass out)
8999 (setq out (replace-match
9000 (int-to-string (+ (string-to-number (match-string 1 out))
9001 (string-to-number (match-string 2 out))))
9002 nil nil out)))
9004 (setq out (replace-match
9005 (int-to-string (- (string-to-number (match-string 1 out))
9006 (string-to-number (match-string 2 out))))
9007 nil nil out))))
9008 out))
9009 ;;(verilog-simplify-range-expression "1")
9010 ;;(verilog-simplify-range-expression "(((16)+1)-3)")
9012 (defun verilog-typedef-name-p (variable-name)
9013 "Return true if the VARIABLE-NAME is a type definition."
9014 (when verilog-typedef-regexp
9015 (string-match verilog-typedef-regexp variable-name)))
9016 \f
9017 ;;
9018 ;; Auto deletion
9019 ;;
9021 (defun verilog-delete-autos-lined ()
9022 "Delete autos that occupy multiple lines, between begin and end comments."
9023 (let ((pt (point)))
9024 (forward-line 1)
9025 (when (and
9027 (search-forward "// End of automatic" nil t))
9028 ;; End exists
9029 (end-of-line)
9030 (delete-region pt (point))
9031 (forward-line 1))))
9033 (defun verilog-delete-empty-auto-pair ()
9034 "Delete begin/end auto pair at point, if empty."
9035 (forward-line 0)
9038 (delete-region (point) (save-excursion (forward-line 2) (point)))))
9040 (defun verilog-forward-close-paren ()
9041 "Find the close parenthesis that match the current point.
9042 Ignore other close parenthesis with matching open parens."
9043 (let ((parens 1))
9044 (while (> parens 0)
9045 (unless (verilog-re-search-forward-quick "[()]" nil t)
9046 (error "%s: Mismatching ()" (verilog-point-text)))
9047 (cond ((= (preceding-char) ?\( )
9048 (setq parens (1+ parens)))
9049 ((= (preceding-char) ?\) )
9050 (setq parens (1- parens)))))))
9052 (defun verilog-backward-open-paren ()
9053 "Find the open parenthesis that match the current point.
9054 Ignore other open parenthesis with matching close parens."
9055 (let ((parens 1))
9056 (while (> parens 0)
9057 (unless (verilog-re-search-backward-quick "[()]" nil t)
9058 (error "%s: Mismatching ()" (verilog-point-text)))
9059 (cond ((= (following-char) ?\) )
9060 (setq parens (1+ parens)))
9061 ((= (following-char) ?\( )
9062 (setq parens (1- parens)))))))
9064 (defun verilog-backward-open-bracket ()
9065 "Find the open bracket that match the current point.
9066 Ignore other open bracket with matching close bracket."
9067 (let ((parens 1))
9068 (while (> parens 0)
9069 (unless (verilog-re-search-backward-quick "[][]" nil t)
9070 (error "%s: Mismatching []" (verilog-point-text)))
9071 (cond ((= (following-char) ?\] )
9072 (setq parens (1+ parens)))
9073 ((= (following-char) ?\[ )
9074 (setq parens (1- parens)))))))
9076 (defun verilog-delete-to-paren ()
9077 "Delete the automatic inst/sense/arg created by autos.
9078 Deletion stops at the matching end parenthesis."
9079 (delete-region (point)
9080 (save-excursion
9081 (verilog-backward-open-paren)
9082 (forward-sexp 1) ;; Moves to paren that closes argdecl's
9083 (backward-char 1)
9084 (point))))
9086 (defun verilog-auto-star-safe ()
9087 "Return if a .* AUTOINST is safe to delete or expand.
9088 It was created by the AUTOS themselves, or by the user."
9089 (and verilog-auto-star-expand
9092 (defun verilog-delete-auto-star-all ()
9093 "Delete a .* AUTOINST, if it is safe."
9094 (when (verilog-auto-star-safe)
9095 (verilog-delete-to-paren)))
9097 (defun verilog-delete-auto-star-implicit ()
9098 "Delete all .* implicit connections created by `verilog-auto-star'.
9099 This function will be called automatically at save unless
9100 `verilog-auto-star-save' is set, any non-templated expanded pins will be
9101 removed."
9102 (interactive)
9103 (let (paren-pt indent have-close-paren)
9104 (save-excursion
9105 (goto-char (point-min))
9106 ;; We need to match these even outside of comments.
9107 ;; For reasonable performance, we don't check if inside comments, sorry.
9109 (setq paren-pt (point))
9110 (beginning-of-line)
9111 (setq have-close-paren
9112 (save-excursion
9113 (when (search-forward ");" paren-pt t)
9114 (setq indent (current-indentation))
9115 t)))
9116 (delete-region (point) (+ 1 paren-pt)) ; Nuke line incl CR
9117 (when have-close-paren
9118 ;; Delete extra commentary
9119 (save-excursion
9120 (while (progn
9121 (forward-line -1)
9123 (delete-region (match-beginning 0) (match-end 0))))
9124 ;; If it is simple, we can put the ); on the same line as the last text
9125 (let ((rtn-pt (point)))
9126 (save-excursion
9127 (while (progn (backward-char 1)
9129 (when (looking-at ",")
9130 (delete-region (+ 1 (point)) rtn-pt))))
9131 (when (bolp)
9132 (indent-to indent))
9134 ;; Still need to kill final comma - always is one as we put one after the .*
9135 (re-search-backward ",")
9136 (delete-char 1))))))
9138 (defun verilog-delete-auto ()
9142 The hooks `verilog-before-delete-auto-hook' and `verilog-delete-auto-hook' are
9143 called before and after this function, respectively."
9144 (interactive)
9145 (save-excursion
9146 (if (buffer-file-name)
9147 (find-file-noselect (buffer-file-name))) ;; To check we have latest version
9148 (verilog-save-no-change-functions
9149 (verilog-save-scan-cache
9150 ;; Allow user to customize
9151 (run-hooks 'verilog-before-delete-auto-hook)
9153 ;; Remove those that have multi-line insertions, possibly with parameters
9154 (verilog-auto-re-search-do
9156 (eval-when-compile
9157 (verilog-regexp-words
9158 `("AUTOASCIIENUM" "AUTOCONCATCOMMENT" "AUTODEFINEVALUE"
9159 "AUTOINOUT" "AUTOINOUTCOMP" "AUTOINOUTMODULE"
9160 "AUTOINPUT" "AUTOINSERTLISP" "AUTOOUTPUT" "AUTOOUTPUTEVERY"
9161 "AUTOREG" "AUTOREGINPUT" "AUTORESET" "AUTOTIEOFF"
9162 "AUTOUNUSED" "AUTOWIRE")))
9163 ;; Optional parens or quoted parameter or .* for (((...)))
9166 'verilog-delete-autos-lined)
9167 ;; Remove those that are in parenthesis
9168 (verilog-auto-re-search-do
9170 (eval-when-compile
9171 (verilog-regexp-words
9172 `("AS" "AUTOARG" "AUTOCONCATWIDTH" "AUTOINST" "AUTOINSTPARAM"
9173 "AUTOSENSE")))
9175 'verilog-delete-to-paren)
9176 ;; Do .* instantiations, but avoid removing any user pins by looking for our magic comments
9178 'verilog-delete-auto-star-all)
9179 ;; Remove template comments ... anywhere in case was pasted after AUTOINST removed
9180 (goto-char (point-min))
9182 (replace-match ""))
9184 ;; Final customize
9185 (run-hooks 'verilog-delete-auto-hook)))))
9186 \f
9187 ;;
9188 ;; Auto inject
9189 ;;
9191 (defun verilog-inject-auto ()
9192 "Examine legacy non-AUTO code and insert AUTOs in appropriate places.
9194 Any always @ blocks with sensitivity lists that match computed lists will
9195 be replaced with /*AS*/ comments.
9197 Any cells will get /*AUTOINST*/ added to the end of the pin list.
9198 Pins with have identical names will be deleted.
9200 Argument lists will not be deleted, /*AUTOARG*/ will only be inserted to
9201 support adding new ports. You may wish to delete older ports yourself.
9203 For example:
9205 module ExampInject (i, o);
9206 input i;
9207 input j;
9208 output o;
9209 always @ (i or j)
9210 o = i | j;
9211 InstModule instName
9212 (.foobar(baz),
9213 j(j));
9214 endmodule
9218 module ExampInject (i, o/*AUTOARG*/
9219 // Inputs
9220 j);
9221 input i;
9222 output o;
9223 always @ (/*AS*/i or j)
9224 o = i | j;
9225 InstModule instName
9226 (.foobar(baz),
9227 /*AUTOINST*/
9228 // Outputs
9229 j(j));
9230 endmodule"
9231 (interactive)
9232 (verilog-auto t))
9234 (defun verilog-inject-arg ()
9235 "Inject AUTOARG into new code. See `verilog-inject-auto'."
9236 ;; Presume one module per file.
9237 (save-excursion
9238 (goto-char (point-min))
9240 (let ((endmodp (save-excursion
9242 (point))))
9243 ;; See if there's already a comment .. inside a comment so not verilog-re-search
9245 (verilog-re-search-forward-quick ";" nil t)
9246 (backward-char 1)
9247 (verilog-backward-syntactic-ws)
9248 (backward-char 1) ; Moves to paren that closes argdecl's
9249 (when (looking-at ")")
9250 (verilog-insert "/*AUTOARG*/")))))))
9252 (defun verilog-inject-sense ()
9253 "Inject AUTOSENSE into new code. See `verilog-inject-auto'."
9254 (save-excursion
9255 (goto-char (point-min))
9257 (let* ((start-pt (point))
9258 (modi (verilog-modi-current))
9259 (moddecls (verilog-modi-get-decls modi))
9260 pre-sigs
9261 got-sigs)
9262 (backward-char 1)
9263 (forward-sexp 1)
9264 (backward-char 1) ;; End )
9266 (setq pre-sigs (verilog-signals-from-signame
9267 (verilog-read-signals start-pt (point)))
9268 got-sigs (verilog-auto-sense-sigs moddecls nil))
9269 (when (not (or (verilog-signals-not-in pre-sigs got-sigs) ; Both are equal?
9270 (verilog-signals-not-in got-sigs pre-sigs)))
9271 (delete-region start-pt (point))
9272 (verilog-insert "/*AS*/")))))))
9274 (defun verilog-inject-inst ()
9275 "Inject AUTOINST into new code. See `verilog-inject-auto'."
9276 (save-excursion
9277 (goto-char (point-min))
9278 ;; It's hard to distinguish modules; we'll instead search for pins.
9279 (while (verilog-re-search-forward-quick "\\.\\s *[a-zA-Z0-9`_\$]+\\s *(\\s *[a-zA-Z0-9`_\$]+\\s *)" nil t)
9280 (verilog-backward-open-paren) ;; Inst start
9281 (cond
9282 ((= (preceding-char) ?\#) ;; #(...) parameter section, not pin. Skip.
9283 (forward-char 1)
9284 (verilog-forward-close-paren)) ;; Parameters done
9285 (t
9286 (forward-char 1)
9287 (let ((indent-pt (+ (current-column)))
9288 (end-pt (save-excursion (verilog-forward-close-paren) (point))))
9290 (goto-char end-pt)) ;; Already there, continue search with next instance
9291 (t
9292 ;; Delete identical interconnect
9293 (let ((case-fold-search nil)) ;; So we don't convert upper-to-lower, etc
9294 (while (verilog-re-search-forward "\\.\\s *\\([a-zA-Z0-9`_\$]+\\)*\\s *(\\s *\\1\\s *)\\s *" end-pt t)
9295 (delete-region (match-beginning 0) (match-end 0))
9296 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))) ;; Keep it correct
9299 (delete-region (match-beginning 0) (match-end 0))
9300 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))))))
9301 (verilog-forward-close-paren)
9302 (backward-char 1)
9303 ;; Not verilog-re-search, as we don't want to strip comments
9305 (delete-region (match-beginning 0) (match-end 0)))
9307 (verilog-insert-indent "/*AUTOINST*/")))))))))
9308 \f
9309 ;;
9310 ;; Auto save
9311 ;;
9313 (defun verilog-auto-save-check ()
9314 "On saving see if we need auto update."
9315 (cond ((not verilog-auto-save-policy)) ; disabled
9316 ((not (save-excursion
9317 (save-match-data
9318 (let ((case-fold-search nil))
9319 (goto-char (point-min))
9320 (re-search-forward "AUTO" nil t))))))
9321 ((eq verilog-auto-save-policy 'force)
9322 (verilog-auto))
9323 ((not (buffer-modified-p)))
9324 ((eq verilog-auto-update-tick (buffer-chars-modified-tick))) ; up-to-date
9325 ((eq verilog-auto-save-policy 'detect)
9326 (verilog-auto))
9327 (t
9328 (when (yes-or-no-p "AUTO statements not recomputed, do it now? ")
9329 (verilog-auto))
9330 ;; Don't ask again if didn't update
9331 (set (make-local-variable 'verilog-auto-update-tick) (buffer-chars-modified-tick))))
9332 (when (not verilog-auto-star-save)
9333 (verilog-delete-auto-star-implicit))
9334 nil) ;; Always return nil -- we don't write the file ourselves
9336 (defun verilog-auto-read-locals ()
9337 "Return file local variable segment at bottom of file."
9338 (save-excursion
9339 (goto-char (point-max))
9340 (if (re-search-backward "Local Variables:" nil t)
9341 (buffer-substring-no-properties (point) (point-max))
9342 "")))
9344 (defun verilog-auto-reeval-locals (&optional force)
9345 "Read file local variable segment at bottom of file if it has changed.
9346 If FORCE, always reread it."
9347 (make-local-variable 'verilog-auto-last-file-locals)
9348 (let ((curlocal (verilog-auto-read-locals)))
9349 (when (or force (not (equal verilog-auto-last-file-locals curlocal)))
9350 (setq verilog-auto-last-file-locals curlocal)
9351 ;; Note this may cause this function to be recursively invoked,
9352 ;; because hack-local-variables may call (verilog-mode)
9353 ;; The above when statement will prevent it from recursing forever.
9354 (hack-local-variables)
9355 t)))
9356 \f
9357 ;;
9358 ;; Auto creation
9359 ;;
9361 (defun verilog-auto-arg-ports (sigs message indent-pt)
9362 "Print a list of ports for a AUTOINST.
9363 Takes SIGS list, adds MESSAGE to front and inserts each at INDENT-PT."
9364 (when sigs
9365 (when verilog-auto-arg-sort
9366 (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
9368 (indent-to indent-pt)
9369 (insert message)
9371 (let ((space ""))
9372 (indent-to indent-pt)
9373 (while sigs
9374 (cond ((> (+ 2 (current-column) (length (verilog-sig-name (car sigs)))) fill-column)
9376 (indent-to indent-pt))
9377 (t (insert space)))
9378 (insert (verilog-sig-name (car sigs)) ",")
9379 (setq sigs (cdr sigs)
9380 space " ")))))
9382 (defun verilog-auto-arg ()
9383 "Expand AUTOARG statements.
9384 Replace the argument declarations at the beginning of the
9385 module with ones automatically derived from input and output
9386 statements. This can be dangerous if the module is instantiated
9387 using position-based connections, so use only name-based when
9388 instantiating the resulting module. Long lines are split based
9391 Limitations:
9392 Concatenation and outputting partial busses is not supported.
9394 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
9396 For example:
9398 module ExampArg (/*AUTOARG*/);
9399 input i;
9400 output o;
9401 endmodule
9405 module ExampArg (/*AUTOARG*/
9406 // Outputs
9407 o,
9408 // Inputs
9409 i
9410 );
9411 input i;
9412 output o;
9413 endmodule
9415 The argument declarations may be printed in declaration order to best suit
9416 order based instantiations, or alphabetically, based on the
9417 `verilog-auto-arg-sort' variable.
9419 Any ports declared between the ( and /*AUTOARG*/ are presumed to be
9420 predeclared and are not redeclared by AUTOARG. AUTOARG will make a
9421 conservative guess on adding a comma for the first signal, if you have
9422 any ifdefs or complicated expressions before the AUTOARG you will need
9423 to choose the comma yourself.
9425 Avoid declaring ports manually, as it makes code harder to maintain."
9426 (save-excursion
9427 (let* ((modi (verilog-modi-current))
9428 (moddecls (verilog-modi-get-decls modi))
9429 (skip-pins (aref (verilog-read-arg-pins) 0)))
9430 (verilog-repair-open-comma)
9431 (verilog-auto-arg-ports (verilog-signals-not-in
9432 (verilog-decls-get-outputs moddecls)
9433 skip-pins)
9434 "// Outputs"
9435 verilog-indent-level-declaration)
9436 (verilog-auto-arg-ports (verilog-signals-not-in
9437 (verilog-decls-get-inouts moddecls)
9438 skip-pins)
9439 "// Inouts"
9440 verilog-indent-level-declaration)
9441 (verilog-auto-arg-ports (verilog-signals-not-in
9442 (verilog-decls-get-inputs moddecls)
9443 skip-pins)
9444 "// Inputs"
9445 verilog-indent-level-declaration)
9446 (verilog-repair-close-comma)
9447 (unless (eq (char-before) ?/ )
9449 (indent-to verilog-indent-level-declaration))))
9451 (defun verilog-auto-inst-port-map (port-st)
9452 nil)
9454 (defvar vl-cell-type nil "See `verilog-auto-inst'.") ; Prevent compile warning
9455 (defvar vl-cell-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
9456 (defvar vl-modport nil "See `verilog-auto-inst'.") ; Prevent compile warning
9457 (defvar vl-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
9458 (defvar vl-width nil "See `verilog-auto-inst'.") ; Prevent compile warning
9459 (defvar vl-dir nil "See `verilog-auto-inst'.") ; Prevent compile warning
9460 (defvar vl-bits nil "See `verilog-auto-inst'.") ; Prevent compile warning
9461 (defvar vl-mbits nil "See `verilog-auto-inst'.") ; Prevent compile warning
9463 (defun verilog-auto-inst-port (port-st indent-pt tpl-list tpl-num for-star par-values)
9464 "Print out a instantiation connection for this PORT-ST.
9465 Insert to INDENT-PT, use template TPL-LIST.
9466 @ are instantiation numbers, replaced with TPL-NUM.
9468 If FOR-STAR add comment it is a .* expansion.
9469 If PAR-VALUES replace final strings with these parameter values."
9470 (let* ((port (verilog-sig-name port-st))
9471 (tpl-ass (or (assoc port (car tpl-list))
9472 (verilog-auto-inst-port-map port-st)))
9473 ;; vl-* are documented for user use
9474 (vl-name (verilog-sig-name port-st))
9475 (vl-width (verilog-sig-width port-st))
9476 (vl-modport (verilog-sig-modport port-st))
9477 (vl-mbits (if (verilog-sig-multidim port-st)
9478 (verilog-sig-multidim-string port-st) ""))
9479 (vl-bits (if (or verilog-auto-inst-vector
9480 (not (assoc port vector-skip-list))
9481 (not (equal (verilog-sig-bits port-st)
9482 (verilog-sig-bits (assoc port vector-skip-list)))))
9483 (or (verilog-sig-bits port-st) "")
9484 ""))
9485 (case-fold-search nil)
9486 (check-values par-values)
9487 tpl-net)
9488 ;; Replace parameters in bit-width
9489 (when (and check-values
9490 (not (equal vl-bits "")))
9491 (while check-values
9492 (setq vl-bits (verilog-string-replace-matches
9494 (concat "(" (nth 1 (car check-values)) ")")
9495 t t vl-bits)
9496 check-values (cdr check-values)))
9497 (setq vl-bits (verilog-simplify-range-expression vl-bits))) ; Not in the loop for speed
9498 ;; Default net value if not found
9499 (setq tpl-net (concat port
9500 (if vl-modport (concat "." vl-modport) "")
9501 (if (verilog-sig-multidim port-st)
9502 (concat "/*" (verilog-sig-multidim-string port-st)
9503 vl-bits "*/")
9504 (concat vl-bits))))
9505 ;; Find template
9506 (cond (tpl-ass ; Template of exact port name
9507 (setq tpl-net (nth 1 tpl-ass)))
9508 ((nth 1 tpl-list) ; Wildcards in template, search them
9509 (let ((wildcards (nth 1 tpl-list)))
9510 (while wildcards
9511 (when (string-match (nth 0 (car wildcards)) port)
9512 (setq tpl-ass (car wildcards) ; so allow @ parsing
9513 tpl-net (replace-match (nth 1 (car wildcards))
9514 t nil port)))
9515 (setq wildcards (cdr wildcards))))))
9516 ;; Parse Templated variable
9517 (when tpl-ass
9518 ;; Evaluate @"(lispcode)"
9521 (setq tpl-net
9522 (concat
9523 (substring tpl-net 0 (match-beginning 0))
9524 (save-match-data
9525 (let* ((expr (match-string 1 tpl-net))
9526 (value
9527 (progn
9529 (setq expr (verilog-string-replace-matches "@" tpl-num nil nil expr))
9530 (prin1 (eval (car (read-from-string expr)))
9531 (lambda (ch) ())))))
9532 (if (numberp value) (setq value (number-to-string value)))
9533 value))
9534 (substring tpl-net (match-end 0))))))
9535 ;; Replace @ and [] magic variables in final output
9536 (setq tpl-net (verilog-string-replace-matches "@" tpl-num nil nil tpl-net))
9538 ;; Insert it
9539 (indent-to indent-pt)
9540 (insert "." port)
9541 (unless (and verilog-auto-inst-dot-name
9542 (equal port tpl-net))
9543 (indent-to verilog-auto-inst-column)
9544 (insert "(" tpl-net ")"))
9545 (insert ",")
9546 (cond (tpl-ass
9547 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
9548 verilog-auto-inst-column))
9549 (if verilog-auto-inst-template-numbers
9550 (verilog-insert " // Templated"
9551 " T" (int-to-string (nth 2 tpl-ass))
9552 " L" (int-to-string (nth 3 tpl-ass)))
9553 (verilog-insert " // Templated")))
9554 (for-star
9555 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
9556 verilog-auto-inst-column))
9557 (verilog-insert " // Implicit .\*"))) ;For some reason the . or * must be escaped...
9559 ;;(verilog-auto-inst-port (list "foo" "[5:0]") 10 (list (list "foo" "a@\"(% (+ @ 1) 4)\"a")) "3")
9563 (defun verilog-auto-inst-first ()
9565 ;; Do we need a trailing comma?
9566 ;; There maybe a ifdef or something similar before us. What a mess. Thus
9567 ;; to avoid trouble we only insert on preceding ) or *.
9568 ;; Insert first port on new line
9570 (save-excursion
9573 (forward-char 1)
9574 (insert ","))))
9576 (defun verilog-auto-star ()
9579 If `verilog-auto-star-expand' is set, .* pins are treated if they were
9580 AUTOINST statements, otherwise they are ignored. For safety, Verilog mode
9581 will also ignore any .* that are not last in your pin list (this prevents
9582 it from deleting pins following the .* when it expands the AUTOINST.)
9584 On writing your file, unless `verilog-auto-star-save' is set, any
9585 non-templated expanded pins will be removed. You may do this at any time
9588 If you are converting a module to use .* for the first time, you may wish
9591 See `verilog-auto-inst' for examples, templates, and more information."
9592 (when (verilog-auto-star-safe)
9593 (verilog-auto-inst)))
9595 (defun verilog-auto-inst ()
9597 Replace the pin connections to an instantiation or interface
9598 declaration with ones automatically derived from the module or
9599 interface header of the instantiated item.
9601 If `verilog-auto-star-expand' is set, also expand SystemVerilog .* ports,
9602 and delete them before saving unless `verilog-auto-star-save' is set.
9603 See `verilog-auto-star' for more information.
9605 Limitations:
9606 Module names must be resolvable to filenames by adding a
9607 `verilog-library-extensions', and being found in the same directory, or
9608 by changing the variable `verilog-library-flags' or
9609 `verilog-library-directories'. Macros `modname are translated through the
9610 vh-{name} Emacs variable, if that is not found, it just ignores the `.
9612 In templates you must have one signal per line, ending in a ), or ));,
9613 and have proper () nesting, including a final ); to end the template.
9615 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
9617 SystemVerilog multidimensional input/output has only experimental support.
9619 SystemVerilog .name syntax is used if `verilog-auto-inst-dot-name' is set.
9621 Parameters referenced by the instantiation will remain symbolic, unless
9622 `verilog-auto-inst-param-value' is set.
9624 Gate primitives (and/or) may have AUTOINST for the purpose of
9625 AUTOWIRE declarations, etc. Gates are the only case when
9626 position based connections are passed.
9628 For example, first take the submodule InstModule.v:
9630 module InstModule (o,i);
9631 output [31:0] o;
9632 input i;
9633 wire [31:0] o = {32{i}};
9634 endmodule
9636 This is then used in a upper level module:
9638 module ExampInst (o,i);
9639 output o;
9640 input i;
9641 InstModule instName
9642 (/*AUTOINST*/);
9643 endmodule
9647 module ExampInst (o,i);
9648 output o;
9649 input i;
9650 InstModule instName
9651 (/*AUTOINST*/
9652 // Outputs
9653 .ov (ov[31:0]),
9654 // Inputs
9655 .i (i));
9656 endmodule
9658 Where the list of inputs and outputs came from the inst module.
9659 \f
9660 Exceptions:
9662 Unless you are instantiating a module multiple times, or the module is
9663 something trivial like an adder, DO NOT CHANGE SIGNAL NAMES ACROSS HIERARCHY.
9664 It just makes for unmaintainable code. To sanitize signal names, try
9665 vrename from URL `http://www.veripool.org'.
9667 When you need to violate this suggestion there are two ways to list
9668 exceptions, placing them before the AUTOINST, or using templates.
9670 Any ports defined before the /*AUTOINST*/ are not included in the list of
9671 automatics. This is similar to making a template as described below, but
9672 is restricted to simple connections just like you normally make. Also note
9673 that any signals before the AUTOINST will only be picked up by AUTOWIRE if
9674 you have the appropriate // Input or // Output comment, and exactly the
9675 same line formatting as AUTOINST itself uses.
9677 InstModule instName
9678 (// Inputs
9679 .i (my_i_dont_mess_with_it),
9680 /*AUTOINST*/
9681 // Outputs
9682 .ov (ov[31:0]));
9684 \f
9685 Templates:
9687 For multiple instantiations based upon a single template, create a
9688 commented out template:
9690 /* InstModule AUTO_TEMPLATE (
9691 .sig3 (sigz[]),
9692 );
9693 */
9695 Templates go ABOVE the instantiation(s). When an instantiation is
9696 expanded `verilog-mode' simply searches up for the closest template.
9697 Thus you can have multiple templates for the same module, just alternate
9698 between the template for an instantiation and the instantiation itself.
9700 The module name must be the same as the name of the module in the
9702 words and capitalized. Only signals that must be different for each
9703 instantiation need to be listed.
9705 Inside a template, a [] in a connection name (with nothing else inside
9706 the brackets) will be replaced by the same bus subscript as it is being
9707 connected to, or the [] will be removed if it is a single bit signal.
9708 Generally it is a good idea to do this for all connections in a template,
9709 as then they will work for any width signal, and with AUTOWIRE. See
9710 PTL_BUS becoming PTL_BUSNEW below.
9712 If you have a complicated template, set `verilog-auto-inst-template-numbers'
9713 to see which regexps are matching. Don't leave that mode set after
9714 debugging is completed though, it will result in lots of extra differences
9715 and merge conflicts.
9717 For example:
9719 /* InstModule AUTO_TEMPLATE (
9720 .ptl_bus (ptl_busnew[]),
9721 );
9722 */
9723 InstModule ms2m (/*AUTOINST*/);
9727 InstModule ms2m (/*AUTOINST*/
9728 // Outputs
9729 .NotInTemplate (NotInTemplate),
9730 .ptl_bus (ptl_busnew[3:0]), // Templated
9731 ....
9732 \f
9733 @ Templates:
9735 It is common to instantiate a cell multiple times, so templates make it
9736 trivial to substitute part of the cell name into the connection name.
9739 .sig1 (sigx[@]),
9741 );
9742 */
9744 If no regular expression is provided immediately after the AUTO_TEMPLATE
9745 keyword, then the @ character in any connection names will be replaced
9746 with the instantiation number; the first digits found in the cell's
9747 instantiation name.
9749 If a regular expression is provided, the @ character will be replaced
9750 with the first \(\) grouping that matches against the cell name. Using a
9752 regexp is provided. If you use multiple layers of parenthesis,
9754 characters after test and before _, whereas
9756 match.
9758 For example:
9760 /* InstModule AUTO_TEMPLATE (
9761 .ptl_mapvalidx (ptl_mapvalid[@]),
9763 );
9764 */
9765 InstModule ms2m (/*AUTOINST*/);
9769 InstModule ms2m (/*AUTOINST*/
9770 // Outputs
9771 .ptl_mapvalidx (ptl_mapvalid[2]),
9772 .ptl_mapvalidp1x (ptl_mapvalid[3]));
9776 Alternatively, using a regular expression for @:
9779 .ptl_mapvalidx (@_ptl_mapvalid),
9780 .ptl_mapvalidp1x (ptl_mapvalid_@),
9781 );
9782 */
9783 InstModule ms2_FOO (/*AUTOINST*/);
9784 InstModule ms2_BAR (/*AUTOINST*/);
9788 InstModule ms2_FOO (/*AUTOINST*/
9789 // Outputs
9790 .ptl_mapvalidx (FOO_ptl_mapvalid),
9791 .ptl_mapvalidp1x (ptl_mapvalid_FOO));
9792 InstModule ms2_BAR (/*AUTOINST*/
9793 // Outputs
9794 .ptl_mapvalidx (BAR_ptl_mapvalid),
9795 .ptl_mapvalidp1x (ptl_mapvalid_BAR));
9797 \f
9798 Regexp Templates:
9800 A template entry of the form
9804 will apply an Emacs style regular expression search for any port beginning
9805 in pci_req followed by numbers and ending in _l and connecting that to
9806 the pci_req_jtag_[] net, with the bus subscript coming from what matches
9810 does the same thing. (Note a @ in the connection/replacement text is
9812 the above template:
9816 Here's another example to remove the _l, useful when naming conventions
9817 specify _ alone to mean active low. Note the use of [] to keep the bus
9818 subscript:
9821 \f
9822 Lisp Templates:
9824 First any regular expression template is expanded.
9827 quotes will be evaluated as a Lisp expression, with @ replaced by the
9828 instantiation number. The MAPVALIDP1X example above would put @+1 modulo
9829 4 into the brackets. Quote all double-quotes inside the expression with
9833 There are special variables defined that are useful in these
9834 Lisp functions:
9836 vl-name Name portion of the input/output port.
9837 vl-bits Bus bits portion of the input/output port ('[2:0]').
9838 vl-mbits Multidimensional array bits for port ('[2:0][3:0]').
9839 vl-width Width of the input/output port ('3' for [2:0]).
9840 May be a (...) expression if bits isn't a constant.
9841 vl-dir Direction of the pin input/output/inout/interface.
9842 vl-modport The modport, if an interface with a modport.
9843 vl-cell-type Module name/type of the cell ('InstModule').
9844 vl-cell-name Instance name of the cell ('instName').
9846 Normal Lisp variables may be used in expressions. See
9847 `verilog-read-defines' which can set vh-{definename} variables for use
9848 here. Also, any comments of the form:
9850 /*AUTO_LISP(setq foo 1)*/
9852 will evaluate any Lisp expression inside the parenthesis between the
9853 beginning of the buffer and the point of the AUTOINST. This allows
9854 functions to be defined or variables to be changed between instantiations.
9855 (See also `verilog-auto-insert-lisp' if you want the output from your
9856 lisp function to be inserted.)
9858 Note that when using lisp expressions errors may occur when @ is not a
9859 number; you may need to use the standard Emacs Lisp functions
9860 `number-to-string' and `string-to-number'.
9862 After the evaluation is completed, @ substitution and [] substitution
9863 occur.
9866 `http://www.veripool.org'."
9867 (save-excursion
9868 ;; Find beginning
9869 (let* ((pt (point))
9871 (indent-pt (save-excursion (verilog-backward-open-paren)
9872 (1+ (current-column))))
9873 (verilog-auto-inst-column (max verilog-auto-inst-column
9874 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
9875 (modi (verilog-modi-current))
9876 (moddecls (verilog-modi-get-decls modi))
9877 (vector-skip-list (unless verilog-auto-inst-vector
9878 (verilog-decls-get-signals moddecls)))
9879 submod submodi submoddecls
9880 inst skip-pins tpl-list tpl-num did-first par-values)
9882 ;; Find module name that is instantiated
9883 (setq submod (verilog-read-inst-module)
9884 inst (verilog-read-inst-name)
9885 vl-cell-type submod
9886 vl-cell-name inst
9887 skip-pins (aref (verilog-read-inst-pins) 0))
9889 ;; Parse any AUTO_LISP() before here
9890 (verilog-read-auto-lisp (point-min) pt)
9892 ;; Read parameters (after AUTO_LISP)
9893 (setq par-values (and verilog-auto-inst-param-value
9894 (verilog-read-inst-param-value)))
9896 ;; Lookup position, etc of submodule
9897 ;; Note this may raise an error
9898 (when (and (not (member submod verilog-gate-keywords))
9899 (setq submodi (verilog-modi-lookup submod t)))
9900 (setq submoddecls (verilog-modi-get-decls submodi))
9901 ;; If there's a number in the instantiation, it may be a argument to the
9902 ;; automatic variable instantiation program.
9903 (let* ((tpl-info (verilog-read-auto-template submod))
9904 (tpl-regexp (aref tpl-info 0)))
9905 (setq tpl-num (if (string-match tpl-regexp inst)
9906 (match-string 1 inst)
9907 "")
9908 tpl-list (aref tpl-info 1)))
9909 ;; Find submodule's signals and dump
9910 (let ((sig-list (and (equal (verilog-modi-get-type submodi) "interface")
9911 (verilog-signals-not-in
9912 (append (verilog-decls-get-wires submoddecls)
9913 (verilog-decls-get-regs submoddecls))
9914 skip-pins)))
9915 (vl-dir "interfaced"))
9916 (when sig-list
9917 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
9918 ;; Note these are searched for in verilog-read-sub-decls.
9920 (mapc (lambda (port)
9921 (verilog-auto-inst-port port indent-pt
9922 tpl-list tpl-num for-star par-values))
9923 sig-list)))
9924 (let ((sig-list (verilog-signals-not-in
9925 (verilog-decls-get-interfaces submoddecls)
9926 skip-pins))
9927 (vl-dir "interface"))
9928 (when sig-list
9929 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
9930 ;; Note these are searched for in verilog-read-sub-decls.
9932 (mapc (lambda (port)
9933 (verilog-auto-inst-port port indent-pt
9934 tpl-list tpl-num for-star par-values))
9935 sig-list)))
9936 (let ((sig-list (verilog-signals-not-in
9937 (verilog-decls-get-outputs submoddecls)
9938 skip-pins))
9939 (vl-dir "output"))
9940 (when sig-list
9941 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
9943 (mapc (lambda (port)
9944 (verilog-auto-inst-port port indent-pt
9945 tpl-list tpl-num for-star par-values))
9946 sig-list)))
9947 (let ((sig-list (verilog-signals-not-in
9948 (verilog-decls-get-inouts submoddecls)
9949 skip-pins))
9950 (vl-dir "inout"))
9951 (when sig-list
9952 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
9954 (mapc (lambda (port)
9955 (verilog-auto-inst-port port indent-pt
9956 tpl-list tpl-num for-star par-values))
9957 sig-list)))
9958 (let ((sig-list (verilog-signals-not-in
9959 (verilog-decls-get-inputs submoddecls)
9960 skip-pins))
9961 (vl-dir "input"))
9962 (when sig-list
9963 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
9965 (mapc (lambda (port)
9966 (verilog-auto-inst-port port indent-pt
9967 tpl-list tpl-num for-star par-values))
9968 sig-list)))
9969 ;; Kill extra semi
9970 (save-excursion
9971 (cond (did-first
9972 (re-search-backward "," pt t)
9973 (delete-char 1)
9974 (insert ");")
9976 (delete-char -1)
9977 (if (search-forward ")" nil t) ;; From user, moved up a line
9978 (delete-char -1))
9979 (if (search-forward ";" nil t) ;; Don't error if user had syntax error and forgot it
9980 (delete-char -1)))))))))
9982 (defun verilog-auto-inst-param ()
9984 Replace the parameter connections to an instantiation with ones
9985 automatically derived from the module header of the instantiated netlist.
9988 output.
9990 For example, first take the submodule InstModule.v:
9992 module InstModule (o,i);
9993 parameter PAR;
9994 endmodule
9996 This is then used in a upper level module:
9998 module ExampInst (o,i);
9999 parameter PAR;
10000 InstModule #(/*AUTOINSTPARAM*/)
10001 instName (/*AUTOINST*/);
10002 endmodule
10006 module ExampInst (o,i);
10007 output o;
10008 input i;
10009 InstModule #(/*AUTOINSTPARAM*/
10010 // Parameters
10011 .PAR (PAR));
10012 instName (/*AUTOINST*/);
10013 endmodule
10015 Where the list of parameter connections come from the inst module.
10016 \f
10017 Templates:
10019 You can customize the parameter connections using AUTO_TEMPLATEs,
10021 (save-excursion
10022 ;; Find beginning
10023 (let* ((pt (point))
10024 (indent-pt (save-excursion (verilog-backward-open-paren)
10025 (1+ (current-column))))
10026 (verilog-auto-inst-column (max verilog-auto-inst-column
10027 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
10028 (modi (verilog-modi-current))
10029 (moddecls (verilog-modi-get-decls modi))
10030 (vector-skip-list (unless verilog-auto-inst-vector
10031 (verilog-decls-get-signals moddecls)))
10032 submod submodi submoddecls
10033 inst skip-pins tpl-list tpl-num did-first)
10034 ;; Find module name that is instantiated
10035 (setq submod (save-excursion
10036 ;; Get to the point where AUTOINST normally is to read the module
10037 (verilog-re-search-forward-quick "[(;]" nil nil)
10038 (verilog-read-inst-module))
10039 inst (save-excursion
10040 ;; Get to the point where AUTOINST normally is to read the module
10041 (verilog-re-search-forward-quick "[(;]" nil nil)
10042 (verilog-read-inst-name))
10043 vl-cell-type submod
10044 vl-cell-name inst
10045 skip-pins (aref (verilog-read-inst-pins) 0))
10047 ;; Parse any AUTO_LISP() before here
10048 (verilog-read-auto-lisp (point-min) pt)
10050 ;; Lookup position, etc of submodule
10051 ;; Note this may raise an error
10052 (when (setq submodi (verilog-modi-lookup submod t))
10053 (setq submoddecls (verilog-modi-get-decls submodi))
10054 ;; If there's a number in the instantiation, it may be a argument to the
10055 ;; automatic variable instantiation program.
10056 (let* ((tpl-info (verilog-read-auto-template submod))
10057 (tpl-regexp (aref tpl-info 0)))
10058 (setq tpl-num (if (string-match tpl-regexp inst)
10059 (match-string 1 inst)
10060 "")
10061 tpl-list (aref tpl-info 1)))
10062 ;; Find submodule's signals and dump
10063 (let ((sig-list (verilog-signals-not-in
10064 (verilog-decls-get-gparams submoddecls)
10065 skip-pins))
10066 (vl-dir "parameter"))
10067 (when sig-list
10068 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
10069 ;; Note these are searched for in verilog-read-sub-decls.
10071 (mapc (lambda (port)
10072 (verilog-auto-inst-port port indent-pt
10073 tpl-list tpl-num nil nil))
10074 sig-list)))
10075 ;; Kill extra semi
10076 (save-excursion
10077 (cond (did-first
10078 (re-search-backward "," pt t)
10079 (delete-char 1)
10080 (insert ")")
10082 (delete-char -1)
10083 (if (search-forward ")" nil t) ;; From user, moved up a line
10084 (delete-char -1)))))))))
10086 (defun verilog-auto-reg ()
10088 Make reg statements for any output that isn't already declared,
10089 and isn't a wire output from a block.
10091 Limitations:
10092 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
10094 This does NOT work on memories, declare those yourself.
10096 An example:
10098 module ExampReg (o,i);
10099 output o;
10100 input i;
10101 /*AUTOREG*/
10102 always o = i;
10103 endmodule
10107 module ExampReg (o,i);
10108 output o;
10109 input i;
10110 /*AUTOREG*/
10111 // Beginning of automatic regs (for this module's undeclared outputs)
10112 reg o;
10113 // End of automatics
10114 always o = i;
10115 endmodule"
10116 (save-excursion
10117 ;; Point must be at insertion point.
10118 (let* ((indent-pt (current-indentation))
10119 (modi (verilog-modi-current))
10120 (moddecls (verilog-modi-get-decls modi))
10121 (modsubdecls (verilog-modi-get-sub-decls modi))
10122 (sig-list (verilog-signals-not-in
10123 (verilog-decls-get-outputs moddecls)
10124 (append (verilog-decls-get-wires moddecls)
10125 (verilog-decls-get-regs moddecls)
10126 (verilog-decls-get-assigns moddecls)
10127 (verilog-decls-get-consts moddecls)
10128 (verilog-decls-get-gparams moddecls)
10129 (verilog-subdecls-get-interfaced modsubdecls)
10130 (verilog-subdecls-get-outputs modsubdecls)
10131 (verilog-subdecls-get-inouts modsubdecls)))))
10132 (forward-line 1)
10133 (when sig-list
10134 (verilog-insert-indent "// Beginning of automatic regs (for this module's undeclared outputs)\n")
10135 (verilog-insert-definition sig-list "reg" indent-pt nil)
10136 (verilog-modi-cache-add-regs modi sig-list)
10139 (defun verilog-auto-reg-input ()
10141 Make reg statements instantiation inputs that aren't already declared.
10142 This is useful for making a top level shell for testing the module that is
10143 to be instantiated.
10145 Limitations:
10146 This ONLY detects inputs of AUTOINSTants (see `verilog-read-sub-decls').
10148 This does NOT work on memories, declare those yourself.
10150 An example (see `verilog-auto-inst' for what else is going on here):
10152 module ExampRegInput (o,i);
10153 output o;
10154 input i;
10155 /*AUTOREGINPUT*/
10156 InstModule instName
10157 (/*AUTOINST*/);
10158 endmodule
10162 module ExampRegInput (o,i);
10163 output o;
10164 input i;
10165 /*AUTOREGINPUT*/
10166 // Beginning of automatic reg inputs (for undeclared ...
10167 reg [31:0] iv; // From inst of inst.v
10168 // End of automatics
10169 InstModule instName
10170 (/*AUTOINST*/
10171 // Outputs
10172 .o (o[31:0]),
10173 // Inputs
10174 .iv (iv));
10175 endmodule"
10176 (save-excursion
10177 ;; Point must be at insertion point.
10178 (let* ((indent-pt (current-indentation))
10179 (modi (verilog-modi-current))
10180 (moddecls (verilog-modi-get-decls modi))
10181 (modsubdecls (verilog-modi-get-sub-decls modi))
10182 (sig-list (verilog-signals-combine-bus
10183 (verilog-signals-not-in
10184 (append (verilog-subdecls-get-inputs modsubdecls)
10185 (verilog-subdecls-get-inouts modsubdecls))
10186 (verilog-decls-get-signals moddecls)))))
10187 (forward-line 1)
10188 (when sig-list
10189 (verilog-insert-indent "// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)\n")
10190 (verilog-insert-definition sig-list "reg" indent-pt nil)
10191 (verilog-modi-cache-add-regs modi sig-list)
10194 (defun verilog-auto-wire ()
10196 Make wire statements for instantiations outputs that aren't
10197 already declared.
10199 Limitations:
10200 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'),
10201 and all busses must have widths, such as those from AUTOINST, or using []
10202 in AUTO_TEMPLATEs.
10204 This does NOT work on memories or SystemVerilog .name connections,
10205 declare those yourself.
10208 determine how to bus together. This occurs when you have ports with
10209 non-numeric or non-sequential bus subscripts. If Verilog mode
10210 mis-guessed, you'll have to declare them yourself.
10212 An example (see `verilog-auto-inst' for what else is going on here):
10214 module ExampWire (o,i);
10215 output o;
10216 input i;
10217 /*AUTOWIRE*/
10218 InstModule instName
10219 (/*AUTOINST*/);
10220 endmodule
10224 module ExampWire (o,i);
10225 output o;
10226 input i;
10227 /*AUTOWIRE*/
10228 // Beginning of automatic wires
10229 wire [31:0] ov; // From inst of inst.v
10230 // End of automatics
10231 InstModule instName
10232 (/*AUTOINST*/
10233 // Outputs
10234 .ov (ov[31:0]),
10235 // Inputs
10236 .i (i));
10237 wire o = | ov;
10238 endmodule"
10239 (save-excursion
10240 ;; Point must be at insertion point.
10241 (let* ((indent-pt (current-indentation))
10242 (modi (verilog-modi-current))
10243 (moddecls (verilog-modi-get-decls modi))
10244 (modsubdecls (verilog-modi-get-sub-decls modi))
10245 (sig-list (verilog-signals-combine-bus
10246 (verilog-signals-not-in
10247 (append (verilog-subdecls-get-outputs modsubdecls)
10248 (verilog-subdecls-get-inouts modsubdecls))
10249 (verilog-decls-get-signals moddecls)))))
10250 (forward-line 1)
10251 (when sig-list
10252 (verilog-insert-indent "// Beginning of automatic wires (for undeclared instantiated-module outputs)\n")
10253 (verilog-insert-definition sig-list "wire" indent-pt nil)
10254 (verilog-modi-cache-add-wires modi sig-list)
10256 (when nil ;; Too slow on huge modules, plus makes everyone's module change
10257 (beginning-of-line)
10258 (setq pnt (point))
10259 (verilog-pretty-declarations quiet)
10260 (goto-char pnt)
10261 (verilog-pretty-expr t "//"))))))
10263 (defun verilog-auto-output (&optional with-params)
10265 Make output statements for any output signal from an /*AUTOINST*/ that
10266 isn't a input to another AUTOINST. This is useful for modules which
10267 only instantiate other modules.
10269 Limitations:
10270 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
10272 If placed inside the parenthesis of a module declaration, it creates
10273 Verilog 2001 style, else uses Verilog 1995 style.
10275 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
10276 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
10278 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
10280 Signals matching `verilog-auto-output-ignore-regexp' are not included.
10282 An example (see `verilog-auto-inst' for what else is going on here):
10284 module ExampOutput (ov,i);
10285 input i;
10286 /*AUTOOUTPUT*/
10287 InstModule instName
10288 (/*AUTOINST*/);
10289 endmodule
10293 module ExampOutput (ov,i);
10294 input i;
10295 /*AUTOOUTPUT*/
10296 // Beginning of automatic outputs (from unused autoinst outputs)
10297 output [31:0] ov; // From inst of inst.v
10298 // End of automatics
10299 InstModule instName
10300 (/*AUTOINST*/
10301 // Outputs
10302 .ov (ov[31:0]),
10303 // Inputs
10304 .i (i));
10305 endmodule
10307 You may also provide an optional regular expression, in which case only
10308 signals matching the regular expression will be included. For example the
10309 same expansion will result from only extracting outputs starting with ov:
10312 (save-excursion
10313 ;; Point must be at insertion point.
10314 (let* ((indent-pt (current-indentation))
10315 (regexp (and with-params
10316 (nth 0 (verilog-read-auto-params 1))))
10317 (v2k (verilog-in-paren))
10318 (modi (verilog-modi-current))
10319 (moddecls (verilog-modi-get-decls modi))
10320 (modsubdecls (verilog-modi-get-sub-decls modi))
10321 (sig-list (verilog-signals-not-in
10322 (verilog-subdecls-get-outputs modsubdecls)
10323 (append (verilog-decls-get-outputs moddecls)
10324 (verilog-decls-get-inouts moddecls)
10325 (verilog-subdecls-get-inputs modsubdecls)
10326 (verilog-subdecls-get-inouts modsubdecls)))))
10327 (when regexp
10328 (setq sig-list (verilog-signals-matching-regexp
10329 sig-list regexp)))
10330 (setq sig-list (verilog-signals-not-matching-regexp
10331 sig-list verilog-auto-output-ignore-regexp))
10332 (forward-line 1)
10333 (when v2k (verilog-repair-open-comma))
10334 (when sig-list
10336 (verilog-insert-definition sig-list "output" indent-pt v2k)
10337 (verilog-modi-cache-add-outputs modi sig-list)
10339 (when v2k (verilog-repair-close-comma)))))
10341 (defun verilog-auto-output-every ()
10343 Make output statements for any signals that aren't primary inputs or
10344 outputs already. This makes every signal in the design a output. This is
10345 useful to get Synopsys to preserve every signal in the design, since it
10346 won't optimize away the outputs.
10348 An example:
10350 module ExampOutputEvery (o,i,tempa,tempb);
10351 output o;
10352 input i;
10353 /*AUTOOUTPUTEVERY*/
10354 wire tempa = i;
10355 wire tempb = tempa;
10356 wire o = tempb;
10357 endmodule
10361 module ExampOutputEvery (o,i,tempa,tempb);
10362 output o;
10363 input i;
10364 /*AUTOOUTPUTEVERY*/
10365 // Beginning of automatic outputs (every signal)
10366 output tempb;
10367 output tempa;
10368 // End of automatics
10369 wire tempa = i;
10370 wire tempb = tempa;
10371 wire o = tempb;
10372 endmodule"
10373 (save-excursion
10374 ;;Point must be at insertion point
10375 (let* ((indent-pt (current-indentation))
10376 (v2k (verilog-in-paren))
10377 (modi (verilog-modi-current))
10378 (moddecls (verilog-modi-get-decls modi))
10379 (sig-list (verilog-signals-combine-bus
10380 (verilog-signals-not-in
10381 (verilog-decls-get-signals moddecls)
10382 (verilog-decls-get-ports moddecls)))))
10383 (forward-line 1)
10384 (when v2k (verilog-repair-open-comma))
10385 (when sig-list
10387 (verilog-insert-definition sig-list "output" indent-pt v2k)
10388 (verilog-modi-cache-add-outputs modi sig-list)
10390 (when v2k (verilog-repair-close-comma)))))
10392 (defun verilog-auto-input (&optional with-params)
10394 Make input statements for any input signal into an /*AUTOINST*/ that
10395 isn't declared elsewhere inside the module. This is useful for modules which
10396 only instantiate other modules.
10398 Limitations:
10399 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
10401 If placed inside the parenthesis of a module declaration, it creates
10402 Verilog 2001 style, else uses Verilog 1995 style.
10404 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
10405 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
10407 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
10409 Signals matching `verilog-auto-input-ignore-regexp' are not included.
10411 An example (see `verilog-auto-inst' for what else is going on here):
10413 module ExampInput (ov,i);
10414 output [31:0] ov;
10415 /*AUTOINPUT*/
10416 InstModule instName
10417 (/*AUTOINST*/);
10418 endmodule
10422 module ExampInput (ov,i);
10423 output [31:0] ov;
10424 /*AUTOINPUT*/
10425 // Beginning of automatic inputs (from unused autoinst inputs)
10426 input i; // From inst of inst.v
10427 // End of automatics
10428 InstModule instName
10429 (/*AUTOINST*/
10430 // Outputs
10431 .ov (ov[31:0]),
10432 // Inputs
10433 .i (i));
10434 endmodule
10436 You may also provide an optional regular expression, in which case only
10437 signals matching the regular expression will be included. For example the
10438 same expansion will result from only extracting inputs starting with i:
10441 (save-excursion
10442 (let* ((indent-pt (current-indentation))
10443 (regexp (and with-params
10444 (nth 0 (verilog-read-auto-params 1))))
10445 (v2k (verilog-in-paren))
10446 (modi (verilog-modi-current))
10447 (moddecls (verilog-modi-get-decls modi))
10448 (modsubdecls (verilog-modi-get-sub-decls modi))
10449 (sig-list (verilog-signals-not-in
10450 (verilog-subdecls-get-inputs modsubdecls)
10451 (append (verilog-decls-get-inputs moddecls)
10452 (verilog-decls-get-inouts moddecls)
10453 (verilog-decls-get-wires moddecls)
10454 (verilog-decls-get-regs moddecls)
10455 (verilog-decls-get-consts moddecls)
10456 (verilog-decls-get-gparams moddecls)
10457 (verilog-subdecls-get-interfaced modsubdecls)
10458 (verilog-subdecls-get-outputs modsubdecls)
10459 (verilog-subdecls-get-inouts modsubdecls)))))
10460 (when regexp
10461 (setq sig-list (verilog-signals-matching-regexp
10462 sig-list regexp)))
10463 (setq sig-list (verilog-signals-not-matching-regexp
10464 sig-list verilog-auto-input-ignore-regexp))
10465 (forward-line 1)
10466 (when v2k (verilog-repair-open-comma))
10467 (when sig-list
10469 (verilog-insert-definition sig-list "input" indent-pt v2k)
10470 (verilog-modi-cache-add-inputs modi sig-list)
10472 (when v2k (verilog-repair-close-comma)))))
10474 (defun verilog-auto-inout (&optional with-params)
10476 Make inout statements for any inout signal in an /*AUTOINST*/ that
10477 isn't declared elsewhere inside the module.
10479 Limitations:
10480 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
10482 If placed inside the parenthesis of a module declaration, it creates
10483 Verilog 2001 style, else uses Verilog 1995 style.
10485 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
10486 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
10488 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
10490 Signals matching `verilog-auto-inout-ignore-regexp' are not included.
10492 An example (see `verilog-auto-inst' for what else is going on here):
10494 module ExampInout (ov,i);
10495 input i;
10496 /*AUTOINOUT*/
10497 InstModule instName
10498 (/*AUTOINST*/);
10499 endmodule
10503 module ExampInout (ov,i);
10504 input i;
10505 /*AUTOINOUT*/
10506 // Beginning of automatic inouts (from unused autoinst inouts)
10507 inout [31:0] ov; // From inst of inst.v
10508 // End of automatics
10509 InstModule instName
10510 (/*AUTOINST*/
10511 // Inouts
10512 .ov (ov[31:0]),
10513 // Inputs
10514 .i (i));
10515 endmodule
10517 You may also provide an optional regular expression, in which case only
10518 signals matching the regular expression will be included. For example the
10519 same expansion will result from only extracting inouts starting with i:
10522 (save-excursion
10523 ;; Point must be at insertion point.
10524 (let* ((indent-pt (current-indentation))
10525 (regexp (and with-params
10526 (nth 0 (verilog-read-auto-params 1))))
10527 (v2k (verilog-in-paren))
10528 (modi (verilog-modi-current))
10529 (moddecls (verilog-modi-get-decls modi))
10530 (modsubdecls (verilog-modi-get-sub-decls modi))
10531 (sig-list (verilog-signals-not-in
10532 (verilog-subdecls-get-inouts modsubdecls)
10533 (append (verilog-decls-get-outputs moddecls)
10534 (verilog-decls-get-inouts moddecls)
10535 (verilog-decls-get-inputs moddecls)
10536 (verilog-subdecls-get-inputs modsubdecls)
10537 (verilog-subdecls-get-outputs modsubdecls)))))
10538 (when regexp
10539 (setq sig-list (verilog-signals-matching-regexp
10540 sig-list regexp)))
10541 (setq sig-list (verilog-signals-not-matching-regexp
10542 sig-list verilog-auto-inout-ignore-regexp))
10543 (forward-line 1)
10544 (when v2k (verilog-repair-open-comma))
10545 (when sig-list
10547 (verilog-insert-definition sig-list "inout" indent-pt v2k)
10548 (verilog-modi-cache-add-inouts modi sig-list)
10550 (when v2k (verilog-repair-close-comma)))))
10552 (defun verilog-auto-inout-module (&optional complement)
10554 Take input/output/inout statements from the specified module and insert
10555 into the current module. This is useful for making null templates and
10556 shell modules which need to have identical I/O with another module.
10557 Any I/O which are already defined in this module will not be redefined.
10558 For the complement of this function, see `verilog-auto-inout-comp'.
10560 Limitations:
10561 If placed inside the parenthesis of a module declaration, it creates
10562 Verilog 2001 style, else uses Verilog 1995 style.
10564 Concatenation and outputting partial busses is not supported.
10566 Module names must be resolvable to filenames. See `verilog-auto-inst'.
10568 Signals are not inserted in the same order as in the original module,
10569 though they will appear to be in the same order to a AUTOINST
10570 instantiating either module.
10572 An example:
10574 module ExampShell (/*AUTOARG*/);
10576 endmodule
10578 module ExampMain (i,o,io);
10579 input i;
10580 output o;
10581 inout io;
10582 endmodule
10586 module ExampShell (/*AUTOARG*/i,o,io);
10588 // Beginning of automatic in/out/inouts (from specific module)
10589 output o;
10590 inout io;
10591 input i;
10592 // End of automatics
10593 endmodule
10595 You may also provide an optional regular expression, in which case only
10596 signals matching the regular expression will be included. For example the
10597 same expansion will result from only extracting signals starting with i:
10601 You may also provide an optional second regular expression, in
10602 which case only signals which have that pin direction and data
10603 type will be included. This matches against everything before
10604 the signal name in the declaration, for example against
10607 probably want to skip spaces in your regexp.
10610 against the previous example's module:
10613 (save-excursion
10614 (let* ((params (verilog-read-auto-params 1 3))
10615 (submod (nth 0 params))
10616 (regexp (nth 1 params))
10617 (direction-re (nth 2 params))
10618 submodi)
10619 ;; Lookup position, etc of co-module
10620 ;; Note this may raise an error
10621 (when (setq submodi (verilog-modi-lookup submod t))
10622 (let* ((indent-pt (current-indentation))
10623 (v2k (verilog-in-paren))
10624 (modi (verilog-modi-current))
10625 (moddecls (verilog-modi-get-decls modi))
10626 (submoddecls (verilog-modi-get-decls submodi))
10627 (sig-list-i (verilog-signals-not-in
10628 (if complement
10629 (verilog-decls-get-outputs submoddecls)
10630 (verilog-decls-get-inputs submoddecls))
10631 (append (verilog-decls-get-inputs moddecls))))
10632 (sig-list-o (verilog-signals-not-in
10633 (if complement
10634 (verilog-decls-get-inputs submoddecls)
10635 (verilog-decls-get-outputs submoddecls))
10636 (append (verilog-decls-get-outputs moddecls))))
10637 (sig-list-io (verilog-signals-not-in
10638 (verilog-decls-get-inouts submoddecls)
10639 (append (verilog-decls-get-inouts moddecls))))
10640 (sig-list-if (verilog-signals-not-in
10641 (verilog-decls-get-interfaces submoddecls)
10642 (append (verilog-decls-get-interfaces moddecls)))))
10643 (forward-line 1)
10644 (setq sig-list-i (verilog-signals-matching-dir-re
10645 (verilog-signals-matching-regexp sig-list-i regexp)
10646 "input" direction-re)
10647 sig-list-o (verilog-signals-matching-dir-re
10648 (verilog-signals-matching-regexp sig-list-o regexp)
10649 "output" direction-re)
10650 sig-list-io (verilog-signals-matching-dir-re
10651 (verilog-signals-matching-regexp sig-list-io regexp)
10652 "inout" direction-re)
10653 sig-list-if (verilog-signals-matching-dir-re
10654 (verilog-signals-matching-regexp sig-list-if regexp)
10655 "interface" direction-re))
10656 (when v2k (verilog-repair-open-comma))
10657 (when (or sig-list-i sig-list-o sig-list-io)
10659 ;; Don't sort them so a upper AUTOINST will match the main module
10660 (verilog-insert-definition sig-list-o "output" indent-pt v2k t)
10661 (verilog-insert-definition sig-list-io "inout" indent-pt v2k t)
10662 (verilog-insert-definition sig-list-i "input" indent-pt v2k t)
10663 (verilog-insert-definition sig-list-if "interface" indent-pt v2k t)
10664 (verilog-modi-cache-add-inputs modi sig-list-i)
10665 (verilog-modi-cache-add-outputs modi sig-list-o)
10666 (verilog-modi-cache-add-inouts modi sig-list-io)
10668 (when v2k (verilog-repair-close-comma)))))))
10670 (defun verilog-auto-inout-comp ()
10672 Take input/output/inout statements from the specified module and
10673 insert the inverse into the current module (inputs become outputs
10674 and vice-versa.) This is useful for making test and stimulus
10675 modules which need to have complementing I/O with another module.
10676 Any I/O which are already defined in this module will not be
10677 redefined. For the complement of this function, see
10678 `verilog-auto-inout-module'.
10680 Limitations:
10681 If placed inside the parenthesis of a module declaration, it creates
10682 Verilog 2001 style, else uses Verilog 1995 style.
10684 Concatenation and outputting partial busses is not supported.
10686 Module names must be resolvable to filenames. See `verilog-auto-inst'.
10688 Signals are not inserted in the same order as in the original module,
10689 though they will appear to be in the same order to a AUTOINST
10690 instantiating either module.
10692 An example:
10694 module ExampShell (/*AUTOARG*/);
10696 endmodule
10698 module ExampMain (i,o,io);
10699 input i;
10700 output o;
10701 inout io;
10702 endmodule
10706 module ExampShell (/*AUTOARG*/i,o,io);
10708 // Beginning of automatic in/out/inouts (from specific module)
10709 output i;
10710 inout io;
10711 input o;
10712 // End of automatics
10713 endmodule
10715 You may also provide an optional regular expression, in which case only
10716 signals matching the regular expression will be included. For example the
10717 same expansion will result from only extracting signals starting with i:
10720 (verilog-auto-inout-module t))
10722 (defun verilog-auto-insert-lisp ()
10724 The Lisp code provided is called, and the Lisp code calls
10725 `insert` to insert text into the current file beginning on the
10726 line after the AUTOINSERTLISP.
10728 See also AUTO_LISP, which takes a Lisp expression and evaluates
10729 it during `verilog-auto-inst' but does not insert any text.
10731 An example:
10733 module ExampInsertLisp;
10735 endmodule
10737 // For this example we declare the function in the
10738 // module's file itself. Often you'd define it instead
10739 // in a site-start.el or .emacs file.
10740 /*
10741 Local Variables:
10742 eval:
10743 (defun my-verilog-insert-hello (who)
10745 End:
10746 */
10749 expand the above into:
10751 // Beginning of automatic insert lisp
10753 // End of automatics
10755 You can also call an external program and insert the returned
10756 text:
10759 // Beginning of automatic insert lisp
10760 //hello
10761 // End of automatics"
10762 (save-excursion
10763 ;; Point is at end of /*AUTO...*/
10764 (let* ((indent-pt (current-indentation))
10765 (cmd-end-pt (save-excursion (search-backward ")")
10766 (forward-char)
10767 (point))) ;; Closing paren
10768 (cmd-beg-pt (save-excursion (goto-char cmd-end-pt)
10769 (backward-sexp 1)
10770 (point))) ;; Beginning paren
10771 (cmd (buffer-substring-no-properties cmd-beg-pt cmd-end-pt)))
10772 (forward-line 1)
10773 ;; Some commands don't move point (like insert-file) so we always
10774 ;; add the begin/end comments, then delete it if not needed
10777 (forward-line -1)
10778 (eval (read cmd))
10779 (forward-line -1)
10780 (setq verilog-scan-cache-tick nil) ;; Clear cache; inserted unknown text
10781 (verilog-delete-empty-auto-pair))))
10783 (defun verilog-auto-sense-sigs (moddecls presense-sigs)
10784 "Return list of signals for current AUTOSENSE block."
10785 (let* ((sigss (verilog-read-always-signals))
10786 (sig-list (verilog-signals-not-params
10787 (verilog-signals-not-in (verilog-alw-get-inputs sigss)
10788 (append (and (not verilog-auto-sense-include-inputs)
10789 (verilog-alw-get-outputs sigss))
10790 (verilog-alw-get-temps sigss)
10791 (verilog-decls-get-consts moddecls)
10792 (verilog-decls-get-gparams moddecls)
10793 presense-sigs)))))
10794 sig-list))
10796 (defun verilog-auto-sense ()
10798 Replace the always (/*AUTOSENSE*/) sensitivity list (/*AS*/ for short)
10799 with one automatically derived from all inputs declared in the always
10800 statement. Signals that are generated within the same always block are NOT
10801 placed into the sensitivity list (see `verilog-auto-sense-include-inputs').
10804 Limitations:
10805 Verilog does not allow memories (multidimensional arrays) in sensitivity
10806 lists. AUTOSENSE will thus exclude them, and add a /*memory or*/ comment.
10808 Constant signals:
10809 AUTOSENSE cannot always determine if a `define is a constant or a signal
10810 (it could be in a include file for example). If a `define or other signal
10811 is put into the AUTOSENSE list and is not desired, use the AUTO_CONSTANT
10812 declaration anywhere in the module (parenthesis are required):
10814 /* AUTO_CONSTANT ( `this_is_really_constant_dont_autosense_it ) */
10816 Better yet, use a parameter, which will be understood to be constant
10817 automatically.
10819 OOps!
10820 If AUTOSENSE makes a mistake, please report it. (First try putting
10821 a begin/end after your always!) As a workaround, if a signal that
10822 shouldn't be in the sensitivity list was, use the AUTO_CONSTANT above.
10823 If a signal should be in the sensitivity list wasn't, placing it before
10824 the /*AUTOSENSE*/ comment will prevent it from being deleted when the
10825 autos are updated (or added if it occurs there already).
10827 An example:
10829 always @ (/*AS*/) begin
10830 /* AUTO_CONSTANT (`constant) */
10831 outin = ina | inb | `constant;
10832 out = outin;
10833 end
10837 always @ (/*AS*/ina or inb) begin
10838 /* AUTO_CONSTANT (`constant) */
10839 outin = ina | inb | `constant;
10840 out = outin;
10841 end
10843 Note in Verilog 2001, you can often get the same result from the new @*
10844 operator. (This was added to the language in part due to AUTOSENSE!)
10846 always @* begin
10847 outin = ina | inb | `constant;
10848 out = outin;
10849 end"
10850 (save-excursion
10851 ;; Find beginning
10852 (let* ((start-pt (save-excursion
10853 (verilog-re-search-backward "(" nil t)
10854 (point)))
10855 (indent-pt (save-excursion
10856 (or (and (goto-char start-pt) (1+ (current-column)))
10857 (current-indentation))))
10858 (modi (verilog-modi-current))
10859 (moddecls (verilog-modi-get-decls modi))
10860 (sig-memories (verilog-signals-memory
10861 (append
10862 (verilog-decls-get-regs moddecls)
10863 (verilog-decls-get-wires moddecls))))
10864 sig-list not-first presense-sigs)
10865 ;; Read signals in always, eliminate outputs from sense list
10866 (setq presense-sigs (verilog-signals-from-signame
10867 (save-excursion
10868 (verilog-read-signals start-pt (point)))))
10869 (setq sig-list (verilog-auto-sense-sigs moddecls presense-sigs))
10870 (when sig-memories
10871 (let ((tlen (length sig-list)))
10872 (setq sig-list (verilog-signals-not-in sig-list sig-memories))
10873 (if (not (eq tlen (length sig-list))) (verilog-insert " /*memory or*/ "))))
10874 (if (and presense-sigs ;; Add a "or" if not "(.... or /*AUTOSENSE*/"
10875 (save-excursion (goto-char (point))
10876 (verilog-re-search-backward "[a-zA-Z0-9$_.%`]+" start-pt t)
10879 (verilog-re-search-backward "[a-zA-Z0-9$_.%`]+" start-pt t)
10882 (setq not-first t))
10883 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
10884 (while sig-list
10885 (cond ((> (+ 4 (current-column) (length (verilog-sig-name (car sig-list)))) fill-column) ;+4 for width of or
10887 (indent-to indent-pt)
10888 (if not-first (insert "or ")))
10889 (not-first (insert " or ")))
10890 (insert (verilog-sig-name (car sig-list)))
10891 (setq sig-list (cdr sig-list)
10892 not-first t)))))
10894 (defun verilog-auto-reset ()
10896 Replace the /*AUTORESET*/ comment with code to initialize all
10897 registers set elsewhere in the always block.
10899 Limitations:
10900 AUTORESET will not clear memories.
10902 AUTORESET uses <= if there are any <= assignments in the block,
10903 else it uses =.
10905 /*AUTORESET*/ presumes that any signals mentioned between the previous
10906 begin/case/if statement and the AUTORESET comment are being reset manually
10907 and should not be automatically reset. This includes omitting any signals
10908 used on the right hand side of assignments.
10910 By default, AUTORESET will include the width of the signal in the autos,
10911 this is a recent change. To control this behavior, see
10912 `verilog-auto-reset-widths'.
10914 AUTORESET ties signals to deasserted, which is presumed to be zero.
10915 Signals that match `verilog-active-low-regexp' will be deasserted by tieing
10916 them to a one.
10918 An example:
10920 always @(posedge clk or negedge reset_l) begin
10921 if (!reset_l) begin
10922 c <= 1;
10923 /*AUTORESET*/
10924 end
10925 else begin
10926 a <= in_a;
10927 b <= in_b;
10928 c <= in_c;
10929 end
10930 end
10934 always @(posedge core_clk or negedge reset_l) begin
10935 if (!reset_l) begin
10936 c <= 1;
10937 /*AUTORESET*/
10938 // Beginning of autoreset for uninitialized flops
10939 a <= 0;
10940 b <= 0;
10941 // End of automatics
10942 end
10943 else begin
10944 a <= in_a;
10945 b <= in_b;
10946 c <= in_c;
10947 end
10948 end"
10950 (interactive)
10951 (save-excursion
10952 ;; Find beginning
10953 (let* ((indent-pt (current-indentation))
10954 (modi (verilog-modi-current))
10955 (moddecls (verilog-modi-get-decls modi))
10956 (all-list (verilog-decls-get-signals moddecls))
10957 sigss sig-list prereset-sigs assignment-str)
10958 ;; Read signals in always, eliminate outputs from reset list
10959 (setq prereset-sigs (verilog-signals-from-signame
10960 (save-excursion
10961 (verilog-read-signals
10962 (save-excursion
10964 (point))
10965 (point)))))
10966 (save-excursion
10967 (verilog-re-search-backward "@" nil t)
10968 (setq sigss (verilog-read-always-signals)))
10969 (setq assignment-str (if (verilog-alw-get-uses-delayed sigss)
10970 (concat " <= " verilog-assignment-delay)
10971 " = "))
10972 (setq sig-list (verilog-signals-not-in (verilog-alw-get-outputs sigss)
10973 (append
10974 (verilog-alw-get-temps sigss)
10975 prereset-sigs)))
10976 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
10977 (when sig-list
10980 (indent-to indent-pt)
10981 (while sig-list
10982 (let ((sig (or (assoc (verilog-sig-name (car sig-list)) all-list) ;; As sig-list has no widths
10983 (car sig-list))))
10984 (insert (verilog-sig-name sig)
10985 assignment-str
10986 (verilog-sig-tieoff sig (not verilog-auto-reset-widths))
10988 (indent-to indent-pt)
10989 (setq sig-list (cdr sig-list))))
10990 (verilog-insert "// End of automatics")))))
10992 (defun verilog-auto-tieoff ()
10994 Replace the /*AUTOTIEOFF*/ comment with code to wire-tie all unused output
10995 signals to deasserted.
10997 /*AUTOTIEOFF*/ is used to make stub modules; modules that have the same
10998 input/output list as another module, but no internals. Specifically, it
10999 finds all outputs in the module, and if that input is not otherwise declared
11000 as a register or wire, creates a tieoff.
11002 AUTORESET ties signals to deasserted, which is presumed to be zero.
11003 Signals that match `verilog-active-low-regexp' will be deasserted by tieing
11004 them to a one.
11006 You can add signals you do not want included in AUTOTIEOFF with
11007 `verilog-auto-tieoff-ignore-regexp'.
11009 An example of making a stub for another module:
11011 module ExampStub (/*AUTOINST*/);
11013 /*AUTOTIEOFF*/
11014 // verilator lint_off UNUSED
11015 wire _unused_ok = &{1'b0,
11016 /*AUTOUNUSED*/
11017 1'b0};
11018 // verilator lint_on UNUSED
11019 endmodule
11023 module ExampStub (/*AUTOINST*/...);
11025 // Beginning of autotieoff
11026 output [2:0] foo;
11027 // End of automatics
11029 /*AUTOTIEOFF*/
11030 // Beginning of autotieoff
11031 wire [2:0] foo = 3'b0;
11032 // End of automatics
11033 ...
11034 endmodule"
11035 (interactive)
11036 (save-excursion
11037 ;; Find beginning
11038 (let* ((indent-pt (current-indentation))
11039 (modi (verilog-modi-current))
11040 (moddecls (verilog-modi-get-decls modi))
11041 (modsubdecls (verilog-modi-get-sub-decls modi))
11042 (sig-list (verilog-signals-not-in
11043 (verilog-decls-get-outputs moddecls)
11044 (append (verilog-decls-get-wires moddecls)
11045 (verilog-decls-get-regs moddecls)
11046 (verilog-decls-get-assigns moddecls)
11047 (verilog-decls-get-consts moddecls)
11048 (verilog-decls-get-gparams moddecls)
11049 (verilog-subdecls-get-interfaced modsubdecls)
11050 (verilog-subdecls-get-outputs modsubdecls)
11051 (verilog-subdecls-get-inouts modsubdecls)))))
11052 (setq sig-list (verilog-signals-not-matching-regexp
11053 sig-list verilog-auto-tieoff-ignore-regexp))
11054 (when sig-list
11055 (forward-line 1)
11056 (verilog-insert-indent "// Beginning of automatic tieoffs (for this module's unterminated outputs)\n")
11057 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
11058 (verilog-modi-cache-add-wires modi sig-list) ; Before we trash list
11059 (while sig-list
11060 (let ((sig (car sig-list)))
11061 (verilog-insert-one-definition sig "wire" indent-pt)
11062 (indent-to (max 48 (+ indent-pt 40)))
11063 (insert "= " (verilog-sig-tieoff sig)
11065 (setq sig-list (cdr sig-list))))
11068 (defun verilog-auto-unused ()
11070 Replace the /*AUTOUNUSED*/ comment with a comma separated list of all unused
11071 input and inout signals.
11073 /*AUTOUNUSED*/ is used to make stub modules; modules that have the same
11074 input/output list as another module, but no internals. Specifically, it
11075 finds all inputs and inouts in the module, and if that input is not otherwise
11076 used, adds it to a comma separated list.
11078 The comma separated list is intended to be used to create a _unused_ok
11080 signal is recommended as it will insure maximum forward compatibility, it
11081 also makes lint warnings easy to understand; ignore any unused warnings
11084 To reduce simulation time, the _unused_ok signal should be forced to a
11085 constant to prevent wiggling. The easiest thing to do is use a
11086 reduction-and with 1'b0 as shown.
11088 This way all unused signals are in one place, making it convenient to add
11089 your tool's specific pragmas around the assignment to disable any unused
11090 warnings.
11092 You can add signals you do not want included in AUTOUNUSED with
11093 `verilog-auto-unused-ignore-regexp'.
11095 An example of making a stub for another module:
11097 module ExampStub (/*AUTOINST*/);
11099 /*AUTOTIEOFF*/
11100 // verilator lint_off UNUSED
11101 wire _unused_ok = &{1'b0,
11102 /*AUTOUNUSED*/
11103 1'b0};
11104 // verilator lint_on UNUSED
11105 endmodule
11109 ...
11110 // verilator lint_off UNUSED
11111 wire _unused_ok = &{1'b0,
11112 /*AUTOUNUSED*/
11113 // Beginning of automatics
11114 unused_input_a,
11115 unused_input_b,
11116 unused_input_c,
11117 // End of automatics
11118 1'b0};
11119 // verilator lint_on UNUSED
11120 endmodule"
11121 (interactive)
11122 (save-excursion
11123 ;; Find beginning
11124 (let* ((indent-pt (progn (search-backward "/*") (current-column)))
11125 (modi (verilog-modi-current))
11126 (moddecls (verilog-modi-get-decls modi))
11127 (modsubdecls (verilog-modi-get-sub-decls modi))
11128 (sig-list (verilog-signals-not-in
11129 (append (verilog-decls-get-inputs moddecls)
11130 (verilog-decls-get-inouts moddecls))
11131 (append (verilog-subdecls-get-inputs modsubdecls)
11132 (verilog-subdecls-get-inouts modsubdecls)))))
11133 (setq sig-list (verilog-signals-not-matching-regexp
11134 sig-list verilog-auto-unused-ignore-regexp))
11135 (when sig-list
11136 (forward-line 1)
11138 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
11139 (while sig-list
11140 (let ((sig (car sig-list)))
11141 (indent-to indent-pt)
11143 (setq sig-list (cdr sig-list))))
11146 (defun verilog-enum-ascii (signm elim-regexp)
11147 "Convert an enum name SIGNM to an ascii string for insertion.
11148 Remove user provided prefix ELIM-REGEXP."
11149 (or elim-regexp (setq elim-regexp "_ DONT MATCH IT_"))
11150 (let ((case-fold-search t))
11151 ;; All upper becomes all lower for readability
11152 (downcase (verilog-string-replace-matches elim-regexp "" nil nil signm))))
11154 (defun verilog-auto-ascii-enum ()
11156 Create a register to contain the ASCII decode of a enumerated signal type.
11157 This will allow trace viewers to show the ASCII name of states.
11159 First, parameters are built into a enumeration using the synopsys enum
11160 comment. The comment must be between the keyword and the symbol.
11161 \(Annoying, but that's what Synopsys's dc_shell FSM reader requires.)
11163 Next, registers which that enum applies to are also tagged with the same
11164 enum. Synopsys also suggests labeling state vectors, but `verilog-mode'
11165 doesn't care.
11167 Finally, a AUTOASCIIENUM command is used.
11169 The first parameter is the name of the signal to be decoded.
11170 If and only if the first parameter width is 2^(number of states
11171 in enum) and does NOT match the width of the enum, the signal
11172 is assumed to be a one hot decode. Otherwise, it's a normal
11173 encoded state vector.
11175 The second parameter is the name to store the ASCII code into. For the
11176 signal foo, I suggest the name _foo__ascii, where the leading _ indicates
11177 a signal that is just for simulation, and the magic characters _ascii
11178 tell viewers like Dinotrace to display in ASCII format.
11180 The final optional parameter is a string which will be removed from the
11181 state names.
11183 An example:
11185 //== State enumeration
11186 parameter [2:0] // synopsys enum state_info
11187 SM_IDLE = 3'b000,
11188 SM_SEND = 3'b001,
11189 SM_WAIT1 = 3'b010;
11190 //== State variables
11191 reg [2:0] /* synopsys enum state_info */
11192 state_r; /* synopsys state_vector state_r */
11193 reg [2:0] /* synopsys enum state_info */
11194 state_e1;
11200 ... same front matter ...
11203 // Beginning of automatic ASCII enum decoding
11204 reg [39:0] state_ascii_r; // Decode of state_r
11205 always @(state_r) begin
11206 case ({state_r})
11211 endcase
11212 end
11213 // End of automatics"
11214 (save-excursion
11215 (let* ((params (verilog-read-auto-params 2 3))
11216 (undecode-name (nth 0 params))
11217 (ascii-name (nth 1 params))
11218 (elim-regexp (nth 2 params))
11219 ;;
11220 (indent-pt (current-indentation))
11221 (modi (verilog-modi-current))
11222 (moddecls (verilog-modi-get-decls modi))
11223 ;;
11224 (sig-list-consts (append (verilog-decls-get-consts moddecls)
11225 (verilog-decls-get-gparams moddecls)))
11226 (sig-list-all (append (verilog-decls-get-regs moddecls)
11227 (verilog-decls-get-outputs moddecls)
11228 (verilog-decls-get-inouts moddecls)
11229 (verilog-decls-get-inputs moddecls)
11230 (verilog-decls-get-wires moddecls)))
11231 ;;
11232 (undecode-sig (or (assoc undecode-name sig-list-all)
11233 (error "%s: Signal %s not found in design" (verilog-point-text) undecode-name)))
11234 (undecode-enum (or (verilog-sig-enum undecode-sig)
11235 (error "%s: Signal %s does not have a enum tag" (verilog-point-text) undecode-name)))
11236 ;;
11237 (enum-sigs (verilog-signals-not-in
11238 (or (verilog-signals-matching-enum sig-list-consts undecode-enum)
11239 (error "%s: No state definitions for %s" (verilog-point-text) undecode-enum))
11240 nil))
11241 ;;
11242 (one-hot (and ;; width(enum) != width(sig)
11243 (or (not (verilog-sig-bits (car enum-sigs)))
11244 (not (equal (verilog-sig-width (car enum-sigs))
11245 (verilog-sig-width undecode-sig))))
11246 ;; count(enums) == width(sig)
11247 (equal (number-to-string (length enum-sigs))
11248 (verilog-sig-width undecode-sig))))
11249 (enum-chars 0)
11250 (ascii-chars 0))
11251 ;;
11252 ;; Find number of ascii chars needed
11253 (let ((tmp-sigs enum-sigs))
11254 (while tmp-sigs
11255 (setq enum-chars (max enum-chars (length (verilog-sig-name (car tmp-sigs))))
11256 ascii-chars (max ascii-chars (length (verilog-enum-ascii
11257 (verilog-sig-name (car tmp-sigs))
11258 elim-regexp)))
11259 tmp-sigs (cdr tmp-sigs))))
11260 ;;
11261 (forward-line 1)
11263 (let ((decode-sig-list (list (list ascii-name (format "[%d:0]" (- (* ascii-chars 8) 1))
11264 (concat "Decode of " undecode-name) nil nil))))
11265 (verilog-insert-definition decode-sig-list "reg" indent-pt nil)
11266 (verilog-modi-cache-add-regs modi decode-sig-list))
11267 ;;
11269 (setq indent-pt (+ indent-pt verilog-indent-level))
11270 (indent-to indent-pt)
11272 (setq indent-pt (+ indent-pt verilog-case-indent))
11273 ;;
11274 (let ((tmp-sigs enum-sigs)
11276 (+ (if one-hot 9 1) (max 8 enum-chars))
11277 ascii-name ascii-chars))
11278 (errname (substring "%Error" 0 (min 6 ascii-chars))))
11279 (while tmp-sigs
11280 (verilog-insert-indent
11281 (concat
11282 (format chrfmt
11283 (concat (if one-hot "(")
11284 (if one-hot (verilog-sig-width undecode-sig))
11285 ;; We use a shift instead of var[index]
11286 ;; so that a non-one hot value will show as error.
11287 (if one-hot "'b1<<")
11288 (verilog-sig-name (car tmp-sigs))
11289 (if one-hot ")") ":")
11290 (verilog-enum-ascii (verilog-sig-name (car tmp-sigs))
11291 elim-regexp))))
11292 (setq tmp-sigs (cdr tmp-sigs)))
11293 (verilog-insert-indent (format chrfmt "default:" errname)))
11294 ;;
11295 (setq indent-pt (- indent-pt verilog-case-indent))
11297 (setq indent-pt (- indent-pt verilog-indent-level))
11301 (defun verilog-auto-templated-rel ()
11302 "Replace Templated relative line numbers with absolute line numbers.
11303 Internal use only. This hacks around the line numbers in AUTOINST Templates
11304 being different from the final output's line numbering."
11305 (let ((templateno 0) (template-line (list 0)) (buf-line 1))
11306 ;; Find line number each template is on
11307 ;; Count lines as we go, as otherwise it's O(n^2) to use count-lines
11308 (goto-char (point-min))
11309 (while (not (eobp))
11310 (when (looking-at ".*AUTO_TEMPLATE")
11311 (setq templateno (1+ templateno))
11312 (setq template-line (cons buf-line template-line)))
11313 (setq buf-line (1+ buf-line))
11314 (forward-line 1))
11315 (setq template-line (nreverse template-line))
11316 ;; Replace T# L# with absolute line number
11317 (goto-char (point-min))
11319 (replace-match
11320 (concat " Templated "
11321 (int-to-string (+ (nth (string-to-number (match-string 1))
11322 template-line)
11323 (string-to-number (match-string 2)))))
11324 t t))))
11326 \f
11327 ;;
11328 ;; Auto top level
11329 ;;
11331 (defun verilog-auto (&optional inject) ; Use verilog-inject-auto instead of passing a arg
11332 "Expand AUTO statements.
11333 Look for any /*AUTO...*/ commands in the code, as used in
11334 instantiations or argument headers. Update the list of signals
11335 following the /*AUTO...*/ command.
11343 The hooks `verilog-before-auto-hook' and `verilog-auto-hook' are
11344 called before and after this function, respectively.
11346 For example:
11347 module ModuleName (/*AUTOARG*/);
11348 /*AUTOINPUT*/
11349 /*AUTOOUTPUT*/
11350 /*AUTOWIRE*/
11351 /*AUTOREG*/
11352 InstMod instName #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);
11354 You can also update the AUTOs from the shell using:
11355 emacs --batch <filenames.v> -f verilog-batch-auto
11356 Or fix indentation with:
11357 emacs --batch <filenames.v> -f verilog-batch-indent
11358 Likewise, you can delete or inject AUTOs with:
11359 emacs --batch <filenames.v> -f verilog-batch-delete-auto
11360 emacs --batch <filenames.v> -f verilog-batch-inject-auto
11363 `verilog-auto-arg' for AUTOARG module instantiations
11364 `verilog-auto-ascii-enum' for AUTOASCIIENUM enumeration decoding
11365 `verilog-auto-inout-comp' for AUTOINOUTCOMP copy complemented i/o
11366 `verilog-auto-inout-module' for AUTOINOUTMODULE copying i/o from elsewhere
11367 `verilog-auto-inout' for AUTOINOUT making hierarchy inouts
11368 `verilog-auto-input' for AUTOINPUT making hierarchy inputs
11369 `verilog-auto-insert-lisp' for AUTOINSERTLISP insert code from lisp function
11370 `verilog-auto-inst' for AUTOINST instantiation pins
11371 `verilog-auto-star' for AUTOINST .* SystemVerilog pins
11372 `verilog-auto-inst-param' for AUTOINSTPARAM instantiation params
11373 `verilog-auto-output' for AUTOOUTPUT making hierarchy outputs
11374 `verilog-auto-output-every' for AUTOOUTPUTEVERY making all outputs
11375 `verilog-auto-reg' for AUTOREG registers
11376 `verilog-auto-reg-input' for AUTOREGINPUT instantiation registers
11377 `verilog-auto-reset' for AUTORESET flop resets
11378 `verilog-auto-sense' for AUTOSENSE always sensitivity lists
11379 `verilog-auto-tieoff' for AUTOTIEOFF output tieoffs
11380 `verilog-auto-unused' for AUTOUNUSED unused inputs/inouts
11381 `verilog-auto-wire' for AUTOWIRE instantiation wires
11383 `verilog-read-defines' for reading `define values
11384 `verilog-read-includes' for reading `includes
11386 If you have bugs with these autos, please file an issue at
11387 URL `http://www.veripool.org/verilog-mode' or contact the AUTOAUTHOR
11388 Wilson Snyder (wsnyder@wsnyder.org)."
11389 (interactive)
11390 (unless noninteractive (message "Updating AUTOs..."))
11391 (if (fboundp 'dinotrace-unannotate-all)
11392 (dinotrace-unannotate-all))
11393 (let ((oldbuf (if (not (buffer-modified-p))
11394 (buffer-string)))
11395 ;; Before version 20, match-string with font-lock returns a
11396 ;; vector that is not equal to the string. IE if on "input"
11397 ;; nil==(equal "input" (progn (looking-at "input") (match-string 0)))
11398 (fontlocked (when (and (boundp 'font-lock-mode)
11399 font-lock-mode)
11400 (font-lock-mode 0)
11401 t))
11402 ;; Cache directories; we don't write new files, so can't change
11403 (verilog-dir-cache-preserving t)
11404 ;; Cache current module
11405 (verilog-modi-cache-current-enable t)
11406 (verilog-modi-cache-current-max (point-min)) ; IE it's invalid
11407 verilog-modi-cache-current)
11408 (unwind-protect
11409 ;; Disable change hooks for speed
11410 ;; This let can't be part of above let; must restore
11411 ;; after-change-functions before font-lock resumes
11412 (verilog-save-no-change-functions
11413 (verilog-save-scan-cache
11414 (save-excursion
11415 ;; If we're not in verilog-mode, change syntax table so parsing works right
11416 (unless (eq major-mode `verilog-mode) (verilog-mode))
11417 ;; Allow user to customize
11418 (run-hooks 'verilog-before-auto-hook)
11419 ;; Try to save the user from needing to revert-file to reread file local-variables
11420 (verilog-auto-reeval-locals)
11421 (verilog-read-auto-lisp-present)
11422 (verilog-read-auto-lisp (point-min) (point-max))
11423 (verilog-getopt-flags)
11424 ;; From here on out, we can cache anything we read from disk
11425 (verilog-preserve-dir-cache
11426 ;; These two may seem obvious to do always, but on large includes it can be way too slow
11427 (when verilog-auto-read-includes
11428 (verilog-read-includes)
11429 (verilog-read-defines nil nil t))
11430 ;; This particular ordering is important
11431 ;; INST: Lower modules correct, no internal dependencies, FIRST
11432 (verilog-preserve-modi-cache
11433 ;; Clear existing autos else we'll be screwed by existing ones
11434 (verilog-delete-auto)
11435 ;; Injection if appropriate
11436 (when inject
11437 (verilog-inject-inst)
11438 (verilog-inject-sense)
11439 (verilog-inject-arg))
11440 ;;
11441 ;; Do user inserts first, so their code can insert AUTOs
11442 ;; We may provide a AUTOINSERTLISPLAST if another cleanup pass is needed
11444 'verilog-auto-insert-lisp)
11445 ;; Expand instances before need the signals the instances input/output
11449 ;; Doesn't matter when done, but combine it with a common changer
11452 ;; Must be done before autoin/out as creates a reg
11454 ;;
11455 ;; first in/outs from other files
11458 ;; next in/outs which need previous sucked inputs first
11460 '(lambda () (verilog-auto-output t)))
11463 '(lambda () (verilog-auto-input t)))
11466 '(lambda () (verilog-auto-inout t)))
11468 ;; Then tie off those in/outs
11470 ;; Wires/regs must be after inputs/outputs
11474 ;; outputevery needs AUTOOUTPUTs done first
11476 ;; After we've created all new variables
11478 ;; Must be after all inputs outputs are generated
11480 ;; Fix line numbers (comments only)
11481 (when verilog-auto-inst-template-numbers
11482 (verilog-auto-templated-rel))))
11483 ;;
11484 (run-hooks 'verilog-auto-hook)
11485 ;;
11486 (set (make-local-variable 'verilog-auto-update-tick) (buffer-chars-modified-tick))
11487 ;;
11488 ;; If end result is same as when started, clear modified flag
11489 (cond ((and oldbuf (equal oldbuf (buffer-string)))
11490 (set-buffer-modified-p nil)
11491 (unless noninteractive (message "Updating AUTOs...done (no changes)")))
11492 (t (unless noninteractive (message "Updating AUTOs...done"))))
11493 ;; End of after-change protection
11494 )))
11495 ;; Unwind forms
11496 (progn
11497 ;; Restore font-lock
11498 (when fontlocked (font-lock-mode t))))))
11499 \f
11501 ;;
11502 ;; Skeleton based code insertion
11503 ;;
11504 (defvar verilog-template-map
11505 (let ((map (make-sparse-keymap)))
11506 (define-key map "a" 'verilog-sk-always)
11507 (define-key map "b" 'verilog-sk-begin)
11508 (define-key map "c" 'verilog-sk-case)
11509 (define-key map "f" 'verilog-sk-for)
11510 (define-key map "g" 'verilog-sk-generate)
11511 (define-key map "h" 'verilog-sk-header)
11512 (define-key map "i" 'verilog-sk-initial)
11513 (define-key map "j" 'verilog-sk-fork)
11514 (define-key map "m" 'verilog-sk-module)
11515 (define-key map "p" 'verilog-sk-primitive)
11516 (define-key map "r" 'verilog-sk-repeat)
11517 (define-key map "s" 'verilog-sk-specify)
11518 (define-key map "t" 'verilog-sk-task)
11519 (define-key map "w" 'verilog-sk-while)
11520 (define-key map "x" 'verilog-sk-casex)
11521 (define-key map "z" 'verilog-sk-casez)
11522 (define-key map "?" 'verilog-sk-if)
11523 (define-key map ":" 'verilog-sk-else-if)
11524 (define-key map "/" 'verilog-sk-comment)
11525 (define-key map "A" 'verilog-sk-assign)
11526 (define-key map "F" 'verilog-sk-function)
11527 (define-key map "I" 'verilog-sk-input)
11528 (define-key map "O" 'verilog-sk-output)
11529 (define-key map "S" 'verilog-sk-state-machine)
11530 (define-key map "=" 'verilog-sk-inout)
11531 (define-key map "W" 'verilog-sk-wire)
11532 (define-key map "R" 'verilog-sk-reg)
11533 (define-key map "D" 'verilog-sk-define-signal)
11534 map)
11535 "Keymap used in Verilog mode for smart template operations.")
11538 ;;
11539 ;; Place the templates into Verilog Mode. They may be inserted under any key.
11540 ;; C-c C-t will be the default. If you use templates a lot, you
11541 ;; may want to consider moving the binding to another key in your .emacs
11542 ;; file.
11543 ;;
11544 ;(define-key verilog-mode-map "\C-ct" verilog-template-map)
11545 (define-key verilog-mode-map "\C-c\C-t" verilog-template-map)
11547 ;;; ---- statement skeletons ------------------------------------------
11549 (define-skeleton verilog-sk-prompt-condition
11550 "Prompt for the loop condition."
11551 "[condition]: " str )
11553 (define-skeleton verilog-sk-prompt-init
11554 "Prompt for the loop init statement."
11555 "[initial statement]: " str )
11557 (define-skeleton verilog-sk-prompt-inc
11558 "Prompt for the loop increment statement."
11559 "[increment statement]: " str )
11561 (define-skeleton verilog-sk-prompt-name
11562 "Prompt for the name of something."
11563 "[name]: " str)
11565 (define-skeleton verilog-sk-prompt-clock
11566 "Prompt for the name of something."
11567 "name and edge of clock(s): " str)
11569 (defvar verilog-sk-reset nil)
11570 (defun verilog-sk-prompt-reset ()
11571 "Prompt for the name of a state machine reset."
11572 (setq verilog-sk-reset (read-string "name of reset: " "rst")))
11575 (define-skeleton verilog-sk-prompt-state-selector
11576 "Prompt for the name of a state machine selector."
11577 "name of selector (eg {a,b,c,d}): " str )
11579 (define-skeleton verilog-sk-prompt-output
11580 "Prompt for the name of something."
11581 "output: " str)
11583 (define-skeleton verilog-sk-prompt-msb
11584 "Prompt for least significant bit specification."
11585 "msb:" str & ?: & '(verilog-sk-prompt-lsb) | -1 )
11587 (define-skeleton verilog-sk-prompt-lsb
11588 "Prompt for least significant bit specification."
11589 "lsb:" str )
11591 (defvar verilog-sk-p nil)
11592 (define-skeleton verilog-sk-prompt-width
11593 "Prompt for a width specification."
11594 ()
11595 (progn
11596 (setq verilog-sk-p (point))
11597 (verilog-sk-prompt-msb)
11598 (if (> (point) verilog-sk-p) "] " " ")))
11600 (defun verilog-sk-header ()
11601 "Insert a descriptive header at the top of the file.
11602 See also `verilog-header' for an alternative format."
11603 (interactive "*")
11604 (save-excursion
11605 (goto-char (point-min))
11606 (verilog-sk-header-tmpl)))
11608 (define-skeleton verilog-sk-header-tmpl
11609 "Insert a comment block containing the module title, author, etc."
11610 "[Description]: "
11611 "// -*- Mode: Verilog -*-"
11622 (define-skeleton verilog-sk-module
11623 "Insert a module definition."
11624 ()
11627 > (- verilog-indent-level-behavioral) "endmodule" (progn (electric-verilog-terminate-line) nil))
11629 (define-skeleton verilog-sk-primitive
11630 "Insert a task definition."
11631 ()
11632 > "primitive " '(verilog-sk-prompt-name) " ( " '(verilog-sk-prompt-output) ("input:" ", " str ) " );"\n
11634 > (- verilog-indent-level-behavioral) "endprimitive" (progn (electric-verilog-terminate-line) nil))
11636 (define-skeleton verilog-sk-task
11637 "Insert a task definition."
11638 ()
11644 > (- verilog-indent-level-behavioral) "endtask" (progn (electric-verilog-terminate-line) nil))
11646 (define-skeleton verilog-sk-function
11647 "Insert a function definition."
11648 ()
11654 > (- verilog-indent-level-behavioral) "endfunction" (progn (electric-verilog-terminate-line) nil))
11656 (define-skeleton verilog-sk-always
11657 "Insert always block. Uses the minibuffer to prompt
11658 for sensitivity list."
11659 ()
11663 )
11665 (define-skeleton verilog-sk-initial
11666 "Insert an initial block."
11667 ()
11672 (define-skeleton verilog-sk-specify
11673 "Insert specify block. "
11674 ()
11679 (define-skeleton verilog-sk-generate
11680 "Insert generate block. "
11681 ()
11686 (define-skeleton verilog-sk-begin
11687 "Insert begin end block. Uses the minibuffer to prompt for name."
11688 ()
11691 > (- verilog-indent-level-behavioral) "end"
11692 )
11694 (define-skeleton verilog-sk-fork
11695 "Insert a fork join block."
11696 ()
11705 > )
11708 (define-skeleton verilog-sk-case
11709 "Build skeleton case statement, prompting for the selector expression,
11710 and the case items."
11711 "[selector expression]: "
11713 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
11714 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
11716 (define-skeleton verilog-sk-casex
11717 "Build skeleton casex statement, prompting for the selector expression,
11718 and the case items."
11719 "[selector expression]: "
11721 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
11722 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
11724 (define-skeleton verilog-sk-casez
11725 "Build skeleton casez statement, prompting for the selector expression,
11726 and the case items."
11727 "[selector expression]: "
11729 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
11730 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
11732 (define-skeleton verilog-sk-if
11733 "Insert a skeleton if statement."
11738 (define-skeleton verilog-sk-else-if
11739 "Insert a skeleton else if statement."
11740 > (verilog-indent-line) "else if ("
11741 (progn (setq verilog-sk-p (point)) nil) '(verilog-sk-prompt-condition) (if (> (point) verilog-sk-p) ") " -1 ) & " begin" \n
11743 > "end" (progn (electric-verilog-terminate-line) nil))
11745 (define-skeleton verilog-sk-datadef
11746 "Common routine to get data definition."
11747 ()
11750 (define-skeleton verilog-sk-input
11751 "Insert an input definition."
11752 ()
11753 > "input [" '(verilog-sk-datadef))
11755 (define-skeleton verilog-sk-output
11756 "Insert an output definition."
11757 ()
11758 > "output [" '(verilog-sk-datadef))
11760 (define-skeleton verilog-sk-inout
11761 "Insert an inout definition."
11762 ()
11763 > "inout [" '(verilog-sk-datadef))
11765 (defvar verilog-sk-signal nil)
11766 (define-skeleton verilog-sk-def-reg
11767 "Insert a reg definition."
11768 ()
11769 > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-signal ";" \n (verilog-pretty-declarations) )
11771 (defun verilog-sk-define-signal ()
11772 "Insert a definition of signal under point at top of module."
11773 (interactive "*")
11774 (let* ((sig-re "[a-zA-Z0-9_]*")
11775 (v1 (buffer-substring
11776 (save-excursion
11777 (skip-chars-backward sig-re)
11778 (point))
11779 (save-excursion
11780 (skip-chars-forward sig-re)
11781 (point)))))
11782 (if (not (member v1 verilog-keywords))
11783 (save-excursion
11784 (setq verilog-sk-signal v1)
11785 (verilog-beg-of-defun)
11786 (verilog-end-of-statement)
11787 (verilog-forward-syntactic-ws)
11788 (verilog-sk-def-reg)
11789 (message "signal at point is %s" v1))
11790 (message "object at point (%s) is a keyword" v1))))
11792 (define-skeleton verilog-sk-wire
11793 "Insert a wire definition."
11794 ()
11795 > "wire [" '(verilog-sk-datadef))
11797 (define-skeleton verilog-sk-reg
11798 "Insert a reg definition."
11799 ()
11800 > "reg [" '(verilog-sk-datadef))
11802 (define-skeleton verilog-sk-assign
11803 "Insert a skeleton assign statement."
11804 ()
11807 (define-skeleton verilog-sk-while
11808 "Insert a skeleton while loop statement."
11809 ()
11812 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
11814 (define-skeleton verilog-sk-repeat
11815 "Insert a skeleton repeat loop statement."
11816 ()
11819 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
11821 (define-skeleton verilog-sk-for
11822 "Insert a skeleton while loop statement."
11823 ()
11824 > "for ("
11825 '(verilog-sk-prompt-init) "; "
11826 '(verilog-sk-prompt-condition) "; "
11827 '(verilog-sk-prompt-inc)
11830 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
11832 (define-skeleton verilog-sk-comment
11833 "Inserts three comment lines, making a display comment."
11834 ()
11837 > "*/")
11839 (define-skeleton verilog-sk-state-machine
11840 "Insert a state machine definition."
11841 "Name of state variable: "
11842 '(setq input "state")
11844 '(setq verilog-sk-state str)
11846 '(setq input nil)
11849 > "always @ ( " (read-string "clock:" "posedge clk") " or " (verilog-sk-prompt-reset) " ) begin" \n
11852 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil)
11857 > ("case selector: " str ": begin" \n > "next_" verilog-sk-state " = " _ ";" \n > (- verilog-indent-level-behavioral) "end" \n )
11858 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil)
11859 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil))
11860 \f
11862 ;;
11863 ;; Include file loading with mouse/return event
11864 ;;
11865 ;; idea & first impl.: M. Rouat (eldo-mode.el)
11866 ;; second (emacs/xemacs) impl.: G. Van der Plas (spice-mode.el)
11868 (if (featurep 'xemacs)
11869 (require 'overlay))
11871 (defconst verilog-include-file-regexp
11873 "Regexp that matches the include file.")
11875 (defvar verilog-mode-mouse-map
11876 (let ((map (make-sparse-keymap))) ; as described in info pages, make a map
11877 (set-keymap-parent map verilog-mode-map)
11878 ;; mouse button bindings
11880 (if (featurep 'xemacs)
11881 (define-key map 'button2 'verilog-load-file-at-mouse);ffap-at-mouse ?
11882 (define-key map [mouse-2] 'verilog-load-file-at-mouse))
11883 (if (featurep 'xemacs)
11884 (define-key map 'Sh-button2 'mouse-yank) ; you wanna paste don't you ?
11885 (define-key map [S-mouse-2] 'mouse-yank-at-click))
11886 map)
11887 "Map containing mouse bindings for `verilog-mode'.")
11890 (defun verilog-highlight-region (beg end old-len)
11891 "Colorize included files and modules in the (changed?) region.
11892 Clicking on the middle-mouse button loads them in a buffer (as in dired)."
11893 (when (or verilog-highlight-includes
11894 verilog-highlight-modules)
11895 (save-excursion
11896 (save-match-data ;; A query-replace may call this function - do not disturb
11897 (verilog-save-buffer-state
11898 (verilog-save-scan-cache
11899 (let (end-point)
11900 (goto-char end)
11901 (setq end-point (verilog-get-end-of-line))
11902 (goto-char beg)
11903 (beginning-of-line) ; scan entire line
11904 ;; delete overlays existing on this line
11905 (let ((overlays (overlays-in (point) end-point)))
11906 (while overlays
11907 (if (and
11908 (overlay-get (car overlays) 'detachable)
11909 (or (overlay-get (car overlays) 'verilog-include-file)
11910 (overlay-get (car overlays) 'verilog-inst-module)))
11911 (delete-overlay (car overlays)))
11912 (setq overlays (cdr overlays))))
11913 ;;
11914 ;; make new include overlays
11915 (when verilog-highlight-includes
11916 (while (search-forward-regexp verilog-include-file-regexp end-point t)
11917 (goto-char (match-beginning 1))
11918 (let ((ov (make-overlay (match-beginning 1) (match-end 1))))
11919 (overlay-put ov 'start-closed 't)
11920 (overlay-put ov 'end-closed 't)
11921 (overlay-put ov 'evaporate 't)
11922 (overlay-put ov 'verilog-include-file 't)
11923 (overlay-put ov 'mouse-face 'highlight)
11924 (overlay-put ov 'local-map verilog-mode-mouse-map))))
11925 ;;
11926 ;; make new module overlays
11927 (goto-char beg)
11928 ;; This scanner is syntax-fragile, so don't get bent
11929 (when verilog-highlight-modules
11930 (condition-case nil
11932 (save-excursion
11933 (goto-char (match-beginning 0))
11934 (unless (verilog-inside-comment-p)
11935 (verilog-read-inst-module-matcher) ;; sets match 0
11936 (let* ((ov (make-overlay (match-beginning 0) (match-end 0))))
11937 (overlay-put ov 'start-closed 't)
11938 (overlay-put ov 'end-closed 't)
11939 (overlay-put ov 'evaporate 't)
11940 (overlay-put ov 'verilog-inst-module 't)
11941 (overlay-put ov 'mouse-face 'highlight)
11942 (overlay-put ov 'local-map verilog-mode-mouse-map)))))
11943 (error nil)))
11944 ;;
11945 ;; Future highlights:
11946 ;; variables - make an Occur buffer of where referenced
11947 ;; pins - make an Occur buffer of the sig in the declaration module
11948 )))))))
11950 (defun verilog-highlight-buffer ()
11951 "Colorize included files and modules across the whole buffer."
11952 ;; Invoked via verilog-mode calling font-lock then `font-lock-mode-hook'
11953 (interactive)
11954 ;; delete and remake overlays
11955 (verilog-highlight-region (point-min) (point-max) nil))
11957 ;; Deprecated, but was interactive, so we'll keep it around
11958 (defalias 'verilog-colorize-include-files-buffer 'verilog-highlight-buffer)
11960 ;; ffap-at-mouse isn't useful for Verilog mode. It uses library paths.
11961 ;; so define this function to do more or less the same as ffap-at-mouse
11962 ;; but first resolve filename...
11963 (defun verilog-load-file-at-mouse (event)
11964 "Load file under button 2 click's EVENT.
11965 Files are checked based on `verilog-library-flags'."
11966 (interactive "@e")
11967 (save-excursion ;; implement a Verilog specific ffap-at-mouse
11968 (mouse-set-point event)
11969 (verilog-load-file-at-point t)))
11971 ;; ffap isn't useable for Verilog mode. It uses library paths.
11972 ;; so define this function to do more or less the same as ffap
11973 ;; but first resolve filename...
11974 (defun verilog-load-file-at-point (&optional warn)
11975 "Load file under point.
11976 If WARN, throw warning if not found.
11977 Files are checked based on `verilog-library-flags'."
11978 (interactive)
11979 (save-excursion ;; implement a Verilog specific ffap
11980 (let ((overlays (overlays-in (point) (point)))
11981 hit)
11982 (while (and overlays (not hit))
11983 (when (overlay-get (car overlays) 'verilog-inst-module)
11984 (verilog-goto-defun-file (buffer-substring
11985 (overlay-start (car overlays))
11986 (overlay-end (car overlays))))
11987 (setq hit t))
11988 (setq overlays (cdr overlays)))
11989 ;; Include?
11990 (beginning-of-line)
11991 (when (and (not hit)
11992 (looking-at verilog-include-file-regexp))
11993 (if (and (car (verilog-library-filenames
11994 (match-string 1) (buffer-file-name)))
11995 (file-readable-p (car (verilog-library-filenames
11996 (match-string 1) (buffer-file-name)))))
11997 (find-file (car (verilog-library-filenames
11998 (match-string 1) (buffer-file-name))))
11999 (when warn
12000 (message
12001 "File '%s' isn't readable, use shift-mouse2 to paste in this field"
12002 (match-string 1))))))))
12004 ;;
12005 ;; Bug reporting
12006 ;;
12008 (defun verilog-faq ()
12009 "Tell the user their current version, and where to get the FAQ etc."
12010 (interactive)
12011 (with-output-to-temp-buffer "*verilog-mode help*"
12021 (autoload 'reporter-submit-bug-report "reporter")
12022 (defvar reporter-prompt-for-summary-p)
12024 (defun verilog-submit-bug-report ()
12025 "Submit via mail a bug report on verilog-mode.el."
12026 (interactive)
12027 (let ((reporter-prompt-for-summary-p t))
12028 (reporter-submit-bug-report
12029 "mac@verilog.com, wsnyder@wsnyder.org"
12030 (concat "verilog-mode v" verilog-mode-version)
12031 '(
12032 verilog-active-low-regexp
12033 verilog-align-ifelse
12034 verilog-assignment-delay
12035 verilog-auto-arg-sort
12036 verilog-auto-endcomments
12037 verilog-auto-hook
12038 verilog-auto-ignore-concat
12039 verilog-auto-indent-on-newline
12040 verilog-auto-inout-ignore-regexp
12041 verilog-auto-input-ignore-regexp
12042 verilog-auto-inst-column
12043 verilog-auto-inst-dot-name
12044 verilog-auto-inst-param-value
12045 verilog-auto-inst-template-numbers
12046 verilog-auto-inst-vector
12047 verilog-auto-lineup
12048 verilog-auto-newline
12049 verilog-auto-output-ignore-regexp
12050 verilog-auto-read-includes
12051 verilog-auto-reset-widths
12052 verilog-auto-save-policy
12053 verilog-auto-sense-defines-constant
12054 verilog-auto-sense-include-inputs
12055 verilog-auto-star-expand
12056 verilog-auto-star-save
12057 verilog-auto-unused-ignore-regexp
12058 verilog-before-auto-hook
12059 verilog-before-delete-auto-hook
12060 verilog-before-getopt-flags-hook
12061 verilog-case-indent
12062 verilog-cexp-indent
12063 verilog-compiler
12064 verilog-coverage
12065 verilog-delete-auto-hook
12066 verilog-getopt-flags-hook
12067 verilog-highlight-grouping-keywords
12068 verilog-highlight-p1800-keywords
12069 verilog-highlight-translate-off
12070 verilog-indent-begin-after-if
12071 verilog-indent-declaration-macros
12072 verilog-indent-level
12073 verilog-indent-level-behavioral
12074 verilog-indent-level-declaration
12075 verilog-indent-level-directive
12076 verilog-indent-level-module
12077 verilog-indent-lists
12078 verilog-library-directories
12079 verilog-library-extensions
12080 verilog-library-files
12081 verilog-library-flags
12082 verilog-linter
12083 verilog-minimum-comment-distance
12084 verilog-mode-hook
12085 verilog-preprocessor
12086 verilog-simulator
12087 verilog-tab-always-indent
12088 verilog-tab-to-comment
12089 verilog-typedef-regexp
12090 )
12091 nil nil
12092 (concat "Hi Mac,
12094 I want to report a bug.
12096 Before I go further, I want to say that Verilog mode has changed my life.
12097 I save so much time, my files are colored nicely, my co workers respect
12098 my coding ability... until now. I'd really appreciate anything you
12099 could do to help me out with this minor deficiency in the product.
12101 I've taken a look at the Verilog-Mode FAQ at
12102 http://www.veripool.org/verilog-mode-faq.html.
12104 And, I've considered filing the bug on the issue tracker at
12105 http://www.veripool.org/verilog-mode-bugs
12106 since I realize that public bugs are easier for you to track,
12107 and for others to search, but would prefer to email.
12109 So, to reproduce the bug, start a fresh Emacs via " invocation-name "
12110 -no-init-file -no-site-file'. In a new buffer, in Verilog mode, type
12111 the code included below.
12113 Given those lines, I expected [[Fill in here]] to happen;
12114 but instead, [[Fill in here]] happens!.
12116 == The code: =="))))
12118 (provide 'verilog-mode)
12120 ;; Local Variables:
12121 ;; checkdoc-permit-comma-termination-flag:t
12122 ;; checkdoc-force-docstrings-flag:nil
12123 ;; End:
12125 ;; arch-tag: 87923725-57b3-41b5-9494-be21118c6a6f
12126 ;;; verilog-mode.el ends here